* [PATCH RESEND v4 14/37] mtd: st_spi_fsm: Add device-tree binding documentation
From: Lee Jones @ 2014-01-23 10:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
Cc: devicetree at vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
Documentation/devicetree/bindings/mtd/st-fsm.txt | 26 ++++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/st-fsm.txt
diff --git a/Documentation/devicetree/bindings/mtd/st-fsm.txt b/Documentation/devicetree/bindings/mtd/st-fsm.txt
new file mode 100644
index 0000000..c248939
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/st-fsm.txt
@@ -0,0 +1,26 @@
+* ST-Microelectronics SPI FSM Serial (NOR) Flash Controller
+
+Required properties:
+ - compatible : Should be "st,spi-fsm"
+ - reg : Contains register's location and length.
+ - reg-names : Should contain the reg names "spi-fsm"
+ - interrupts : The interrupt number
+ - pinctrl-0 : Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
+
+Optional properties:
+ - st,syscfg : Phandle to boot-device system configuration registers
+ - st,boot-device-reg : Address of the aforementioned boot-device register(s)
+ - st,boot-device-spi : Expected boot-device value if booted via this device
+
+Example:
+ spifsm: spifsm at fe902000{
+ compatible = "st,spi-fsm";
+ reg = <0xfe902000 0x1000>;
+ reg-names = "spi-fsm";
+ pinctrl-0 = <&pinctrl_fsm>;
+ st,syscfg = <&syscfg_rear>;
+ st,boot-device-reg = <0x958>;
+ st,boot-device-spi = <0x1a>;
+ status = "okay";
+ };
+
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 13/37] mtd: st_spi_fsm: Prepare the read/write FSM message sequence(s)
From: Lee Jones @ 2014-01-23 10:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
The FSM Serial Flash Controller is driven by issuing a standard set of
register writes we call a message sequence. This patch supplies a method
to prepare read/write FSM message sequence(s) based on chip capability
and configuration.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 69 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 1803f94..961abfd 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -520,6 +520,75 @@ stfsm_search_seq_rw_configs(struct stfsm *fsm,
return NULL;
}
+/* Prepare a READ/WRITE sequence according to configuration parameters */
+static void stfsm_prepare_rw_seq(struct stfsm *fsm,
+ struct stfsm_seq *seq,
+ struct seq_rw_config *cfg)
+{
+ int addr1_cycles, addr2_cycles;
+ int i = 0;
+
+ memset(seq, 0, sizeof(*seq));
+
+ /* Add READ/WRITE OPC */
+ seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
+ SEQ_OPC_CYCLES(8) |
+ SEQ_OPC_OPCODE(cfg->cmd));
+
+ /* Add WREN OPC for a WRITE sequence */
+ if (cfg->write)
+ seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
+ SEQ_OPC_CYCLES(8) |
+ SEQ_OPC_OPCODE(FLASH_CMD_WREN) |
+ SEQ_OPC_CSDEASSERT);
+
+ /* Address configuration (24 or 32-bit addresses) */
+ addr1_cycles = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8;
+ addr1_cycles /= cfg->addr_pads;
+ addr2_cycles = 16 / cfg->addr_pads;
+ seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 | /* ADD1 cycles */
+ (cfg->addr_pads - 1) << 6 | /* ADD1 pads */
+ (addr2_cycles & 0x3f) << 16 | /* ADD2 cycles */
+ ((cfg->addr_pads - 1) << 22)); /* ADD2 pads */
+
+ /* Data/Sequence configuration */
+ seq->seq_cfg = ((cfg->data_pads - 1) << 16 |
+ SEQ_CFG_STARTSEQ |
+ SEQ_CFG_CSDEASSERT);
+ if (!cfg->write)
+ seq->seq_cfg |= SEQ_CFG_READNOTWRITE;
+
+ /* Mode configuration (no. of pads taken from addr cfg) */
+ seq->mode = ((cfg->mode_data & 0xff) << 0 | /* data */
+ (cfg->mode_cycles & 0x3f) << 16 | /* cycles */
+ (cfg->addr_pads - 1) << 22); /* pads */
+
+ /* Dummy configuration (no. of pads taken from addr cfg) */
+ seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 | /* cycles */
+ (cfg->addr_pads - 1) << 22); /* pads */
+
+
+ /* Instruction sequence */
+ i = 0;
+ if (cfg->write)
+ seq->seq[i++] = STFSM_INST_CMD2;
+
+ seq->seq[i++] = STFSM_INST_CMD1;
+
+ seq->seq[i++] = STFSM_INST_ADD1;
+ seq->seq[i++] = STFSM_INST_ADD2;
+
+ if (cfg->mode_cycles)
+ seq->seq[i++] = STFSM_INST_MODE;
+
+ if (cfg->dummy_cycles)
+ seq->seq[i++] = STFSM_INST_DUMMY;
+
+ seq->seq[i++] =
+ cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ;
+ seq->seq[i++] = STFSM_INST_STOP;
+}
+
static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec)
{
const struct stfsm_seq *seq = &stfsm_seq_read_jedec;
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 12/37] mtd: st_spi_fsm: Fetch platform specific configurations
From: Lee Jones @ 2014-01-23 10:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
All supported platforms are able to pass specific configurations via
the Device Tree on boot. Here we add a function which is to be called
during the probing process which will extract them, or make other
assumptions based on capabilities provided.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index efd8fdb..1803f94 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -654,6 +654,16 @@ static int stfsm_init(struct stfsm *fsm)
return 0;
}
+static void stfsm_fetch_platform_configs(struct platform_device *pdev)
+{
+ struct stfsm *fsm = platform_get_drvdata(pdev);
+ struct flash_info *info = fsm->info;
+
+ /* Use device size to determine address width */
+ if (info->sector_size * info->n_sectors > 0xFFFFFF)
+ info->flags |= FLASH_FLAG_32BIT_ADDR;
+}
+
static int stfsm_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -712,6 +722,8 @@ static int stfsm_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, fsm);
+ stfsm_fetch_platform_configs(pdev);
+
fsm->mtd.dev.parent = &pdev->dev;
fsm->mtd.type = MTD_NORFLASH;
fsm->mtd.writesize = 4;
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 11/37] mtd: st_spi_fsm: Search for preferred FSM message sequence configurations
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
Here we provide a means to traverse though all supplied FSM message
sequence configurations and pick one based on our chip's capabilities.
The first one we match will be the preferred one, as they are
presented in order of preference.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index a70e916..efd8fdb 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -258,6 +258,18 @@ struct stfsm_seq {
uint32_t seq_cfg;
} __packed __aligned(4);
+/* Parameters to configure a READ or WRITE FSM sequence */
+struct seq_rw_config {
+ uint32_t flags; /* flags to support config */
+ uint8_t cmd; /* FLASH command */
+ int write; /* Write Sequence */
+ uint8_t addr_pads; /* No. of addr pads (MODE & DUMMY) */
+ uint8_t data_pads; /* No. of data pads */
+ uint8_t mode_data; /* MODE data */
+ uint8_t mode_cycles; /* No. of MODE cycles */
+ uint8_t dummy_cycles; /* No. of DUMMY cycles */
+};
+
/* SPI Flash Device Table */
struct flash_info {
char *name;
@@ -493,6 +505,21 @@ static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf,
}
}
+/* Search for preferred configuration based on available flags */
+static struct seq_rw_config *
+stfsm_search_seq_rw_configs(struct stfsm *fsm,
+ struct seq_rw_config cfgs[])
+{
+ struct seq_rw_config *config;
+ int flags = fsm->info->flags;
+
+ for (config = cfgs; config->cmd != 0; config++)
+ if ((config->flags & flags) == config->flags)
+ return config;
+
+ return NULL;
+}
+
static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec)
{
const struct stfsm_seq *seq = &stfsm_seq_read_jedec;
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 10/37] mtd: st_spi_fsm: Dynamically setup flash device based on JEDEC ID
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
Using previously added infrastructure we can now extract a device's JEDEC
ID, compare it to a list of known and supported devices and make assumptions
based on known characteristics of a given chip.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 455deef..a70e916 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -240,6 +240,7 @@ struct stfsm {
struct resource *region;
struct mtd_info mtd;
struct mutex lock;
+ struct flash_info *info;
uint32_t fifo_dir_delay;
};
@@ -508,6 +509,7 @@ static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec)
static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm)
{
+ struct flash_info *info;
u16 ext_jedec;
u32 jedec;
u8 id[5];
@@ -525,6 +527,15 @@ static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm)
dev_dbg(fsm->dev, "JEDEC = 0x%08x [%02x %02x %02x %02x %02x]\n",
jedec, id[0], id[1], id[2], id[3], id[4]);
+ for (info = flash_types; info->name; info++) {
+ if (info->jedec_id == jedec) {
+ if (info->ext_id && info->ext_id != ext_jedec)
+ continue;
+ return info;
+ }
+ }
+ dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec);
+
return NULL;
}
@@ -619,6 +630,7 @@ static int stfsm_init(struct stfsm *fsm)
static int stfsm_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
+ struct flash_info *info;
struct resource *res;
struct stfsm *fsm;
int ret;
@@ -665,7 +677,11 @@ static int stfsm_probe(struct platform_device *pdev)
}
/* Detect SPI FLASH device */
- stfsm_jedec_probe(fsm);
+ info = stfsm_jedec_probe(fsm);
+ if (!info)
+ return -ENODEV;
+
+ fsm->info = info;
platform_set_drvdata(pdev, fsm);
@@ -674,6 +690,15 @@ static int stfsm_probe(struct platform_device *pdev)
fsm->mtd.writesize = 4;
fsm->mtd.writebufsize = fsm->mtd.writesize;
fsm->mtd.flags = MTD_CAP_NORFLASH;
+ fsm->mtd.size = info->sector_size * info->n_sectors;
+ fsm->mtd.erasesize = info->sector_size;
+
+ dev_err(&pdev->dev,
+ "Found serial flash device: %s\n"
+ " size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n",
+ info->name,
+ (long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20),
+ fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10));
return mtd_device_parse_register(&fsm->mtd, NULL, NULL, NULL, 0);
}
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 09/37] mtd: st_spi_fsm: Provide device look-up table
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
Supply a lookup table of all the devices we intend to support. This table
is used to store device information such as; a human readable device name,
their JEDEC ID (plus the extended version), sector size and amount, a bit
store of a device's capabilities, its maximum running frequency and
possible use of a per-device configuration call-back.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 136 +++++++++++++++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index fe4f3c1..455deef 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -257,6 +257,142 @@ struct stfsm_seq {
uint32_t seq_cfg;
} __packed __aligned(4);
+/* SPI Flash Device Table */
+struct flash_info {
+ char *name;
+ /*
+ * JEDEC id zero means "no ID" (most older chips); otherwise it has
+ * a high byte of zero plus three data bytes: the manufacturer id,
+ * then a two byte device id.
+ */
+ u32 jedec_id;
+ u16 ext_id;
+ /*
+ * The size listed here is what works with FLASH_CMD_SE, which isn't
+ * necessarily called a "sector" by the vendor.
+ */
+ unsigned sector_size;
+ u16 n_sectors;
+ u32 flags;
+ /*
+ * Note, where FAST_READ is supported, freq_max specifies the
+ * FAST_READ frequency, not the READ frequency.
+ */
+ u32 max_freq;
+ int (*config)(struct stfsm *);
+};
+
+static struct flash_info flash_types[] = {
+ /*
+ * ST Microelectronics/Numonyx --
+ * (newer production versions may have feature updates
+ * (eg faster operating frequency)
+ */
+#define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST)
+ { "m25p40", 0x202013, 0, 64 * 1024, 8, M25P_FLAG, 25, NULL },
+ { "m25p80", 0x202014, 0, 64 * 1024, 16, M25P_FLAG, 25, NULL },
+ { "m25p16", 0x202015, 0, 64 * 1024, 32, M25P_FLAG, 25, NULL },
+ { "m25p32", 0x202016, 0, 64 * 1024, 64, M25P_FLAG, 50, NULL },
+ { "m25p64", 0x202017, 0, 64 * 1024, 128, M25P_FLAG, 50, NULL },
+ { "m25p128", 0x202018, 0, 256 * 1024, 64, M25P_FLAG, 50, NULL },
+
+#define M25PX_FLAG (FLASH_FLAG_READ_WRITE | \
+ FLASH_FLAG_READ_FAST | \
+ FLASH_FLAG_READ_1_1_2 | \
+ FLASH_FLAG_WRITE_1_1_2)
+ { "m25px32", 0x207116, 0, 64 * 1024, 64, M25PX_FLAG, 75, NULL },
+ { "m25px64", 0x207117, 0, 64 * 1024, 128, M25PX_FLAG, 75, NULL },
+
+#define MX25_FLAG (FLASH_FLAG_READ_WRITE | \
+ FLASH_FLAG_READ_FAST | \
+ FLASH_FLAG_READ_1_1_2 | \
+ FLASH_FLAG_READ_1_2_2 | \
+ FLASH_FLAG_READ_1_1_4 | \
+ FLASH_FLAG_READ_1_4_4 | \
+ FLASH_FLAG_SE_4K | \
+ FLASH_FLAG_SE_32K)
+ { "mx25l25635e", 0xc22019, 0, 64*1024, 512,
+ (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, NULL }
+
+#define N25Q_FLAG (FLASH_FLAG_READ_WRITE | \
+ FLASH_FLAG_READ_FAST | \
+ FLASH_FLAG_READ_1_1_2 | \
+ FLASH_FLAG_READ_1_2_2 | \
+ FLASH_FLAG_READ_1_1_4 | \
+ FLASH_FLAG_READ_1_4_4 | \
+ FLASH_FLAG_WRITE_1_1_2 | \
+ FLASH_FLAG_WRITE_1_2_2 | \
+ FLASH_FLAG_WRITE_1_1_4 | \
+ FLASH_FLAG_WRITE_1_4_4)
+ { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, NULL },
+ { "n25q256", 0x20ba19, 0, 64 * 1024, 512,
+ N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, NULL },
+
+ /*
+ * Spansion S25FLxxxP
+ * - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
+ */
+#define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE | \
+ FLASH_FLAG_READ_1_1_2 | \
+ FLASH_FLAG_READ_1_2_2 | \
+ FLASH_FLAG_READ_1_1_4 | \
+ FLASH_FLAG_READ_1_4_4 | \
+ FLASH_FLAG_WRITE_1_1_4 | \
+ FLASH_FLAG_READ_FAST)
+ { "s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, S25FLXXXP_FLAG, 80,
+ NULL },
+ { "s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, S25FLXXXP_FLAG, 80,
+ NULL },
+
+ /*
+ * Spansion S25FLxxxS
+ * - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
+ * - RESET# signal supported by die but not bristled out on all
+ * package types. The package type is a function of board design,
+ * so this information is captured in the board's flags.
+ * - Supports 'DYB' sector protection. Depending on variant, sectors
+ * may default to locked state on power-on.
+ */
+#define S25FLXXXS_FLAG (S25FLXXXP_FLAG | \
+ FLASH_FLAG_RESET | \
+ FLASH_FLAG_DYB_LOCKING)
+ { "s25fl128s0", 0x012018, 0x0300, 256 * 1024, 64, S25FLXXXS_FLAG, 80,
+ NULL },
+ { "s25fl128s1", 0x012018, 0x0301, 64 * 1024, 256, S25FLXXXS_FLAG, 80,
+ NULL },
+ { "s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128,
+ S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, NULL },
+ { "s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512,
+ S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, NULL },
+
+ /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
+#define W25X_FLAG (FLASH_FLAG_READ_WRITE | \
+ FLASH_FLAG_READ_FAST | \
+ FLASH_FLAG_READ_1_1_2 | \
+ FLASH_FLAG_WRITE_1_1_2)
+ { "w25x40", 0xef3013, 0, 64 * 1024, 8, W25X_FLAG, 75, NULL },
+ { "w25x80", 0xef3014, 0, 64 * 1024, 16, W25X_FLAG, 75, NULL },
+ { "w25x16", 0xef3015, 0, 64 * 1024, 32, W25X_FLAG, 75, NULL },
+ { "w25x32", 0xef3016, 0, 64 * 1024, 64, W25X_FLAG, 75, NULL },
+ { "w25x64", 0xef3017, 0, 64 * 1024, 128, W25X_FLAG, 75, NULL },
+
+ /* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */
+#define W25Q_FLAG (FLASH_FLAG_READ_WRITE | \
+ FLASH_FLAG_READ_FAST | \
+ FLASH_FLAG_READ_1_1_2 | \
+ FLASH_FLAG_READ_1_2_2 | \
+ FLASH_FLAG_READ_1_1_4 | \
+ FLASH_FLAG_READ_1_4_4 | \
+ FLASH_FLAG_WRITE_1_1_4)
+ { "w25q80", 0xef4014, 0, 64 * 1024, 16, W25Q_FLAG, 80, NULL },
+ { "w25q16", 0xef4015, 0, 64 * 1024, 32, W25Q_FLAG, 80, NULL },
+ { "w25q32", 0xef4016, 0, 64 * 1024, 64, W25Q_FLAG, 80, NULL },
+ { "w25q64", 0xef4017, 0, 64 * 1024, 128, W25Q_FLAG, 80, NULL },
+
+ /* Sentinel */
+ { NULL, 0x000000, 0, 0, 0, 0, 0, NULL },
+};
+
static struct stfsm_seq stfsm_seq_read_jedec = {
.data_size = TRANSFER_SIZE(8),
.seq_opc[0] = (SEQ_OPC_PADS_1 |
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 08/37] mtd: devices: Provide header for shared OPCODEs and SFDP commands
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
JEDEC have helped to standardise a great deal of the commands which
can be issued to a Serial Flash devices. Many of the Serial Flash
Discoverable Parameters (SFDP) commands are generic across devices.
This patch provides a shared point where these commands can be
defined.
Suggested-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/serial_flash_cmds.h | 81 +++++++++++++++++++++++++++++++++
drivers/mtd/devices/st_spi_fsm.c | 2 +
2 files changed, 83 insertions(+)
create mode 100644 drivers/mtd/devices/serial_flash_cmds.h
diff --git a/drivers/mtd/devices/serial_flash_cmds.h b/drivers/mtd/devices/serial_flash_cmds.h
new file mode 100644
index 0000000..4f0c2c7
--- /dev/null
+++ b/drivers/mtd/devices/serial_flash_cmds.h
@@ -0,0 +1,81 @@
+/*
+ * Generic/SFDP Flash Commands and Device Capabilities
+ *
+ * Copyright (C) 2013 Lee Jones <lee.jones@lianro.org>
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MTD_SERIAL_FLASH_CMDS_H
+#define _MTD_SERIAL_FLASH_CMDS_H
+
+/* Generic Flash Commands/OPCODEs */
+#define FLASH_CMD_WREN 0x06
+#define FLASH_CMD_WRDI 0x04
+#define FLASH_CMD_RDID 0x9f
+#define FLASH_CMD_RDSR 0x05
+#define FLASH_CMD_RDSR2 0x35
+#define FLASH_CMD_WRSR 0x01
+#define FLASH_CMD_SE_4K 0x20
+#define FLASH_CMD_SE_32K 0x52
+#define FLASH_CMD_SE 0xd8
+#define FLASH_CMD_CHIPERASE 0xc7
+#define FLASH_CMD_WRVCR 0x81
+#define FLASH_CMD_RDVCR 0x85
+
+/* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
+#define FLASH_CMD_READ 0x03 /* READ */
+#define FLASH_CMD_READ_FAST 0x0b /* FAST READ */
+#define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */
+#define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */
+#define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */
+#define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */
+
+#define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */
+#define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
+#define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
+#define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
+#define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
+
+#define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */
+#define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */
+
+/* READ commands with 32-bit addressing */
+#define FLASH_CMD_READ4 0x13
+#define FLASH_CMD_READ4_FAST 0x0c
+#define FLASH_CMD_READ4_1_1_2 0x3c
+#define FLASH_CMD_READ4_1_2_2 0xbc
+#define FLASH_CMD_READ4_1_1_4 0x6c
+#define FLASH_CMD_READ4_1_4_4 0xec
+
+/* Configuration flags */
+#define FLASH_FLAG_SINGLE 0x000000ff
+#define FLASH_FLAG_READ_WRITE 0x00000001
+#define FLASH_FLAG_READ_FAST 0x00000002
+#define FLASH_FLAG_SE_4K 0x00000004
+#define FLASH_FLAG_SE_32K 0x00000008
+#define FLASH_FLAG_CE 0x00000010
+#define FLASH_FLAG_32BIT_ADDR 0x00000020
+#define FLASH_FLAG_RESET 0x00000040
+#define FLASH_FLAG_DYB_LOCKING 0x00000080
+
+#define FLASH_FLAG_DUAL 0x0000ff00
+#define FLASH_FLAG_READ_1_1_2 0x00000100
+#define FLASH_FLAG_READ_1_2_2 0x00000200
+#define FLASH_FLAG_READ_2_2_2 0x00000400
+#define FLASH_FLAG_WRITE_1_1_2 0x00001000
+#define FLASH_FLAG_WRITE_1_2_2 0x00002000
+#define FLASH_FLAG_WRITE_2_2_2 0x00004000
+
+#define FLASH_FLAG_QUAD 0x00ff0000
+#define FLASH_FLAG_READ_1_1_4 0x00010000
+#define FLASH_FLAG_READ_1_4_4 0x00020000
+#define FLASH_FLAG_READ_4_4_4 0x00040000
+#define FLASH_FLAG_WRITE_1_1_4 0x00100000
+#define FLASH_FLAG_WRITE_1_4_4 0x00200000
+#define FLASH_FLAG_WRITE_4_4_4 0x00400000
+
+#endif /* _MTD_SERIAL_FLASH_CMDS_H */
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 8a10f16..fe4f3c1 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -21,6 +21,8 @@
#include <linux/io.h>
#include <linux/of.h>
+#include "serial_flash_cmds.h"
+
/*
* FSM SPI Controller Registers
*/
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 07/37] mtd: st_spi_fsm: Add support for JEDEC ID extraction
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
Once we start supporting devices it will be handy go detect them
dynamically. This will be done using the chip's unique JEDEC ID. This
patch allows us to extract a device's JEDEC ID using the a predefined
FSM register write sequence.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 55 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index bb0f20a..8a10f16 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -255,6 +255,22 @@ struct stfsm_seq {
uint32_t seq_cfg;
} __packed __aligned(4);
+static struct stfsm_seq stfsm_seq_read_jedec = {
+ .data_size = TRANSFER_SIZE(8),
+ .seq_opc[0] = (SEQ_OPC_PADS_1 |
+ SEQ_OPC_CYCLES(8) |
+ SEQ_OPC_OPCODE(FLASH_CMD_RDID)),
+ .seq = {
+ STFSM_INST_CMD1,
+ STFSM_INST_DATA_READ,
+ STFSM_INST_STOP,
+ },
+ .seq_cfg = (SEQ_CFG_PADS_1 |
+ SEQ_CFG_READNOTWRITE |
+ SEQ_CFG_CSDEASSERT |
+ SEQ_CFG_STARTSEQ),
+};
+
static inline int stfsm_is_idle(struct stfsm *fsm)
{
return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10;
@@ -338,6 +354,42 @@ static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf,
}
}
+static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec)
+{
+ const struct stfsm_seq *seq = &stfsm_seq_read_jedec;
+ uint32_t tmp[2];
+
+ stfsm_load_seq(fsm, seq);
+
+ stfsm_read_fifo(fsm, tmp, 8);
+
+ memcpy(jedec, tmp, 5);
+
+ stfsm_wait_seq(fsm);
+}
+
+static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm)
+{
+ u16 ext_jedec;
+ u32 jedec;
+ u8 id[5];
+
+ stfsm_read_jedec(fsm, id);
+
+ jedec = id[0] << 16 | id[1] << 8 | id[2];
+ /*
+ * JEDEC also defines an optional "extended device information"
+ * string for after vendor-specific data, after the three bytes
+ * we use here. Supporting some chips might require using it.
+ */
+ ext_jedec = id[3] << 8 | id[4];
+
+ dev_dbg(fsm->dev, "JEDEC = 0x%08x [%02x %02x %02x %02x %02x]\n",
+ jedec, id[0], id[1], id[2], id[3], id[4]);
+
+ return NULL;
+}
+
static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
{
int ret, timeout = 10;
@@ -474,6 +526,9 @@ static int stfsm_probe(struct platform_device *pdev)
return ret;
}
+ /* Detect SPI FLASH device */
+ stfsm_jedec_probe(fsm);
+
platform_set_drvdata(pdev, fsm);
fsm->mtd.dev.parent = &pdev->dev;
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 06/37] mtd: st_spi_fsm: Supply defines for the possible flash command opcodes
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
Flash chip commands are issued using a set of predefined opcodes. These
are mostly the same for all flash devices, but do differ on occasion.
This patch supplies the majority of the key ones which will be used in
this driver.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 0eba759..bb0f20a 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -194,6 +194,44 @@
#define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */
+/* Flash Commands */
+#define FLASH_CMD_WREN 0x06
+#define FLASH_CMD_WRDI 0x04
+#define FLASH_CMD_RDID 0x9f
+#define FLASH_CMD_RDSR 0x05
+#define FLASH_CMD_RDSR2 0x35
+#define FLASH_CMD_WRSR 0x01
+#define FLASH_CMD_SE_4K 0x20
+#define FLASH_CMD_SE_32K 0x52
+#define FLASH_CMD_SE 0xd8
+#define FLASH_CMD_CHIPERASE 0xc7
+#define FLASH_CMD_WRVCR 0x81
+#define FLASH_CMD_RDVCR 0x85
+
+#define FLASH_CMD_READ 0x03 /* READ */
+#define FLASH_CMD_READ_FAST 0x0b /* FAST READ */
+#define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */
+#define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */
+#define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */
+#define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */
+
+#define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */
+#define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
+#define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
+#define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
+#define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
+
+#define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */
+#define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */
+
+/* READ commands with 32-bit addressing (N25Q256 and S25FLxxxS) */
+#define FLASH_CMD_READ4 0x13
+#define FLASH_CMD_READ4_FAST 0x0c
+#define FLASH_CMD_READ4_1_1_2 0x3c
+#define FLASH_CMD_READ4_1_2_2 0xbc
+#define FLASH_CMD_READ4_1_1_4 0x6c
+#define FLASH_CMD_READ4_1_4_4 0xec
+
struct stfsm {
struct device *dev;
void __iomem *base;
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 05/37] mtd: st_spi_fsm: Supply a method to read from the FSM's FIFO
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
When invoked the driver will attempt to read any available data from
the FSM's data register. Any data collected from this FIFO would have
originated from the flash chip.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index c7daeca..0eba759 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -274,6 +274,32 @@ static void stfsm_wait_seq(struct stfsm *fsm)
dev_err(fsm->dev, "timeout on sequence completion\n");
}
+static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf,
+ const uint32_t size)
+{
+ uint32_t remaining = size >> 2;
+ uint32_t avail;
+ uint32_t words;
+
+ dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size);
+
+ BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3));
+
+ while (remaining) {
+ for (;;) {
+ avail = stfsm_fifo_available(fsm);
+ if (avail)
+ break;
+ udelay(1);
+ }
+ words = min(avail, remaining);
+ remaining -= words;
+
+ readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
+ buf += words;
+ }
+}
+
static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
{
int ret, timeout = 10;
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 04/37] mtd: st_spi_fsm: Supply framework for device requests
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
The FSM hardware works by setting a predetermined sequence of register
writes. Rather than open coding them inside each functional block we're
going to define them in a series of formatted 'sequence structures'.
This patch provides the framework which shall be used for every action.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 49 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 5badbe4..c7daeca 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -204,6 +204,24 @@ struct stfsm {
uint32_t fifo_dir_delay;
};
+struct stfsm_seq {
+ uint32_t data_size;
+ uint32_t addr1;
+ uint32_t addr2;
+ uint32_t addr_cfg;
+ uint32_t seq_opc[5];
+ uint32_t mode;
+ uint32_t dummy;
+ uint32_t status;
+ uint8_t seq[16];
+ uint32_t seq_cfg;
+} __packed __aligned(4);
+
+static inline int stfsm_is_idle(struct stfsm *fsm)
+{
+ return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10;
+}
+
static inline uint32_t stfsm_fifo_available(struct stfsm *fsm)
{
return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f;
@@ -225,6 +243,37 @@ static void stfsm_clear_fifo(struct stfsm *fsm)
}
}
+static inline void stfsm_load_seq(struct stfsm *fsm,
+ const struct stfsm_seq *seq)
+{
+ void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE;
+ const uint32_t *src = (const uint32_t *)seq;
+ int words = sizeof(*seq) / sizeof(*src);
+
+ BUG_ON(!stfsm_is_idle(fsm));
+
+ while (words--) {
+ writel(*src, dst);
+ src++;
+ dst += 4;
+ }
+}
+
+static void stfsm_wait_seq(struct stfsm *fsm)
+{
+ unsigned long timeo = jiffies + HZ;
+
+ while (time_before(jiffies, timeo)) {
+ if (stfsm_is_idle(fsm))
+ return;
+
+ cond_resched();
+ }
+
+ if (!stfsm_is_idle(fsm))
+ dev_err(fsm->dev, "timeout on sequence completion\n");
+}
+
static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
{
int ret, timeout = 10;
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 03/37] mtd: st_spi_fsm: Initialise and configure the FSM for normal working conditions
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
This patch uses default values to initialise a connected flash chip. This
includes; a device soft reset, setting of a safe working frequency, a
switch into Fast Sequencing Mode, configuring of timing data and a purge
of the FIFO.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 127 +++++++++++++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index ccee749..5badbe4 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -74,6 +74,10 @@
#define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16)
#define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24)
+#define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0x0AA)
+#define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0xA0)
+#define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0x00)
+
/*
* Register: SPI_FAST_SEQ_TRANSFER_SIZE
*/
@@ -185,19 +189,136 @@
#define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0)
#define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0)
+#define STFSM_DEFAULT_EMI_FREQ 100000000UL /* 100 MHz */
+#define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */
+
+#define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */
+
struct stfsm {
struct device *dev;
void __iomem *base;
struct resource *region;
struct mtd_info mtd;
struct mutex lock;
+
+ uint32_t fifo_dir_delay;
};
+static inline uint32_t stfsm_fifo_available(struct stfsm *fsm)
+{
+ return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f;
+}
+
+static void stfsm_clear_fifo(struct stfsm *fsm)
+{
+ uint32_t avail;
+
+ for (;;) {
+ avail = stfsm_fifo_available(fsm);
+ if (!avail)
+ break;
+
+ while (avail) {
+ readl(fsm->base + SPI_FAST_SEQ_DATA_REG);
+ avail--;
+ }
+ }
+}
+
+static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
+{
+ int ret, timeout = 10;
+
+ /* Wait for controller to accept mode change */
+ while (--timeout) {
+ ret = readl(fsm->base + SPI_STA_MODE_CHANGE);
+ if (ret & 0x1)
+ break;
+ udelay(1);
+ }
+
+ if (!timeout)
+ return -EBUSY;
+
+ writel(mode, fsm->base + SPI_MODESELECT);
+
+ return 0;
+}
+
+static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq)
+{
+ uint32_t emi_freq;
+ uint32_t clk_div;
+
+ /* TODO: Make this dynamic */
+ emi_freq = STFSM_DEFAULT_EMI_FREQ;
+
+ /*
+ * Calculate clk_div - values between 2 and 128
+ * Multiple of 2, rounded up
+ */
+ clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq);
+ if (clk_div < 2)
+ clk_div = 2;
+ else if (clk_div > 128)
+ clk_div = 128;
+
+ /*
+ * Determine a suitable delay for the IP to complete a change of
+ * direction of the FIFO. The required delay is related to the clock
+ * divider used. The following heuristics are based on empirical tests,
+ * using a 100MHz EMI clock.
+ */
+ if (clk_div <= 4)
+ fsm->fifo_dir_delay = 0;
+ else if (clk_div <= 10)
+ fsm->fifo_dir_delay = 1;
+ else
+ fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10);
+
+ dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n",
+ emi_freq, spi_freq, clk_div);
+
+ writel(clk_div, fsm->base + SPI_CLOCKDIV);
+}
+
+static int stfsm_init(struct stfsm *fsm)
+{
+ int ret;
+
+ /* Perform a soft reset of the FSM controller */
+ writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG);
+ udelay(1);
+ writel(0, fsm->base + SPI_FAST_SEQ_CFG);
+
+ /* Set clock to 'safe' frequency initially */
+ stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ);
+
+ /* Switch to FSM */
+ ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM);
+ if (ret)
+ return ret;
+
+ /* Set timing parameters */
+ writel(SPI_CFG_DEVICE_ST |
+ SPI_CFG_DEFAULT_MIN_CS_HIGH |
+ SPI_CFG_DEFAULT_CS_SETUPHOLD |
+ SPI_CFG_DEFAULT_DATA_HOLD,
+ fsm->base + SPI_CONFIGDATA);
+ writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG);
+
+ /* Clear FIFO, just in case */
+ stfsm_clear_fifo(fsm);
+
+ return 0;
+}
+
static int stfsm_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *res;
struct stfsm *fsm;
+ int ret;
if (!np) {
dev_err(&pdev->dev, "No DT found\n");
@@ -234,6 +355,12 @@ static int stfsm_probe(struct platform_device *pdev)
mutex_init(&fsm->lock);
+ ret = stfsm_init(fsm);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to initialise FSM Controller\n");
+ return ret;
+ }
+
platform_set_drvdata(pdev, fsm);
fsm->mtd.dev.parent = &pdev->dev;
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 02/37] mtd: st_spi_fsm: Supply all register address and bit logic defines
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
Here we provide the FSM's register addresses, register bit names/offsets
and some commands which will prove useful as we start bulk the FMS's
driver out with functionality.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/st_spi_fsm.c | 172 ++++++++++++++++++++++++++++++++++++++-
drivers/mtd/devices/st_spi_fsm.h | 27 ------
2 files changed, 171 insertions(+), 28 deletions(-)
delete mode 100644 drivers/mtd/devices/st_spi_fsm.h
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index fe66342..ccee749 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -21,7 +21,177 @@
#include <linux/io.h>
#include <linux/of.h>
-#include "st_spi_fsm.h"
+/*
+ * FSM SPI Controller Registers
+ */
+#define SPI_CLOCKDIV 0x0010
+#define SPI_MODESELECT 0x0018
+#define SPI_CONFIGDATA 0x0020
+#define SPI_STA_MODE_CHANGE 0x0028
+#define SPI_FAST_SEQ_TRANSFER_SIZE 0x0100
+#define SPI_FAST_SEQ_ADD1 0x0104
+#define SPI_FAST_SEQ_ADD2 0x0108
+#define SPI_FAST_SEQ_ADD_CFG 0x010c
+#define SPI_FAST_SEQ_OPC1 0x0110
+#define SPI_FAST_SEQ_OPC2 0x0114
+#define SPI_FAST_SEQ_OPC3 0x0118
+#define SPI_FAST_SEQ_OPC4 0x011c
+#define SPI_FAST_SEQ_OPC5 0x0120
+#define SPI_MODE_BITS 0x0124
+#define SPI_DUMMY_BITS 0x0128
+#define SPI_FAST_SEQ_FLASH_STA_DATA 0x012c
+#define SPI_FAST_SEQ_1 0x0130
+#define SPI_FAST_SEQ_2 0x0134
+#define SPI_FAST_SEQ_3 0x0138
+#define SPI_FAST_SEQ_4 0x013c
+#define SPI_FAST_SEQ_CFG 0x0140
+#define SPI_FAST_SEQ_STA 0x0144
+#define SPI_QUAD_BOOT_SEQ_INIT_1 0x0148
+#define SPI_QUAD_BOOT_SEQ_INIT_2 0x014c
+#define SPI_QUAD_BOOT_READ_SEQ_1 0x0150
+#define SPI_QUAD_BOOT_READ_SEQ_2 0x0154
+#define SPI_PROGRAM_ERASE_TIME 0x0158
+#define SPI_MULT_PAGE_REPEAT_SEQ_1 0x015c
+#define SPI_MULT_PAGE_REPEAT_SEQ_2 0x0160
+#define SPI_STATUS_WR_TIME_REG 0x0164
+#define SPI_FAST_SEQ_DATA_REG 0x0300
+
+/*
+ * Register: SPI_MODESELECT
+ */
+#define SPI_MODESELECT_CONTIG 0x01
+#define SPI_MODESELECT_FASTREAD 0x02
+#define SPI_MODESELECT_DUALIO 0x04
+#define SPI_MODESELECT_FSM 0x08
+#define SPI_MODESELECT_QUADBOOT 0x10
+
+/*
+ * Register: SPI_CONFIGDATA
+ */
+#define SPI_CFG_DEVICE_ST 0x1
+#define SPI_CFG_DEVICE_ATMEL 0x4
+#define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0xfff) << 4)
+#define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16)
+#define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24)
+
+/*
+ * Register: SPI_FAST_SEQ_TRANSFER_SIZE
+ */
+#define TRANSFER_SIZE(x) ((x) * 8)
+
+/*
+ * Register: SPI_FAST_SEQ_ADD_CFG
+ */
+#define ADR_CFG_CYCLES_ADD1(x) ((x) << 0)
+#define ADR_CFG_PADS_1_ADD1 (0x0 << 6)
+#define ADR_CFG_PADS_2_ADD1 (0x1 << 6)
+#define ADR_CFG_PADS_4_ADD1 (0x3 << 6)
+#define ADR_CFG_CSDEASSERT_ADD1 (1 << 8)
+#define ADR_CFG_CYCLES_ADD2(x) ((x) << (0+16))
+#define ADR_CFG_PADS_1_ADD2 (0x0 << (6+16))
+#define ADR_CFG_PADS_2_ADD2 (0x1 << (6+16))
+#define ADR_CFG_PADS_4_ADD2 (0x3 << (6+16))
+#define ADR_CFG_CSDEASSERT_ADD2 (1 << (8+16))
+
+/*
+ * Register: SPI_FAST_SEQ_n
+ */
+#define SEQ_OPC_OPCODE(x) ((x) << 0)
+#define SEQ_OPC_CYCLES(x) ((x) << 8)
+#define SEQ_OPC_PADS_1 (0x0 << 14)
+#define SEQ_OPC_PADS_2 (0x1 << 14)
+#define SEQ_OPC_PADS_4 (0x3 << 14)
+#define SEQ_OPC_CSDEASSERT (1 << 16)
+
+/*
+ * Register: SPI_FAST_SEQ_CFG
+ */
+#define SEQ_CFG_STARTSEQ (1 << 0)
+#define SEQ_CFG_SWRESET (1 << 5)
+#define SEQ_CFG_CSDEASSERT (1 << 6)
+#define SEQ_CFG_READNOTWRITE (1 << 7)
+#define SEQ_CFG_ERASE (1 << 8)
+#define SEQ_CFG_PADS_1 (0x0 << 16)
+#define SEQ_CFG_PADS_2 (0x1 << 16)
+#define SEQ_CFG_PADS_4 (0x3 << 16)
+
+/*
+ * Register: SPI_MODE_BITS
+ */
+#define MODE_DATA(x) (x & 0xff)
+#define MODE_CYCLES(x) ((x & 0x3f) << 16)
+#define MODE_PADS_1 (0x0 << 22)
+#define MODE_PADS_2 (0x1 << 22)
+#define MODE_PADS_4 (0x3 << 22)
+#define DUMMY_CSDEASSERT (1 << 24)
+
+/*
+ * Register: SPI_DUMMY_BITS
+ */
+#define DUMMY_CYCLES(x) ((x & 0x3f) << 16)
+#define DUMMY_PADS_1 (0x0 << 22)
+#define DUMMY_PADS_2 (0x1 << 22)
+#define DUMMY_PADS_4 (0x3 << 22)
+#define DUMMY_CSDEASSERT (1 << 24)
+
+/*
+ * Register: SPI_FAST_SEQ_FLASH_STA_DATA
+ */
+#define STA_DATA_BYTE1(x) ((x & 0xff) << 0)
+#define STA_DATA_BYTE2(x) ((x & 0xff) << 8)
+#define STA_PADS_1 (0x0 << 16)
+#define STA_PADS_2 (0x1 << 16)
+#define STA_PADS_4 (0x3 << 16)
+#define STA_CSDEASSERT (0x1 << 20)
+#define STA_RDNOTWR (0x1 << 21)
+
+/*
+ * FSM SPI Instruction Opcodes
+ */
+#define STFSM_OPC_CMD 0x1
+#define STFSM_OPC_ADD 0x2
+#define STFSM_OPC_STA 0x3
+#define STFSM_OPC_MODE 0x4
+#define STFSM_OPC_DUMMY 0x5
+#define STFSM_OPC_DATA 0x6
+#define STFSM_OPC_WAIT 0x7
+#define STFSM_OPC_JUMP 0x8
+#define STFSM_OPC_GOTO 0x9
+#define STFSM_OPC_STOP 0xF
+
+/*
+ * FSM SPI Instructions (== opcode + operand).
+ */
+#define STFSM_INSTR(cmd, op) ((cmd) | ((op) << 4))
+
+#define STFSM_INST_CMD1 STFSM_INSTR(STFSM_OPC_CMD, 1)
+#define STFSM_INST_CMD2 STFSM_INSTR(STFSM_OPC_CMD, 2)
+#define STFSM_INST_CMD3 STFSM_INSTR(STFSM_OPC_CMD, 3)
+#define STFSM_INST_CMD4 STFSM_INSTR(STFSM_OPC_CMD, 4)
+#define STFSM_INST_CMD5 STFSM_INSTR(STFSM_OPC_CMD, 5)
+#define STFSM_INST_ADD1 STFSM_INSTR(STFSM_OPC_ADD, 1)
+#define STFSM_INST_ADD2 STFSM_INSTR(STFSM_OPC_ADD, 2)
+
+#define STFSM_INST_DATA_WRITE STFSM_INSTR(STFSM_OPC_DATA, 1)
+#define STFSM_INST_DATA_READ STFSM_INSTR(STFSM_OPC_DATA, 2)
+
+#define STFSM_INST_STA_RD1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
+#define STFSM_INST_STA_WR1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
+#define STFSM_INST_STA_RD2 STFSM_INSTR(STFSM_OPC_STA, 0x2)
+#define STFSM_INST_STA_WR1_2 STFSM_INSTR(STFSM_OPC_STA, 0x3)
+
+#define STFSM_INST_MODE STFSM_INSTR(STFSM_OPC_MODE, 0)
+#define STFSM_INST_DUMMY STFSM_INSTR(STFSM_OPC_DUMMY, 0)
+#define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0)
+#define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0)
+
+struct stfsm {
+ struct device *dev;
+ void __iomem *base;
+ struct resource *region;
+ struct mtd_info mtd;
+ struct mutex lock;
+};
static int stfsm_probe(struct platform_device *pdev)
{
diff --git a/drivers/mtd/devices/st_spi_fsm.h b/drivers/mtd/devices/st_spi_fsm.h
deleted file mode 100644
index df45e1a..0000000
--- a/drivers/mtd/devices/st_spi_fsm.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * st_spi_fsm.c Support for ST Serial Flash Controller
- *
- * Author: Angus Clark <angus.clark@st.com>
- *
- * Copyright (C) 2010-2013 STicroelectronics Limited
- *
- * JEDEC probe based on drivers/mtd/devices/m25p80.c
- *
- * This code is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef ST_SPI_FSM_H
-#define ST_SPI_FSM_H
-
-struct stfsm {
- struct device *dev;
- void __iomem *base;
- struct resource *region;
- struct mtd_info mtd;
- struct mutex lock;
-};
-
-#endif /* ST_SPI_FSM_H */
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 01/37] mtd: st_spi_fsm: Allocate resources and register with MTD framework
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390473085-24626-1-git-send-email-lee.jones@linaro.org>
This is a new driver. It's used to communicate with a special type of
optimised Serial Flash Controller called the FSM. The FSM uses a subset
of the SPI protocol to communicate with supported NOR-Flash devices.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mtd/devices/Kconfig | 8 +++
drivers/mtd/devices/Makefile | 1 +
drivers/mtd/devices/st_spi_fsm.c | 109 +++++++++++++++++++++++++++++++++++++++
drivers/mtd/devices/st_spi_fsm.h | 27 ++++++++++
4 files changed, 145 insertions(+)
create mode 100644 drivers/mtd/devices/st_spi_fsm.c
create mode 100644 drivers/mtd/devices/st_spi_fsm.h
diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 74ab4b7..0cf48ac 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -217,6 +217,14 @@ config MTD_DOCG3
M-Systems and now Sandisk. The support is very experimental,
and doesn't give access to any write operations.
+config MTD_ST_SPI_FSM
+ tristate "ST Microelectronics SPI FSM Serial Flash Controller"
+ depends on ARM || SH
+ help
+ This provides an MTD device driver for the ST Microelectronics
+ SPI FSM Serial Flash Controller and support for a subset of
+ connected Serial Flash devices.
+
if MTD_DOCG3
config BCH_CONST_M
default 14
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
index d83bd73..c68868f 100644
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_NAND_OMAP_BCH) += elm.o
obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
obj-$(CONFIG_MTD_SST25L) += sst25l.o
obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
+obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o
CFLAGS_docg3.o += -I$(src)
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
new file mode 100644
index 0000000..fe66342
--- /dev/null
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -0,0 +1,109 @@
+/*
+ * st_spi_fsm.c Support for ST Serial Flash Controller
+ *
+ * Author: Angus Clark <angus.clark@st.com>
+ *
+ * Copyright (C) 2010-2013 STicroelectronics Limited
+ *
+ * JEDEC probe based on drivers/mtd/devices/m25p80.c
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include "st_spi_fsm.h"
+
+static int stfsm_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct resource *res;
+ struct stfsm *fsm;
+
+ if (!np) {
+ dev_err(&pdev->dev, "No DT found\n");
+ return -EINVAL;
+ }
+
+ fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL);
+ if (!fsm)
+ return -ENOMEM;
+
+ fsm->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Resource not found\n");
+ return -ENODEV;
+ }
+
+ fsm->region = devm_request_mem_region(&pdev->dev, res->start,
+ resource_size(res), pdev->name);
+ if (!fsm->region) {
+ dev_err(&pdev->dev,
+ "Failed to reserve memory region [0x%08x-0x%08x]\n",
+ res->start, res->end);
+ return -EBUSY;
+ }
+
+ fsm->base = devm_ioremap_nocache(&pdev->dev,
+ res->start, resource_size(res));
+ if (!fsm->base) {
+ dev_err(&pdev->dev, "Failed to ioremap [0x%08x]\n", res->start);
+ return -EINVAL;
+ }
+
+ mutex_init(&fsm->lock);
+
+ platform_set_drvdata(pdev, fsm);
+
+ fsm->mtd.dev.parent = &pdev->dev;
+ fsm->mtd.type = MTD_NORFLASH;
+ fsm->mtd.writesize = 4;
+ fsm->mtd.writebufsize = fsm->mtd.writesize;
+ fsm->mtd.flags = MTD_CAP_NORFLASH;
+
+ return mtd_device_parse_register(&fsm->mtd, NULL, NULL, NULL, 0);
+}
+
+static int stfsm_remove(struct platform_device *pdev)
+{
+ struct stfsm *fsm = platform_get_drvdata(pdev);
+ int err;
+
+ err = mtd_device_unregister(&fsm->mtd);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static struct of_device_id stfsm_match[] = {
+ { .compatible = "st,spi-fsm", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, stfsm_match);
+
+static struct platform_driver stfsm_driver = {
+ .probe = stfsm_probe,
+ .remove = stfsm_remove,
+ .driver = {
+ .name = "st-spi-fsm",
+ .owner = THIS_MODULE,
+ .of_match_table = stfsm_match,
+ },
+};
+module_platform_driver(stfsm_driver);
+
+MODULE_AUTHOR("Angus Clark <angus.clark@st.com>");
+MODULE_DESCRIPTION("ST SPI FSM driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/devices/st_spi_fsm.h b/drivers/mtd/devices/st_spi_fsm.h
new file mode 100644
index 0000000..df45e1a
--- /dev/null
+++ b/drivers/mtd/devices/st_spi_fsm.h
@@ -0,0 +1,27 @@
+/*
+ * st_spi_fsm.c Support for ST Serial Flash Controller
+ *
+ * Author: Angus Clark <angus.clark@st.com>
+ *
+ * Copyright (C) 2010-2013 STicroelectronics Limited
+ *
+ * JEDEC probe based on drivers/mtd/devices/m25p80.c
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef ST_SPI_FSM_H
+#define ST_SPI_FSM_H
+
+struct stfsm {
+ struct device *dev;
+ void __iomem *base;
+ struct resource *region;
+ struct mtd_info mtd;
+ struct mutex lock;
+};
+
+#endif /* ST_SPI_FSM_H */
--
1.8.3.2
^ permalink raw reply related
* [PATCH RESEND v4 00/37] mtd: st_spi_fsm: Add new driver
From: Lee Jones @ 2014-01-23 10:30 UTC (permalink / raw)
To: linux-arm-kernel
Version 4:
Tended to Brian's review comments
- Checkpatch acceptance
- MODULE_DEVICE_TABLE() name slip correction
- Timeout issue(s) resolved
- Potential infinite loop mitigated
- Code clarity suggests heeded
- Duplication with MTD core code removed
- Upgraded to using ROUND_UP() helper
- Moved non-shared header code into main driver
- Relocated dynamic msg sequence stores into main struct
- Averted adaption of static (table) data
- Basic whitespace/spelling/data type/dev_err suggestions applied
Version 3:
Okay, this thing should be fully functional now. Identify a chip
based on it's JEDEC ID, Read, Write, Erase (all or by sector).
Support for various chip quirks added too.
Version 2:
The first bunch of these patches have been on the MLs before, but
didn't receive a great deal of attention for the most part. We are
a little more featureful this time however. We can now successfully
setup and configure the N25Q256. We still can't read/write/erase
it though. I'll start work on that next week and will provide it in
the next instalment.
Version 1:
First stab at getting this thing Mainlined. It doesn't do a great deal
yet, but we are able to initialise the device and dynamically set it up
correctly based on an extracted JEDEC ID.
Documentation/devicetree/bindings/mtd/st-fsm.txt | 26 ++
arch/arm/boot/dts/stih416-b2105.dts | 14 +
arch/arm/boot/dts/stih416-pinctrl.dtsi | 12 +
drivers/mtd/devices/Kconfig | 8 +
drivers/mtd/devices/Makefile | 1 +
drivers/mtd/devices/serial_flash_cmds.h | 81 ++++
drivers/mtd/devices/st_spi_fsm.c | 2124 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
7 files changed, 2266 insertions(+)
^ permalink raw reply
* [PATCH] [media] s5p-mfc: Add Horizontal and Vertical search range for Video Macro Blocks
From: Sylwester Nawrocki @ 2014-01-23 10:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <019f01cf1823$7e020fa0$7a062ee0$%debski@samsung.com>
Hi,
On 23/01/14 11:11, Kamil Debski wrote:
>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
>> > b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
>> > index 4ff3b6c..a02e7b8 100644
>> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
>> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
>> > @@ -208,6 +208,24 @@ static struct mfc_control controls[] = {
>> > .default_value = 0,
>> > },
>> > {
>> > + .id = V4L2_CID_MPEG_VIDEO_HORZ_SEARCH_RANGE,
>> > + .type = V4L2_CTRL_TYPE_INTEGER,
>> > + .name = "horizontal search range of video macro block",
>
> This too should be property capitalised. Please mention the motion vectors
> too.
And additionally length of the name string should not exceed 31 characters.
--
Thanks,
Sylwester
^ permalink raw reply
* [PATCH] [media] s5p-mfc: Add Horizontal and Vertical search range for Video Macro Blocks
From: Kamil Debski @ 2014-01-23 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1388400186-22045-1-git-send-email-amit.grover@samsung.com>
Hi Amit,
> From: Amit Grover [mailto:amit.grover at samsung.com]
> Sent: Monday, December 30, 2013 11:43 AM
>
> This patch adds Controls to set Horizontal and Vertical search range
> for Motion Estimation block for Samsung MFC video Encoders.
>
> Signed-off-by: Swami Nathan <swaminath.p@samsung.com>
> Signed-off-by: Amit Grover <amit.grover@samsung.com>
> ---
> Documentation/DocBook/media/v4l/controls.xml | 14 +++++++++++++
> drivers/media/platform/s5p-mfc/s5p_mfc_common.h | 2 ++
> drivers/media/platform/s5p-mfc/s5p_mfc_enc.c | 24
> +++++++++++++++++++++++
> drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c | 8 ++------
> drivers/media/v4l2-core/v4l2-ctrls.c | 14 +++++++++++++
> include/uapi/linux/v4l2-controls.h | 2 ++
> 6 files changed, 58 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/DocBook/media/v4l/controls.xml
> b/Documentation/DocBook/media/v4l/controls.xml
> index 7a3b49b..70a0f6f 100644
> --- a/Documentation/DocBook/media/v4l/controls.xml
> +++ b/Documentation/DocBook/media/v4l/controls.xml
> @@ -2258,6 +2258,20 @@ Applicable to the MPEG1, MPEG2, MPEG4
> encoders.</entry>
> VBV buffer control.</entry>
> </row>
>
> + <row><entry></entry></row>
> + <row id="v4l2-mpeg-video-horz-search-range">
> + <entry
> spanname="id"><constant>V4L2_CID_MPEG_VIDEO_HORZ_SEARCH_RANGE</constant
HORZ is nowhere used. HOR is more commonly used in control names.
V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE seems better.
> > </entry>
> + <entry>integer</entry>
> + </row><row><entry spanname="descr">Sets the Horizontal
> search range for Video Macro blocks.</entry>
> + </row>
It's expressed in pixels? If so then it should be mentioned here. Also I
think this lacks the mention that it is used for motion estimation.
Please add a more detailed description.
> +
> + <row><entry></entry></row>
> + <row id="v4l2-mpeg-video-vert-search-range">
> + <entry
> spanname="id"><constant>V4L2_CID_MPEG_VIDEO_VERT_SEARCH_RANGE</constant
> > </entry>
V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE seems better.
> + <entry>integer</entry>
> + </row><row><entry spanname="descr">Sets the Vertical search
> range for Video Macro blocks.</entry>
> + </row>
> +
This description is too vague as well.
> <row><entry></entry></row>
> <row>
> <entry
> spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE</constant>&nb
> sp;</entry>
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> index 6920b54..f2c13c3 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> @@ -430,6 +430,8 @@ struct s5p_mfc_vp8_enc_params {
> struct s5p_mfc_enc_params {
> u16 width;
> u16 height;
> + u32 horz_range;
> + u32 vert_range;
mv_h_range ?
mv_v_range ?
>
> u16 gop_size;
> enum v4l2_mpeg_video_multi_slice_mode slice_mode;
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> index 4ff3b6c..a02e7b8 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> @@ -208,6 +208,24 @@ static struct mfc_control controls[] = {
> .default_value = 0,
> },
> {
> + .id = V4L2_CID_MPEG_VIDEO_HORZ_SEARCH_RANGE,
> + .type = V4L2_CTRL_TYPE_INTEGER,
> + .name = "horizontal search range of video macro block",
This too should be property capitalised. Please mention the motion vectors
too.
> + .minimum = 16,
> + .maximum = 128,
> + .step = 16,
> + .default_value = 32,
> + },
> + {
> + .id = V4L2_CID_MPEG_VIDEO_VERT_SEARCH_RANGE,
> + .type = V4L2_CTRL_TYPE_INTEGER,
> + .name = "vertical search range of video macro block",
This too should be property capitalised. Please mention the motion vectors
too.
> + .minimum = 16,
> + .maximum = 128,
> + .step = 16,
> + .default_value = 32,
> + },
> + {
> .id = V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
> .type = V4L2_CTRL_TYPE_INTEGER,
> .minimum = 0,
> @@ -1377,6 +1395,12 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl
> *ctrl)
> case V4L2_CID_MPEG_VIDEO_VBV_SIZE:
> p->vbv_size = ctrl->val;
> break;
> + case V4L2_CID_MPEG_VIDEO_HORZ_SEARCH_RANGE:
> + p->horz_range = ctrl->val;
> + break;
> + case V4L2_CID_MPEG_VIDEO_VERT_SEARCH_RANGE:
> + p->vert_range = ctrl->val;
> + break;
> case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE:
> p->codec.h264.cpb_size = ctrl->val;
> break;
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> index 461358c..47e1807 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> @@ -727,14 +727,10 @@ static int s5p_mfc_set_enc_params(struct
> s5p_mfc_ctx *ctx)
> WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
>
> /* setting for MV range [16, 256] */
> - reg = 0;
> - reg &= ~(0x3FFF);
> - reg = 256;
> + reg = (p->horz_range & 0x3fff); /* conditional check in app */
> WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE_V6);
Please add a S5P_FIMV_E_MV_HOR_RANGE_V6_MASK or something instead of this
magic number.
>
> - reg = 0;
> - reg &= ~(0x3FFF);
> - reg = 256;
> + reg = (p->vert_range & 0x3fff); /* conditional check in app */
Please add a S5P_FIMV_E_MV_VER_RANGE_V6_MASK or something instead of this
magic number.
> WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE_V6);
>
> WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION_V6);
> diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-
> core/v4l2-ctrls.c
> index fb46790..7cf23d5 100644
> --- a/drivers/media/v4l2-core/v4l2-ctrls.c
> +++ b/drivers/media/v4l2-core/v4l2-ctrls.c
> @@ -735,6 +735,8 @@ const char *v4l2_ctrl_get_name(u32 id)
> case V4L2_CID_MPEG_VIDEO_DEC_PTS: return
"Video
> Decoder PTS";
> case V4L2_CID_MPEG_VIDEO_DEC_FRAME: return
"Video
> Decoder Frame Count";
> case V4L2_CID_MPEG_VIDEO_VBV_DELAY: return
"Initial
> Delay for VBV Control";
> + case V4L2_CID_MPEG_VIDEO_HORZ_SEARCH_RANGE: return "hor
> search range of video MB";
This should be property capitalised. Please mention the motion vectors too.
> + case V4L2_CID_MPEG_VIDEO_VERT_SEARCH_RANGE: return "vert
> search range of video MB";
This too should be property capitalised. Please mention the motion vectors
too.
> case V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER: return
> "Repeat Sequence Header";
>
> /* VPX controls */
> @@ -905,6 +907,18 @@ void v4l2_ctrl_fill(u32 id, const char **name,
> enum v4l2_ctrl_type *type,
> *min = 0;
> *max = *step = 1;
> break;
> + case V4L2_CID_MPEG_VIDEO_HORZ_SEARCH_RANGE:
> + *type = V4L2_CTRL_TYPE_INTEGER;
> + *min = 16;
> + *max = 128;
> + *step = 16;
> + break;
> + case V4L2_CID_MPEG_VIDEO_VERT_SEARCH_RANGE:
> + *type = V4L2_CTRL_TYPE_INTEGER;
> + *min = 16;
> + *max = 128;
> + *step = 16;
> + break;
> case V4L2_CID_PAN_RESET:
> case V4L2_CID_TILT_RESET:
> case V4L2_CID_FLASH_STROBE:
> diff --git a/include/uapi/linux/v4l2-controls.h
> b/include/uapi/linux/v4l2-controls.h
> index 1666aab..bcce536 100644
> --- a/include/uapi/linux/v4l2-controls.h
> +++ b/include/uapi/linux/v4l2-controls.h
> @@ -372,6 +372,8 @@ enum v4l2_mpeg_video_multi_slice_mode {
> #define V4L2_CID_MPEG_VIDEO_DEC_FRAME
> (V4L2_CID_MPEG_BASE+224)
> #define V4L2_CID_MPEG_VIDEO_VBV_DELAY
> (V4L2_CID_MPEG_BASE+225)
> #define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER
> (V4L2_CID_MPEG_BASE+226)
> +#define V4L2_CID_MPEG_VIDEO_HORZ_SEARCH_RANGE
> (V4L2_CID_MPEG_BASE+227)
> +#define V4L2_CID_MPEG_VIDEO_VERT_SEARCH_RANGE
> (V4L2_CID_MPEG_BASE+228)
>
> #define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP
> (V4L2_CID_MPEG_BASE+300)
> #define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP
> (V4L2_CID_MPEG_BASE+301)
> --
> 1.7.9.5
Best wishes,
--
Kamil Debski
Samsung R&D Institute Poland
^ permalink raw reply
* [PATCH 1/6] arm64: Add macros to manage processor debug state
From: Will Deacon @ 2014-01-23 9:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALicx6sax=SHv2NryhY5QSBtyv-_wbCpPR5hFt9gngD96yP0oQ@mail.gmail.com>
On Thu, Jan 23, 2014 at 04:46:36AM +0000, Vijay Kilari wrote:
> On Wed, Jan 22, 2014 at 11:01 PM, Will Deacon <will.deacon@arm.com> wrote:
> >> diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
> >> index 23586bd..774ad04 100644
> >> --- a/arch/arm64/kernel/debug-monitors.c
> >> +++ b/arch/arm64/kernel/debug-monitors.c
> >> @@ -51,7 +51,7 @@ u8 debug_monitors_arch(void)
> >> static void mdscr_write(u32 mdscr)
> >> {
> >> unsigned long flags;
> >> - local_dbg_save(flags);
> >> + flags = local_dbg_save();
> >
> > Why are you changing the API? This is now pointlessly different to irqs.
>
> To be in line with arch_local_irq_save & arch_local_save_flags in irqflags.h,
> I moved this macros into functions and accordingly changed the caller.
> I could not find any code using this local_dbg_{save, restore} except
> from debug-monitors.c file
>
> If required, I can think of renaming local_dbg_{save,restore} as
> local_dbg_{save,restore}_flags
No, I'd rather local_dbg_{save, restore} were aligned with local_irq_{save,
restore} (as defined in include/linux/irqflags.h).
Will
^ permalink raw reply
* [PATCH] ARM: davinci: defconfig: drop CONFIG_REGULATOR_DUMMY
From: Prabhakar Lad @ 2014-01-23 9:27 UTC (permalink / raw)
To: linux-arm-kernel
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
This patch drops CONFIG_REGULATOR_DUMMY as this obsolete.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
---
arch/arm/configs/da8xx_omapl_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index 1571bea..c78de86 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -89,7 +89,6 @@ CONFIG_PINCTRL_SINGLE=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DUMMY=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_FB=y
CONFIG_FB_DA8XX=y
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/2] PWM: handle additional flags in of_pwm_simple_xlate
From: Sascha Hauer @ 2014-01-23 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390467898-9216-1-git-send-email-s.hauer@pengutronix.de>
Let of_pwm_simple_xlate behave like of_pwm_xlate_with_flags when
the argument count is 3. This makes of_pwm_xlate_with_flags unncessary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/pwm/core.c | 30 ++++++------------------------
drivers/pwm/pwm-atmel-tcb.c | 1 -
drivers/pwm/pwm-renesas-tpu.c | 1 -
drivers/pwm/pwm-samsung.c | 2 --
drivers/pwm/pwm-tiecap.c | 1 -
drivers/pwm/pwm-tiehrpwm.c | 1 -
drivers/pwm/pwm-vt8500.c | 1 -
include/linux/pwm.h | 3 ---
8 files changed, 6 insertions(+), 34 deletions(-)
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index c882051..329b1e5 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -131,12 +131,12 @@ static int pwm_device_request(struct pwm_device *pwm, const char *label)
return 0;
}
-struct pwm_device *
-of_pwm_xlate_with_flags(struct pwm_chip *pc, const struct of_phandle_args *args)
+static struct pwm_device *
+of_pwm_simple_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
{
struct pwm_device *pwm;
- if (args->args_count != 3)
+ if (args->args_count < 2)
return ERR_PTR(-EINVAL);
if (args->args[0] >= pc->npwm)
@@ -148,6 +148,9 @@ of_pwm_xlate_with_flags(struct pwm_chip *pc, const struct of_phandle_args *args)
pwm_set_period(pwm, args->args[1]);
+ if (args->args_count < 3)
+ return 0;
+
if (args->args[2] & PWM_POLARITY_INVERTED)
pwm_set_polarity(pwm, PWM_POLARITY_INVERSED);
else
@@ -155,27 +158,6 @@ of_pwm_xlate_with_flags(struct pwm_chip *pc, const struct of_phandle_args *args)
return pwm;
}
-EXPORT_SYMBOL_GPL(of_pwm_xlate_with_flags);
-
-static struct pwm_device *
-of_pwm_simple_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
-{
- struct pwm_device *pwm;
-
- if (args->args_count != 2)
- return ERR_PTR(-EINVAL);
-
- if (args->args[0] >= pc->npwm)
- return ERR_PTR(-EINVAL);
-
- pwm = pwm_request_from_chip(pc, args->args[0], NULL);
- if (IS_ERR(pwm))
- return pwm;
-
- pwm_set_period(pwm, args->args[1]);
-
- return pwm;
-}
static void of_pwmchip_add(struct pwm_chip *chip)
{
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
index 55fabf8..e1e5a20 100644
--- a/drivers/pwm/pwm-atmel-tcb.c
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -394,7 +394,6 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)
tcbpwm->chip.dev = &pdev->dev;
tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
- tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags;
tcbpwm->chip.base = -1;
tcbpwm->chip.npwm = NPWM;
tcbpwm->tc = tc;
diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c
index 0a8adb6..82dcab9 100644
--- a/drivers/pwm/pwm-renesas-tpu.c
+++ b/drivers/pwm/pwm-renesas-tpu.c
@@ -433,7 +433,6 @@ static int tpu_probe(struct platform_device *pdev)
tpu->chip.dev = &pdev->dev;
tpu->chip.ops = &tpu_pwm_ops;
- tpu->chip.of_xlate = of_pwm_xlate_with_flags;
tpu->chip.base = -1;
tpu->chip.npwm = TPU_CHANNEL_MAX;
diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c
index 8d8dced..465f9ee 100644
--- a/drivers/pwm/pwm-samsung.c
+++ b/drivers/pwm/pwm-samsung.c
@@ -485,8 +485,6 @@ static int pwm_samsung_probe(struct platform_device *pdev)
ret = pwm_samsung_parse_dt(chip);
if (ret)
return ret;
-
- chip->chip.of_xlate = of_pwm_xlate_with_flags;
} else {
if (!pdev->dev.platform_data) {
dev_err(&pdev->dev, "no platform data specified\n");
diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
index 4d7a01a..27cde03 100644
--- a/drivers/pwm/pwm-tiecap.c
+++ b/drivers/pwm/pwm-tiecap.c
@@ -228,7 +228,6 @@ static int ecap_pwm_probe(struct platform_device *pdev)
pc->chip.dev = &pdev->dev;
pc->chip.ops = &ecap_pwm_ops;
- pc->chip.of_xlate = of_pwm_xlate_with_flags;
pc->chip.base = -1;
pc->chip.npwm = 1;
diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index 2c2621a..4e566df 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -459,7 +459,6 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev)
pc->chip.dev = &pdev->dev;
pc->chip.ops = &ehrpwm_pwm_ops;
- pc->chip.of_xlate = of_pwm_xlate_with_flags;
pc->chip.base = -1;
pc->chip.npwm = NUM_PWM_CHANNEL;
diff --git a/drivers/pwm/pwm-vt8500.c b/drivers/pwm/pwm-vt8500.c
index 5472051..30def61 100644
--- a/drivers/pwm/pwm-vt8500.c
+++ b/drivers/pwm/pwm-vt8500.c
@@ -218,7 +218,6 @@ static int vt8500_pwm_probe(struct platform_device *pdev)
chip->chip.dev = &pdev->dev;
chip->chip.ops = &vt8500_pwm_ops;
- chip->chip.of_xlate = of_pwm_xlate_with_flags;
chip->chip.base = -1;
chip->chip.npwm = VT8500_NR_PWMS;
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index f0feafd..2447d6f 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -188,9 +188,6 @@ struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip,
unsigned int index,
const char *label);
-struct pwm_device *of_pwm_xlate_with_flags(struct pwm_chip *pc,
- const struct of_phandle_args *args);
-
struct pwm_device *pwm_get(struct device *dev, const char *con_id);
struct pwm_device *of_pwm_get(struct device_node *np, const char *con_id);
void pwm_put(struct pwm_device *pwm);
--
1.8.5.2
^ permalink raw reply related
* [PATCH 1/2] PWM: let of_xlate handlers check args count
From: Sascha Hauer @ 2014-01-23 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390467898-9216-1-git-send-email-s.hauer@pengutronix.de>
of_pwm_n_cells for the of_xlate handler is stored in struct pwm_chip,
but it is only ever used by the of_xlate handler itsel. Remove
of_pwm_n_cells from struct pwm_chip and let the handler do the argument
count checking to simplify the code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/pwm/core.c | 15 +++------------
drivers/pwm/pwm-atmel-tcb.c | 1 -
drivers/pwm/pwm-renesas-tpu.c | 1 -
drivers/pwm/pwm-samsung.c | 1 -
drivers/pwm/pwm-tiecap.c | 1 -
drivers/pwm/pwm-tiehrpwm.c | 1 -
drivers/pwm/pwm-vt8500.c | 1 -
7 files changed, 3 insertions(+), 18 deletions(-)
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 2ca9504..c882051 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -136,7 +136,7 @@ of_pwm_xlate_with_flags(struct pwm_chip *pc, const struct of_phandle_args *args)
{
struct pwm_device *pwm;
- if (pc->of_pwm_n_cells < 3)
+ if (args->args_count != 3)
return ERR_PTR(-EINVAL);
if (args->args[0] >= pc->npwm)
@@ -162,7 +162,7 @@ of_pwm_simple_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
{
struct pwm_device *pwm;
- if (pc->of_pwm_n_cells < 2)
+ if (args->args_count != 2)
return ERR_PTR(-EINVAL);
if (args->args[0] >= pc->npwm)
@@ -182,10 +182,8 @@ static void of_pwmchip_add(struct pwm_chip *chip)
if (!chip->dev || !chip->dev->of_node)
return;
- if (!chip->of_xlate) {
+ if (!chip->of_xlate)
chip->of_xlate = of_pwm_simple_xlate;
- chip->of_pwm_n_cells = 2;
- }
of_node_get(chip->dev->of_node);
}
@@ -536,13 +534,6 @@ struct pwm_device *of_pwm_get(struct device_node *np, const char *con_id)
goto put;
}
- if (args.args_count != pc->of_pwm_n_cells) {
- pr_debug("%s: wrong #pwm-cells for %s\n", np->full_name,
- args.np->full_name);
- pwm = ERR_PTR(-EINVAL);
- goto put;
- }
-
pwm = pc->of_xlate(pc, &args);
if (IS_ERR(pwm))
goto put;
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
index f3dcd02..55fabf8 100644
--- a/drivers/pwm/pwm-atmel-tcb.c
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -395,7 +395,6 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)
tcbpwm->chip.dev = &pdev->dev;
tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags;
- tcbpwm->chip.of_pwm_n_cells = 3;
tcbpwm->chip.base = -1;
tcbpwm->chip.npwm = NPWM;
tcbpwm->tc = tc;
diff --git a/drivers/pwm/pwm-renesas-tpu.c b/drivers/pwm/pwm-renesas-tpu.c
index aff6ba9..0a8adb6 100644
--- a/drivers/pwm/pwm-renesas-tpu.c
+++ b/drivers/pwm/pwm-renesas-tpu.c
@@ -434,7 +434,6 @@ static int tpu_probe(struct platform_device *pdev)
tpu->chip.dev = &pdev->dev;
tpu->chip.ops = &tpu_pwm_ops;
tpu->chip.of_xlate = of_pwm_xlate_with_flags;
- tpu->chip.of_pwm_n_cells = 3;
tpu->chip.base = -1;
tpu->chip.npwm = TPU_CHANNEL_MAX;
diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c
index b59639e..8d8dced 100644
--- a/drivers/pwm/pwm-samsung.c
+++ b/drivers/pwm/pwm-samsung.c
@@ -487,7 +487,6 @@ static int pwm_samsung_probe(struct platform_device *pdev)
return ret;
chip->chip.of_xlate = of_pwm_xlate_with_flags;
- chip->chip.of_pwm_n_cells = 3;
} else {
if (!pdev->dev.platform_data) {
dev_err(&pdev->dev, "no platform data specified\n");
diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
index 4e5c3d1..4d7a01a 100644
--- a/drivers/pwm/pwm-tiecap.c
+++ b/drivers/pwm/pwm-tiecap.c
@@ -229,7 +229,6 @@ static int ecap_pwm_probe(struct platform_device *pdev)
pc->chip.dev = &pdev->dev;
pc->chip.ops = &ecap_pwm_ops;
pc->chip.of_xlate = of_pwm_xlate_with_flags;
- pc->chip.of_pwm_n_cells = 3;
pc->chip.base = -1;
pc->chip.npwm = 1;
diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index a4d8f51..2c2621a 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -460,7 +460,6 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev)
pc->chip.dev = &pdev->dev;
pc->chip.ops = &ehrpwm_pwm_ops;
pc->chip.of_xlate = of_pwm_xlate_with_flags;
- pc->chip.of_pwm_n_cells = 3;
pc->chip.base = -1;
pc->chip.npwm = NUM_PWM_CHANNEL;
diff --git a/drivers/pwm/pwm-vt8500.c b/drivers/pwm/pwm-vt8500.c
index 323125a..5472051 100644
--- a/drivers/pwm/pwm-vt8500.c
+++ b/drivers/pwm/pwm-vt8500.c
@@ -219,7 +219,6 @@ static int vt8500_pwm_probe(struct platform_device *pdev)
chip->chip.dev = &pdev->dev;
chip->chip.ops = &vt8500_pwm_ops;
chip->chip.of_xlate = of_pwm_xlate_with_flags;
- chip->chip.of_pwm_n_cells = 3;
chip->chip.base = -1;
chip->chip.npwm = VT8500_NR_PWMS;
--
1.8.5.2
^ permalink raw reply related
* [PATCHv2 2/2] pwm: imx: support polarity inversion
From: Sascha Hauer @ 2014-01-23 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140123083714.3c6e86ae@ipc1.ka-ro>
I thinking more of the following. I haven't tested it, but it has a negative
diffstat, so it must be good ;)
Sascha
----------------------------------------------------------------
Sascha Hauer (2):
PWM: let of_xlate handlers check args count
PWM: handle additional flags in of_pwm_simple_xlate
drivers/pwm/core.c | 41 +++++++----------------------------------
drivers/pwm/pwm-atmel-tcb.c | 2 --
drivers/pwm/pwm-renesas-tpu.c | 2 --
drivers/pwm/pwm-samsung.c | 3 ---
drivers/pwm/pwm-tiecap.c | 2 --
drivers/pwm/pwm-tiehrpwm.c | 2 --
drivers/pwm/pwm-vt8500.c | 2 --
include/linux/pwm.h | 3 ---
8 files changed, 7 insertions(+), 50 deletions(-)
^ permalink raw reply
* [PATCH 2/2] clocksource: Make clocksource register functions void
From: Yijing Wang @ 2014-01-23 9:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E0D575.5050702@linaro.org>
On 2014/1/23 16:40, Daniel Lezcano wrote:
> On 01/23/2014 08:12 AM, Yijing Wang wrote:
>> Currently, clocksource_register() and __clocksource_register_scale()
>> functions always return 0, it's pointless, make functions void.
>> And remove the dead code that check the clocksource_register_hz()
>> return value.
>>
>> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
>
> Well, do we really want to change all these files to not take care of a return value ? What about is we have to check it again later ?
>
> I would recommend to investigate __clocksource_register_scale and the underneath functions if there is not an error to be returned in the call stack somewhere which is ignored today.
>
> The same applies for clocksource_register.
Hi Daniel, thanks for your comment, all functions type under __clocksource_register_scale() are void.
This just is trivial cleanup patch, I don't know whether we will check these function return value again later.
If there is some possibility to check it again, I agree to keep them. Of course, this is all determined by Thomas.
Thanks!
Yijing.
>
>> ---
>> arch/arm/mach-davinci/time.c | 5 ++---
>> arch/arm/mach-msm/timer.c | 4 +---
>> arch/arm/mach-omap2/timer.c | 8 +++-----
>> arch/avr32/kernel/time.c | 4 +---
>> arch/blackfin/kernel/time-ts.c | 6 ++----
>> arch/microblaze/kernel/timer.c | 3 +--
>> arch/mips/jz4740/time.c | 6 +-----
>> arch/mips/loongson/common/cs5536/cs5536_mfgpt.c | 3 ++-
>> arch/openrisc/kernel/time.c | 3 +--
>> arch/powerpc/kernel/time.c | 6 +-----
>> arch/um/kernel/time.c | 6 +-----
>> arch/x86/platform/uv/uv_time.c | 14 ++++++--------
>> drivers/clocksource/acpi_pm.c | 3 ++-
>> drivers/clocksource/cadence_ttc_timer.c | 6 +-----
>> drivers/clocksource/exynos_mct.c | 4 +---
>> drivers/clocksource/i8253.c | 3 ++-
>> drivers/clocksource/mmio.c | 3 ++-
>> drivers/clocksource/samsung_pwm_timer.c | 5 +----
>> drivers/clocksource/scx200_hrt.c | 3 ++-
>> drivers/clocksource/tcb_clksrc.c | 8 +-------
>> drivers/clocksource/timer-marco.c | 2 +-
>> drivers/clocksource/timer-prima2.c | 2 +-
>> drivers/clocksource/vt8500_timer.c | 4 +---
>> include/linux/clocksource.h | 8 ++++----
>> kernel/time/clocksource.c | 6 ++----
>> kernel/time/jiffies.c | 3 ++-
>> 26 files changed, 45 insertions(+), 83 deletions(-)
>>
>> diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
>> index 56c6eb5..9536f85 100644
>> --- a/arch/arm/mach-davinci/time.c
>> +++ b/arch/arm/mach-davinci/time.c
>> @@ -387,9 +387,8 @@ void __init davinci_timer_init(void)
>>
>> /* setup clocksource */
>> clocksource_davinci.name = id_to_name[clocksource_id];
>> - if (clocksource_register_hz(&clocksource_davinci,
>> - davinci_clock_tick_rate))
>> - printk(err, clocksource_davinci.name);
>> + clocksource_register_hz(&clocksource_davinci,
>> + davinci_clock_tick_rate);
>>
>> setup_sched_clock(davinci_read_sched_clock, 32,
>> davinci_clock_tick_rate);
>> diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
>> index 1e9c338..c96e034 100644
>> --- a/arch/arm/mach-msm/timer.c
>> +++ b/arch/arm/mach-msm/timer.c
>> @@ -226,9 +226,7 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
>>
>> err:
>> writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
>> - res = clocksource_register_hz(cs, dgt_hz);
>> - if (res)
>> - pr_err("clocksource_register failed\n");
>> + clocksource_register_hz(cs, dgt_hz);
>> setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
>> }
>>
>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>> index 3ca81e0..beaf7c7 100644
>> --- a/arch/arm/mach-omap2/timer.c
>> +++ b/arch/arm/mach-omap2/timer.c
>> @@ -473,11 +473,9 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
>> OMAP_TIMER_NONPOSTED);
>> setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
>>
>> - if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
>> - pr_err("Could not register clocksource %s\n",
>> - clocksource_gpt.name);
>> - else
>> - pr_info("OMAP clocksource: %s at %lu Hz\n",
>> + clocksource_register_hz(&clocksource_gpt, clksrc.rate);
>> +
>> + pr_info("OMAP clocksource: %s at %lu Hz\n",
>> clocksource_gpt.name, clksrc.rate);
>> }
>>
>> diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
>> index d0f771b..51b4a66 100644
>> --- a/arch/avr32/kernel/time.c
>> +++ b/arch/avr32/kernel/time.c
>> @@ -134,9 +134,7 @@ void __init time_init(void)
>>
>> /* figure rate for counter */
>> counter_hz = clk_get_rate(boot_cpu_data.clk);
>> - ret = clocksource_register_hz(&counter, counter_hz);
>> - if (ret)
>> - pr_debug("timer: could not register clocksource: %d\n", ret);
>> + clocksource_register_hz(&counter, counter_hz);
>>
>> /* setup COMPARE clockevent */
>> comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
>> diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
>> index cb0a484..df3bb08 100644
>> --- a/arch/blackfin/kernel/time-ts.c
>> +++ b/arch/blackfin/kernel/time-ts.c
>> @@ -51,8 +51,7 @@ static inline unsigned long long bfin_cs_cycles_sched_clock(void)
>>
>> static int __init bfin_cs_cycles_init(void)
>> {
>> - if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
>> - panic("failed to register clocksource");
>> + clocksource_register_hz(&bfin_cs_cycles, get_cclk());
>>
>> return 0;
>> }
>> @@ -103,8 +102,7 @@ static int __init bfin_cs_gptimer0_init(void)
>> {
>> setup_gptimer0();
>>
>> - if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
>> - panic("failed to register clocksource");
>> + clocksource_register_hz(&bfin_cs_gptimer0, get_sclk());
>>
>> return 0;
>> }
>> diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
>> index 3e39b10..6a2417e 100644
>> --- a/arch/microblaze/kernel/timer.c
>> +++ b/arch/microblaze/kernel/timer.c
>> @@ -208,8 +208,7 @@ static struct clocksource clocksource_microblaze = {
>>
>> static int __init xilinx_clocksource_init(void)
>> {
>> - if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq))
>> - panic("failed to register clocksource");
>> + clocksource_register_hz(&clocksource_microblaze, timer_clock_freq);
>>
>> /* stop timer1 */
>> out_be32(timer_baseaddr + TCSR1,
>> diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
>> index 5e430ce..041cdff 100644
>> --- a/arch/mips/jz4740/time.c
>> +++ b/arch/mips/jz4740/time.c
>> @@ -105,7 +105,6 @@ static struct irqaction timer_irqaction = {
>>
>> void __init plat_time_init(void)
>> {
>> - int ret;
>> uint32_t clk_rate;
>> uint16_t ctrl;
>>
>> @@ -121,10 +120,7 @@ void __init plat_time_init(void)
>>
>> clockevents_register_device(&jz4740_clockevent);
>>
>> - ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
>> -
>> - if (ret)
>> - printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
>> + clocksource_register_hz(&jz4740_clocksource, clk_rate);
>>
>> setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
>>
>> diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
>> index c639b9d..9fa6d99 100644
>> --- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
>> +++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
>> @@ -208,7 +208,8 @@ int __init init_mfgpt_clocksource(void)
>> if (num_possible_cpus() > 1) /* MFGPT does not scale! */
>> return 0;
>>
>> - return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
>> + clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
>> + return 0;
>> }
>>
>> arch_initcall(init_mfgpt_clocksource);
>> diff --git a/arch/openrisc/kernel/time.c b/arch/openrisc/kernel/time.c
>> index 7c52e94..3f789aa 100644
>> --- a/arch/openrisc/kernel/time.c
>> +++ b/arch/openrisc/kernel/time.c
>> @@ -156,8 +156,7 @@ static struct clocksource openrisc_timer = {
>>
>> static int __init openrisc_timer_init(void)
>> {
>> - if (clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency))
>> - panic("failed to register clocksource");
>> + clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency);
>>
>> /* Enable the incrementer: 'continuous' mode with interrupt disabled */
>> mtspr(SPR_TTMR, SPR_TTMR_CR);
>> diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
>> index b3b1441..27c0627 100644
>> --- a/arch/powerpc/kernel/time.c
>> +++ b/arch/powerpc/kernel/time.c
>> @@ -788,11 +788,7 @@ static void __init clocksource_init(void)
>> else
>> clock = &clocksource_timebase;
>>
>> - if (clocksource_register_hz(clock, tb_ticks_per_sec)) {
>> - printk(KERN_ERR "clocksource: %s is already registered\n",
>> - clock->name);
>> - return;
>> - }
>> + clocksource_register_hz(clock, tb_ticks_per_sec);
>>
>> printk(KERN_INFO "clocksource: %s mult[%x] shift[%d] registered\n",
>> clock->name, clock->mult, clock->shift);
>> diff --git a/arch/um/kernel/time.c b/arch/um/kernel/time.c
>> index 117568d..2034b58 100644
>> --- a/arch/um/kernel/time.c
>> +++ b/arch/um/kernel/time.c
>> @@ -92,11 +92,7 @@ static void __init setup_itimer(void)
>> clockevent_delta2ns(60 * HZ, &itimer_clockevent);
>> itimer_clockevent.min_delta_ns =
>> clockevent_delta2ns(1, &itimer_clockevent);
>> - err = clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC);
>> - if (err) {
>> - printk(KERN_ERR "clocksource_register_hz returned %d\n", err);
>> - return;
>> - }
>> + clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC);
>> clockevents_register_device(&itimer_clockevent);
>> }
>>
>> diff --git a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c
>> index 5c86786..b963774 100644
>> --- a/arch/x86/platform/uv/uv_time.c
>> +++ b/arch/x86/platform/uv/uv_time.c
>> @@ -379,15 +379,13 @@ static __init int uv_rtc_setup_clock(void)
>> if (!is_uv_system())
>> return -ENODEV;
>>
>> - rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
>> - if (rc)
>> - printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
>> - else
>> - printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
>> - sn_rtc_cycles_per_second/(unsigned long)1E6);
>> + clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
>> +
>> + pr_info("UV RTC clocksource registered freq %lu MHz\n",
>> + sn_rtc_cycles_per_second/(unsigned long)1E6);
>>
>> - if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
>> - return rc;
>> + if (!uv_rtc_evt_enable || x86_platform_ipi_callback)
>> + return 0;
>>
>> /* Setup and register clockevents */
>> rc = uv_rtc_allocate_timers();
>> diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c
>> index 6eab889..ab1dc63 100644
>> --- a/drivers/clocksource/acpi_pm.c
>> +++ b/drivers/clocksource/acpi_pm.c
>> @@ -218,8 +218,9 @@ static int __init init_acpi_pm_clocksource(void)
>> return -ENODEV;
>> }
>>
>> - return clocksource_register_hz(&clocksource_acpi_pm,
>> + clocksource_register_hz(&clocksource_acpi_pm,
>> PMTMR_TICKS_PER_SEC);
>> + return 0;
>> }
>>
>> /* We use fs_initcall because we want the PCI fixups to have run
>> diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
>> index 63f176d..b9b56ed 100644
>> --- a/drivers/clocksource/cadence_ttc_timer.c
>> +++ b/drivers/clocksource/cadence_ttc_timer.c
>> @@ -301,11 +301,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
>> __raw_writel(CNT_CNTRL_RESET,
>> ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
>>
>> - err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
>> - if (WARN_ON(err)) {
>> - kfree(ttccs);
>> - return;
>> - }
>> + clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
>>
>> ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
>> sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
>> diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
>> index 62b0de6..98649c7 100644
>> --- a/drivers/clocksource/exynos_mct.c
>> +++ b/drivers/clocksource/exynos_mct.c
>> @@ -193,9 +193,7 @@ struct clocksource mct_frc = {
>> static void __init exynos4_clocksource_init(void)
>> {
>> exynos4_mct_frc_start(0, 0);
>> -
>> - if (clocksource_register_hz(&mct_frc, clk_rate))
>> - panic("%s: can't register clocksource\n", mct_frc.name);
>> + clocksource_register_hz(&mct_frc, clk_rate);
>> }
>>
>> static void exynos4_mct_comp0_stop(void)
>> diff --git a/drivers/clocksource/i8253.c b/drivers/clocksource/i8253.c
>> index 14ee3ef..9c45f0a 100644
>> --- a/drivers/clocksource/i8253.c
>> +++ b/drivers/clocksource/i8253.c
>> @@ -95,7 +95,8 @@ static struct clocksource i8253_cs = {
>>
>> int __init clocksource_i8253_init(void)
>> {
>> - return clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
>> + clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
>> + return 0;
>> }
>> #endif
>>
>> diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c
>> index c0e2512..6e0b530 100644
>> --- a/drivers/clocksource/mmio.c
>> +++ b/drivers/clocksource/mmio.c
>> @@ -69,5 +69,6 @@ int __init clocksource_mmio_init(void __iomem *base, const char *name,
>> cs->clksrc.mask = CLOCKSOURCE_MASK(bits);
>> cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
>>
>> - return clocksource_register_hz(&cs->clksrc, hz);
>> + clocksource_register_hz(&cs->clksrc, hz);
>> + return 0;
>> }
>> diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
>> index 5645cfc..c59292f 100644
>> --- a/drivers/clocksource/samsung_pwm_timer.c
>> +++ b/drivers/clocksource/samsung_pwm_timer.c
>> @@ -340,7 +340,6 @@ static void __init samsung_clocksource_init(void)
>> {
>> unsigned long pclk;
>> unsigned long clock_rate;
>> - int ret;
>>
>> pclk = clk_get_rate(pwm.timerclk);
>>
>> @@ -361,9 +360,7 @@ static void __init samsung_clocksource_init(void)
>> pwm.variant.bits, clock_rate);
>>
>> samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
>> - ret = clocksource_register_hz(&samsung_clocksource, clock_rate);
>> - if (ret)
>> - panic("samsung_clocksource_timer: can't register clocksource\n");
>> + clocksource_register_hz(&samsung_clocksource, clock_rate);
>> }
>>
>> static void __init samsung_timer_resources(void)
>> diff --git a/drivers/clocksource/scx200_hrt.c b/drivers/clocksource/scx200_hrt.c
>> index 64f9e82..57bdc04 100644
>> --- a/drivers/clocksource/scx200_hrt.c
>> +++ b/drivers/clocksource/scx200_hrt.c
>> @@ -83,7 +83,8 @@ static int __init init_hrt_clocksource(void)
>>
>> pr_info("enabling scx200 high-res timer (%s MHz +%d ppm)\n", mhz27 ? "27":"1", ppm);
>>
>> - return clocksource_register_hz(&cs_hrt, freq);
>> + clocksource_register_hz(&cs_hrt, freq);
>> + return 0;
>> }
>>
>> module_init(init_hrt_clocksource);
>> diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
>> index 00fdd11..805245d 100644
>> --- a/drivers/clocksource/tcb_clksrc.c
>> +++ b/drivers/clocksource/tcb_clksrc.c
>> @@ -340,9 +340,7 @@ static int __init tcb_clksrc_init(void)
>> }
>>
>> /* and away we go! */
>> - ret = clocksource_register_hz(&clksrc, divided_rate);
>> - if (ret)
>> - goto err_disable_t1;
>> + clocksource_register_hz(&clksrc, divided_rate);
>>
>> /* channel 2: periodic and oneshot timer support */
>> ret = setup_clkevents(tc, clk32k_divisor_idx);
>> @@ -354,10 +352,6 @@ static int __init tcb_clksrc_init(void)
>> err_unregister_clksrc:
>> clocksource_unregister(&clksrc);
>>
>> -err_disable_t1:
>> - if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
>> - clk_disable_unprepare(tc->clk[1]);
>> -
>> err_disable_t0:
>> clk_disable_unprepare(t0_clk);
>>
>> diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
>> index 09a17d9..ae78ce0 100644
>> --- a/drivers/clocksource/timer-marco.c
>> +++ b/drivers/clocksource/timer-marco.c
>> @@ -283,7 +283,7 @@ static void __init sirfsoc_marco_timer_init(void)
>> /* Clear all interrupts */
>> writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
>>
>> - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
>> + clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE);
>>
>> sirfsoc_clockevent_init();
>> }
>> diff --git a/drivers/clocksource/timer-prima2.c b/drivers/clocksource/timer-prima2.c
>> index 8a492d3..c9cc307 100644
>> --- a/drivers/clocksource/timer-prima2.c
>> +++ b/drivers/clocksource/timer-prima2.c
>> @@ -204,7 +204,7 @@ static void __init sirfsoc_prima2_timer_init(struct device_node *np)
>> writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
>> writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
>>
>> - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
>> + clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE);
>>
>> sched_clock_register(sirfsoc_read_sched_clock, 64, CLOCK_TICK_RATE);
>>
>> diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c
>> index 1098ed3..13f5fa4 100644
>> --- a/drivers/clocksource/vt8500_timer.c
>> +++ b/drivers/clocksource/vt8500_timer.c
>> @@ -150,9 +150,7 @@ static void __init vt8500_timer_init(struct device_node *np)
>> writel(0xf, regbase + TIMER_STATUS_VAL);
>> writel(~0, regbase + TIMER_MATCH_VAL);
>>
>> - if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
>> - pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
>> - __func__, clocksource.name);
>> + clocksource_register_hz(&clocksource, VT8500_TIMER_HZ);
>>
>> clockevent.cpumask = cpumask_of(0);
>>
>> diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
>> index 67301a4..5a17c5e 100644
>> --- a/include/linux/clocksource.h
>> +++ b/include/linux/clocksource.h
>> @@ -282,7 +282,7 @@ static inline s64 clocksource_cyc2ns(cycle_t cycles, u32 mult, u32 shift)
>> }
>>
>>
>> -extern int clocksource_register(struct clocksource*);
>> +extern void clocksource_register(struct clocksource *);
>> extern int clocksource_unregister(struct clocksource*);
>> extern void clocksource_touch_watchdog(void);
>> extern struct clocksource* clocksource_get_next(void);
>> @@ -301,17 +301,17 @@ clocks_calc_mult_shift(u32 *mult, u32 *shift, u32 from, u32 to, u32 minsec);
>> * Don't call __clocksource_register_scale directly, use
>> * clocksource_register_hz/khz
>> */
>> -extern int
>> +extern void
>> __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq);
>> extern void
>> __clocksource_updatefreq_scale(struct clocksource *cs, u32 scale, u32 freq);
>>
>> -static inline int clocksource_register_hz(struct clocksource *cs, u32 hz)
>> +static inline void clocksource_register_hz(struct clocksource *cs, u32 hz)
>> {
>> return __clocksource_register_scale(cs, 1, hz);
>> }
>>
>> -static inline int clocksource_register_khz(struct clocksource *cs, u32 khz)
>> +static inline void clocksource_register_khz(struct clocksource *cs, u32 khz)
>> {
>> return __clocksource_register_scale(cs, 1000, khz);
>> }
>> diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c
>> index 9951575..686ff72 100644
>> --- a/kernel/time/clocksource.c
>> +++ b/kernel/time/clocksource.c
>> @@ -782,7 +782,7 @@ EXPORT_SYMBOL_GPL(__clocksource_updatefreq_scale);
>> * This *SHOULD NOT* be called directly! Please use the
>> * clocksource_register_hz() or clocksource_register_khz helper functions.
>> */
>> -int __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq)
>> +void __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq)
>> {
>>
>> /* Initialize mult/shift and max_idle_ns */
>> @@ -794,7 +794,6 @@ int __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq)
>> clocksource_enqueue_watchdog(cs);
>> clocksource_select();
>> mutex_unlock(&clocksource_mutex);
>> - return 0;
>> }
>> EXPORT_SYMBOL_GPL(__clocksource_register_scale);
>>
>> @@ -804,7 +803,7 @@ EXPORT_SYMBOL_GPL(__clocksource_register_scale);
>> * @cs: clocksource to be registered
>> *
>> */
>> -int clocksource_register(struct clocksource *cs)
>> +void clocksource_register(struct clocksource *cs)
>> {
>> /* calculate max adjustment for given mult/shift */
>> cs->maxadj = clocksource_max_adjustment(cs);
>> @@ -820,7 +819,6 @@ int clocksource_register(struct clocksource *cs)
>> clocksource_enqueue_watchdog(cs);
>> clocksource_select();
>> mutex_unlock(&clocksource_mutex);
>> - return 0;
>> }
>> EXPORT_SYMBOL(clocksource_register);
>>
>> diff --git a/kernel/time/jiffies.c b/kernel/time/jiffies.c
>> index 7a925ba..ae4c534 100644
>> --- a/kernel/time/jiffies.c
>> +++ b/kernel/time/jiffies.c
>> @@ -88,7 +88,8 @@ EXPORT_SYMBOL(jiffies);
>>
>> static int __init init_jiffies_clocksource(void)
>> {
>> - return clocksource_register(&clocksource_jiffies);
>> + clocksource_register(&clocksource_jiffies);
>> + return 0;
>> }
>>
>> core_initcall(init_jiffies_clocksource);
>>
>
>
--
Thanks!
Yijing
^ permalink raw reply
* [PATCH] vt8500: pinctrl: Change devicetree data parsing
From: Tony Prisk @ 2014-01-23 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdaFJphJdf6hyKoYEZ_wXikwRiwzMgtL=hY+3B8WrBnQaw@mail.gmail.com>
On 23/01/14 21:43, Linus Walleij wrote:
> On Thu, Jan 23, 2014 at 7:31 AM, Tony Prisk <linux@prisktech.co.nz> wrote:
>
>> Due to an assumption in the VT8500 pinctrl driver, the value passed
>> from devicetree for 'wm,pull' was not explicitly translated before
>> being passed to pinconf.
>>
>> With changes to 'enum pin_config_param', PIN_CONFIG_BIAS_PULL_(UP/DOWN)
>> no longer map 1-to-1 with the expected values in devicetree.
>>
>> This patch adds a small translation between the devicetree values (0..2)
>> and the enum pin_config_param equivalent values.
>>
>> Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
> Isn't this a regression fix for stable?
>
I wasn't sure how to handle this since it's been a problem since 3.10
but no one has mentioned it (or patched it).
I assume this is because:
a) pinctrl is only used for I2C in mainline - and there is no mainline
I2C consumer device drivers for the WonderMedia devices
b) most users are using the non-mainline kernel which has more support
(as nasty as some of it is).
Regards
Tony Prisk
^ permalink raw reply
* [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
From: Michal Simek @ 2014-01-23 8:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201401171804.30572.arnd@arndb.de>
On 01/17/2014 06:04 PM, Arnd Bergmann wrote:
> On Thursday 16 January 2014, Mark Brown wrote:
>> On Thu, Jan 16, 2014 at 12:19:00PM +0100, Arnd Bergmann wrote:
>>
>>> 1. Other platforms also require the syscon driver to be active before
>>> the regular device driver probing starts. Michal Simek has the same
>>> issue in the zynq clock driver that you have for SMP initialization.
>>> We have talked about this with Mark Brown already, and I think we will
>>> find a solution for this in the end, but it's not as straightforward
>>> as I first hoped. We can probably use help in this area.
>>
>> I thought the solution with deferring registration of the resource for
>> dev_get_regmap() until a proper device materialised seemed simple and
>> enough, did you folks run into any problems with that? I had assumed a
>> patch was likely to materialise so wasn't worrying about it myself.
>
> I'm still hoping that Michal will do that patch.
And what was the resolution/recommendation how to do it?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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