* [PATCH v5 14/14] ARM: sun7i: dts: Add ahci / sata support
From: Hans de Goede @ 2014-02-03 22:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140131134638.GH2950@lukather>
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Hi,
On 01/31/2014 02:46 PM, Maxime Ripard wrote:
> On Wed, Jan 22, 2014 at 08:04:49PM +0100, Hans de Goede wrote:
>> This patch adds sunxi sata support to A20 boards that have such a connector. Some boards also feature a regulator via a GPIO and support for this is also added.
>>
>> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 6 ++++++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 20 ++++++++++++++++++++ arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 6 ++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 4 files changed, 40 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 48777cd..1cab521 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -13,6 +13,7 @@
>>
>> /dts-v1/; /include/ "sun7i-a20.dtsi" +/include/ "sunxi-ahci-reg.dtsi"
>>
>> / { model = "Cubietech Cubieboard2"; @@ -28,6 +29,11 @@ status = "okay"; };
>>
>> + ahci: sata at 01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + pinctrl at 01c20800 { mmc0_cd_pin_cubieboard2: mmc0_cd_pin at 0 { allwinner,pins = "PH1"; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 2684f27..1247ea1 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -13,6 +13,7 @@
>>
>> /dts-v1/; /include/ "sun7i-a20.dtsi" +/include/ "sunxi-ahci-reg.dtsi"
>>
>> / { model = "Cubietech Cubietruck"; @@ -28,6 +29,11 @@ status = "okay"; };
>>
>> + ahci: sata at 01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + pinctrl at 01c20800 { mmc0_cd_pin_cubietruck: mmc0_cd_pin at 0 { allwinner,pins = "PH1"; @@ -36,6 +42,13 @@ allwinner,pull = <0>; };
>>
>> + ahci_pwr_pin_cubietruck: ahci_pwr_pin at 1 { + allwinner,pins = "PH12"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + led_pins_cubietruck: led_pins at 0 { allwinner,pins = "PH7", "PH11", "PH20", "PH21"; allwinner,function = "gpio_out"; @@ -84,4 +97,11 @@ gpios = <&pio 7 7 0>; }; }; + + regulators { + reg_ahci_5v: ahci-5v { + pinctrl-0 = <&ahci_pwr_pin_cubietruck>; + gpio = <&pio 7 12 0>; + }; + }; }; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index
>> bf6f6c8..f135886 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -13,6 +13,7 @@
>>
>> /dts-v1/; /include/ "sun7i-a20.dtsi" +/include/ "sunxi-ahci-reg.dtsi"
>>
>> / { model = "Olimex A20-Olinuxino Micro"; @@ -37,6 +38,11 @@ status = "okay"; };
>>
>> + ahci: sata at 01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + pinctrl at 01c20800 { mmc0_cd_pin_olinuxinom: mmc0_cd_pin at 0 { allwinner,pins = "PH1"; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index c9c123a..0657bad 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -347,6 +347,14 @@ status = "disabled"; };
>>
>> + ahci: sata at 01c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <0 56 1>;
>
> This is supposed to be a level triggered interrupt, not an edge triggered one.
Good catch, will fix for the next version.
Regards,
Hans
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^ permalink raw reply
* [PATCH RFC v4 00/10] ahci: library-ise ahci_platform, add sunxi driver and cleanup imx driver
From: Hans de Goede @ 2014-02-03 22:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqKnus+9rgLAQ990eD-1F6-2G-SuqYuPkmc+Tw6QP1CT4g@mail.gmail.com>
Hi,
On 02/03/2014 05:31 PM, Rob Herring wrote:
> On Mon, Jan 20, 2014 at 10:44 AM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi All,
>>
>> Here is v4 of my patchset for adding ahci-sunxi support. It has grown quite
>> a bit since I've been going for a more generic approach this time and I've
>> also cleaned up the ahci-imx driver to use the same generic approach.
>
> I don't know if you missed it or just don't intend to refactor all
> AHCI drivers, but the highbank driver could benefit from this as well.
I don't intend to refactor all of them, esp. not the ones for which I don't
have hardware to test.
As they say: patches welcome :)
Regards,
Hans
^ permalink raw reply
* [PATCH v5 00/14] ahci: library-ise ahci_platform, add sunxi driver and cleanup imx driver
From: Hans de Goede @ 2014-02-03 22:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140203160936.GC30250@htj.dyndns.org>
Hi,
On 02/03/2014 05:09 PM, Tejun Heo wrote:
> Hello,
>
> On Wed, Jan 22, 2014 at 08:04:35PM +0100, Hans de Goede wrote:
>> Here is v4 of my patchset for adding ahci-sunxi support. It has grown quite
>> a bit since I've been going for a more generic approach this time and I've
>> also cleaned up the ahci-imx driver to use the same generic approach.
>
> On top of which tree were these patches generated? They don't apply
> to 3.14-rc1.
They are on top of 3.13, I'll rebase them, address Maxime's review of
the dts bits and send a new version sometime during the next couple of days.
Thanks,
Hans
^ permalink raw reply
* [PATCH] arm64: Add architecture support for PCI
From: Liviu Dudau @ 2014-02-03 21:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3808209.DeG1VobanZ@wuerfel>
On Mon, Feb 03, 2014 at 08:05:56PM +0000, Arnd Bergmann wrote:
> On Monday 03 February 2014 19:18:38 Liviu Dudau wrote:
> > On Mon, Feb 03, 2014 at 06:58:56PM +0000, Arnd Bergmann wrote:
> > > On Monday 03 February 2014 18:43:48 Liviu Dudau wrote:
> > > > diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
> > > > index 4cc813e..ce5bad2 100644
> > > > --- a/arch/arm64/include/asm/io.h
> > > > +++ b/arch/arm64/include/asm/io.h
> > > > @@ -120,9 +120,13 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
> > > > /*
> > > > * I/O port access primitives.
> > > > */
> > > > +#define arch_has_dev_port() (0)
> > >
> > > Why not?
> >
> > Maybe I got it the wrong way around, but the comment in include/linux/io.h says:
> >
> > /*
> > * Some systems do not have legacy ISA devices.
> > * /dev/port is not a valid interface on these systems.
> > * So for those archs, <asm/io.h> should define the following symbol.
> > */
> >
> > So ... defining it should mean no legacy ISA devices, right?
>
> I would read that comment as referring to systems that don't have
> any I/O space. If you have PCI, you can by definition have ISA
> compatible devices behind a bridge. A typical example would be
> a VGA card that supports the 03c0-03df port range.
But if you have PCI and don't want to support ISA do you have /dev/port? I guess yes.
In that case ISA support is irrelevant here. Will update the value when I send v2.
>
> > >
> > > > #define IO_SPACE_LIMIT 0xffff
> > >
> > > You probably want to increase this a bit, to allow multiple host bridges
> > > to have their own I/O space.
> >
> > OK, but to what size?
>
> 2 MB was a compromise on arm32 to allow up to 32 PCI host bridges but not
> take up too much virtual space. On arm64 it should be at least as big.
> Could be more than that, although I don't see a reason why it should be,
> unless we expect to see systems with tons of host bridges, or buses
> that exceed 64KB of I/O space.
I will increase the size to 2MB for v2.
>
> > > > +#define ioport_map(port, nr) (PCI_IOBASE + ((port) & IO_SPACE_LIMIT))
> > > > +#define ioport_unmap(addr)
> > >
> > > inline functions?
> >
> > Will do, thanks!
>
> I suppose you can actually use the generic implementation from
> asm-generic/io.h, and fix it by using the definition you have
> above, since it's currently broken.
Not exactly broken, but it makes the assumption that your IO space starts at
physical address zero and you have not remapped it. It does guard the
definition with #ifndef CONFIG_GENERIC_IOMAP after all, so it does not
expect to be generic :)
>
> > > > diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h
> > > > new file mode 100644
> > > > index 0000000..dd084a3
> > > > --- /dev/null
> > > > +++ b/arch/arm64/include/asm/pci.h
> > > > @@ -0,0 +1,35 @@
> > > > +#ifndef __ASM_PCI_H
> > > > +#define __ASM_PCI_H
> > > > +#ifdef __KERNEL__
> > > > +
> > > > +#include <linux/types.h>
> > > > +#include <linux/slab.h>
> > > > +#include <linux/dma-mapping.h>
> > > > +
> > > > +#include <asm/io.h>
> > > > +#include <asm-generic/pci-bridge.h>
> > > > +#include <asm-generic/pci-dma-compat.h>
> > > > +
> > > > +#define PCIBIOS_MIN_IO 0
> > > > +#define PCIBIOS_MIN_MEM 0
> > >
> > > PCIBIOS_MIN_IO is normally set to 0x1000, to stay out of the ISA range.
> >
> > :) No ISA support! (Die ISA, die!!)
>
> If only it were that easy.
Lets try! :)
I wonder how many active devices that have an ISA slot are still supported
by mainline kernel.
I will update PCIBIOS_MIN_xxxx to match arch/arm for v2.
>
> > > > diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
> > > > new file mode 100644
> > > > index 0000000..7b652cf
> > > > --- /dev/null
> > > > +++ b/arch/arm64/kernel/pci.c
> > > > @@ -0,0 +1,112 @@
> > >
> > > None of this looks really arm64 specific, nor should it be. I think
> > > we should try a little harder to move this as a default implementation
> > > into common code, even if we start out by having all architectures
> > > override it.
> >
> > Agree. This is the RFC version. I didn't dare to post a patch with fixes
> > for all architectures. :)
>
> No need to change the other architectures. You can make it opt-in for
> now and just put the code into a common location.
>
> An interesting question however is what the transition plan is to
> have the code shared between arm32 and arm64: We will certainly need
> to share at least the dw-pcie and the generic SBSA compliant pci
> implementation.
My vote would be for updating the host controllers to the new API and
to offer the CONFIG option to choose between arch APIs. The alternative
is to use the existing API to wrap the generic implementation.
My main concern with the existing API is the requirement to have a subsys_initcall
in your host bridge or mach code, due to the way the initialisation is done (you
need the DT code to probe your driver, but you cannot start the scanning of the
PCI bus until the arch code is initialised, so it gets deferred via
subsys_initcall when it calls pci_common_init). I bet that if one tries to
instantiate a Tegra PCI host bridge controller on a Marvell platform things will
break pretty quickly (random example here).
>
> > > > +int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
> > > > +{
> > > > + BUG_ON(offset + SZ_64K - 1 > IO_SPACE_LIMIT);
> > > > +
> > > > + return ioremap_page_range((unsigned long)PCI_IOBASE + offset,
> > > > + (unsigned long)PCI_IOBASE + offset + SZ_64K,
> > > > + phys_addr,
> > > > + __pgprot(PROT_DEVICE_nGnRE));
> > > > +}
> > >
> > > Not sure if we want to treat this one as architecture specific though.
> > > It certainly won't be portable to x86, but it could be shared with
> > > a couple of others. We may also want to redesign the interface.
> > > I've been thinking we could make this function allocate space in the
> > > Linux virtual I/O space aperture, and pass two resources into it
> > > (physical I/O aperture and bus I/O range), and get the actual
> > > io_offset as the return value, or a negative error number.
> >
> > Not sure I completely follow your idea.
>
> Something like this (coded in mail client, don't try to compile):
>
> #define IO_SPACE_PAGES (IO_SPACE_LIMIT + 1) / PAGE_SIZE)
> static DECLARE_BITMAP(pci_iospace, IO_SPACE_PAGES);
> unsigned long pci_ioremap_io(const struct resource *bus, const struct resource phys)
> {
> unsigned long start, len, virt_start;
> int error;
>
> /* use logical address == bus address if possible */
> start = bus->start / PAGE_SIZE;
> if (start > IO_SPACE_LIMIT / PAGE_SIZE)
> start = 0;
>
> /*
> * try finding free space for the whole size first,
> * fall back to 64K if not available
> */
> len = min(resource_size(bus), resource_size(phys);
> start = bitmap_find_next_zero_area(pci_iospace, IO_SPACE_PAGES,
> start, len / PAGE_SIZE, 0);
> if (start == IO_SPACE_PAGES && len > SZ_64K)
> len = SZ_64K;
> start = 0;
> start = bitmap_find_next_zero_area(pci_iospace, IO_SPACE_PAGES,
> start, len / PAGE_SIZE, 0);
> }
>
> /* no 64K area found */
> if (start == IO_SPACE_PAGES)
> return -ENOMEM;
>
> /* ioremap physical aperture to virtual aperture */
> virt_start = start * PAGE_SIZE + (unsigned long)PCI_IOBASE;
> error = ioremap_page_range(virt_start, virt_start + len,
> phys->start, __pgprot(PROT_DEVICE_nGnRE));
> if (error)
> return error;
>
> bitmap_set(start, len / PAGE_SIZE);
>
> /* return io_offset */
> return start * PAGE_SIZE - bus->start;
> }
> EXPORT_SYMBOL_GPL(pci_ioremap_io);
>
> Arnd
>
I see. I need to think how this will change the existing code. Current users of pci_ioremap_io
ask for multiples of SZ_64K offsets regardless of the actual need.
Best regards,
Liviu
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^ permalink raw reply
* [PATCH v6 8/8] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
From: Marc Carino @ 2014-02-03 21:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391463041-15241-1-git-send-email-marc.ceeeee@gmail.com>
Add a sample DTS which will allow bootup of a board populated
with the BCM7445 chip.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm7445.dts | 111 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 111 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/bcm7445.dts
diff --git a/arch/arm/boot/dts/bcm7445.dts b/arch/arm/boot/dts/bcm7445.dts
new file mode 100644
index 0000000..ffa3305
--- /dev/null
+++ b/arch/arm/boot/dts/bcm7445.dts
@@ -0,0 +1,111 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Broadcom STB (bcm7445)";
+ compatible = "brcm,bcm7445", "brcm,brcmstb";
+ interrupt-parent = <&gic>;
+
+ chosen {};
+
+ memory {
+ device_type = "memory";
+ reg = <0x00 0x00000000 0x00 0x40000000>,
+ <0x00 0x40000000 0x00 0x40000000>,
+ <0x00 0x80000000 0x00 0x40000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "brcm,brahma-b15";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu at 1 {
+ compatible = "brcm,brahma-b15";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu at 2 {
+ compatible = "brcm,brahma-b15";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu at 3 {
+ compatible = "brcm,brahma-b15";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ gic: interrupt-controller at ffd00000 {
+ compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
+ reg = <0x00 0xffd01000 0x00 0x1000>,
+ <0x00 0xffd02000 0x00 0x2000>,
+ <0x00 0xffd04000 0x00 0x2000>,
+ <0x00 0xffd06000 0x00 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ rdb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x00 0xf0000000 0x1000000>;
+
+ serial at 406b00 {
+ compatible = "ns16550a";
+ reg = <0x406b00 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <0 75 0x4>;
+ clock-frequency = <0x4d3f640>;
+ };
+
+ sun_top_ctrl: syscon at 404000 {
+ compatible = "brcm,bcm7445-sun-top-ctrl",
+ "syscon";
+ reg = <0x404000 0x51c>;
+ };
+
+ hif_cpubiuctrl: syscon at 3e2400 {
+ compatible = "brcm,bcm7445-hif-cpubiuctrl",
+ "syscon";
+ reg = <0x3e2400 0x5b4>;
+ };
+
+ hif_continuation: syscon at 452000 {
+ compatible = "brcm,bcm7445-hif-continuation",
+ "syscon";
+ reg = <0x452000 0x100>;
+ };
+ };
+
+ smpboot {
+ compatible = "brcm,brcmstb-smpboot";
+ syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
+ syscon-cont = <&hif_continuation>;
+ };
+
+ reboot {
+ compatible = "brcm,brcmstb-reboot";
+ syscon = <&sun_top_ctrl 0x304 0x308>;
+ };
+};
--
1.7.1
^ permalink raw reply related
* [PATCH v6 7/8] ARM: brcmstb: gic: add compatible string for Broadcom Brahma15
From: Marc Carino @ 2014-02-03 21:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391463041-15241-1-git-send-email-marc.ceeeee@gmail.com>
Document the Broadcom Brahma B15 GIC implementation as compatible
with the ARM GIC standard.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
Documentation/devicetree/bindings/arm/gic.txt | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index bae0d87..d1f0b98 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -16,6 +16,7 @@ Main node required properties:
"arm,cortex-a9-gic"
"arm,cortex-a7-gic"
"arm,arm11mp-gic"
+ "brcm,brahma-b15-gic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 3.
--
1.7.1
^ permalink raw reply related
* [PATCH v6 6/8] ARM: brcmstb: add misc. DT bindings for brcmstb
From: Marc Carino @ 2014-02-03 21:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391463041-15241-1-git-send-email-marc.ceeeee@gmail.com>
Document the bindings that the Broadcom STB platform needs
for proper bootup.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/arm/brcm-brcmstb.txt | 95 ++++++++++++++++++++
1 files changed, 95 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
diff --git a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
new file mode 100644
index 0000000..3c436cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
@@ -0,0 +1,95 @@
+ARM Broadcom STB platforms Device Tree Bindings
+-----------------------------------------------
+Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
+SoC shall have the following DT organization:
+
+Required root node properties:
+ - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
+
+example:
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Broadcom STB (bcm7445)";
+ compatible = "brcm,bcm7445", "brcm,brcmstb";
+
+Further, syscon nodes that map platform-specific registers used for general
+system control is required:
+
+ - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
+ - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
+ - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
+
+example:
+ rdb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x00 0xf0000000 0x1000000>;
+
+ sun_top_ctrl: syscon at 404000 {
+ compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
+ reg = <0x404000 0x51c>;
+ };
+
+ hif_cpubiuctrl: syscon at 3e2400 {
+ compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
+ reg = <0x3e2400 0x5b4>;
+ };
+
+ hif_continuation: syscon at 452000 {
+ compatible = "brcm,bcm7445-hif-continuation", "syscon";
+ reg = <0x452000 0x100>;
+ };
+ };
+
+Lastly, nodes that allow for support of SMP initialization and reboot are
+required:
+
+smpboot
+-------
+Required properties:
+
+ - compatible
+ The string "brcm,brcmstb-smpboot".
+
+ - syscon-cpu
+ A phandle / integer array property which lets the BSP know the location
+ of certain CPU power-on registers.
+
+ The layout of the property is as follows:
+ o a phandle to the "hif_cpubiuctrl" syscon node
+ o offset to the base CPU power zone register
+ o offset to the base CPU reset register
+
+ - syscon-cont
+ A phandle pointing to the syscon node which describes the CPU boot
+ continuation registers.
+ o a phandle to the "hif_continuation" syscon node
+
+example:
+ smpboot {
+ compatible = "brcm,brcmstb-smpboot";
+ syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
+ syscon-cont = <&hif_continuation>;
+ };
+
+reboot
+-------
+Required properties
+
+ - compatible
+ The string property "brcm,brcmstb-reboot".
+
+ - syscon
+ A phandle / integer array that points to the syscon node which describes
+ the general system reset registers.
+ o a phandle to "sun_top_ctrl"
+ o offset to the "reset source enable" register
+ o offset to the "software master reset" register
+
+example:
+ reboot {
+ compatible = "brcm,brcmstb-reboot";
+ syscon = <&sun_top_ctrl 0x304 0x308>;
+ };
--
1.7.1
^ permalink raw reply related
* [PATCH v6 5/8] ARM: brcmstb: add CPU binding for Broadcom Brahma15
From: Marc Carino @ 2014-02-03 21:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391463041-15241-1-git-send-email-marc.ceeeee@gmail.com>
Add the Broadcom Brahma B15 CPU to the DT CPU binding list.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..0cd1e25 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -163,6 +163,7 @@ nodes to be present and contain the properties described below.
"arm,cortex-r4"
"arm,cortex-r5"
"arm,cortex-r7"
+ "brcm,brahma-b15"
"faraday,fa526"
"intel,sa110"
"intel,sa1100"
--
1.7.1
^ permalink raw reply related
* [PATCH v6 4/8] ARM: do CPU-specific init for Broadcom Brahma15 cores
From: Marc Carino @ 2014-02-03 21:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391463041-15241-1-git-send-email-marc.ceeeee@gmail.com>
Perform any CPU-specific initialization required on the
Broadcom Brahma-15 core.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/mm/proc-v7.S | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index bd17819..98ea423 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -193,6 +193,7 @@ __v7_cr7mp_setup:
b 1f
__v7_ca7mp_setup:
__v7_ca15mp_setup:
+__v7_b15mp_setup:
mov r10, #0
1:
#ifdef CONFIG_SMP
@@ -494,6 +495,16 @@ __v7_ca15mp_proc_info:
.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
/*
+ * Broadcom Corporation Brahma-B15 processor.
+ */
+ .type __v7_b15mp_proc_info, #object
+__v7_b15mp_proc_info:
+ .long 0x420f00f0
+ .long 0xff0ffff0
+ __v7_proc __v7_b15mp_setup, hwcaps = HWCAP_IDIV
+ .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
+
+ /*
* Qualcomm Inc. Krait processors.
*/
.type __krait_proc_info, #object
--
1.7.1
^ permalink raw reply related
* [PATCH v6 3/8] ARM: brcmstb: add debug UART for earlyprintk support
From: Marc Carino @ 2014-02-03 21:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391463041-15241-1-git-send-email-marc.ceeeee@gmail.com>
Add the UART definitions needed to support earlyprintk on brcmstb machines.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/Kconfig.debug | 15 ++++++++++++++-
1 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 0531da8..5d7f76b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -125,6 +125,17 @@ choice
Say Y here if you want kernel low-level debugging support
on Marvell Berlin SoC based platforms.
+ config DEBUG_BRCMSTB_UART
+ bool "Use BRCMSTB UART for low-level debug"
+ depends on ARCH_BRCMSTB
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the first serial port on these devices.
+
+ If you have a Broadcom STB chip and would like early print
+ messages to appear over the UART, select this option.
+
config DEBUG_CLPS711X_UART1
bool "Kernel low-level debugging messages via UART1"
depends on ARCH_CLPS711X
@@ -1049,6 +1060,7 @@ config DEBUG_UART_PHYS
default 0xd4018000 if DEBUG_MMP_UART3
default 0xe0000000 if ARCH_SPEAR13XX
default 0xf0000be0 if ARCH_EBSA110
+ default 0xf0406b00 if DEBUG_BRCMSTB_UART
default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
ARCH_ORION5X
@@ -1083,6 +1095,7 @@ config DEBUG_UART_VIRT
default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
+ default 0xfc406b00 if DEBUG_BRCMSTB_UART
default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
default 0xfd000000 if ARCH_SPEAR13XX
default 0xfd012000 if ARCH_MV78XX0
@@ -1136,7 +1149,7 @@ config DEBUG_UART_8250_WORD
ARCH_KEYSTONE || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
- DEBUG_BCM_KONA_UART
+ DEBUG_BCM_KONA_UART || DEBUG_BRCMSTB_UART
config DEBUG_UART_8250_FLOW_CONTROL
bool "Enable flow control for 8250 UART"
--
1.7.1
^ permalink raw reply related
* [PATCH v6 2/8] power: reset: Add reboot driver for brcmstb
From: Marc Carino @ 2014-02-03 21:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391463041-15241-1-git-send-email-marc.ceeeee@gmail.com>
Add support for reboot functionality on boards with ARM-based
Broadcom STB chipsets.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
---
arch/arm/mach-bcm/Kconfig | 1 +
drivers/power/reset/Kconfig | 10 +++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/brcmstb-reboot.c | 120 ++++++++++++++++++++++++++++++++++
4 files changed, 132 insertions(+), 0 deletions(-)
create mode 100644 drivers/power/reset/brcmstb-reboot.c
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index f85e7bc..d8f6d7a 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -39,6 +39,7 @@ config ARCH_BRCMSTB
select MIGHT_HAVE_PCI
select HAVE_SMP
select HAVE_ARM_ARCH_TIMER
+ select POWER_RESET_BRCMSTB
help
Say Y if you intend to run the kernel on a Broadcom ARM-based STB
chipset.
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 6d452a7..c886505 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -12,6 +12,16 @@ config POWER_RESET_AS3722
help
This driver supports turning off board via a ams AS3722 power-off.
+config POWER_RESET_BRCMSTB
+ bool "Broadcom STB reset driver"
+ depends on POWER_RESET && ARCH_BRCMSTB
+ help
+ This driver provides restart support for ARM-based Broadcom STB
+ boards.
+
+ Say Y here if you have an ARM-based Broadcom STB board and you wish
+ to have restart support.
+
config POWER_RESET_GPIO
bool "GPIO power-off driver"
depends on OF_GPIO && POWER_RESET
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index a5b4a77..72bb94f 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
obj-$(CONFIG_POWER_RESET_XGENE) += xgene-reboot.o
+obj-$(CONFIG_POWER_RESET_BRCMSTB) += brcmstb-reboot.o
diff --git a/drivers/power/reset/brcmstb-reboot.c b/drivers/power/reset/brcmstb-reboot.c
new file mode 100644
index 0000000..3f23692
--- /dev/null
+++ b/drivers/power/reset/brcmstb-reboot.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+
+#include <asm/system_misc.h>
+
+#define RESET_SOURCE_ENABLE_REG 1
+#define SW_MASTER_RESET_REG 2
+
+static struct regmap *regmap;
+static u32 rst_src_en;
+static u32 sw_mstr_rst;
+
+static void brcmstb_reboot(enum reboot_mode mode, const char *cmd)
+{
+ int rc;
+ u32 tmp;
+
+ rc = regmap_write(regmap, rst_src_en, 1);
+ if (rc) {
+ pr_err("failed to write rst_src_en (%d)\n", rc);
+ return;
+ }
+
+ rc = regmap_read(regmap, rst_src_en, &tmp);
+ if (rc) {
+ pr_err("failed to read rst_src_en (%d)\n", rc);
+ return;
+ }
+
+ rc = regmap_write(regmap, sw_mstr_rst, 1);
+ if (rc) {
+ pr_err("failed to write sw_mstr_rst (%d)\n", rc);
+ return;
+ }
+
+ rc = regmap_read(regmap, sw_mstr_rst, &tmp);
+ if (rc) {
+ pr_err("failed to read sw_mstr_rst (%d)\n", rc);
+ return;
+ }
+
+ while (1)
+ ;
+}
+
+static int brcmstb_reboot_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct device_node *np = pdev->dev.of_node;
+
+ regmap = syscon_regmap_lookup_by_phandle(np, "syscon");
+ if (IS_ERR(regmap)) {
+ pr_err("failed to get syscon phandle\n");
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32_index(np, "syscon", RESET_SOURCE_ENABLE_REG,
+ &rst_src_en);
+ if (rc) {
+ pr_err("can't get rst_src_en offset (%d)\n", rc);
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32_index(np, "syscon", SW_MASTER_RESET_REG,
+ &sw_mstr_rst);
+ if (rc) {
+ pr_err("can't get sw_mstr_rst offset (%d)\n", rc);
+ return -EINVAL;
+ }
+
+ arm_pm_restart = brcmstb_reboot;
+
+ return 0;
+}
+
+static const struct of_device_id of_match[] = {
+ { .compatible = "brcm,brcmstb-reboot", },
+ {},
+};
+
+static struct platform_driver brcmstb_reboot_driver = {
+ .probe = brcmstb_reboot_probe,
+ .driver = {
+ .name = "brcmstb-reboot",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match,
+ },
+};
+
+static int __init brcmstb_reboot_init(void)
+{
+ return platform_driver_probe(&brcmstb_reboot_driver,
+ brcmstb_reboot_probe);
+}
+subsys_initcall(brcmstb_reboot_init);
--
1.7.1
^ permalink raw reply related
* [PATCH v6 1/8] ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
From: Marc Carino @ 2014-02-03 21:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391463041-15241-1-git-send-email-marc.ceeeee@gmail.com>
The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes.
This patch adds machine support for the ARM-based Broadcom SoCs.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/mach-bcm/Kconfig | 14 ++
arch/arm/mach-bcm/Makefile | 4 +
arch/arm/mach-bcm/brcmstb.c | 104 ++++++++++++
arch/arm/mach-bcm/brcmstb.h | 38 +++++
arch/arm/mach-bcm/headsmp-brcmstb.S | 33 ++++
arch/arm/mach-bcm/hotplug-brcmstb.c | 311 +++++++++++++++++++++++++++++++++++
7 files changed, 505 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-bcm/brcmstb.c
create mode 100644 arch/arm/mach-bcm/brcmstb.h
create mode 100644 arch/arm/mach-bcm/headsmp-brcmstb.S
create mode 100644 arch/arm/mach-bcm/hotplug-brcmstb.c
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 845bc74..2437b7f 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -12,6 +12,7 @@ CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_MACH_BERLIN_BG2=y
CONFIG_MACH_BERLIN_BG2CD=y
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index b1aa6a9..f85e7bc 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -32,6 +32,20 @@ config ARCH_BCM_MOBILE
BCM11130, BCM11140, BCM11351, BCM28145 and
BCM28155 variants.
+config ARCH_BRCMSTB
+ bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
+ depends on MMU
+ select ARM_GIC
+ select MIGHT_HAVE_PCI
+ select HAVE_SMP
+ select HAVE_ARM_ARCH_TIMER
+ help
+ Say Y if you intend to run the kernel on a Broadcom ARM-based STB
+ chipset.
+
+ This enables support for Broadcom ARM-based set-top box chipsets,
+ including the 7445 family of chips.
+
endmenu
endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index c2ccd5a..b744a12 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -13,3 +13,7 @@
obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_ARCH_BRCMSTB) := brcmstb.o
+obj-$(CONFIG_SMP) += headsmp-brcmstb.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug-brcmstb.o
diff --git a/arch/arm/mach-bcm/brcmstb.c b/arch/arm/mach-bcm/brcmstb.c
new file mode 100644
index 0000000..71387a8
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/console.h>
+#include <linux/clocksource.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+#include "brcmstb.h"
+
+/***********************************************************************
+ * STB CPU (main application processor)
+ ***********************************************************************/
+
+static const char *brcmstb_match[] __initconst = {
+ "brcm,bcm7445",
+ "brcm,brcmstb",
+ NULL
+};
+
+/***********************************************************************
+ * SMP boot
+ ***********************************************************************/
+
+#ifdef CONFIG_SMP
+static DEFINE_SPINLOCK(boot_lock);
+
+static void brcmstb_secondary_init(unsigned int cpu)
+{
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+static int brcmstb_boot_secondary(unsigned int cpu,
+ struct task_struct *idle)
+{
+ /*
+ * set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ /* Bring up power to the core if necessary */
+ if (brcmstb_cpu_get_power_state(cpu) == 0)
+ brcmstb_cpu_power_on(cpu);
+
+ brcmstb_cpu_boot(cpu);
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return 0;
+}
+
+struct smp_operations brcmstb_smp_ops __initdata = {
+ .smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
+ .smp_secondary_init = brcmstb_secondary_init,
+ .smp_boot_secondary = brcmstb_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_kill = brcmstb_cpu_kill,
+ .cpu_die = brcmstb_cpu_die,
+#endif
+};
+#endif
+
+DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
+ .dt_compat = brcmstb_match,
+#ifdef CONFIG_SMP
+ .smp = smp_ops(brcmstb_smp_ops),
+#endif
+MACHINE_END
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
new file mode 100644
index 0000000..e49bde6
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BRCMSTB_H__
+#define __BRCMSTB_H__
+
+#if !defined(__ASSEMBLY__)
+#include <linux/smp.h>
+#endif
+
+#if !defined(__ASSEMBLY__)
+extern void brcmstb_secondary_startup(void);
+extern void brcmstb_cpu_boot(unsigned int cpu);
+extern void brcmstb_cpu_power_on(unsigned int cpu);
+extern int brcmstb_cpu_get_power_state(unsigned int cpu);
+extern struct smp_operations brcmstb_smp_ops;
+#if defined(CONFIG_HOTPLUG_CPU)
+extern void brcmstb_cpu_die(unsigned int cpu);
+extern int brcmstb_cpu_kill(unsigned int cpu);
+void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus);
+#else
+static inline void brcmstb_cpu_die(unsigned int cpu) {}
+static inline int brcmstb_cpu_kill(unsigned int cpu) {}
+static inline void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus) {}
+#endif
+#endif
+
+#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
new file mode 100644
index 0000000..89134c7
--- /dev/null
+++ b/arch/arm/mach-bcm/headsmp-brcmstb.S
@@ -0,0 +1,33 @@
+/*
+ * SMP boot code for secondary CPUs
+ * Based on arch/arm/mach-tegra/headsmp.S
+ *
+ * Copyright (C) 2010 NVIDIA, Inc.
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/assembler.h>
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ .section ".text.head", "ax"
+
+ENTRY(brcmstb_secondary_startup)
+ /*
+ * Ensure CPU is in a sane state by disabling all IRQs and switching
+ * into SVC mode.
+ */
+ setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
+
+ bl v7_invalidate_l1
+ b secondary_startup
+ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/hotplug-brcmstb.c b/arch/arm/mach-bcm/hotplug-brcmstb.c
new file mode 100644
index 0000000..21431a6
--- /dev/null
+++ b/arch/arm/mach-bcm/hotplug-brcmstb.c
@@ -0,0 +1,311 @@
+/*
+ * Broadcom STB CPU hotplug support for ARM
+ *
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/printk.h>
+#include <linux/regmap.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/mach-types.h>
+#include <asm/smp_plat.h>
+
+#include "brcmstb.h"
+
+enum {
+ ZONE_MAN_CLKEN_MASK = BIT(0),
+ ZONE_MAN_RESET_CNTL_MASK = BIT(1),
+ ZONE_MAN_MEM_PWR_MASK = BIT(4),
+ ZONE_RESERVED_1_MASK = BIT(5),
+ ZONE_MAN_ISO_CNTL_MASK = BIT(6),
+ ZONE_MANUAL_CONTROL_MASK = BIT(7),
+ ZONE_PWR_DN_REQ_MASK = BIT(9),
+ ZONE_PWR_UP_REQ_MASK = BIT(10),
+ ZONE_BLK_RST_ASSERT_MASK = BIT(12),
+ ZONE_PWR_OFF_STATE_MASK = BIT(25),
+ ZONE_PWR_ON_STATE_MASK = BIT(26),
+ ZONE_DPG_PWR_STATE_MASK = BIT(28),
+ ZONE_MEM_PWR_STATE_MASK = BIT(29),
+ ZONE_RESET_STATE_MASK = BIT(31),
+ CPU0_PWR_ZONE_CTRL_REG = 1,
+ CPU_RESET_CONFIG_REG = 2,
+};
+
+static void __iomem *cpubiuctrl_block;
+static void __iomem *hif_cont_block;
+static u32 cpu0_pwr_zone_ctrl_reg;
+static u32 cpu_rst_cfg_reg;
+static u32 hif_cont_reg;
+DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
+
+static int per_cpu_sw_state_rd(u32 cpu)
+{
+ sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
+ return per_cpu(per_cpu_sw_state, cpu);
+}
+
+static void per_cpu_sw_state_wr(u32 cpu, int val)
+{
+ per_cpu(per_cpu_sw_state, cpu) = val;
+ dmb();
+ sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
+ dsb_sev();
+}
+
+static void __iomem *pwr_ctrl_get_base(u32 cpu)
+{
+ void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
+ base += (cpu_logical_map(cpu) * 4);
+ return base;
+}
+
+static u32 pwr_ctrl_rd(u32 cpu)
+{
+ void __iomem *base = pwr_ctrl_get_base(cpu);
+ return readl_relaxed(base);
+}
+
+static void pwr_ctrl_wr(u32 cpu, u32 val)
+{
+ void __iomem *base = pwr_ctrl_get_base(cpu);
+ writel(val, base);
+}
+
+static void cpu_rst_cfg_set(u32 cpu, int set)
+{
+ u32 val;
+ val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
+ if (set)
+ val |= BIT(cpu_logical_map(cpu));
+ else
+ val &= ~BIT(cpu_logical_map(cpu));
+ writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
+}
+
+static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
+{
+ const int reg_ofs = cpu_logical_map(cpu) * 8;
+ writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
+ writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
+}
+
+void brcmstb_cpu_boot(u32 cpu)
+{
+ pr_info("SMP: Booting CPU%d...\n", cpu);
+
+ /*
+ * set the reset vector to point to the secondary_startup
+ * routine
+ */
+ cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
+
+ /* unhalt the cpu */
+ cpu_rst_cfg_set(cpu, 0);
+}
+
+void brcmstb_cpu_power_on(u32 cpu)
+{
+ /*
+ * The secondary cores power was cut, so we must go through
+ * power-on initialization.
+ */
+ u32 tmp;
+
+ pr_info("SMP: Powering up CPU%d...\n", cpu);
+
+ /* Request zone power up */
+ pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
+
+ /* Wait for the power up FSM to complete */
+ do {
+ tmp = pwr_ctrl_rd(cpu);
+ } while (!(tmp & ZONE_PWR_ON_STATE_MASK));
+
+ per_cpu_sw_state_wr(cpu, 1);
+}
+
+int brcmstb_cpu_get_power_state(u32 cpu)
+{
+ int tmp = pwr_ctrl_rd(cpu);
+ return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
+}
+
+void __ref brcmstb_cpu_die(u32 cpu)
+{
+ v7_exit_coherency_flush(all);
+
+ /* Prevent all interrupts from reaching this CPU. */
+ arch_local_irq_disable();
+
+ /*
+ * Final full barrier to ensure everything before this instruction has
+ * quiesced.
+ */
+ isb();
+ dsb();
+
+ per_cpu_sw_state_wr(cpu, 0);
+
+ /* Sit and wait to die */
+ wfi();
+
+ /* We should never get here... */
+ panic("Spurious interrupt on CPU %d received!\n", cpu);
+}
+
+int brcmstb_cpu_kill(u32 cpu)
+{
+ u32 tmp;
+
+ pr_info("SMP: Powering down CPU%d...\n", cpu);
+
+ while (per_cpu_sw_state_rd(cpu))
+ ;
+
+ /* Program zone reset */
+ pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
+ ZONE_PWR_DN_REQ_MASK);
+
+ /* Verify zone reset */
+ tmp = pwr_ctrl_rd(cpu);
+ if (!(tmp & ZONE_RESET_STATE_MASK))
+ pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
+ __func__, cpu);
+
+ /* Wait for power down */
+ do {
+ tmp = pwr_ctrl_rd(cpu);
+ } while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
+
+ /* Settle-time from Broadcom-internal DVT reference code */
+ udelay(7);
+
+ /* Assert reset on the CPU */
+ cpu_rst_cfg_set(cpu, 1);
+
+ return 1;
+}
+
+static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
+{
+ int rc = 0;
+ char *name;
+ struct device_node *syscon_np = NULL;
+
+ name = "syscon-cpu";
+
+ syscon_np = of_parse_phandle(np, name, 0);
+ if (!syscon_np) {
+ pr_err("can't find phandle %s\n", name);
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ cpubiuctrl_block = of_iomap(syscon_np, 0);
+ if (!cpubiuctrl_block) {
+ pr_err("iomap failed for cpubiuctrl_block\n");
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
+ &cpu0_pwr_zone_ctrl_reg);
+ if (rc) {
+ pr_err("failed to read 1st entry from %s property (%d)\n", name,
+ rc);
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
+ &cpu_rst_cfg_reg);
+ if (rc) {
+ pr_err("failed to read 2nd entry from %s property (%d)\n", name,
+ rc);
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+cleanup:
+ if (syscon_np)
+ of_node_put(syscon_np);
+
+ return rc;
+}
+
+static int __init setup_hifcont_regs(struct device_node *np)
+{
+ int rc = 0;
+ char *name;
+ struct device_node *syscon_np = NULL;
+
+ name = "syscon-cont";
+
+ syscon_np = of_parse_phandle(np, name, 0);
+ if (!syscon_np) {
+ pr_err("can't find phandle %s\n", name);
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ hif_cont_block = of_iomap(syscon_np, 0);
+ if (!hif_cont_block) {
+ pr_err("iomap failed for hif_cont_block\n");
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ /* offset is at top of hif_cont_block */
+ hif_cont_reg = 0;
+
+cleanup:
+ if (syscon_np)
+ of_node_put(syscon_np);
+
+ return rc;
+}
+
+void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
+{
+ int rc;
+ struct device_node *np;
+ char *name;
+
+ name = "brcm,brcmstb-smpboot";
+ np = of_find_compatible_node(NULL, NULL, name);
+ if (!np) {
+ pr_err("can't find compatible node %s\n", name);
+ return;
+ }
+
+ rc = setup_hifcpubiuctrl_regs(np);
+ if (rc)
+ return;
+
+ rc = setup_hifcont_regs(np);
+ if (rc)
+ return;
+}
+
--
1.7.1
^ permalink raw reply related
* [PATCH v6 0/8] ARM: brcmstb: Add Broadcom STB SoC support
From: Marc Carino @ 2014-02-03 21:30 UTC (permalink / raw)
To: linux-arm-kernel
This patchset contains the board support package for the
Broadcom BCM7445 ARM-based SoC [1]. These changes contain a
minimal set of code needed for a BCM7445-based board to boot
the Linux kernel.
These changes heavily leverage the OF/devicetree framework.
v6:
- rebased to v3.14-rc1
- utilize common APIs for handling CPU power-down
- drop deprecated __cpuinit attributes
v5 (https://lkml.org/lkml/2014/1/21/640):
- rebased to v3.13 tag
- make UART DT node a child of 'rdb' node
- fix ordering of debug UART entries
v4 (https://lkml.org/lkml/2014/1/17/455):
- make a reboot driver and put it in the drivers folder
- rework DT bindings to leverage 'syscon'
- rework BSP code to use 'syscon' for all register mappings
- misc. tweaks per suggestions from v3
v3 (https://lkml.org/lkml/2014/1/14/696):
- rebased to v3.13-rc8
- switched to using 'multi_v7_defconfig'
- eliminated dependence on compile-time peripheral register access
- moved DT node iomap out from 'init_early'
- misc. minor cleanups from mailing-list discussion for v2
v2 (https://lkml.org/lkml/2013/11/26/570):
- rebased to v3.13-rc1
- moved implementation to 'mach-bcm' folder
- added CPU init for B16RM
v1:
- initial submission
[1] http://www.broadcom.com/products/Cable/Cable-Set-Top-Box-Solutions/BCM7445
Marc Carino (8):
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
power: reset: Add reboot driver for brcmstb
ARM: brcmstb: add debug UART for earlyprintk support
ARM: do CPU-specific init for Broadcom Brahma15 cores
ARM: brcmstb: add CPU binding for Broadcom Brahma15
ARM: brcmstb: add misc. DT bindings for brcmstb
ARM: brcmstb: gic: add compatible string for Broadcom Brahma15
ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
.../devicetree/bindings/arm/brcm-brcmstb.txt | 95 ++++++
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
Documentation/devicetree/bindings/arm/gic.txt | 1 +
arch/arm/Kconfig.debug | 15 +-
arch/arm/boot/dts/bcm7445.dts | 111 +++++++
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/mach-bcm/Kconfig | 15 +
arch/arm/mach-bcm/Makefile | 4 +
arch/arm/mach-bcm/brcmstb.c | 104 +++++++
arch/arm/mach-bcm/brcmstb.h | 38 +++
arch/arm/mach-bcm/headsmp-brcmstb.S | 33 ++
arch/arm/mach-bcm/hotplug-brcmstb.c | 311 ++++++++++++++++++++
arch/arm/mm/proc-v7.S | 11 +
drivers/power/reset/Kconfig | 10 +
drivers/power/reset/Makefile | 1 +
drivers/power/reset/brcmstb-reboot.c | 120 ++++++++
16 files changed, 870 insertions(+), 1 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
create mode 100644 arch/arm/boot/dts/bcm7445.dts
create mode 100644 arch/arm/mach-bcm/brcmstb.c
create mode 100644 arch/arm/mach-bcm/brcmstb.h
create mode 100644 arch/arm/mach-bcm/headsmp-brcmstb.S
create mode 100644 arch/arm/mach-bcm/hotplug-brcmstb.c
create mode 100644 drivers/power/reset/brcmstb-reboot.c
^ permalink raw reply
* NFS client broken in Linus' tip
From: Christoph Hellwig @ 2014-02-03 20:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391201970.6978.1.camel@leira.trondhjem.org>
Looks good as the lesser evil:
Reviewed-by: Christoph Hellwig <hch@lst.de>
^ permalink raw reply
* arm64: kernel panic in paging_init()
From: Mark Salter @ 2014-02-03 20:50 UTC (permalink / raw)
To: linux-arm-kernel
I'm seeing the following panic in paging init. This is on the foundation
model with a modified dtb memory node which has a non section-aligned
bank:
memory at 80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x20000000>,
<0x00000000 0xa0300000 0 0x1fd00000>;
};
I only see this with 64k pagesize configured. What happens is the
non section-aligned bank causes alloc_init_pte() to allocate a page
for the new pte from the end of the first bank (the failing address
0xfffffe001fff0000 [0x9fff0000 phys]). This should be a valid page
since it was mapped during the create_mapping() call for the first
memory bank. A flush_tlb_all() added to the end of create_mapping()
makes the panic go away so I think the problem is something stale
cached before the page with the failing address was mapped.
Thoughts?
Linux version 3.14.0-rc1+ (msalter at deneb.redhat.com) (gcc version 4.8.1 20130717 (Red Hat 4.8.1-5) (GCC) ) #1 SMP Mon Feb 3 10:31:04 EST 2014
CPU: AArch64 Processor [410fd000] revision 0
bootconsole [earlycon0] enabled
Unable to handle kernel paging request at virtual address fffffe001fff0000
pgd = fffffe0000050000
[fffffe001fff0000] *pgd=0000000080000711, *pmd=0000000080000711
Internal error: Oops: 96000047 [#1] SMP
Modules linked in:
CPU: 0 PID: 0 Comm: swapper Not tainted 3.14.0-rc1+ #1
task: fffffe00007f6920 ti: fffffe00007c0000 task.ti: fffffe00007c0000
PC is at memset+0x1c/0x60
LR is at early_alloc.constprop.6+0x3c/0x4c
pc : [<fffffe00002f2e7c>] lr : [<fffffe000076439c>] pstate: 200002c5
sp : fffffe00007c3e40
x29: fffffe00007c3e40 x28: fffffe0020300000
x27: fffffbffffffffff x26: fffffe0000804000
x25: fffffe00006a6b18 x24: fffffe0000000000
x23: fffffe0000804000 x22: 0000000000000018
x21: fffffe000084e000 x20: fffffe000084e000
x19: fffffe001fff0000 x18: 0000000000000000
x17: fffffe000087c308 x16: 0000000000000000
x15: 0000000000000007 x14: 00000000a0000000
x13: 0000000000000018 x12: 0000000080000000
x11: fffffe000087cf08 x10: 000000000020153d
x9 : 0000000300000000 x8 : 0000000000000007
x7 : 00000000ff79b000 x6 : 0000000000001000
x5 : fffffe000087cf98 x4 : fffffe001fff0000
x3 : 00000000000000a8 x2 : 000000000000fff8
x1 : 0000000000000000 x0 : fffffe001fff0000
Process swapper (pid: 0, stack limit = 0xfffffe00007c0058)
Stack: (0xfffffe00007c3e40 to 0xfffffe00007c4000)
3e40: 007c3e60 fffffe00 00764598 fffffe00 0087c320 fffffe00 001424a8 fffffe00
3e60: 007c3f10 fffffe00 00762bf0 fffffe00 0084e000 fffffe00 00080000 fffffe00
3e80: 007c3fe0 fffffe00 0084d000 fffffe00 807f9000 00000000 80000000 00000000
3ea0: 80030000 00000000 80050000 00000000 000803f8 fffffe00 80080200 00000000
3ec0: a0300000 00000000 40000000 fffffe00 40000000 fffffe00 00058008 fffffe00
3ee0: 0000a030 00000000 20000000 00000000 3fffffff fffffe00 0084e080 fffffe00
3f00: 00000000 02c00000 00000000 00000200 007c3fa0 fffffe00 0076051c fffffe00
3f20: 0084de40 fffffe00 00000001 00000000 00000000 00000000 410fd000 00000000
3f40: 807f9000 00000000 80000000 00000000 80030000 00000000 80050000 00000000
3f60: 000803f8 fffffe00 005600a8 fffffe00 00000001 00000000 00000001 00000000
3f80: 007ff330 fffffe00 00000000 00000000 9f400000 00000000 00854168 fffffe00
3fa0: 00000000 00000000 80080200 00000000 ff7b2f18 00000000 00000e12 00000000
3fc0: 9f400000 00000000 410fd000 00000000 807f9000 00000000 00000000 00000000
3fe0: 00787278 fffffe00 00000000 00000000 00000000 00000000 00000000 00000000
Call trace:
[<fffffe00002f2e7c>] memset+0x1c/0x60
[<fffffe0000764598>] paging_init+0x194/0x314
[<fffffe0000762bf0>] setup_arch+0x1d0/0x520
[<fffffe000076051c>] start_kernel+0x88/0x384
Code: 2a014021 aa018021 f1002042 54000084 (f8008481)
---[ end trace 3406ff24bd97382e ]---
Kernel panic - not syncing: Attempted to kill the idle task!
^ permalink raw reply
* [PATCH v5 15/16] ARM: add uprobes support
From: Rabin Vincent @ 2014-02-03 20:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391445367.3509.30.camel@linaro1.home>
2014-02-03 Jon Medhurst (Tixy) <tixy@linaro.org>:
> On Thu, 2014-01-23 at 15:05 -0500, David Long wrote:
> > From: "David A. Long" <dave.long@linaro.org>
> >
> > Using Rabin Vincent's ARM uprobes patches as a base, enable uprobes
> > support on ARM.
> >
> > Caveats:
> >
> > - Thumb is not supported
> >
> > Signed-off-by: David A. Long <dave.long@linaro.org>
>
> As this is based on Rabin's work, and the new files have his Copyright,
> then this patch also needs his 'Signed-off-by'. Rabin, I assume that you
> agree?
Don't know if it's needed, but if it is, you may certainly add it to
this patch, David:
Signed-off-by: Rabin Vincent <rabin@rab.in>
^ permalink raw reply
* NFS client broken in Linus' tip
From: Trond Myklebust @ 2014-02-03 20:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140203202543.GA7070@infradead.org>
On Feb 3, 2014, at 15:25, Christoph Hellwig <hch@infradead.org> wrote:
> On Mon, Feb 03, 2014 at 03:22:15PM -0500, Trond Myklebust wrote:
>> FWIW, here is the alternative patch. I've tested it, and it seems to
>> work.
>
> I much prefer the original one. One major point of the series was to
> get individual filesystems out of the business of providing xattr
> handlers for ACLs.
>
Then could you and Al please provide an Acked-by? This is a userspace API, so we shouldn?t be changing return values without good reason.
--
Trond Myklebust
Linux NFS client maintainer
^ permalink raw reply
* [PATCH v2 1/7] ARM: perf_event: Support percpu irqs for the CPU PMU
From: Christopher Covington @ 2014-02-03 20:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389808535-23852-2-git-send-email-sboyd@codeaurora.org>
On 01/15/2014 12:55 PM, Stephen Boyd wrote:
> Some CPU PMUs are wired up with one PPI for all the CPUs instead
> of with a different SPI for each CPU. Add support for these
> devices.
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
> arch/arm/kernel/perf_event.c | 14 ++++--
> arch/arm/kernel/perf_event_cpu.c | 97 ++++++++++++++++++++++++++++------------
> 2 files changed, 80 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> index 789d846a9184..e76750980b38 100644
> --- a/arch/arm/kernel/perf_event.c
> +++ b/arch/arm/kernel/perf_event.c
> @@ -16,6 +16,8 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/uaccess.h>
> +#include <linux/irq.h>
> +#include <linux/irqdesc.h>
>
> #include <asm/irq_regs.h>
> #include <asm/pmu.h>
> @@ -295,9 +297,15 @@ validate_group(struct perf_event *event)
>
> static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
> {
> - struct arm_pmu *armpmu = (struct arm_pmu *) dev;
> - struct platform_device *plat_device = armpmu->plat_device;
> - struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
> + struct arm_pmu *armpmu;
> + struct platform_device *plat_device;
> + struct arm_pmu_platdata *plat;
> +
> + if (irq_is_percpu(irq))
In case anyone else is trying to follow along, this requires:
http://lkml.org/lkml/2013/12/4/316
Regards,
Christopher
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by the Linux Foundation.
^ permalink raw reply
* NFS client broken in Linus' tip
From: Christoph Hellwig @ 2014-02-03 20:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391458935.17089.1.camel@leira.trondhjem.org>
On Mon, Feb 03, 2014 at 03:22:15PM -0500, Trond Myklebust wrote:
> FWIW, here is the alternative patch. I've tested it, and it seems to
> work.
I much prefer the original one. One major point of the series was to
get individual filesystems out of the business of providing xattr
handlers for ACLs.
^ permalink raw reply
* NFS client broken in Linus' tip
From: Russell King - ARM Linux @ 2014-02-03 20:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391458935.17089.1.camel@leira.trondhjem.org>
On Mon, Feb 03, 2014 at 03:22:15PM -0500, Trond Myklebust wrote:
> On Mon, 2014-02-03 at 10:45 -0500, Trond Myklebust wrote:
> > On Feb 3, 2014, at 9:57, Christoph Hellwig <hch@infradead.org> wrote:
> >
> > > On Mon, Feb 03, 2014 at 09:17:30AM -0500, Trond Myklebust wrote:
> > >> As I said above, that causes posix_acl_xattr_get() to return the wrong answer (ENODATA instead of EOPNOTSUPP).
> > >
> > > Is it really the wrong answer? How does userspace care wether this
> > > server doesn't support ACLs at all or none is set? The resulting
> > > behavior is the same.
> >
> > It will certainly cause acl_get_file() to behave differently than previously. I?ve no idea how that will affect applications, though.
> >
> > > If there's a good reason to care we might have to go with your patch,
> > > but if we can avoid it I'd prefer to keep things simple.
> >
> > One alternative is to simply wrap posix_acl_xattr_get() in fs/nfs/nfs3acl.c, and have it check the value of nfs_server_capable(inode, NFS_CAP_ACLS) before returning ENODATA. That?s rather ugly too...
>
> FWIW, here is the alternative patch. I've tested it, and it seems to
> work.
Thanks.
As there's now two fixes, which would you like me to test?
One comment on this patch though:
> +static int
> +nfs_posix_acl_xattr_get(struct dentry *dentry, const char *name,
> + void *value, size_t size, int type)
> +{
> + int ret;
> +
> + ret = posix_acl_xattr_get(dentry, name, value, size, type);
> + /*
> + * This check is needed to override the ENODATA error that
> + * posix_acl_xattr_get will return if the acl probe fails.
> + */
> + if (!nfs_server_capable(dentry->d_inode, NFS_CAP_ACLS))
> + ret = -EOPNOTSUPP;
I'm not familiar with this code, but the above looks slightly weird,
and a little suspicious - especially with the lack of blank line
before the comment. Is the above actually intended?
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* NFS client broken in Linus' tip
From: Trond Myklebust @ 2014-02-03 20:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3003D7E5-93F8-4B32-ACDB-07ED3F6CE70D@primarydata.com>
On Mon, 2014-02-03 at 10:45 -0500, Trond Myklebust wrote:
> On Feb 3, 2014, at 9:57, Christoph Hellwig <hch@infradead.org> wrote:
>
> > On Mon, Feb 03, 2014 at 09:17:30AM -0500, Trond Myklebust wrote:
> >> As I said above, that causes posix_acl_xattr_get() to return the wrong answer (ENODATA instead of EOPNOTSUPP).
> >
> > Is it really the wrong answer? How does userspace care wether this
> > server doesn't support ACLs at all or none is set? The resulting
> > behavior is the same.
>
> It will certainly cause acl_get_file() to behave differently than previously. I?ve no idea how that will affect applications, though.
>
> > If there's a good reason to care we might have to go with your patch,
> > but if we can avoid it I'd prefer to keep things simple.
>
> One alternative is to simply wrap posix_acl_xattr_get() in fs/nfs/nfs3acl.c, and have it check the value of nfs_server_capable(inode, NFS_CAP_ACLS) before returning ENODATA. That?s rather ugly too...
FWIW, here is the alternative patch. I've tested it, and it seems to
work.
8<---------------------------------------------------------------------
>From 2e527b12169a67e9cfcf43898ae4d15bcfa1ede9 Mon Sep 17 00:00:00 2001
From: Trond Myklebust <trond.myklebust@primarydata.com>
Date: Mon, 3 Feb 2014 13:07:05 -0500
Subject: [PATCH] NFSv3: Fix return values for get_acl()
Ensure that nfs3_get_acl() returns NULL when the server doesn't support
POSIX acls. This ensures that posix_acl_create() does the right thing,
and applies the current_umask() to the mode before returning.
Add a wrapper around posix_acl_xattr_get() so that we continue to
return EOPNOTSUPP when the server doesn't support POSIX acls. Otherwise,
the NULL return from nfs3_get_acl() will cause ENODATA to be returned.
Also add the appropriate exports to posix_acl_xattr_get, posix_acl_xattr_set
and posix_acl_xattr_list to enable their use in the wrapper.
Reported-by: Russell King <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/20140130140834.GW15937 at n2100.arm.linux.org.uk
Cc: Christoph Hellwig <hch@lst.de>
Cc: Al Viro viro at zeniv.linux.org.uk>
Signed-off-by: Trond Myklebust <trond.myklebust@primarydata.com>
---
fs/nfs/nfs3acl.c | 42 ++++++++++++++++++++++++++++++++++++-----
fs/posix_acl.c | 9 ++++++---
include/linux/posix_acl_xattr.h | 8 ++++++++
3 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/fs/nfs/nfs3acl.c b/fs/nfs/nfs3acl.c
index 871d6eda8dba..d1bc84f22f64 100644
--- a/fs/nfs/nfs3acl.c
+++ b/fs/nfs/nfs3acl.c
@@ -28,8 +28,10 @@ struct posix_acl *nfs3_get_acl(struct inode *inode, int type)
};
int status, count;
- if (!nfs_server_capable(inode, NFS_CAP_ACLS))
- return ERR_PTR(-EOPNOTSUPP);
+ if (!nfs_server_capable(inode, NFS_CAP_ACLS)) {
+ cache_no_acl(inode);
+ return NULL;
+ }
status = nfs_revalidate_inode(server, inode);
if (status < 0)
@@ -70,7 +72,7 @@ struct posix_acl *nfs3_get_acl(struct inode *inode, int type)
dprintk("NFS_V3_ACL extension not supported; disabling\n");
server->caps &= ~NFS_CAP_ACLS;
case -ENOTSUPP:
- status = -EOPNOTSUPP;
+ status = 0;
default:
goto getout;
}
@@ -242,8 +244,38 @@ fail:
return PTR_ERR(alloc);
}
+static int
+nfs_posix_acl_xattr_get(struct dentry *dentry, const char *name,
+ void *value, size_t size, int type)
+{
+ int ret;
+
+ ret = posix_acl_xattr_get(dentry, name, value, size, type);
+ /*
+ * This check is needed to override the ENODATA error that
+ * posix_acl_xattr_get will return if the acl probe fails.
+ */
+ if (!nfs_server_capable(dentry->d_inode, NFS_CAP_ACLS))
+ ret = -EOPNOTSUPP;
+ return ret;
+}
+
+static const struct xattr_handler nfs_posix_acl_access_xattr_handler = {
+ .prefix = POSIX_ACL_XATTR_ACCESS,
+ .flags = ACL_TYPE_ACCESS,
+ .get = nfs_posix_acl_xattr_get,
+ .set = posix_acl_xattr_set,
+};
+
+static const struct xattr_handler nfs_posix_acl_default_xattr_handler = {
+ .prefix = POSIX_ACL_XATTR_DEFAULT,
+ .flags = ACL_TYPE_DEFAULT,
+ .get = nfs_posix_acl_xattr_get,
+ .set = posix_acl_xattr_set,
+};
+
const struct xattr_handler *nfs3_xattr_handlers[] = {
- &posix_acl_access_xattr_handler,
- &posix_acl_default_xattr_handler,
+ &nfs_posix_acl_access_xattr_handler,
+ &nfs_posix_acl_default_xattr_handler,
NULL,
};
diff --git a/fs/posix_acl.c b/fs/posix_acl.c
index 38bae5a0ea25..835167f92952 100644
--- a/fs/posix_acl.c
+++ b/fs/posix_acl.c
@@ -750,7 +750,7 @@ posix_acl_to_xattr(struct user_namespace *user_ns, const struct posix_acl *acl,
}
EXPORT_SYMBOL (posix_acl_to_xattr);
-static int
+int
posix_acl_xattr_get(struct dentry *dentry, const char *name,
void *value, size_t size, int type)
{
@@ -773,8 +773,9 @@ posix_acl_xattr_get(struct dentry *dentry, const char *name,
return error;
}
+EXPORT_SYMBOL_GPL(posix_acl_xattr_get);
-static int
+int
posix_acl_xattr_set(struct dentry *dentry, const char *name,
const void *value, size_t size, int flags, int type)
{
@@ -809,8 +810,9 @@ out:
posix_acl_release(acl);
return ret;
}
+EXPORT_SYMBOL_GPL(posix_acl_xattr_set);
-static size_t
+size_t
posix_acl_xattr_list(struct dentry *dentry, char *list, size_t list_size,
const char *name, size_t name_len, int type)
{
@@ -832,6 +834,7 @@ posix_acl_xattr_list(struct dentry *dentry, char *list, size_t list_size,
memcpy(list, xname, size);
return size;
}
+EXPORT_SYMBOL_GPL(posix_acl_xattr_list);
const struct xattr_handler posix_acl_access_xattr_handler = {
.prefix = POSIX_ACL_XATTR_ACCESS,
diff --git a/include/linux/posix_acl_xattr.h b/include/linux/posix_acl_xattr.h
index 6f14ee295822..fc062003a456 100644
--- a/include/linux/posix_acl_xattr.h
+++ b/include/linux/posix_acl_xattr.h
@@ -69,6 +69,14 @@ struct posix_acl *posix_acl_from_xattr(struct user_namespace *user_ns,
int posix_acl_to_xattr(struct user_namespace *user_ns,
const struct posix_acl *acl, void *buffer, size_t size);
+int posix_acl_xattr_get(struct dentry *dentry, const char *name,
+ void *value, size_t size, int type);
+int posix_acl_xattr_set(struct dentry *dentry, const char *name,
+ const void *value, size_t size, int flags, int type);
+size_t posix_acl_xattr_list(struct dentry *dentry, char *list,
+ size_t list_size, const char *name,
+ size_t name_len, int type);
+
extern const struct xattr_handler posix_acl_access_xattr_handler;
extern const struct xattr_handler posix_acl_default_xattr_handler;
--
1.8.5.3
--
Trond Myklebust
Linux NFS client maintainer
^ permalink raw reply related
* [PATCH 1/2] clocksource: sunxi: Add new compatibles
From: Daniel Lezcano @ 2014-02-03 20:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140203194505.GF25625@lukather>
On 02/03/2014 08:45 PM, Maxime Ripard wrote:
> Hi Daniel,
>
> (Adding DT mailing-list in CC)
>
> On Mon, Feb 03, 2014 at 05:36:03PM +0100, Daniel Lezcano wrote:
>> On 02/02/2014 02:37 PM, Maxime Ripard wrote:
>>> The Allwinner A10 compatibles were following a slightly different compatible
>>> patterns than the rest of the SoCs for historical reasons. Add compatibles
>>> matching the other pattern to the timer driver for consistency, and keep the
>>> older one for backward compatibility.
>>
>> Hi Maxime,
>>
>> is it really needed to keep the old pattern ?
>
> We agreed during the ARM Kernel Summit to consider the DT as a stable
> ABI.
>
> While I'd be ok with removing the older ones, that also means that we
> would break the boot of newer kernels with older DT, so yes, we
> actually need to keep the old compatibles.
Thanks for the clarification.
So these old compatibles will stay there 'ad vitam aeternam', right ?
>>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>>> ---
>>> Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | 5 +++--
>>> drivers/clocksource/sun4i_timer.c | 4 ++++
>>> 2 files changed, 7 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
>>> index 48aeb78..d9e35ae 100644
>>> --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
>>> +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
>>> @@ -2,7 +2,8 @@ Allwinner A1X SoCs Timer Controller
>>>
>>> Required properties:
>>>
>>> -- compatible : should be "allwinner,sun4i-timer"
>>> +- compatible : should be "allwinner,sun4i-a10-timer"
>>> + (Deprecated "allwinner,sun4i-timer")
>>> - reg : Specifies base physical address and size of the registers.
>>> - interrupts : The interrupt of the first timer
>>> - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
>>> @@ -10,7 +11,7 @@ Required properties:
>>> Example:
>>>
>>> timer {
>>> - compatible = "allwinner,sun4i-timer";
>>> + compatible = "allwinner,sun4i-a10-timer";
>>> reg = <0x01c20c00 0x400>;
>>> interrupts = <22>;
>>> clocks = <&osc>;
>>> diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
>>> index bf497af..de03895 100644
>>> --- a/drivers/clocksource/sun4i_timer.c
>>> +++ b/drivers/clocksource/sun4i_timer.c
>>> @@ -196,5 +196,9 @@ static void __init sun4i_timer_init(struct device_node *node)
>>> clockevents_config_and_register(&sun4i_clockevent, rate,
>>> TIMER_SYNC_TICKS, 0xffffffff);
>>> }
>>> +CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
>>> + sun4i_timer_init);
>>> +
>>> +/* Deprecated */
>>> CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
>>> sun4i_timer_init);
>>>
>>
>>
>> --
>> <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
>>
>> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
>> <http://twitter.com/#!/linaroorg> Twitter |
>> <http://www.linaro.org/linaro-blog/> Blog
>>
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [RFC PATCH V3 1/4] pci: APM X-Gene PCIe controller driver
From: Tanmay Inamdar @ 2014-02-03 20:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4985267.LnsktRmabM@wuerfel>
On Mon, Feb 3, 2014 at 12:12 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Monday 03 February 2014 11:42:22 Tanmay Inamdar wrote:
>> On Thu, Jan 30, 2014 at 6:16 AM, Arnd Bergmann <arnd@arndb.de> wrote:
>> > On Friday 24 January 2014, Tanmay Inamdar wrote:
>> >
>> >> +static void xgene_pcie_fixup_bridge(struct pci_dev *dev)
>> >> +{
>> >> + int i;
>> >> +
>> >> + /* Hide the PCI host BARs from the kernel as their content doesn't
>> >> + * fit well in the resource management
>> >> + */
>> >> + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
>> >> + dev->resource[i].start = dev->resource[i].end = 0;
>> >> + dev->resource[i].flags = 0;
>> >> + }
>> >> + dev_info(&dev->dev, "Hiding X-Gene pci host bridge resources %s\n",
>> >> + pci_name(dev));
>> >> +}
>> >> +DECLARE_PCI_FIXUP_HEADER(XGENE_PCIE_VENDORID, XGENE_PCIE_DEVICEID,
>> >> + xgene_pcie_fixup_bridge);
>> >
>> > Shouldn't this be gone now that the host bridge is correctly shown
>> > at the domain root?
>>
>> In inbound region configuration, whole DDR space is mapped into the
>> BAR of RC. When Linux PCI mid-layer starts enumerating, it reads the
>> size of BAR of RC and tries to fit it into the memory resource. First
>> thing is that the outbound memory is not enough to map the inbound BAR
>> space. This creates problem with the resource management logic and
>> second thing is that, it is not required to map inbound BAR space RC
>> bar as no one will be accessing it further.
>>
>> As Jason suggested, Bridge BAR's should be 0 size unless the bridge
>> itself has registers. However this is not the case with XGene PCIe
>> controller. It may have been inherited from the legacy design.
>> 'arch/powerpc/sysdev/ppc4xx_pci.c' has similar fixup function.
>
> Are you sure that is true for the root bridge as well? I don't
> remember the details, but I though that for the host bridge,
> we don't actually look at the BARs at all.
>
>> > If you want to try out the I/O space, I'd suggest using an Intel
>> > e1000 network card, which has both memory and i/o space. There
>> > is a patch at http://www.spinics.net/lists/linux-pci/msg27684.html
>> > that lets you check the I/O registers on it, or you can go
>> > through /dev/port from user space.
>> >
>> > I also haven't seen your patch that adds pci_ioremap_io() for
>> > arm64. It would be helpful to keep it in the same patch
>> > series, since it won't build without this patch.
>>
>> I will post the arm64 pci patch along with next revision of this
>> driver. That will cover the 'pci_ioremap_io' as well.
>
> Please note that today, Liviu Dudau has also posted patches for this,
> so you should coordinate a bit.
Yes. Just looking at his patches. Looks similar to what I have. I will
wait till your solution shapes up.
>
> Arnd
^ permalink raw reply
* [RFC PATCH V3 1/4] pci: APM X-Gene PCIe controller driver
From: Arnd Bergmann @ 2014-02-03 20:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACoXjcnXoysMeBsGuOb3t5b10zdeJ8pOnuOOzR8AaZhsOOYVEw@mail.gmail.com>
On Monday 03 February 2014 11:42:22 Tanmay Inamdar wrote:
> On Thu, Jan 30, 2014 at 6:16 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Friday 24 January 2014, Tanmay Inamdar wrote:
> >
> >> +static void xgene_pcie_fixup_bridge(struct pci_dev *dev)
> >> +{
> >> + int i;
> >> +
> >> + /* Hide the PCI host BARs from the kernel as their content doesn't
> >> + * fit well in the resource management
> >> + */
> >> + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
> >> + dev->resource[i].start = dev->resource[i].end = 0;
> >> + dev->resource[i].flags = 0;
> >> + }
> >> + dev_info(&dev->dev, "Hiding X-Gene pci host bridge resources %s\n",
> >> + pci_name(dev));
> >> +}
> >> +DECLARE_PCI_FIXUP_HEADER(XGENE_PCIE_VENDORID, XGENE_PCIE_DEVICEID,
> >> + xgene_pcie_fixup_bridge);
> >
> > Shouldn't this be gone now that the host bridge is correctly shown
> > at the domain root?
>
> In inbound region configuration, whole DDR space is mapped into the
> BAR of RC. When Linux PCI mid-layer starts enumerating, it reads the
> size of BAR of RC and tries to fit it into the memory resource. First
> thing is that the outbound memory is not enough to map the inbound BAR
> space. This creates problem with the resource management logic and
> second thing is that, it is not required to map inbound BAR space RC
> bar as no one will be accessing it further.
>
> As Jason suggested, Bridge BAR's should be 0 size unless the bridge
> itself has registers. However this is not the case with XGene PCIe
> controller. It may have been inherited from the legacy design.
> 'arch/powerpc/sysdev/ppc4xx_pci.c' has similar fixup function.
Are you sure that is true for the root bridge as well? I don't
remember the details, but I though that for the host bridge,
we don't actually look at the BARs at all.
> > If you want to try out the I/O space, I'd suggest using an Intel
> > e1000 network card, which has both memory and i/o space. There
> > is a patch at http://www.spinics.net/lists/linux-pci/msg27684.html
> > that lets you check the I/O registers on it, or you can go
> > through /dev/port from user space.
> >
> > I also haven't seen your patch that adds pci_ioremap_io() for
> > arm64. It would be helpful to keep it in the same patch
> > series, since it won't build without this patch.
>
> I will post the arm64 pci patch along with next revision of this
> driver. That will cover the 'pci_ioremap_io' as well.
Please note that today, Liviu Dudau has also posted patches for this,
so you should coordinate a bit.
Arnd
^ permalink raw reply
* [PATCH 1/2] clocksource: sunxi: Add new compatibles
From: Rob Herring @ 2014-02-03 20:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140203194505.GF25625@lukather>
On Mon, Feb 3, 2014 at 1:45 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Daniel,
>
> (Adding DT mailing-list in CC)
>
> On Mon, Feb 03, 2014 at 05:36:03PM +0100, Daniel Lezcano wrote:
>> On 02/02/2014 02:37 PM, Maxime Ripard wrote:
>> >The Allwinner A10 compatibles were following a slightly different compatible
>> >patterns than the rest of the SoCs for historical reasons. Add compatibles
>> >matching the other pattern to the timer driver for consistency, and keep the
>> >older one for backward compatibility.
>>
>> Hi Maxime,
>>
>> is it really needed to keep the old pattern ?
>
> We agreed during the ARM Kernel Summit to consider the DT as a stable
> ABI.
>
> While I'd be ok with removing the older ones, that also means that we
> would break the boot of newer kernels with older DT, so yes, we
> actually need to keep the old compatibles.
It all depends if that would really cause problems for a given
platform. So if Allwinner DT support is a moving target, then changing
is probably okay. For example, if anyone using the platform is going
to need to update their DTB to add more nodes to get various features
anyway, then breaking it is not all that important.
Rob
^ permalink raw reply
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