* [PATCH 05/10] ARM: ux500: move AB8500 USB UICC settings to DT
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the set-up of the USB UICC (InteChip USB) from the
board file to the device tree.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 19 ++++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 9 ---------
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 3aae4ec5bcc9..9cf12d5d0923 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -34,7 +34,8 @@
<&gpio35_default_mode>,
<&ycbcr_default_mode>,
<&pwm_default_mode>,
- <&adi1_default_mode>;
+ <&adi1_default_mode>,
+ <&usbuicc_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -301,6 +302,22 @@
};
};
};
+ /* This sets up the USB UICC pins */
+ usbuicc {
+ usbuicc_default_mode: usbuicc_default {
+ default_mux {
+ ste,function = "usbuicc";
+ ste,pins = "usbuicc_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO21_H19",
+ "GPIO22_G20",
+ "GPIO23_G19";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index d0b262242ab7..443b1f4b828a 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,15 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 21,22 and 23 are muxed in USB UICC
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
- AB8500_PIN_HOG("GPIO21_H19", in_pd),
- AB8500_PIN_HOG("GPIO22_G20", in_pd),
- AB8500_PIN_HOG("GPIO23_G19", in_pd),
-
- /*
* pins 27,28 are muxed in DMIC12
* configured in INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 04/10] ARM: ux500: move AB8500 audio interface 1 settings to DT
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the pin muxing and configuration for audio interface
one over to the device tree as a hog configuration.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 20 +++++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 10 ----------
2 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index cdf2b3fd22dc..3aae4ec5bcc9 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -33,7 +33,8 @@
<&gpio26_default_mode>,
<&gpio35_default_mode>,
<&ycbcr_default_mode>,
- <&pwm_default_mode>;
+ <&pwm_default_mode>,
+ <&adi1_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -283,6 +284,23 @@
};
};
};
+ /* This sets up audio interface 1 */
+ adi1 {
+ adi1_default_mode: adi1_default {
+ default_mux {
+ ste,function = "adi1";
+ ste,pins = "adi1_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO17_P5",
+ "GPIO18_R5",
+ "GPIO19_U5",
+ "GPIO20_T5";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index b75089faf956..d0b262242ab7 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,16 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 17,18,19 and 20 are muxed in AUDIO interface 1
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("adi1_d_1", "adi1"),
- AB8500_PIN_HOG("GPIO17_P5", in_pd),
- AB8500_PIN_HOG("GPIO18_R5", in_pd),
- AB8500_PIN_HOG("GPIO19_U5", in_pd),
- AB8500_PIN_HOG("GPIO20_T5", in_pd),
-
- /*
* pins 21,22 and 23 are muxed in USB UICC
* configured in INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 03/10] ARM: ux500: move AB8500 PWM out settings to device tree
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the muxing and biasing of the AB8500 PWM output pins
over to the device tree for affected platforms.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 18 +++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 10 ----------
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 2b548e90878e..cdf2b3fd22dc 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -32,7 +32,8 @@
<&gpio42_default_mode>,
<&gpio26_default_mode>,
<&gpio35_default_mode>,
- <&ycbcr_default_mode>;
+ <&ycbcr_default_mode>,
+ <&pwm_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -267,6 +268,21 @@
};
};
};
+ /* This sets up the PWM pins 14 and 15 */
+ pwm {
+ pwm_default_mode: pwm_default {
+ default_mux {
+ ste,function = "pwmout";
+ ste,pins = "pwmout1_d_1", "pwmout2_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO14_F14",
+ "GPIO15_B17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index d58513b08a6d..b75089faf956 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,16 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 14,15 are muxed in PWM1 and PWM2
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
- AB8500_PIN_HOG("GPIO14_F14", in_pd),
-
- AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
- AB8500_PIN_HOG("GPIO15_B17", in_pd),
-
- /*
* pins 17,18,19 and 20 are muxed in AUDIO interface 1
* configured in INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 02/10] ARM: ux500: move AB8500 YCBCR settings to device tree
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the pin control settings for the YCBCR connector
on the AB8500 over to the device tree as a hog.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 23 ++++++++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 10 ----------
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 58b00d0f023e..2b548e90878e 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -31,7 +31,8 @@
<&gpio39_default_mode>,
<&gpio42_default_mode>,
<&gpio26_default_mode>,
- <&gpio35_default_mode>;
+ <&gpio35_default_mode>,
+ <&ycbcr_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -246,6 +247,26 @@
};
};
};
+ /*
+ * This sets up the YCBCR connector pins, i.e. analog video out.
+ * Set as input with no bias.
+ */
+ ycbcr {
+ ycbcr_default_mode: ycbcr_default {
+ default_mux {
+ ste,function = "ycbcr";
+ ste,pins = "ycbcr0123_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO6_Y18",
+ "GPIO7_AA20",
+ "GPIO8_W18",
+ "GPIO9_AA19";
+ input-enable;
+ bias-disable;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 139298043685..d58513b08a6d 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,16 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 6,7,8 and 9 are muxed in YCBCR0123
- * configured in INPUT PULL UP
- */
- AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
- AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
- AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
- AB8500_PIN_HOG("GPIO8_W18", in_nopull),
- AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
-
- /*
* pins 14,15 are muxed in PWM1 and PWM2
* configured in INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 01/10] ARM: ux500: move AB8500 GPIOs to device tree
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
Move the AB8500 muxing and biasing settings over from the board
file to the device tree, include it in the reference designs using
the AB8500: HREF prior to v60, v60plus and Snowball. Set up these
GPIO lines using hogs, just like in the board file.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 253 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/ste-hrefprev60.dtsi | 1 +
arch/arm/boot/dts/ste-hrefv60plus.dtsi | 1 +
arch/arm/boot/dts/ste-snowball.dts | 1 +
arch/arm/mach-ux500/board-mop500-pins.c | 79 ----------
5 files changed, 256 insertions(+), 79 deletions(-)
create mode 100644 arch/arm/boot/dts/ste-href-ab8500.dtsi
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
new file mode 100644
index 000000000000..58b00d0f023e
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -0,0 +1,253 @@
+/*
+ * Copyright 2014 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+ soc {
+ prcmu at 80157000 {
+ ab8500 {
+ ab8500-gpio {
+ /* Hog a few default settings */
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio2_default_mode>,
+ <&gpio4_default_mode>,
+ <&gpio10_default_mode>,
+ <&gpio11_default_mode>,
+ <&gpio12_default_mode>,
+ <&gpio13_default_mode>,
+ <&gpio16_default_mode>,
+ <&gpio24_default_mode>,
+ <&gpio25_default_mode>,
+ <&gpio36_default_mode>,
+ <&gpio37_default_mode>,
+ <&gpio38_default_mode>,
+ <&gpio39_default_mode>,
+ <&gpio42_default_mode>,
+ <&gpio26_default_mode>,
+ <&gpio35_default_mode>;
+
+ /*
+ * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
+ * are muxed in as GPIO, and configured as INPUT PULL DOWN
+ */
+ gpio2 {
+ gpio2_default_mode: gpio2_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio2_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO2_T9";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio4 {
+ gpio4_default_mode: gpio4_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio4_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO4_W2";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio10 {
+ gpio10_default_mode: gpio10_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio10_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO10_U17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio11 {
+ gpio11_default_mode: gpio11_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio11_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO11_AA18";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio12 {
+ gpio12_default_mode: gpio12_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio12_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO12_U16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio13 {
+ gpio13_default_mode: gpio13_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio13_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO13_W17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio16 {
+ gpio16_default_mode: gpio16_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio16_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO16_F15";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio24 {
+ gpio24_default_mode: gpio24_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio24_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO24_T14";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio25 {
+ gpio25_default_mode: gpio25_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio25_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO25_R16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio36 {
+ gpio36_default_mode: gpio36_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio36_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO36_A17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio37 {
+ gpio37_default_mode: gpio37_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio37_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO37_E15";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio38 {
+ gpio38_default_mode: gpio38_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio38_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO38_C17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio39 {
+ gpio39_default_mode: gpio39_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio39_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO39_E16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio42 {
+ gpio42_default_mode: gpio42_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio42_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO42_U2";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /*
+ * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW
+ */
+ gpio26 {
+ gpio26_default_mode: gpio26_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio26_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO26_M16";
+ output-low;
+ };
+ };
+ };
+ gpio35 {
+ gpio35_default_mode: gpio35_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio35_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO35_W15";
+ output-low;
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index 40f0ecdf9303..abc762e24fcb 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -12,6 +12,7 @@
*/
#include "ste-dbx5x0.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-href.dtsi"
/ {
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 3b6d1181939b..c2341061b943 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -10,6 +10,7 @@
*/
#include "ste-dbx5x0.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-href.dtsi"
/ {
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 97d5d21b7db7..a2f632d0be2a 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -11,6 +11,7 @@
/dts-v1/;
#include "ste-dbx5x0.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-href-family-pinctrl.dtsi"
/ {
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index f63619b69113..139298043685 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -18,7 +18,6 @@
/* These simply sets bias for pins */
#define BIAS(a,b) static unsigned long a[] = { b }
-BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
@@ -50,10 +49,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
- /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
- AB8500_MUX_HOG("gpio2_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO2_T9", in_pd),
-
/* Sysclkreq4 */
AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
@@ -61,10 +56,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
- /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
- AB8500_MUX_HOG("gpio4_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO4_W2", in_pd),
-
/*
* pins 6,7,8 and 9 are muxed in YCBCR0123
* configured in INPUT PULL UP
@@ -76,22 +67,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
/*
- * pins 10,11,12 and 13 are muxed in GPIO
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio10_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO10_U17", in_pd),
-
- AB8500_MUX_HOG("gpio11_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO11_AA18", in_pd),
-
- AB8500_MUX_HOG("gpio12_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO12_U16", in_pd),
-
- AB8500_MUX_HOG("gpio13_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO13_W17", in_pd),
-
- /*
* pins 14,15 are muxed in PWM1 and PWM2
* configured in INPUT PULL DOWN
*/
@@ -102,13 +77,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_HOG("GPIO15_B17", in_pd),
/*
- * pins 16 is muxed in GPIO
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio16_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO14_F14", in_pd),
-
- /*
* pins 17,18,19 and 20 are muxed in AUDIO interface 1
* configured in INPUT PULL DOWN
*/
@@ -128,23 +96,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_HOG("GPIO23_G19", in_pd),
/*
- * pins 24,25 are muxed in GPIO
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio24_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO24_T14", in_pd),
-
- AB8500_MUX_HOG("gpio25_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO25_R16", in_pd),
-
- /*
- * pins 26 is muxed in GPIO
- * configured in OUTPUT LOW
- */
- AB8500_MUX_HOG("gpio26_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO26_M16", out_lo),
-
- /*
* pins 27,28 are muxed in DMIC12
* configured in INPUT PULL DOWN
*/
@@ -176,42 +127,12 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_HOG("GPIO34_R17", in_pd),
/*
- * pins 35 is muxed in GPIO
- * configured in OUTPUT LOW
- */
- AB8500_MUX_HOG("gpio35_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO35_W15", in_pd),
-
- /*
- * pins 36,37,38 and 39 are muxed in GPIO
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio36_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO36_A17", in_pd),
-
- AB8500_MUX_HOG("gpio37_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO37_E15", in_pd),
-
- AB8500_MUX_HOG("gpio38_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO38_C17", in_pd),
-
- AB8500_MUX_HOG("gpio39_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO39_E16", in_pd),
-
- /*
* pins 40 and 41 are muxed in MODCSLSDA
* configured INPUT PULL DOWN
*/
AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
AB8500_PIN_HOG("GPIO40_T19", in_pd),
AB8500_PIN_HOG("GPIO41_U19", in_pd),
-
- /*
- * pins 42 is muxed in GPIO
- * configured INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio42_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO42_U2", in_pd),
};
static struct pinctrl_map __initdata ab8505_pinmap[] = {
--
1.8.5.3
^ permalink raw reply related
* [PATCH v2 5/5] ARM: bcm_defconfig: Enable PWM and Backlight
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Enable PWM drivers and the PWM-based backlight driver.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
arch/arm/configs/bcm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 2519d6d..b1898c3 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -84,6 +84,7 @@ CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
@@ -97,6 +98,7 @@ CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_PWM=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 4/5] ARM: dts: Enable the PWM for bcm28155 AP board
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Mark the PWM as enabled on the bcm28155 AP board.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
arch/arm/boot/dts/bcm28155-ap.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index 5ff2382..37c72eb 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -66,6 +66,10 @@
status = "okay";
};
+ pwm: pwm at 3e01a000 {
+ status = "okay";
+ };
+
usbotg: usb at 3f120000 {
status = "okay";
};
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 3/5] ARM: dts: Declare the PWM for bcm11351 (bcm281xx)
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Add the device tree node for the PWM on bcm11351 SoCs.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
arch/arm/boot/dts/bcm11351.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index e491b82..5296c3d 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -191,6 +191,14 @@
status = "disabled";
};
+ pwm: pwm at 3e01a000 {
+ compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
+ reg = <0x3e01a000 0xcc>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
clocks {
bsc1_clk: bsc1 {
compatible = "fixed-clock";
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 2/5] pwm: kona: Introduce Kona PWM controller support
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Add support for the six-channel Kona PWM controller found on Broadcom
mobile SoCs like bcm281xx.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
drivers/pwm/Kconfig | 10 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-bcm-kona.c | 291 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 302 insertions(+)
create mode 100644 drivers/pwm/pwm-bcm-kona.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 22f2f28..1fd42af 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -62,6 +62,16 @@ config PWM_ATMEL_TCB
To compile this driver as a module, choose M here: the module
will be called pwm-atmel-tcb.
+config PWM_BCM_KONA
+ tristate "Kona PWM support"
+ depends on ARCH_BCM_MOBILE
+ default y
+ help
+ Generic PWM framework driver for Broadcom Kona PWM block.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-bcm-kona.
+
config PWM_BFIN
tristate "Blackfin PWM support"
depends on BFIN_GPTIMERS
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index d8906ec..7413090 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_PWM_SYSFS) += sysfs.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
+obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
new file mode 100644
index 0000000..631ec14
--- /dev/null
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#define PWM_CONTROL_OFFSET (0x00000000)
+#define PWM_CONTROL_SMOOTH_SHIFT(chan) (24 + (chan))
+#define PWM_CONTROL_TYPE_SHIFT(chan) (16 + (chan))
+#define PWM_CONTROL_POLARITY_SHIFT(chan) (8 + (chan))
+#define PWM_CONTROL_ENABLE_SHIFT(chan) (chan)
+
+#define PRESCALE_OFFSET (0x00000004)
+#define PRESCALE_SHIFT(chan) ((chan) << 2)
+#define PRESCALE_MASK(chan) (0x7 << PRESCALE_SHIFT(chan))
+#define PRESCALE_MIN (0x00000000)
+#define PRESCALE_MAX (0x00000007)
+
+#define PERIOD_COUNT_OFFSET(chan) (0x00000008 + ((chan) << 3))
+#define PERIOD_COUNT_MIN (0x00000002)
+#define PERIOD_COUNT_MAX (0x00ffffff)
+
+#define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + ((chan) << 3))
+#define DUTY_CYCLE_HIGH_MIN (0x00000000)
+#define DUTY_CYCLE_HIGH_MAX (0x00ffffff)
+
+struct kona_pwmc {
+ struct pwm_chip chip;
+ void __iomem *base;
+ struct clk *clk;
+};
+
+static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
+{
+ /* New settings take effect on rising edge of enable bit */
+ unsigned long value = readl(kp->base + PWM_CONTROL_OFFSET);
+
+ value &= ~(1 << PWM_CONTROL_ENABLE_SHIFT(chan));
+ writel(value, kp->base + PWM_CONTROL_OFFSET);
+
+ value |= (1 << PWM_CONTROL_ENABLE_SHIFT(chan));
+ writel(value, kp->base + PWM_CONTROL_OFFSET);
+}
+
+static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
+ int duty_ns, int period_ns)
+{
+ struct kona_pwmc *kp = dev_get_drvdata(chip->dev);
+ u64 val, div, clk_rate;
+ unsigned long prescale = PRESCALE_MIN, pc, dc;
+ unsigned int value, chan = pwm->hwpwm;
+
+ /*
+ * Find period count, duty count and prescale to suit duty_ns and
+ * period_ns. This is done according to formulas described below:
+ *
+ * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
+ * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
+ *
+ * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
+ * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
+ */
+
+ clk_rate = clk_get_rate(kp->clk);
+
+ /* There is polarity support in HW but it is easier to manage in SW */
+ if (pwm->polarity == PWM_POLARITY_INVERSED)
+ duty_ns = period_ns - duty_ns;
+
+ while (1) {
+ div = 1000000000;
+ div *= 1 + prescale;
+ val = clk_rate * period_ns;
+ pc = div64_u64(val, div);
+ val = clk_rate * duty_ns;
+ dc = div64_u64(val, div);
+
+ /* If duty_ns or period_ns are not achievable then return */
+ if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN)
+ return -EINVAL;
+
+ /* If pc and dc are in bounds, the calculation is done */
+ if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
+ break;
+
+ /* Otherwise, increase prescale and recalculate pc and dc */
+ if (++prescale > PRESCALE_MAX)
+ return -EINVAL;
+ }
+
+ /* If the PWM channel is enabled, write the settings to the HW */
+ if (test_bit(PWMF_ENABLED, &pwm->flags)) {
+ value = readl(kp->base + PRESCALE_OFFSET);
+ value &= ~PRESCALE_MASK(chan);
+ value |= prescale << PRESCALE_SHIFT(chan);
+ writel(value, kp->base + PRESCALE_OFFSET);
+
+ writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
+
+ writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
+
+ kona_pwmc_apply_settings(kp, chan);
+ }
+
+ return 0;
+}
+
+static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
+ enum pwm_polarity polarity)
+{
+ /*
+ * The framework only allows the polarity to be changed when a PWM is
+ * disabled so no immediate action is required here. When a channel is
+ * enabled, the polarity gets handled as part of the re-config step.
+ */
+
+ return 0;
+}
+
+static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct kona_pwmc *kp = dev_get_drvdata(chip->dev);
+ int ret;
+
+ /*
+ * The PWM framework does not clear the enable bit in the flags if an
+ * error is returned from a PWM driver's enable function so it must be
+ * cleared here if any trouble is encountered.
+ */
+
+ ret = clk_prepare_enable(kp->clk);
+ if (ret < 0) {
+ dev_err(chip->dev, "failed to enable clock: %d\n", ret);
+ clear_bit(PWMF_ENABLED, &pwm->flags);
+ return ret;
+ }
+
+ ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
+ if (ret < 0) {
+ clk_disable_unprepare(kp->clk);
+ clear_bit(PWMF_ENABLED, &pwm->flags);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct kona_pwmc *kp = dev_get_drvdata(chip->dev);
+ unsigned int chan = pwm->hwpwm;
+
+ /*
+ * The "enable" bits in the control register only affect when settings
+ * start to take effect so the only real way to disable the PWM output
+ * is to program a zero duty cycle.
+ */
+
+ writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
+ kona_pwmc_apply_settings(kp, chan);
+
+ /*
+ * When the PWM clock is disabled, the output is pegged high or low
+ * depending on its state at that instant. To guarantee that the new
+ * settings have taken effect and the output is low a delay of 400ns is
+ * required.
+ */
+
+ ndelay(400);
+
+ clk_disable_unprepare(kp->clk);
+}
+
+static const struct pwm_ops kona_pwm_ops = {
+ .config = kona_pwmc_config,
+ .set_polarity = kona_pwmc_set_polarity,
+ .enable = kona_pwmc_enable,
+ .disable = kona_pwmc_disable,
+ .owner = THIS_MODULE,
+};
+
+static int kona_pwmc_probe(struct platform_device *pdev)
+{
+ struct kona_pwmc *kp;
+ struct resource *res;
+ unsigned int chan, value;
+ int ret = 0;
+
+ kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL);
+ if (kp == NULL)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, kp);
+
+ kp->chip.dev = &pdev->dev;
+ kp->chip.ops = &kona_pwm_ops;
+ kp->chip.base = -1;
+ kp->chip.npwm = 6;
+ kp->chip.of_xlate = of_pwm_xlate_with_flags;
+ kp->chip.of_pwm_n_cells = 3;
+ kp->chip.can_sleep = true;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ kp->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(kp->base))
+ return PTR_ERR(kp->base);
+
+ kp->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(kp->clk)) {
+ dev_err(&pdev->dev, "failed to get clock: %ld\n",
+ PTR_ERR(kp->clk));
+ return PTR_ERR(kp->clk);
+ }
+
+ ret = clk_prepare_enable(kp->clk);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
+ return ret;
+ }
+
+ /* Set smooth mode, push/pull, and normal polarity for all channels */
+ for (value = 0, chan = 0; chan < kp->chip.npwm; chan++) {
+ value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
+ value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
+ value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
+ }
+ writel(value, kp->base + PWM_CONTROL_OFFSET);
+
+ clk_disable_unprepare(kp->clk);
+
+ ret = pwmchip_add(&kp->chip);
+ if (ret < 0)
+ dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
+
+ return ret;
+}
+
+static int kona_pwmc_remove(struct platform_device *pdev)
+{
+ struct kona_pwmc *kp = platform_get_drvdata(pdev);
+ unsigned int chan;
+
+ for (chan = 0; chan < kp->chip.npwm; chan++)
+ if (test_bit(PWMF_ENABLED, &kp->chip.pwms[chan].flags))
+ clk_disable_unprepare(kp->clk);
+
+ return pwmchip_remove(&kp->chip);
+}
+
+static const struct of_device_id bcm_kona_pwmc_dt[] = {
+ { .compatible = "brcm,kona-pwm" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);
+
+static struct platform_driver kona_pwmc_driver = {
+
+ .driver = {
+ .name = "bcm-kona-pwm",
+ .of_match_table = bcm_kona_pwmc_dt,
+ },
+ .probe = kona_pwmc_probe,
+ .remove = kona_pwmc_remove,
+};
+
+module_platform_driver(kona_pwmc_driver);
+
+MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
+MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
+MODULE_DESCRIPTION("Driver for Kona PWM controller");
+MODULE_LICENSE("GPL v2");
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 1/5] Documentation: dt: Add Kona PWM binding
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Add the binding description for the Kona PWM controller found on Broadcom's
mobile SoCs.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
.../devicetree/bindings/pwm/bcm-kona-pwm.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt
diff --git a/Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt b/Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt
new file mode 100644
index 0000000..c8e2d13
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt
@@ -0,0 +1,24 @@
+Broadcom Kona PWM controller device tree bindings
+
+This controller has 6 channels.
+
+Required Properties :
+- compatible: should be "brcm,kona-pwm"
+- reg: physical base address and length of the controller's registers
+- clocks: phandle + clock specifier pair for the external clock
+- #pwm-cells: should be 3. The first cell specifies the per-chip index
+ of the PWM to use, the second cell is the period in nanoseconds, and
+ the third cell is the flags.
+
+Refer to pwm/pwm.txt for generic pwm controller node properties.
+
+Refer to clocks/clock-bindings.txt for generic clock consumer properties.
+
+Example:
+
+pwm: pwm at 3e01a000 {
+ compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
+ reg = <0x3e01a000 0xc4>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+};
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 0/5] Add Broadcom Kona PWM Support
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
This series introduces the driver for the Kona PWM controller found in
Broadcom mobile SoCs like bcm281xx and updates the device tree and the
defconfig to enable use of this hardware on the bcm28155 AP board.
Changes since v1:
- Fixed up macros to be clearer and more complete
- Corrected spelling and punctuation mistakes
- Added support for polarity
- Made peripheral clock use more efficient
- Made prescale and duty computation clearer
- Moved Makefile addition to keep alphabetical
- Split complex lines into multiple steps
Tim Kryger (5):
Documentation: dt: Add Kona PWM binding
pwm: kona: Introduce Kona PWM controller support
ARM: dts: Declare the PWM for bcm11351 (bcm281xx)
ARM: dts: Enable the PWM for bcm28155 AP board
ARM: bcm_defconfig: Enable PWM and Backlight
.../devicetree/bindings/pwm/bcm-kona-pwm.txt | 24 ++
arch/arm/boot/dts/bcm11351.dtsi | 8 +
arch/arm/boot/dts/bcm28155-ap.dts | 4 +
arch/arm/configs/bcm_defconfig | 2 +
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-bcm-kona.c | 291 +++++++++++++++++++++
7 files changed, 340 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt
create mode 100644 drivers/pwm/pwm-bcm-kona.c
--
1.8.0.1
^ permalink raw reply
* [PATCH] arm64: Add architecture support for PCI
From: Arnd Bergmann @ 2014-02-04 19:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqLN4RjVzNCfZ50K44RcP61Z8zFOVnpY1+CfVFz_QnSBEg@mail.gmail.com>
On Tuesday 04 February 2014, Rob Herring wrote:
> > Here is how a sane person would read SBSA to create a compliant
> > implementation:
>
> s/sane/software/
> > Here is how a crazy person would read the same sentence in the SBSA:
>
> s/crazy/hardware/
Not much of a difference, apparently ...
> My money is on the latter. I think non-PCI implementations of xHCI
> interfaces will be common. This was certainly the case at Calxeda in
> what was believed to be a SBSA compliant SOC.
I just looked up the EHCI and xHCI specs and am shocked to see that
the PCI config space access for both is an optional part of the
spec, so that assertion may well have been correct.
On the other hand, it does seem impossible to create a compliant
AHCI implementation without making it show up as a PCI function,
so any SBSA compliant SoC that contains AHCI already has to have
all the bits for doing the same on USB.
> However, I think PCI
> device or not is the least of the issues and all the other examples
> you list are the difficult ones to deal with.
Agreed. But if they get the difficult problems right, it's
trivial to also do the PCI config space either in the way
that Jason described, or as a separate PCI domain. In the worst
case, it could still be faked up by a secure-mode firmware
catching all config space accesses.
Arnd
^ permalink raw reply
* [PATCH] ARM: pxa: fix various compilation problems
From: Linus Walleij @ 2014-02-04 19:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4895932.cC8EyYOxb5@wuerfel>
On Tue, Feb 4, 2014 at 3:56 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tuesday 04 February 2014 13:53:07 Linus Walleij wrote:
>> Hi ARM SoC folks: please apply this patch directly to the ARM
>> SoC tree fixes branch if you are happy with it.
>
> It's also needed for 3.13-backports, right?
Yes. Tagging for stable # v3.13+ should do the trick.
Yours,
Linus Walleij
^ permalink raw reply
* [ath9k-devel] [PATCH 1/3] ath9k: Fix build error on ARM
From: Joe Perches @ 2014-02-04 19:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3469296.SINb5BZOG8@wuerfel>
On Tue, 2014-02-04 at 19:40 +0100, Arnd Bergmann wrote:
> On Tuesday 04 February 2014 08:36:36 Joe Perches wrote:
> > On Tue, 2014-02-04 at 08:03 +0100, Holger Schurig wrote:
> > > Joe, look in linux/arch/arm/include/asm/delay.h. The macro udelay
> > > cannot handle large values because of lost-of-precision.
> > >
> > > IMHO udelay on ARM is broken, because it also cannot work with fast
> > > ARM processors (where bogomips >= 3355, which is in sight now). It's
> > > just not broken enought that someone did something against it ... so
> > > the current kludge is good enought.
> >
> > Maybe something like this would be better?
> >
>
> I actually like the fact that we get link errors for insane 'udelay'
> times.
For static values yes, for computed values no.
This emits a warning/dump_stack on the non-static
values. It could also emit some similar #warning
on static values > insane too.
^ permalink raw reply
* [PATCH v3 2/5] ASoC: tda998x: add a codec driver for the TDA998x
From: Mark Brown @ 2014-02-04 19:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204195921.5ace6163@armhf>
On Tue, Feb 04, 2014 at 07:59:21PM +0100, Jean-Francois Moine wrote:
> Mark Brown <broonie@kernel.org> wrote:
> > You shouldn't be representing this as a separate node in the DT unless
> > there really is a distinct and reusable IP, otherwise you're putting
> > Linux implementation details in there. Describe the hardware, not the
> > implemementation.
> If there is no 'compatible' node for the tda998x CODEC in the DT, the
> simple-card is not usable, simply because you want the CODEC DAIs to be
> defined by 'phandle + index' instead of by DAI name.
This is a bit circular, though - it's only happening because you decided
to push everything onto a subnode in the DT. If you just work with the
existing device this is no different to any other device.
> > > I don't understand. The tda CODEC can only be used with the TDA998x I2C
> > > driver. It might have been included in the tda998x source as well.
> > You shouldn't have the default settings there at all, that's not the
> > normal idiom for MFDs. I'd also not expect to have to build the CODEC
> > driver just because I built the DRM component.
> As the tda998x handles audio in HDMI, it would be a pity if you should
> connect an other cable to your screen.
My screen doesn't have any speakers anyway :P (I'm writing this on a
computer with the monitor connected via HDMI). Besides, this is more
about build coverage stuff than anything else.
> So, as I understand from your remarks, the CODEC should be included in
> the tda998x driver, and, then, as the simple-card cannot be used, there
> should be a Cubox specific audio card driver for the (kirkwood audio +
> tda998x HDMI + S/PDIF) set. Am I right?
No, it shouldn't be.
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* [PATCH v3 0/4] In-kernel PSCI v0.2 emulation for KVM ARM/ARM64
From: Christoffer Dall @ 2014-02-04 19:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391507296-2099-1-git-send-email-anup.patel@linaro.org>
On Tue, Feb 04, 2014 at 03:18:12PM +0530, Anup Patel wrote:
> Currently, KVM ARM/ARM64 only provides in-kernel emulation of Power State
> and Coordination Interface (PSCI) v0.1.
>
> This patchset aims at providing newer PSCI v0.2 for KVM ARM/ARM64 VCPUs
> such that it does not break current KVM ARM/ARM64 ABI. Also, the patchset
> provides emulation of only few PSCI v0.2 functions such as PSCI_VERSION,
> CPU_ON, and CPU_OFF. Emulation of other PSCI v0.2 functions will be added
> later.
>
> The user space tools (i.e. QEMU or KVMTOOL) will have to explicitly enable
> KVM_ARM_VCPU_PSCI_0_2 feature using KVM_ARM_VCPU_INIT ioctl for providing
> PSCI v0.2 to VCPUs.
>
> Changlog:
>
> V3:
> - Make KVM_ARM_VCPU_PSCI_0_2 feature experiementatl for now so that
> it fails for user space till all mandatory PSCI v0.2 functions are
> emulated by KVM ARM/ARM64
> - Have separate patch for making KVM_ARM_VCPU_PSCI_0_2 feature available
> to user space. This patch can be defferred for now.
>
I think we just want the feature bit when there's proper PSCI 0.2
support as per Mark's comments, so I'll hold off with reviewing until we
have a more complete patch set.
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH v2 0/5] net: phy: Ethernet PHY powerdown optimization
From: Sebastian Hesselbarth @ 2014-02-04 19:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20131217.144313.1563516273987934449.davem@davemloft.net>
On 12/17/2013 08:43 PM, David Miller wrote:
> From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Date: Fri, 13 Dec 2013 10:20:24 +0100
>
>> This is v2 of the ethernet PHY power optimization patches to reduce
>> power consumption of network PHYs with link that are either unused or
>> the corresponding netdev is down.
>>
>> Compared to the last version, this patch set drops a patch to disable
>> unused PHYs after late initcall, as it is not compatible with a modular
>> mdio bus [1]. I'll investigate different ways to have a modular mdio bus
>> driver get notified when driver loading is done.
>>
>> Again, a branch with v2 applied to v3.13-rc2 can also be found at
>> https://github.com/shesselba/linux-dove.git topic/ethphy-power-v2
>>
>> [1] http://www.spinics.net/lists/arm-kernel/msg293028.html
>
> Series applied, thanks.
>
David, Mungunthan, Florian,
as expected the above patches create a Linux to bootloader dependency
that surfaces dumb bootloaders not initializing PHYs correctly.
Andrew has a Kirkwood based board that does not power-up and restart
auto-negotiation on the powered down PHY after a warm restart. While
this specific bootloader allows a soft-workaround by issuing the
required PHY writes before accessing the interface, others may not.
I think we should allow the user to soft-disable the automatic
power-down of PHYs, i.e. by exploiting a kernel parameter.
Do you have any preference for naming it? My call would be something
like libphy.suspend_halted = [0,1] with 1 being the default.
Sebastian
^ permalink raw reply
* [PATCH v2 0/6] ARM: sunxi: Add driver for SD/MMC hosts found on allwinner sunxi SOCs
From: David Lanzendörfer @ 2014-02-04 19:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch>
Hi
I forgot to mention that the autoparenting patch of Emilios is a crucial
depency...
http://git.o2s.ch/?p=linux-next.git;a=commit;h=f8e936772672a3a6ec934558d2a7aef030c663c4
Without it, the clock will return the wrong value and the card will refuse to
initialize
regards
david
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* Extending OPP bindings
From: Nishanth Menon @ 2014-02-04 19:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204182220.GQ22609@sirena.org.uk>
On 02/04/2014 12:22 PM, Mark Brown wrote:
> On Tue, Feb 04, 2014 at 12:01:11PM -0600, Nishanth Menon wrote:
>
>> As long as the key to the data sets are all the same (frequency),
>> information in data set #0 is maintained. It would be in our common
>> long term interest to maintain the split.
>
> You're assuming that the frequency is a unique key here. That may not
> be the case, for example two OPPs might have the same CPU clock
> (assuming that's the frequency you're referring to) but different bus
> clocking and of course the CPUs or CPU clusters might be individually
> scalable (this is common in big.LITTLE designs I think).
>
Which is why OPPs are maintained per device, bus OPPs belong to bus
device (in TI terminology, we'd be talking of cross domain dependency
here for maintaining asynchronous bridge timing closure constraints -
but ofcourse, other SoCs may or maynot have such constraints). For
scaling bus frequency, we already have infrastructure in place - clock
notifiers - discussion of using that is much deeper topic of it's own.
for each processor that is uniquely transitioning, we'd have it's own
sets of OPPs - the correct representation of the device node is the
key there.
--
Regards,
Nishanth Menon
^ permalink raw reply
* [PATCH 09/10] watchdog: xilinx: Add missing binding
From: Arnd Bergmann @ 2014-02-04 19:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4c4539fe-e810-4c0a-9a01-c1e4c67ea661@AM1EHSMHS007.ehs.local>
On Monday 03 February 2014, Michal Simek wrote:
> On 02/03/2014 04:32 PM, Arnd Bergmann wrote:
> > On Monday 03 February 2014 16:13:47 Michal Simek wrote:
> >> Intention wasn't to fix binding but document current one
> >> which is in mainline for a long time.
> >
> > Ok, I see.
> >
> >> Apart of this - yes, wdt-enable-once is nowayout and wdt-interval should be timeout
> >> is seconds, and clock-frequency should go out and use CCF for getting clock.
> >
> > Could we make a common binding then, and document that the xilinx
> > watchdog can optionally provide either one?
>
> Do you mean to have 2 DT bindings?
>
> This binding is used from 2011-07.
> It means it was generated for all hw designs at least from this time.
> I would say from DT usage on Microblaze because it is not special case
> in our dt generator.
I certainly wasn't suggesting to break the binding, quite the contrary.
What I tried to say is that the properties look like they should be
useful for different kinds of watchdogs, not just xilinx, so it would
be good to have a common definition using generic strings.
The xilinx driver would definitely have to keep supporting the traditional
property names, but it could also support the generic names in the
future.
> xlnx,XXX are XXX parameters which you have to setup in tools
> and get synthesized. This is valid for all xilinx IPs. We have full
> IP description by generating xlnx,XXX parameters directly from tools
> because we know all variants which can happen.
>
> Just back to your previous post:
> "I'm not sure about the enable-once flag, which seems to just map to the
> "nowayout" watchdog option that is not a hardware feature at all"
> this is hw feature which you can select in tools because this is fpga. :-)
Ah, so you mean the properties are not settings that the driver
programs into the hardware, but they are hardware properties that the
driver reports to user space?
Arnd
^ permalink raw reply
* [PATCH v2 6/6] ARM: dts: sun5i: Add support for mmc
From: David Lanzendörfer @ 2014-02-04 19:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch>
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 30 +++++++++++++++
arch/arm/boot/dts/sun5i-a10s.dtsi | 44 ++++++++++++++++++++++
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 15 ++++++++
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 15 ++++++++
arch/arm/boot/dts/sun5i-a13.dtsi | 37 +++++++++++++++++++
5 files changed, 141 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 3c9f8b3..7189adf55 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -34,7 +34,37 @@
};
};
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_olinuxino_micro>;
+ cd-gpios = <&pio 6 1 0>; /* PG1 */
+ status = "okay";
+ };
+
+ mmc1: mmc at 01c10000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ pinctrl-1 = <&mmc1_cd_pin_olinuxino_micro>;
+ cd-gpios = <&pio 6 13 0>; /* PG13 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
+ mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin at 0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin at 0 {
+ allwinner,pins = "PG13";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
led_pins_olinuxino: led_pins at 0 {
allwinner,pins = "PE3";
allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ea16054..abff7f8 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -293,6 +293,36 @@
#size-cells = <0>;
};
+ mmc0: mmc at 01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <32>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc at 01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <33>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc at 01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <34>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
intc: interrupt-controller at 01c20400 {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
@@ -363,6 +393,20 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0 at 0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ mmc1_pins_a: mmc1 at 0 {
+ allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
+ allwinner,function = "mmc1";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
};
timer at 01c20c00 {
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index fe2ce0a..6ae5867 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -20,7 +20,22 @@
compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
soc at 01c00000 {
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_olinuxinom>;
+ cd-gpios = <&pio 6 0 0>; /* PG0 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
+ mmc0_cd_pin_olinuxinom: mmc0_cd_pin at 0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
led_pins_olinuxinom: led_pins at 0 {
allwinner,pins = "PG9";
allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index a4ba5ff..b23237b 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -19,7 +19,22 @@
compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
soc at 01c00000 {
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_olinuxino>;
+ cd-gpios = <&pio 6 0 0>; /* PG0 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
+ mmc0_cd_pin_olinuxino: mmc0_cd_pin at 0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
led_pins_olinuxino: led_pins at 0 {
allwinner,pins = "PG9";
allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 320335a..5d71c82 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -274,6 +274,36 @@
#size-cells = <1>;
ranges;
+ mmc0: mmc at 01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <32>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc at 01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <33>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc at 01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <34>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
intc: interrupt-controller at 01c20400 {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
@@ -326,6 +356,13 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0 at 0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
};
timer at 01c20c00 {
^ permalink raw reply related
* [PATCH v2 5/6] ARM: dts: sun4i: Add support for mmc
From: David Lanzendörfer @ 2014-02-04 19:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch>
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 8 ++++
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 8 ++++
arch/arm/boot/dts/sun4i-a10.dtsi | 54 ++++++++++++++++++++++++++++
3 files changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index d4b081d..a879ef3 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -35,6 +35,14 @@
};
};
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
emac_power_pin_a1000: emac_power_pin at 0 {
allwinner,pins = "PH15";
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b139ee6..20b976a 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -33,6 +33,14 @@
};
};
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
led_pins_cubieboard: led_pins at 0 {
allwinner,pins = "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 040bb0e..c941ca3 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -330,6 +330,46 @@
#size-cells = <0>;
};
+ mmc0: mmc at 01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <32>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc at 01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <33>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc at 01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <34>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc at 01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <35>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
intc: interrupt-controller at 01c20400 {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
@@ -400,6 +440,20 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0 at 0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
};
timer at 01c20c00 {
^ permalink raw reply related
* [PATCH v2 4/6] ARM: dts: sun7i: Add support for mmc
From: David Lanzendörfer @ 2014-02-04 19:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch>
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8 +++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8 +++
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +++++++++
arch/arm/boot/dts/sun7i-a20.dtsi | 61 +++++++++++++++++++++++
4 files changed, 100 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 5c51cb8..ae800b6 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -34,6 +34,14 @@
};
};
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
led_pins_cubieboard2: led_pins at 0 {
allwinner,pins = "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f9dcb61..370cef84 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -19,6 +19,14 @@
compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
soc at 01c00000 {
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
led_pins_cubietruck: led_pins at 0 {
allwinner,pins = "PH7", "PH11", "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index ead3013..46dbe5b 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -34,7 +34,30 @@
};
};
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
+ mmc3: mmc at 01c12000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ pinctrl-1 = <&mmc3_cd_pin_olinuxinom>;
+ cd-gpios = <&pio 7 11 0>; /* PH11 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
+ mmc3_cd_pin_olinuxinom: mmc3_cd_pin at 0 {
+ allwinner,pins = "PH11";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
led_pins_olinuxino: led_pins at 0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 119f066..4cd6210 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -355,6 +355,46 @@
#size-cells = <0>;
};
+ mmc0: mmc at 01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 32 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc at 01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 33 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc at 01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 34 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc at 01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 35 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
pio: pinctrl at 01c20800 {
compatible = "allwinner,sun7i-a20-pinctrl";
reg = <0x01c20800 0x400>;
@@ -432,6 +472,27 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0 at 0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ mmc3_pins_a: mmc3 at 0 {
+ allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
+ allwinner,function = "mmc3";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
};
timer at 01c20c00 {
^ permalink raw reply related
* [PATCH v2 3/6] ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
From: David Lanzendörfer @ 2014-02-04 19:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch>
From: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
include/linux/clk/sunxi.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 include/linux/clk/sunxi.h
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 0000000..1ef5c89
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SUNXI_H_
+#define __LINUX_CLK_SUNXI_H_
+
+#include <linux/clk.h>
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
+
+#endif
^ permalink raw reply related
* [PATCH v2 2/6] clk: sunxi: Implement MMC phase control
From: David Lanzendörfer @ 2014-02-04 19:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch>
From: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abb6c5a..33b9977 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
/**
+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
+ */
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
+{
+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+ struct clk_composite *composite = to_clk_composite(hw);
+ struct clk_hw *rate_hw = composite->rate_hw;
+ struct clk_factors *factors = to_clk_factors(rate_hw);
+ unsigned long flags = 0;
+ u32 reg;
+
+ if (factors->lock)
+ spin_lock_irqsave(factors->lock, flags);
+
+ reg = readl(factors->reg);
+
+ /* set sample clock phase control */
+ reg &= ~(0x7 << 20);
+ reg |= ((sample & 0x7) << 20);
+
+ /* set output clock phase control */
+ reg &= ~(0x7 << 8);
+ reg |= ((output & 0x7) << 8);
+
+ writel(reg, factors->reg);
+
+ if (factors->lock)
+ spin_unlock_irqrestore(factors->lock, flags);
+}
+
+
+/**
* sunxi_factors_clk_setup() - Setup function for factor clocks
*/
^ permalink raw reply related
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