* [PATCH 00/18] arm64: GICv3 support
From: Marc Zyngier @ 2014-02-05 13:30 UTC (permalink / raw)
To: linux-arm-kernel
GICv3 is the base for a new generation of interrupt controllers
designed to overcome some of the most glaring limitations of GICv2.
Some of the features are:
- Support for more than 8 CPUs (a lot more...)
- System registers for CPU interface access (GICC, GICV, GICH)
- Message based interrupts
This patch series currently support:
- Affinity Routing
- System Registers
- Non-Secure Group-1 interrupts only
- KVM support (GICv3 host, GICv2 guest)
What is *not yet* supported in this series:
- LPI/ITS/MSI (patches are available in the below branch,
though still in development)
- KVM GICv3 guest support (requires GICv3 distributor emulation)
- Any form of power management
- 32bit systems
To be built, this code requires a fairly recent compiler/binutils
combo. Linaro 13.06 seems to do the trick. This has been tested on the
ARM FVP model, with non-regressions run on a VExpress TC-2.
The code is also available at the following location:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv3
Marc Zyngier (18):
arm64: initial support for GICv3
arm64: GICv3 device tree binding documentation
arm64: boot protocol documentation update for GICv3
KVM: arm/arm64: vgic: move GICv2 registers to their own structure
KVM: ARM: vgic: introduce vgic_ops and LR manipulation primitives
KVM: ARM: vgic: abstract access to the ELRSR bitmap
KVM: ARM: vgic: abstract EISR bitmap access
KVM: ARM: vgic: abstract MISR decoding
KVM: ARM: vgic: move underflow handling to vgic_ops
KVM: ARM: vgic: abstract VMCR access
KVM: ARM: vgic: introduce vgic_enable
KVM: ARM: introduce vgic_params structure
KVM: ARM: vgic: split GICv2 backend from the main vgic code
arm64: KVM: remove __kvm_hyp_code_{start,end} from hyp.S
arm64: KVM: split GICv2 world switch from hyp code
arm64: KVM: move hcr_el2 setting into vgic-v2-switch.S
KVM: ARM: vgic: add the GICv3 backend
arm64: KVM: vgic: add GICv3 world switch
Documentation/arm64/booting.txt | 7 +
Documentation/devicetree/bindings/arm/gic-v3.txt | 81 +++
arch/arm/include/asm/kvm_host.h | 5 +
arch/arm/kernel/asm-offsets.c | 14 +-
arch/arm/kvm/Makefile | 1 +
arch/arm/kvm/interrupts_head.S | 26 +-
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/kvm_asm.h | 18 +-
arch/arm64/include/asm/kvm_host.h | 21 +
arch/arm64/include/asm/virt.h | 4 +
arch/arm64/kernel/asm-offsets.c | 22 +-
arch/arm64/kernel/head.S | 14 +
arch/arm64/kernel/hyp-stub.S | 41 +-
arch/arm64/kvm/Makefile | 4 +
arch/arm64/kvm/hyp.S | 132 +----
arch/arm64/kvm/vgic-v2-switch.S | 149 +++++
arch/arm64/kvm/vgic-v3-switch.S | 275 ++++++++++
drivers/irqchip/Kconfig | 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-gic-v3.c | 665 +++++++++++++++++++++++
include/kvm/arm_vgic.h | 103 +++-
include/linux/irqchip/arm-gic-v3.h | 190 +++++++
virt/kvm/arm/vgic-v2.c | 228 ++++++++
virt/kvm/arm/vgic-v3.c | 220 ++++++++
virt/kvm/arm/vgic.c | 330 ++++++-----
25 files changed, 2238 insertions(+), 319 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/gic-v3.txt
create mode 100644 arch/arm64/kvm/vgic-v2-switch.S
create mode 100644 arch/arm64/kvm/vgic-v3-switch.S
create mode 100644 drivers/irqchip/irq-gic-v3.c
create mode 100644 include/linux/irqchip/arm-gic-v3.h
create mode 100644 virt/kvm/arm/vgic-v2.c
create mode 100644 virt/kvm/arm/vgic-v3.c
--
1.8.3.4
^ permalink raw reply
* [PATCH] arm: add DSB after icache flush in __flush_icache_all()
From: Catalin Marinas @ 2014-02-05 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391592782-18576-1-git-send-email-vkale@apm.com>
On Wed, Feb 05, 2014 at 09:33:02AM +0000, Vinayak Kale wrote:
> Add DSB after icache flush to complete the cache maintenance operation.
>
> Signed-off-by: Vinayak Kale <vkale@apm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
^ permalink raw reply
* [PATCH v2 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support
From: Lukasz Majewski @ 2014-02-05 13:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJuA9aiokvq-=a-hK=nJnTkZTGF1Zc2ERXk2rpk-Xv7gUHaVpw@mail.gmail.com>
Hi Thomas,
> Hi Lukasz,
>
> On Wed, Feb 5, 2014 at 5:14 PM, Lukasz Majewski
> <l.majewski@samsung.com> wrote:
> > Hi Thomas,
> >
> > Fist of all, thanks for your patches.
> >
> >> Hi Lukasz,
> >>
> >> On Mon, Jan 20, 2014 at 1:38 PM, Lukasz Majewski
> >> <l.majewski@samsung.com> wrote:
> >> > Hi Thomas,
> >> >
> >> >> From: Thomas Abraham <thomas.ab@samsung.com>
> >> >>
> >> >> Exynos4210, Exynos4x12 and Exynos5250 based platforms have
> >> >> switched over to use cpufreq-cpu0 driver for cpufreq
> >> >> functionality. So the Exynos specific cpufreq drivers for these
> >> >> platforms can be removed.
> >> >>
> >>
> >> <snip>
> >>
> >> >> -static unsigned int exynos4x12_volt_table[] = {
> >> >> - 1350000, 1287500, 1250000, 1187500, 1137500, 1087500,
> >> >> 1037500,
> >> >> - 1000000, 987500, 975000, 950000, 925000, 900000,
> >> >> 900000 -};
> >> >> -
> >> >> -static struct cpufreq_frequency_table exynos4x12_freq_table[]
> >> >> = {
> >> >> - {CPUFREQ_BOOST_FREQ, 1500 * 1000},
> >> >
> >> > Here, you are removing BOOST support for Exynos4412, without any
> >> > code, which brings back this functionality in the new code.
> >> >
> >> > I'd propose adding new property to cpus node and during
> >> > operating-points parsing mark the entry at the
> >> > cpufreq_frequency_table accordingly.
> >>
> >> I tried doing this as you suggested with [1] but looks like that
> >> will not go through at this point.
> >
> > I've read your patches regarding OPP. In my opinion, despite the
> > problem with further OPP format discussion (which is ongoing and
> > probably will take some time), there is a palatable solution
> > (presented below).
> >
> >> The other alternative would be to use
> >> exynos specific cpufreq drivers only if multiplatform config is not
> >> selected or use cpufreq-cpu0 if multiplatform config is selected
> >> (but this is not something I would want to do). With this, there
> >> are issues like clock blocks encapsulated within the opaque clock
> >> type cannot be removed since exynos specific cpufreq drivers need
> >> it and hence it is not really a clean solution.
> >
> > It would be a maintenance nightmare. We cannot afford to do such
> > huge cleanup only partially. The rationale for the whole clean up
> > is to remove exynosXXXX-cpufreq.c files.
> >
> > I also share your doubts here. We shall NOT do it this way.
> >
> >>The other option is to drop the support
> >> for boost on exynos4x12 for now and reintroduce that when the OPP
> >> bindings have been finalized.
> >
> > So you want to drop the BOOST kernel functionality just because you
> > are doing clean up and this feature is problematic to provide at new
> > approach?
> >
> >> Would that be okay?
> >
> > It is NOT acceptable. Sorry, but NAK.
> >
> >> Any other
> >> suggestions will also be helpful.
> >
> > For me it would be perfectly fine to see at device tree CPU0 node
> > code proposed by Nishanth:
> >
> > operating-points = < Fa Va
> > Fb Vb
> > Fc Vc
> > Fd Vd
> > >;
> > boost-frequencies = <Fc Fd>;
> >
> > And then the cpufreq table could be properly modified by marking
> > relevant frequencies as CPUFREQ_BOOST_FREQ.
>
> Okay, thanks. Initially it looked like adding boost frequencies into
> operating-modes would convolute it but I guess I was wrong. So I will
> add support for looking up "boost-frequencies" property in
> dev_pm_opp_init_cpufreq_table function and mark the frequencies listed
> in this binding as CPUFREQ_BOOST_FREQ.
That would be great. I'm looking forward for patches :-).
Thanks.
>
> Thanks,
> Thomas.
>
> >
> >>
> >> Thanks,
> >> Thomas.
> >>
> >> >
> >> >> - {L1, 1400 * 1000},
> >> >> - {L2, 1300 * 1000},
> >> >> - {L3, 1200 * 1000},
> >> >> - {L4, 1100 * 1000},
> >> >> - {L5, 1000 * 1000},
> >> >> - {L6, 900 * 1000},
> >> >> - {L7, 800 * 1000},
> >> >> - {L8, 700 * 1000},
> >> >> - {L9, 600 * 1000},
> >> >> - {L10, 500 * 1000},
> >> >> - {L11, 400 * 1000},
> >> >> - {L12, 300 * 1000},
> >> >> - {L13, 200 * 1000},
> >> >> - {0, CPUFREQ_TABLE_END},
> >> >> -};
> >> >> -
> >> >> -static struct apll_freq *apll_freq_4x12;
> >> >> -
> >> >> -static struct apll_freq apll_freq_4212[] = {
> >> >> - /*
> >> >> - * values:
> >> >> - * freq
> >> >> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
> >> >> PCLK_DBG, APLL, CORE2
> >> >> - * clock divider for COPY, HPM, RESERVED
> >> >> - * PLL M, P, S
> >> >> - */
> >> >> - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4,
> >> >> 0),
> >> >> - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3,
> >> >> 0),
> >> >> - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6,
> >> >> 0),
> >> >> - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4,
> >> >> 0),
> >> >> - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6,
> >> >> 0),
> >> >> - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3,
> >> >> 0),
> >> >> - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4,
> >> >> 0),
> >> >> - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3,
> >> >> 0),
> >> >> - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3,
> >> >> 1),
> >> >> - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4,
> >> >> 1),
> >> >> - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3,
> >> >> 1),
> >> >> - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3,
> >> >> 1),
> >> >> - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4,
> >> >> 2),
> >> >> - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3,
> >> >> 2), -};
> >> >> -
> >> >> -static struct apll_freq apll_freq_4412[] = {
> >> >> - /*
> >> >> - * values:
> >> >> - * freq
> >> >> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
> >> >> PCLK_DBG, APLL, CORE2
> >> >> - * clock divider for COPY, HPM, CORES
> >> >> - * PLL M, P, S
> >> >> - */
> >> >> - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4,
> >> >> 0),
> >> >> - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3,
> >> >> 0),
> >> >> - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6,
> >> >> 0),
> >> >> - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4,
> >> >> 0),
> >> >> - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6,
> >> >> 0),
> >> >> - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3,
> >> >> 0),
> >> >> - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4,
> >> >> 0),
> >> >> - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3,
> >> >> 0),
> >> >> - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3,
> >> >> 1),
> >> >> - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4,
> >> >> 1),
> >> >> - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3,
> >> >> 1),
> >> >> - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3,
> >> >> 1),
> >> >> - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4,
> >> >> 2),
> >> >> - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3,
> >> >> 2), -};
> >> >> -
> >> >> -static void exynos4x12_set_clkdiv(unsigned int div_index)
> >> >> -{
> >> >> - unsigned int tmp;
> >> >> - unsigned int stat_cpu1;
> >> >> -
> >> >> - /* Change Divider - CPU0 */
> >> >> -
> >> >> - tmp = apll_freq_4x12[div_index].clk_div_cpu0;
> >> >> -
> >> >> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
> >> >> -
> >> >> - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
> >> >> - cpu_relax();
> >> >> -
> >> >> - /* Change Divider - CPU1 */
> >> >> - tmp = apll_freq_4x12[div_index].clk_div_cpu1;
> >> >> -
> >> >> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
> >> >> - if (soc_is_exynos4212())
> >> >> - stat_cpu1 = 0x11;
> >> >> - else
> >> >> - stat_cpu1 = 0x111;
> >> >> -
> >> >> - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
> >> >> - cpu_relax();
> >> >> -}
> >> >> -
> >> >> -static void exynos4x12_set_apll(unsigned int index)
> >> >> -{
> >> >> - unsigned int tmp, freq = apll_freq_4x12[index].freq;
> >> >> -
> >> >> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
> >> >> - clk_set_parent(moutcore, mout_mpll);
> >> >> -
> >> >> - do {
> >> >> - cpu_relax();
> >> >> - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
> >> >> - >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
> >> >> - tmp &= 0x7;
> >> >> - } while (tmp != 0x2);
> >> >> -
> >> >> - clk_set_rate(mout_apll, freq * 1000);
> >> >> -
> >> >> - /* MUX_CORE_SEL = APLL */
> >> >> - clk_set_parent(moutcore, mout_apll);
> >> >> -
> >> >> - do {
> >> >> - cpu_relax();
> >> >> - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
> >> >> - tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
> >> >> - } while (tmp != (0x1 <<
> >> >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); -}
> >> >> -
> >> >> -static void exynos4x12_set_frequency(unsigned int old_index,
> >> >> - unsigned int new_index)
> >> >> -{
> >> >> - if (old_index > new_index) {
> >> >> - exynos4x12_set_clkdiv(new_index);
> >> >> - exynos4x12_set_apll(new_index);
> >> >> - } else if (old_index < new_index) {
> >> >> - exynos4x12_set_apll(new_index);
> >> >> - exynos4x12_set_clkdiv(new_index);
> >> >> - }
> >> >> -}
> >> >> -
> >> >> -int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
> >> >> -{
> >> >> - unsigned long rate;
> >> >> -
> >> >> - cpu_clk = clk_get(NULL, "armclk");
> >> >> - if (IS_ERR(cpu_clk))
> >> >> - return PTR_ERR(cpu_clk);
> >> >> -
> >> >> - moutcore = clk_get(NULL, "moutcore");
> >> >> - if (IS_ERR(moutcore))
> >> >> - goto err_moutcore;
> >> >> -
> >> >> - mout_mpll = clk_get(NULL, "mout_mpll");
> >> >> - if (IS_ERR(mout_mpll))
> >> >> - goto err_mout_mpll;
> >> >> -
> >> >> - rate = clk_get_rate(mout_mpll) / 1000;
> >> >> -
> >> >> - mout_apll = clk_get(NULL, "mout_apll");
> >> >> - if (IS_ERR(mout_apll))
> >> >> - goto err_mout_apll;
> >> >> -
> >> >> - if (soc_is_exynos4212())
> >> >> - apll_freq_4x12 = apll_freq_4212;
> >> >> - else
> >> >> - apll_freq_4x12 = apll_freq_4412;
> >> >> -
> >> >> - info->mpll_freq_khz = rate;
> >> >> - /* 800Mhz */
> >> >> - info->pll_safe_idx = L7;
> >> >> - info->cpu_clk = cpu_clk;
> >> >> - info->volt_table = exynos4x12_volt_table;
> >> >> - info->freq_table = exynos4x12_freq_table;
> >> >> - info->set_freq = exynos4x12_set_frequency;
> >> >> -
> >> >> - return 0;
> >> >> -
> >> >> -err_mout_apll:
> >> >> - clk_put(mout_mpll);
> >> >> -err_mout_mpll:
> >> >> - clk_put(moutcore);
> >> >> -err_moutcore:
> >> >> - clk_put(cpu_clk);
> >> >> -
> >> >> - pr_debug("%s: failed initialization\n", __func__);
> >> >> - return -EINVAL;
> >> >> -}
> >> >> diff --git a/drivers/cpufreq/exynos5250-cpufreq.c
> >> >> b/drivers/cpufreq/exynos5250-cpufreq.c deleted file mode 100644
> >> >> index 5f90b82..0000000
> >> >> --- a/drivers/cpufreq/exynos5250-cpufreq.c
> >> >> +++ /dev/null
> >> >> @@ -1,183 +0,0 @@
> >> >> -/*
> >> >> - * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
> >> >> - * http://www.samsung.com
> >> >> - *
> >> >> - * EXYNOS5250 - CPU frequency scaling support
> >> >> - *
> >> >> - * This program is free software; you can redistribute it
> >> >> and/or modify
> >> >> - * it under the terms of the GNU General Public License
> >> >> version 2 as
> >> >> - * published by the Free Software Foundation.
> >> >> -*/
> >> >> -
> >> >> -#include <linux/module.h>
> >> >> -#include <linux/kernel.h>
> >> >> -#include <linux/err.h>
> >> >> -#include <linux/clk.h>
> >> >> -#include <linux/io.h>
> >> >> -#include <linux/slab.h>
> >> >> -#include <linux/cpufreq.h>
> >> >> -
> >> >> -#include <mach/map.h>
> >> >> -
> >> >> -#include "exynos-cpufreq.h"
> >> >> -
> >> >> -static struct clk *cpu_clk;
> >> >> -static struct clk *moutcore;
> >> >> -static struct clk *mout_mpll;
> >> >> -static struct clk *mout_apll;
> >> >> -
> >> >> -static unsigned int exynos5250_volt_table[] = {
> >> >> - 1300000, 1250000, 1225000, 1200000, 1150000,
> >> >> - 1125000, 1100000, 1075000, 1050000, 1025000,
> >> >> - 1012500, 1000000, 975000, 950000, 937500,
> >> >> - 925000
> >> >> -};
> >> >> -
> >> >> -static struct cpufreq_frequency_table exynos5250_freq_table[]
> >> >> = {
> >> >> - {L0, 1700 * 1000},
> >> >> - {L1, 1600 * 1000},
> >> >> - {L2, 1500 * 1000},
> >> >> - {L3, 1400 * 1000},
> >> >> - {L4, 1300 * 1000},
> >> >> - {L5, 1200 * 1000},
> >> >> - {L6, 1100 * 1000},
> >> >> - {L7, 1000 * 1000},
> >> >> - {L8, 900 * 1000},
> >> >> - {L9, 800 * 1000},
> >> >> - {L10, 700 * 1000},
> >> >> - {L11, 600 * 1000},
> >> >> - {L12, 500 * 1000},
> >> >> - {L13, 400 * 1000},
> >> >> - {L14, 300 * 1000},
> >> >> - {L15, 200 * 1000},
> >> >> - {0, CPUFREQ_TABLE_END},
> >> >> -};
> >> >> -
> >> >> -static struct apll_freq apll_freq_5250[] = {
> >> >> - /*
> >> >> - * values:
> >> >> - * freq
> >> >> - * clock divider for ARM, CPUD, ACP, PERIPH, ATB,
> >> >> PCLK_DBG, APLL, ARM2
> >> >> - * clock divider for COPY, HPM, RESERVED
> >> >> - * PLL M, P, S
> >> >> - */
> >> >> - APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6,
> >> >> 0),
> >> >> - APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3,
> >> >> 0),
> >> >> - APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4,
> >> >> 0),
> >> >> - APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3,
> >> >> 0),
> >> >> - APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6,
> >> >> 0),
> >> >> - APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4,
> >> >> 0),
> >> >> - APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6,
> >> >> 0),
> >> >> - APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3,
> >> >> 0),
> >> >> - APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4,
> >> >> 0),
> >> >> - APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3,
> >> >> 0),
> >> >> - APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3,
> >> >> 1),
> >> >> - APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4,
> >> >> 1),
> >> >> - APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3,
> >> >> 1),
> >> >> - APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3,
> >> >> 1),
> >> >> - APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4,
> >> >> 2),
> >> >> - APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3,
> >> >> 2), -};
> >> >> -
> >> >> -static void set_clkdiv(unsigned int div_index)
> >> >> -{
> >> >> - unsigned int tmp;
> >> >> -
> >> >> - /* Change Divider - CPU0 */
> >> >> -
> >> >> - tmp = apll_freq_5250[div_index].clk_div_cpu0;
> >> >> -
> >> >> - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
> >> >> -
> >> >> - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
> >> >> - cpu_relax();
> >> >> -
> >> >> - /* Change Divider - CPU1 */
> >> >> - tmp = apll_freq_5250[div_index].clk_div_cpu1;
> >> >> -
> >> >> - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
> >> >> -
> >> >> - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
> >> >> - cpu_relax();
> >> >> -}
> >> >> -
> >> >> -static void set_apll(unsigned int index)
> >> >> -{
> >> >> - unsigned int tmp;
> >> >> - unsigned int freq = apll_freq_5250[index].freq;
> >> >> -
> >> >> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
> >> >> - clk_set_parent(moutcore, mout_mpll);
> >> >> -
> >> >> - do {
> >> >> - cpu_relax();
> >> >> - tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
> >> >> - tmp &= 0x7;
> >> >> - } while (tmp != 0x2);
> >> >> -
> >> >> - clk_set_rate(mout_apll, freq * 1000);
> >> >> -
> >> >> - /* MUX_CORE_SEL = APLL */
> >> >> - clk_set_parent(moutcore, mout_apll);
> >> >> -
> >> >> - do {
> >> >> - cpu_relax();
> >> >> - tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
> >> >> - tmp &= (0x7 << 16);
> >> >> - } while (tmp != (0x1 << 16));
> >> >> -}
> >> >> -
> >> >> -static void exynos5250_set_frequency(unsigned int old_index,
> >> >> - unsigned int new_index)
> >> >> -{
> >> >> - if (old_index > new_index) {
> >> >> - set_clkdiv(new_index);
> >> >> - set_apll(new_index);
> >> >> - } else if (old_index < new_index) {
> >> >> - set_apll(new_index);
> >> >> - set_clkdiv(new_index);
> >> >> - }
> >> >> -}
> >> >> -
> >> >> -int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
> >> >> -{
> >> >> - unsigned long rate;
> >> >> -
> >> >> - cpu_clk = clk_get(NULL, "armclk");
> >> >> - if (IS_ERR(cpu_clk))
> >> >> - return PTR_ERR(cpu_clk);
> >> >> -
> >> >> - moutcore = clk_get(NULL, "mout_cpu");
> >> >> - if (IS_ERR(moutcore))
> >> >> - goto err_moutcore;
> >> >> -
> >> >> - mout_mpll = clk_get(NULL, "mout_mpll");
> >> >> - if (IS_ERR(mout_mpll))
> >> >> - goto err_mout_mpll;
> >> >> -
> >> >> - rate = clk_get_rate(mout_mpll) / 1000;
> >> >> -
> >> >> - mout_apll = clk_get(NULL, "mout_apll");
> >> >> - if (IS_ERR(mout_apll))
> >> >> - goto err_mout_apll;
> >> >> -
> >> >> - info->mpll_freq_khz = rate;
> >> >> - /* 800Mhz */
> >> >> - info->pll_safe_idx = L9;
> >> >> - info->cpu_clk = cpu_clk;
> >> >> - info->volt_table = exynos5250_volt_table;
> >> >> - info->freq_table = exynos5250_freq_table;
> >> >> - info->set_freq = exynos5250_set_frequency;
> >> >> -
> >> >> - return 0;
> >> >> -
> >> >> -err_mout_apll:
> >> >> - clk_put(mout_mpll);
> >> >> -err_mout_mpll:
> >> >> - clk_put(moutcore);
> >> >> -err_moutcore:
> >> >> - clk_put(cpu_clk);
> >> >> -
> >> >> - pr_err("%s: failed initialization\n", __func__);
> >> >> - return -EINVAL;
> >> >> -}
> >> >
> >> >
> >> >
> >> > --
> >> > Best regards,
> >> >
> >> > Lukasz Majewski
> >> >
> >> > Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe cpufreq"
> >> in the body of a message to majordomo at vger.kernel.org
> >> More majordomo info at http://vger.kernel.org/majordomo-info.html
> >>
> >
> >
> >
> > --
> > Best regards,
> >
> > Lukasz Majewski
> >
> > Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply
* [PATCH 1/3] Phytec phyFLEX-i.MX6 : Added USB_HOST Support
From: Fabio Estevam @ 2014-02-05 13:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391488493-30662-1-git-send-email-ashutosh.s@phytec.in>
On Tue, Feb 4, 2014 at 2:34 AM, Ashutosh singh <ashutosh.s@phytec.in> wrote:
> +
> + reg_usb_h1_vbus: regulator at 1 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio1 0 0>;
> + enable-active-low;
You should remove this 'enable-active-low' as this is not a valid property.
By default the gpio is active low according to
Documentation/devicetree/bindings/regulator/gpio-regulator.txt
Regards,
Fabio Estevam
^ permalink raw reply
* [PATCH V5 2/4] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
From: Sricharan R @ 2014-02-05 13:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.02.1402041713470.24986@ionos.tec.linutronix.de>
On Tuesday 04 February 2014 09:44 PM, Thomas Gleixner wrote:
> On Mon, 3 Feb 2014, Sricharan R wrote:
>>> I already have your reviewed-by tag for the first patch in this series.
>>>
>>> Kevin was pointing out that irqchip maintainer tag is needed for this patch as well
>>> to be merged. We are planning to take this series through arm-soc tree.
>>>
>>> Can i please have your tag for this patch as well ?
>
> Acked-by-me
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Thanks Thomas.
Kevin,
I will re-send a branch based on rc1 for this.
Regards,
Sricharan
^ permalink raw reply
* [PATCH 2/2] ARM: dts: imx28-tx28: Remove 'enable-active-low' property
From: Fabio Estevam @ 2014-02-05 13:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391605810-3285-1-git-send-email-fabio.estevam@freescale.com>
'enable-active-low' is not a valid property for a GPIO controlled regulator.
According to Documentation/devicetree/bindings/regulator/gpio-regulator.txt:
"Optional properties:
...
- enable-active-high : Polarity of GPIO is active high (default is low)."
,so the correct way to define an active-low GPIO controlled regulator is to
simply not pass 'enable-active-high'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/boot/dts/imx28-tx28.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 3c54e8d..e14bd86 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -91,7 +91,6 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 0 0>;
- enable-active-low;
pinctrl-names = "default";
pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
};
--
1.8.1.2
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: mx53: Remove 'enable-active-low' property
From: Fabio Estevam @ 2014-02-05 13:10 UTC (permalink / raw)
To: linux-arm-kernel
'enable-active-low' is not a valid property for a GPIO controlled regulator.
According to Documentation/devicetree/bindings/regulator/gpio-regulator.txt:
"Optional properties:
...
- enable-active-high : Polarity of GPIO is active high (default is low)."
,so the correct way to define an active-low GPIO controlled regulator is to
simply not pass 'enable-active-high'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/boot/dts/imx53-m53evk.dts | 1 -
arch/arm/boot/dts/imx53-mba53.dts | 1 -
arch/arm/boot/dts/imx53-tx53.dtsi | 1 -
3 files changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index 7100d08..e8d11e2 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -103,7 +103,6 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 2 0>;
- enable-active-low;
};
};
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 0358366..55af110 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -46,7 +46,6 @@
regulator-name = "lcd-supply";
gpio = <&gpio2 5 0>;
startup-delay-us = <5000>;
- enable-active-low;
};
reg_3p2v: regulator at 1 {
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index a44403a..e348796 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -96,7 +96,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_xcvr>;
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
- enable-active-low;
};
reg_usbh1_vbus: regulator at 3 {
--
1.8.1.2
^ permalink raw reply related
* [PATCH 1/3] clk: rcar-h2: fix sd0/sd1 divisor table
From: Laurent Pinchart @ 2014-02-05 13:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F23166.1030609@codethink.co.uk>
Hi Ben,
On Wednesday 05 February 2014 12:41:10 Ben Dooks wrote:
> On 05/02/14 11:55, Ben Dooks wrote:
> > On 05/02/14 10:56, Laurent Pinchart wrote:
> >> On Tuesday 04 February 2014 18:17:36 William Towle wrote:
> >>> The clk_div_table for cpg_sd01_div_table[] concurs with the manual
> >>> but not with values found in the device itself (which are also the
> >>> same as the ones in arch/arm/mach-shmobile/clock-r8a7790.c).
> >>>
> >>> Update the clk-rcar-gen2.c driver to have the same table as the one
> >>> used by the mach-shmobile driver which work once further issues are
> >>> fixed in the clk-rcar-gen2.c driver.
> >>>
> >>> Part of the fix for the following error where the driver reports the
> >>>
> >>> output as 1MHz but is really 97.5MHz:
> >>> sh_mobile_sdhi ee100000.sd: mmc0 base at 0xee100000 clock rate 1
> >>> MHz
> >>>
> >>> [ben.dooks at codethink.co.uk: updated patch description]
> >>> Signed-off-by: William Towle <william.towle@codethink.co.uk>
> >>> Reviewed-by: Ben Dooks <ben.dooks@codethink.co.uk>
> >>> ---
> >>>
> >>> drivers/clk/shmobile/clk-rcar-gen2.c | 2 ++
> >>> 1 file changed, 2 insertions(+)
> >>>
> >>> diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c
> >>> b/drivers/clk/shmobile/clk-rcar-gen2.c index a59ec21..df4a1e6 100644
> >>> --- a/drivers/clk/shmobile/clk-rcar-gen2.c
> >>> +++ b/drivers/clk/shmobile/clk-rcar-gen2.c
> >>> @@ -170,6 +170,8 @@ static const struct clk_div_table
> >>> cpg_sdh_div_table[] =
> >>> { };
> >>>
> >>> static const struct clk_div_table cpg_sd01_div_table[] = {
> >>>
> >>> + { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
> >>> + { 4, 8 },
> >>>
> >>> { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
> >>> { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
> >>
> >> With this applied the only difference between the sdh and sd0/1 dividers
> >> tables would be the { 12, 10 } entry, available for sd0/1 only. Given
> >> that the hardware does not match the documentation, could you check
> >> whether that entry is supported by sdh as well ? If so we could merge the
> >> two tables. Otherwise this patch looks good, could you please just
> >> reformat the table to avoid the mostly empty line in the middle ?
> >
> > I would like feedback from Renesas on this issue if possible. I can
> > have a quick try at setting the clock value to 10 in u-boot and scope
> > it out and see what happens.
> >
> > Magnus or Morimoto-san, is there a chance this could be reviewed by
> > someone in Renesas who has knowledge of the hardware block?
> >
> > [PS, added Kuninori Morimoto to this[
>
> I got William to do a quick test with the following u-boot command
> mw.l 0xE6150074 0xCCC
>
> sdhi0 showed 156MHz output, and it seemed to work. So there is a
> distinct possibility that the sdh clock also supports setting 12
> for a /10
Thank you for trying it out. I'd like feedback from Renesas as well, assuming
we don't get a "don't do that or it will cause the universe to collapse -
woops, too late" nack, let's respin this patch and merge the two tables
instead.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH v4 5/5] ARM: sunxi: Enable A31 SPI and SID in the defconfig
From: Maxime Ripard @ 2014-02-05 13:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391605507-30981-1-git-send-email-maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/configs/sunxi_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 3e2259b..b5df4a5 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -24,6 +24,7 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_EEPROM_SUNXI_SID=y
CONFIG_NETDEVICES=y
CONFIG_SUN4I_EMAC=y
# CONFIG_NET_CADENCE is not set
@@ -48,6 +49,8 @@ CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MV64XXX=y
+CONFIG_SPI=y
+CONFIG_SPI_SUN6I=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
--
1.8.4.2
^ permalink raw reply related
* [PATCH v4 4/5] ARM: sun6i: dt: Add SPI controllers to the A31 DTSI
From: Maxime Ripard @ 2014-02-05 13:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391605507-30981-1-git-send-email-maxime.ripard@free-electrons.com>
The A31 has 4 SPI controllers. Add them in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 93d7bb6..fc07f70 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -350,6 +350,46 @@
status = "disabled";
};
+ spi0: spi at 01c68000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <0 65 4>;
+ clocks = <&ahb1_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 20>;
+ status = "disabled";
+ };
+
+ spi1: spi at 01c69000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <0 66 4>;
+ clocks = <&ahb1_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 21>;
+ status = "disabled";
+ };
+
+ spi2: spi at 01c6a000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c6a000 0x1000>;
+ interrupts = <0 67 4>;
+ clocks = <&ahb1_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 22>;
+ status = "disabled";
+ };
+
+ spi3: spi at 01c6b000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c6b000 0x1000>;
+ interrupts = <0 68 4>;
+ clocks = <&ahb1_gates 23>, <&spi3_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 23>;
+ status = "disabled";
+ };
+
gic: interrupt-controller at 01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
1.8.4.2
^ permalink raw reply related
* [PATCH v4 3/5] spi: sunxi: Add Allwinner A31 SPI controller driver
From: Maxime Ripard @ 2014-02-05 13:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391605507-30981-1-git-send-email-maxime.ripard@free-electrons.com>
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
.../devicetree/bindings/spi/spi-sun6i.txt | 24 +
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-sun6i.c | 483 +++++++++++++++++++++
4 files changed, 514 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-sun6i.txt
create mode 100644 drivers/spi/spi-sun6i.c
diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
new file mode 100644
index 0000000..21de73d
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
@@ -0,0 +1,24 @@
+Allwinner A31 SPI controller
+
+Required properties:
+- compatible: Should be "allwinner,sun6i-a31-spi".
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks: phandle to the clocks feeding the SPI controller. Two are
+ needed:
+ - "ahb": the gated AHB parent clock
+ - "mod": the parent module clock
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset controller asserting this device in
+ reset
+
+Example:
+
+spi1: spi at 01c69000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <0 66 4>;
+ clocks = <&ahb1_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 21>;
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ba9310b..7cfe0ee 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -446,6 +446,12 @@ config SPI_SIRF
help
SPI driver for CSR SiRFprimaII SoCs
+config SPI_SUN6I
+ tristate "Allwinner A31 SPI controller"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ help
+ This enables using the SPI controller on the Allwinner A31 SoCs.
+
config SPI_MXS
tristate "Freescale MXS SPI controller"
depends on ARCH_MXS
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 95af48d..13b6ccf 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
+obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
new file mode 100644
index 0000000..94d38d0
--- /dev/null
+++ b/drivers/spi/spi-sun6i.c
@@ -0,0 +1,483 @@
+/*
+ * Copyright (C) 2012 - 2014 Allwinner Tech
+ * Pan Nan <pannan@allwinnertech.com>
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/workqueue.h>
+
+#include <linux/spi/spi.h>
+
+#define SUN6I_FIFO_DEPTH 128
+
+#define SUN6I_GBL_CTL_REG 0x04
+#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
+#define SUN6I_GBL_CTL_MASTER BIT(1)
+#define SUN6I_GBL_CTL_TP BIT(7)
+#define SUN6I_GBL_CTL_RST BIT(31)
+
+#define SUN6I_TFR_CTL_REG 0x08
+#define SUN6I_TFR_CTL_CPHA BIT(0)
+#define SUN6I_TFR_CTL_CPOL BIT(1)
+#define SUN6I_TFR_CTL_SPOL BIT(2)
+#define SUN6I_TFR_CTL_CS_MASK 0x3
+#define SUN6I_TFR_CTL_CS(cs) (((cs) & SUN6I_TFR_CTL_CS_MASK) << 4)
+#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
+#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
+#define SUN6I_TFR_CTL_DHB BIT(8)
+#define SUN6I_TFR_CTL_FBS BIT(12)
+#define SUN6I_TFR_CTL_XCH BIT(31)
+
+#define SUN6I_INT_CTL_REG 0x10
+#define SUN6I_INT_CTL_RF_OVF BIT(8)
+#define SUN6I_INT_CTL_TC BIT(12)
+
+#define SUN6I_INT_STA_REG 0x14
+
+#define SUN6I_FIFO_CTL_REG 0x18
+#define SUN6I_FIFO_CTL_RF_RST BIT(15)
+#define SUN6I_FIFO_CTL_TF_RST BIT(31)
+
+#define SUN6I_FIFO_STA_REG 0x1c
+#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
+#define SUN6I_FIFO_STA_RF_CNT_BITS 0
+#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
+#define SUN6I_FIFO_STA_TF_CNT_BITS 16
+
+#define SUN6I_CLK_CTL_REG 0x24
+#define SUN6I_CLK_CTL_CDR2_MASK 0xff
+#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
+#define SUN6I_CLK_CTL_CDR1_MASK 0xf
+#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
+#define SUN6I_CLK_CTL_DRS BIT(12)
+
+#define SUN6I_BURST_CNT_REG 0x30
+#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff)
+
+#define SUN6I_XMIT_CNT_REG 0x34
+#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
+
+#define SUN6I_BURST_CTL_CNT_REG 0x38
+#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff)
+
+#define SUN6I_TXDATA_REG 0x200
+#define SUN6I_RXDATA_REG 0x300
+
+struct sun6i_spi {
+ struct spi_master *master;
+ void __iomem *base_addr;
+ struct clk *hclk;
+ struct clk *mclk;
+ struct reset_control *rstc;
+
+ struct completion done;
+
+ const u8 *tx_buf;
+ u8 *rx_buf;
+ int len;
+};
+
+static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
+{
+ return readl(sspi->base_addr + reg);
+}
+
+static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
+{
+ writel(value, sspi->base_addr + reg);
+}
+
+static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
+{
+ u32 reg, cnt;
+ u8 byte;
+
+ /* See how much data is available */
+ reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
+ reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
+ cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
+
+ if (len > cnt)
+ len = cnt;
+
+ while (len--) {
+ byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
+ if (sspi->rx_buf)
+ *sspi->rx_buf++ = byte;
+ }
+}
+
+static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
+{
+ u8 byte;
+
+ if (len > sspi->len)
+ len = sspi->len;
+
+ while (len--) {
+ byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
+ writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
+ sspi->len--;
+ }
+}
+
+static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
+{
+ struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
+ u32 reg;
+
+ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
+ reg &= ~SUN6I_TFR_CTL_CS_MASK;
+ reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
+
+ if (enable)
+ reg |= SUN6I_TFR_CTL_CS_LEVEL;
+ else
+ reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
+
+ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
+}
+
+
+static int sun6i_spi_transfer_one(struct spi_master *master,
+ struct spi_device *spi,
+ struct spi_transfer *tfr)
+{
+ struct sun6i_spi *sspi = spi_master_get_devdata(master);
+ unsigned int mclk_rate, div, timeout;
+ unsigned int tx_len = 0;
+ int ret = 0;
+ u32 reg;
+
+ /* We don't support transfer larger than the FIFO */
+ if (tfr->len > SUN6I_FIFO_DEPTH)
+ return -EINVAL;
+
+ reinit_completion(&sspi->done);
+ sspi->tx_buf = tfr->tx_buf;
+ sspi->rx_buf = tfr->rx_buf;
+ sspi->len = tfr->len;
+
+ /* Clear pending interrupts */
+ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
+
+ /* Reset FIFO */
+ sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
+ SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
+
+ /*
+ * Setup the transfer control register: Chip Select,
+ * polarities, etc.
+ */
+ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
+
+ if (spi->mode & SPI_CPOL)
+ reg |= SUN6I_TFR_CTL_CPOL;
+ else
+ reg &= ~SUN6I_TFR_CTL_CPOL;
+
+ if (spi->mode & SPI_CPHA)
+ reg |= SUN6I_TFR_CTL_CPHA;
+ else
+ reg &= ~SUN6I_TFR_CTL_CPHA;
+
+ if (spi->mode & SPI_LSB_FIRST)
+ reg |= SUN6I_TFR_CTL_FBS;
+ else
+ reg &= ~SUN6I_TFR_CTL_FBS;
+
+ /*
+ * If it's a TX only transfer, we don't want to fill the RX
+ * FIFO with bogus data
+ */
+ if (sspi->rx_buf)
+ reg &= ~SUN6I_TFR_CTL_DHB;
+ else
+ reg |= SUN6I_TFR_CTL_DHB;
+
+ /* We want to control the chip select manually */
+ reg |= SUN6I_TFR_CTL_CS_MANUAL;
+
+ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
+
+ /* Ensure that we have a parent clock fast enough */
+ mclk_rate = clk_get_rate(sspi->mclk);
+ if (mclk_rate < (2 * spi->max_speed_hz)) {
+ clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
+ mclk_rate = clk_get_rate(sspi->mclk);
+ }
+
+ /*
+ * Setup clock divider.
+ *
+ * We have two choices there. Either we can use the clock
+ * divide rate 1, which is calculated thanks to this formula:
+ * SPI_CLK = MOD_CLK / (2 ^ cdr)
+ * Or we can use CDR2, which is calculated with the formula:
+ * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
+ * Wether we use the former or the latter is set through the
+ * DRS bit.
+ *
+ * First try CDR2, and if we can't reach the expected
+ * frequency, fall back to CDR1.
+ */
+ div = mclk_rate / (2 * spi->max_speed_hz);
+ if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
+ if (div > 0)
+ div--;
+
+ reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
+ } else {
+ div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
+ reg = SUN6I_CLK_CTL_CDR1(div);
+ }
+
+ sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
+
+ /* Setup the transfer now... */
+ if (sspi->tx_buf)
+ tx_len = tfr->len;
+
+ /* Setup the counters */
+ sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
+ sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
+ sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
+ SUN6I_BURST_CTL_CNT_STC(tx_len));
+
+ /* Fill the TX FIFO */
+ sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
+
+ /* Enable the interrupts */
+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
+
+ /* Start the transfer */
+ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
+ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
+
+ timeout = wait_for_completion_timeout(&sspi->done,
+ msecs_to_jiffies(1000));
+ if (!timeout) {
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
+
+out:
+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
+
+ return ret;
+}
+
+static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
+{
+ struct sun6i_spi *sspi = dev_id;
+ u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
+
+ /* Transfer complete */
+ if (status & SUN6I_INT_CTL_TC) {
+ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
+ complete(&sspi->done);
+ return IRQ_HANDLED;
+ }
+
+ return IRQ_NONE;
+}
+
+static int sun6i_spi_runtime_resume(struct device *dev)
+{
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct sun6i_spi *sspi = spi_master_get_devdata(master);
+ int ret;
+
+ ret = clk_prepare_enable(sspi->hclk);
+ if (ret) {
+ dev_err(dev, "Couldn't enable AHB clock\n");
+ goto out;
+ }
+
+ ret = clk_prepare_enable(sspi->mclk);
+ if (ret) {
+ dev_err(dev, "Couldn't enable module clock\n");
+ goto err;
+ }
+
+ ret = reset_control_deassert(sspi->rstc);
+ if (ret) {
+ dev_err(dev, "Couldn't deassert the device from reset\n");
+ goto err2;
+ }
+
+ sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
+ SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
+
+ return 0;
+
+err2:
+ clk_disable_unprepare(sspi->mclk);
+err:
+ clk_disable_unprepare(sspi->hclk);
+out:
+ return ret;
+}
+
+static int sun6i_spi_runtime_suspend(struct device *dev)
+{
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct sun6i_spi *sspi = spi_master_get_devdata(master);
+
+ reset_control_assert(sspi->rstc);
+ clk_disable_unprepare(sspi->mclk);
+ clk_disable_unprepare(sspi->hclk);
+
+ return 0;
+}
+
+static int sun6i_spi_probe(struct platform_device *pdev)
+{
+ struct spi_master *master;
+ struct sun6i_spi *sspi;
+ struct resource *res;
+ int ret = 0, irq;
+
+ master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
+ if (!master) {
+ dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(pdev, master);
+ sspi = spi_master_get_devdata(master);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(sspi->base_addr)) {
+ ret = PTR_ERR(sspi->base_addr);
+ goto err_free_master;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "No spi IRQ specified\n");
+ ret = -ENXIO;
+ goto err_free_master;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
+ 0, "sun6i-spi", sspi);
+ if (ret) {
+ dev_err(&pdev->dev, "Cannot request IRQ\n");
+ goto err_free_master;
+ }
+
+ sspi->master = master;
+ master->set_cs = sun6i_spi_set_cs;
+ master->transfer_one = sun6i_spi_transfer_one;
+ master->num_chipselect = 4;
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
+ master->dev.of_node = pdev->dev.of_node;
+ master->auto_runtime_pm = true;
+
+ sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
+ if (IS_ERR(sspi->hclk)) {
+ dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
+ ret = PTR_ERR(sspi->hclk);
+ goto err_free_master;
+ }
+
+ sspi->mclk = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(sspi->mclk)) {
+ dev_err(&pdev->dev, "Unable to acquire module clock\n");
+ ret = PTR_ERR(sspi->mclk);
+ goto err_free_master;
+ }
+
+ init_completion(&sspi->done);
+
+ sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(sspi->rstc)) {
+ dev_err(&pdev->dev, "Couldn't get reset controller\n");
+ ret = PTR_ERR(sspi->rstc);
+ goto err_free_master;
+ }
+
+ /*
+ * This wake-up/shutdown pattern is to be able to have the
+ * device woken up, even if runtime_pm is disabled
+ */
+ ret = sun6i_spi_runtime_resume(&pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't resume the device\n");
+ goto err_free_master;
+ }
+
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_idle(&pdev->dev);
+
+ ret = devm_spi_register_master(&pdev->dev, master);
+ if (ret) {
+ dev_err(&pdev->dev, "cannot register SPI master\n");
+ goto err_pm_disable;
+ }
+
+ return 0;
+
+err_pm_disable:
+ pm_runtime_disable(&pdev->dev);
+ sun6i_spi_runtime_suspend(&pdev->dev);
+err_free_master:
+ spi_master_put(master);
+ return ret;
+}
+
+static int sun6i_spi_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id sun6i_spi_match[] = {
+ { .compatible = "allwinner,sun6i-a31-spi", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun6i_spi_match);
+
+static const struct dev_pm_ops sun6i_spi_pm_ops = {
+ .runtime_resume = sun6i_spi_runtime_resume,
+ .runtime_suspend = sun6i_spi_runtime_suspend,
+};
+
+static struct platform_driver sun6i_spi_driver = {
+ .probe = sun6i_spi_probe,
+ .remove = sun6i_spi_remove,
+ .driver = {
+ .name = "sun6i-spi",
+ .owner = THIS_MODULE,
+ .of_match_table = sun6i_spi_match,
+ .pm = &sun6i_spi_pm_ops,
+ },
+};
+module_platform_driver(sun6i_spi_driver);
+
+MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
+MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
+MODULE_LICENSE("GPL");
--
1.8.4.2
^ permalink raw reply related
* [PATCH v4 2/5] ARM: sun6i: dt: Add PLL6 and SPI module clocks
From: Maxime Ripard @ 2014-02-05 13:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391605507-30981-1-git-send-email-maxime.ripard@free-electrons.com>
The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 46 ++++++++++++++++++++++++++++++++--------
1 file changed, 37 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 092bf97..93d7bb6 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -83,16 +83,12 @@
clocks = <&osc24M>;
};
- /*
- * This is a dummy clock, to be used as placeholder on
- * other mux clocks when a specific parent clock is not
- * yet implemented. It should be dropped when the driver
- * is complete.
- */
- pll6: pll6 {
+ pll6: clk at 01c20028 {
#clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6";
};
cpu: cpu at 01c20050 {
@@ -192,6 +188,38 @@
"apb2_uart1", "apb2_uart2", "apb2_uart3",
"apb2_uart4", "apb2_uart5";
};
+
+ spi0_clk: clk at 01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk at 01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk at 01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi2";
+ };
+
+ spi3_clk: clk at 01c200ac {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-mod0-clk";
+ reg = <0x01c200ac 0x4>;
+ clocks = <&osc24M>, <&pll6>;
+ clock-output-names = "spi3";
+ };
};
soc at 01c00000 {
--
1.8.4.2
^ permalink raw reply related
* [PATCH v4 1/5] clk: sunxi: Add support for PLL6 on the A31
From: Maxime Ripard @ 2014-02-05 13:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391605507-30981-1-git-send-email-maxime.ripard@free-electrons.com>
The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sunxi.c | 45 +++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index c2cb762..954845c 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -11,6 +11,7 @@ Required properties:
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
"allwinner,sun4i-pll5-clk" - for the PLL5 clock
"allwinner,sun4i-pll6-clk" - for the PLL6 clock
+ "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
"allwinner,sun4i-axi-clk" - for the AXI clock
"allwinner,sun4i-axi-gates-clk" - for the AXI gates
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abb6c5a..0c05c2d 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -249,7 +249,38 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
*n = DIV_ROUND_UP(div, (*k+1));
}
+/**
+ * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
+ * PLL6 rate is calculated as follows
+ * rate = parent_rate * n * (k + 1) / 2
+ * parent_rate is always 24Mhz
+ */
+
+static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
+ u8 *n, u8 *k, u8 *m, u8 *p)
+{
+ u8 div;
+
+ /*
+ * We always have 24MHz / 2, so we can just say that our
+ * parent clock is 12MHz.
+ */
+ parent_rate = parent_rate / 2;
+
+ /* Normalize value to a parent_rate multiple (24M / 2) */
+ div = *freq / parent_rate;
+ *freq = parent_rate * div;
+
+ /* we were called to round the frequency, we can now return */
+ if (n == NULL)
+ return;
+
+ *k = div / 32;
+ if (*k > 3)
+ *k = 3;
+ *n = DIV_ROUND_UP(div, (*k+1));
+}
/**
* sun4i_get_apb1_factors() - calculates m, p factors for APB1
@@ -416,6 +447,13 @@ static struct clk_factors_config sun4i_pll5_config = {
.kwidth = 2,
};
+static struct clk_factors_config sun6i_a31_pll6_config = {
+ .nshift = 8,
+ .nwidth = 5,
+ .kshift = 4,
+ .kwidth = 2,
+};
+
static struct clk_factors_config sun4i_apb1_config = {
.mshift = 0,
.mwidth = 5,
@@ -457,6 +495,12 @@ static const struct factors_data sun4i_pll5_data __initconst = {
.getter = sun4i_get_pll5_factors,
};
+static const struct factors_data sun6i_a31_pll6_data __initconst = {
+ .enable = 31,
+ .table = &sun6i_a31_pll6_config,
+ .getter = sun6i_a31_get_pll6_factors,
+};
+
static const struct factors_data sun4i_apb1_data __initconst = {
.table = &sun4i_apb1_config,
.getter = sun4i_get_apb1_factors,
@@ -972,6 +1016,7 @@ free_clkdata:
static const struct of_device_id clk_factors_match[] __initconst = {
{.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
+ {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
{.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
--
1.8.4.2
^ permalink raw reply related
* [PATCH v4 0/5] Add Allwinner A31 SPI controller support
From: Maxime Ripard @ 2014-02-05 13:05 UTC (permalink / raw)
To: linux-arm-kernel
Hi everyone,
This patchset brings support for the SPI controller found in the
Allwinner A31 SoC.
Even though the controller supports DMA, the driver only supports PIO
mode for now. This driver will be used to bring up and test DMA on the
SoC, so support for the DMA will come eventually.
It doesn't support transfer larger than the FIFO size (128 bytes) for
now, I expect it to be fixed in the future.
Thanks!
Maxime
Changes from v3:
- Rebased on top of 3.14-rc1
- Removed the dependency on devm_spi_alloc_master
- Modified the pm_runtime code according to reviews
Changes from v2:
- Removed the select on runtime_pm
- Fixed the clock error messages
- Trigger the CS manually, and honour the enable bit in set_cs
- Convert to devm_* functions
- Remove useless clk_disable_unprepare in probe
Changes from v1:
- Switched to using the transfer_one and set_cs callbacks
- Switched to using runtime_pm
- Report an error when we try to do a transfer larger than the FIFO
size, instead of silently timeouting.
- Added a Kconfig symbol
- Move the clock ratio change at transfer time
- Fixed the PLL6 cell size in the DTSI
- A few fixes here and there: typos, etc.
Maxime Ripard (5):
clk: sunxi: Add support for PLL6 on the A31
ARM: sun6i: dt: Add PLL6 and SPI module clocks
spi: sunxi: Add Allwinner A31 SPI controller driver
ARM: sun6i: dt: Add SPI controllers to the A31 DTSI
ARM: sunxi: Enable A31 SPI and SID in the defconfig
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
.../devicetree/bindings/spi/spi-sun6i.txt | 24 +
arch/arm/boot/dts/sun6i-a31.dtsi | 86 +++-
arch/arm/configs/sunxi_defconfig | 3 +
drivers/clk/sunxi/clk-sunxi.c | 45 ++
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-sun6i.c | 483 +++++++++++++++++++++
8 files changed, 640 insertions(+), 9 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi-sun6i.txt
create mode 100644 drivers/spi/spi-sun6i.c
--
1.8.4.2
^ permalink raw reply
* [ath9k-devel] [PATCH 1/3] ath9k: Fix build error on ARM
From: Joe Perches @ 2014-02-05 13:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205124127.GP26684@n2100.arm.linux.org.uk>
On Wed, 2014-02-05 at 12:41 +0000, Russell King - ARM Linux wrote:
> On Wed, Feb 05, 2014 at 04:32:46AM -0800, Joe Perches wrote:
> > Apparently, people just convert stupidly large udelay()s
> > to mdelay and not be bothered.
>
> And that's the correct answer. Having udelay(10000) rather than mdelay(10)
> is a sign that they weren't paying that much attention when writing the
> code.
Not really.
Look at the code that brought this up in the first place.
On Tue, 2014-02-04 at 08:37 +0530, Sujith Manoharan wrote:
> From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
>
> Use mdelay instead of udelay to fix this error:
>
> ERROR: "__bad_udelay" [drivers/net/wireless/ath/ath9k/ath9k_hw.ko] undefined!
[]
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
[]
> @@ -1316,7 +1316,7 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
> if (AR_SREV_9300_20_OR_LATER(ah))
> udelay(50);
> else if (AR_SREV_9100(ah))
> - udelay(10000);
> + mdelay(10);
> else
> udelay(100);
>
>
> > if (AR_SREV_9300_20_OR_LATER(ah))
> > udelay(50);
> > else if (AR_SREV_9100(ah))
> > - udelay(10000);
> > + mdelay(10);
> > else
> > udelay(100);
One chip needs a larger delay than the others.
It's not so much not paying attention as not
knowing ARM is broken for large udelay().
^ permalink raw reply
* [PATCH v2 0/6] ARM: sunxi: Add driver for SD/MMC hosts found on allwinner sunxi SOCs
From: David Lanzendörfer @ 2014-02-05 13:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205103949.GC3192@lukather>
Hi Maxime
> I have four comments here:
> - Read Documentation/SubmittingPatches, especially Section 5 and 12
> (hints, you forgot the clock maintainers for your clock patches
> and you didn't put any signed-off-by tags)
Oops. I added signed-offs now
> - You ignored pretty much all the comments that were made during the
> review of the first version. Go through
Uh? I just fixed the commits and squashed them together for easier handling.
I'm even using mmc_of_parse now...
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-December/219339.
> html and address the comments that were made.
> - Each of your patches should compile. Fix the order of your
> patches.
Done.
> - Submit a v3, with the changes you made. Otherwise we have no way
> of knowing what have been fixed and what didn't
Too many patches would be bloaty.
That's why I've squashed them into small and corrected patches.
> Looking forward for the next iteration!
Good :-)
You can have a look at the recent status here:
http://git.o2s.ch/?p=linux-next.git;a=shortlog;h=refs/heads/20140205
cheers
David
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^ permalink raw reply
* [PATCH 10/17] spi: pl022: Remove redundant pinctrl to default state in probe
From: Linus Walleij @ 2014-02-05 12:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391529538-21685-11-git-send-email-ulf.hansson@linaro.org>
On Tue, Feb 4, 2014 at 4:58 PM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> The driver core is now taking care of putting our pins into default
> state at probe. Thus we can remove the redundant call for it in probe.
>
> Cc: Mark Brown <broonie@kernel.org>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 05/17] mmc: mmci: Put the device into low power state at system suspend
From: Linus Walleij @ 2014-02-05 12:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8738jyu1h9.fsf@paris.lan>
On Tue, Feb 4, 2014 at 8:22 PM, Kevin Hilman <khilman@linaro.org> wrote:
> Ulf Hansson <ulf.hansson@linaro.org> writes:
>
>> Due to the available runtime PM callbacks, we are now able to put our
>> device into low power state at system suspend.
(...)
> I'm trying to thing of a good reason to not make PM_SLEEP depend on
> PM_RUNTIME for platforms like this.
Isn't the typical Android platform using PM_SLEEP without using
PM_RUNTIME?
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 16/18] charger: max14577: Add support for MAX77836 charger
From: Krzysztof Kozlowski @ 2014-02-05 12:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140203113031.GA8848@jenny-desktop>
Hi,
On Mon, 2014-02-03 at 17:00 +0530, Jenny Tc wrote:
> On Tue, Jan 28, 2014 at 01:18:40PM +0100, Krzysztof Kozlowski wrote:
> > - /* Battery-Charger Constant Voltage (CV) Mode, from SM-V700: 4.35V */
> > + /* Battery-Charger Constant Voltage (CV) Mode, set to: 4.35V */
>
> Does this charger chip support only 4.35V batteries? If the CV is hard coded
> to 4.35V, it's not safe for 4.2V batteries.
>
> > + /* End-of-Charge Current, set to 50mA (max14577) / 7.5mA (max77836) */
> The End of charge current basically depend on battery and not on charger chip.
>
> > - /* Overvoltage-Protection Threshold, from SM-V700: 6.5V */
> > + /* Overvoltage-Protection Threshold, set to 6.5V */
> 6.5V as over voltage for battery? A 4.35V battery would have exploded by
> that time!
Currently the max14577 driver has all these values hard-coded. This
patch doesn't change this, it only adds support for max77836. I agree
with you that hard-coding these values is not a proper way of doing
this.
I'll add another patch for parsing these values from DTS.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v4] of: add functions to count number of elements in a property
From: Heiko Stübner @ 2014-02-05 12:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205120652.9B1A7C40A89@trevor.secretlab.ca>
Am Mittwoch, 5. Februar 2014, 12:06:52 schrieb Grant Likely:
> On Tue, 04 Feb 2014 19:48:17 +0100, Heiko St??bner <heiko@sntech.de> wrote:
> > Hi Grant,
> >
> > On Tuesday, 4. February 2014 17:30:34 Grant Likely wrote:
> > > On Sat, 18 Jan 2014 09:07:30 -0600, Rob Herring <robherring2@gmail.com>
> >
> > wrote:
> > > > On Sat, Jan 18, 2014 at 6:02 AM, Heiko St????bner <heiko@sntech.de>
wrote:
> > > > > The need to know the number of array elements in a property is
> > > > > a common pattern. To prevent duplication of open-coded
> > > > > implementations
> > > > > add a helper static function that also centralises strict sanity
> > > > > checking and DTB format details, as well as a set of wrapper
> > > > > functions
> > > > > for u8, u16, u32 and u64.
> > > > >
> > > > > Suggested-by: Mark Rutland <mark.rutland@arm.com>
> > > > > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > > > > ---
> > > >
> > > > Looks good. Do you plan to convert some users to use this?
> > >
> > > I'll take that as an acked-by. Merged, thanks.
> >
> > before you taking this patch, I was planning on simply sending this as
> > part of my rockchip-smp series - as I'm currently the only user of it :-)
> > .
> >
> > This going through your tree is most likely the better way, but now I need
> > it to somehow make its way into arm-soc too ... I guess some sort of
> > stable branch arm-soc could pull?
>
> Nah, I'll drop it from my tree. Add my acked-by and merge it via
> arm-soc.
As I said on IRC, now it seems like you can keep this patch in your tree :-)
If we're really going with reserved-memory like you suggested in the rockchip-
smp series it removes the need to count u32-elements in a property for me, as
the reserved blocks move into individual subnodes.
Heiko
^ permalink raw reply
* [PATCH v2 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support
From: Thomas Abraham @ 2014-02-05 12:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205124459.61c7da0e@amdc2363>
Hi Lukasz,
On Wed, Feb 5, 2014 at 5:14 PM, Lukasz Majewski <l.majewski@samsung.com> wrote:
> Hi Thomas,
>
> Fist of all, thanks for your patches.
>
>> Hi Lukasz,
>>
>> On Mon, Jan 20, 2014 at 1:38 PM, Lukasz Majewski
>> <l.majewski@samsung.com> wrote:
>> > Hi Thomas,
>> >
>> >> From: Thomas Abraham <thomas.ab@samsung.com>
>> >>
>> >> Exynos4210, Exynos4x12 and Exynos5250 based platforms have switched
>> >> over to use cpufreq-cpu0 driver for cpufreq functionality. So the
>> >> Exynos specific cpufreq drivers for these platforms can be removed.
>> >>
>>
>> <snip>
>>
>> >> -static unsigned int exynos4x12_volt_table[] = {
>> >> - 1350000, 1287500, 1250000, 1187500, 1137500, 1087500,
>> >> 1037500,
>> >> - 1000000, 987500, 975000, 950000, 925000, 900000, 900000
>> >> -};
>> >> -
>> >> -static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
>> >> - {CPUFREQ_BOOST_FREQ, 1500 * 1000},
>> >
>> > Here, you are removing BOOST support for Exynos4412, without any
>> > code, which brings back this functionality in the new code.
>> >
>> > I'd propose adding new property to cpus node and during
>> > operating-points parsing mark the entry at the
>> > cpufreq_frequency_table accordingly.
>>
>> I tried doing this as you suggested with [1] but looks like that will
>> not go through at this point.
>
> I've read your patches regarding OPP. In my opinion, despite the problem
> with further OPP format discussion (which is ongoing and probably will
> take some time), there is a palatable solution (presented below).
>
>> The other alternative would be to use
>> exynos specific cpufreq drivers only if multiplatform config is not
>> selected or use cpufreq-cpu0 if multiplatform config is selected (but
>> this is not something I would want to do). With this, there are issues
>> like clock blocks encapsulated within the opaque clock type cannot be
>> removed since exynos specific cpufreq drivers need it and hence it is
>> not really a clean solution.
>
> It would be a maintenance nightmare. We cannot afford to do such huge
> cleanup only partially. The rationale for the whole clean up is to
> remove exynosXXXX-cpufreq.c files.
>
> I also share your doubts here. We shall NOT do it this way.
>
>>The other option is to drop the support
>> for boost on exynos4x12 for now and reintroduce that when the OPP
>> bindings have been finalized.
>
> So you want to drop the BOOST kernel functionality just because you are
> doing clean up and this feature is problematic to provide at new
> approach?
>
>> Would that be okay?
>
> It is NOT acceptable. Sorry, but NAK.
>
>> Any other
>> suggestions will also be helpful.
>
> For me it would be perfectly fine to see at device tree CPU0 node code
> proposed by Nishanth:
>
> operating-points = < Fa Va
> Fb Vb
> Fc Vc
> Fd Vd
> >;
> boost-frequencies = <Fc Fd>;
>
> And then the cpufreq table could be properly modified by marking
> relevant frequencies as CPUFREQ_BOOST_FREQ.
Okay, thanks. Initially it looked like adding boost frequencies into
operating-modes would convolute it but I guess I was wrong. So I will
add support for looking up "boost-frequencies" property in
dev_pm_opp_init_cpufreq_table function and mark the frequencies listed
in this binding as CPUFREQ_BOOST_FREQ.
Thanks,
Thomas.
>
>>
>> Thanks,
>> Thomas.
>>
>> >
>> >> - {L1, 1400 * 1000},
>> >> - {L2, 1300 * 1000},
>> >> - {L3, 1200 * 1000},
>> >> - {L4, 1100 * 1000},
>> >> - {L5, 1000 * 1000},
>> >> - {L6, 900 * 1000},
>> >> - {L7, 800 * 1000},
>> >> - {L8, 700 * 1000},
>> >> - {L9, 600 * 1000},
>> >> - {L10, 500 * 1000},
>> >> - {L11, 400 * 1000},
>> >> - {L12, 300 * 1000},
>> >> - {L13, 200 * 1000},
>> >> - {0, CPUFREQ_TABLE_END},
>> >> -};
>> >> -
>> >> -static struct apll_freq *apll_freq_4x12;
>> >> -
>> >> -static struct apll_freq apll_freq_4212[] = {
>> >> - /*
>> >> - * values:
>> >> - * freq
>> >> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
>> >> PCLK_DBG, APLL, CORE2
>> >> - * clock divider for COPY, HPM, RESERVED
>> >> - * PLL M, P, S
>> >> - */
>> >> - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
>> >> - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
>> >> - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
>> >> - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
>> >> - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
>> >> - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
>> >> - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
>> >> - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
>> >> - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
>> >> - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
>> >> - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
>> >> - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
>> >> - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
>> >> - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
>> >> -};
>> >> -
>> >> -static struct apll_freq apll_freq_4412[] = {
>> >> - /*
>> >> - * values:
>> >> - * freq
>> >> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
>> >> PCLK_DBG, APLL, CORE2
>> >> - * clock divider for COPY, HPM, CORES
>> >> - * PLL M, P, S
>> >> - */
>> >> - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
>> >> - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
>> >> - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
>> >> - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
>> >> - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
>> >> - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
>> >> - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
>> >> - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
>> >> - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
>> >> - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
>> >> - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
>> >> - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
>> >> - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
>> >> - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
>> >> -};
>> >> -
>> >> -static void exynos4x12_set_clkdiv(unsigned int div_index)
>> >> -{
>> >> - unsigned int tmp;
>> >> - unsigned int stat_cpu1;
>> >> -
>> >> - /* Change Divider - CPU0 */
>> >> -
>> >> - tmp = apll_freq_4x12[div_index].clk_div_cpu0;
>> >> -
>> >> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
>> >> -
>> >> - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
>> >> - cpu_relax();
>> >> -
>> >> - /* Change Divider - CPU1 */
>> >> - tmp = apll_freq_4x12[div_index].clk_div_cpu1;
>> >> -
>> >> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
>> >> - if (soc_is_exynos4212())
>> >> - stat_cpu1 = 0x11;
>> >> - else
>> >> - stat_cpu1 = 0x111;
>> >> -
>> >> - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
>> >> - cpu_relax();
>> >> -}
>> >> -
>> >> -static void exynos4x12_set_apll(unsigned int index)
>> >> -{
>> >> - unsigned int tmp, freq = apll_freq_4x12[index].freq;
>> >> -
>> >> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
>> >> - clk_set_parent(moutcore, mout_mpll);
>> >> -
>> >> - do {
>> >> - cpu_relax();
>> >> - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
>> >> - >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
>> >> - tmp &= 0x7;
>> >> - } while (tmp != 0x2);
>> >> -
>> >> - clk_set_rate(mout_apll, freq * 1000);
>> >> -
>> >> - /* MUX_CORE_SEL = APLL */
>> >> - clk_set_parent(moutcore, mout_apll);
>> >> -
>> >> - do {
>> >> - cpu_relax();
>> >> - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
>> >> - tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
>> >> - } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
>> >> -}
>> >> -
>> >> -static void exynos4x12_set_frequency(unsigned int old_index,
>> >> - unsigned int new_index)
>> >> -{
>> >> - if (old_index > new_index) {
>> >> - exynos4x12_set_clkdiv(new_index);
>> >> - exynos4x12_set_apll(new_index);
>> >> - } else if (old_index < new_index) {
>> >> - exynos4x12_set_apll(new_index);
>> >> - exynos4x12_set_clkdiv(new_index);
>> >> - }
>> >> -}
>> >> -
>> >> -int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
>> >> -{
>> >> - unsigned long rate;
>> >> -
>> >> - cpu_clk = clk_get(NULL, "armclk");
>> >> - if (IS_ERR(cpu_clk))
>> >> - return PTR_ERR(cpu_clk);
>> >> -
>> >> - moutcore = clk_get(NULL, "moutcore");
>> >> - if (IS_ERR(moutcore))
>> >> - goto err_moutcore;
>> >> -
>> >> - mout_mpll = clk_get(NULL, "mout_mpll");
>> >> - if (IS_ERR(mout_mpll))
>> >> - goto err_mout_mpll;
>> >> -
>> >> - rate = clk_get_rate(mout_mpll) / 1000;
>> >> -
>> >> - mout_apll = clk_get(NULL, "mout_apll");
>> >> - if (IS_ERR(mout_apll))
>> >> - goto err_mout_apll;
>> >> -
>> >> - if (soc_is_exynos4212())
>> >> - apll_freq_4x12 = apll_freq_4212;
>> >> - else
>> >> - apll_freq_4x12 = apll_freq_4412;
>> >> -
>> >> - info->mpll_freq_khz = rate;
>> >> - /* 800Mhz */
>> >> - info->pll_safe_idx = L7;
>> >> - info->cpu_clk = cpu_clk;
>> >> - info->volt_table = exynos4x12_volt_table;
>> >> - info->freq_table = exynos4x12_freq_table;
>> >> - info->set_freq = exynos4x12_set_frequency;
>> >> -
>> >> - return 0;
>> >> -
>> >> -err_mout_apll:
>> >> - clk_put(mout_mpll);
>> >> -err_mout_mpll:
>> >> - clk_put(moutcore);
>> >> -err_moutcore:
>> >> - clk_put(cpu_clk);
>> >> -
>> >> - pr_debug("%s: failed initialization\n", __func__);
>> >> - return -EINVAL;
>> >> -}
>> >> diff --git a/drivers/cpufreq/exynos5250-cpufreq.c
>> >> b/drivers/cpufreq/exynos5250-cpufreq.c deleted file mode 100644
>> >> index 5f90b82..0000000
>> >> --- a/drivers/cpufreq/exynos5250-cpufreq.c
>> >> +++ /dev/null
>> >> @@ -1,183 +0,0 @@
>> >> -/*
>> >> - * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
>> >> - * http://www.samsung.com
>> >> - *
>> >> - * EXYNOS5250 - CPU frequency scaling support
>> >> - *
>> >> - * This program is free software; you can redistribute it and/or
>> >> modify
>> >> - * it under the terms of the GNU General Public License version 2
>> >> as
>> >> - * published by the Free Software Foundation.
>> >> -*/
>> >> -
>> >> -#include <linux/module.h>
>> >> -#include <linux/kernel.h>
>> >> -#include <linux/err.h>
>> >> -#include <linux/clk.h>
>> >> -#include <linux/io.h>
>> >> -#include <linux/slab.h>
>> >> -#include <linux/cpufreq.h>
>> >> -
>> >> -#include <mach/map.h>
>> >> -
>> >> -#include "exynos-cpufreq.h"
>> >> -
>> >> -static struct clk *cpu_clk;
>> >> -static struct clk *moutcore;
>> >> -static struct clk *mout_mpll;
>> >> -static struct clk *mout_apll;
>> >> -
>> >> -static unsigned int exynos5250_volt_table[] = {
>> >> - 1300000, 1250000, 1225000, 1200000, 1150000,
>> >> - 1125000, 1100000, 1075000, 1050000, 1025000,
>> >> - 1012500, 1000000, 975000, 950000, 937500,
>> >> - 925000
>> >> -};
>> >> -
>> >> -static struct cpufreq_frequency_table exynos5250_freq_table[] = {
>> >> - {L0, 1700 * 1000},
>> >> - {L1, 1600 * 1000},
>> >> - {L2, 1500 * 1000},
>> >> - {L3, 1400 * 1000},
>> >> - {L4, 1300 * 1000},
>> >> - {L5, 1200 * 1000},
>> >> - {L6, 1100 * 1000},
>> >> - {L7, 1000 * 1000},
>> >> - {L8, 900 * 1000},
>> >> - {L9, 800 * 1000},
>> >> - {L10, 700 * 1000},
>> >> - {L11, 600 * 1000},
>> >> - {L12, 500 * 1000},
>> >> - {L13, 400 * 1000},
>> >> - {L14, 300 * 1000},
>> >> - {L15, 200 * 1000},
>> >> - {0, CPUFREQ_TABLE_END},
>> >> -};
>> >> -
>> >> -static struct apll_freq apll_freq_5250[] = {
>> >> - /*
>> >> - * values:
>> >> - * freq
>> >> - * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG,
>> >> APLL, ARM2
>> >> - * clock divider for COPY, HPM, RESERVED
>> >> - * PLL M, P, S
>> >> - */
>> >> - APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
>> >> - APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
>> >> - APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
>> >> - APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
>> >> - APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
>> >> - APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
>> >> - APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
>> >> - APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
>> >> - APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
>> >> - APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
>> >> - APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
>> >> - APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
>> >> - APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
>> >> - APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
>> >> - APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
>> >> - APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
>> >> -};
>> >> -
>> >> -static void set_clkdiv(unsigned int div_index)
>> >> -{
>> >> - unsigned int tmp;
>> >> -
>> >> - /* Change Divider - CPU0 */
>> >> -
>> >> - tmp = apll_freq_5250[div_index].clk_div_cpu0;
>> >> -
>> >> - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
>> >> -
>> >> - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
>> >> - cpu_relax();
>> >> -
>> >> - /* Change Divider - CPU1 */
>> >> - tmp = apll_freq_5250[div_index].clk_div_cpu1;
>> >> -
>> >> - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
>> >> -
>> >> - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
>> >> - cpu_relax();
>> >> -}
>> >> -
>> >> -static void set_apll(unsigned int index)
>> >> -{
>> >> - unsigned int tmp;
>> >> - unsigned int freq = apll_freq_5250[index].freq;
>> >> -
>> >> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
>> >> - clk_set_parent(moutcore, mout_mpll);
>> >> -
>> >> - do {
>> >> - cpu_relax();
>> >> - tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
>> >> - tmp &= 0x7;
>> >> - } while (tmp != 0x2);
>> >> -
>> >> - clk_set_rate(mout_apll, freq * 1000);
>> >> -
>> >> - /* MUX_CORE_SEL = APLL */
>> >> - clk_set_parent(moutcore, mout_apll);
>> >> -
>> >> - do {
>> >> - cpu_relax();
>> >> - tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
>> >> - tmp &= (0x7 << 16);
>> >> - } while (tmp != (0x1 << 16));
>> >> -}
>> >> -
>> >> -static void exynos5250_set_frequency(unsigned int old_index,
>> >> - unsigned int new_index)
>> >> -{
>> >> - if (old_index > new_index) {
>> >> - set_clkdiv(new_index);
>> >> - set_apll(new_index);
>> >> - } else if (old_index < new_index) {
>> >> - set_apll(new_index);
>> >> - set_clkdiv(new_index);
>> >> - }
>> >> -}
>> >> -
>> >> -int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
>> >> -{
>> >> - unsigned long rate;
>> >> -
>> >> - cpu_clk = clk_get(NULL, "armclk");
>> >> - if (IS_ERR(cpu_clk))
>> >> - return PTR_ERR(cpu_clk);
>> >> -
>> >> - moutcore = clk_get(NULL, "mout_cpu");
>> >> - if (IS_ERR(moutcore))
>> >> - goto err_moutcore;
>> >> -
>> >> - mout_mpll = clk_get(NULL, "mout_mpll");
>> >> - if (IS_ERR(mout_mpll))
>> >> - goto err_mout_mpll;
>> >> -
>> >> - rate = clk_get_rate(mout_mpll) / 1000;
>> >> -
>> >> - mout_apll = clk_get(NULL, "mout_apll");
>> >> - if (IS_ERR(mout_apll))
>> >> - goto err_mout_apll;
>> >> -
>> >> - info->mpll_freq_khz = rate;
>> >> - /* 800Mhz */
>> >> - info->pll_safe_idx = L9;
>> >> - info->cpu_clk = cpu_clk;
>> >> - info->volt_table = exynos5250_volt_table;
>> >> - info->freq_table = exynos5250_freq_table;
>> >> - info->set_freq = exynos5250_set_frequency;
>> >> -
>> >> - return 0;
>> >> -
>> >> -err_mout_apll:
>> >> - clk_put(mout_mpll);
>> >> -err_mout_mpll:
>> >> - clk_put(moutcore);
>> >> -err_moutcore:
>> >> - clk_put(cpu_clk);
>> >> -
>> >> - pr_err("%s: failed initialization\n", __func__);
>> >> - return -EINVAL;
>> >> -}
>> >
>> >
>> >
>> > --
>> > Best regards,
>> >
>> > Lukasz Majewski
>> >
>> > Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
>> --
>> To unsubscribe from this list: send the line "unsubscribe cpufreq" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
>
>
> --
> Best regards,
>
> Lukasz Majewski
>
> Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply
* [ath9k-devel] [PATCH 1/3] ath9k: Fix build error on ARM
From: Russell King - ARM Linux @ 2014-02-05 12:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391603566.2538.63.camel@joe-AO722>
On Wed, Feb 05, 2014 at 04:32:46AM -0800, Joe Perches wrote:
> On Wed, 2014-02-05 at 11:50 +0000, Russell King - ARM Linux wrote:
> > On Tue, Feb 04, 2014 at 08:36:36AM -0800, Joe Perches wrote:
> > > On Tue, 2014-02-04 at 08:03 +0100, Holger Schurig wrote:
> > > > Joe, look in linux/arch/arm/include/asm/delay.h. The macro udelay
> > > > cannot handle large values because of lost-of-precision.
> > > >
> > > > IMHO udelay on ARM is broken, because it also cannot work with fast
> > > > ARM processors (where bogomips >= 3355, which is in sight now). It's
> > > > just not broken enought that someone did something against it ... so
> > > > the current kludge is good enought.
> > >
> > > Maybe something like this would be better?
> >
> > No, the point of __bad_udelay() is that people doing stupidly large
> > udelay()s result in build errors,
>
> Apparently, people just convert stupidly large udelay()s
> to mdelay and not be bothered.
And that's the correct answer. Having udelay(10000) rather than mdelay(10)
is a sign that they weren't paying that much attention when writing the
code.
> Perhaps there should be some runtime udelay > maximum supported check.
Having both a runtime check _and_ a compile time check would actually
be a good thing, but any runtime check needs to be suitably rate-
limited.
The compile time check is very important because it catches a lot of
cases which wouldn't otherwise be found (eg, in drivers which hardly
anyone uses on ARM.)
Maybe the compile time check should be something which is implemented
in a cross-architecture way in linux/delay.h with the maximum set to
the lowest that any architecture can do?
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* [PATCH 1/3] clk: rcar-h2: fix sd0/sd1 divisor table
From: Ben Dooks @ 2014-02-05 12:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F226A0.5070301@codethink.co.uk>
On 05/02/14 11:55, Ben Dooks wrote:
> On 05/02/14 10:56, Laurent Pinchart wrote:
>> Hi William,
>>
>> Thank you for the patch.
>>
>> On Tuesday 04 February 2014 18:17:36 William Towle wrote:
>>> The clk_div_table for cpg_sd01_div_table[] concurs with the manual
>>> but not with values found in the device itself (which are also the
>>> same as the ones in arch/arm/mach-shmobile/clock-r8a7790.c).
>>>
>>> Update the clk-rcar-gen2.c driver to have the same table as the one
>>> used by the mach-shmobile driver which work once further issues are
>>> fixed in the clk-rcar-gen2.c driver.
>>>
>>> Part of the fix for the following error where the driver reports the
>>> output as 1MHz but is really 97.5MHz:
>>> sh_mobile_sdhi ee100000.sd: mmc0 base at 0xee100000 clock rate 1
>>> MHz
>>>
>>> [ben.dooks at codethink.co.uk: updated patch description]
>>> Signed-off-by: William Towle <william.towle@codethink.co.uk>
>>> Reviewed-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>> ---
>>> drivers/clk/shmobile/clk-rcar-gen2.c | 2 ++
>>> 1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c
>>> b/drivers/clk/shmobile/clk-rcar-gen2.c index a59ec21..df4a1e6 100644
>>> --- a/drivers/clk/shmobile/clk-rcar-gen2.c
>>> +++ b/drivers/clk/shmobile/clk-rcar-gen2.c
>>> @@ -170,6 +170,8 @@ static const struct clk_div_table
>>> cpg_sdh_div_table[] =
>>> { };
>>>
>>> static const struct clk_div_table cpg_sd01_div_table[] = {
>>> + { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
>>> + { 4, 8 },
>>> { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
>>> { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
>>
>> With this applied the only difference between the sdh and sd0/1 dividers
>> tables would be the { 12, 10 } entry, available for sd0/1 only. Given
>> that the
>> hardware does not match the documentation, could you check whether
>> that entry
>> is supported by sdh as well ? If so we could merge the two tables.
>> Otherwise
>> this patch looks good, could you please just reformat the table to
>> avoid the
>> mostly empty line in the middle ?
>
> I would like feedback from Renesas on this issue if possible. I can
> have a quick try at setting the clock value to 10 in u-boot and scope
> it out and see what happens.
>
> Magnus or Morimoto-san, is there a chance this could be reviewed by
> someone in Renesas who has knowledge of the hardware block?
>
> [PS, added Kuninori Morimoto to this[
I got William to do a quick test with the following u-boot command
mw.l 0xE6150074 0xCCC
sdhi0 showed 156MHz output, and it seemed to work. So there is a
distinct possibility that the sdh clock also supports setting 12
for a /10
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
^ permalink raw reply
* [ath9k-devel] [PATCH 1/3] ath9k: Fix build error on ARM
From: Joe Perches @ 2014-02-05 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205115035.GO26684@n2100.arm.linux.org.uk>
On Wed, 2014-02-05 at 11:50 +0000, Russell King - ARM Linux wrote:
> On Tue, Feb 04, 2014 at 08:36:36AM -0800, Joe Perches wrote:
> > On Tue, 2014-02-04 at 08:03 +0100, Holger Schurig wrote:
> > > Joe, look in linux/arch/arm/include/asm/delay.h. The macro udelay
> > > cannot handle large values because of lost-of-precision.
> > >
> > > IMHO udelay on ARM is broken, because it also cannot work with fast
> > > ARM processors (where bogomips >= 3355, which is in sight now). It's
> > > just not broken enought that someone did something against it ... so
> > > the current kludge is good enought.
> >
> > Maybe something like this would be better?
>
> No, the point of __bad_udelay() is that people doing stupidly large
> udelay()s result in build errors,
Apparently, people just convert stupidly large udelay()s
to mdelay and not be bothered.
> rather than having to run the kernel
> and trip over a non-existent debugging message beacuse they haven't
> built the kernel with DEBUG defined.
>
> NAK.
<shrug>
Perhaps there should be some runtime udelay > maximum
supported check.
^ permalink raw reply
* [GIT PULL] ARM: imx: device tree changes for 3.15, take 1
From: Shawn Guo @ 2014-02-05 12:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi arm-soc folks,
This is basically imx-dt-3.14 pull request that missed the 3.14 merge
window with the pingrp removal series applied on top of. It also
includes a few additional board support I collected since imx-dt-3.14.
There will be another round of IMX DT changes for 3.15 later, but this
one should be the majority. Please pull, thanks.
Shawn
The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:
Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)
are available in the git repository at:
git://git.linaro.org/people/shawnguo/linux-2.6.git tags/imx-dt-3.15
for you to fetch changes up to 6e63728deb5340f6a4988d98ff86227abf62c81d:
ARM: dts: imx28-m28cu3: Remove 'reset-active-high' (2014-02-03 22:57:45 +0800)
----------------------------------------------------------------
i.MX device tree changes for 3.15:
- New SoC device tree support for imx35 and imx50.
- A good number of new i.MX6 boards support: SolidRun HummingBoard,
cm-fx6, dmo-edmqmx6, nitrogen6x, Gateworks Ventana gw5xxx family,
DFI FS700-M60 and Zealz GK802.
- A few other new i.MX boards support: imx25-eukrea, imx28-duckbill,
imx28-eukrea, Eukrea cpuimx35, imx50-evk, imx51-eukrea, imx53-voipac,
MCIMX53-START-R and Ka-Ro TX53.
- Add pinfunc headers for imx25, imx27 and imx50.
- Make pinctrl nodes board specific to avoid floating board specific
device tree blob with so many unused pinctrl data.
- Use clock defines in imx5 DTS files.
- Update imx6q-sabrelite device tree and add Dual Lite/Solo support.
- Use GPIO_6 for FEC interrupt to workaround a hardware bug (ERR006687
ENET: Only the ENET wake-up interrupt request can wake the system
from Wait mode.)
- A plenty of random updates on various SoC and board device tree
sources, adding pinctrl settings, device nodes, properties, etc.
----------------------------------------------------------------
Aida Mynzhasova (1):
ARM: dts: mxs: add auart2 pinmux to imx28.dtsi
Alexander Shiyan (26):
ARM: dts: i.MX51: Update CPU node
ARM: dts: i.MX51: Add dummy clock to AUDMUX
ARM: dts: i.MX51: Switch to use standard IRQ flags definitions
ARM: dts: i.MX51: Move usbphy0 node from AIPS1
ARM: dts: i.MX51 boards: Switch to use standard GPIO flags definitions
ARM: dts: imx51-babbage: Fix chipselect level for dataflash on spi0.1
ARM: dts: imx51-babbage: Define FEC reset pin
ARM: dts: imx27-phytec-phycore-som: Add on-flash BBT support
ARM: dts: imx27-phytec-phycore-rdk: Add DT node for camera module
ARM: dts: imx27-phytec-phycore-som: Update FEC node
ARM: dts: i.MX27 boards: Switch to use standard GPIO and IRQ flags definitions
ARM: dts: i.MX27: Configure GPIOs as "input" by default
ARM: dts: i.MX: Move include "imxXX-pinfunc.h" into "imxXX-pingrp.h"
ARM: dts: imx27-phytec-phycore-rdk: Change pinctrl settings for I2C1
ARM: dts: imx27-phytec-phycore-som: trivial: Typo fix
ARM: dts: imx27-phytec-phycore-som: Add pinctrl for CSPI1 and GPIOs used on module
ARM: dts: imx27-phytec-phycore-som: Rename file to .dtsi
ARM: dts: imx27-phytec-phycore-som: Add NFC pin group
ARM: dts: imx27-phytec-phycore-rdk: Enable 1-Wire module
ARM: dts: imx27-phytec-phycore-som: Add spi-cs-high property to PMIC
ARM: dts: i.MX27: Add missing pullup settings for SDHC pin groups
ARM: dts: imx27-phytec-phycore-rdk: Add pingrp for SDHC
ARM: dts: imx27-phytec-phycore-rdk: Add pinctrl definitions for WEIM
ARM: dts: i.MX27: Add SSI nodes
ARM: dts: imx53-evk: Remove board support
ARM: dts: i.MX51: Switch to use standard definitions for input subsystem
Alexandre Belloni (3):
ARM: dts: mxs: add #io-channel-cells to mx28 lradc
ARM: dts: mxs: Add iio-hwmon to mx28 soc
ARM: dts: mxs: Add iio-hwmon to mx23 soc
Anson Huang (7):
ARM: dts: imx6q: update setting of VDDARM_CAP voltage
ARM: dts: imx6q: add vddsoc/pu setpoint info
ARM: dts: imx6dl: enable cpufreq support
ARM: dts: imx6qdl: add necessary thermal clk
ARM: dts: imx6qdl-sabresd: Add power key support
ARM: dts: imx6sl: add ocram device support
ARM: dts: imx6sl: add keypad support for i.mx6sl-evk board.
Denis Carikli (15):
of: add vendor prefix for Eukrea Electromatique.
ARM: dts: i.MX25: Add ssi clocks and DMA events.
ARM: dts: i.MX25: Add sdma script path.
ARM: dts: imx25.dtsi: Add a label for the Audio Multiplexer.
ARM: dts: imx51.dtsi: Add some pinmux pins.
ARM: dts: Add support for the cpuimx51 board from Eukrea and its baseboard.
ARM: dts: imx25: Add pinctrl functions and groups.
ARM: dts: imx25.dtsi: label the iomuxc.
ARM: dts: mxs: Add 18bit pin config for lcdif.
ARM: dts: mxs: Add a new pin config for the usb0 ID.
ARM: dts: Add support for the cpuimx25 board from Eukrea and its baseboard.
ARM: dts: mbimxsd25: Add sound support.
ARM: dts: mbimxsd51: Add sound support.
ARM: dts: imx53: Add gpio and input dt includes.
ARM: dts: Add support for the cpuimx35 board from Eukrea and its baseboard.
Eric B?nard (1):
ARM: mxs: Add support for the eukrea-cpuimx28.
Fabio Estevam (8):
ARM: dts: imx6q-udoo: Add Ethernet support
ARM: dts: imx6q-sabrelite: Remove duplicate GPIO entry
ARM: dts: imx6q-sabrelite: Place 'status' as the last node
ARM: dts: imx28-evk: Run I2C0 at 400kHz
ARM: dts: imx6: Use 'vddarm' as the regulator name
ARM: dts: imx6qdl-sabresd: Add PFUZE100 support
ARM: dts: imx6qdl-sabreauto: Add LVDS support
ARM: dts: imx28-m28cu3: Remove 'reset-active-high'
Frank Li (1):
ARM: dts: imxqdl: enable dma for spi
Greg Ungerer (3):
ARM: dts: imx: add device tree pin definitions for the IMX50
ARM: dts: imx: add IMX50 SoC device tree
ARM: dts: imx: add device tree support for Freescale imx50evk board
Gwenhael Goavec-Merou (10):
ARM: imx27-apf27dev: Add sdhci support
ARM: dts: imx27-apf27dev: fix display size
ARM: imx27: add pingroups for cspi, sdhc and framebuffer
ARM: dts: imx27: imx27-apf27: add pinctrl for fec and uart1
ARM: dts: imx27: imx27-apf27dev: add pinctrl for cspi, i2c, sdhc and framebuffer
ARM: dts: apf28dev: set gpio polarity for usb regulator and pinctrl for regulator gpio
ARM: imx28: add apf28 specific initialization (macaddr)
ARM: imx27: add pwm pingrp
ARM: dts: apf27dev: Add pwm support
ARM: dts: imx27-apf27dev: Add pinctrl for cspi, sdhci, leds and keys
Huang Shijie (1):
ARM: dts: vf610: use the interrupt macros
John Tobias (1):
ARM: dts: imx6sl: Adding cpu frequency and VDDSOC/PU table.
Lothar Wa?mann (4):
ARM: dts: imx6qdl: add aliases for can interfaces
ARM: dts: imx6qdl: add pingroup for enet interface in RMII mode
ARM: dts: imx6qdl: add new pingroup for audmux
ARM: dts: imx53: add support for Ka-Ro TX53 modules
Lucas Stach (3):
ARM: imx53: use clock defines in DTS files
ARM: imx51: use clock defines in DTS files
ARM: imx50: use clock defines in DTS files
Marek Vasut (6):
ARM: dts: imx53: Fix display pinmux for M53EVK
ARM: dts: imx53: Fix backlight for M53EVK
ARM: dts: imx53: Add USB support for M53EVK
ARM: dts: imx53: Add AHCI SATA DT node
ARM: dts: imx53: Enable AHCI SATA for M53EVK
ARM: dts: imx6q-sabrelite: Enable PCI express
Markus Pargmann (7):
ARM: dts: imx27 pin functions
ARM: dts: imx27 pingroups
ARM: dts: imx27 iomux device node
ARM: dts: imx27 phyCARD-S pinctrl
ARM: dts: imx27 phycore move uart1 to rdk
ARM: dts: imx27 phycore pinctrl
ARM: DTS: imx5* imx6*, use imx51-ssi
Maxime Ripard (2):
ARM: mxs: cfa10049: Add NAU7802 ADCs to the device tree
ARM: dts: cfa10036: Add dr_mode and phy_type properties to the DT
Michael Grzeschik (1):
ARM: i.MX28: dts: rename usbphy pin names
Michael Heimpold (1):
ARM: mxs: add support for I2SE's duckbill series
Nicolin Chen (2):
ARM: dts: imx: specify the value of audmux pinctrl instead of 0x80000000
ARM: dts: imx6qdl: add spdif support for sabreauto
Peter Chen (3):
ARM: dts: imx6q-arm2: enable USB OTG
ARM: dts: imx6: add anatop phandle for usbphy
ARM: dts: imx: add mxs phy controller id
Philipp Zabel (2):
ARM: dts: imx6q-sabrelite: PHY reset is active-low
ARM: dts: imx6: edmqmx6: add PF0100 PMIC to device tree
Robert Nelson (1):
ARM: dts: imx53: Enable AHCI SATA for imx53-qsb
Rostislav Lisovy (8):
ARM: dts: i.MX53: Add alternate pinmux option for i2c_3
ARM: dts: i.MX53: Internal keyboard controller
ARM: dts: Add vendor prefix for Voipac Technologies s.r.o.
ARM: dts: i.MX53: dts for Voipac x53-dmm-668 module
ARM: dts: i.MX53: Devicetree for Voipac Baseboard using x53-dmm-668 module
ARM: dts: voipac: Improve fixed voltage regulator definition
ARM: i.MX53: dts: NAND flash controller
ARM: i.MX53: dts: USB host controller
Sascha Hauer (9):
ARM: dts: imx53: Add mmc aliases
ARM: dts: imx6q: Add spi4 alias
ARM: dts: imx6qdl: Add mmc aliases
ARM: dts: imx51: Add mmc aliases
ARM: dts: imx6: Add DFI FS700-M60 board support
ARM: dts: imx6: edmqmx6: Add usdhc4 (emmc) support
ARM: dts: imx6: edmqmx6: Add sata support
ARM: dts: imx6: edmqmx6: Add LED support
ARM: dts: imx6q: Add support for Zealz GK802
Shawn Guo (17):
ARM: dts: imx6qdl: make pinctrl nodes board specific
ARM: dts: imx6sl: make pinctrl nodes board specific
ARM: dts: imx53: make pinctrl nodes board specific
ARM: dts: imx51: make pinctrl nodes board specific
ARM: dts: imx50: make pinctrl nodes board specific
ARM: dts: imx53-mba53: create a container for fixed regulators
ARM: dts: imx: use generic node name for fixed regulator
ARM: dts: vf610: make pinctrl nodes board specific
ARM: dts: imx6qdl: remove the use of pingrp macros
ARM: dts: imx6sl: remove the use of pingrp macros
ARM: dts: imx53: remove the use of pingrp macros
ARM: dts: imx51: remove the use of pingrp macros
ARM: dts: imx50: remove the use of pingrp macros
ARM: dts: imx35: remove the use of pingrp macros
ARM: dts: imx25: remove the use of pingrp macros
ARM: dts: imx27: remove the use of pingrp macros
ARM: dts: vf610: remove the use of pingrp macros
Silvio F (2):
DT: Add Data Modul vendor prefix
ARM: dts: imx6: Add support for imx6q dmo edmqmx6
Steffen Trumtrar (3):
ARM: dts: Add support for the i.MX35.
ARM: i.MX53: dts: move common QSB nodes to new file
ARM: i.MX53: dts: add support for MCIMX53-START-R
S?bastien Szymanski (1):
ARM: dts: imx28-apf28dev: add user button
Tim Harvey (3):
ARM: dts: disable flexcan by default
ARM: dts: added several new imx-pinmux groups
ARM: dts: add Gateworks Ventana support
Troy Kisky (30):
ARM: dts: imx: pinfunc: add MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT
ARM: dts: imx: imx6qdl.dtsi: add mipi_csi tag
ARM: dts: imx: imx6q.dtsi: use IRQ_TYPE_LEVEL_HIGH
ARM: dts: imx: imx6dl.dtsi: use IRQ_TYPE_LEVEL_HIGH
ARM: dts: imx: imx6sl.dtsi: use IRQ_TYPE_LEVEL_HIGH
ARM: dts: imx: imx6qdl.dtsi: use IRQ_TYPE_LEVEL_HIGH
ARM: dts: imx: imx6sl/qdl-pingrp: reorganize USDHCx pad groups
ARM: dts: imx: sabrelite: add Dual Lite/Solo support
ARM: dts: imx6qdl-sabrelite: Add uart1 support
ARM: dts: imx6qdl-sabrelite: remove usdhc4 wp-gpio
ARM: dts: imx6qdl-sabrelite: move pcie to imx6qdl-sabrelite.dtsi
ARM: dts: imx6qdl-sabrelite: move USDHC4 CD to pinctrl_usdhc4
ARM: dts: imx6qdl-sabrelite: move USDHC3 CD/WP to pinctrl_usdhc3
ARM: dts: imx6qdl-sabrelite: move spi-nor CS to pinctrl_ecspi1
ARM: dts: imx6qdl-sabrelite: move usbotg power enable to pinctrl_usbotg
ARM: dts: imx6qdl-sabrelite: move phy reset to pinctrl_enet
ARM: dts: imx6qdl-sabrelite: explicitly set pad for SGTL5000 sys_mclk
ARM: dts: imx6qdl-sabrelite: add pwms for backlights
ARM: dts: imx6qdl-sabrelite: add skews for Micrel phy
ARM: dts: imx6qdl-sabrelite: fix ENET group
ARM: dts: imx6qdl-sabrelite: Add over-current pin to usbotg
ARM: dts: imx: add nitrogen6x board
ARM: dts: imx6qdl-sabrelite: add gpio-keys
ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ
ARM: dts: imx6qdl: add pingroups for enet with GPIO6 interrupt
ARM: dts: imx6qdl-sabrelite: use MX6QDL_ENET_PINGRP_RGMII_MD
ARM: dts: imx6qdl: use interrupts-extended for fec
ARM: dts: imx6qdl-sabrelite: use GPIO_6 for FEC interrupt.
ARM: dts: imx6qdl-sabreauto: use GPIO_6 for FEC interrupt.
ARM: dts: imx6q-arm2: use GPIO_6 for FEC interrupt.
Valentin Raevsky (1):
ARM: dts: Add initial support for cm-fx6.
.../devicetree/bindings/vendor-prefixes.txt | 3 +
arch/arm/boot/dts/Makefile | 30 +-
arch/arm/boot/dts/imx23-evk.dts | 8 +-
arch/arm/boot/dts/imx23-olinuxino.dts | 5 +-
arch/arm/boot/dts/imx23-stmp378x_devb.dts | 5 +-
arch/arm/boot/dts/imx23.dtsi | 8 +-
arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi | 73 ++
.../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 174 ++++
arch/arm/boot/dts/imx25-pinfunc.h | 494 +++++++++++
arch/arm/boot/dts/imx25.dtsi | 18 +-
arch/arm/boot/dts/imx27-apf27.dts | 38 +
arch/arm/boot/dts/imx27-apf27dev.dts | 149 +++-
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 61 +-
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | 42 +-
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 97 +-
...ycore-som.dts => imx27-phytec-phycore-som.dtsi} | 95 +-
arch/arm/boot/dts/imx27-pinfunc.h | 526 +++++++++++
arch/arm/boot/dts/imx27.dtsi | 151 ++--
arch/arm/boot/dts/imx28-apf28dev.dts | 29 +-
arch/arm/boot/dts/imx28-apx4devkit.dts | 5 +-
arch/arm/boot/dts/imx28-cfa10036.dts | 2 +
arch/arm/boot/dts/imx28-cfa10037.dts | 7 +-
arch/arm/boot/dts/imx28-cfa10049.dts | 31 +-
arch/arm/boot/dts/imx28-cfa10057.dts | 7 +-
arch/arm/boot/dts/imx28-cfa10058.dts | 7 +-
arch/arm/boot/dts/imx28-duckbill.dts | 121 +++
arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts | 71 ++
arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts | 50 ++
arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi | 326 +++++++
arch/arm/boot/dts/imx28-evk.dts | 24 +-
arch/arm/boot/dts/imx28-m28cu3.dts | 17 +-
arch/arm/boot/dts/imx28-m28evk.dts | 18 +-
arch/arm/boot/dts/imx28-sps1.dts | 7 +-
arch/arm/boot/dts/imx28-tx28.dts | 23 +-
arch/arm/boot/dts/imx28.dtsi | 65 +-
arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi | 81 ++
.../boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts | 143 +++
arch/arm/boot/dts/imx35.dtsi | 359 ++++++++
arch/arm/boot/dts/imx50-evk.dts | 119 +++
arch/arm/boot/dts/imx50-pinfunc.h | 923 +++++++++++++++++++
arch/arm/boot/dts/imx50.dtsi | 478 ++++++++++
arch/arm/boot/dts/imx51-apf51.dts | 40 +-
arch/arm/boot/dts/imx51-apf51dev.dts | 102 ++-
arch/arm/boot/dts/imx51-babbage.dts | 248 +++++-
arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | 93 ++
.../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 174 ++++
arch/arm/boot/dts/imx51.dtsi | 459 ++--------
arch/arm/boot/dts/imx53-ard.dts | 33 +-
arch/arm/boot/dts/imx53-evk.dts | 126 ---
arch/arm/boot/dts/imx53-m53evk.dts | 233 ++++-
arch/arm/boot/dts/imx53-mba53.dts | 40 +-
arch/arm/boot/dts/imx53-qsb-common.dtsi | 336 +++++++
arch/arm/boot/dts/imx53-qsb.dts | 210 +----
arch/arm/boot/dts/imx53-qsrb.dts | 158 ++++
arch/arm/boot/dts/imx53-smd.dts | 119 ++-
arch/arm/boot/dts/imx53-tqma53.dtsi | 175 +++-
arch/arm/boot/dts/imx53-tx53-x03x.dts | 315 +++++++
arch/arm/boot/dts/imx53-tx53-x13x.dts | 243 +++++
arch/arm/boot/dts/imx53-tx53.dtsi | 511 ++++++++++-
arch/arm/boot/dts/imx53-voipac-bsb.dts | 159 ++++
arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | 277 ++++++
arch/arm/boot/dts/imx53.dtsi | 663 +++-----------
arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts | 23 +
arch/arm/boot/dts/imx6dl-gw51xx.dts | 19 +
arch/arm/boot/dts/imx6dl-gw52xx.dts | 19 +
arch/arm/boot/dts/imx6dl-gw53xx.dts | 19 +
arch/arm/boot/dts/imx6dl-gw54xx.dts | 19 +
arch/arm/boot/dts/imx6dl-nitrogen6x.dts | 21 +
arch/arm/boot/dts/imx6dl-pinfunc.h | 2 +
arch/arm/boot/dts/imx6dl-sabrelite.dts | 20 +
arch/arm/boot/dts/imx6dl.dtsi | 29 +-
arch/arm/boot/dts/imx6q-arm2.dts | 140 ++-
arch/arm/boot/dts/imx6q-cm-fx6.dts | 107 +++
arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts | 23 +
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 372 ++++++++
arch/arm/boot/dts/imx6q-gk802.dts | 171 ++++
arch/arm/boot/dts/imx6q-gw51xx.dts | 19 +
arch/arm/boot/dts/imx6q-gw52xx.dts | 23 +
arch/arm/boot/dts/imx6q-gw53xx.dts | 23 +
arch/arm/boot/dts/imx6q-gw5400-a.dts | 546 ++++++++++++
arch/arm/boot/dts/imx6q-gw54xx.dts | 23 +
arch/arm/boot/dts/imx6q-nitrogen6x.dts | 25 +
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 85 +-
arch/arm/boot/dts/imx6q-pinfunc.h | 2 +
arch/arm/boot/dts/imx6q-sabrelite.dts | 178 +---
arch/arm/boot/dts/imx6q-sbc6x.dts | 58 +-
arch/arm/boot/dts/imx6q-udoo.dts | 54 +-
arch/arm/boot/dts/imx6q.dtsi | 21 +-
arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 199 +++++
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 374 ++++++++
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 490 ++++++++++
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 553 ++++++++++++
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 580 ++++++++++++
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 422 +++++++++
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 246 ++++-
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 423 +++++++++
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 272 +++++-
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 128 ++-
arch/arm/boot/dts/imx6qdl.dtsi | 938 +++-----------------
arch/arm/boot/dts/imx6sl-evk.dts | 210 ++++-
arch/arm/boot/dts/imx6sl.dtsi | 385 +++-----
arch/arm/boot/dts/vf610-cosmic.dts | 29 +-
arch/arm/boot/dts/vf610-twr.dts | 66 +-
arch/arm/boot/dts/vf610.dtsi | 207 +----
arch/arm/mach-mxs/mach-mxs.c | 33 +
105 files changed, 14073 insertions(+), 3127 deletions(-)
create mode 100644 arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
create mode 100644 arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
create mode 100644 arch/arm/boot/dts/imx25-pinfunc.h
rename arch/arm/boot/dts/{imx27-phytec-phycore-som.dts => imx27-phytec-phycore-som.dtsi} (61%)
create mode 100644 arch/arm/boot/dts/imx27-pinfunc.h
create mode 100644 arch/arm/boot/dts/imx28-duckbill.dts
create mode 100644 arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
create mode 100644 arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
create mode 100644 arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
create mode 100644 arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
create mode 100644 arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
create mode 100644 arch/arm/boot/dts/imx35.dtsi
create mode 100644 arch/arm/boot/dts/imx50-evk.dts
create mode 100644 arch/arm/boot/dts/imx50-pinfunc.h
create mode 100644 arch/arm/boot/dts/imx50.dtsi
create mode 100644 arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
create mode 100644 arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
delete mode 100644 arch/arm/boot/dts/imx53-evk.dts
create mode 100644 arch/arm/boot/dts/imx53-qsb-common.dtsi
create mode 100644 arch/arm/boot/dts/imx53-qsrb.dts
create mode 100644 arch/arm/boot/dts/imx53-tx53-x03x.dts
create mode 100644 arch/arm/boot/dts/imx53-tx53-x13x.dts
create mode 100644 arch/arm/boot/dts/imx53-voipac-bsb.dts
create mode 100644 arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
create mode 100644 arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
create mode 100644 arch/arm/boot/dts/imx6dl-gw51xx.dts
create mode 100644 arch/arm/boot/dts/imx6dl-gw52xx.dts
create mode 100644 arch/arm/boot/dts/imx6dl-gw53xx.dts
create mode 100644 arch/arm/boot/dts/imx6dl-gw54xx.dts
create mode 100644 arch/arm/boot/dts/imx6dl-nitrogen6x.dts
create mode 100644 arch/arm/boot/dts/imx6dl-sabrelite.dts
create mode 100644 arch/arm/boot/dts/imx6q-cm-fx6.dts
create mode 100644 arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
create mode 100644 arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
create mode 100644 arch/arm/boot/dts/imx6q-gk802.dts
create mode 100644 arch/arm/boot/dts/imx6q-gw51xx.dts
create mode 100644 arch/arm/boot/dts/imx6q-gw52xx.dts
create mode 100644 arch/arm/boot/dts/imx6q-gw53xx.dts
create mode 100644 arch/arm/boot/dts/imx6q-gw5400-a.dts
create mode 100644 arch/arm/boot/dts/imx6q-gw54xx.dts
create mode 100644 arch/arm/boot/dts/imx6q-nitrogen6x.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
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