* [PATCH 06/13] ARM: shmobile: r8a7790: add Audio DMAC clock
From: Simon Horman @ 2014-02-06 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391666228.git.horms+renesas@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Audio DMAC can be controlled via sh-dma-engine
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/clock-r8a7790.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index a028f96..58f3dcf 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -201,6 +201,7 @@ enum {
MSTP717, MSTP716,
MSTP704,
MSTP522,
+ MSTP502, MSTP501,
MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
MSTP124,
@@ -236,6 +237,8 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
[MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
+ [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
+ [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
[MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
[MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
@@ -311,6 +314,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+ CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
+ CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
--
1.8.5.2
^ permalink raw reply related
* [PATCH 07/13] ARM: shmobile: r8a7790: add Audio DMAC support
From: Simon Horman @ 2014-02-06 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391666228.git.horms+renesas@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
R-Car H2 has many DMACs
(ex SYS-DMAC, 2D-DMAC, Audio-DMAC, USB-DMAC etc)
and, these DMAEngine needs DMA slave IDs to use it.
This patch adds new DMA slave ID list for r8a7790.
There, common part has RCAR_DMA_xxx prefix,
and Audio DMAC part has AUDIO_DMAC_SLAVE_xxx prefix.
Audio DMAC can be controlled via sh-dma-engine
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/include/mach/r8a7790.h | 25 ++++++++
arch/arm/mach-shmobile/setup-r8a7790.c | 90 +++++++++++++++++++++++++++
2 files changed, 115 insertions(+)
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 5fbfa28..2177325 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -3,6 +3,31 @@
#include <mach/rcar-gen2.h>
+/* DMA slave IDs */
+enum {
+ RCAR_DMA_SLAVE_INVALID,
+ AUDIO_DMAC_SLAVE_SSI0_TX,
+ AUDIO_DMAC_SLAVE_SSI0_RX,
+ AUDIO_DMAC_SLAVE_SSI1_TX,
+ AUDIO_DMAC_SLAVE_SSI1_RX,
+ AUDIO_DMAC_SLAVE_SSI2_TX,
+ AUDIO_DMAC_SLAVE_SSI2_RX,
+ AUDIO_DMAC_SLAVE_SSI3_TX,
+ AUDIO_DMAC_SLAVE_SSI3_RX,
+ AUDIO_DMAC_SLAVE_SSI4_TX,
+ AUDIO_DMAC_SLAVE_SSI4_RX,
+ AUDIO_DMAC_SLAVE_SSI5_TX,
+ AUDIO_DMAC_SLAVE_SSI5_RX,
+ AUDIO_DMAC_SLAVE_SSI6_TX,
+ AUDIO_DMAC_SLAVE_SSI6_RX,
+ AUDIO_DMAC_SLAVE_SSI7_TX,
+ AUDIO_DMAC_SLAVE_SSI7_RX,
+ AUDIO_DMAC_SLAVE_SSI8_TX,
+ AUDIO_DMAC_SLAVE_SSI8_RX,
+ AUDIO_DMAC_SLAVE_SSI9_TX,
+ AUDIO_DMAC_SLAVE_SSI9_RX,
+};
+
void r8a7790_add_standard_devices(void);
void r8a7790_add_dt_devices(void);
void r8a7790_clock_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 6ab37aa..c4616f0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -24,12 +24,100 @@
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
#include <mach/common.h>
+#include <mach/dma-register.h>
#include <mach/irqs.h>
#include <mach/r8a7790.h>
#include <asm/mach/arch.h>
+/* Audio-DMAC */
+#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
+{ \
+ .slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
+ .addr = _addr + 0x8, \
+ .chcr = CHCR_TX(XMIT_SZ_32BIT), \
+ .mid_rid = t, \
+}, { \
+ .slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
+ .addr = _addr + 0xc, \
+ .chcr = CHCR_RX(XMIT_SZ_32BIT), \
+ .mid_rid = r, \
+}
+
+static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
+ AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
+ AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
+ AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
+ AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
+ AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
+ AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
+ AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
+ AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
+ AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
+ AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
+};
+
+#define DMAE_CHANNEL(a, b) \
+{ \
+ .offset = (a) - 0x20, \
+ .dmars = (a) - 0x20 + 0x40, \
+ .chclr_bit = (b), \
+ .chclr_offset = 0x80 - 0x20, \
+}
+
+static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
+ DMAE_CHANNEL(0x8000, 0),
+ DMAE_CHANNEL(0x8080, 1),
+ DMAE_CHANNEL(0x8100, 2),
+ DMAE_CHANNEL(0x8180, 3),
+ DMAE_CHANNEL(0x8200, 4),
+ DMAE_CHANNEL(0x8280, 5),
+ DMAE_CHANNEL(0x8300, 6),
+ DMAE_CHANNEL(0x8380, 7),
+ DMAE_CHANNEL(0x8400, 8),
+ DMAE_CHANNEL(0x8480, 9),
+ DMAE_CHANNEL(0x8500, 10),
+ DMAE_CHANNEL(0x8580, 11),
+ DMAE_CHANNEL(0x8600, 12),
+};
+
+static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
+ .slave = r8a7790_audio_dmac_slaves,
+ .slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
+ .channel = r8a7790_audio_dmac_channels,
+ .channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
+ .ts_low_shift = TS_LOW_SHIFT,
+ .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
+ .ts_high_shift = TS_HI_SHIFT,
+ .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
+ .ts_shift = dma_ts_shift,
+ .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
+ .dmaor_init = DMAOR_DME,
+ .chclr_present = 1,
+ .chclr_bitwise = 1,
+};
+
+static struct resource r8a7790_audio_dmac_resources[] = {
+ /* Channel registers and DMAOR for low */
+ DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
+ DEFINE_RES_IRQ(gic_spi(346)),
+ DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
+
+ /* Channel registers and DMAOR for hi */
+ DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
+ DEFINE_RES_IRQ(gic_spi(347)),
+ DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
+};
+
+#define r8a7790_register_audio_dmac(id) \
+ platform_device_register_resndata( \
+ &platform_bus, "sh-dma-engine", id, \
+ &r8a7790_audio_dmac_resources[id * 3], 3, \
+ &r8a7790_audio_dmac_platform_data, \
+ sizeof(r8a7790_audio_dmac_platform_data))
+
static const struct resource pfc_resources[] __initconst = {
DEFINE_RES_MEM(0xe6060000, 0x250),
};
@@ -101,6 +189,8 @@ void __init r8a7790_pinmux_init(void)
r8a7790_register_i2c(1);
r8a7790_register_i2c(2);
r8a7790_register_i2c(3);
+ r8a7790_register_audio_dmac(0);
+ r8a7790_register_audio_dmac(1);
}
#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
--
1.8.5.2
^ permalink raw reply related
* [GIT PULL 00/13] Renesas ARM Based SoC Updates for v3.15
From: Simon Horman @ 2014-02-06 6:21 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
please consider these Renesas ARM based SoC updates for v3.15.
This pull request is based on "Renesas CPG update for v3.15",
tagged as renesas-cpg-for-v3.15, which I am also sending a pull request for
today. The reason for the dependency is to provide driver support for
the "Wait for status on selected MSTP clocks" patches in this pull-request.
These are correctness fixes.
The following changes since commit a028c6da34d434e35ba8322568c756ea97ff3c18:
ARM: shmobile: wait for MSTP clock status to toggle, when enabling it (2014-02-04 10:22:39 +0900)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-for-v3.15
for you to fetch changes up to 012a7069b5a10a0851584d71a1facdc40a972319:
ARM: shmobile: r8a7790: Add PCI USB host clock support (2014-02-04 10:25:03 +0900)
----------------------------------------------------------------
Renesas ARM Based SoC Updates for v3.15
* r7s72100 SoC (RZ/A1H)
- Add i2c clocks (portion missing from previous patch due to miss-merge)
* r8a7791 (R-Car M2)
- Add SATA clocks
- Add ZS clock
- Wait for status on all MSTP clocks
-- Add I2C and VIN clocks
* r8a7790 (R-Car H2)
- Add PCI USB host clock support
- Add Audio DMAC, SATA and VIN clocks
- Add Audio DMAC support
* r8a7779 (R-Car H1)
- Wait for status on selected MSTP clocks
----------------------------------------------------------------
Kuninori Morimoto (2):
ARM: shmobile: r8a7790: add Audio DMAC clock
ARM: shmobile: r8a7790: add Audio DMAC support
Laurent Pinchart (1):
ARM: shmobile: r8a7779: Wait for status on selected MSTP clocks
Shinya Kuribayashi (2):
ARM: shmobile: r8a7790: Wait for status on all MSTP clocks
ARM: shmobile: r8a7791: Wait for status on all MSTP clocks
Valentine Barshak (7):
ARM: shmobile: r8a7791: Add I2C clocks
ARM: shmobile: r8a7791: Add VIN clocks
ARM: shmobile: r8a7790: Add VIN clock support
ARM: shmobile: r8a7790: Add SATA clocks
ARM: shmobile: r8a7791: Add ZS clock
ARM: shmobile: r8a7791: Add SATA clocks
ARM: shmobile: r8a7790: Add PCI USB host clock support
Wolfram Sang (1):
ARM: shmobile: r7s72100: really add i2c clocks
arch/arm/mach-shmobile/clock-r7s72100.c | 4 +
arch/arm/mach-shmobile/clock-r8a7779.c | 20 ++--
arch/arm/mach-shmobile/clock-r8a7790.c | 140 ++++++++++++++++----------
arch/arm/mach-shmobile/clock-r8a7791.c | 81 +++++++++++----
arch/arm/mach-shmobile/include/mach/r8a7790.h | 25 +++++
arch/arm/mach-shmobile/setup-r8a7790.c | 90 +++++++++++++++++
6 files changed, 275 insertions(+), 85 deletions(-)
^ permalink raw reply
* [PATCH 08/13] ARM: shmobile: r8a7790: Add VIN clock support
From: Simon Horman @ 2014-02-06 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391666228.git.horms+renesas@verge.net.au>
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
This adds VIN[0-3] clock support to R8A7790 SoC.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
[horms+renesas at verge.net.au: manually applied]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/clock-r8a7790.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 58f3dcf..b2b2323 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -197,6 +197,7 @@ enum {
MSTP931, MSTP930, MSTP929, MSTP928,
MSTP917,
MSTP813,
+ MSTP811, MSTP810, MSTP809, MSTP808,
MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
MSTP717, MSTP716,
MSTP704,
@@ -226,6 +227,10 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
+ [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
+ [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
+ [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
+ [MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 8, MSTPSR8, 0), /* VIN3 */
[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
@@ -312,6 +317,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
+ CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
+ CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
+ CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
+ CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
--
1.8.5.2
^ permalink raw reply related
* [PATCH 09/13] ARM: shmobile: r8a7790: Add SATA clocks
From: Simon Horman @ 2014-02-06 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391666228.git.horms+renesas@verge.net.au>
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
This adds SATA[01] clock support to R8A7790 SoC.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
[horms+renesas at verge.net.au: resolved trivial conflicts]
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/clock-r8a7790.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index b2b2323..f25b43a 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -196,6 +196,7 @@ enum {
MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
MSTP931, MSTP930, MSTP929, MSTP928,
MSTP917,
+ MSTP815, MSTP814,
MSTP813,
MSTP811, MSTP810, MSTP809, MSTP808,
MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
@@ -226,6 +227,8 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
+ [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
+ [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
@@ -340,6 +343,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
+ CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
+ CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
/* ICK */
CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
--
1.8.5.2
^ permalink raw reply related
* [PATCH 10/13] ARM: shmobile: r8a7791: Add ZS clock
From: Simon Horman @ 2014-02-06 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391666228.git.horms+renesas@verge.net.au>
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
This adds fixed ratio zs_clk to R8A7791 clocks.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/clock-r8a7791.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index 1074ba4..52d7d13 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -113,6 +113,7 @@ SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
+SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
static struct clk *main_clks[] = {
&extal_clk,
@@ -128,6 +129,7 @@ static struct clk *main_clks[] = {
&cp_clk,
&zg_clk,
&zx_clk,
+ &zs_clk,
};
/* MSTP */
@@ -187,6 +189,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
CLKDEV_CON_ID("pll3", &pll3_clk),
CLKDEV_CON_ID("zg", &zg_clk),
+ CLKDEV_CON_ID("zs", &zs_clk),
CLKDEV_CON_ID("hp", &hp_clk),
CLKDEV_CON_ID("p", &p_clk),
CLKDEV_CON_ID("rclk", &rclk_clk),
--
1.8.5.2
^ permalink raw reply related
* [PATCH 11/13] ARM: shmobile: r8a7791: Add SATA clocks
From: Simon Horman @ 2014-02-06 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391666228.git.horms+renesas@verge.net.au>
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
This adds SATA[01] clock support to R8A7791 SoC.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/clock-r8a7791.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index 52d7d13..e4e4dfa 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -135,6 +135,7 @@ static struct clk *main_clks[] = {
/* MSTP */
enum {
MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
+ MSTP815, MSTP814,
MSTP813,
MSTP811, MSTP810, MSTP809,
MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
@@ -153,6 +154,8 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
[MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
[MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
+ [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
+ [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
@@ -229,6 +232,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("r8a7791-vin.0", &mstp_clks[MSTP811]),
CLKDEV_DEV_ID("r8a7791-vin.1", &mstp_clks[MSTP810]),
CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),
+ CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
+ CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
};
#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
--
1.8.5.2
^ permalink raw reply related
* [PATCH 12/13] ARM: shmobile: r7s72100: really add i2c clocks
From: Simon Horman @ 2014-02-06 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391666228.git.horms+renesas@verge.net.au>
From: Wolfram Sang <wsa@sang-engineering.com>
Due to a merge conflict, addition of the clocks was lost. Tested with
RIIC2 on a genmai board. Others untested but hopefully trivial enough to
be added.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
[horms+renesas at verge.net.au: Capitalised "ARM" in subject]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/clock-r7s72100.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index e6ab0cd..dd8ce87 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -176,6 +176,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
/* MSTP clocks */
+ CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
+ CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
+ CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
+ CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),
CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
/* ICK */
--
1.8.5.2
^ permalink raw reply related
* [PATCH 13/13] ARM: shmobile: r8a7790: Add PCI USB host clock support
From: Simon Horman @ 2014-02-06 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391666228.git.horms+renesas@verge.net.au>
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
This adds internal PCI USB host clock support.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/clock-r8a7790.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index f25b43a..507073e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -201,7 +201,7 @@ enum {
MSTP811, MSTP810, MSTP809, MSTP808,
MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
MSTP717, MSTP716,
- MSTP704,
+ MSTP704, MSTP703,
MSTP522,
MSTP502, MSTP501,
MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
@@ -244,6 +244,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
[MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
[MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
+ [MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
[MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
[MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
@@ -343,6 +344,9 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
+ CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
+ CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
+ CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
--
1.8.5.2
^ permalink raw reply related
* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
From: Kishon Vijay Abraham I @ 2014-02-06 6:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140206061430.GA2394@pratyush-vbox>
Hi,
On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> Hi Kishon,
>
> On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
>>> skeleton support for the same.
>>>
>>> Currently phy ops are returning -EINVAL. They can be elaborated
>>> depending on the SOC being supported in future.
>>>
>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>> Cc: spear-devel at list.st.com
>>> Cc: linux-arm-kernel at lists.infradead.org
>>> Cc: devicetree at vger.kernel.org
>>> Cc: linux-kernel at vger.kernel.org
>>> ---
>>> .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
>>> drivers/phy/Kconfig | 6 +
>>> drivers/phy/Makefile | 1 +
>>> drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
>>> 4 files changed, 193 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> create mode 100644 drivers/phy/phy-miphy40lp.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> new file mode 100644
>>> index 0000000..d0c7096
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> @@ -0,0 +1,12 @@
>>> +Required properties:
>>> +- compatible : should be "st,miphy40lp-phy"
>>> + Other supported soc specific compatible:
>>> + "st,spear1310-miphy"
>>> + "st,spear1340-miphy"
>>> +- reg : offset and length of the PHY register set.
>>> +- misc: phandle for the syscon node to access misc registers
>>> +- phy-id: Instance id of the phy.
>>> +- #phy-cells : from the generic PHY bindings, must be 1.
>>> + - 1st cell: phandle to the phy node.
>>> + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
>>> + and 2 for Super Speed USB.
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index afa2354..2f58993 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
>>> help
>>> Enable this to support the Broadcom Kona USB 2.0 PHY.
>>>
>>> +config PHY_ST_MIPHY40LP
>>> + tristate "ST MIPHY 40LP driver"
>>> + help
>>> + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
>>> + select GENERIC_PHY
>>> +
>>> endmenu
>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>> index b57c253..c061091 100644
>>> --- a/drivers/phy/Makefile
>>> +++ b/drivers/phy/Makefile
>>> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
>>> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
>>> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
>>> obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
>>> +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> new file mode 100644
>>> index 0000000..d478c14
>>> --- /dev/null
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -0,0 +1,174 @@
>>> +/*
>>> + * ST MiPHY-40LP PHY driver
>>> + *
>>> + * Copyright (C) 2014 ST Microelectronics
>>> + * Pratyush Anand <pratyush.anand@st.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + */
>>> +
>>> +#include <linux/delay.h>
>>> +#include <linux/dma-mapping.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <linux/regmap.h>
>>> +
>>> +enum phy_mode {
>>> + SATA,
>>> + PCIE,
>>> + SS_USB,
>>> +};
>>> +
>>> +struct st_miphy40lp_priv {
>>> + /* regmap for any soc specific misc registers */
>>> + struct regmap *misc;
>>> + /* phy struct pointer */
>>> + struct phy *phy;
>>> + /* device node pointer */
>>> + struct device_node *np;
>>> + /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
>>> + enum phy_mode mode;
>>> + /* instance id of this phy */
>>> + u32 id;
>>> +};
>>> +
>>> +static int miphy40lp_init(struct phy *phy)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_exit(struct phy *phy)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_off(struct phy *phy)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_on(struct phy *phy)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static const struct of_device_id st_miphy40lp_of_match[] = {
>>> + { .compatible = "st,miphy40lp-phy" },
>>> + { },
>>> +};
>>> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
>>> +
>>> +static struct phy_ops st_miphy40lp_ops = {
>>> + .init = miphy40lp_init,
>>> + .exit = miphy40lp_exit,
>>> + .power_off = miphy40lp_power_off,
>>> + .power_on = miphy40lp_power_on,
>>> + .owner = THIS_MODULE,
>>
>> Would prefer to either align all the fields or align none. Here only owner is
>> aligned.
>
> ok.
>
>>> +};
>>> +
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int miphy40lp_suspend(struct device *dev)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_resume(struct device *dev)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +#endif
>>> +
>>> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
>>> + miphy40lp_resume);
>>> +
>>> +static struct phy *st_miphy40lp_xlate(struct device *dev,
>>> + struct of_phandle_args *args)
>>> +{
>>> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
>>> +
>>> + if (args->args_count < 1) {
>>> + dev_err(dev, "DT did not pass correct no of args\n");
>>> + return NULL;
>>> + }
>>> +
>>> + phypriv->mode = args->args[0];
>>> +
>>> + return phypriv->phy;
>>> +}
>>> +
>>> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
>>> +{
>>> + struct device *dev = &pdev->dev;
>>> + struct st_miphy40lp_priv *phypriv;
>>> + struct phy_provider *phy_provider;
>>> +
>>> + phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
>>> + if (!phypriv) {
>>> + dev_err(dev, "can't alloc miphy40lp private date memory\n");
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + phypriv->np = dev->of_node;
>>> +
>>> + phypriv->misc =
>>> + syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
>>> + if (IS_ERR(phypriv->misc)) {
>>> + dev_err(dev, "failed to find misc regmap\n");
>>> + return PTR_ERR(phypriv->misc);
>>> + }
>>> +
>>> + if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
>>> + dev_err(dev, "failed to find phy id\n");
>>> + return -EINVAL;
>>> + }
>> Do we really need this phy id? How is it being used?
>
> Yes , it is being used by patch 6/8.
Alright.
>
>>
>>> +
>>> + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
>>> + if (IS_ERR(phy_provider)) {
>>> + dev_err(dev, "failed to register phy provider\n");
>>> + return PTR_ERR(phy_provider);
>>> + }
>>
>> phy_provider_register should be the last step in registering the PHY. Or your
>> PHY call backs can be called before you create the PHY. Btw in your case you
>
> But every one else like phy-exynos-mipi-video or phy-omap-usb2 or any
> other did it same way. First phy_provider_register and then
> phy_create.
That's a bug which we figured out very late. Will get it fixed in this -rc cycle.
Thanks
Kishon
^ permalink raw reply
* [PATCH 02/03] pinctrl: sh-pfc: r8a7790: Break out USB0 OVC/VBUS
From: Simon Horman @ 2014-02-06 6:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANqRtoSubhvfgzn590k9oePLv04V00Z7aEuKw2Ofxi8FeCObbA@mail.gmail.com>
Hi Laurent,
On Fri, Jan 31, 2014 at 12:10:05PM +0900, Magnus Damm wrote:
> Hi Laurent,
>
> On Fri, Jan 31, 2014 at 10:17 AM, Laurent Pinchart
> <laurent.pinchart@ideasonboard.com> wrote:
> > Hi Magnus,
> >
> > Thank you for the patch.
> >
> > On Thursday 30 January 2014 08:10:19 Magnus Damm wrote:
> >> From: Magnus Damm <damm@opensource.se>
> >>
> >> Create a new group for the USB0 OVC/VBUS pin by itself. This
> >> allows us to monitor PWEN as GPIO on the Lager board.
> >>
> >> Signed-off-by: Magnus Damm <damm@opensource.se>
> >> ---
> >>
> >> drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 9 +++++++++
> >> 1 file changed, 9 insertions(+)
> >>
> >> --- 0001/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> >> +++ work/drivers/pinctrl/sh-pfc/pfc-r8a7790.c 2014-01-24
> > 10:23:32.000000000
> >> +0900 @@ -3231,6 +3231,13 @@ static const unsigned int usb0_pins[] =
> >> static const unsigned int usb0_mux[] = {
> >> USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
> >> };
> >> +static const unsigned int usb0_ovc_vbus_pins[] = {
> >> + /* OVC/VBUS */
> >> + RCAR_GP_PIN(5, 19),
> >> +};
> >> +static const unsigned int usb0_ovc_vbus_mux[] = {
> >> + USB0_OVC_VBUS_MARK,
> >> +};
> >
> > Another option would have been to split the existing usb0 group in usb0_pwen
> > and usb0_ovc. I'm not sure which is better though, I'd just like to know if
> > you had given it a thought.
>
> I actually did just that in my first local attempt, but I decided not
> to since it will only cause potential breakage.
>
> > Regardless, what about naming the new group usb0_ovc instead of usb0_ovc_bus
> > to keep names short ?
>
> Is there any particular reason why you want shorter names?
>
> >From my side, I prefer to keep the names in sync with the data sheet.
> In this particular case it is a shared pin so OVC is used for Host
> while VBUS is used for gadget, so if you're proposing to ditch VBUS
> then this feels somewhat inconsistent with the current gadget use
> case. =)
Hi Laurent,
I would like to move this patch forwards somehow.
If you are happy with it as-is could you consider merging it?
Otherwise, could you let me know what changes you would like made
so I can see about making it so?
Thanks
^ permalink raw reply
* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
From: Pratyush Anand @ 2014-02-06 6:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F32A58.1000904@ti.com>
On Thu, Feb 06, 2014 at 02:23:20PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> > Hi Kishon,
> >
> > On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
[...]
> >>> +
> >>> + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> >>> + if (IS_ERR(phy_provider)) {
> >>> + dev_err(dev, "failed to register phy provider\n");
> >>> + return PTR_ERR(phy_provider);
> >>> + }
> >>
> >> phy_provider_register should be the last step in registering the PHY. Or your
> >> PHY call backs can be called before you create the PHY. Btw in your case you
> >
> > But every one else like phy-exynos-mipi-video or phy-omap-usb2 or any
> > other did it same way. First phy_provider_register and then
> > phy_create.
>
> That's a bug which we figured out very late. Will get it fixed in this -rc cycle.
Ok..I ll correct in mine too. :)
Rgds
Pratyush
>
> Thanks
> Kishon
^ permalink raw reply
* [PATCH] ARM: shmobile: Use 64-bit dma_addr_t on r8a7790/r8a7791
From: Simon Horman @ 2014-02-06 6:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205053628.29078.92360.sendpatchset@w520>
On Wed, Feb 05, 2014 at 02:36:28PM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
>
> Some on-chip devices on r8a7790 and r8a7791 can do
> bus mastering and access more than 32-bits of address
> space. Select ARCH_DMA_ADDR_T_64BIT when LPAE is set
> in case of multiplatform and legacy SoC support.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
Thanks, I will queue this up.
^ permalink raw reply
* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
From: Kishon Vijay Abraham I @ 2014-02-06 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ab13bc3c8147974e58425604667737723c3aa3a6.1391661589.git.pratyush.anand@st.com>
Hi,
On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ahci driver needs some platform specific functions which are called at
> init, exit, suspend and resume conditions. Till now these functions were
> present in a platform driver with a fixme notes.
>
> Similar functions modifying same set of registers will also be needed in
> case of PCIe phy init/exit.
>
> So move all these SATA platform code to phy-miphy40lp driver.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree at vger.kernel.org
> Cc: linux-ide at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> ---
> .../devicetree/bindings/arm/spear-misc.txt | 4 +
> arch/arm/boot/dts/spear1310-evb.dts | 4 +
> arch/arm/boot/dts/spear1310.dtsi | 39 +++-
> arch/arm/boot/dts/spear1340-evb.dts | 4 +
> arch/arm/boot/dts/spear1340.dtsi | 13 +-
> arch/arm/boot/dts/spear13xx.dtsi | 5 +
> arch/arm/mach-spear/Kconfig | 2 +
> arch/arm/mach-spear/spear1340.c | 127 +------------
> drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
It would be better if you can split this patch. Keep arch/ in separate patch
and drivers/ in separate patch.
> 9 files changed, 266 insertions(+), 136 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>
.
.
<snip>
.
.
> static const char * const spear1340_dt_board_compat[] = {
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> index d478c14..cc7f45d 100644
> --- a/drivers/phy/phy-miphy40lp.c
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -8,6 +8,7 @@
> * it under the terms of the GNU General Public License version 2 as
> * published by the Free Software Foundation.
> *
> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> */
>
> #include <linux/delay.h>
> @@ -19,6 +20,60 @@
> #include <linux/phy/phy.h>
> #include <linux/regmap.h>
>
> +/* SPEAr1340 Registers */
> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG 0x100
> + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
> +#define SPEAR1340_PCM_WKUP_CFG 0x104
> +#define SPEAR1340_SWITCH_CTR 0x108
> +
> +#define SPEAR1340_PERIP1_SW_RST 0x318
> + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
> +#define SPEAR1340_PERIP2_SW_RST 0x31C
> +#define SPEAR1340_PERIP3_SW_RST 0x320
> +
> +/* PCIE - SATA configuration registers */
> +#define SPEAR1340_PCIE_SATA_CFG 0x424
> + /* PCIE CFG MASks */
> + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
use BIT() wherever possible.
> + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
> + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
> + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
> + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
> + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
> + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
> + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
> + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
> + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> + SPEAR1340_SATA_CFG_PM_CLK_EN | \
> + SPEAR1340_SATA_CFG_POWERUP_RESET | \
> + SPEAR1340_SATA_CFG_RX_CLK_EN | \
> + SPEAR1340_SATA_CFG_TX_CLK_EN)
> +
> +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
> + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
> + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> +
> enum phy_mode {
> SATA,
> PCIE,
> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> u32 id;
> };
>
> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
The function name format here differs from what you have already added. It will
be good to have consistent name in the file.
> +{
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> + /* Switch on sata power domain */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> + msleep(20);
> + /* Disable PCIE SATA Controller reset */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> + msleep(20);
> +
> + return 0;
> +}
> +
> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> +
> + /* Enable PCIE SATA Controller reset */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RST_SATA,
> + SPEAR1340_PERIP1_SW_RST_SATA);
> + msleep(20);
> + /* Switch off sata power domain */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> + msleep(20);
> +
> + return 0;
> +}
> +
> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
This compatible value is a bit confusing since it doesn't have 'sata' in it.
spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
> + return spear1340_sata_miphy_init(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_sata_miphy_exit(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return 0;
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return 0;
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_sata_miphy_exit(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_sata_miphy_init(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> static int miphy40lp_init(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_init(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_exit(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_exit(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_power_off(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_power_off(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_power_on(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_power_on(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static const struct of_device_id st_miphy40lp_of_match[] = {
> { .compatible = "st,miphy40lp-phy" },
> + { .compatible = "st,spear1340-miphy" },
> { },
> };
> MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
> #ifdef CONFIG_PM_SLEEP
> static int miphy40lp_suspend(struct device *dev)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> + if (dev->power.power_state.event == PM_EVENT_FREEZE)
> + return 0;
I'm not sure if you should be accessing it from the drivers. Will be good to
check with PM guys.
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_suspend(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_resume(struct device *dev)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> + if (dev->power.power_state.event == PM_EVENT_THAW)
> + return 0;
Same here.
Thanks
Kishon
^ permalink raw reply
* [PATCH 0/2] Add Ether's PHY IRQ support for Lager/Koelsh boards
From: Simon Horman @ 2014-02-06 6:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F268AA.6070808@cogentembedded.com>
On Wed, Feb 05, 2014 at 07:36:58PM +0300, Sergei Shtylyov wrote:
> Hello.
>
> On 02/05/2014 10:25 AM, Magnus Damm wrote:
>
> >> Here's the set of 2 patches against Simon Horman's 'renesas.git' repo,
> >>'renesas-devel-v3.14-rc1-20130204' tag. Here we add support for the Ether's PHY
> >>IRQ to the R8A7790/Lager and R8A7791/Koelsch boards.
>
> >>[1/2] ARM: shmobile: Lager: pass Ether PHY IRQ
> >>[1/2] ARM: shmobile: Koelsch: pass Ether PHY IRQ
>
> >Thanks, looking good!
>
> Not at all, you've already tested these patches, IIRC.
Thanks, I have queued these up with Magnus's ack which
he supplied the previous time that you posted them.
^ permalink raw reply
* [PATCH 0/2] sh_sci updates for v3.15
From: Simon Horman @ 2014-02-06 6:47 UTC (permalink / raw)
To: linux-arm-kernel
Hi Greg,
for the v3.14 release you asked me to handle merging sh_sci
updates through my renesas tree as there were circular dependencies between
sh_sci and Renesas SoC code.
While I am happy to keep doing this for v3.15 and beyond as the
motivation above no longer exists I assume that you would like
to go back to handling sh_sci patches through your tree.
If that is the case then please consider this series for v3.15.
It consists of two patches that were sitting in my tree but
didn't make the cut for v3.14 (the arm-soc window for that closed
over a month ago).
Otherwise I will queue them, and other sh_sci patches that have been
more recently posted by others, up in my renesas tree.
Laurent Pinchart (2):
serial: sh-sci: Restrict non-COMPILE_TEST compilation
serial: sh-sci: Fix compatible string in DT bindings example
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 +-
drivers/tty/serial/Kconfig | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
--
1.8.5.2
^ permalink raw reply
* [PATCH 1/2] serial: sh-sci: Restrict non-COMPILE_TEST compilation
From: Simon Horman @ 2014-02-06 6:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391669260-23970-1-git-send-email-horms+renesas@verge.net.au>
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Hardware supported by the driver is only found on SUPERH or
ARCH_SHMOBILE platforms. Restrict non-COMPILE_TEST compilation to them.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial at vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/tty/serial/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index a3815ea..923d3de 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -708,7 +708,8 @@ config SERIAL_IP22_ZILOG_CONSOLE
config SERIAL_SH_SCI
tristate "SuperH SCI(F) serial port support"
- depends on HAVE_CLK && (SUPERH || ARM || COMPILE_TEST)
+ depends on HAVE_CLK
+ depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
select SERIAL_CORE
config SERIAL_SH_SCI_NR_UARTS
--
1.8.5.2
^ permalink raw reply related
* [PATCH 2/2] serial: sh-sci: Fix compatible string in DT bindings example
From: Simon Horman @ 2014-02-06 6:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391669260-23970-1-git-send-email-horms+renesas@verge.net.au>
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Remove the -generic suffix from the compatible string in the serial port
DT bindings example.
Cc: devicetree at vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index f372cf2..53e6c17 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -37,7 +37,7 @@ Example:
};
scifa0: serial at e6c40000 {
- compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
+ compatible = "renesas,scifa-r8a7790", "renesas,scifa";
reg = <0 0xe6c40000 0 64>;
interrupt-parent = <&gic>;
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
--
1.8.5.2
^ permalink raw reply related
* [PATCH] backlight: add PWM dependencies
From: Jingoo Han @ 2014-02-06 6:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbB8LFM0Vu8VRo4niqxwxUdS-c5gmmWaxbUTbnLCLZbMA@mail.gmail.com>
On Wednesday, February 05, 2014 5:58 PM, Linus Walleij wrote:
> On Wed, Feb 5, 2014 at 6:01 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> > On Tuesday, February 04, 2014 9:57 PM, Linus Walleij wrote:
> >>
> >> In some compilations the LM3630A and LP855X backlight drivers
> >> fail like this:
> >>
> >> drivers/built-in.o: In function `lm3630a_pwm_ctrl':
> >> drivers/video/backlight/lm3630a_bl.c:168: undefined reference to `pwm_config'
> >> drivers/video/backlight/lm3630a_bl.c:172: undefined reference to `pwm_disable'
> >> drivers/video/backlight/lm3630a_bl.c:170: undefined reference to `pwm_enable'
> >> drivers/built-in.o: In function `lp855x_pwm_ctrl':
> >> drivers/video/backlight/lp855x_bl.c:249: undefined reference to `pwm_config'
> >> drivers/video/backlight/lp855x_bl.c:253: undefined reference to `pwm_disable'
> >> drivers/video/backlight/lp855x_bl.c:251: undefined reference to `pwm_enable'
> >>
> >> This is because both drivers depend on the PWM framework, so
> >> add this dependency to their Kconfig entries.
> >
> > However, even though, when CONFIG_PWM is not enabled, the problem
> > should not happen. pwm_config(),pwm_disable(), and pwm_enable()
> > are already defined for CONFIG_PWM=n case as below.
>
> So you may think but it does happen :-)
>
> I reproduced this with the defconfig for ARM pxa255-idp and enabling
> all boards for that platform, then enabling all available backlight drivers
> as compiled-in objects (y).
However, I cannot reproduce it with mainline kernel 3.14-rc1.
1. make pxa255-idp_defconfig
2. Enabling all boards
(System Type -> Intel PXA2xx/PXA3xx Implementations -> ...)
3. Enabling all available backlight drivers as compiled-in objects (y)
In this case, the LM3630A and LP855X backlight drivers are compiled
properly as below:
drivers/video/backlight/lm3630a_bl.o
drivers/video/backlight/lp855x_bl.o
Would you check it with mainline kernel 3.14-rc1?
If the errors happen, please attach the .config file.
Best regards,
Jingoo Han
>
> > ./include/linux/pwm.h
> > #if IS_ENABLED(CONFIG_PWM) || IS_ENABLED(CONFIG_HAVE_PWM)
> > .....
> > #else
>
> Hm PXA that I am using defines CONFIG_HAVE_PWM, but doesn't
> provide the required signatures (pwm_config/pwm_disable/pwm_enable).
>
> One of two things is wrong:
>
> - Either the PXA platform is breaking the CONFIG_HAVE_PWM
> contract by not providing pwm_config/pwm_disable/pwm_enable
> functions. Then HAVE_PWM should be removed from the PXA
> Kconfig selects.
>
> Or:
>
> - There is no such contract that these functions must exist if
> CONFIG_HAVE_PWM is defined, and the
> #if IS_ENABLED(CONFIG_HAVE_PWM)
> should be removed from <linux/pwm.h>
>
> Does anyone know which one it is?
>
> PWM subsystem maintainer? :-)
>
> Yours,
> Linus Walleij
^ permalink raw reply
* [PATCH 03/03] ARM: shmobile: Lager USB0 cable detection workaround
From: Simon Horman @ 2014-02-06 7:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140129231029.22655.58864.sendpatchset@w520>
On Thu, Jan 30, 2014 at 08:10:29AM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
>
> Add Lager board code to check the PWEN GPIO signal and refuse to
> allow probe of the USBHS driver in case of DIP misconfiguration.
>
> For correct operation Lager DIP switches SW5 and SW6 shall be
> configured in 2-3 position to enable USB Function support.
>
> If the DIP switch is configured incorrectly then the user can
> simply adjust the hardware and either reboot or use the bind interface
> to try to probe again:
>
> # echo renesas_usbhs > /sys/bus/platform/drivers/renesas_usbhs/bind
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
Thanks, I have queue this up.
^ permalink raw reply
* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
From: Pratyush Anand @ 2014-02-06 7:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F32C8A.5060100@ti.com>
On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ahci driver needs some platform specific functions which are called at
> > init, exit, suspend and resume conditions. Till now these functions were
> > present in a platform driver with a fixme notes.
> >
> > Similar functions modifying same set of registers will also be needed in
> > case of PCIe phy init/exit.
> >
> > So move all these SATA platform code to phy-miphy40lp driver.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Tested-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > Cc: Tejun Heo <tj@kernel.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: spear-devel at list.st.com
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: devicetree at vger.kernel.org
> > Cc: linux-ide at vger.kernel.org
> > Cc: linux-kernel at vger.kernel.org
> > ---
> > .../devicetree/bindings/arm/spear-misc.txt | 4 +
> > arch/arm/boot/dts/spear1310-evb.dts | 4 +
> > arch/arm/boot/dts/spear1310.dtsi | 39 +++-
> > arch/arm/boot/dts/spear1340-evb.dts | 4 +
> > arch/arm/boot/dts/spear1340.dtsi | 13 +-
> > arch/arm/boot/dts/spear13xx.dtsi | 5 +
> > arch/arm/mach-spear/Kconfig | 2 +
> > arch/arm/mach-spear/spear1340.c | 127 +------------
> > drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
>
> It would be better if you can split this patch. Keep arch/ in separate patch
> and drivers/ in separate patch.
Code is actually moving from arch to driver. Therefore I kept it in
same patch.
> > 9 files changed, 266 insertions(+), 136 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> >
> .
> .
> <snip>
> .
> .
> > static const char * const spear1340_dt_board_compat[] = {
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > index d478c14..cc7f45d 100644
> > --- a/drivers/phy/phy-miphy40lp.c
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -8,6 +8,7 @@
> > * it under the terms of the GNU General Public License version 2 as
> > * published by the Free Software Foundation.
> > *
> > + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> > */
> >
> > #include <linux/delay.h>
> > @@ -19,6 +20,60 @@
> > #include <linux/phy/phy.h>
> > #include <linux/regmap.h>
> >
> > +/* SPEAr1340 Registers */
> > +/* Power Management Registers */
> > +#define SPEAR1340_PCM_CFG 0x100
> > + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
> > +#define SPEAR1340_PCM_WKUP_CFG 0x104
> > +#define SPEAR1340_SWITCH_CTR 0x108
> > +
> > +#define SPEAR1340_PERIP1_SW_RST 0x318
> > + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
> > +#define SPEAR1340_PERIP2_SW_RST 0x31C
> > +#define SPEAR1340_PERIP3_SW_RST 0x320
> > +
> > +/* PCIE - SATA configuration registers */
> > +#define SPEAR1340_PCIE_SATA_CFG 0x424
> > + /* PCIE CFG MASks */
> > + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
>
> use BIT() wherever possible.
OK.
> > + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
> > + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
> > + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
> > + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
> > + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
> > + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
> > + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
> > + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> > + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> > + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
> > + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> > + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> > + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> > + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> > + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> > + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> > + SPEAR1340_SATA_CFG_PM_CLK_EN | \
> > + SPEAR1340_SATA_CFG_POWERUP_RESET | \
> > + SPEAR1340_SATA_CFG_RX_CLK_EN | \
> > + SPEAR1340_SATA_CFG_TX_CLK_EN)
> > +
> > +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
> > + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
> > + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
> > + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> > + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
> > + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> > + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
> > + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> > + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> > + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> > + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> > + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> > + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> > + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> > +
> > enum phy_mode {
> > SATA,
> > PCIE,
> > @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> > u32 id;
> > };
> >
> > +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>
> The function name format here differs from what you have already added. It will
> be good to have consistent name in the file.
You mean to pass "struct phy *phy" in all the internal functions too?
> > +{
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> > + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> > + /* Switch on sata power domain */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> > + msleep(20);
> > + /* Disable PCIE SATA Controller reset */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> > + msleep(20);
> > +
> > + return 0;
> > +}
> > +
> > +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> > +
> > + /* Enable PCIE SATA Controller reset */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > + SPEAR1340_PERIP1_SW_RST_SATA,
> > + SPEAR1340_PERIP1_SW_RST_SATA);
> > + msleep(20);
> > + /* Switch off sata power domain */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> > + msleep(20);
> > +
> > + return 0;
> > +}
> > +
> > +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
>
> This compatible value is a bit confusing since it doesn't have 'sata' in it.
> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
same spear1340 miphy is used for sata as well as for pcie. sata or
pcie mode is selected using mode args passed in phys.
> > + return spear1340_sata_miphy_init(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_sata_miphy_exit(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return 0;
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return 0;
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_sata_miphy_exit(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_sata_miphy_init(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > static int miphy40lp_init(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_init(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_exit(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_exit(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_power_off(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_power_off(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_power_on(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_power_on(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static const struct of_device_id st_miphy40lp_of_match[] = {
> > { .compatible = "st,miphy40lp-phy" },
> > + { .compatible = "st,spear1340-miphy" },
> > { },
> > };
> > MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
> > #ifdef CONFIG_PM_SLEEP
> > static int miphy40lp_suspend(struct device *dev)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > + if (dev->power.power_state.event == PM_EVENT_FREEZE)
> > + return 0;
>
> I'm not sure if you should be accessing it from the drivers. Will be good to
> check with PM guys.
+ linux-pm mailing list.
Rgds
Pratyush
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_suspend(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_resume(struct device *dev)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > + if (dev->power.power_state.event == PM_EVENT_THAW)
> > + return 0;
>
> Same here.
>
> Thanks
> Kishon
^ permalink raw reply
* [PATCH] ARM: shmobile: Break out R-Car SYSC PM code
From: Simon Horman @ 2014-02-06 7:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140115074308.8471.64824.sendpatchset@w520>
On Wed, Jan 15, 2014 at 04:43:08PM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
>
> Break out the R-Car SYSC power management code from
> the r8a7779 SoC code. With this new shared R-Car SYSC
> code base it is possible to hook in Generation 2 SoCs
> as well.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
Thanks, I have queued this up.
^ permalink raw reply
* [PATCH 00/04] ARM: shmobile: r8a7790 SYSC, SCU and CCI setup code
From: Simon Horman @ 2014-02-06 7:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140115122539.9437.63968.sendpatchset@w520>
On Wed, Jan 15, 2014 at 09:25:39PM +0900, Magnus Damm wrote:
> ARM: shmobile: r8a7790 SYSC, SCU and CCI setup code
>
> [PATCH 01/04] ARM: shmobile: r8a7790 SYSC setup code
> [PATCH 02/04] ARM: shmobile: r8a7790 CA7-SCU enablement
> [PATCH 03/04] ARM: shmobile: r8a7790 CA15-SCU enablement
Thanks, I have queued up the above three patches.
> [PATCH 04/04] ARM: shmobile: r8a7790 CCI configuration
This one seems not quite ready.
>
> Add r8a7790 specific SYSC, SCU and CCI setup code.
>
> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
> Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
> [damm at opensource.se: Converted to use broken out SYSC code]
> Signed-off-by: Magnus Damm <damm@opensource.se>
> ---
>
> Written against renesas.git tag renesas-devel-v3.13-rc8-20140115,
> also requires "[PATCH] ARM: shmobile: Break out R-Car SYSC PM code"
>
> arch/arm/mach-shmobile/Makefile | 1
> arch/arm/mach-shmobile/include/mach/r8a7790.h | 1
> arch/arm/mach-shmobile/pm-r8a7790.c | 45 +++++++++++++++++++++++++
> arch/arm/mach-shmobile/smp-r8a7790.c | 32 +++++++++++++++++
> 4 files changed, 79 insertions(+)
>
^ permalink raw reply
* [PATCH] backlight: add PWM dependencies
From: Jingoo Han @ 2014-02-06 7:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000101cf2307$97a3c770$c6eb5650$%han@samsung.com>
On Thursday, February 06, 2014 3:50 PM, Jingoo Han wrote:
> On Wednesday, February 05, 2014 5:58 PM, Linus Walleij wrote:
> > On Wed, Feb 5, 2014 at 6:01 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> > > On Tuesday, February 04, 2014 9:57 PM, Linus Walleij wrote:
> > >>
> > >> In some compilations the LM3630A and LP855X backlight drivers
> > >> fail like this:
> > >>
> > >> drivers/built-in.o: In function `lm3630a_pwm_ctrl':
> > >> drivers/video/backlight/lm3630a_bl.c:168: undefined reference to `pwm_config'
> > >> drivers/video/backlight/lm3630a_bl.c:172: undefined reference to `pwm_disable'
> > >> drivers/video/backlight/lm3630a_bl.c:170: undefined reference to `pwm_enable'
> > >> drivers/built-in.o: In function `lp855x_pwm_ctrl':
> > >> drivers/video/backlight/lp855x_bl.c:249: undefined reference to `pwm_config'
> > >> drivers/video/backlight/lp855x_bl.c:253: undefined reference to `pwm_disable'
> > >> drivers/video/backlight/lp855x_bl.c:251: undefined reference to `pwm_enable'
> > >>
> > >> This is because both drivers depend on the PWM framework, so
> > >> add this dependency to their Kconfig entries.
> > >
> > > However, even though, when CONFIG_PWM is not enabled, the problem
> > > should not happen. pwm_config(),pwm_disable(), and pwm_enable()
> > > are already defined for CONFIG_PWM=n case as below.
> >
> > So you may think but it does happen :-)
> >
> > I reproduced this with the defconfig for ARM pxa255-idp and enabling
> > all boards for that platform, then enabling all available backlight drivers
> > as compiled-in objects (y).
>
> However, I cannot reproduce it with mainline kernel 3.14-rc1.
>
> 1. make pxa255-idp_defconfig
> 2. Enabling all boards
> (System Type -> Intel PXA2xx/PXA3xx Implementations -> ...)
> 3. Enabling all available backlight drivers as compiled-in objects (y)
>
> In this case, the LM3630A and LP855X backlight drivers are compiled
> properly as below:
>
> drivers/video/backlight/lm3630a_bl.o
> drivers/video/backlight/lp855x_bl.o
>
> Would you check it with mainline kernel 3.14-rc1?
> If the errors happen, please attach the .config file.
(+cc Arnd Bergmann)
Oh, sorry. There was my mistake.
I tested this with linux-next tree.
With linux 3.14-rc1, it makes the problem as below.
drivers/built-in.o: In function `lm3630a_pwm_ctrl':
drivers/video/backlight/lm3630a_bl.c:168: undefined reference to `pwm_config'
drivers/video/backlight/lm3630a_bl.c:172: undefined reference to `pwm_disable'
drivers/video/backlight/lm3630a_bl.c:170: undefined reference to `pwm_enable'
drivers/built-in.o: In function `lp855x_pwm_ctrl':
drivers/video/backlight/lp855x_bl.c:249: undefined reference to `pwm_config'
drivers/video/backlight/lp855x_bl.c:253: undefined reference to `pwm_disable'
drivers/video/backlight/lp855x_bl.c:251: undefined reference to `pwm_enable'
>
> >
> > > ./include/linux/pwm.h
> > > #if IS_ENABLED(CONFIG_PWM) || IS_ENABLED(CONFIG_HAVE_PWM)
> > > .....
> > > #else
> >
> > Hm PXA that I am using defines CONFIG_HAVE_PWM, but doesn't
> > provide the required signatures (pwm_config/pwm_disable/pwm_enable).
> >
> > One of two things is wrong:
> >
> > - Either the PXA platform is breaking the CONFIG_HAVE_PWM
> > contract by not providing pwm_config/pwm_disable/pwm_enable
> > functions. Then HAVE_PWM should be removed from the PXA
> > Kconfig selects.
> >
> > Or:
> >
> > - There is no such contract that these functions must exist if
> > CONFIG_HAVE_PWM is defined, and the
> > #if IS_ENABLED(CONFIG_HAVE_PWM)
> > should be removed from <linux/pwm.h>
> >
> > Does anyone know which one it is?
> >
> > PWM subsystem maintainer? :-)
Thierry Reding,
Would you confirm this?
In the case of "CONFIG_HAVE_PWM=y && CONFIG_PWM=n", it makes
the problem.
The HAVE_PWM symbol is only for legacy platforms that provide
the PWM API without using the generic framework. PXA looks to
use the generic PWM framework. Then, how about removing
"select HAVE_PWM" from PXA as below?
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -7,7 +7,6 @@ comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
config MACH_PXA3XX_DT
bool "Support PXA3xx platforms from device tree"
select CPU_PXA300
- select HAVE_PWM
select POWER_SUPPLY
select PXA3xx
select USE_OF
@@ -23,12 +22,10 @@ config ARCH_LUBBOCK
config MACH_MAINSTONE
bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
- select HAVE_PWM
select PXA27x
config MACH_ZYLONITE
bool
- select HAVE_PWM
select PXA3xx
.....
Best regards,
Jingoo Han
^ permalink raw reply
* emmc on imx6 sabresd
From: Shawn Guo @ 2014-02-06 7:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140129100321.GA32101@frolo.macqel>
On Wed, Jan 29, 2014 at 11:03:21AM +0100, Philippe De Muyter wrote:
> Hi Shawn,
>
> I try to use the emmc on my sabresd board and on a similar custom board
> using 3.13, and I have just discovered by reading Internet that it was
> not supported up to some weeks ago. Is there a git tree somewhere that
> has a branch containing 3.13 or linux-next and all the fixes for emmc on
> sabresd ?
I think it will just work if you apply the patch [1] on top of
v3.14-rc1.
Shawn
[1] http://www.spinics.net/lists/linux-mmc/msg23039.html
^ permalink raw reply
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