* [PATCH v8 0/4] Add ethernet support for r7s72100
From: Simon Horman @ 2014-02-06 8:36 UTC (permalink / raw)
To: linux-arm-kernel
From: Simon Horman <horms@verge.net.au>
Hi,
this series integrates ethernet support to sh-pfc for the r7s72100 SoC
and Genmai board.
This series is based on renesas-devel-v3.14-rc1-20140204
but patches from topic/r7s72100-v3.14-rc1-20140206 are required
in order to boot the Genmai board.
There are no changes to these patches since v7,
however driver patches included in that series have
been dropped as they are present in v3.14-rc1.
Simon Horman (2):
ARM: shmobile: r7s72100: Add clock for r7s72100-ether
ARM: shmobile: genmai: Enable r7s72100-ether
arch/arm/mach-shmobile/board-genmai.c | 21 +++++++++++++++++++++
arch/arm/mach-shmobile/clock-r7s72100.c | 4 ++++
2 files changed, 25 insertions(+)
--
1.8.5.2
^ permalink raw reply
* [PATCH] backlight: add PWM dependencies
From: Linus Walleij @ 2014-02-06 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000001cf230c$60ec1ca0$22c455e0$%han@samsung.com>
On Thu, Feb 6, 2014 at 8:23 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> In the case of "CONFIG_HAVE_PWM=y && CONFIG_PWM=n", it makes
> the problem.
>
> The HAVE_PWM symbol is only for legacy platforms that provide
> the PWM API without using the generic framework. PXA looks to
> use the generic PWM framework. Then, how about removing
> "select HAVE_PWM" from PXA as below?
>
> --- a/arch/arm/mach-pxa/Kconfig
> +++ b/arch/arm/mach-pxa/Kconfig
> @@ -7,7 +7,6 @@ comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
> config MACH_PXA3XX_DT
> bool "Support PXA3xx platforms from device tree"
> select CPU_PXA300
> - select HAVE_PWM
> select POWER_SUPPLY
> select PXA3xx
> select USE_OF
> @@ -23,12 +22,10 @@ config ARCH_LUBBOCK
>
> config MACH_MAINSTONE
> bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
> - select HAVE_PWM
> select PXA27x
>
> config MACH_ZYLONITE
> bool
> - select HAVE_PWM
> select PXA3xx
Looks like the right solution to me.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 2/3] PCI: ARM: add support for virtual PCI host controller
From: Arnd Bergmann @ 2014-02-06 8:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205205319.GH25695@obsidianresearch.com>
On Wednesday 05 February 2014, Jason Gunthorpe wrote:
> On Wed, Feb 05, 2014 at 09:26:17PM +0100, Arnd Bergmann wrote:
> > > > What you get out of "of_pci_range_to_resource(&range, np, &pci->io)"
> > > > is not the resource you want to pass into pci_add_resource()
> > > > later.
>
> Right, of_pci_range_to_resource returns the CPU MMIO address. A big
> problem here is that struct resource is being re-used for bus
> physical, CPU MMIO, and Linux Driver addressing domains without any
> helpful tagging.
>
> typedef struct resource resource_bus;
> typedef struct resource resource_cpu;
>
> ?
I fear the resource management needs a bigger overhaul than than.
Most importantly, 'struct resource' is not connected to 'struct device'
at the moment, and it only deals with resource types that were around
15 years ago.
> > > Do I need to open-code the resource translation from phys -> logical?
> >
> > I think we should have some common infrastructure that lets you
> > get this right more easily.
>
> The offset stuff seems to be very confusing to people, removing it
> from the APIs and forcing drivers to talk about bus addresess, CPU
> addresses and internal Linux addresses seems a bit more plain?
Interesting idea. I'm not sure how Bjorn will like that
after he just did an overhaul of all users of the offset
API some time ago, but let's see what he thinks.
> What do you think about something like this:
>
> int of_pci_alloc_io(.. resources,
> struct of_pci_range *range,
> struct device_node *np)
> {
> struct resource bus_address, mmio_window, res;
>
> bus_address.start = range->pci_addr;
> bus_address.end = range->pci_addr + range->size - 1;
>
> mmio_window.start = range->cpu_addr;
> mmio_window.end = range->cpu_addr + range->size - 1;
>
> /* Input bus_address - addresses seen on the bus
> mmio_window - physical CPU address to create the bus
> addreses
> Output res - Address suitable for use in drivers
> This does the pci_ioremap_io too */
> pci_alloc_virtual_io_window(&bus_address, &mmio_window, &res);
>
> /* bus_address - addresses seen on the bus
> res - matching driver view for the bus addresses */
> pci_add_resource_bus(&resources, &bus_address, &res);
> }
>
> And a similar function for MMIO that just omits
> pci_alloc_virtual_io_window.
It certainly seems workable. OTOH if we just manage to do a
helper that scans the OF ranges, allocates the I/O window,
remaps it and calls the existing pci_add_resource_offset()
helper, PCI host drivers don't need to worry about the
io_offsets computation either and just need to pull out the
correct window locations if they need to set up the hardware
translation windows (which I'd hope we can often let the boot
loader take care of).
Arnd
^ permalink raw reply
* [PATCH 0/3] ARM: OMAP2+: AM43x: Enable in OMAP2PLUS and add ID for ES1.1
From: Lokesh Vutla @ 2014-02-06 8:26 UTC (permalink / raw)
To: linux-arm-kernel
This patch series enables AM43XX SOC in omap2plus_deconfig along with
updating clocksource and adding support for ES1.1.
With this series using omap2plus_defconfig alone boots on AM43XX.
Tested on: AM4372 EPOS EVM
Afzal Mohammed (1):
ARM: OMAP2+: AM43x: enable in default config
Lokesh Vutla (1):
ARM: OMAP2+: AM43x: Add ID for ES1.1
Rajendra Nayak (1):
ARM: OMAP2+: AM43x: Use gptimer as clocksource
arch/arm/configs/omap2plus_defconfig | 1 +
arch/arm/mach-omap2/board-generic.c | 2 +-
arch/arm/mach-omap2/id.c | 14 ++++++++++++--
arch/arm/mach-omap2/soc.h | 3 ++-
arch/arm/mach-omap2/timer.c | 3 ++-
5 files changed, 18 insertions(+), 5 deletions(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH 1/2] [media] v4l2: Add settings for Horizontal and Vertical MV Search Range
From: Prabhakar Lad @ 2014-02-06 8:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391507999-31437-2-git-send-email-amit.grover@samsung.com>
On Tue, Feb 4, 2014 at 3:29 PM, Amit Grover <amit.grover@samsung.com> wrote:
> Adding V4L2 controls for horizontal and vertical search range in pixels
> for motion estimation module in video encoder.
>
> Signed-off-by: Swami Nathan <swaminath.p@samsung.com>
> Signed-off-by: Amit Grover <amit.grover@samsung.com>
Acked-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Regards,
--Prabhakar Lad
> ---
> Documentation/DocBook/media/v4l/controls.xml | 20 ++++++++++++++++++++
> drivers/media/v4l2-core/v4l2-ctrls.c | 6 ++++++
> include/uapi/linux/v4l2-controls.h | 2 ++
> 3 files changed, 28 insertions(+)
>
> diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml
> index a5a3188..0e1770c 100644
> --- a/Documentation/DocBook/media/v4l/controls.xml
> +++ b/Documentation/DocBook/media/v4l/controls.xml
> @@ -2258,6 +2258,26 @@ Applicable to the MPEG1, MPEG2, MPEG4 encoders.</entry>
> VBV buffer control.</entry>
> </row>
>
> + <row><entry></entry></row>
> + <row id=""v4l2-mpeg-video-hor-search-range">
> + <entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE</constant> </entry>
> + <entry>integer</entry>
> + </row>
> + <row><entry spanname="descr">Horizontal search range defines maximum horizontal search area in pixels
> +to search and match for the present Macroblock (MB) in the reference picture. This V4L2 control macro is used to set
> +horizontal search range for motion estimation module in video encoder.</entry>
> + </row>
> +
> + <row><entry></entry></row>
> + <row id="v4l2-mpeg-video-vert-search-range">
> + <entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE</constant> </entry>
> + <entry>integer</entry>
> + </row>
> + <row><entry spanname="descr">Vertical search range defines maximum vertical search area in pixels
> +to search and match for the present Macroblock (MB) in the reference picture. This V4L2 control macro is used to set
> +vertical search range for motion estimation module in video encoder.</entry>
> + </row>
> +
> <row><entry></entry></row>
> <row>
> <entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE</constant> </entry>
> diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
> index 6ff002b..e9e12c4 100644
> --- a/drivers/media/v4l2-core/v4l2-ctrls.c
> +++ b/drivers/media/v4l2-core/v4l2-ctrls.c
> @@ -735,6 +735,8 @@ const char *v4l2_ctrl_get_name(u32 id)
> case V4L2_CID_MPEG_VIDEO_DEC_PTS: return "Video Decoder PTS";
> case V4L2_CID_MPEG_VIDEO_DEC_FRAME: return "Video Decoder Frame Count";
> case V4L2_CID_MPEG_VIDEO_VBV_DELAY: return "Initial Delay for VBV Control";
> + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE: return "Horizontal MV Search Range";
> + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE: return "Vertical MV Search Range";
> case V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER: return "Repeat Sequence Header";
>
> /* VPX controls */
> @@ -910,6 +912,10 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
> *min = 0;
> *max = *step = 1;
> break;
> + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE:
> + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE:
> + *type = V4L2_CTRL_TYPE_INTEGER;
> + break;
> case V4L2_CID_PAN_RESET:
> case V4L2_CID_TILT_RESET:
> case V4L2_CID_FLASH_STROBE:
> diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
> index 2cbe605..cda6fa0 100644
> --- a/include/uapi/linux/v4l2-controls.h
> +++ b/include/uapi/linux/v4l2-controls.h
> @@ -376,6 +376,8 @@ enum v4l2_mpeg_video_multi_slice_mode {
> #define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224)
> #define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_MPEG_BASE+225)
> #define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_MPEG_BASE+226)
> +#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE (V4L2_CID_MPEG_BASE+227)
> +#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228)
>
> #define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300)
> #define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301)
> --
> 1.7.9.5
>
^ permalink raw reply
* [PATCH v2] ARM: dts: imx6qdl-sabreauto: Add PFUZE100 support
From: Shawn Guo @ 2014-02-06 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390997715-25498-1-git-send-email-festevam@gmail.com>
On Wed, Jan 29, 2014 at 10:15:15AM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> mx6 sabreauto boards have Freescale PFUZE100 regulator, so add support for it.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v1:
> - Remove pingrp
>
> arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 113 +++++++++++++++++++++++++++++++
> 1 file changed, 113 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> index 10a00e4..772c5a1 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> @@ -63,6 +63,112 @@
> status = "okay";
> };
>
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + pmic: pfuze100 at 08 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1ab {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw1c_reg: sw1c {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw2_reg: sw2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3a_reg: sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3b_reg: sw3b {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw4_reg: sw4 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen1_reg: vgen1 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen2_reg: vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen3_reg: vgen3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> &iomuxc {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_hog>;
> @@ -111,6 +217,13 @@
> >;
> };
>
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
Put it in alphabetic order.
Shawn
> pinctrl_gpmi_nand: gpminandgrp {
> fsl,pins = <
> MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
> --
> 1.8.1.2
>
^ permalink raw reply
* [PATCH v2 2/2] ARM: dts: imx6sl-evk: Add audio support
From: Shawn Guo @ 2014-02-06 8:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390996695-25164-2-git-send-email-festevam@gmail.com>
On Wed, Jan 29, 2014 at 09:58:15AM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> imx6sl-evk has a wm8962 codec. Add support for it.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v1:
> - Remove pingrp
> - Use regulator at num mode
>
> arch/arm/boot/dts/imx6sl-evk.dts | 81 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 81 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
> index 4fc62e8..17db01a 100644
> --- a/arch/arm/boot/dts/imx6sl-evk.dts
> +++ b/arch/arm/boot/dts/imx6sl-evk.dts
> @@ -43,9 +43,47 @@
> gpio = <&gpio4 2 0>;
> enable-active-high;
> };
> +
> + reg_aud3v: regulator at 2 {
> + compatible = "regulator-fixed";
reg = <2>;
> + regulator-name = "wm8962-supply-3v15";
> + regulator-min-microvolt = <3150000>;
> + regulator-max-microvolt = <3150000>;
> + regulator-boot-on;
> + };
> +
> + reg_aud4v: regulator at 3 {
> + compatible = "regulator-fixed";
reg = <3>;
Shawn
> + regulator-name = "wm8962-supply-4v2";
> + regulator-min-microvolt = <4325000>;
> + regulator-max-microvolt = <4325000>;
> + regulator-boot-on;
> + };
> + };
> +
> + sound {
> + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
> + model = "wm8962-audio";
> + ssi-controller = <&ssi2>;
> + audio-codec = <&codec>;
> + audio-routing =
> + "Headphone Jack", "HPOUTL",
> + "Headphone Jack", "HPOUTR",
> + "Ext Spk", "SPKOUTL",
> + "Ext Spk", "SPKOUTR",
> + "AMIC", "MICBIAS",
> + "IN3R", "AMIC";
> + mux-int-port = <2>;
> + mux-ext-port = <3>;
> };
> };
>
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux3>;
> + status = "okay";
> +};
> +
> &i2c1 {
> clock-frequency = <100000>;
> pinctrl-names = "default";
> @@ -152,6 +190,27 @@
> };
> };
>
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + codec: wm8962 at 1a {
> + compatible = "wlf,wm8962";
> + reg = <0x1a>;
> + clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
> + DCVDD-supply = <&vgen3_reg>;
> + DBVDD-supply = <®_aud3v>;
> + AVDD-supply = <&vgen3_reg>;
> + CPVDD-supply = <&vgen3_reg>;
> + MICVDD-supply = <®_aud3v>;
> + PLLVDD-supply = <&vgen3_reg>;
> + SPKVDD1-supply = <®_aud4v>;
> + SPKVDD2-supply = <®_aud4v>;
> + };
> +};
> +
> &ecspi1 {
> fsl,spi-num-chipselects = <1>;
> cs-gpios = <&gpio4 11 0>;
> @@ -189,6 +248,16 @@
> MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
> MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
> MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
> + MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
> + >;
> + };
> +
> + pinctrl_audmux3: audmux3grp {
> + fsl,pins = <
> + MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
> + MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
> + MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
> + MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
> >;
> };
>
> @@ -199,6 +268,13 @@
> >;
> };
>
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
> + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> pinctrl_ecspi1: ecspi1grp {
> fsl,pins = <
> MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
> @@ -374,6 +450,11 @@
> status = "okay";
> };
>
> +&ssi2 {
> + fsl,mode = "i2s-slave";
> + status = "okay";
> +};
> +
> &uart1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_uart1>;
> --
> 1.8.1.2
>
^ permalink raw reply
* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
From: Pratyush Anand @ 2014-02-06 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F34155.8010900@ti.com>
On Thu, Feb 06, 2014 at 04:01:25PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> > On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ahci driver needs some platform specific functions which are called at
> >>> init, exit, suspend and resume conditions. Till now these functions were
> >>> present in a platform driver with a fixme notes.
> >>>
> >>> Similar functions modifying same set of registers will also be needed in
> >>> case of PCIe phy init/exit.
> >>>
> >>> So move all these SATA platform code to phy-miphy40lp driver.
> >>>
> >>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> >>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> >>> Cc: Viresh Kumar <viresh.linux@gmail.com>
> >>> Cc: Tejun Heo <tj@kernel.org>
> >>> Cc: Arnd Bergmann <arnd@arndb.de>
> >>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> >>> Cc: spear-devel at list.st.com
> >>> Cc: linux-arm-kernel at lists.infradead.org
> >>> Cc: devicetree at vger.kernel.org
> >>> Cc: linux-ide at vger.kernel.org
> >>> Cc: linux-kernel at vger.kernel.org
> >>> ---
> >>> .../devicetree/bindings/arm/spear-misc.txt | 4 +
> >>> arch/arm/boot/dts/spear1310-evb.dts | 4 +
> >>> arch/arm/boot/dts/spear1310.dtsi | 39 +++-
> >>> arch/arm/boot/dts/spear1340-evb.dts | 4 +
> >>> arch/arm/boot/dts/spear1340.dtsi | 13 +-
> >>> arch/arm/boot/dts/spear13xx.dtsi | 5 +
> >>> arch/arm/mach-spear/Kconfig | 2 +
> >>> arch/arm/mach-spear/spear1340.c | 127 +------------
> >>> drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
> >>
> >> It would be better if you can split this patch. Keep arch/ in separate patch
> >> and drivers/ in separate patch.
> >
> > Code is actually moving from arch to driver. Therefore I kept it in
> > same patch.
> >
> >>> 9 files changed, 266 insertions(+), 136 deletions(-)
> >>> create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> >>>
> >> .
> >> .
> >> <snip>
> >> .
> >> .
> >>> static const char * const spear1340_dt_board_compat[] = {
> >>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> >>> index d478c14..cc7f45d 100644
> >>> --- a/drivers/phy/phy-miphy40lp.c
> >>> +++ b/drivers/phy/phy-miphy40lp.c
> >>> @@ -8,6 +8,7 @@
> >>> * it under the terms of the GNU General Public License version 2 as
> >>> * published by the Free Software Foundation.
> >>> *
> >>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> >>> */
> >>>
> >>> #include <linux/delay.h>
> >>> @@ -19,6 +20,60 @@
> >>> #include <linux/phy/phy.h>
> >>> #include <linux/regmap.h>
> >>>
> >>> +/* SPEAr1340 Registers */
> >>> +/* Power Management Registers */
> >>> +#define SPEAR1340_PCM_CFG 0x100
> >>> + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
> >>> +#define SPEAR1340_PCM_WKUP_CFG 0x104
> >>> +#define SPEAR1340_SWITCH_CTR 0x108
> >>> +
> >>> +#define SPEAR1340_PERIP1_SW_RST 0x318
> >>> + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
> >>> +#define SPEAR1340_PERIP2_SW_RST 0x31C
> >>> +#define SPEAR1340_PERIP3_SW_RST 0x320
> >>> +
> >>> +/* PCIE - SATA configuration registers */
> >>> +#define SPEAR1340_PCIE_SATA_CFG 0x424
> >>> + /* PCIE CFG MASks */
> >>> + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
> >>
> >> use BIT() wherever possible.
> >
> > OK.
> >
> >>> + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
> >>> + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
> >>> + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
> >>> + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
> >>> + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
> >>> + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
> >>> + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
> >>> + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> >>> + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> >>> + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
> >>> + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> >>> + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> >>> + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> >>> + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> >>> + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> >>> + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> >>> + SPEAR1340_SATA_CFG_PM_CLK_EN | \
> >>> + SPEAR1340_SATA_CFG_POWERUP_RESET | \
> >>> + SPEAR1340_SATA_CFG_RX_CLK_EN | \
> >>> + SPEAR1340_SATA_CFG_TX_CLK_EN)
> >>> +
> >>> +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
> >>> + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
> >>> + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
> >>> + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> >>> + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
> >>> + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> >>> + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
> >>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> >>> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> >>> + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> >>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> >>> + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> >>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> >>> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> >>> +
> >>> enum phy_mode {
> >>> SATA,
> >>> PCIE,
> >>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> >>> u32 id;
> >>> };
> >>>
> >>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> >>
> >> The function name format here differs from what you have already added. It will
> >> be good to have consistent name in the file.
> >
> > You mean to pass "struct phy *phy" in all the internal functions too?
>
> No. I meant let all the function names begin with miphy40lp_.
okkk.. miphy40lp_spear1340_sata_init looks better :)
Rgds
Pratyush
^ permalink raw reply
* [PATCH v2 1/2] ARM: dts: imx6sl-evk: Add PFUZE100 support
From: Shawn Guo @ 2014-02-06 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390996695-25164-1-git-send-email-festevam@gmail.com>
On Wed, Jan 29, 2014 at 09:58:14AM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> imx6sl-evk board has Freescale PFUZE100 regulator, so add support for it.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v1:
> - Remove pingrp
>
> arch/arm/boot/dts/imx6sl-evk.dts | 113 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 113 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
> index 0001804..4fc62e8 100644
> --- a/arch/arm/boot/dts/imx6sl-evk.dts
> +++ b/arch/arm/boot/dts/imx6sl-evk.dts
> @@ -46,6 +46,112 @@
> };
> };
>
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pmic: pfuze100 at 08 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1ab {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw1c_reg: sw1c {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw2_reg: sw2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3a_reg: sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3b_reg: sw3b {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw4_reg: sw4 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen1_reg: vgen1 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen2_reg: vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen3_reg: vgen3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> &ecspi1 {
> fsl,spi-num-chipselects = <1>;
> cs-gpios = <&gpio4 11 0>;
> @@ -86,6 +192,13 @@
> >;
> };
>
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
> + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
> + >;
> + };
> +
Sort it alphabetically.
Shawn
> pinctrl_ecspi1: ecspi1grp {
> fsl,pins = <
> MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
> --
> 1.8.1.2
>
^ permalink raw reply
* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
From: Kishon Vijay Abraham I @ 2014-02-06 8:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140206070053.GC2394@pratyush-vbox>
Hi,
On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ahci driver needs some platform specific functions which are called at
>>> init, exit, suspend and resume conditions. Till now these functions were
>>> present in a platform driver with a fixme notes.
>>>
>>> Similar functions modifying same set of registers will also be needed in
>>> case of PCIe phy init/exit.
>>>
>>> So move all these SATA platform code to phy-miphy40lp driver.
>>>
>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>>> Cc: Viresh Kumar <viresh.linux@gmail.com>
>>> Cc: Tejun Heo <tj@kernel.org>
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>> Cc: spear-devel at list.st.com
>>> Cc: linux-arm-kernel at lists.infradead.org
>>> Cc: devicetree at vger.kernel.org
>>> Cc: linux-ide at vger.kernel.org
>>> Cc: linux-kernel at vger.kernel.org
>>> ---
>>> .../devicetree/bindings/arm/spear-misc.txt | 4 +
>>> arch/arm/boot/dts/spear1310-evb.dts | 4 +
>>> arch/arm/boot/dts/spear1310.dtsi | 39 +++-
>>> arch/arm/boot/dts/spear1340-evb.dts | 4 +
>>> arch/arm/boot/dts/spear1340.dtsi | 13 +-
>>> arch/arm/boot/dts/spear13xx.dtsi | 5 +
>>> arch/arm/mach-spear/Kconfig | 2 +
>>> arch/arm/mach-spear/spear1340.c | 127 +------------
>>> drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
>>
>> It would be better if you can split this patch. Keep arch/ in separate patch
>> and drivers/ in separate patch.
>
> Code is actually moving from arch to driver. Therefore I kept it in
> same patch.
>
>>> 9 files changed, 266 insertions(+), 136 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>>>
>> .
>> .
>> <snip>
>> .
>> .
>>> static const char * const spear1340_dt_board_compat[] = {
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> index d478c14..cc7f45d 100644
>>> --- a/drivers/phy/phy-miphy40lp.c
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -8,6 +8,7 @@
>>> * it under the terms of the GNU General Public License version 2 as
>>> * published by the Free Software Foundation.
>>> *
>>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
>>> */
>>>
>>> #include <linux/delay.h>
>>> @@ -19,6 +20,60 @@
>>> #include <linux/phy/phy.h>
>>> #include <linux/regmap.h>
>>>
>>> +/* SPEAr1340 Registers */
>>> +/* Power Management Registers */
>>> +#define SPEAR1340_PCM_CFG 0x100
>>> + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
>>> +#define SPEAR1340_PCM_WKUP_CFG 0x104
>>> +#define SPEAR1340_SWITCH_CTR 0x108
>>> +
>>> +#define SPEAR1340_PERIP1_SW_RST 0x318
>>> + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
>>> +#define SPEAR1340_PERIP2_SW_RST 0x31C
>>> +#define SPEAR1340_PERIP3_SW_RST 0x320
>>> +
>>> +/* PCIE - SATA configuration registers */
>>> +#define SPEAR1340_PCIE_SATA_CFG 0x424
>>> + /* PCIE CFG MASks */
>>> + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
>>
>> use BIT() wherever possible.
>
> OK.
>
>>> + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
>>> + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
>>> + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
>>> + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
>>> + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
>>> + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
>>> + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
>>> + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
>>> + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
>>> + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
>>> + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
>>> + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
>>> + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
>>> + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
>>> + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
>>> + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
>>> + SPEAR1340_SATA_CFG_PM_CLK_EN | \
>>> + SPEAR1340_SATA_CFG_POWERUP_RESET | \
>>> + SPEAR1340_SATA_CFG_RX_CLK_EN | \
>>> + SPEAR1340_SATA_CFG_TX_CLK_EN)
>>> +
>>> +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
>>> + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
>>> + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
>>> + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
>>> + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
>>> + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
>>> + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
>>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
>>> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
>>> + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
>>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
>>> + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
>>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
>>> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
>>> +
>>> enum phy_mode {
>>> SATA,
>>> PCIE,
>>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
>>> u32 id;
>>> };
>>>
>>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>
>> The function name format here differs from what you have already added. It will
>> be good to have consistent name in the file.
>
> You mean to pass "struct phy *phy" in all the internal functions too?
No. I meant let all the function names begin with miphy40lp_.
>
>>> +{
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
>>> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
>>> + /* Switch on sata power domain */
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
>>> + msleep(20);
>>> + /* Disable PCIE SATA Controller reset */
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> + SPEAR1340_PERIP1_SW_RST_SATA, 0);
>>> + msleep(20);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
>>> +
>>> + /* Enable PCIE SATA Controller reset */
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> + SPEAR1340_PERIP1_SW_RST_SATA,
>>> + SPEAR1340_PERIP1_SW_RST_SATA);
>>> + msleep(20);
>>> + /* Switch off sata power domain */
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
>>> + msleep(20);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
>>
>> This compatible value is a bit confusing since it doesn't have 'sata' in it.
>> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
>
> same spear1340 miphy is used for sata as well as for pcie. sata or
> pcie mode is selected using mode args passed in phys.
Alright. Got it while reading the next patch ;-)
Thanks
Kishon
^ permalink raw reply
* emmc on imx6 sabresd
From: Shawn Guo @ 2014-02-06 7:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140129100321.GA32101@frolo.macqel>
On Wed, Jan 29, 2014 at 11:03:21AM +0100, Philippe De Muyter wrote:
> Hi Shawn,
>
> I try to use the emmc on my sabresd board and on a similar custom board
> using 3.13, and I have just discovered by reading Internet that it was
> not supported up to some weeks ago. Is there a git tree somewhere that
> has a branch containing 3.13 or linux-next and all the fixes for emmc on
> sabresd ?
I think it will just work if you apply the patch [1] on top of
v3.14-rc1.
Shawn
[1] http://www.spinics.net/lists/linux-mmc/msg23039.html
^ permalink raw reply
* [PATCH] backlight: add PWM dependencies
From: Jingoo Han @ 2014-02-06 7:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000101cf2307$97a3c770$c6eb5650$%han@samsung.com>
On Thursday, February 06, 2014 3:50 PM, Jingoo Han wrote:
> On Wednesday, February 05, 2014 5:58 PM, Linus Walleij wrote:
> > On Wed, Feb 5, 2014 at 6:01 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> > > On Tuesday, February 04, 2014 9:57 PM, Linus Walleij wrote:
> > >>
> > >> In some compilations the LM3630A and LP855X backlight drivers
> > >> fail like this:
> > >>
> > >> drivers/built-in.o: In function `lm3630a_pwm_ctrl':
> > >> drivers/video/backlight/lm3630a_bl.c:168: undefined reference to `pwm_config'
> > >> drivers/video/backlight/lm3630a_bl.c:172: undefined reference to `pwm_disable'
> > >> drivers/video/backlight/lm3630a_bl.c:170: undefined reference to `pwm_enable'
> > >> drivers/built-in.o: In function `lp855x_pwm_ctrl':
> > >> drivers/video/backlight/lp855x_bl.c:249: undefined reference to `pwm_config'
> > >> drivers/video/backlight/lp855x_bl.c:253: undefined reference to `pwm_disable'
> > >> drivers/video/backlight/lp855x_bl.c:251: undefined reference to `pwm_enable'
> > >>
> > >> This is because both drivers depend on the PWM framework, so
> > >> add this dependency to their Kconfig entries.
> > >
> > > However, even though, when CONFIG_PWM is not enabled, the problem
> > > should not happen. pwm_config(),pwm_disable(), and pwm_enable()
> > > are already defined for CONFIG_PWM=n case as below.
> >
> > So you may think but it does happen :-)
> >
> > I reproduced this with the defconfig for ARM pxa255-idp and enabling
> > all boards for that platform, then enabling all available backlight drivers
> > as compiled-in objects (y).
>
> However, I cannot reproduce it with mainline kernel 3.14-rc1.
>
> 1. make pxa255-idp_defconfig
> 2. Enabling all boards
> (System Type -> Intel PXA2xx/PXA3xx Implementations -> ...)
> 3. Enabling all available backlight drivers as compiled-in objects (y)
>
> In this case, the LM3630A and LP855X backlight drivers are compiled
> properly as below:
>
> drivers/video/backlight/lm3630a_bl.o
> drivers/video/backlight/lp855x_bl.o
>
> Would you check it with mainline kernel 3.14-rc1?
> If the errors happen, please attach the .config file.
(+cc Arnd Bergmann)
Oh, sorry. There was my mistake.
I tested this with linux-next tree.
With linux 3.14-rc1, it makes the problem as below.
drivers/built-in.o: In function `lm3630a_pwm_ctrl':
drivers/video/backlight/lm3630a_bl.c:168: undefined reference to `pwm_config'
drivers/video/backlight/lm3630a_bl.c:172: undefined reference to `pwm_disable'
drivers/video/backlight/lm3630a_bl.c:170: undefined reference to `pwm_enable'
drivers/built-in.o: In function `lp855x_pwm_ctrl':
drivers/video/backlight/lp855x_bl.c:249: undefined reference to `pwm_config'
drivers/video/backlight/lp855x_bl.c:253: undefined reference to `pwm_disable'
drivers/video/backlight/lp855x_bl.c:251: undefined reference to `pwm_enable'
>
> >
> > > ./include/linux/pwm.h
> > > #if IS_ENABLED(CONFIG_PWM) || IS_ENABLED(CONFIG_HAVE_PWM)
> > > .....
> > > #else
> >
> > Hm PXA that I am using defines CONFIG_HAVE_PWM, but doesn't
> > provide the required signatures (pwm_config/pwm_disable/pwm_enable).
> >
> > One of two things is wrong:
> >
> > - Either the PXA platform is breaking the CONFIG_HAVE_PWM
> > contract by not providing pwm_config/pwm_disable/pwm_enable
> > functions. Then HAVE_PWM should be removed from the PXA
> > Kconfig selects.
> >
> > Or:
> >
> > - There is no such contract that these functions must exist if
> > CONFIG_HAVE_PWM is defined, and the
> > #if IS_ENABLED(CONFIG_HAVE_PWM)
> > should be removed from <linux/pwm.h>
> >
> > Does anyone know which one it is?
> >
> > PWM subsystem maintainer? :-)
Thierry Reding,
Would you confirm this?
In the case of "CONFIG_HAVE_PWM=y && CONFIG_PWM=n", it makes
the problem.
The HAVE_PWM symbol is only for legacy platforms that provide
the PWM API without using the generic framework. PXA looks to
use the generic PWM framework. Then, how about removing
"select HAVE_PWM" from PXA as below?
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -7,7 +7,6 @@ comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
config MACH_PXA3XX_DT
bool "Support PXA3xx platforms from device tree"
select CPU_PXA300
- select HAVE_PWM
select POWER_SUPPLY
select PXA3xx
select USE_OF
@@ -23,12 +22,10 @@ config ARCH_LUBBOCK
config MACH_MAINSTONE
bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
- select HAVE_PWM
select PXA27x
config MACH_ZYLONITE
bool
- select HAVE_PWM
select PXA3xx
.....
Best regards,
Jingoo Han
^ permalink raw reply
* [PATCH 00/04] ARM: shmobile: r8a7790 SYSC, SCU and CCI setup code
From: Simon Horman @ 2014-02-06 7:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140115122539.9437.63968.sendpatchset@w520>
On Wed, Jan 15, 2014 at 09:25:39PM +0900, Magnus Damm wrote:
> ARM: shmobile: r8a7790 SYSC, SCU and CCI setup code
>
> [PATCH 01/04] ARM: shmobile: r8a7790 SYSC setup code
> [PATCH 02/04] ARM: shmobile: r8a7790 CA7-SCU enablement
> [PATCH 03/04] ARM: shmobile: r8a7790 CA15-SCU enablement
Thanks, I have queued up the above three patches.
> [PATCH 04/04] ARM: shmobile: r8a7790 CCI configuration
This one seems not quite ready.
>
> Add r8a7790 specific SYSC, SCU and CCI setup code.
>
> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
> Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
> [damm at opensource.se: Converted to use broken out SYSC code]
> Signed-off-by: Magnus Damm <damm@opensource.se>
> ---
>
> Written against renesas.git tag renesas-devel-v3.13-rc8-20140115,
> also requires "[PATCH] ARM: shmobile: Break out R-Car SYSC PM code"
>
> arch/arm/mach-shmobile/Makefile | 1
> arch/arm/mach-shmobile/include/mach/r8a7790.h | 1
> arch/arm/mach-shmobile/pm-r8a7790.c | 45 +++++++++++++++++++++++++
> arch/arm/mach-shmobile/smp-r8a7790.c | 32 +++++++++++++++++
> 4 files changed, 79 insertions(+)
>
^ permalink raw reply
* [PATCH] ARM: shmobile: Break out R-Car SYSC PM code
From: Simon Horman @ 2014-02-06 7:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140115074308.8471.64824.sendpatchset@w520>
On Wed, Jan 15, 2014 at 04:43:08PM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
>
> Break out the R-Car SYSC power management code from
> the r8a7779 SoC code. With this new shared R-Car SYSC
> code base it is possible to hook in Generation 2 SoCs
> as well.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
Thanks, I have queued this up.
^ permalink raw reply
* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
From: Pratyush Anand @ 2014-02-06 7:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F32C8A.5060100@ti.com>
On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ahci driver needs some platform specific functions which are called at
> > init, exit, suspend and resume conditions. Till now these functions were
> > present in a platform driver with a fixme notes.
> >
> > Similar functions modifying same set of registers will also be needed in
> > case of PCIe phy init/exit.
> >
> > So move all these SATA platform code to phy-miphy40lp driver.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Tested-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > Cc: Tejun Heo <tj@kernel.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: spear-devel at list.st.com
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: devicetree at vger.kernel.org
> > Cc: linux-ide at vger.kernel.org
> > Cc: linux-kernel at vger.kernel.org
> > ---
> > .../devicetree/bindings/arm/spear-misc.txt | 4 +
> > arch/arm/boot/dts/spear1310-evb.dts | 4 +
> > arch/arm/boot/dts/spear1310.dtsi | 39 +++-
> > arch/arm/boot/dts/spear1340-evb.dts | 4 +
> > arch/arm/boot/dts/spear1340.dtsi | 13 +-
> > arch/arm/boot/dts/spear13xx.dtsi | 5 +
> > arch/arm/mach-spear/Kconfig | 2 +
> > arch/arm/mach-spear/spear1340.c | 127 +------------
> > drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
>
> It would be better if you can split this patch. Keep arch/ in separate patch
> and drivers/ in separate patch.
Code is actually moving from arch to driver. Therefore I kept it in
same patch.
> > 9 files changed, 266 insertions(+), 136 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> >
> .
> .
> <snip>
> .
> .
> > static const char * const spear1340_dt_board_compat[] = {
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > index d478c14..cc7f45d 100644
> > --- a/drivers/phy/phy-miphy40lp.c
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -8,6 +8,7 @@
> > * it under the terms of the GNU General Public License version 2 as
> > * published by the Free Software Foundation.
> > *
> > + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> > */
> >
> > #include <linux/delay.h>
> > @@ -19,6 +20,60 @@
> > #include <linux/phy/phy.h>
> > #include <linux/regmap.h>
> >
> > +/* SPEAr1340 Registers */
> > +/* Power Management Registers */
> > +#define SPEAR1340_PCM_CFG 0x100
> > + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
> > +#define SPEAR1340_PCM_WKUP_CFG 0x104
> > +#define SPEAR1340_SWITCH_CTR 0x108
> > +
> > +#define SPEAR1340_PERIP1_SW_RST 0x318
> > + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
> > +#define SPEAR1340_PERIP2_SW_RST 0x31C
> > +#define SPEAR1340_PERIP3_SW_RST 0x320
> > +
> > +/* PCIE - SATA configuration registers */
> > +#define SPEAR1340_PCIE_SATA_CFG 0x424
> > + /* PCIE CFG MASks */
> > + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
>
> use BIT() wherever possible.
OK.
> > + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
> > + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
> > + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
> > + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
> > + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
> > + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
> > + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
> > + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> > + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> > + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
> > + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> > + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> > + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> > + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> > + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> > + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> > + SPEAR1340_SATA_CFG_PM_CLK_EN | \
> > + SPEAR1340_SATA_CFG_POWERUP_RESET | \
> > + SPEAR1340_SATA_CFG_RX_CLK_EN | \
> > + SPEAR1340_SATA_CFG_TX_CLK_EN)
> > +
> > +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
> > + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
> > + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
> > + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> > + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
> > + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> > + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
> > + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> > + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> > + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> > + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> > + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> > + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> > + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> > +
> > enum phy_mode {
> > SATA,
> > PCIE,
> > @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> > u32 id;
> > };
> >
> > +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>
> The function name format here differs from what you have already added. It will
> be good to have consistent name in the file.
You mean to pass "struct phy *phy" in all the internal functions too?
> > +{
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> > + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> > + /* Switch on sata power domain */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> > + msleep(20);
> > + /* Disable PCIE SATA Controller reset */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> > + msleep(20);
> > +
> > + return 0;
> > +}
> > +
> > +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> > +
> > + /* Enable PCIE SATA Controller reset */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > + SPEAR1340_PERIP1_SW_RST_SATA,
> > + SPEAR1340_PERIP1_SW_RST_SATA);
> > + msleep(20);
> > + /* Switch off sata power domain */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> > + msleep(20);
> > +
> > + return 0;
> > +}
> > +
> > +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
>
> This compatible value is a bit confusing since it doesn't have 'sata' in it.
> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
same spear1340 miphy is used for sata as well as for pcie. sata or
pcie mode is selected using mode args passed in phys.
> > + return spear1340_sata_miphy_init(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_sata_miphy_exit(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return 0;
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return 0;
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_sata_miphy_exit(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_sata_miphy_init(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > static int miphy40lp_init(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_init(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_exit(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_exit(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_power_off(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_power_off(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_power_on(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_power_on(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static const struct of_device_id st_miphy40lp_of_match[] = {
> > { .compatible = "st,miphy40lp-phy" },
> > + { .compatible = "st,spear1340-miphy" },
> > { },
> > };
> > MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
> > #ifdef CONFIG_PM_SLEEP
> > static int miphy40lp_suspend(struct device *dev)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > + if (dev->power.power_state.event == PM_EVENT_FREEZE)
> > + return 0;
>
> I'm not sure if you should be accessing it from the drivers. Will be good to
> check with PM guys.
+ linux-pm mailing list.
Rgds
Pratyush
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_suspend(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_resume(struct device *dev)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > + if (dev->power.power_state.event == PM_EVENT_THAW)
> > + return 0;
>
> Same here.
>
> Thanks
> Kishon
^ permalink raw reply
* [PATCH 03/03] ARM: shmobile: Lager USB0 cable detection workaround
From: Simon Horman @ 2014-02-06 7:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140129231029.22655.58864.sendpatchset@w520>
On Thu, Jan 30, 2014 at 08:10:29AM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
>
> Add Lager board code to check the PWEN GPIO signal and refuse to
> allow probe of the USBHS driver in case of DIP misconfiguration.
>
> For correct operation Lager DIP switches SW5 and SW6 shall be
> configured in 2-3 position to enable USB Function support.
>
> If the DIP switch is configured incorrectly then the user can
> simply adjust the hardware and either reboot or use the bind interface
> to try to probe again:
>
> # echo renesas_usbhs > /sys/bus/platform/drivers/renesas_usbhs/bind
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
Thanks, I have queue this up.
^ permalink raw reply
* [PATCH] backlight: add PWM dependencies
From: Jingoo Han @ 2014-02-06 6:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbB8LFM0Vu8VRo4niqxwxUdS-c5gmmWaxbUTbnLCLZbMA@mail.gmail.com>
On Wednesday, February 05, 2014 5:58 PM, Linus Walleij wrote:
> On Wed, Feb 5, 2014 at 6:01 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> > On Tuesday, February 04, 2014 9:57 PM, Linus Walleij wrote:
> >>
> >> In some compilations the LM3630A and LP855X backlight drivers
> >> fail like this:
> >>
> >> drivers/built-in.o: In function `lm3630a_pwm_ctrl':
> >> drivers/video/backlight/lm3630a_bl.c:168: undefined reference to `pwm_config'
> >> drivers/video/backlight/lm3630a_bl.c:172: undefined reference to `pwm_disable'
> >> drivers/video/backlight/lm3630a_bl.c:170: undefined reference to `pwm_enable'
> >> drivers/built-in.o: In function `lp855x_pwm_ctrl':
> >> drivers/video/backlight/lp855x_bl.c:249: undefined reference to `pwm_config'
> >> drivers/video/backlight/lp855x_bl.c:253: undefined reference to `pwm_disable'
> >> drivers/video/backlight/lp855x_bl.c:251: undefined reference to `pwm_enable'
> >>
> >> This is because both drivers depend on the PWM framework, so
> >> add this dependency to their Kconfig entries.
> >
> > However, even though, when CONFIG_PWM is not enabled, the problem
> > should not happen. pwm_config(),pwm_disable(), and pwm_enable()
> > are already defined for CONFIG_PWM=n case as below.
>
> So you may think but it does happen :-)
>
> I reproduced this with the defconfig for ARM pxa255-idp and enabling
> all boards for that platform, then enabling all available backlight drivers
> as compiled-in objects (y).
However, I cannot reproduce it with mainline kernel 3.14-rc1.
1. make pxa255-idp_defconfig
2. Enabling all boards
(System Type -> Intel PXA2xx/PXA3xx Implementations -> ...)
3. Enabling all available backlight drivers as compiled-in objects (y)
In this case, the LM3630A and LP855X backlight drivers are compiled
properly as below:
drivers/video/backlight/lm3630a_bl.o
drivers/video/backlight/lp855x_bl.o
Would you check it with mainline kernel 3.14-rc1?
If the errors happen, please attach the .config file.
Best regards,
Jingoo Han
>
> > ./include/linux/pwm.h
> > #if IS_ENABLED(CONFIG_PWM) || IS_ENABLED(CONFIG_HAVE_PWM)
> > .....
> > #else
>
> Hm PXA that I am using defines CONFIG_HAVE_PWM, but doesn't
> provide the required signatures (pwm_config/pwm_disable/pwm_enable).
>
> One of two things is wrong:
>
> - Either the PXA platform is breaking the CONFIG_HAVE_PWM
> contract by not providing pwm_config/pwm_disable/pwm_enable
> functions. Then HAVE_PWM should be removed from the PXA
> Kconfig selects.
>
> Or:
>
> - There is no such contract that these functions must exist if
> CONFIG_HAVE_PWM is defined, and the
> #if IS_ENABLED(CONFIG_HAVE_PWM)
> should be removed from <linux/pwm.h>
>
> Does anyone know which one it is?
>
> PWM subsystem maintainer? :-)
>
> Yours,
> Linus Walleij
^ permalink raw reply
* [PATCH 2/2] serial: sh-sci: Fix compatible string in DT bindings example
From: Simon Horman @ 2014-02-06 6:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391669260-23970-1-git-send-email-horms+renesas@verge.net.au>
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Remove the -generic suffix from the compatible string in the serial port
DT bindings example.
Cc: devicetree at vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index f372cf2..53e6c17 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -37,7 +37,7 @@ Example:
};
scifa0: serial at e6c40000 {
- compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
+ compatible = "renesas,scifa-r8a7790", "renesas,scifa";
reg = <0 0xe6c40000 0 64>;
interrupt-parent = <&gic>;
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
--
1.8.5.2
^ permalink raw reply related
* [PATCH 1/2] serial: sh-sci: Restrict non-COMPILE_TEST compilation
From: Simon Horman @ 2014-02-06 6:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391669260-23970-1-git-send-email-horms+renesas@verge.net.au>
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Hardware supported by the driver is only found on SUPERH or
ARCH_SHMOBILE platforms. Restrict non-COMPILE_TEST compilation to them.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial at vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/tty/serial/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index a3815ea..923d3de 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -708,7 +708,8 @@ config SERIAL_IP22_ZILOG_CONSOLE
config SERIAL_SH_SCI
tristate "SuperH SCI(F) serial port support"
- depends on HAVE_CLK && (SUPERH || ARM || COMPILE_TEST)
+ depends on HAVE_CLK
+ depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
select SERIAL_CORE
config SERIAL_SH_SCI_NR_UARTS
--
1.8.5.2
^ permalink raw reply related
* [PATCH 0/2] sh_sci updates for v3.15
From: Simon Horman @ 2014-02-06 6:47 UTC (permalink / raw)
To: linux-arm-kernel
Hi Greg,
for the v3.14 release you asked me to handle merging sh_sci
updates through my renesas tree as there were circular dependencies between
sh_sci and Renesas SoC code.
While I am happy to keep doing this for v3.15 and beyond as the
motivation above no longer exists I assume that you would like
to go back to handling sh_sci patches through your tree.
If that is the case then please consider this series for v3.15.
It consists of two patches that were sitting in my tree but
didn't make the cut for v3.14 (the arm-soc window for that closed
over a month ago).
Otherwise I will queue them, and other sh_sci patches that have been
more recently posted by others, up in my renesas tree.
Laurent Pinchart (2):
serial: sh-sci: Restrict non-COMPILE_TEST compilation
serial: sh-sci: Fix compatible string in DT bindings example
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 +-
drivers/tty/serial/Kconfig | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
--
1.8.5.2
^ permalink raw reply
* [PATCH 0/2] Add Ether's PHY IRQ support for Lager/Koelsh boards
From: Simon Horman @ 2014-02-06 6:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F268AA.6070808@cogentembedded.com>
On Wed, Feb 05, 2014 at 07:36:58PM +0300, Sergei Shtylyov wrote:
> Hello.
>
> On 02/05/2014 10:25 AM, Magnus Damm wrote:
>
> >> Here's the set of 2 patches against Simon Horman's 'renesas.git' repo,
> >>'renesas-devel-v3.14-rc1-20130204' tag. Here we add support for the Ether's PHY
> >>IRQ to the R8A7790/Lager and R8A7791/Koelsch boards.
>
> >>[1/2] ARM: shmobile: Lager: pass Ether PHY IRQ
> >>[1/2] ARM: shmobile: Koelsch: pass Ether PHY IRQ
>
> >Thanks, looking good!
>
> Not at all, you've already tested these patches, IIRC.
Thanks, I have queued these up with Magnus's ack which
he supplied the previous time that you posted them.
^ permalink raw reply
* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
From: Kishon Vijay Abraham I @ 2014-02-06 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ab13bc3c8147974e58425604667737723c3aa3a6.1391661589.git.pratyush.anand@st.com>
Hi,
On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ahci driver needs some platform specific functions which are called at
> init, exit, suspend and resume conditions. Till now these functions were
> present in a platform driver with a fixme notes.
>
> Similar functions modifying same set of registers will also be needed in
> case of PCIe phy init/exit.
>
> So move all these SATA platform code to phy-miphy40lp driver.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree at vger.kernel.org
> Cc: linux-ide at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> ---
> .../devicetree/bindings/arm/spear-misc.txt | 4 +
> arch/arm/boot/dts/spear1310-evb.dts | 4 +
> arch/arm/boot/dts/spear1310.dtsi | 39 +++-
> arch/arm/boot/dts/spear1340-evb.dts | 4 +
> arch/arm/boot/dts/spear1340.dtsi | 13 +-
> arch/arm/boot/dts/spear13xx.dtsi | 5 +
> arch/arm/mach-spear/Kconfig | 2 +
> arch/arm/mach-spear/spear1340.c | 127 +------------
> drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
It would be better if you can split this patch. Keep arch/ in separate patch
and drivers/ in separate patch.
> 9 files changed, 266 insertions(+), 136 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>
.
.
<snip>
.
.
> static const char * const spear1340_dt_board_compat[] = {
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> index d478c14..cc7f45d 100644
> --- a/drivers/phy/phy-miphy40lp.c
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -8,6 +8,7 @@
> * it under the terms of the GNU General Public License version 2 as
> * published by the Free Software Foundation.
> *
> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> */
>
> #include <linux/delay.h>
> @@ -19,6 +20,60 @@
> #include <linux/phy/phy.h>
> #include <linux/regmap.h>
>
> +/* SPEAr1340 Registers */
> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG 0x100
> + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
> +#define SPEAR1340_PCM_WKUP_CFG 0x104
> +#define SPEAR1340_SWITCH_CTR 0x108
> +
> +#define SPEAR1340_PERIP1_SW_RST 0x318
> + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
> +#define SPEAR1340_PERIP2_SW_RST 0x31C
> +#define SPEAR1340_PERIP3_SW_RST 0x320
> +
> +/* PCIE - SATA configuration registers */
> +#define SPEAR1340_PCIE_SATA_CFG 0x424
> + /* PCIE CFG MASks */
> + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
use BIT() wherever possible.
> + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
> + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
> + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
> + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
> + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
> + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
> + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
> + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
> + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> + SPEAR1340_SATA_CFG_PM_CLK_EN | \
> + SPEAR1340_SATA_CFG_POWERUP_RESET | \
> + SPEAR1340_SATA_CFG_RX_CLK_EN | \
> + SPEAR1340_SATA_CFG_TX_CLK_EN)
> +
> +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
> + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
> + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> +
> enum phy_mode {
> SATA,
> PCIE,
> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> u32 id;
> };
>
> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
The function name format here differs from what you have already added. It will
be good to have consistent name in the file.
> +{
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> + /* Switch on sata power domain */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> + msleep(20);
> + /* Disable PCIE SATA Controller reset */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> + msleep(20);
> +
> + return 0;
> +}
> +
> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> +
> + /* Enable PCIE SATA Controller reset */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RST_SATA,
> + SPEAR1340_PERIP1_SW_RST_SATA);
> + msleep(20);
> + /* Switch off sata power domain */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> + msleep(20);
> +
> + return 0;
> +}
> +
> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
This compatible value is a bit confusing since it doesn't have 'sata' in it.
spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
> + return spear1340_sata_miphy_init(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_sata_miphy_exit(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return 0;
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return 0;
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_sata_miphy_exit(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_sata_miphy_init(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> static int miphy40lp_init(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_init(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_exit(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_exit(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_power_off(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_power_off(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_power_on(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_power_on(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static const struct of_device_id st_miphy40lp_of_match[] = {
> { .compatible = "st,miphy40lp-phy" },
> + { .compatible = "st,spear1340-miphy" },
> { },
> };
> MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
> #ifdef CONFIG_PM_SLEEP
> static int miphy40lp_suspend(struct device *dev)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> + if (dev->power.power_state.event == PM_EVENT_FREEZE)
> + return 0;
I'm not sure if you should be accessing it from the drivers. Will be good to
check with PM guys.
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_suspend(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_resume(struct device *dev)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> + if (dev->power.power_state.event == PM_EVENT_THAW)
> + return 0;
Same here.
Thanks
Kishon
^ permalink raw reply
* [PATCH] ARM: shmobile: Use 64-bit dma_addr_t on r8a7790/r8a7791
From: Simon Horman @ 2014-02-06 6:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205053628.29078.92360.sendpatchset@w520>
On Wed, Feb 05, 2014 at 02:36:28PM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
>
> Some on-chip devices on r8a7790 and r8a7791 can do
> bus mastering and access more than 32-bits of address
> space. Select ARCH_DMA_ADDR_T_64BIT when LPAE is set
> in case of multiplatform and legacy SoC support.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
Thanks, I will queue this up.
^ permalink raw reply
* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
From: Pratyush Anand @ 2014-02-06 6:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F32A58.1000904@ti.com>
On Thu, Feb 06, 2014 at 02:23:20PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> > Hi Kishon,
> >
> > On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
[...]
> >>> +
> >>> + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> >>> + if (IS_ERR(phy_provider)) {
> >>> + dev_err(dev, "failed to register phy provider\n");
> >>> + return PTR_ERR(phy_provider);
> >>> + }
> >>
> >> phy_provider_register should be the last step in registering the PHY. Or your
> >> PHY call backs can be called before you create the PHY. Btw in your case you
> >
> > But every one else like phy-exynos-mipi-video or phy-omap-usb2 or any
> > other did it same way. First phy_provider_register and then
> > phy_create.
>
> That's a bug which we figured out very late. Will get it fixed in this -rc cycle.
Ok..I ll correct in mine too. :)
Rgds
Pratyush
>
> Thanks
> Kishon
^ permalink raw reply
* [PATCH 02/03] pinctrl: sh-pfc: r8a7790: Break out USB0 OVC/VBUS
From: Simon Horman @ 2014-02-06 6:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANqRtoSubhvfgzn590k9oePLv04V00Z7aEuKw2Ofxi8FeCObbA@mail.gmail.com>
Hi Laurent,
On Fri, Jan 31, 2014 at 12:10:05PM +0900, Magnus Damm wrote:
> Hi Laurent,
>
> On Fri, Jan 31, 2014 at 10:17 AM, Laurent Pinchart
> <laurent.pinchart@ideasonboard.com> wrote:
> > Hi Magnus,
> >
> > Thank you for the patch.
> >
> > On Thursday 30 January 2014 08:10:19 Magnus Damm wrote:
> >> From: Magnus Damm <damm@opensource.se>
> >>
> >> Create a new group for the USB0 OVC/VBUS pin by itself. This
> >> allows us to monitor PWEN as GPIO on the Lager board.
> >>
> >> Signed-off-by: Magnus Damm <damm@opensource.se>
> >> ---
> >>
> >> drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 9 +++++++++
> >> 1 file changed, 9 insertions(+)
> >>
> >> --- 0001/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> >> +++ work/drivers/pinctrl/sh-pfc/pfc-r8a7790.c 2014-01-24
> > 10:23:32.000000000
> >> +0900 @@ -3231,6 +3231,13 @@ static const unsigned int usb0_pins[] =
> >> static const unsigned int usb0_mux[] = {
> >> USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
> >> };
> >> +static const unsigned int usb0_ovc_vbus_pins[] = {
> >> + /* OVC/VBUS */
> >> + RCAR_GP_PIN(5, 19),
> >> +};
> >> +static const unsigned int usb0_ovc_vbus_mux[] = {
> >> + USB0_OVC_VBUS_MARK,
> >> +};
> >
> > Another option would have been to split the existing usb0 group in usb0_pwen
> > and usb0_ovc. I'm not sure which is better though, I'd just like to know if
> > you had given it a thought.
>
> I actually did just that in my first local attempt, but I decided not
> to since it will only cause potential breakage.
>
> > Regardless, what about naming the new group usb0_ovc instead of usb0_ovc_bus
> > to keep names short ?
>
> Is there any particular reason why you want shorter names?
>
> >From my side, I prefer to keep the names in sync with the data sheet.
> In this particular case it is a shared pin so OVC is used for Host
> while VBUS is used for gadget, so if you're proposing to ditch VBUS
> then this feels somewhat inconsistent with the current gadget use
> case. =)
Hi Laurent,
I would like to move this patch forwards somehow.
If you are happy with it as-is could you consider merging it?
Otherwise, could you let me know what changes you would like made
so I can see about making it so?
Thanks
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