* [PATCH] clk: at91: remove redundant assignment
From: Boris BREZILLON @ 2014-02-07 10:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F4AF3F.7040809@atmel.com>
Hi Nicolas, Colin,
On 07/02/2014 11:02, Nicolas Ferre wrote:
> On 06/02/2014 19:53, Colin King :
>> From: Colin Ian King <colin.king@canonical.com>
>>
>> remove the redundant shift = shift assignment, it is extraneous.
Thanks for reporting and fixing this.
>> Signed-off-by: Colin Ian King <colin.king@canonical.com>
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>
> Thanks.
>
> Boris, can you integrate this patch to the "fixes" series that will be
> sent to Mike during the 3.14 development cycle?
The round_rate function has been replaced by determine_rate and thus the
bug is not present anymore.
See JJ's series:
http://us.generation-nt.com/patch-v2-0-4-clk-at91-better-support-pcks-help-213900572.html
Best Regards,
Boris
> Bye,
>
>> ---
>> drivers/clk/at91/clk-programmable.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
>> index fd792b2..ff86efe 100644
>> --- a/drivers/clk/at91/clk-programmable.c
>> +++ b/drivers/clk/at91/clk-programmable.c
>> @@ -109,7 +109,7 @@ static long clk_programmable_round_rate(struct clk_hw *hw, unsigned long rate,
>> unsigned long best_diff;
>> unsigned long new_diff;
>> unsigned long cur_rate;
>> - int shift = shift;
>> + int shift;
>>
>> if (rate > *parent_rate)
>> return *parent_rate;
>>
>
^ permalink raw reply
* [PATCH v6 05/19] watchdog: orion: Make sure the watchdog is initially stopped
From: Ezequiel Garcia @ 2014-02-07 10:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F43ED0.4050808@roeck-us.net>
On Thu, Feb 06, 2014 at 06:02:56PM -0800, Guenter Roeck wrote:
> On 02/06/2014 09:20 AM, Ezequiel Garcia wrote:
> > Having the watchdog initially fully stopped is important to avoid
> > any spurious watchdog triggers, in case the registers are not in
> > its reset state.
> >
> > Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> > Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> > Tested-by: Willy Tarreau <w@1wt.eu>
> > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> > ---
> > drivers/watchdog/orion_wdt.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
> > index 6746033..2dbeee9 100644
> > --- a/drivers/watchdog/orion_wdt.c
> > +++ b/drivers/watchdog/orion_wdt.c
> > @@ -142,6 +142,9 @@ static int orion_wdt_probe(struct platform_device *pdev)
> > orion_wdt.max_timeout = wdt_max_duration;
> > watchdog_init_timeout(&orion_wdt, heartbeat, &pdev->dev);
> >
> > + /* Let's make sure the watchdog is fully stopped */
> > + orion_wdt_stop(&orion_wdt);
> > +
>
> Actually we just had that in another driver, and I stumbled over it there.
>
> Problem with stopping the watchdog in probe unconditionally is that you can
> use it to defeat nowayout: unload the module, then load it again,
> and the watchdog is stopped even if nowayout is true.
>
Hm... I see.
> Is this really what you want ? Or, in other words, what is the problem
> you are trying to solve ?
>
Well, this is related to the discussion about the bootloader not
reseting the watchdog properly, provoking spurious watchdog triggering.
Jason Gunthorpe explained [1] that we needed a particular sequence:
1. Disable WDT
2. Clear bridge
3. Enable WDT
We added the irq handling to satisfy (2), and the watchdog stop for (1).
The watchdog stop was agreed specifically [2].
Ideas?
[1] http://www.spinics.net/lists/arm-kernel/msg302340.html
[2] http://www.spinics.net/lists/arm-kernel/msg302507.html
--
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 14/15] charger: max14577: Configure battery-dependent settings from DTS
From: Lee Jones @ 2014-02-07 10:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391767487-10017-15-git-send-email-k.kozlowski@samsung.com>
> Remove hard-coded values for:
> - Fast Charge current,
> - End Of Charge current,
> - Fast Charge timer,
> - Overvoltage Protection Threshold,
> - Battery Constant Voltage,
> and use DTS to configure them. This allows using the max14577 charger
> driver with different batteries.
>
> Now the charger driver requires valid configuration data from DTS. In
> case of wrong configuration data it fails during probe. Patch adds
> of_compatible to the charger mfd cell in MFD driver core.
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
I already acked the MFD parts of this. Or has the patch changed?
> Cc: Kyungmin Park <kyungmin.park@samsung.com>
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Jenny Tc <jenny.tc@intel.com>
> ---
> drivers/mfd/max14577.c | 5 +-
> drivers/power/max14577_charger.c | 234 +++++++++++++++++++++++++++++-----
> include/linux/mfd/max14577-private.h | 10 ++
> include/linux/mfd/max14577.h | 8 ++
> 4 files changed, 227 insertions(+), 30 deletions(-)
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [RFC PATCH 08/15] ata: ahci_platform: Manage SATA PHY
From: Roger Quadros @ 2014-02-07 10:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <463926864.ALblgUKdgH@wuerfel>
On 02/07/2014 12:39 PM, Arnd Bergmann wrote:
> On Friday 07 February 2014 12:33:38 Roger Quadros wrote:
>>
>> This means we need to make CONFIG_SATA_AHCI_PLATFORM depend on CONFIG_GENERIC_PHY or
>> select it.
>>
>> OR
>>
>> Generic PHY layer must be fixed so that the API's are always built in.
>>
>> What is the better option? I believe making the PHY API's always built in is the better option.
>>
>
> CONFIG_SATA_AHCI_PLATFORM should do
>
> "depends on CONFIG_GENERIC_PHY || !CONFIG_GENERIC_PHY"
>
> which is the Kconfig way of saying that if CONFIG_GENERIC_PHY is a module,
> CONFIG_SATA_AHCI_PLATFORM needs to be a module as well.
>
Ah, that's neat. Thanks :).
cheers,
-roger
^ permalink raw reply
* [PATCH] ARM: imx6q: support ptp and rmii clock from pad
From: Philippe De Muyter @ 2014-02-07 10:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391666018-12825-1-git-send-email-shawn.guo@linaro.org>
Thanks, Shawn
your patch works perfectly. I can now use the same kernel on my sabresd
board (RGMII, enet_ref_clock generated by the imx6q) and my custom board
(RMII, clock generated by the PHY).
some comments. though :
the patch did not apply cleanly in clk-imx6q.c on v3.13
don't forget to complete Documentation/devicetree/bindings/
But, again, many thanks for the support
Philippe
On Thu, Feb 06, 2014 at 01:53:38PM +0800, Shawn Guo wrote:
> On imx6qdl, the ENET RMII and PTP clock can come from either internal
> ANATOP/CCM or external clock source through pad GPIO_16. But in case
> of the external clock source, bit IOMUXC_GPR1[21] needs to be cleared.
>
> The patch adds the support for systems that use an external clock source
> and distinguishes above two cases by checking if the PTP clock specified
> in device tree is the one coming from the internal ANATOP/CCM.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> arch/arm/mach-imx/clk-imx6q.c | 1 +
> arch/arm/mach-imx/mach-imx6q.c | 36 +++++++++++++++++++++++++++++++++++-
> 2 files changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index dd4f1e3..45de2e5 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -437,6 +437,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
>
> clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
> clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
> + clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
>
> if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
> cpu_is_imx6dl()) {
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index f9cbbf9..d131499b 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -182,16 +182,50 @@ static void __init imx6q_enet_phy_init(void)
>
> static void __init imx6q_1588_init(void)
> {
> + struct device_node *np;
> + struct clk *ptp_clk;
> + struct clk *enet_ref;
> struct regmap *gpr;
> + u32 clksel;
> +
> + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
> + if (!np) {
> + pr_warn("%s: failed to find fec node\n", __func__);
> + return;
> + }
> +
> + ptp_clk = of_clk_get(np, 2);
> + if (IS_ERR(ptp_clk)) {
> + pr_warn("%s: failed to get ptp clock\n", __func__);
> + goto put_node;
> + }
> +
> + enet_ref = clk_get_sys(NULL, "enet_ref");
> + if (IS_ERR(enet_ref)) {
> + pr_warn("%s: failed to get enet clock\n", __func__);
> + goto put_ptp_clk;
> + }
>
> + /*
> + * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
> + * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
> + * (external OSC), and we need to clear the bit.
> + */
> + clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
> + IMX6Q_GPR1_ENET_CLK_SEL_PAD;
> gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> if (!IS_ERR(gpr))
> regmap_update_bits(gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_ENET_CLK_SEL_MASK,
> - IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
> + clksel);
> else
> pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
>
> + clk_put(enet_ref);
> +put_ptp_clk:
> + clk_put(ptp_clk);
> +put_node:
> + of_node_put(np);
> }
>
> static void __init imx6q_init_machine(void)
> --
> 1.7.9.5
>
--
Philippe De Muyter +32 2 6101532 Macq SA rue de l'Aeronef 2 B-1140 Bruxelles
^ permalink raw reply
* [PATCH v2 14/15] charger: max14577: Configure battery-dependent settings from DTS
From: Krzysztof Kozlowski @ 2014-02-07 10:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140207104238.GH14727@lee--X1>
On Fri, 2014-02-07 at 10:42 +0000, Lee Jones wrote:
> > Remove hard-coded values for:
> > - Fast Charge current,
> > - End Of Charge current,
> > - Fast Charge timer,
> > - Overvoltage Protection Threshold,
> > - Battery Constant Voltage,
> > and use DTS to configure them. This allows using the max14577 charger
> > driver with different batteries.
> >
> > Now the charger driver requires valid configuration data from DTS. In
> > case of wrong configuration data it fails during probe. Patch adds
> > of_compatible to the charger mfd cell in MFD driver core.
> >
> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
> I already acked the MFD parts of this. Or has the patch changed?
Hi,
This patch is new in v2 so you haven't acked it yet. I need your ACK
here and in 13/15 (regulator/mfd: max14577: Export symbols for
calculating charger current).
Best regards,
Krzysztof
> > Cc: Kyungmin Park <kyungmin.park@samsung.com>
> > Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> > Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
> > Cc: David Woodhouse <dwmw2@infradead.org>
> > Cc: Jenny Tc <jenny.tc@intel.com>
> > ---
> > drivers/mfd/max14577.c | 5 +-
> > drivers/power/max14577_charger.c | 234 +++++++++++++++++++++++++++++-----
> > include/linux/mfd/max14577-private.h | 10 ++
> > include/linux/mfd/max14577.h | 8 ++
> > 4 files changed, 227 insertions(+), 30 deletions(-)
>
^ permalink raw reply
* [PATCH v2 08/15] mfd: max77836: Add max77836 support to max14577 driver
From: Lee Jones @ 2014-02-07 10:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391767487-10017-9-git-send-email-k.kozlowski@samsung.com>
On Fri, 07 Feb 2014, Krzysztof Kozlowski wrote:
> Add Maxim 77836 support to max14577 driver. The chipsets have same MUIC
> component so the extcon, charger and regulators are almost the same. The
> max77836 however has also PMIC and Fuel Gauge.
>
> The MAX77836 uses three I2C slave addresses and has additional interrupts
> (related to PMIC and Fuel Gauge). It has also Interrupt Source register,
> just like MAX77686 and MAX77693.
>
> The MAX77836 PMIC's TOPSYS and INTSRC interrupts are reported in the
> PMIC block. The PMIC block has different I2C slave address and uses own
> regmap so another regmap_irq_chip is needed.
>
> Since we have two regmap_irq_chip, use shared interrupts on MAX77836.
>
> This patch adds additional defines and functions to the max14577 MFD core
> driver so the driver will handle both chipsets. Also this patch replaces
> "0x1 << N" with BIT(N) in defines for register masks.
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
This should be a Mainatiner's Ack.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 08/15] mfd: max77836: Add max77836 support to max14577 driver
From: Lee Jones @ 2014-02-07 10:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391767487-10017-9-git-send-email-k.kozlowski@samsung.com>
> Add Maxim 77836 support to max14577 driver. The chipsets have same MUIC
> component so the extcon, charger and regulators are almost the same. The
> max77836 however has also PMIC and Fuel Gauge.
>
> The MAX77836 uses three I2C slave addresses and has additional interrupts
> (related to PMIC and Fuel Gauge). It has also Interrupt Source register,
> just like MAX77686 and MAX77693.
>
> The MAX77836 PMIC's TOPSYS and INTSRC interrupts are reported in the
> PMIC block. The PMIC block has different I2C slave address and uses own
> regmap so another regmap_irq_chip is needed.
>
> Since we have two regmap_irq_chip, use shared interrupts on MAX77836.
>
> This patch adds additional defines and functions to the max14577 MFD core
> driver so the driver will handle both chipsets. Also this patch replaces
> "0x1 << N" with BIT(N) in defines for register masks.
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
My Ack is missing from this patch too.
... and probably all the others? How will I know which ones I've
already Acked without reviewing them all again?
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* emmc on imx6 sabresd
From: Philippe De Muyter @ 2014-02-07 10:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140206075748.GC3708@S2101-09.ap.freescale.net>
Thanks Shawn,
On Thu, Feb 06, 2014 at 03:57:50PM +0800, Shawn Guo wrote:
> On Wed, Jan 29, 2014 at 11:03:21AM +0100, Philippe De Muyter wrote:
> > Hi Shawn,
> >
> > I try to use the emmc on my sabresd board and on a similar custom board
> > using 3.13, and I have just discovered by reading Internet that it was
> > not supported up to some weeks ago. Is there a git tree somewhere that
> > has a branch containing 3.13 or linux-next and all the fixes for emmc on
> > sabresd ?
>
> I think it will just work if you apply the patch [1] on top of
> v3.14-rc1.
>
> Shawn
>
> [1] http://www.spinics.net/lists/linux-mmc/msg23039.html
As I could not wait till then, I cloned the cjb's mmc tree, extracted the needed
patches using 'git format-patch', and applied them to my (then) v3.13-rc8 tree
using 'git am'. I can confirm that that works perfectly.
Philippe
--
Philippe De Muyter +32 2 6101532 Macq SA rue de l'Aeronef 2 B-1140 Bruxelles
^ permalink raw reply
* [PATCH v2 05/15] mfd: max14577: Add detection of device type
From: Lee Jones @ 2014-02-07 10:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391767487-10017-6-git-send-email-k.kozlowski@samsung.com>
> This patch continues the preparation for adding support for max77836
> device to existing max14577 driver.
>
> Add enum for types of devices supported by this driver. The device type
> will be detected by matching of_device_id, or i2c_device_id as a
> fallback.
>
> The patch also moves to separate function the code related to displaying
> DeviceID register values.
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: Kyungmin Park <kyungmin.park@samsung.com>
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/mfd/max14577.c | 64 ++++++++++++++++++++++++----------
> include/linux/mfd/max14577-private.h | 12 ++++---
> 2 files changed, 53 insertions(+), 23 deletions(-)
Acked-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 08/15] mfd: max77836: Add max77836 support to max14577 driver
From: Krzysztof Kozlowski @ 2014-02-07 10:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140207104912.GJ14727@lee--X1>
On Fri, 2014-02-07 at 10:49 +0000, Lee Jones wrote:
> > Add Maxim 77836 support to max14577 driver. The chipsets have same MUIC
> > component so the extcon, charger and regulators are almost the same. The
> > max77836 however has also PMIC and Fuel Gauge.
> >
> > The MAX77836 uses three I2C slave addresses and has additional interrupts
> > (related to PMIC and Fuel Gauge). It has also Interrupt Source register,
> > just like MAX77686 and MAX77693.
> >
> > The MAX77836 PMIC's TOPSYS and INTSRC interrupts are reported in the
> > PMIC block. The PMIC block has different I2C slave address and uses own
> > regmap so another regmap_irq_chip is needed.
> >
> > Since we have two regmap_irq_chip, use shared interrupts on MAX77836.
> >
> > This patch adds additional defines and functions to the max14577 MFD core
> > driver so the driver will handle both chipsets. Also this patch replaces
> > "0x1 << N" with BIT(N) in defines for register masks.
> >
> > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>
> My Ack is missing from this patch too.
>
> ... and probably all the others? How will I know which ones I've
> already Acked without reviewing them all again?
I already added your ACK-s to patches which got them. Unfortunately the
numbering of patches changed because 4 of them were applied and 1 was
dropped.
This particular patch (previously: 13/18) haven't got you ACK because
you've pointed some issues to fix.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v2 0/3] net: stmmac: Add STi GMAC ethernet
From: srinivas.kandagatla at st.com @ 2014-02-07 10:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391428787-27143-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Hi All,
This patch series adds Ethernet support to STi series SOCs STiH415 and STiH416.
STi SOC series integrates dwmac IP from synopsis, however there is a hardware
glue on top of this standard IP, this glue needs to configured before the
actual dwmac can be used. Also the glue logic needs re-configuring when the
link speed changes, This is because the clk source can change as the link
speed changes.
This patch just adds STi specific callbacks into of_data for configuring the
glue layer.
I have rebased my original patches (http://lkml.org/lkml/2013/11/12/243)
to latest stmmac which updates callbacks to suit glue drivers like this.
These patches are tested on b2000 and B2020 with STiH415 and STiH416.
Changes since v1:
- fixed multi-line function call format as suggested by David Miller.
Dave, Can I request you to take the first patch via net tree for v3.15, I can
request Arnd or Olof to take the DT patches via the arm-soc tree for v3.15.
Thanks,
srini
Srinivas Kandagatla (3):
net: stmmac:sti: Add STi SOC glue driver.
ARM: STi: Add STiH415 ethernet support.
ARM: STi: Add STiH416 ethernet support.
.../devicetree/bindings/net/sti-dwmac.txt | 58 ++++
arch/arm/boot/dts/stih415-clock.dtsi | 14 +
arch/arm/boot/dts/stih415-pinctrl.dtsi | 121 +++++++
arch/arm/boot/dts/stih415.dtsi | 48 +++
arch/arm/boot/dts/stih416-clock.dtsi | 14 +
arch/arm/boot/dts/stih416-pinctrl.dtsi | 109 +++++++
arch/arm/boot/dts/stih416.dtsi | 44 +++
arch/arm/boot/dts/stih41x-b2000.dtsi | 22 ++
arch/arm/boot/dts/stih41x-b2020.dtsi | 26 ++
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 331 ++++++++++++++++++++
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 3 +
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 +
14 files changed, 807 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
--
1.7.9.5
^ permalink raw reply
* [PATCH v2 1/3] net: stmmac:sti: Add STi SOC glue driver.
From: srinivas.kandagatla at st.com @ 2014-02-07 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391770455-24291-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
STi series SOCs have a glue layer on top of the synopsis gmac IP, this
glue layer needs to be configured before the gmac driver starts using
the IP.
This patch adds a support to this glue layer which is configured via
stmmac setup, init, exit callbacks.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/net/sti-dwmac.txt | 58 ++++
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 331 ++++++++++++++++++++
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 3 +
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 +
6 files changed, 409 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/sti-dwmac.txt
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
new file mode 100644
index 0000000..3dd3d0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
@@ -0,0 +1,58 @@
+STMicroelectronics SoC DWMAC glue layer controller
+
+The device node has following properties.
+
+Required properties:
+ - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
+ "st,stid127-dwmac".
+ - reg : Offset of the glue configuration register map in system
+ configuration regmap pointed by st,syscon property and size.
+
+ - reg-names : Should be "sti-ethconf".
+
+ - st,syscon : Should be phandle to system configuration node which
+ encompases this glue registers.
+
+ - st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
+ wired up in from different sources. One via TXCLK pin and other via CLK_125
+ pin. This wiring is totally board dependent. However the retiming glue
+ logic should be configured accordingly. Possible values for this property
+
+ "txclk" - if 125Mhz clock is wired up via txclk line.
+ "clk_125" - if 125Mhz clock is wired up via clk_125 line.
+
+ This property is only valid for Giga bit setup( GMII, RGMII), and it is
+ un-used for non-giga bit (MII and RMII) setups. Also note that internal
+ clockgen can not generate stable 125Mhz clock.
+
+ - st,ext-phyclk: This boolean property indicates who is generating the clock
+ for tx and rx. This property is only valid for RMII case where the clock can
+ be generated from the MAC or PHY.
+
+ - clock-names: should be "sti-ethclk".
+ - clocks: Should point to ethernet clockgen which can generate phyclk.
+
+
+Example:
+
+ethernet0: dwmac at fe810000 {
+ device_type = "network";
+ compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+ reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+ interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ phy-mode = "mii";
+
+ st,syscon = <&syscfg_rear>;
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ resets = <&softreset STIH416_ETH0_SOFTRESET>;
+ reset-names = "stmmaceth";
+ pinctrl-0 = <&pinctrl_mii0>;
+ pinctrl-names = "default";
+ clocks = <&CLK_S_GMAC0_PHY>;
+ clock-names = "stmmaceth";
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index e2f202e..f2d7c70 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -37,6 +37,17 @@ config DWMAC_SUNXI
stmmac device driver. This driver is used for A20/A31
GMAC ethernet controller.
+config DWMAC_STI
+ bool "STi GMAC support"
+ depends on STMMAC_PLATFORM && ARCH_STI
+ default y
+ ---help---
+ Support for ethernet controller on STi SOCs.
+
+ This selects STi SoC glue layer support for the stmmac
+ device driver. This driver is used on for the STi series
+ SOCs GMAC ethernet controller.
+
config STMMAC_PCI
bool "STMMAC PCI bus support"
depends on STMMAC_ETH && PCI
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index ecadece..dcef287 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_STMMAC_ETH) += stmmac.o
stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
+stmmac-$(CONFIG_DWMAC_STI) += dwmac-sti.o
stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
new file mode 100644
index 0000000..47113c2
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
@@ -0,0 +1,331 @@
+/**
+ * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
+ *
+ * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/stmmac.h>
+#include <linux/phy.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+
+/**
+ * STi GMAC glue logic.
+ * --------------------
+ *
+ * _
+ * | \
+ * --------|0 \ ETH_SEL_INTERNAL_NOTEXT_PHYCLK
+ * phyclk | |___________________________________________
+ * | | | (phyclk-in)
+ * --------|1 / |
+ * int-clk |_ / |
+ * | _
+ * | | \
+ * |_______|0 \ ETH_SEL_TX_RETIME_CLK
+ * | |___________________________
+ * | | (tx-retime-clk)
+ * _______|1 /
+ * | |_ /
+ * _ |
+ * | \ |
+ * --------|0 \ |
+ * clk_125 | |__|
+ * | | ETH_SEL_TXCLK_NOT_CLK125
+ * --------|1 /
+ * txclk |_ /
+ *
+ *
+ * ETH_SEL_INTERNAL_NOTEXT_PHYCLK is valid only for RMII where PHY can
+ * generate 50MHz clock or MAC can generate it.
+ * This bit is configured by "st,ext-phyclk" property.
+ *
+ * ETH_SEL_TXCLK_NOT_CLK125 is only valid for gigabit modes, where the 125Mhz
+ * clock either comes from clk-125 pin or txclk pin. This configuration is
+ * totally driven by the board wiring. This bit is configured by
+ * "st,tx-retime-src" property.
+ *
+ * TXCLK configuration is different for different phy interface modes
+ * and changes according to link speed in modes like RGMII.
+ *
+ * Below table summarizes the clock requirement and clock sources for
+ * supported phy interface modes with link speeds.
+ * ________________________________________________
+ *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link |
+ * ------------------------------------------------
+ *| MII | n/a | 25Mhz |
+ *| | | txclk |
+ * ------------------------------------------------
+ *| GMII | 125Mhz | 25Mhz |
+ *| | clk-125/txclk | txclk |
+ * ------------------------------------------------
+ *| RGMII | 125Mhz | 25Mhz |
+ *| | clk-125/txclk | clkgen |
+ * ------------------------------------------------
+ *| RMII | n/a | 25Mhz |
+ *| | |clkgen/phyclk-in |
+ * ------------------------------------------------
+ *
+ * TX lines are always retimed with a clk, which can vary depending
+ * on the board configuration. Below is the table of these bits
+ * in eth configuration register depending on source of retime clk.
+ *
+ *---------------------------------------------------------------
+ * src | tx_rt_clk | int_not_ext_phyclk | txclk_n_clk125|
+ *---------------------------------------------------------------
+ * txclk | 0 | n/a | 1 |
+ *---------------------------------------------------------------
+ * ck_125| 0 | n/a | 0 |
+ *---------------------------------------------------------------
+ * phyclk| 1 | 0 | n/a |
+ *---------------------------------------------------------------
+ * clkgen| 1 | 1 | n/a |
+ *---------------------------------------------------------------
+ */
+
+ /* Register definition */
+
+ /* 3 bits [8:6]
+ * [6:6] ETH_SEL_TXCLK_NOT_CLK125
+ * [7:7] ETH_SEL_INTERNAL_NOTEXT_PHYCLK
+ * [8:8] ETH_SEL_TX_RETIME_CLK
+ *
+ */
+
+#define TX_RETIME_SRC_MASK GENMASK(8, 6)
+#define ETH_SEL_TX_RETIME_CLK BIT(8)
+#define ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
+#define ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
+
+#define ENMII_MASK GENMASK(5, 5)
+#define ENMII BIT(5)
+
+/**
+ * 3 bits [4:2]
+ * 000-GMII/MII
+ * 001-RGMII
+ * 010-SGMII
+ * 100-RMII
+*/
+#define MII_PHY_SEL_MASK GENMASK(4, 2)
+#define ETH_PHY_SEL_RMII BIT(4)
+#define ETH_PHY_SEL_SGMII BIT(3)
+#define ETH_PHY_SEL_RGMII BIT(2)
+#define ETH_PHY_SEL_GMII 0x0
+#define ETH_PHY_SEL_MII 0x0
+
+#define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \
+ iface == PHY_INTERFACE_MODE_RGMII_ID || \
+ iface == PHY_INTERFACE_MODE_RGMII_RXID || \
+ iface == PHY_INTERFACE_MODE_RGMII_TXID)
+
+#define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \
+ iface == PHY_INTERFACE_MODE_GMII)
+
+struct sti_dwmac {
+ int interface;
+ bool ext_phyclk;
+ bool is_tx_retime_src_clk_125;
+ struct clk *clk;
+ int reg;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static u32 phy_intf_sels[] = {
+ [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
+ [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
+ [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
+ [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
+ [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
+};
+
+enum {
+ TX_RETIME_SRC_NA = 0,
+ TX_RETIME_SRC_TXCLK = 1,
+ TX_RETIME_SRC_CLK_125,
+ TX_RETIME_SRC_PHYCLK,
+ TX_RETIME_SRC_CLKGEN,
+};
+
+static const char * const tx_retime_srcs[] = {
+ [TX_RETIME_SRC_NA] = "",
+ [TX_RETIME_SRC_TXCLK] = "txclk",
+ [TX_RETIME_SRC_CLK_125] = "clk_125",
+ [TX_RETIME_SRC_PHYCLK] = "phyclk",
+ [TX_RETIME_SRC_CLKGEN] = "clkgen",
+};
+
+static u32 tx_retime_val[] = {
+ [TX_RETIME_SRC_TXCLK] = ETH_SEL_TXCLK_NOT_CLK125,
+ [TX_RETIME_SRC_CLK_125] = 0x0,
+ [TX_RETIME_SRC_PHYCLK] = ETH_SEL_TX_RETIME_CLK,
+ [TX_RETIME_SRC_CLKGEN] = ETH_SEL_TX_RETIME_CLK |
+ ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
+};
+
+static void setup_retime_src(struct sti_dwmac *dwmac, u32 spd)
+{
+ u32 src = 0, freq = 0;
+
+ if (spd == SPEED_100) {
+ if (dwmac->interface == PHY_INTERFACE_MODE_MII ||
+ dwmac->interface == PHY_INTERFACE_MODE_GMII) {
+ src = TX_RETIME_SRC_TXCLK;
+ } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) {
+ if (dwmac->ext_phyclk) {
+ src = TX_RETIME_SRC_PHYCLK;
+ } else {
+ src = TX_RETIME_SRC_CLKGEN;
+ freq = 50000000;
+ }
+
+ } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) {
+ src = TX_RETIME_SRC_CLKGEN;
+ freq = 25000000;
+ }
+
+ if (src == TX_RETIME_SRC_CLKGEN && dwmac->clk)
+ clk_set_rate(dwmac->clk, freq);
+
+ } else if (spd == SPEED_1000) {
+ if (dwmac->is_tx_retime_src_clk_125)
+ src = TX_RETIME_SRC_CLK_125;
+ else
+ src = TX_RETIME_SRC_TXCLK;
+ }
+
+ regmap_update_bits(dwmac->regmap, dwmac->reg,
+ TX_RETIME_SRC_MASK, tx_retime_val[src]);
+}
+
+static void sti_dwmac_exit(struct platform_device *pdev, void *priv)
+{
+ struct sti_dwmac *dwmac = priv;
+
+ if (dwmac->clk)
+ clk_disable_unprepare(dwmac->clk);
+}
+
+static void sti_fix_mac_speed(void *priv, unsigned int spd)
+{
+ struct sti_dwmac *dwmac = priv;
+ setup_retime_src(dwmac, spd);
+ return;
+}
+
+static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
+ struct platform_device *pdev)
+{
+ struct resource *res;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct regmap *regmap;
+ int err;
+
+ if (!np)
+ return -EINVAL;
+
+ res = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "sti-ethconf");
+ if (!res)
+ return -ENODATA;
+
+ regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ dwmac->dev = dev;
+ dwmac->interface = of_get_phy_mode(np);
+ dwmac->regmap = regmap;
+ dwmac->reg = res->start;
+ dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
+
+ dwmac->is_tx_retime_src_clk_125 = false;
+
+ if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) {
+ const char *rs;
+ err = of_property_read_string(np, "st,tx-retime-src", &rs);
+ if (err < 0) {
+ dev_err(dev, "st,tx-retime-src not specified\n");
+ return err;
+ }
+
+ if (!strcasecmp(rs, "clk_125"))
+ dwmac->is_tx_retime_src_clk_125 = true;
+
+ }
+
+ dwmac->clk = devm_clk_get(dev, "sti-ethclk");
+
+ if (IS_ERR(dwmac->clk))
+ dwmac->clk = NULL;
+
+ return 0;
+}
+
+static int sti_dwmac_init(struct platform_device *pdev, void *priv)
+{
+ struct sti_dwmac *dwmac = priv;
+ struct regmap *regmap = dwmac->regmap;
+ int iface = dwmac->interface;
+ u32 reg = dwmac->reg;
+ u32 val, spd;
+
+ if (dwmac->clk)
+ clk_prepare_enable(dwmac->clk);
+
+ regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK,
+ phy_intf_sels[iface]);
+
+ val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
+ regmap_update_bits(regmap, reg, ENMII_MASK, val);
+
+ if (IS_PHY_IF_MODE_GBIT(iface))
+ spd = SPEED_1000;
+ else
+ spd = SPEED_100;
+
+ setup_retime_src(dwmac, spd);
+
+ return 0;
+}
+
+static void *sti_dwmac_setup(struct platform_device *pdev)
+{
+ struct sti_dwmac *dwmac;
+ int ret;
+
+ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
+ if (!dwmac)
+ return ERR_PTR(-ENOMEM);
+
+ ret = sti_dwmac_parse_data(dwmac, pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Unable to parse OF data\n");
+ return ERR_PTR(ret);
+ }
+
+ return dwmac;
+}
+
+const struct stmmac_of_data sti_gmac_data = {
+ .fix_mac_speed = sti_fix_mac_speed,
+ .setup = sti_dwmac_setup,
+ .init = sti_dwmac_init,
+ .exit = sti_dwmac_exit,
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index d9af26e..f9e60d7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -133,6 +133,9 @@ bool stmmac_eee_init(struct stmmac_priv *priv);
#ifdef CONFIG_DWMAC_SUNXI
extern const struct stmmac_of_data sun7i_gmac_data;
#endif
+#ifdef CONFIG_DWMAC_STI
+extern const struct stmmac_of_data sti_gmac_data;
+#endif
extern struct platform_driver stmmac_pltfr_driver;
static inline int stmmac_register_platform(void)
{
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 5884a7d..c61bc72b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -33,6 +33,11 @@ static const struct of_device_id stmmac_dt_ids[] = {
#ifdef CONFIG_DWMAC_SUNXI
{ .compatible = "allwinner,sun7i-a20-gmac", .data = &sun7i_gmac_data},
#endif
+#ifdef CONFIG_DWMAC_STI
+ { .compatible = "st,stih415-dwmac", .data = &sti_gmac_data},
+ { .compatible = "st,stih416-dwmac", .data = &sti_gmac_data},
+ { .compatible = "st,stih127-dwmac", .data = &sti_gmac_data},
+#endif
/* SoC specific glue layers should come before generic bindings */
{ .compatible = "st,spear600-gmac"},
{ .compatible = "snps,dwmac-3.610"},
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 2/3] ARM: STi: Add STiH415 ethernet support.
From: srinivas.kandagatla at st.com @ 2014-02-07 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391770455-24291-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH415 SOC, which has two ethernet
snps,dwmac controllers version 3.610. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih415-clock.dtsi | 14 ++++
arch/arm/boot/dts/stih415-pinctrl.dtsi | 121 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 48 +++++++++++++
arch/arm/boot/dts/stih41x-b2000.dtsi | 22 ++++++
arch/arm/boot/dts/stih41x-b2020.dtsi | 26 +++++++
5 files changed, 231 insertions(+)
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 174c799..d047dbc 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -34,5 +34,19 @@
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
+
+ CLKS_GMAC0_PHY: clockgenA1 at 7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_GMAC0_PHY";
+ };
+
+ CLKS_ETH1_PHY: clockgenA0 at 7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLKS_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 887c5e5..9ca20aa 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -119,6 +119,56 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
+ };
+ };
+
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
};
pin-controller-front {
@@ -284,6 +334,77 @@
};
};
};
+
+ gmac0{
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
+
+ };
+ };
+
+ pinctrl_gmii0: gmii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
+
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+ txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+ rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
+
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
+
+
+ };
+ };
+ };
};
pin-controller-left {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d52207c..cc9b22b 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -147,5 +147,53 @@
status = "disabled";
};
+
+ ethernet0: dwmac at fe810000 {
+ device_type = "network";
+ compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+
+ reg = <0xfe810000 0x8000>, <0x148 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+
+ interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ reset-names = "stmmaceth";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+ snps,force_sf_dma_mode;
+
+ st,syscon = <&syscfg_rear>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_GMAC0_PHY>;
+ };
+
+ ethernet1: dwmac at fef08000 {
+ device_type = "network";
+ compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>, <0x74 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+ interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+ snps,force_sf_dma_mode;
+
+ st,syscon = <&syscfg_sbc>;
+
+ resets = <&softreset STIH415_ETH1_SOFTRESET>;
+ reset-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLKS_ETH1_PHY>;
+ };
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 1e6aa92..bf65c49 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -20,6 +20,8 @@
aliases {
ttyAS0 = &serial2;
+ ethernet0 = ðernet0;
+ ethernet1 = ðernet1;
};
soc {
@@ -46,5 +48,25 @@
status = "okay";
};
+
+ ethernet0: dwmac at fe810000 {
+ status = "okay";
+ phy-mode = "mii";
+ pinctrl-0 = <&pinctrl_mii0>;
+
+ snps,reset-gpio = <&PIO106 2>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
+
+ ethernet1: dwmac at fef08000 {
+ status = "disabled";
+ phy-mode = "mii";
+ st,tx-retime-src = "txclk";
+
+ snps,reset-gpio = <&PIO4 7>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 0ef0a69..6c9a2ab 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -19,6 +19,7 @@
aliases {
ttyAS0 = &sbc_serial1;
+ ethernet1 = ðernet1;
};
soc {
sbc_serial1: serial at fe531000 {
@@ -60,5 +61,30 @@
i2c at fe541000 {
status = "okay";
};
+
+ /**
+ * ethernet clk routing:
+ * for
+ * max-speed = <1000>;
+ * set
+ * st,tx-retime-src = "clk_125";
+ *
+ * for
+ * max-speed = <100>;
+ * set
+ * st,tx-retime-src = "clkgen";
+ */
+
+ ethernet1: dwmac at fef08000 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ max-speed = <1000>;
+ st,tx-retime-src = "clk_125";
+ snps,reset-gpio = <&PIO3 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 10000>;
+
+ pinctrl-0 = <&pinctrl_rgmii1>;
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH] i2c: mv64xxx: Fix locked bus when offload is selected but not used on a message
From: Gregory CLEMENT @ 2014-02-07 10:55 UTC (permalink / raw)
To: linux-arm-kernel
Offload can be used only on regular transactions and for 1 to byte
transfers. In the other cases we switch back to usual work flow.
In this case we need to call mv64xxx_i2c_prepare_for_io() as this
function is not used when we try to use offloading.
This commit adds this missing call when offloading have failed in the
MV64XXX_I2C_ACTION_OFFLOAD_SEND_START case.
This fix the timeout seen when the the i2c driver try to access an
address where the device is absent on the Armada XP bases board.
Cc: stable at vger.kernel.org # v3.12+
Fixes: 930ab3d403ae (i2c: mv64xxx: Add I2C Transaction Generator support)
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/i2c/busses/i2c-mv64xxx.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index b8c5187b9ee0..a1700c62d955 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -461,8 +461,15 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
case MV64XXX_I2C_ACTION_OFFLOAD_SEND_START:
if (!mv64xxx_i2c_offload_msg(drv_data))
break;
- else
+ else {
drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
+ /*
+ * Switch to the standard path, so we finally need to
+ * prepare the io that have not been done in
+ * mv64xxx_i2c_execute_msg
+ */
+ mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
+ }
/* FALLTHRU */
case MV64XXX_I2C_ACTION_SEND_START:
writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
--
1.8.1.2
^ permalink raw reply related
* [PATCH v2 3/3] ARM: STi: Add STiH416 ethernet support.
From: srinivas.kandagatla at st.com @ 2014-02-07 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391770455-24291-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416-clock.dtsi | 14 ++++
arch/arm/boot/dts/stih416-pinctrl.dtsi | 109 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih416.dtsi | 44 +++++++++++++
3 files changed, 167 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1..a6942c7 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
clock-frequency = <100000000>;
clock-output-names = "CLK_S_ICN_REG_0";
};
+
+ CLK_S_GMAC0_PHY: clockgenA1 at 7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_GMAC0_PHY";
+ };
+
+ CLK_S_ETH1_PHY: clockgenA0 at 7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "CLK_S_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 8863c38..c4beef2 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -132,6 +132,58 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&PIO0 7 ALT1 IN BYPASS 1000>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
+ };
+ };
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
+ txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
+ txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+ rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
+ rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
+ rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
+ rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
+
+ rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
+ rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
+
+ clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
};
pin-controller-front {
@@ -322,6 +374,63 @@
};
};
};
+
+ gmac0 {
+ pinctrl_mii0: mii0 {
+ st,pins {
+ mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
+ txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+ txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
+ col = <&PIO15 3 ALT2 IN BYPASS 1000>;
+ mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+ phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
+ };
+ };
+
+ pinctrl_gmii0: gmii0 {
+ st,pins {
+ };
+ };
+ pinctrl_rgmii0: rgmii0 {
+ st,pins {
+ phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
+ txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
+ txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
+ txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
+ txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
+ txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
+ txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+
+ mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
+ mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+ rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
+ rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
+ rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
+ rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
+ rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
+ rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+
+ clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
};
pin-controller-fvdp-fe {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 788ba5b..a96055b 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -156,5 +156,49 @@
status = "disabled";
};
+
+ ethernet0: dwmac at fe810000 {
+ device_type = "network";
+ compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+
+ interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ st,syscon = <&syscfg_rear>;
+ resets = <&softreset STIH416_ETH0_SOFTRESET>;
+ reset-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii0>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_GMAC0_PHY>;
+ };
+
+ ethernet1: dwmac at fef08000 {
+ device_type = "network";
+ compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+ status = "disabled";
+ reg = <0xfef08000 0x8000>, <0x7f0 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+ interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+
+ snps,pbl = <32>;
+ snps,mixed-burst;
+
+ st,syscon = <&syscfg_sbc>;
+
+ resets = <&softreset STIH416_ETH1_SOFTRESET>;
+ reset-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mii1>;
+ clock-names = "stmmaceth";
+ clocks = <&CLK_S_ETH1_PHY>;
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* mv64xxx: I2C bus locked when scanning absent devices on Armada XP
From: Gregory CLEMENT @ 2014-02-07 10:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F35DE3.8060503@free-electrons.com>
On 06/02/2014 11:03, Gregory CLEMENT wrote:
> Hi,
>
> I write this email mainly to let you know that there are some issues
> on i2c on the Armada XP (rev A0 and B0) based boards.
>
> What we observed was that if the i2c driver try to access an address
> where the device is absent, then the bus is locked. After the timeout
> the driver give up, but if we have a lot of i2c client registered,
> then the kernel spend a lot of time trying to scan all the
> addresses. It is noticeable when using the multiv7_defconfig where
> many i2c clients are registered, whereas with mvebu_defconfig we have
> fewer i2c clients, and most of them are present on the boards.
>
> Here is an extract of what you can see during a boot:
>
> [ 4.127648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 4.137338] rtc-s35390a 1-0030: rtc core: registered rtc-s35390a as rtc0
> [ 6.137649] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 8.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 10.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 12.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 14.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 16.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 18.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 20.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 22.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 24.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 26.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 28.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 30.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 32.137649] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 34.137648] i2c i2c-0: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 36.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 38.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 40.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 42.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 44.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 46.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 48.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 50.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 52.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 54.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 56.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 58.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 60.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 62.137648] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
> [ 62.144403] sdhci: Secure Digital Host Controller Interface driver
>
> Then the kernel continue to boot. and except this very annoying delay,
> everything else is working on i2c.
>
> If anyone have an idea of the cause of this issue, I would be glad to
> have any input.
>
> I continue to investigate it, and for the record v3.12 was not
> affected but v3.13 was. So now I am going to bisect.
Hi all,
I wanted to let you know that I have just found a fix for this issue.
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 1/2] ALSA: hda/ca0132 - setup/cleanup streams
From: Takashi Iwai @ 2014-02-07 10:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391744130-15043-1-git-send-email-hychao@chromium.org>
At Fri, 7 Feb 2014 11:35:29 +0800,
Hsin-Yu Chao wrote:
>
> When a HDMI stream is opened with the same stream tag
> as a following opened stream to ca0132, audio will be
> heard from two ports simultaneously.
> Fix this issue by change to use snd_hda_codec_setup_stream
> and snd_hda_codec_cleanup_stream instead, so that an
> inactive stream can be marked as 'dirty' when found
> with a conflict stream tag, and then get purified.
>
> Signed-off-by: Hsin-Yu Chao <hychao@chromium.org>
> Reviewed-by: Chih-Chung Chang <chihchung@chromium.org>
Thanks, applied this one.
Takashi
> ---
> sound/pci/hda/patch_ca0132.c | 68 ++++++--------------------------------------
> 1 file changed, 9 insertions(+), 59 deletions(-)
>
> diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c
> index 54d1479..59104dc 100644
> --- a/sound/pci/hda/patch_ca0132.c
> +++ b/sound/pci/hda/patch_ca0132.c
> @@ -2662,60 +2662,6 @@ static bool dspload_wait_loaded(struct hda_codec *codec)
> }
>
> /*
> - * PCM stuffs
> - */
> -static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
> - u32 stream_tag,
> - int channel_id, int format)
> -{
> - unsigned int oldval, newval;
> -
> - if (!nid)
> - return;
> -
> - snd_printdd(
> - "ca0132_setup_stream: NID=0x%x, stream=0x%x, "
> - "channel=%d, format=0x%x\n",
> - nid, stream_tag, channel_id, format);
> -
> - /* update the format-id if changed */
> - oldval = snd_hda_codec_read(codec, nid, 0,
> - AC_VERB_GET_STREAM_FORMAT,
> - 0);
> - if (oldval != format) {
> - msleep(20);
> - snd_hda_codec_write(codec, nid, 0,
> - AC_VERB_SET_STREAM_FORMAT,
> - format);
> - }
> -
> - oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
> - newval = (stream_tag << 4) | channel_id;
> - if (oldval != newval) {
> - snd_hda_codec_write(codec, nid, 0,
> - AC_VERB_SET_CHANNEL_STREAMID,
> - newval);
> - }
> -}
> -
> -static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
> -{
> - unsigned int val;
> -
> - if (!nid)
> - return;
> -
> - snd_printdd(KERN_INFO "ca0132_cleanup_stream: NID=0x%x\n", nid);
> -
> - val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
> - if (!val)
> - return;
> -
> - snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
> - snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
> -}
> -
> -/*
> * PCM callbacks
> */
> static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
> @@ -2726,7 +2672,9 @@ static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
> {
> struct ca0132_spec *spec = codec->spec;
>
> - ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
> + ca0132_toggle_dac_format(codec);
> +
> + snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
>
> return 0;
> }
> @@ -2745,7 +2693,7 @@ static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
> if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
> msleep(50);
>
> - ca0132_cleanup_stream(codec, spec->dacs[0]);
> + snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
>
> return 0;
> }
> @@ -2824,8 +2772,8 @@ static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
> {
> struct ca0132_spec *spec = codec->spec;
>
> - ca0132_setup_stream(codec, spec->adcs[substream->number],
> - stream_tag, 0, format);
> + snd_hda_codec_setup_stream(codec, spec->adcs[substream->number],
> + stream_tag, 0, format);
>
> return 0;
> }
> @@ -2839,7 +2787,7 @@ static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
> if (spec->dsp_state == DSP_DOWNLOADING)
> return 0;
>
> - ca0132_cleanup_stream(codec, hinfo->nid);
> + snd_hda_codec_cleanup_stream(codec, hinfo->nid);
> return 0;
> }
>
> @@ -4742,6 +4690,8 @@ static int patch_ca0132(struct hda_codec *codec)
> return err;
>
> codec->patch_ops = ca0132_patch_ops;
> + codec->pcm_format_first = 1;
> + codec->no_sticky_stream = 1;
>
> return 0;
> }
> --
> 1.9.0.rc1.175.g0b1dcb5
>
^ permalink raw reply
* [PATCH 1/2] PPC: powernv: remove redundant cpuidle_idle_call()
From: Preeti U Murthy @ 2014-02-07 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F4AB54.801@linux.vnet.ibm.com>
Hi Deepthi,
On 02/07/2014 03:15 PM, Deepthi Dharwar wrote:
> Hi Preeti,
>
> Thanks for the patch.
>
> On 02/07/2014 12:31 PM, Preeti U Murthy wrote:
>> Hi Nicolas,
>>
>> Find below the patch that will need to be squashed with this one.
>> This patch is based on the mainline.Adding Deepthi, the author of
>> the patch which introduced the powernv cpuidle driver. Deepthi,
>> do you think the below patch looks right? We do not need to do an
>> explicit local_irq_enable() since we are in the call path of
>> cpuidle driver and that explicitly enables irqs on exit from
>> idle states.
>
> Yes, We enable irqs explicitly while entering snooze loop and we always
> have interrupts enabled in the snooze state.
> For NAP state, we exit out of this state with interrupts enabled so we
> do not need an explicit enable of irqs.
>
>> On 02/07/2014 06:47 AM, Nicolas Pitre wrote:
>>> On Thu, 6 Feb 2014, Preeti U Murthy wrote:
>>>
>>>> Hi Daniel,
>>>>
>>>> On 02/06/2014 09:55 PM, Daniel Lezcano wrote:
>>>>> Hi Nico,
>>>>>
>>>>>
>>>>> On 6 February 2014 14:16, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>>>>>
>>>>>> The core idle loop now takes care of it.
>>>>>>
>>>>>> Signed-off-by: Nicolas Pitre <nico@linaro.org>
>>>>>> ---
>>>>>> arch/powerpc/platforms/powernv/setup.c | 13 +------------
>>>>>> 1 file changed, 1 insertion(+), 12 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/powerpc/platforms/powernv/setup.c
>>>>>> b/arch/powerpc/platforms/powernv/setup.c
>>>>>> index 21166f65c9..a932feb290 100644
>>>>>> --- a/arch/powerpc/platforms/powernv/setup.c
>>>>>> +++ b/arch/powerpc/platforms/powernv/setup.c
>>>>>> @@ -26,7 +26,6 @@
>>>>>> #include <linux/of_fdt.h>
>>>>>> #include <linux/interrupt.h>
>>>>>> #include <linux/bug.h>
>>>>>> -#include <linux/cpuidle.h>
>>>>>>
>>>>>> #include <asm/machdep.h>
>>>>>> #include <asm/firmware.h>
>>>>>> @@ -217,16 +216,6 @@ static int __init pnv_probe(void)
>>>>>> return 1;
>>>>>> }
>>>>>>
>>>>>> -void powernv_idle(void)
>>>>>> -{
>>>>>> - /* Hook to cpuidle framework if available, else
>>>>>> - * call on default platform idle code
>>>>>> - */
>>>>>> - if (cpuidle_idle_call()) {
>>>>>> - power7_idle();
>>>>>> - }
>>>>>>
>>
>> drivers/cpuidle/cpuidle-powernv.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c
>> index 78fd174..130f081 100644
>> --- a/drivers/cpuidle/cpuidle-powernv.c
>> +++ b/drivers/cpuidle/cpuidle-powernv.c
>> @@ -31,11 +31,13 @@ static int snooze_loop(struct cpuidle_device *dev,
>> set_thread_flag(TIF_POLLING_NRFLAG);
>>
>> while (!need_resched()) {
>> + ppc64_runlatch_off();
> ^^^^^^^^^^^^^^^
> We could move this before the while() loop.
> It would ideal to turn off latch when we enter snooze and
> turn it on when we are about to exit, rather than doing
> it over and over in the while loop.
You are right, this can be moved out of the loop.
Thanks
Regards
Preeti U Murthy
^ permalink raw reply
* [PATCH 2/2] ALSA: hda/ca0132 - Fix recording from mode id 0x8
From: Takashi Iwai @ 2014-02-07 11:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391744130-15043-2-git-send-email-hychao@chromium.org>
At Fri, 7 Feb 2014 11:35:30 +0800,
Hsin-Yu Chao wrote:
>
> The Chromebook Pixel has a microphone under the keyboard that
> is attached to node id 0x8. Before this fix, recording would
> always go to the main internal mic (node id 0x7).
>
> Signed-off-by: Hsin-Yu Chao <hychao@chromium.org>
> Reviewed-by: Dylan Reid <dgreid@chromium.org>
The description doesn't state why it fixes what: the patch is actually
a fix for the wrong ADC pickup in ca0132_capture_pcm_prepare() where
it assumes wrongly the multiple streams although the driver implements
one stream per ADC. (And, ca0132_capture_pcm_cleanup() already does
the right thing.)
Could you rephrase the patch description and resend?
thanks,
Takashi
> ---
> sound/pci/hda/patch_ca0132.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c
> index 59104dc..d5aabce 100644
> --- a/sound/pci/hda/patch_ca0132.c
> +++ b/sound/pci/hda/patch_ca0132.c
> @@ -2770,9 +2770,7 @@ static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
> unsigned int format,
> struct snd_pcm_substream *substream)
> {
> - struct ca0132_spec *spec = codec->spec;
> -
> - snd_hda_codec_setup_stream(codec, spec->adcs[substream->number],
> + snd_hda_codec_setup_stream(codec, hinfo->nid,
> stream_tag, 0, format);
>
> return 0;
> --
> 1.9.0.rc1.175.g0b1dcb5
>
^ permalink raw reply
* [PATCH v2 6/6] cpu/idle.c: move to sched/idle.c
From: Nicolas Pitre @ 2014-02-07 11:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140206164336.GU2936@laptop.programming.kicks-ass.net>
On Thu, 6 Feb 2014, Peter Zijlstra wrote:
> On Thu, Feb 06, 2014 at 02:09:59PM +0000, Nicolas Pitre wrote:
> > Hi Peter,
> >
> > Did you merge those patches in your tree?
>
> tree, tree, what's in a word.
Something you may plant on a patch of grass? "Merging" becomes a
strange concept in that context though. :-)
> Its in my patch stack yes.
Quilt I suppose?? (yet another word.)
> I should get some of that into tip I suppose, been side-tracked a bit
> this week. Sorry for the delay.
If you prefer we pile those patches (and future ones after revew)
ourselves just let me know. Future patches are likely to be more
intimate with the scheduler so I just need to know who to upstream them
through afterwards.
Nicolas
^ permalink raw reply
* [PATCH 1/2] ALSA: hda/ca0132 - setup/cleanup streams
From: Takashi Iwai @ 2014-02-07 11:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <s5hvbwrtchj.wl%tiwai@suse.de>
At Fri, 07 Feb 2014 11:59:20 +0100,
Takashi Iwai wrote:
>
> At Fri, 7 Feb 2014 11:35:29 +0800,
> Hsin-Yu Chao wrote:
> >
> > When a HDMI stream is opened with the same stream tag
> > as a following opened stream to ca0132, audio will be
> > heard from two ports simultaneously.
> > Fix this issue by change to use snd_hda_codec_setup_stream
> > and snd_hda_codec_cleanup_stream instead, so that an
> > inactive stream can be marked as 'dirty' when found
> > with a conflict stream tag, and then get purified.
> >
> > Signed-off-by: Hsin-Yu Chao <hychao@chromium.org>
> > Reviewed-by: Chih-Chung Chang <chihchung@chromium.org>
>
> Thanks, applied this one.
Hrm, not good.
sound/pci/hda/patch_ca0132.c: In function ?ca0132_playback_pcm_prepare?:
sound/pci/hda/patch_ca0132.c:2675:2: error: implicit declaration of function ?ca0132_toggle_dac_format? [-Werror=implicit-function-declaration]
ca0132_toggle_dac_format(codec);
^
Please give a patch that really builds and works cleanly with the
upstream code!
thanks,
Takashi
^ permalink raw reply
* [PATCH 3/6] irqchip: gic: use writel instead of dsb + writel_relaxed
From: Will Deacon @ 2014-02-07 11:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140206152048.GD32520@arm.com>
On Thu, Feb 06, 2014 at 03:20:48PM +0000, Catalin Marinas wrote:
> On Thu, Feb 06, 2014 at 01:26:44PM +0000, Will Deacon wrote:
> > On Thu, Feb 06, 2014 at 12:23:40PM +0000, Catalin Marinas wrote:
> > > On Thu, Feb 06, 2014 at 12:13:50PM +0000, Will Deacon wrote:
> > > > Ok, so if we assume that a dsb(ishst) is sufficient because the CPU we're
> > > > talking to is either (a) coherent in the inner-shareable domain or (b)
> > > > incoherent, and we flushed everything to PoC, then why wouldn't a dmb(ishst)
> > > > work?
> > >
> > > Because you want to guarantee the ordering between a store to Normal
> > > Cacheable memory vs store to Device for the IPI (see the mailbox example
> > > in the Barrier Litmus section ;)). The second is just a slave access, DMB
> > > guarantees observability from the master access perspective.
> >
> > Ok, my reasoning is as follows:
> >
> > - CPU0 tries to message CPU1. It writes to a location in normal memory,
> > then writes to the GICD to send the SGI
> >
> > - We need to ensure that CPU1 observes the write to normal memory before
> > the write to GICD reaches the distributor. This is *not* about end-point
> > ordering (the usual non-coherent DMA example).
> >
> > - A dmb ishst ensures that the two writes are observed in order by CPU1
> > (and, in fact, the inner-shareable domain containing CPU0).
>
> The last bullet point is not correct. DMB would only guarantee that the
> two writes (memory and GICD) are observed by CPU1 if CPU1 actually read
> the GICD (observability is defined for master accesses).
No, that's not how observability is defined, unfortunately.
Rather than attempt to solve this via email (your examples below are already
getting hard to follow :), how about we sit down with $drink_of_choice and
post back here with our conclusions?
In the meantime, I'll use dsb(ishst) because I think we now agree that
works. The question is whether it can be relaxed further to a dmb.
Will
^ permalink raw reply
* [PATCH] gpio: mvebu: use chained_irq_{enter, exit} for GIC compatibility
From: Thomas Petazzoni @ 2014-02-07 11:29 UTC (permalink / raw)
To: linux-arm-kernel
On currently supported SoCs, the GPIO block used on Marvell EBU SoCs
is always connected to the Marvell MPIC. However, we are going to
introduce the support for newer Marvell EBU SoCs that use the
Cortex-A9 core, and therefore use the GIC as their main interrupt
controller, to which the GPIO block controlled by the gpio-mvebu
driver is connected.
The GIC interrupt controller driver uses the fasteoi flow handler. In
order to ensure that the eoi hook of the GIC driver gets called, the
GPIO driver should call chained_irq_enter() and chained_irq_exit() in
its handler. Without this, the first GPIO interrupt locks up the
system because it doesn't get acked at the GIC level.
This change is similar to for example commit
0d978eb7349941139241a99acf05de6dd49b78d1 ("gpio: davinci: use
chained_irq_enter/chained_irq_exit API").
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/gpio/gpio-mvebu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 3b1fd1c..d425094 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -44,6 +44,7 @@
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/irqchip/chained_irq.h>
/*
* GPIO unit register offsets.
@@ -438,12 +439,15 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
u32 cause, type;
int i;
if (mvchip == NULL)
return;
+ chained_irq_enter(chip, desc);
+
cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
@@ -466,8 +470,11 @@ static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
polarity ^= 1 << i;
writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
}
+
generic_handle_irq(irq);
}
+
+ chained_irq_exit(chip, desc);
}
#ifdef CONFIG_DEBUG_FS
--
1.8.3.2
^ permalink raw reply related
* [PATCH v2 1/7] ARM: perf_event: Support percpu irqs for the CPU PMU
From: Will Deacon @ 2014-02-07 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D96E5C.4040506@codeaurora.org>
Hi Stephen,
I just remembered about this series.
On Fri, Jan 17, 2014 at 05:54:36PM +0000, Stephen Boyd wrote:
> On 01/17/14 07:04, Will Deacon wrote:
> > Hi Stephen,
> >
> > On Wed, Jan 15, 2014 at 08:54:27PM +0000, Stephen Boyd wrote:
> >> On 01/15, Stephen Boyd wrote:
> >>> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> >>> index 789d846a9184..e76750980b38 100644
> >>> --- a/arch/arm/kernel/perf_event.c
> >>> +++ b/arch/arm/kernel/perf_event.c
> >>> @@ -295,9 +297,15 @@ validate_group(struct perf_event *event)
> >>>
> >>> static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
> >>> {
> >>> - struct arm_pmu *armpmu = (struct arm_pmu *) dev;
> >>> - struct platform_device *plat_device = armpmu->plat_device;
> >>> - struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
> >>> + struct arm_pmu *armpmu;
> >>> + struct platform_device *plat_device;
> >>> + struct arm_pmu_platdata *plat;
> >>> +
> >>> + if (irq_is_percpu(irq))
> >>> + dev = *(struct arm_pmu_cpu **)dev;
> >> Oh. I just realized that struct arm_pmu_cpu doesn't even exist. This
> >> still compiles though because we're dealing with a void pointer.
> >>
> >> Perhaps its better to just do
> >>
> >> dev = *(void **)dev;
> >>
> >> here. Can you fix that up when applying? Otherwise I'll do it on
> >> the next send if there are more comments.
> > Shouldn't that actually be some per_cpu accessor like this_cpu_ptr?
> >
>
> Nope. The genirq layer unwraps the per_cpu pointer and passes it to the
> handler.
I think we resolved all the questions/issues that came up during review.
Please can you send a new version that I can take into my tree for 3.15?
Cheers,
Will
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