* [PATCH v2 1/5] drivers: of: add initialization code for reserved memory
From: Grant Likely @ 2014-02-11 12:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FA0D6E.9090304@samsung.com>
On Tue, 11 Feb 2014 12:45:50 +0100, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> Hello,
>
> On 2014-02-05 12:05, Grant Likely wrote:
> > On Tue, 04 Feb 2014 13:09:29 +0100, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> > > This patch adds device tree support for contiguous and reserved memory
> > > regions defined in device tree.
> > >
> > > Large memory blocks can be reliably reserved only during early boot.
> > > This must happen before the whole memory management subsystem is
> > > initialized, because we need to ensure that the given contiguous blocks
> > > are not yet allocated by kernel. Also it must happen before kernel
> > > mappings for the whole low memory are created, to ensure that there will
> > > be no mappings (for reserved blocks) or mapping with special properties
> > > can be created (for CMA blocks). This all happens before device tree
> > > structures are unflattened, so we need to get reserved memory layout
> > > directly from fdt.
> > >
> > > Later, those reserved memory regions are assigned to devices on each
> > > device structure initialization.
> > >
> > > Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > > Cc: Laura Abbott <lauraa@codeaurora.org>
> > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > > [joshc: rework to implement new DT binding, provide mechanism for
> > > plugging in new reserved-memory node handlers via
> > > RESERVEDMEM_OF_DECLARE]
> > > Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
> > > [mszyprow: little code cleanup]
> > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > > ---
> > > drivers/of/Kconfig | 6 +
> > > drivers/of/Makefile | 1 +
> > > drivers/of/of_reserved_mem.c | 219 +++++++++++++++++++++++++++++++++++++
> > > drivers/of/platform.c | 7 ++
> > > include/asm-generic/vmlinux.lds.h | 11 ++
> > > include/linux/of_reserved_mem.h | 62 +++++++++++
> > > 6 files changed, 306 insertions(+)
> > > create mode 100644 drivers/of/of_reserved_mem.c
> > > create mode 100644 include/linux/of_reserved_mem.h
> > >
> > > diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
> > > index c6973f101a3e..aba13df56f3a 100644
> > > --- a/drivers/of/Kconfig
> > > +++ b/drivers/of/Kconfig
> > > @@ -75,4 +75,10 @@ config OF_MTD
> > > depends on MTD
> > > def_bool y
> > >
> > > +config OF_RESERVED_MEM
> > > + depends on HAVE_MEMBLOCK
> > > + def_bool y
> > > + help
> > > + Helpers to allow for reservation of memory regions
> > > +
> > > endmenu # OF
> > > diff --git a/drivers/of/Makefile b/drivers/of/Makefile
> > > index efd05102c405..ed9660adad77 100644
> > > --- a/drivers/of/Makefile
> > > +++ b/drivers/of/Makefile
> > > @@ -9,3 +9,4 @@ obj-$(CONFIG_OF_MDIO) += of_mdio.o
> > > obj-$(CONFIG_OF_PCI) += of_pci.o
> > > obj-$(CONFIG_OF_PCI_IRQ) += of_pci_irq.o
> > > obj-$(CONFIG_OF_MTD) += of_mtd.o
> > > +obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o
> > > diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c
> > > new file mode 100644
> > > index 000000000000..f17cd56e68d9
> > > --- /dev/null
> > > +++ b/drivers/of/of_reserved_mem.c
> > > @@ -0,0 +1,219 @@
> > > +/*
> > > + * Device tree based initialization code for reserved memory.
> > > + *
> > > + * Copyright (c) 2013, The Linux Foundation. All Rights Reserved.
> > > + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> > > + * http://www.samsung.com
> > > + * Author: Marek Szyprowski <m.szyprowski@samsung.com>
> > > + * Author: Josh Cartwright <joshc@codeaurora.org>
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > + * modify it under the terms of the GNU General Public License as
> > > + * published by the Free Software Foundation; either version 2 of the
> > > + * License or (at your optional) any later version of the license.
> > > + */
> > > +#include <linux/memblock.h>
> > > +#include <linux/err.h>
> > > +#include <linux/of.h>
> > > +#include <linux/of_fdt.h>
> > > +#include <linux/of_platform.h>
> > > +#include <linux/mm.h>
> > > +#include <linux/sizes.h>
> > > +#include <linux/of_reserved_mem.h>
> > > +
> > > +#define MAX_RESERVED_REGIONS 16
> > > +static struct reserved_mem reserved_mem[MAX_RESERVED_REGIONS];
> > > +static int reserved_mem_count;
> > > +
> > > +int __init of_parse_flat_dt_reg(unsigned long node, const char *uname,
> > > + phys_addr_t *base, phys_addr_t *size)
> >
> > Useful utility function; move to drivers/of/fdt.c
> >
> > > +{
> > > + unsigned long len;
> > > + __be32 *prop;
> > > +
> > > + prop = of_get_flat_dt_prop(node, "reg", &len);
> > > + if (!prop)
> > > + return -EINVAL;
> > > +
> > > + if (len < (dt_root_addr_cells + dt_root_size_cells) * sizeof(__be32)) {
> > > + pr_err("Reserved memory: invalid reg property in '%s' node.\n",
> > > + uname);
> > > + return -EINVAL;
> > > + }
> >
> > This is /okay/ for an initial implementation, but it is naive. While I
> > suggested making #address-cells and #size-cells equal the root node
> > values for the purpose of simplicity, it should still be perfectly valid
> > to have different values if the ranges property is correctly formed.
> >
> > > +
> > > + *base = dt_mem_next_cell(dt_root_addr_cells, &prop);
> > > + *size = dt_mem_next_cell(dt_root_size_cells, &prop);
> >
> > Future enhancement; allow for parsing more than just the first reg
> > tuple.
>
> One more question. Does it really makes any sense to support more than
> one tuple for reg property? For consistency we should also allow more
> than one entry in size, align and alloc-ranges property, but I don't
> see any benefits for defining more than one range for a single region.
> Same can be achieved by defining more regions instead if one really
> needs such configuration.
Yes, if only because it is an define usage of the reg property. If a
devtree has multiple tuples in reg, then all of those tuples should be
treated as reserved, even if the kernel doesn't know how to use them.
I would not do the same for size/align/alloc-ranges unless there is a
very specific use case that you can define. These ones are different
from the static regions because they aren't ever used to protect
something that already exists in the memory.
g.
^ permalink raw reply
* [PATCH 0/7] primecell: make correct clock parsing possible
From: Russell King - ARM Linux @ 2014-02-11 12:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392118632-11312-1-git-send-email-mark.rutland@arm.com>
On Tue, Feb 11, 2014 at 11:37:05AM +0000, Mark Rutland wrote:
> These patches attempt to harmonize the bindings and the drivers with what's in
> use today, in a backwards compatible fashion, relieving us of our present
> Kafkaesque nightmare. Each peripheral's clock(s) are given explicit names which
> can be used, though code will fall back to the existing behaviour if said names
> are not provided. Additionally the currently unmet ordering requirement of
> apb_pclk is dropped, given all existing that code requires this to be named
> anyway.
The reason why these clocks ended up with NULL names was to force the
issue that clocks shall not be named solely by their connection IDs,
which was a major problem before DT. Now that we have DT, I'm happier
to reinstate the names, but I think we should just reinstate the names
we had previously. That should be in the git history.
The down-side is those names are all in capitals - but they were named
after the signal name(s) given in the Primecell documentation.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* [PATCH 1/7] sound: codec: add Device Tree binding to cs42l51
From: Mark Brown @ 2014-02-11 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391102051-5319-2-git-send-email-thomas.petazzoni@free-electrons.com>
On Thu, Jan 30, 2014 at 06:14:05PM +0100, Thomas Petazzoni wrote:
> This commit adds a trivial Device Tree binding to the I2C-based
> cs42l51 sound codec, so that it can be used from Device Tree based
> platforms.
Applied, thanks.
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* [PATCH] can: xilinx CAN controller support.
From: Marc Kleine-Budde @ 2014-02-11 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <da80c522-5524-4f53-9373-3f2bb6f81ddc@CO9EHSMHS015.ehs.local>
On 02/11/2014 12:45 PM, Michal Simek wrote:
> Hi Marc,
>
> On 02/07/2014 10:37 AM, Marc Kleine-Budde wrote:
>> On 02/07/2014 09:42 AM, Appana Durga Kedareswara Rao wrote:
>>>>> ---
>>>>> This patch is rebased on the 3.14 rc1 kernel.
>>>>> ---
>>>>> .../devicetree/bindings/net/can/xilinx_can.txt | 43 +
>>>>> drivers/net/can/Kconfig | 8 +
>>>>> drivers/net/can/Makefile | 1 +
>>>>> drivers/net/can/xilinx_can.c | 1150 ++++++++++++++++++++
>>>>> 4 files changed, 1202 insertions(+), 0 deletions(-) create mode
>>>>> 100644 Documentation/devicetree/bindings/net/can/xilinx_can.txt
>>>>> create mode 100644 drivers/net/can/xilinx_can.c
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/net/can/xilinx_can.txt
>>>>> b/Documentation/devicetree/bindings/net/can/xilinx_can.txt
>>>>> new file mode 100644
>>>>> index 0000000..34f9643
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/net/can/xilinx_can.txt
>>>>> @@ -0,0 +1,43 @@
>>>>> +Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
>>>>> +---------------------------------------------------------
>>>>> +
>>>>> +Required properties:
>>>>> +- compatible : Should be "xlnx,zynq-can-1.00.a" for Zynq
>>>> CAN
>>>>> + controllers and "xlnx,axi-can-1.00.a" for Axi CAN
>>>>> + controllers.
>>>>> +- reg : Physical base address and size of the Axi CAN/Zynq
>>>>> + CANPS registers map.
>>>>> +- interrupts : Property with a value describing the interrupt
>>>>> + number.
>>>>> +- interrupt-parent : Must be core interrupt controller
>>>>> +- clock-names : List of input clock names - "ref_clk",
>>>> "aper_clk"
>>>>> + (See clock bindings for details. Two clocks are
>>>>> + required for Zynq CAN. For Axi CAN
>>>>> + case it is one(ref_clk)).
>>>>> +- clocks : Clock phandles (see clock bindings for details).
>>>>> +- xlnx,can-tx-dpth : Can Tx fifo depth (Required for Axi CAN).
>>>>> +- xlnx,can-rx-dpth : Can Rx fifo depth (Required for Axi CAN).
>>>>> +
>>>>> +
>>>>> +Example:
>>>>> +
>>>>> +For Zynq CANPS Dts file:
>>>>> + zynq_can_0: zynq-can at e0008000 {
>>>>> + compatible = "xlnx,zynq-can-1.00.a";
>>>>> + clocks = <&clkc 19>, <&clkc 36>;
>>>>> + clock-names = "ref_clk", "aper_clk";
>>>>> + reg = <0xe0008000 0x1000>;
>>>>> + interrupts = <0 28 4>;
>>>>> + interrupt-parent = <&intc>;
>>>>
>>>> Above xlnx,can-{rx,tx}-dpth is mentioned as required, but it's not in the
>>>> Zynq example.
>>>
>>> One of the Difference b/w the AXI CAN and zynq CAN is in AXI CAN the fifo depth(tx,rx)
>>> Is user configurable. But in case of ZYNQ CAN the fifo depth is fixed for tx and rx fifo's(64)
>>> Xlnx,can-{rx,tx}-dpth is required only for AXI CAN case it is not required for zynq CAN.
>>> That's why didn't putted that property in device tree.
>>
>> The device tree should be a hardware only description and should not
>> hold any user configurable data. Please split your patch into two
>> patches. The first one should add the driver with a fixed fifo size
>> (e.g. 0x40) for the AXI, too. The second patch should make the fifo
>> configurable via device tree.
>
> can-rx/tx-dpth is not user configurable data as you think.
> This is FPGA where you can configure this parameter in design tools.
> It means these 2 values just describe real hardware and user can't just change it
> for different software behaviour.
I see, thanks for the clarification. I had a short grep over the
arm/boot/dts folder and it seems that fifo-depth is a more or less
common property. I think it should be called {rx,tx}-fifo-depth. I'm
unsure whether we need the xlnx or not.
> Also I don't think it is worth to create 2 patches for the same driver
> where the first one is useless for axi can device. But if you think
> that it is worth to do we can create 2 patches as you suggested.
>
> Also what we can do is to define that this property is required also
> for zynq which is 0x40 and change code according too.
Good idea, I think this would make the driver more uniform.
>> If it's acceptable to describe the fifo usage by device tree, I'd like
>> to make it a generic CAN driver option. But we have to look around, e.g.
>> what the Ethernet driver use to configure their hardware.
>
> I think the real question is not if this is acceptable or not. It is just
> reality that we can setup hardware fifo depth and driver has to reflect this
> because without it driver just doesn't work for axi can.
>
> The only remaining question is if we should create generic DT binding
> for fifo depth. Arnd, Rob: Any opinion about it?
> Definitely will be worth to have one generic binding if this is generic feature.
> But if this is just specific feature for us then current properties should
> be fine.
>
> In general all these xlnx,XXX properties just reflect all configurable options
> which you can setup in design tool which means that provide full hw description
> with all variants and they are automatically generated from tools.
>
> Please let me know what you think.
I like:
rx-fifo-depth
tx-fifo-depth
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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* [PATCH 2/7] sound: soc: enable Kirkwood driver for mvebu platforms
From: Mark Brown @ 2014-02-11 12:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391102051-5319-3-git-send-email-thomas.petazzoni@free-electrons.com>
On Thu, Jan 30, 2014 at 06:14:06PM +0100, Thomas Petazzoni wrote:
> The audio unit found in the Armada 370 SoC is similar to the one used
> in the Marvell Kirkwood and Marvell Dove SoCs. Therefore, this commit
> allows the Kirkwood audio driver to be built on mvebu platforms, and
> adds an additional compatible string to identify the Armada 370
> variant of the audio unit.
Applied, thanks.
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* [PATCH 3/7] sound: soc: add ASoC board driver for Armada 370 DB
From: Mark Brown @ 2014-02-11 12:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391102051-5319-4-git-send-email-thomas.petazzoni@free-electrons.com>
On Thu, Jan 30, 2014 at 06:14:07PM +0100, Thomas Petazzoni wrote:
> + fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS;
> + ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
> + if (ret < 0)
> + return ret;
> +
> + ret = snd_soc_dai_set_fmt(codec_dai, fmt);
> + if (ret < 0)
> + return ret;
Set .dai_fmt in the DAI link.
> +static int a370db_dai_init(struct snd_soc_pcm_runtime *rtd)
> +{
> + struct snd_soc_codec *codec = rtd->codec;
> + struct snd_soc_dapm_context *dapm = &codec->dapm;
> +
> + snd_soc_dapm_enable_pin(dapm, "Out Jack");
> + snd_soc_dapm_enable_pin(dapm, "In Jack");
No need to do this, everything defaults to enabled.
> +
> + card->dev = &pdev->dev;
> +
> + return snd_soc_register_card(card);
> +}
devm_snd_soc_register_card().
> +static const struct of_device_id a370db_dt_ids[] = {
> + { .compatible = "marvell,a370db-audio" },
> + { },
> +};
No binding document for this, and you should be using DT to look up the
controller and CODEC rather than hard coding their names (which may
change in future when instantiated from DT, especially the platform
device).
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* [PATCH v6 0/3] Introduce clocksource driver for Keystone platform
From: Daniel Lezcano @ 2014-02-11 12:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F8F55A.2090903@ti.com>
On 02/10/2014 04:50 PM, Santosh Shilimkar wrote:
> Daniel,
>
> On Monday 10 February 2014 05:10 AM, Ivan Khoronzhuk wrote:
>> Add a broadcast timer64 based clockevent driver for keystone arch.
>> This driver uses timer in 64-bit general purpose mode as clock event
>> device.
>>
>> Documentation:
>> http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
>>
>> Based on
>> git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
>> keystone/master
>>
>> v5..v6:
>> added function to encapsulate __iowmb().
>>
>> v4..v5:
>> used __iowmb() insted of wmb()
>>
>> v3..v4:
>> rebased on latest of linux-keystone.git keystone/master
>>
>> v2..v3:
>> - clocksource: timer-keystone: introduce clocksource driver for
>> changed "u64" type to "unsigned long" for hz_period as more appropriate
>> hz_period rounded up by DIV_ROUND_UP(rate, HZ)
>> corrected comments
>>
>> v1..v2:
>> - clocksource: timer-keystone: introduce clocksource driver for
>> renamed timer on "timer-keystone"
>> in keystone_timer_interrupt() evet pointer is passed via "dev_id"
>> used __relaxed variants of writel/readl and added explicit barriers
>> added "keystone_timer_disable()" for using in keystone_set_mode()
>> keystone_timer_config() is not used for disabling the timer any more
>> in case of an unsupported mode the keystone_timer_config() returns -1.
>> used request_irq() instead of setup_irq()
>> assigned irq for event_device in event_dev->irq
>> calculated timer.hz_period for CLOCK_EVT_MODE_PERIODIC at init
>> deleted spare call of keystone_timer_config() in keystone_timer_init()
>>
>> Ivan Khoronzhuk (3):
>> clocksource: timer-keystone: introduce clocksource driver for Keystone
>> clocksource: keystone: add bindings for keystone timer
>> arm: dts: keystone: add keystone timer entry
>>
> Can you queue the first two patches from the series ?
> I will queue the dts patch via my tree.
Sure.
--
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^ permalink raw reply
* [PATCH v6 1/3] clocksource: timer-keystone: introduce clocksource driver for Keystone
From: Daniel Lezcano @ 2014-02-11 12:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392027058-11680-2-git-send-email-ivan.khoronzhuk@ti.com>
On 02/10/2014 11:10 AM, Ivan Khoronzhuk wrote:
> Add broadcast clock-event device for the Keystone arch.
>
> The timer can be configured as a general-purpose 64-bit timer,
> dual general-purpose 32-bit timers. When configured as dual 32-bit
> timers, each half can operate in conjunction (chain mode) or
> independently (unchained mode) of each other.
>
> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
> Acked-by: Santosh shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
Applied to my tree for 3.15
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
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^ permalink raw reply
* [PATCH v6 2/3] clocksource: keystone: add bindings for keystone timer
From: Daniel Lezcano @ 2014-02-11 12:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392027058-11680-3-git-send-email-ivan.khoronzhuk@ti.com>
On 02/10/2014 11:10 AM, Ivan Khoronzhuk wrote:
> This patch provides bindings for the 64-bit timer in the KeyStone
> architecture devices. The timer can be configured as a general-purpose 64-bit
> timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
> timers, each half can operate in conjunction (chain mode) or independently
> (unchained mode) of each other.
>
> It is global timer is a free running up-counter and can generate interrupt
> when the counter reaches preset counter values.
>
> Documentation:
> http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
>
> Acked-by: Rob Herring <robh@kernel.org>
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
Applied to my tree for 3.15
Thanks !
-- Daniel
--
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^ permalink raw reply
* [PATCH] ARM: ux500: disable msp2 device tree node
From: Linus Walleij @ 2014-02-11 13:02 UTC (permalink / raw)
To: linux-arm-kernel
Commit 70b41abc151f9
"ARM: ux500: move MSP pin control to the device tree"
accidentally activated MSP2, giving rise to a boot scroll
scream as the kernel attempts to probe a driver for it and
fails to obtain DMA channel 14.
Fix this up by marking the node disabled again.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Hi ARM SoC guys, can you please apply this patch directly
for fixes, there is no point to send a pull request with a
single patch in it.
---
arch/arm/boot/dts/ste-href.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 0c1e8d871ed1..6cb9b68e2188 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -188,7 +188,6 @@
msp2: msp at 80117000 {
pinctrl-names = "default";
pinctrl-0 = <&msp2_default_mode>;
- status = "okay";
};
msp3: msp at 80125000 {
--
1.8.5.3
^ permalink raw reply related
* [PATCH 0/2] Marvell Armada 375 and 38x timer support
From: Daniel Lezcano @ 2014-02-11 13:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392059274-26965-1-git-send-email-ezequiel.garcia@free-electrons.com>
On 02/10/2014 08:07 PM, Ezequiel Garcia wrote:
> Hello Daniel,
>
> This small series adds support for the two new Marvell ARM SoCs:
> the Armada 375 and Armada 38x.
>
> These new SoCs are based on Cortex-A9 CPU cores, and share a
> number of peripherals with their predecessors in the mach-mvebu
> family. The core support (arch/arm/mach-mvebu) for these SOCs have just
> been posted, and we're aiming at having this merged for 3.15.
>
> The A375 SoC timer is modeled matching the A370 timer, while the
> A38x SoC timer is modeled matching the AXP timer. However, we'd like
> to keep the compatible strings as SoC-specific.
>
> In the past, we've had trouble chosing a common compatible string, resulting
> in the introduction of per-SoC compatibles. Such compatible-string change
> of course implies breaking backards compatibility, and was only possible
> after agreeing that the old compatible wasn't used in production.
>
> So, in order to avoid such problems, we think it's better to keep them
> separate.
>
> Gregory CLEMENT (2):
> clocksource: armada-370-xp: Add support for Armada 375
> clocksource: armada-370-xp: Add support for Armada 38x
>
> .../bindings/timer/marvell,armada-370-xp-timer.txt | 13 ++++++++----
> drivers/clocksource/time-armada-370-xp.c | 23 +++++++++++++++++++++-
> 2 files changed, 31 insertions(+), 5 deletions(-)
Applied to my tree for 3.15.
Thanks !
-- Daniel
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH 0/3] ARM: dts: Fixes for Overo/Tobi against 3.14-rc1
From: Florian Vaussard @ 2014-02-11 13:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87d2j0rwv8.fsf@paris.lan>
Hi,
On 02/06/2014 06:09 PM, Kevin Hilman wrote:
> Florian Vaussard <florian.vaussard@epfl.ch> writes:
>
>> OMAP36xx-based Overo (Storm and alike) are now failing to boot with 3.14-rc1 [1].
>> This series fixes this, by moving model-agnostic DT into a common dtsi file,
>> and creating model-specific DT files:
>>
>> - omap3-overo-tobi.dts -> older OMAP35xx Overo
>> - omap3-overo-storm-tobi.dts -> newer OMAP36xx/AM37xx/DM37xx Overo
>>
>> People will have to use the right Overo / expansion board combination.
>>
>> (Patch 2 in an unrelated fix that was waiting in my queue.)
>>
>> omap3-overo-tobi.dts tested with Overo Sand (OMAP3503) and omap3-overo-storm-tobi.dts
>> tested with Overo EarthStorm (AM3703). Both boot. With the Overo Sand, I cannot
>> mount the ext3 rootfs, but this seems unrelated to the current topic, maybe
>> a missing errata.
>
> And I tested with my 35xx/Overo with omap3-overo-tobi.dts and my
> 37xx/Overo STORM with omap3-overo-storm-tobi.dts and they're both
> working.
>
> Tested-by: Kevin Hilman <khilman@linaro.org>
>
> Tony, with your ack, I can apply these directly to arm-soc/fixes.
>
> Florian, thanks for the fixes.
>
This issue is still present in 3.14-rc2.
Shall I send a v2, including the suggestion of Nishanth, against 3.14-rc2?
Regards,
Florian
^ permalink raw reply
* [PATCH 0/2] Marvell Armada 375 and 38x timer support
From: Jason Cooper @ 2014-02-11 13:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FA1FBD.90906@linaro.org>
Daniel,
On Tue, Feb 11, 2014 at 02:03:57PM +0100, Daniel Lezcano wrote:
> On 02/10/2014 08:07 PM, Ezequiel Garcia wrote:
> >Hello Daniel,
> >
> >This small series adds support for the two new Marvell ARM SoCs:
> >the Armada 375 and Armada 38x.
> >
> >These new SoCs are based on Cortex-A9 CPU cores, and share a
> >number of peripherals with their predecessors in the mach-mvebu
> >family. The core support (arch/arm/mach-mvebu) for these SOCs have just
> >been posted, and we're aiming at having this merged for 3.15.
> >
> >The A375 SoC timer is modeled matching the A370 timer, while the
> >A38x SoC timer is modeled matching the AXP timer. However, we'd like
> >to keep the compatible strings as SoC-specific.
> >
> >In the past, we've had trouble chosing a common compatible string, resulting
> >in the introduction of per-SoC compatibles. Such compatible-string change
> >of course implies breaking backards compatibility, and was only possible
> >after agreeing that the old compatible wasn't used in production.
> >
> >So, in order to avoid such problems, we think it's better to keep them
> >separate.
> >
> >Gregory CLEMENT (2):
> > clocksource: armada-370-xp: Add support for Armada 375
> > clocksource: armada-370-xp: Add support for Armada 38x
> >
> > .../bindings/timer/marvell,armada-370-xp-timer.txt | 13 ++++++++----
> > drivers/clocksource/time-armada-370-xp.c | 23 +++++++++++++++++++++-
> > 2 files changed, 31 insertions(+), 5 deletions(-)
>
> Applied to my tree for 3.15.
Please hold off until we've resolved the discussion regarding adding
unneeded compatible strings. It's under patch 6 in the main series
adding support for this new SoC.
[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver
thx,
Jason.
^ permalink raw reply
* [PATCH 0/2] Marvell Armada 375 and 38x timer support
From: Daniel Lezcano @ 2014-02-11 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211130758.GX8533@titan.lakedaemon.net>
On 02/11/2014 02:07 PM, Jason Cooper wrote:
> Daniel,
>
> On Tue, Feb 11, 2014 at 02:03:57PM +0100, Daniel Lezcano wrote:
>> On 02/10/2014 08:07 PM, Ezequiel Garcia wrote:
>>> Hello Daniel,
>>>
>>> This small series adds support for the two new Marvell ARM SoCs:
>>> the Armada 375 and Armada 38x.
>>>
>>> These new SoCs are based on Cortex-A9 CPU cores, and share a
>>> number of peripherals with their predecessors in the mach-mvebu
>>> family. The core support (arch/arm/mach-mvebu) for these SOCs have just
>>> been posted, and we're aiming at having this merged for 3.15.
>>>
>>> The A375 SoC timer is modeled matching the A370 timer, while the
>>> A38x SoC timer is modeled matching the AXP timer. However, we'd like
>>> to keep the compatible strings as SoC-specific.
>>>
>>> In the past, we've had trouble chosing a common compatible string, resulting
>>> in the introduction of per-SoC compatibles. Such compatible-string change
>>> of course implies breaking backards compatibility, and was only possible
>>> after agreeing that the old compatible wasn't used in production.
>>>
>>> So, in order to avoid such problems, we think it's better to keep them
>>> separate.
>>>
>>> Gregory CLEMENT (2):
>>> clocksource: armada-370-xp: Add support for Armada 375
>>> clocksource: armada-370-xp: Add support for Armada 38x
>>>
>>> .../bindings/timer/marvell,armada-370-xp-timer.txt | 13 ++++++++----
>>> drivers/clocksource/time-armada-370-xp.c | 23 +++++++++++++++++++++-
>>> 2 files changed, 31 insertions(+), 5 deletions(-)
>>
>> Applied to my tree for 3.15.
>
> Please hold off until we've resolved the discussion regarding adding
> unneeded compatible strings. It's under patch 6 in the main series
> adding support for this new SoC.
>
> [PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver
Ok, thanks for the heads up.
-- Daniel
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH] video: imxfb: Use regulator API with LCD class for powering
From: Tomi Valkeinen @ 2014-02-11 13:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211024318.GA31484@S2101-09.ap.freescale.net>
On 11/02/14 04:43, Shawn Guo wrote:
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
Thanks. Queued for 3.15.
Tomi
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^ permalink raw reply
* [PATCH] video: xilinxfb: Move xilinxfb_platform_data directly to the driver
From: Tomi Valkeinen @ 2014-02-11 13:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <af8de8bd8803b319c0f6a02ca5109768e5ef8457.1392101292.git.michal.simek@xilinx.com>
On 11/02/14 08:48, Michal Simek wrote:
> No reason to have separate file in header in include/linux folder
> if this is purely driver specific structure.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> I have this patch in my devel tree for a while and would like
> to hear your opinion. I can't see any reason to have
> xilinxfb_platform_data in header if this is purely OF driver
> used on OF archs.
> ---
> drivers/video/xilinxfb.c | 15 ++++++++++++++-
> include/linux/xilinxfb.h | 30 ------------------------------
> 2 files changed, 14 insertions(+), 31 deletions(-)
> delete mode 100644 include/linux/xilinxfb.h
Thanks. Queued for 3.15.
Tomi
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* [PATCH 0/2] Marvell Armada 375 and 38x timer support
From: Gregory CLEMENT @ 2014-02-11 13:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211130758.GX8533@titan.lakedaemon.net>
On 11/02/2014 14:07, Jason Cooper wrote:
> Daniel,
>
> On Tue, Feb 11, 2014 at 02:03:57PM +0100, Daniel Lezcano wrote:
>> On 02/10/2014 08:07 PM, Ezequiel Garcia wrote:
>>> Hello Daniel,
>>>
>>> This small series adds support for the two new Marvell ARM SoCs:
>>> the Armada 375 and Armada 38x.
>>>
>>> These new SoCs are based on Cortex-A9 CPU cores, and share a
>>> number of peripherals with their predecessors in the mach-mvebu
>>> family. The core support (arch/arm/mach-mvebu) for these SOCs have just
>>> been posted, and we're aiming at having this merged for 3.15.
>>>
>>> The A375 SoC timer is modeled matching the A370 timer, while the
>>> A38x SoC timer is modeled matching the AXP timer. However, we'd like
>>> to keep the compatible strings as SoC-specific.
>>>
>>> In the past, we've had trouble chosing a common compatible string, resulting
>>> in the introduction of per-SoC compatibles. Such compatible-string change
>>> of course implies breaking backards compatibility, and was only possible
>>> after agreeing that the old compatible wasn't used in production.
>>>
>>> So, in order to avoid such problems, we think it's better to keep them
>>> separate.
>>>
>>> Gregory CLEMENT (2):
>>> clocksource: armada-370-xp: Add support for Armada 375
>>> clocksource: armada-370-xp: Add support for Armada 38x
>>>
>>> .../bindings/timer/marvell,armada-370-xp-timer.txt | 13 ++++++++----
>>> drivers/clocksource/time-armada-370-xp.c | 23 +++++++++++++++++++++-
>>> 2 files changed, 31 insertions(+), 5 deletions(-)
>>
>> Applied to my tree for 3.15.
>
> Please hold off until we've resolved the discussion regarding adding
> unneeded compatible strings. It's under patch 6 in the main series
> adding support for this new SoC.
>
> [PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver
>
I still believe that having different compatible strings for
different IP even if at first sight they look similar.
Moreover we are already aware of some issue on this SoC such as
the 25Mhz timer which don't work (yet) on Armada 375.
Thanks,
Gregory
> thx,
>
> Jason.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] clk:at91: Fix memory leak in of_at91_clk_master_setup()
From: Masanari Iida @ 2014-02-11 13:15 UTC (permalink / raw)
To: linux-arm-kernel
cppcheck detected following error
[clk-master.c:245]: (error) Memory leak: characteristics
The original code forgot to free characteristics when
irq_of_parse_and_map() failed.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
---
drivers/clk/at91/clk-master.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index bd313f7..c1af80b 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -242,7 +242,7 @@ of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc,
irq = irq_of_parse_and_map(np, 0);
if (!irq)
- return;
+ goto out_free_characteristics;
clk = at91_clk_register_master(pmc, irq, name, num_parents,
parent_names, layout,
--
1.9.rc1
^ permalink raw reply related
* [PATCH] clk:at91: Fix memory leak in of_at91_clk_master_setup()
From: Boris BREZILLON @ 2014-02-11 13:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392124507-14463-1-git-send-email-standby24x7@gmail.com>
On 11/02/2014 14:15, Masanari Iida wrote:
> cppcheck detected following error
> [clk-master.c:245]: (error) Memory leak: characteristics
>
> The original code forgot to free characteristics when
> irq_of_parse_and_map() failed.
>
> Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by Boris BREZILLON <b.brezillon@overkiz.com>
Thanks for fixing this.
Best Regards,
Boris
> ---
> drivers/clk/at91/clk-master.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
> index bd313f7..c1af80b 100644
> --- a/drivers/clk/at91/clk-master.c
> +++ b/drivers/clk/at91/clk-master.c
> @@ -242,7 +242,7 @@ of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc,
>
> irq = irq_of_parse_and_map(np, 0);
> if (!irq)
> - return;
> + goto out_free_characteristics;
>
> clk = at91_clk_register_master(pmc, irq, name, num_parents,
> parent_names, layout,
^ permalink raw reply
* [PATCH 1/4] arm64: topology: Implement basic CPU topology support
From: Vincent Guittot @ 2014-02-11 13:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211103428.GC8693@mudshark.cambridge.arm.com>
On 11 February 2014 11:34, Will Deacon <will.deacon@arm.com> wrote:
> On Tue, Feb 11, 2014 at 08:15:19AM +0000, Vincent Guittot wrote:
>> On 10 February 2014 17:46, Mark Brown <broonie@kernel.org> wrote:
>> > On Mon, Feb 10, 2014 at 04:22:31PM +0000, Catalin Marinas wrote:
>> >> On Mon, Feb 10, 2014 at 01:02:01PM +0000, Mark Brown wrote:
>> >
>> >> > + if (cpu != cpuid)
>> >> > + cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
>> >> > + }
>> >> > + smp_wmb();
>> >
>> >> I now noticed there are a couple of smp_wmb() calls in this patch. What
>> >> are they for?
>> >
>> > To be honest I mostly cargo culted them from the ARM implementation; I
>> > did look a bit but didn't fully dig into it - it seemed they were
>> > required to ensure that the updates for the new CPU are visible over all
>> > CPUs. Vincent?
>>
>> Yes that's it. we must ensure that updates are made visible to other CPUs
>
> In relation to what? The smp_* barriers ensure ordering of observability
> between a number of independent accesses, so you must be ensuring
> ordering against something else. Also, you need to guarantee ordering on the
> read-side too -- how is this achieved? I can't see any smp_rmb calls from a
> quick grep, so I assume you're making use of address dependencies?
The boot sequence ensures the rmb
Vincent
>
> /confused
>
> Will
^ permalink raw reply
* [PATCH] can: xilinx CAN controller support.
From: Michal Simek @ 2014-02-11 13:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FA1910.2060101@pengutronix.de>
On 02/11/2014 01:35 PM, Marc Kleine-Budde wrote:
> On 02/11/2014 12:45 PM, Michal Simek wrote:
>> Hi Marc,
>>
>> On 02/07/2014 10:37 AM, Marc Kleine-Budde wrote:
>>> On 02/07/2014 09:42 AM, Appana Durga Kedareswara Rao wrote:
>>>>>> ---
>>>>>> This patch is rebased on the 3.14 rc1 kernel.
>>>>>> ---
>>>>>> .../devicetree/bindings/net/can/xilinx_can.txt | 43 +
>>>>>> drivers/net/can/Kconfig | 8 +
>>>>>> drivers/net/can/Makefile | 1 +
>>>>>> drivers/net/can/xilinx_can.c | 1150 ++++++++++++++++++++
>>>>>> 4 files changed, 1202 insertions(+), 0 deletions(-) create mode
>>>>>> 100644 Documentation/devicetree/bindings/net/can/xilinx_can.txt
>>>>>> create mode 100644 drivers/net/can/xilinx_can.c
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/net/can/xilinx_can.txt
>>>>>> b/Documentation/devicetree/bindings/net/can/xilinx_can.txt
>>>>>> new file mode 100644
>>>>>> index 0000000..34f9643
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/net/can/xilinx_can.txt
>>>>>> @@ -0,0 +1,43 @@
>>>>>> +Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
>>>>>> +---------------------------------------------------------
>>>>>> +
>>>>>> +Required properties:
>>>>>> +- compatible : Should be "xlnx,zynq-can-1.00.a" for Zynq
>>>>> CAN
>>>>>> + controllers and "xlnx,axi-can-1.00.a" for Axi CAN
>>>>>> + controllers.
>>>>>> +- reg : Physical base address and size of the Axi CAN/Zynq
>>>>>> + CANPS registers map.
>>>>>> +- interrupts : Property with a value describing the interrupt
>>>>>> + number.
>>>>>> +- interrupt-parent : Must be core interrupt controller
>>>>>> +- clock-names : List of input clock names - "ref_clk",
>>>>> "aper_clk"
>>>>>> + (See clock bindings for details. Two clocks are
>>>>>> + required for Zynq CAN. For Axi CAN
>>>>>> + case it is one(ref_clk)).
>>>>>> +- clocks : Clock phandles (see clock bindings for details).
>>>>>> +- xlnx,can-tx-dpth : Can Tx fifo depth (Required for Axi CAN).
>>>>>> +- xlnx,can-rx-dpth : Can Rx fifo depth (Required for Axi CAN).
>>>>>> +
>>>>>> +
>>>>>> +Example:
>>>>>> +
>>>>>> +For Zynq CANPS Dts file:
>>>>>> + zynq_can_0: zynq-can at e0008000 {
>>>>>> + compatible = "xlnx,zynq-can-1.00.a";
>>>>>> + clocks = <&clkc 19>, <&clkc 36>;
>>>>>> + clock-names = "ref_clk", "aper_clk";
>>>>>> + reg = <0xe0008000 0x1000>;
>>>>>> + interrupts = <0 28 4>;
>>>>>> + interrupt-parent = <&intc>;
>>>>>
>>>>> Above xlnx,can-{rx,tx}-dpth is mentioned as required, but it's not in the
>>>>> Zynq example.
>>>>
>>>> One of the Difference b/w the AXI CAN and zynq CAN is in AXI CAN the fifo depth(tx,rx)
>>>> Is user configurable. But in case of ZYNQ CAN the fifo depth is fixed for tx and rx fifo's(64)
>>>> Xlnx,can-{rx,tx}-dpth is required only for AXI CAN case it is not required for zynq CAN.
>>>> That's why didn't putted that property in device tree.
>>>
>>> The device tree should be a hardware only description and should not
>>> hold any user configurable data. Please split your patch into two
>>> patches. The first one should add the driver with a fixed fifo size
>>> (e.g. 0x40) for the AXI, too. The second patch should make the fifo
>>> configurable via device tree.
>>
>> can-rx/tx-dpth is not user configurable data as you think.
>> This is FPGA where you can configure this parameter in design tools.
>> It means these 2 values just describe real hardware and user can't just change it
>> for different software behaviour.
>
> I see, thanks for the clarification. I had a short grep over the
> arm/boot/dts folder and it seems that fifo-depth is a more or less
> common property. I think it should be called {rx,tx}-fifo-depth. I'm
> unsure whether we need the xlnx or not.
We are using xlnx prefix for all generated properties that's why
Kedar just kept it there.
>> Also I don't think it is worth to create 2 patches for the same driver
>> where the first one is useless for axi can device. But if you think
>> that it is worth to do we can create 2 patches as you suggested.
>>
>> Also what we can do is to define that this property is required also
>> for zynq which is 0x40 and change code according too.
>
> Good idea, I think this would make the driver more uniform.
ok.
>>> If it's acceptable to describe the fifo usage by device tree, I'd like
>>> to make it a generic CAN driver option. But we have to look around, e.g.
>>> what the Ethernet driver use to configure their hardware.
>>
>> I think the real question is not if this is acceptable or not. It is just
>> reality that we can setup hardware fifo depth and driver has to reflect this
>> because without it driver just doesn't work for axi can.
>>
>> The only remaining question is if we should create generic DT binding
>> for fifo depth. Arnd, Rob: Any opinion about it?
>> Definitely will be worth to have one generic binding if this is generic feature.
>> But if this is just specific feature for us then current properties should
>> be fine.
>>
>> In general all these xlnx,XXX properties just reflect all configurable options
>> which you can setup in design tool which means that provide full hw description
>> with all variants and they are automatically generated from tools.
>>
>> Please let me know what you think.
>
> I like:
>
> rx-fifo-depth
> tx-fifo-depth
No problem with that. Let Kedar to fix it according this and he will send v2 with this.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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* [PATCH] clk:ti: Fix memory leak in of_ti_composite_divider_clk_setup()
From: Masanari Iida @ 2014-02-11 13:25 UTC (permalink / raw)
To: linux-arm-kernel
cppcheck detected following error
[drivers/clk/ti/divider.c:480]: (error) Memory leak: div
The original code forgot to free div and just returned.
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
---
drivers/clk/ti/divider.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index a15e445..a105d94 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -477,7 +477,6 @@ static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
goto cleanup;
if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
- return;
cleanup:
kfree(div->table);
--
1.9.rc1
^ permalink raw reply related
* [RFC PATCH 0/4] i.MX6 PU power domain support
From: Philipp Zabel @ 2014-02-11 13:27 UTC (permalink / raw)
To: linux-arm-kernel
The i.MX6Q can gate off the CPU and PU (GPU/VPU) power domains using the
Power Gating Controller (PGC) in the GPC register space. The CPU power
domain is already handled by wait state code, but the PU power domain can
be controlled using the generic power domain framework and power off the PU
supply regulator if all devices in the power domain are (runtime) suspended.
This patchset adds a GPC platform device initialized at subsys_initcall time
(after anatop regulators) that binds to the gpc device tree node and sets up
the PU power domain:
gpc: gpc at 020dc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 0x04 0 90 0x04>;
pu-supply = <®_pu>;
pd_pu: power-domain at 020dc260 {
compatible = "fsl,power-domain";
reg = <0x020dc260 0x10>;
};
};
It registers a platform bus notifier so that it can add GPU and VPU devices
to the power domain when they are bound. If finds devices to be added to the
power domain by scanning the device tree for nodes that contain a
power-domain = <&pd_pu>;
property.
For i.MX6QDL there is only one power domain, but on i.MX6SL I suspect the
DISP power domain could be handled using the same mechanism.
regards
Philipp
Philipp Zabel (4):
ARM: imx6: gpc: Add PU power domain for GPU/VPU
ARM: imx6: gpc: Add pm clock support to PU power domain
ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp
delay
ARM: dts: imx6qdl: Add PU power-domain information to gpc node
arch/arm/boot/dts/imx6qdl.dtsi | 11 +-
arch/arm/mach-imx/Kconfig | 2 +
arch/arm/mach-imx/gpc.c | 243 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 255 insertions(+), 1 deletion(-)
--
1.8.5.3
^ permalink raw reply
* [RFC PATCH 1/4] ARM: imx6: gpc: Add PU power domain for GPU/VPU
From: Philipp Zabel @ 2014-02-11 13:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392125231-28387-1-git-send-email-p.zabel@pengutronix.de>
When generic pm domain support is enabled, the PGC can be used
to completely gate power to the PU power domain containing GPU3D,
GPU2D, and VPU cores.
This code triggers the PGC powerdown sequence to disable the GPU/VPU
isolation cells and gate power and then disables the PU regulator.
To reenable, the reverse powerup sequence is triggered after the PU
regulaotor is enabled again.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
arch/arm/mach-imx/Kconfig | 2 +
arch/arm/mach-imx/gpc.c | 169 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 171 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 33567aa..3c58f2e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -808,6 +808,7 @@ config SOC_IMX6Q
select PL310_ERRATA_727915 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310
select PM_OPP if PM
+ select PM_GENERIC_DOMAINS if PM
help
This enables support for Freescale i.MX6 Quad processor.
@@ -827,6 +828,7 @@ config SOC_IMX6SL
select PL310_ERRATA_588369 if CACHE_PL310
select PL310_ERRATA_727915 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310
+ select PM_GENERIC_DOMAINS if PM
help
This enables support for Freescale i.MX6 SoloLite processor.
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 586e017..c3ec2c5 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -10,19 +10,32 @@
* http://www.gnu.org/copyleft/gpl.html
*/
+#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
+#include "hardware.h"
+#define GPC_CNTR 0x000
#define GPC_IMR1 0x008
+#define GPC_PGC_GPU_PDN 0x260
+#define GPC_PGC_GPU_PUPSCR 0x264
+#define GPC_PGC_GPU_PDNSCR 0x268
#define GPC_PGC_CPU_PDN 0x2a0
#define IMR_NUM 4
+#define GPU_VPU_PUP_REQ BIT(1)
+#define GPU_VPU_PDN_REQ BIT(0)
+
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];
@@ -138,3 +151,159 @@ void __init imx_gpc_init(void)
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
}
+
+static struct regulator *pu_reg;
+
+static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
+{
+ u32 val;
+ int iso, iso2sw;
+
+ /* GPU3D, GPU2D, and VPU clocks should be disabled here */
+
+ /* Read ISO and ISO2SW power down delays */
+ val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
+ iso = val & 0x3f;
+ iso2sw = (val >> 8) & 0x3f;
+
+ /* Gate off PU domain when GPU/VPU when powered down */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+
+ /* Request GPC to power down GPU/VPU */
+ val = readl_relaxed(gpc_base + GPC_CNTR);
+ val |= GPU_VPU_PDN_REQ;
+ writel_relaxed(val, gpc_base + GPC_CNTR);
+
+ /* Wait ISO + ISO2SW IPG clock cycles */
+ ndelay((iso + iso2sw) * 1000 / 66);
+
+ regulator_disable(pu_reg);
+
+ return 0;
+}
+
+static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
+{
+ int ret;
+ u32 val;
+ int sw, sw2iso;
+
+ ret = regulator_enable(pu_reg);
+ if (ret) {
+ pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* Gate off PU domain when GPU/VPU when powered down */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+
+ /* Read ISO and ISO2SW power down delays */
+ val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
+ sw = val & 0x3f;
+ sw2iso = (val >> 8) & 0x3f;
+
+ /* Request GPC to power up GPU/VPU */
+ val = readl_relaxed(gpc_base + GPC_CNTR);
+ val |= GPU_VPU_PUP_REQ;
+ writel_relaxed(val, gpc_base + GPC_CNTR);
+
+ /* Wait ISO + ISO2SW IPG clock cycles */
+ ndelay((sw + sw2iso) * 1000 / 66);
+
+ return 0;
+}
+
+static struct generic_pm_domain imx6q_pu_domain = {
+ .name = "PU",
+ .power_off = imx6q_pm_pu_power_off,
+ .power_on = imx6q_pm_pu_power_on,
+};
+
+static int imx6q_pm_notifier_call(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct generic_pm_domain *genpd;
+ struct device *dev = data;
+ struct device_node *np;
+ int ret;
+
+ switch (event) {
+ case BUS_NOTIFY_BIND_DRIVER:
+ np = of_parse_phandle(dev->of_node, "power-domain", 0);
+ if (!np)
+ return NOTIFY_DONE;
+
+ ret = pm_genpd_of_add_device(np, dev);
+ if (ret)
+ dev_err(dev, "failed to add to power domain: %d\n",
+ ret);
+ break;
+ case BUS_NOTIFY_UNBOUND_DRIVER:
+ genpd = dev_to_genpd(dev);
+ if (IS_ERR(genpd))
+ return NOTIFY_DONE;
+ ret = pm_genpd_remove_device(genpd, dev);
+ if (ret)
+ dev_err(dev, "failed to remove from power domain: %d\n",
+ ret);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block imx6q_platform_nb = {
+ .notifier_call = imx6q_pm_notifier_call,
+};
+
+static int imx_gpc_probe(struct platform_device *pdev)
+{
+ struct device_node *np;
+ int ret;
+
+ np = of_get_child_by_name(pdev->dev.of_node, "power-domain");
+ if (!np) {
+ dev_err(&pdev->dev, "missing power-domain node\n");
+ return -EINVAL;
+ }
+
+ pu_reg = devm_regulator_get(&pdev->dev, "pu");
+ if (IS_ERR(pu_reg)) {
+ ret = PTR_ERR(pu_reg);
+ dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
+ return ret;
+ }
+
+ /* The regulator is initially enabled */
+ ret = regulator_enable(pu_reg);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to enable pu regulator: %d\n", ret);
+ return ret;
+ }
+
+ imx6q_pu_domain.of_node = np;
+ pm_genpd_init(&imx6q_pu_domain, NULL, false);
+ bus_register_notifier(&platform_bus_type, &imx6q_platform_nb);
+
+ return 0;
+}
+
+static struct of_device_id imx_gpc_dt_ids[] = {
+ { .compatible = "fsl,imx6q-gpc" },
+ { }
+};
+
+static struct platform_driver imx_gpc_driver = {
+ .driver = {
+ .name = "imx-gpc",
+ .owner = THIS_MODULE,
+ .of_match_table = imx_gpc_dt_ids,
+ },
+ .probe = imx_gpc_probe,
+};
+
+static int __init imx_pgc_init(void)
+{
+ return platform_driver_register(&imx_gpc_driver);
+}
+subsys_initcall(imx_pgc_init);
--
1.8.5.3
^ permalink raw reply related
* [RFC PATCH 2/4] ARM: imx6: gpc: Add pm clock support to PU power domain
From: Philipp Zabel @ 2014-02-11 13:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392125231-28387-1-git-send-email-p.zabel@pengutronix.de>
Drivers still handle clocks themselves, we only enable pm clocks of the
GPU and VPU devices in the PU power domain temporarily during powerup
so that the reset machinery can work.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
arch/arm/mach-imx/gpc.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index c3ec2c5..e3f4492 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -18,6 +18,7 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
@@ -184,6 +185,7 @@ static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
{
+ struct pm_domain_data *pdd;
int ret;
u32 val;
int sw, sw2iso;
@@ -194,6 +196,10 @@ static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
return ret;
}
+ /* Enable PM clocks for all devices in the PU domain */
+ list_for_each_entry(pdd, &genpd->dev_list, list_node)
+ pm_clk_resume(pdd->dev);
+
/* Gate off PU domain when GPU/VPU when powered down */
writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
@@ -210,6 +216,10 @@ static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
/* Wait ISO + ISO2SW IPG clock cycles */
ndelay((sw + sw2iso) * 1000 / 66);
+ /* Disable PM clocks for all devices in the PU domain */
+ list_for_each_entry(pdd, &genpd->dev_list, list_node)
+ pm_clk_suspend(pdd->dev);
+
return 0;
}
@@ -219,6 +229,68 @@ static struct generic_pm_domain imx6q_pu_domain = {
.power_on = imx6q_pm_pu_power_on,
};
+int imx6q_pm_clk_add(struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ const char *con_id;
+ struct clk *clk;
+ int i = 0;
+
+ /* Add and prepare named clocks */
+ while (!of_property_read_string_index(np, "clock-names", i, &con_id)) {
+ pm_clk_add(dev, con_id);
+ clk = of_clk_get(np, i);
+ if (!IS_ERR(clk)) {
+ clk_prepare(clk);
+ clk_put(clk);
+ }
+ i++;
+ }
+
+ /* If no named clocks are given, add and prepare unnamed clock */
+ if (i == 1 && of_find_property(dev->of_node, "clocks", NULL)) {
+ pm_clk_add(dev, NULL);
+ clk = of_clk_get(np, 0);
+ if (!IS_ERR(clk)) {
+ clk_prepare(clk);
+ clk_put(clk);
+ }
+ }
+
+ return 0;
+}
+
+int imx6q_pm_clk_remove(struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ const char *con_id;
+ struct clk *clk;
+ int i = 0;
+
+ /* Remove and unprepare named clocks */
+ while (!of_property_read_string_index(np, "clock-names", i, &con_id)) {
+ pm_clk_remove(dev, con_id);
+ clk = of_clk_get(np, i);
+ if (!IS_ERR(clk)) {
+ clk_unprepare(clk);
+ clk_put(clk);
+ }
+ i++;
+ }
+
+ /* If no named clocks are given, remove and unprepare unnamed clock */
+ if (i == 1 && of_find_property(dev->of_node, "clocks", NULL)) {
+ pm_clk_remove(dev, NULL);
+ clk = of_clk_get(np, 0);
+ if (!IS_ERR(clk)) {
+ clk_unprepare(clk);
+ clk_put(clk);
+ }
+ }
+
+ return 0;
+}
+
static int imx6q_pm_notifier_call(struct notifier_block *nb,
unsigned long event, void *data)
{
@@ -237,6 +309,7 @@ static int imx6q_pm_notifier_call(struct notifier_block *nb,
if (ret)
dev_err(dev, "failed to add to power domain: %d\n",
ret);
+ imx6q_pm_clk_add(dev);
break;
case BUS_NOTIFY_UNBOUND_DRIVER:
genpd = dev_to_genpd(dev);
@@ -246,6 +319,7 @@ static int imx6q_pm_notifier_call(struct notifier_block *nb,
if (ret)
dev_err(dev, "failed to remove from power domain: %d\n",
ret);
+ imx6q_pm_clk_remove(dev);
break;
}
--
1.8.5.3
^ permalink raw reply related
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