* [PATCH v3 0/3] exynos: arch: add support for exynos5260 SoC
From: Rahul Sharma @ 2014-02-14 13:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Rahul Sharma <Rahul.Sharma@samsung.com>
V3:
1) Addressed review comments from Tomasz figa.
V2:
1) Split up DT patch into SoC and Board patch.
This series is dependent on Sachin's patch
"ARM: EXYNOS: Consolidate CPU init code" at
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/26560
This series is based on Kukjin's for-next branch at
http://git.kernel.org/?p=linux/kernel/git/kgene/linux-samsung.git
Pankaj Dubey (1):
ARM: EXYNOS: initial board support for exynos5260 SoC
Rahul Sharma (2):
ARM: dts: add dts files for exynos5260 SoC
ARM: dts: add dts files for xyref5260 board
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 574 +++++++++++++++++++++++
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 105 +++++
arch/arm/boot/dts/exynos5260.dtsi | 304 ++++++++++++
arch/arm/mach-exynos/Kconfig | 9 +
arch/arm/mach-exynos/common.c | 11 +
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8 +
9 files changed, 1014 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
--
1.7.9.5
^ permalink raw reply
* [PATCH v3 1/3] ARM: EXYNOS: initial board support for exynos5260 SoC
From: Rahul Sharma @ 2014-02-14 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392385032-22015-1-git-send-email-rahul.sharma@samsung.com>
From: Pankaj Dubey <pankaj.dubey@samsung.com>
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 9 +++++++++
arch/arm/mach-exynos/common.c | 11 +++++++++++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
5 files changed, 30 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c414af..5c96248 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -91,6 +91,15 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5260
+ bool "SAMSUNG EXYNOS5260"
+ default y
+ depends on ARCH_EXYNOS5
+ select AUTO_ZRELADDR
+ select SAMSUNG_DMADEV
+ help
+ Enable EXYNOS5260 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index bab52ca..02b142d 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -176,6 +176,15 @@ static struct map_desc exynos5250_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5260_iodesc[] __initdata = {
+ {
+ .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn = __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
@@ -326,6 +335,8 @@ static void __init exynos_map_io(void)
iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5260())
+ iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..bd6fa02 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
+#define EXYNOS5260_PA_SYSRAM_NS 0x02073000
#define EXYNOS_PA_CHIPID 0x10000000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 65a4646..18aee57 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5260",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb3..60687aa 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
+#define EXYNOS5260_SOC_ID 0xE5260000
#define EXYNOS5420_SOC_ID 0xE5420000
#define EXYNOS5440_SOC_ID 0xE5440000
#define EXYNOS5_SOC_MASK 0xFFFFF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5260, EXYNOS5260_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
@@ -148,6 +150,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos5250() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5260)
+# define soc_is_exynos5260() is_samsung_exynos5260()
+#else
+# define soc_is_exynos5260() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 2/3] ARM: dts: add dts files for exynos5260 SoC
From: Rahul Sharma @ 2014-02-14 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392385032-22015-1-git-send-email-rahul.sharma@samsung.com>
The patch adds the dts files for exynos5260.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 574 +++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5260.dtsi | 304 +++++++++++++++
2 files changed, 878 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
new file mode 100644
index 0000000..f6ee55e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -0,0 +1,574 @@
+/*
+ * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define PIN_PULL_NONE 0
+#define PIN_PULL_DOWN 1
+#define PIN_PULL_UP 3
+
+&pinctrl_0 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb3: gpb3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb5: gpb5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk0: gpk0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx3: gpx3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart0_data: uart0-data {
+ samsung,pins = "gpa0-0", "gpa0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = "gpa0-2", "gpa0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-4", "gpa1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ usb3_vbus0_en: usb3-vbus0-en {
+ samsung,pins = "gpa2-4";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2s1_bus: i2s1-bus {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+ "gpb0-4";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ pcm1_bus: pcm1-bus {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+ "gpb0-4";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ spdif1_bus: spdif1-bus {
+ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2";
+ samsung,pin-function = <4>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c0_hs_bus: i2c0-hs-bus {
+ samsung,pins = "gpb3-0", "gpb3-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c1_hs_bus: i2c1-hs-bus {
+ samsung,pins = "gpb3-2", "gpb3-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c2_hs_bus: i2c2-hs-bus {
+ samsung,pins = "gpb3-4", "gpb3-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c3_hs_bus: i2c3-hs-bus {
+ samsung,pins = "gpb3-6", "gpb3-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c4_bus: i2c4-bus {
+ samsung,pins = "gpb4-0", "gpb4-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c5_bus: i2c5-bus {
+ samsung,pins = "gpb4-2", "gpb4-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c6_bus: i2c6-bus {
+ samsung,pins = "gpb4-4", "gpb4-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c7_bus: i2c7-bus {
+ samsung,pins = "gpb4-6", "gpb4-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c8_bus: i2c8-bus {
+ samsung,pins = "gpb5-0", "gpb5-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c9_bus: i2c9-bus {
+ samsung,pins = "gpb5-2", "gpb5-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c10_bus: i2c10-bus {
+ samsung,pins = "gpb5-4", "gpb5-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c11_bus: i2c11-bus {
+ samsung,pins = "gpb5-6", "gpb5-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_gpio_a: cam-gpio-a {
+ samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
+ "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
+ "gpe1-0", "gpe1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_gpio_b: cam-gpio-b {
+ samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
+ "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_i2c1_bus: cam-i2c1-bus {
+ samsung,pins = "gpf0-2", "gpf0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_i2c0_bus: cam-i2c0-bus {
+ samsung,pins = "gpf0-0", "gpf0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_spi0_bus: cam-spi0-bus {
+ samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ cam_spi1_bus: cam-spi1-bus {
+ samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&pinctrl_1 {
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc4: gpc4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd0_clk: sd0-clk {
+ samsung,pins = "gpc0-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_cmd: sd0-cmd {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus1: sd0-bus-width1 {
+ samsung,pins = "gpc0-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus8: sd0-bus-width8 {
+ samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_rdqs: sd0-rdqs {
+ samsung,pins = "gpc0-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_clk: sd1-clk {
+ samsung,pins = "gpc1-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pins = "gpc1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pins = "gpc1-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_bus8: sd1-bus-width8 {
+ samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpc2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpc2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpc2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpc2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+};
+
+&pinctrl_2 {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
new file mode 100644
index 0000000..876e23f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -0,0 +1,304 @@
+/*
+ * SAMSUNG EXYNOS5260 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/clk/exynos5260-clk.h>
+
+/ {
+ compatible = "samsung,exynos5260";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_0;
+ pinctrl1 = &pinctrl_1;
+ pinctrl2 = &pinctrl_2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ cci-control-port = <&cci_control1>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ cci-control-port = <&cci_control1>;
+ };
+
+ cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cci-control-port = <&cci_control0>;
+ };
+
+ cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cci-control-port = <&cci_control0>;
+ };
+
+ cpu at 102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ cci-control-port = <&cci_control0>;
+ };
+
+ cpu at 103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ cci-control-port = <&cci_control0>;
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clock_top: clock-controller at 10010000 {
+ compatible = "samsung,exynos5260-clock-top";
+ reg = <0x10010000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_peri: clock-controller at 10200000 {
+ compatible = "samsung,exynos5260-clock-peri";
+ reg = <0x10200000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_egl: clock-controller at 10600000 {
+ compatible = "samsung,exynos5260-clock-egl";
+ reg = <0x10600000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_kfc: clock-controller at 10700000 {
+ compatible = "samsung,exynos5260-clock-kfc";
+ reg = <0x10700000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_g2d: clock-controller at 10A00000 {
+ compatible = "samsung,exynos5260-clock-g2d";
+ reg = <0x10A00000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_mif: clock-controller at 10CE0000 {
+ compatible = "samsung,exynos5260-clock-mif";
+ reg = <0x10CE0000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_mfc: clock-controller at 11090000 {
+ compatible = "samsung,exynos5260-clock-mfc";
+ reg = <0x11090000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_g3d: clock-controller at 11830000 {
+ compatible = "samsung,exynos5260-clock-g3d";
+ reg = <0x11830000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_fsys: clock-controller at 122E0000 {
+ compatible = "samsung,exynos5260-clock-fsys";
+ reg = <0x122E0000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_aud: clock-controller at 128C0000 {
+ compatible = "samsung,exynos5260-clock-aud";
+ reg = <0x128C0000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_isp: clock-controller at 133C0000 {
+ compatible = "samsung,exynos5260-clock-isp";
+ reg = <0x133C0000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_gscl: clock-controller at 13F00000 {
+ compatible = "samsung,exynos5260-clock-gscl";
+ reg = <0x13F00000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ clock_disp: clock-controller at 14550000 {
+ compatible = "samsung,exynos5260-clock-disp";
+ reg = <0x14550000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller at 10481000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-controller;
+ reg = <0x10481000 0x1000>,
+ <0x10482000 0x1000>,
+ <0x10484000 0x2000>,
+ <0x10486000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ chipid: chipid at 10000000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ mct: mct at 100B0000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x100B0000 0x1000>;
+ clocks = <&clock_top FIN_PLL>, <&clock_peri PERI_CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+ interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
+ <0 107 0>, <0 122 0>, <0 123 0>,
+ <0 124 0>, <0 125 0>, <0 126 0>,
+ <0 127 0>, <0 128 0>, <0 129 0>;
+ };
+
+ cci: cci at 10F00000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x10F00000 0x1000>;
+ ranges = <0x0 0x10F00000 0x6000>;
+
+ cci_control0: slave-if at 4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control1: slave-if at 5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+ };
+
+ pinctrl_0: pinctrl at 11600000 {
+ compatible = "samsung,exynos5260-pinctrl";
+ reg = <0x11600000 0x1000>;
+ interrupts = <0 79 0>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos4210-wakeup-eint";
+ interrupt-parent = <&gic>;
+ interrupts = <0 32 0>;
+ };
+ };
+
+ pinctrl_1: pinctrl at 12290000 {
+ compatible = "samsung,exynos5260-pinctrl";
+ reg = <0x12290000 0x1000>;
+ interrupts = <0 157 0>;
+ };
+
+ pinctrl_2: pinctrl at 128B0000 {
+ compatible = "samsung,exynos5260-pinctrl";
+ reg = <0x128B0000 0x1000>;
+ interrupts = <0 243 0>;
+ };
+
+ uart0: serial at 12C00000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C00000 0x100>;
+ interrupts = <0 146 0>;
+ clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ uart1: serial at 12C10000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C10000 0x100>;
+ interrupts = <0 147 0>;
+ clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ uart2: serial at 12C20000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C20000 0x100>;
+ interrupts = <0 148 0>;
+ clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ uart3: serial at 12860000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12860000 0x100>;
+ interrupts = <0 145 0>;
+ clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ mmc_0: mmc0 at 12140000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12140000 0x2000>;
+ interrupts = <0 156 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <64>;
+ status = "disabled";
+ };
+
+ mmc_1: mmc1 at 12150000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12150000 0x2000>;
+ interrupts = <0 158 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <64>;
+ status = "disabled";
+ };
+
+ mmc_2: mmc2 at 12160000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12160000 0x2000>;
+ interrupts = <0 159 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <64>;
+ status = "disabled";
+ };
+ };
+};
+
+#include "exynos5260-pinctrl.dtsi"
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 3/3] ARM: dts: add dts files for xyref5260 board
From: Rahul Sharma @ 2014-02-14 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392385032-22015-1-git-send-email-rahul.sharma@samsung.com>
The patch adds the dts files for xyref5260 board which
is based on Exynos5260 Evt0 sample.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 105 +++++++++++++++++++++++
2 files changed, 106 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fa70ea2..c513a69 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -64,6 +64,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5260-xyref5260-evt0.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
new file mode 100644
index 0000000..c4efc1e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
@@ -0,0 +1,105 @@
+/*
+ * SAMSUNG XYREF5260 EVT0 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5260.dtsi"
+
+/ {
+ model = "SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260";
+ compatible = "samsung,xyref5260", "samsung,exynos5260";
+
+ memory {
+ reg = <0x20000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fin_pll: oscillator at 0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+ };
+};
+
+&pinctrl_0 {
+ hdmi_hpd_irq: hdmi-hpd-irq {
+ samsung,pins = "gpx3-7";
+ samsung,pin-function = <0>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ supports-hs200-mode; /* 200 Mhz */
+ fifo-depth = <0x40>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+
+ slot at 0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+};
+
+&mmc_2 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ fifo-depth = <0x40>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+
+ slot at 0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3] input: sirfsoc-onkey - report onkey untouch event by detecting pin status
From: Barry Song @ 2014-02-14 13:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <847BC5012124A94BB5CA1B26E022CCA3012BAFDC27@SHAASIEXM01.ASIA.ROOT.PRI>
>> Input: sirfsoc-onkey - implement open and close methods
>>
>> From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
>>
>> We can control whetehr device generates interrupts or not so let's
>> implement open and close methods of input device so that we do not do any
>> processing until there are users.
>>
>> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Tested-by: Xianglong Du <Xianglong.Du@csr.com>
Dmitry, will you push this one to your tree so that i can rebase others?
>> ---
>> drivers/input/misc/sirfsoc-onkey.c | 50 +++++++++++++++++++++++++++++-------
>> 1 file changed, 40 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/input/misc/sirfsoc-onkey.c b/drivers/input/misc/sirfsoc-onkey.c
>> index e8897c3..dc7db65 100644
>> --- a/drivers/input/misc/sirfsoc-onkey.c
>> +++ b/drivers/input/misc/sirfsoc-onkey.c
>> @@ -49,6 +49,35 @@ static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
>> return IRQ_HANDLED;
>> }
>>
>> +static void sirfsoc_pwrc_toggle_interrupts(struct sirfsoc_pwrc_drvdata *pwrcdrv,
>> + bool enable)
>> +{
>> + u32 int_mask;
>> +
>> + int_mask = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK);
>> + if (enable)
>> + int_mask |= PWRC_ON_KEY_BIT;
>> + else
>> + int_mask &= ~PWRC_ON_KEY_BIT;
>> + sirfsoc_rtc_iobrg_writel(int_mask, pwrcdrv->pwrc_base + PWRC_INT_MASK);
>> +}
>> +
>> +static int sirfsoc_pwrc_open(struct input_dev *input)
>> +{
>> + struct sirfsoc_pwrc_drvdata *pwrcdrv = input_get_drvdata(input);
>> +
>> + sirfsoc_pwrc_toggle_interrupts(pwrcdrv, true);
>> +
>> + return 0;
>> +}
>> +
>> +static void sirfsoc_pwrc_close(struct input_dev *input)
>> +{
>> + struct sirfsoc_pwrc_drvdata *pwrcdrv = input_get_drvdata(input);
>> +
>> + sirfsoc_pwrc_toggle_interrupts(pwrcdrv, false);
>> +}
>> +
>> static const struct of_device_id sirfsoc_pwrc_of_match[] = {
>> { .compatible = "sirf,prima2-pwrc" },
>> {},
>> @@ -70,7 +99,7 @@ static int sirfsoc_pwrc_probe(struct platform_device *pdev)
>> }
>>
>> /*
>> - * we can't use of_iomap because pwrc is not mapped in memory,
>> + * We can't use of_iomap because pwrc is not mapped in memory,
>> * the so-called base address is only offset in rtciobrg
>> */
>> error = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);
>> @@ -88,6 +117,11 @@ static int sirfsoc_pwrc_probe(struct platform_device *pdev)
>> pwrcdrv->input->phys = "pwrc/input0";
>> pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR);
>>
>> + pwrcdrv->input->open = sirfsoc_pwrc_open;
>> + pwrcdrv->input->close = sirfsoc_pwrc_close;
>> +
>> + input_set_drvdata(pwrcdrv->input, pwrcdrv);
>> +
>> irq = platform_get_irq(pdev, 0);
>> error = devm_request_irq(&pdev->dev, irq,
>> sirfsoc_pwrc_isr, IRQF_SHARED,
>> @@ -98,11 +132,6 @@ static int sirfsoc_pwrc_probe(struct platform_device *pdev)
>> return error;
>> }
>>
>> - sirfsoc_rtc_iobrg_writel(
>> - sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK) |
>> - PWRC_ON_KEY_BIT,
>> - pwrcdrv->pwrc_base + PWRC_INT_MASK);
>> -
>> error = input_register_device(pwrcdrv->input);
>> if (error) {
>> dev_err(&pdev->dev,
>> @@ -129,15 +158,16 @@ static int pwrc_resume(struct device *dev)
>> {
>> struct platform_device *pdev = to_platform_device(dev);
>> struct sirfsoc_pwrc_drvdata *pwrcdrv = platform_get_drvdata(pdev);
>> + struct input_dev *input = pwrcdrv->input;
>>
>> /*
>> * Do not mask pwrc interrupt as we want pwrc work as a wakeup source
>> * if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
>> */
>> - sirfsoc_rtc_iobrg_writel(
>> - sirfsoc_rtc_iobrg_readl(
>> - pwrcdrv->pwrc_base + PWRC_INT_MASK) | PWRC_ON_KEY_BIT,
>> - pwrcdrv->pwrc_base + PWRC_INT_MASK);
>> + mutex_lock(&input->mutex);
>> + if (input->users)
>> + sirfsoc_pwrc_toggle_interrupts(pwrcdrv, true);
>> + mutex_unlock(&input->mutex);
>>
>> return 0;
>> }
>
> -barry
-barry
^ permalink raw reply
* [PATCH 1/8] clk: divider: fix rate calculation for fractional rates
From: Tero Kristo @ 2014-02-14 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392285846-13199-2-git-send-email-tomi.valkeinen@ti.com>
On 02/13/2014 12:03 PM, Tomi Valkeinen wrote:
> clk-divider.c does not calculate the rates consistently at the moment.
>
> As an example, on OMAP3 we have a clock divider with a source clock of
> 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are:
>
> 6: 144000000
> 7: 123428571.428571...
> 8: 108000000
>
> Calling clk_round_rate() with the rate in the first column will give the
> rate in the second column:
>
> 144000000 -> 144000000
> 143999999 -> 123428571
> 123428572 -> 123428571
> 123428571 -> 108000000
>
> Note how clk_round_rate() returns 123428571 for rates from 123428572 to
> 143999999, which is mathematically correct, but when clk_round_rate() is
> called with 123428571, the returned value is surprisingly 108000000.
>
> This means that the following code works a bit oddly:
>
> rate = clk_round_rate(clk, 123428572);
> clk_set_rate(clk, rate);
>
> As clk_set_rate() also does clock rate rounding, the result is that the
> clock is set to the rate of 108000000, not 123428571 returned by the
> clk_round_rate.
>
> This patch changes the clk-divider.c to use DIV_ROUND_UP when
> calculating the rate. This gives the following behavior which fixes the
> inconsistency:
>
> 144000000 -> 144000000
> 143999999 -> 123428572
> 123428572 -> 123428572
> 123428571 -> 108000000
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> ---
> drivers/clk/clk-divider.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 5543b7df8e16..ec22112e569f 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -24,7 +24,7 @@
> * Traits of this clock:
> * prepare - clk_prepare only ensures that parents are prepared
> * enable - clk_enable only ensures that parents are enabled
> - * rate - rate is adjustable. clk->rate = parent->rate / divisor
> + * rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor)
> * parent - fixed parent. No clk_set_parent support
> */
>
> @@ -115,7 +115,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> return parent_rate;
> }
>
> - return parent_rate / div;
> + return DIV_ROUND_UP(parent_rate, div);
> }
>
> /*
> @@ -185,7 +185,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
> }
> parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
> MULT_ROUND_UP(rate, i));
> - now = parent_rate / i;
> + now = DIV_ROUND_UP(parent_rate, i);
> if (now <= rate && now > best) {
> bestdiv = i;
> best = now;
> @@ -207,7 +207,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> int div;
> div = clk_divider_bestdiv(hw, rate, prate);
>
> - return *prate / div;
> + return DIV_ROUND_UP(*prate, div);
> }
>
> static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
> @@ -218,7 +218,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
> unsigned long flags = 0;
> u32 val;
>
> - div = parent_rate / rate;
> + div = DIV_ROUND_UP(parent_rate, rate);
> value = _get_val(divider, div);
>
> if (value > div_mask(divider))
>
Basically the patch looks good to me, but it might be good to have a
testing round of sort with this. It can potentially cause regressions on
multiple boards if the drivers happen to rely on the "broken" clock
rates. Same for patch #2 which is a copy paste of this one, but only
impacts TI boards.
-Tero
^ permalink raw reply
* [PATCH 26/27] ARM: shmobile: lager-reference: Enable CMT0 in device tree
From: Sergei Shtylyov @ 2014-02-14 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392339605-20691-27-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Hello.
On 14-02-2014 5:00, Laurent Pinchart wrote:
> Enable the CMT0 device and configure channel 0 as a clock event
> provider.
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
> index 0b95bab..62b31f3 100644
> --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
> +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
> @@ -29,7 +29,6 @@ enum {
> };
>
> void r8a7790_add_standard_devices(void);
> -void r8a7790_add_dt_devices(void);
> void r8a7790_clock_init(void);
> void r8a7790_pinmux_init(void);
> void r8a7790_pm_init(void);
> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
> index 3e5813f..462c81f 100644
> --- a/arch/arm/mach-shmobile/setup-r8a7790.c
> +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> @@ -294,11 +294,6 @@ static struct resource cmt0_resources[] = {
> &cmt##idx##_platform_data, \
> sizeof(struct sh_timer_config))
>
> -void __init r8a7790_add_dt_devices(void)
> -{
> - r8a7790_register_cmt(0);
> -}
> -
> void __init r8a7790_add_standard_devices(void)
> {
> r8a7790_register_scif(0);
> @@ -311,7 +306,7 @@ void __init r8a7790_add_standard_devices(void)
> r8a7790_register_scif(7);
> r8a7790_register_scif(8);
> r8a7790_register_scif(9);
> - r8a7790_add_dt_devices();
> + r8a7790_register_cmt(0);
> r8a7790_register_irqc(0);
> r8a7790_register_thermal();
> }
IMHO, these 2 files should be split into a separate patch.
WBR, Sergei
^ permalink raw reply
* [PATCH 27/27] ARM: shmobile: koelsch-reference: Enable CMT0 in device tree
From: Sergei Shtylyov @ 2014-02-14 13:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392339605-20691-28-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Hello.
On 14-02-2014 5:00, Laurent Pinchart wrote:
> Enable the CMT0 device and configure channel 0 as a clock event
> provider.
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> arch/arm/boot/dts/r8a7791-koelsch.dts | 9 +++++++++
> arch/arm/mach-shmobile/board-koelsch-reference.c | 15 +--------------
> arch/arm/mach-shmobile/include/mach/r8a7791.h | 1 -
> arch/arm/mach-shmobile/setup-r8a7791.c | 7 +------
The latter 2 files are worth splitting into a separate patch as well...
> 4 files changed, 11 insertions(+), 21 deletions(-)
WBR, Sergei
^ permalink raw reply
* [PATCH 0/6] ARM: integrator: multiplatform advancements
From: Russell King - ARM Linux @ 2014-02-14 13:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392373771-17303-1-git-send-email-linus.walleij@linaro.org>
On Fri, Feb 14, 2014 at 11:29:25AM +0100, Linus Walleij wrote:
> The *real* solution, one might argue is to convert the CLCD
> driver to DRM and add device tree bindings, but it appears that
> this is an orthogonal goal that has been attempted by other with
> mixed results.
What mixed results? You know, I find it rather sick that people run
around trying to do this to a driver that I authored and maintain
without one comment to me about it. It sometimes feels like people
think I don't exist anymore.
The biggest complaint I've heard against DRM is the amount of code
required. That's partly because we haven't - until now - had a good
way to separate the "connectors" as stand-alone implementations separate
from the core DRM drivers. I'm hopeful that by 3.15, we will see some
implementations (imx-drm and armada) start making use of this.
Also, remember that DRM is Direct Rendering Manager, which incorporates
Kernel Mode Setting. It's the KMS part which is most relevant to things
like CLCD since it has no GPU. However, the non-KMS bits also are when
you have something like a Mali GPU or other GPU.
We /really/ need these GPUs to move over to DRM - any ARM platform using
a GPU today is inherently insecure since they all have been coded to push
physical addresses around everywhere, which basically means userspace can
use the GPU to access parts of the system such as overwriting bits of the
kernel.
It's useless write-protecting the vectors page and/or the kernel text in
a vain attempt to provide additional security if the GPU can be used from
userspace to write to that RAM.
Having everything under DRM eliminates that problem because userspace only
gets to deal with handles to the various buffers rather than physical
addresses, which ensures that you can't specify an address for a buffer
you don't own.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* [PATCH 1/2] mfd: twl4030-madc: Add devicetree support.
From: Lee Jones @ 2014-02-14 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392383861-14169-1-git-send-email-marek@goldelico.com>
> Signed-off-by: Marek Belisko <marek@goldelico.com>
> ---
> .../devicetree/bindings/mfd/twl4030-madc.txt | 18 +++++++++++++
> drivers/mfd/twl4030-madc.c | 31
> ++++++++++++++++++++--
Please separate these into different patches.
> 2 files changed, 47 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mfd/twl4030-madc.txt
<snip>
> +++ b/drivers/mfd/twl4030-madc.c
> @@ -695,6 +695,29 @@ static int twl4030_madc_set_power(struct twl4030_madc_data *madc, int on)
> return 0;
> }
>
> +#ifdef CONFIG_OF
I believe we're heading for a more:
if (IS_ENABLED(CONFIG_OF))
... approach. I won't enforce it, but please consider using it.
> +static struct twl4030_madc_platform_data *
> + twl4030_madc_of_parse(struct platform_device *pdev)
> +{
> + struct twl4030_madc_platform_data *pdata;
> +
> + pdata = devm_kzalloc(&pdev->dev,
> + sizeof(struct twl4030_madc_platform_data), GFP_KERNEL);
s/struct twl4030_madc_platform_data/*pdata/
> + if (!pdata)
> + return ERR_PTR(-ENOMEM);
> +
> + pdata->irq_line = platform_get_irq(pdev, 0);
Why weren't 'resources' used in the original implementation?
> + return pdata;
> +}
> +
> +static const struct of_device_id twl4030_madc_dt_match_table[] = {
> + { .compatible = "ti,twl4030-madc" },
> + {},
> +};
> +
> +#endif
> +
> /*
> * Initialize MADC and request for threaded irq
> */
> @@ -706,8 +729,11 @@ static int twl4030_madc_probe(struct platform_device *pdev)
> u8 regval;
>
> if (!pdata) {
> - dev_err(&pdev->dev, "platform_data not available\n");
> - return -EINVAL;
> + pdata = twl4030_madc_of_parse(pdev);
> + if (!pdata) {
And if you received -ENOMEM?
> + dev_err(&pdev->dev, "platform_data not available\n");
> + return -EINVAL;
> + }
> }
> madc = kzalloc(sizeof(*madc), GFP_KERNEL);
> if (!madc)
> @@ -807,6 +833,7 @@ static struct platform_driver twl4030_madc_driver = {
> .driver = {
> .name = "twl4030_madc",
> .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(twl4030_madc_dt_match_table),
> },
> };
>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 4/8] ARM: dts: fix omap3 dss clock handle names
From: Tero Kristo @ 2014-02-14 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392285846-13199-5-git-send-email-tomi.valkeinen@ti.com>
On 02/13/2014 12:04 PM, Tomi Valkeinen wrote:
> The DSS fclk and iclk handles are named differently on OMAP3430 ES1 than
> on later OMAP revisions. The ES1 has handles 'dss1_alwon_fck_3430es1'
> and 'dss_ick_3430es1', whereas later revisions have similar names but
> ending with 'es2'.
>
> This means we don't have one clock handle to which we could refer to
> when defining the DSS clocks.
>
> However, as the namespaces are separate for ES1 and ES2+ OMAPs, we can
> just rename the handles to 'dss1_alwon_fck' and 'dss_ick' for both ES1
> and ES2+, removing the issue.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
> ---
> arch/arm/boot/dts/omap3430es1-clocks.dtsi | 6 +++---
> arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
> index 02f6c7fabbec..f9202656168f 100644
> --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
> @@ -152,7 +152,7 @@
> clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
> };
>
> - dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
> + dss1_alwon_fck: dss1_alwon_fck_3430es1 {
> #clock-cells = <0>;
> compatible = "ti,gate-clock";
> clocks = <&dpll4_m4x2_ck>;
> @@ -161,7 +161,7 @@
> ti,set-rate-parent;
> };
>
> - dss_ick_3430es1: dss_ick_3430es1 {
> + dss_ick: dss_ick_3430es1 {
> #clock-cells = <0>;
> compatible = "ti,omap3-no-wait-interface-clock";
> clocks = <&l4_ick>;
> @@ -184,7 +184,7 @@
> dss_clkdm: dss_clkdm {
> compatible = "ti,clockdomain";
> clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
> - <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
> + <&dss1_alwon_fck>, <&dss_ick>;
> };
>
> d2d_clkdm: d2d_clkdm {
> diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
> index af9ae5346bf2..080fb3f4e429 100644
> --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
> @@ -160,7 +160,7 @@
> ti,bit-shift = <30>;
> };
>
> - dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
> + dss1_alwon_fck: dss1_alwon_fck_3430es2 {
> #clock-cells = <0>;
> compatible = "ti,dss-gate-clock";
> clocks = <&dpll4_m4x2_ck>;
> @@ -169,7 +169,7 @@
> ti,set-rate-parent;
> };
>
> - dss_ick_3430es2: dss_ick_3430es2 {
> + dss_ick: dss_ick_3430es2 {
> #clock-cells = <0>;
> compatible = "ti,omap3-dss-interface-clock";
> clocks = <&l4_ick>;
> @@ -216,7 +216,7 @@
> dss_clkdm: dss_clkdm {
> compatible = "ti,clockdomain";
> clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
> - <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
> + <&dss1_alwon_fck>, <&dss_ick>;
> };
>
> core_l4_clkdm: core_l4_clkdm {
>
^ permalink raw reply
* [PATCH 26/27] ARM: shmobile: lager-reference: Enable CMT0 in device tree
From: Laurent Pinchart @ 2014-02-14 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FE1E14.5090400@cogentembedded.com>
Hi Sergei,
Thank you for the review.
On Friday 14 February 2014 17:45:56 Sergei Shtylyov wrote:
> On 14-02-2014 5:00, Laurent Pinchart wrote:
> > Enable the CMT0 device and configure channel 0 as a clock event
> > provider.
> >
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com>
> >
> > diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h
> > b/arch/arm/mach-shmobile/include/mach/r8a7790.h index 0b95bab..62b31f3
> > 100644
> > --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
> > +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
> > @@ -29,7 +29,6 @@ enum {
> > };
> >
> > void r8a7790_add_standard_devices(void);
> > -void r8a7790_add_dt_devices(void);
> > void r8a7790_clock_init(void);
> > void r8a7790_pinmux_init(void);
> > void r8a7790_pm_init(void);
> > diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c
> > b/arch/arm/mach-shmobile/setup-r8a7790.c index 3e5813f..462c81f 100644
> > --- a/arch/arm/mach-shmobile/setup-r8a7790.c
> > +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
> > @@ -294,11 +294,6 @@ static struct resource cmt0_resources[] = {
> > &cmt##idx##_platform_data, \
> > sizeof(struct sh_timer_config))
> >
> > -void __init r8a7790_add_dt_devices(void)
> > -{
> > - r8a7790_register_cmt(0);
> > -}
> > -
> > void __init r8a7790_add_standard_devices(void)
> > {
> > r8a7790_register_scif(0);
> > @@ -311,7 +306,7 @@ void __init r8a7790_add_standard_devices(void)
> > r8a7790_register_scif(7);
> > r8a7790_register_scif(8);
> > r8a7790_register_scif(9);
> > - r8a7790_add_dt_devices();
> > + r8a7790_register_cmt(0);
> > r8a7790_register_irqc(0);
> > r8a7790_register_thermal();
> > }
>
> IMHO, these 2 files should be split into a separate patch.
That could easily be done, but why ?
--
Regards,
Laurent Pinchart
^ permalink raw reply
* How to select between different display timings? (was: [PATCH 7/8] ARM: dts: tx28: restructure and update DTS file)
From: Dirk Behme @ 2014-02-14 13:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1375966287-6784-8-git-send-email-LW@KARO-electronics.de>
Hi Lothar and Shawn,
On 08.08.2013 14:51, Lothar Wa?mann wrote:
> - add Copyright header
> - use label references for better readability
> - sort the entries alphabetically
> - add some aliases used by U-Boot to edit the DT data
>
> Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
> ---
> arch/arm/boot/dts/imx28-tx28.dts | 693 +++++++++++++++++++++++++++++++++-----
> 1 files changed, 611 insertions(+), 82 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
> index 37be532..866af60 100644
> --- a/arch/arm/boot/dts/imx28-tx28.dts
> +++ b/arch/arm/boot/dts/imx28-tx28.dts
...
> +&lcdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &lcdif_ctrl_pins_a>;
> + lcd-supply = <®_lcd>;
> + display = <&display>;
> + status = "okay";
> +
> + display: display at 0 {
> + bits-per-pixel = <32>;
> + bus-width = <24>;
> +
> + display-timings {
> + native-mode = <&timing5>;
> + timing0: timing0 {
> + panel-name = "VGA";
> + clock-frequency = <25175000>;
> + hactive = <640>;
> + vactive = <480>;
> + hback-porch = <48>;
> + hsync-len = <96>;
> + hfront-porch = <16>;
> + vback-porch = <33>;
> + vsync-len = <2>;
> + vfront-porch = <10>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + pixelclk-active = <1>;
> + };
> +
> + timing1: timing1 {
> + panel-name = "ETV570";
> + clock-frequency = <25175000>;
> + hactive = <640>;
> + vactive = <480>;
> + hback-porch = <114>;
> + hsync-len = <30>;
> + hfront-porch = <16>;
> + vback-porch = <32>;
> + vsync-len = <3>;
> + vfront-porch = <10>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + pixelclk-active = <1>;
> + };
> +
> + timing2: timing2 {
> + panel-name = "ET0350";
> + clock-frequency = <6500000>;
> + hactive = <320>;
> + vactive = <240>;
> + hback-porch = <34>;
> + hsync-len = <34>;
> + hfront-porch = <20>;
> + vback-porch = <15>;
> + vsync-len = <3>;
> + vfront-porch = <4>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + pixelclk-active = <1>;
> + };
> +
> + timing3: timing3 {
> + panel-name = "ET0430";
> + clock-frequency = <9000000>;
> + hactive = <480>;
> + vactive = <272>;
> + hback-porch = <2>;
> + hsync-len = <41>;
> + hfront-porch = <2>;
> + vback-porch = <2>;
> + vsync-len = <10>;
> + vfront-porch = <2>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + pixelclk-active = <1>;
> + };
> +
> + timing4: timing4 {
> + panel-name = "ET0500", "ET0700";
> + clock-frequency = <33260000>;
> + hactive = <800>;
> + vactive = <480>;
> + hback-porch = <88>;
> + hsync-len = <128>;
> + hfront-porch = <40>;
> + vback-porch = <33>;
> + vsync-len = <2>;
> + vfront-porch = <10>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + pixelclk-active = <1>;
> + };
> +
> + timing5: timing5 {
> + panel-name = "ETQ570";
> + clock-frequency = <6400000>;
> + hactive = <320>;
> + vactive = <240>;
> + hback-porch = <38>;
> + hsync-len = <30>;
> + hfront-porch = <30>;
> + vback-porch = <16>;
> + vsync-len = <3>;
> + vfront-porch = <4>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + pixelclk-active = <1>;
> + };
> + };
> + };
> +};
Being no graphics expert, looking at above device tree change, I'd like
to understand how this can be used to switch between different display
timings?
In the kernel, I've found the code which selects the default/native-mode
(of_display_timing.c). But, as here, if there is a native/default mode,
there are alternative modes. I haven't understood how and who to select
these other modes? In this case, how could the alternative modes
timing0/1/2/3/4 be selected in the kernel?
Do you have any pointers regarding this?
Many thanks and best regards
Dirk
^ permalink raw reply
* [PATCH 5/8] ARM: dts: fix DPLL4 x2 clkouts on 3630
From: Tero Kristo @ 2014-02-14 13:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392285846-13199-6-git-send-email-tomi.valkeinen@ti.com>
On 02/13/2014 12:04 PM, Tomi Valkeinen wrote:
> OMAP3630 DPLL4 is different than on OMAP3430, in that it doesn't have
> the x2 multiplier for its outputs. This is not currently reflected in
> the clock DT data.
>
> Fix the issue by setting the clock multiplier to 1 (instead of 2) for the
> DPLL4 output clocks.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
> arch/arm/boot/dts/omap36xx-clocks.dtsi | 20 ++++++++++++++++++++
> arch/arm/boot/dts/omap36xx.dtsi | 2 +-
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
> index 2fcf253b677c..0b2df76b9d38 100644
> --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
> @@ -70,6 +70,26 @@
> };
> };
>
> +&dpll4_m2x2_mul_ck {
> + clock-mult = <1>;
> +};
> +
> +&dpll4_m3x2_mul_ck {
> + clock-mult = <1>;
> +};
> +
> +&dpll4_m4x2_mul_ck {
> + clock-mult = <1>;
> +};
> +
> +&dpll4_m5x2_mul_ck {
> + clock-mult = <1>;
> +};
> +
> +&dpll4_m6x2_mul_ck {
> + clock-mult = <1>;
> +};
> +
> &cm_clockdomains {
> dpll4_clkdm: dpll4_clkdm {
> compatible = "ti,clockdomain";
> diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
> index 7e8dee9175d6..5e1bcd06a996 100644
> --- a/arch/arm/boot/dts/omap36xx.dtsi
> +++ b/arch/arm/boot/dts/omap36xx.dtsi
> @@ -52,7 +52,7 @@
> };
> };
>
> -/include/ "omap36xx-clocks.dtsi"
> /include/ "omap34xx-omap36xx-clocks.dtsi"
> /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
> /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
> +/include/ "omap36xx-clocks.dtsi"
>
I think this re-ordering of the includes is unnecessary.
Other than that, the patch looks okay to me, so acked.
-Tero
^ permalink raw reply
* [PATCH 6/8] ARM: dts: use ti, fixed-factor-clock for dpll4_m4x2_mul_ck
From: Tero Kristo @ 2014-02-14 13:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392285846-13199-7-git-send-email-tomi.valkeinen@ti.com>
On 02/13/2014 12:04 PM, Tomi Valkeinen wrote:
> We need to use set-rate-parent for dpll4_m4 clock path, so use the
> ti,fixed-factor-clock version which supports set-rate-parent property.
.... you are talking about the flag but not introducing it in this
patch, maybe squash this + patch 7...?
-Tero
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
> arch/arm/boot/dts/omap36xx-clocks.dtsi | 2 +-
> arch/arm/boot/dts/omap3xxx-clocks.dtsi | 6 +++---
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
> index 0b2df76b9d38..6b5280d04a0e 100644
> --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
> @@ -79,7 +79,7 @@
> };
>
> &dpll4_m4x2_mul_ck {
> - clock-mult = <1>;
> + ti,clock-mult = <1>;
> };
>
> &dpll4_m5x2_mul_ck {
> diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
> index cb04d4b37e7f..df3c699a1893 100644
> --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
> @@ -425,10 +425,10 @@
>
> dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
> #clock-cells = <0>;
> - compatible = "fixed-factor-clock";
> + compatible = "ti,fixed-factor-clock";
> clocks = <&dpll4_m4_ck>;
> - clock-mult = <2>;
> - clock-div = <1>;
> + ti,clock-mult = <2>;
> + ti,clock-div = <1>;
> };
>
> dpll4_m4x2_ck: dpll4_m4x2_ck {
>
^ permalink raw reply
* [PATCH 7/8] ARM: dts: set 'ti,set-rate-parent' for dpll4_m4 path
From: Tero Kristo @ 2014-02-14 13:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392285846-13199-8-git-send-email-tomi.valkeinen@ti.com>
On 02/13/2014 12:04 PM, Tomi Valkeinen wrote:
> Set 'ti,set-rate-parent' property for clocks in the dpll4_m4 clock
> path, which is used for DSS functional clock. This fixes DSS driver's
> clock rate configuration, which needs the rate to be propagated properly
> to the divider node (dpll4_m4_ck).
... squash to #6?
-Tero
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
> arch/arm/boot/dts/omap3xxx-clocks.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
> index df3c699a1893..12be2b35dae9 100644
> --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
> @@ -429,6 +429,7 @@
> clocks = <&dpll4_m4_ck>;
> ti,clock-mult = <2>;
> ti,clock-div = <1>;
> + ti,set-rate-parent;
> };
>
> dpll4_m4x2_ck: dpll4_m4x2_ck {
> @@ -438,6 +439,7 @@
> ti,bit-shift = <0x1d>;
> reg = <0x0d00>;
> ti,set-bit-to-disable;
> + ti,set-rate-parent;
> };
>
> dpll4_m5_ck: dpll4_m5_ck {
>
^ permalink raw reply
* [PATCH] ARM: shmobile: lager: Add internal USB PCI support
From: Sergei Shtylyov @ 2014-02-14 13:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140214032948.3287.33351.sendpatchset@w520>
Hello.
On 14-02-2014 7:29, Magnus Damm wrote:
> From: Valentine Barshak <valentine.barshak@cogentembedded.com>
> This adds internal PCI USB host devices to R-Car H2 Lager board.
> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
> [damm at opensource.se: Rebased and reworked to only include USB1 and USB2]
> Signed-off-by: Magnus Damm <damm@opensource.se>
> ---
> Written against renesas-devel-v3.14-rc2-20140213
> arch/arm/mach-shmobile/board-lager.c | 50 ++++++++++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
> --- 0001/arch/arm/mach-shmobile/board-lager.c
> +++ work/arch/arm/mach-shmobile/board-lager.c 2014-02-14 12:16:26.000000000 +0900
> @@ -638,6 +638,48 @@ static struct resource sdhi2_resources[]
> DEFINE_RES_IRQ(gic_spi(167)),
> };
>
> +/* Internal PCI1 */
> +static const struct resource pci1_resources[] __initconst = {
> + DEFINE_RES_MEM(0xee0b0000, 0x10000), /* CFG */
> + DEFINE_RES_MEM(0xee0a0000, 0x10000), /* MEM */
> + DEFINE_RES_IRQ(gic_spi(112)),
> +};
> +
> +static const struct platform_device_info pci1_info __initconst = {
> + .parent = &platform_bus,
> + .name = "pci-rcar-gen2",
> + .id = 1,
> + .res = pci1_resources,
> + .num_res = ARRAY_SIZE(pci1_resources),
> + .dma_mask = DMA_BIT_MASK(32),
> +};
> +
> +static void __init lager_add_usb1_device(void)
Actually, this adds PCI device, not USB, so the name is strange.
Also, I doubt that such functions are really necessary.
> +{
> + platform_device_register_full(&pci1_info);
> +}
> +
> +/* Internal PCI2 */
> +static const struct resource pci2_resources[] __initconst = {
> + DEFINE_RES_MEM(0xee0d0000, 0x10000), /* CFG */
> + DEFINE_RES_MEM(0xee0c0000, 0x10000), /* MEM */
> + DEFINE_RES_IRQ(gic_spi(113)),
> +};
> +
> +static const struct platform_device_info pci2_info __initconst = {
> + .parent = &platform_bus,
> + .name = "pci-rcar-gen2",
> + .id = 2,
> + .res = pci2_resources,
> + .num_res = ARRAY_SIZE(pci2_resources),
> + .dma_mask = DMA_BIT_MASK(32),
> +};
> +
I suspect the PCI resources and info could be wrapped by macros and then
instantiated by using only 2 lines.
WBR, Sergei
^ permalink raw reply
* [PATCH RESEND] ARM: mcpm: Make all mcpm functions notrace
From: Dave Martin @ 2014-02-14 13:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392378721.3475.12.camel@linaro1.home>
On Fri, Feb 14, 2014 at 11:52:01AM +0000, Jon Medhurst (Tixy) wrote:
> On Thu, 2014-02-13 at 15:42 -0500, Nicolas Pitre wrote:
> > On Thu, 13 Feb 2014, Jon Medhurst (Tixy) wrote:
> >
> > > From: Dave Martin <dave.martin@linaro.org>
> > >
> > > The functions in mcpm_entry.c are mostly intended for use during
> > > scary cache and coherency disabling sequences, or do other things
> > > which confuse trace ... like powering a CPU down and not
> > > returning. Similarly for the backend code.
> > >
> > > For simplicity, this patch just makes whole files notrace.
> > > There should be more than enough traceable points on the paths to
> > > these functions, but we can be more fine-grained later if there is
> > > a need for it.
> > >
> > > Signed-off-by: Dave Martin <dave.martin@linaro.org>
> > >
> > > Also added spc.o to the list of files as it contains functions used by
> > > MCPM code which have comments comments like: "might be used in code
> > > paths where normal cacheable locks are not working"
> > >
> > > Signed-off-by: Jon Medhurst <tixy@linaro.org>
> >
> > Acked-by: Nicolas Pitre <nico@linaro.org>
> >
> > Please send to RMK's patch system.
>
> Thanks, added as patch 7962/2 [1]. (My first attempt accidentally
> omitted the "From: Dave Martin" line - I hope the patch system
> understands such lines).
I won't lost sleep over it if not...
I'd forgotten about this patch, to be honest.
Cheers
---Dave
^ permalink raw reply
* [PATCH 7/8] ARM: dts: set 'ti,set-rate-parent' for dpll4_m4 path
From: Tomi Valkeinen @ 2014-02-14 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FE2020.2010601@ti.com>
On 14/02/14 15:54, Tero Kristo wrote:
> On 02/13/2014 12:04 PM, Tomi Valkeinen wrote:
>> Set 'ti,set-rate-parent' property for clocks in the dpll4_m4 clock
>> path, which is used for DSS functional clock. This fixes DSS driver's
>> clock rate configuration, which needs the rate to be propagated properly
>> to the divider node (dpll4_m4_ck).
>
>
> ... squash to #6?
I got no problem with that, but I think it's cleaner to separate these
two things. #6 converts the clock to use a different driver, and by
having these separate, it's easier to see that #6 converts the node 1:1
without other functional change.
Tomi
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 901 bytes
Desc: OpenPGP digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140214/74d12cda/attachment.sig>
^ permalink raw reply
* [PATCH v2 1/9] ARM: centralize common multi-platform kconfig options
From: Rob Herring @ 2014-02-14 14:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdb5DzXbFV=mH24HuyGQ91OjPYx5=bMeNSb+xQ8q4epGiA@mail.gmail.com>
On Fri, Feb 14, 2014 at 4:40 AM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Tue, Feb 11, 2014 at 10:11 PM, Rob Herring <robherring2@gmail.com> wrote:
>
>> From: Rob Herring <robh@kernel.org>
>>
>> Multi-platform requires various kconfig options to be selected, so
>> platforms don't need to select them individually.
>>
>> Signed-off-by: Rob Herring <robh@kernel.org>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: Russell King <linux@arm.linux.org.uk>
>
> OK makes sense. Maybe a bit unintuitive that multiplat
> make gpiolib wanted optional and then platforms override
> this by requiring it, but whatever, I cannot think of anything
> better.
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
It's really just about making gpiolib visible. Can we just kill the
symbol or there are still non-gpiolib users that would conflict?
Rob
^ permalink raw reply
* How to select between different display timings? (was: [PATCH 7/8] ARM: dts: tx28: restructure and update DTS file)
From: Lothar Waßmann @ 2014-02-14 14:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FE1F2D.4010102@de.bosch.com>
Hi,
Dirk Behme wrote:
> Hi Lothar and Shawn,
>
> On 08.08.2013 14:51, Lothar Wa?mann wrote:
> > - add Copyright header
> > - use label references for better readability
> > - sort the entries alphabetically
> > - add some aliases used by U-Boot to edit the DT data
> >
> > Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
> > ---
> > arch/arm/boot/dts/imx28-tx28.dts | 693 +++++++++++++++++++++++++++++++++-----
> > 1 files changed, 611 insertions(+), 82 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
> > index 37be532..866af60 100644
> > --- a/arch/arm/boot/dts/imx28-tx28.dts
> > +++ b/arch/arm/boot/dts/imx28-tx28.dts
> ...
> > +&lcdif {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &lcdif_ctrl_pins_a>;
> > + lcd-supply = <®_lcd>;
> > + display = <&display>;
> > + status = "okay";
> > +
> > + display: display at 0 {
> > + bits-per-pixel = <32>;
> > + bus-width = <24>;
> > +
> > + display-timings {
> > + native-mode = <&timing5>;
^^^^^^^^^^^^^^^^^^^^^^^^^
> > + timing0: timing0 {
[...]
> > + };
> > + };
> > + };
> > +};
>
> Being no graphics expert, looking at above device tree change, I'd like
> to understand how this can be used to switch between different display
> timings?
>
> In the kernel, I've found the code which selects the default/native-mode
> (of_display_timing.c). But, as here, if there is a native/default mode,
> there are alternative modes. I haven't understood how and who to select
> these other modes? In this case, how could the alternative modes
> timing0/1/2/3/4 be selected in the kernel?
>
> Do you have any pointers regarding this?
>
You need to set the property 'native-mode' to the phandle of the
display-timings entry like marked above.
Lothar Wa?mann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________
^ permalink raw reply
* [PATCH 6/8] ARM: dts: use ti, fixed-factor-clock for dpll4_m4x2_mul_ck
From: Tomi Valkeinen @ 2014-02-14 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FE2001.1020906@ti.com>
On 14/02/14 15:54, Tero Kristo wrote:
> On 02/13/2014 12:04 PM, Tomi Valkeinen wrote:
>> We need to use set-rate-parent for dpll4_m4 clock path, so use the
>> ti,fixed-factor-clock version which supports set-rate-parent property.
>
>
> .... you are talking about the flag but not introducing it in this
> patch, maybe squash this + patch 7...?
Hmm, yes, I should mention that the flag itself is set in a following patch.
Tomi
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 901 bytes
Desc: OpenPGP digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140214/bb600c28/attachment.sig>
^ permalink raw reply
* [PATCH 26/27] ARM: shmobile: lager-reference: Enable CMT0 in device tree
From: Sergei Shtylyov @ 2014-02-14 14:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2244047.l1cecWDdMU@avalon>
On 14-02-2014 17:48, Laurent Pinchart wrote:
>>> Enable the CMT0 device and configure channel 0 as a clock event
>>> provider.
>>> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>>> diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h
>>> b/arch/arm/mach-shmobile/include/mach/r8a7790.h index 0b95bab..62b31f3 100644
>>> --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
>>> +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
>>> @@ -29,7 +29,6 @@ enum {
>>> };
>>>
>>> void r8a7790_add_standard_devices(void);
>>> -void r8a7790_add_dt_devices(void);
>>> void r8a7790_clock_init(void);
>>> void r8a7790_pinmux_init(void);
>>> void r8a7790_pm_init(void);
>>> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c
>>> b/arch/arm/mach-shmobile/setup-r8a7790.c index 3e5813f..462c81f 100644
>>> --- a/arch/arm/mach-shmobile/setup-r8a7790.c
>>> +++ b/arch/arm/mach-shmobile/setup-r8a7790.c
>>> @@ -294,11 +294,6 @@ static struct resource cmt0_resources[] = {
>>> &cmt##idx##_platform_data, \
>>> sizeof(struct sh_timer_config))
>>>
>>> -void __init r8a7790_add_dt_devices(void)
>>> -{
>>> - r8a7790_register_cmt(0);
>>> -}
>>> -
>>> void __init r8a7790_add_standard_devices(void)
>>> {
>>> r8a7790_register_scif(0);
>>> @@ -311,7 +306,7 @@ void __init r8a7790_add_standard_devices(void)
>>> r8a7790_register_scif(7);
>>> r8a7790_register_scif(8);
>>> r8a7790_register_scif(9);
>>> - r8a7790_add_dt_devices();
>>> + r8a7790_register_cmt(0);
>>> r8a7790_register_irqc(0);
>>> r8a7790_register_thermal();
>>> }
>> IMHO, these 2 files should be split into a separate patch.
> That could easily be done, but why ?
It does not seem necessary to combine these changes in one patch.
Remember, Simon has separate branches for boards and SoCs. So finally it's up
to him to decide on this...
WBR, Sergei
^ permalink raw reply
* [PATCH v4 0/4]
From: Christoph Fritz @ 2014-02-14 14:20 UTC (permalink / raw)
To: linux-arm-kernel
This set of patches adds board support for an omap36 (dm3730) system
from INCOstartec. It's based on Linux 3.14-rc2 + patch series:
"OMAP: OMAP3 DSS related clock patches".
Due to boot order and deferring probe, IRQs for network and USB couldn't
be requested (see Bootlog below).
Changes compared to previous version (v4):
- rebased on Linux 3.14-rc2 + series: "OMAP: OMAP3 DSS related clock patches"
- move gpio_156 (DSS enable pin) pinctrl to &gpio5 domain
Changes compared to previous version (v3):
- rebased on next-20140124
- use pinctrl macros OMAP3_WKUP_IOPAD, OMAP3_CORE1_IOPAD
and OMAP3630_CORE2_IOPAD
- use same convention for all comments
- dss-quirk: name twl4030 VPLL2 regulator as vdds_dsi
- fix style
Changes compared to previous version (v2):
- rebased on next-20140122 from next-20140115
- using omap36xx.dtsi instead of unsupported 1ghz omap37xx100
Initial version (v1):
- based on next-20140115
Christoph Fritz (4):
ARM: dts: omap3: Add support for INCOstartec a83x module
ARM: dts: omap3: Add support for INCOstartec DBB056 baseboard
ARM: OMAP2+: add legacy display for omap3 DBB056
ARM: OMAP2+: Add pdata quirk for sys_clkout2 for omap3 DBB056
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 459 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/omap3-lilly-dbb056.dts | 170 +++++++++++
arch/arm/mach-omap2/dss-common.c | 49 ++++
arch/arm/mach-omap2/dss-common.h | 1 +
arch/arm/mach-omap2/pdata-quirks.c | 45 ++-
6 files changed, 724 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/omap3-lilly-a83x.dtsi
create mode 100644 arch/arm/boot/dts/omap3-lilly-dbb056.dts
Bootlog:
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.14.0-rc2+ (c at c) (gcc version 4.7.3 20121106 (prerelease) (linaro-4.7-2012.11) ) #1 PREEMPT Fri Feb 14 14:50:48 CET 2014
[ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine model: INCOstartec LILLY-DBB056 (DM3730)
[ 0.000000] Memory policy: Data cache writeback
[ 0.000000] CPU: All CPU(s) started in SVC mode.
[ 0.000000] OMAP3630 ES1.2 (l2cache iva sgx neon isp 192mhz_clk )
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256
[ 0.000000] Kernel command line: console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0 ip=dhcp root=/dev/nfs
[ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Memory: 115052K/130048K available (5686K kernel code, 415K rwdata, 1852K rodata, 216K init, 5434K bss, 14996K reserved, 0K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0764c3c (7540 kB)
[ 0.000000] .init : 0xc0765000 - 0xc079b3c8 ( 217 kB)
[ 0.000000] .data : 0xc079c000 - 0xc0803c40 ( 416 kB)
[ 0.000000] .bss : 0xc0803c4c - 0xc0d52814 (5435 kB)
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts
[ 0.000000] Total of 96 interrupts on 1 active controller
[ 0.000000] Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz
[ 0.000000] OMAP clockevent source: timer1 at 32768 Hz
[ 9.571105] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns
[ 0.000000] OMAP clocksource: 32k_counter at 32768 Hz
[ 0.000915] Console: colour dummy device 80x30
[ 0.001007] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.001007] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.001007] ... MAX_LOCK_DEPTH: 48
[ 0.001037] ... MAX_LOCKDEP_KEYS: 8191
[ 0.001037] ... CLASSHASH_SIZE: 4096
[ 0.001068] ... MAX_LOCKDEP_ENTRIES: 16384
[ 0.001068] ... MAX_LOCKDEP_CHAINS: 32768
[ 0.001068] ... CHAINHASH_SIZE: 16384
[ 0.001098] memory used by lock dependency info: 3695 kB
[ 0.001098] per task-struct memory footprint: 1152 bytes
[ 0.001159] Calibrating delay loop... 594.73 BogoMIPS (lpj=2973696)
[ 0.107971] pid_max: default: 4096 minimum: 301
[ 0.108306] Security Framework initialized
[ 0.108398] Mount-cache hash table entries: 512
[ 0.167358] CPU: Testing write buffer coherency: ok
[ 0.168914] Setting up static identity map for 0x805650f8 - 0x80565150
[ 0.174591] devtmpfs: initialized
[ 0.179748] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
[ 0.252075] omap_hwmod: mcbsp2_sidetone using broken dt data from mcbsp
[ 0.254119] omap_hwmod: mcbsp3_sidetone using broken dt data from mcbsp
[ 0.281341] omap_hwmod: usb_host_hs: could not associate to clkdm l3_init_clkdm
[ 0.283538] omap_hwmod: usb_tll_hs: could not associate to clkdm l3_init_clkdm
[ 0.351043] pinctrl core: initialized pinctrl subsystem
[ 0.354339] regulator-dummy: no parameters
[ 0.356475] NET: Registered protocol family 16
[ 0.357208] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.359466] cpuidle: using governor ladder
[ 0.359497] cpuidle: using governor menu
[ 0.365661] Reprogramming SDRC clock to 400000000 Hz
[ 0.372924] omap_gpio 48310000.gpio: could not find pctldev for node /ocp/pinmux at 480025a0/pinmux_gpio1_pins, deferring probe
[ 0.372985] platform 48310000.gpio: Driver omap_gpio requests probe deferral
[ 0.376647] OMAP GPIO hardware version 2.5
[ 0.380523] omap_gpio 49054000.gpio: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_gpio4_pins, deferring probe
[ 0.380554] platform 49054000.gpio: Driver omap_gpio requests probe deferral
[ 0.381286] omap_gpio 49056000.gpio: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_gpio5_pins, deferring probe
[ 0.381317] platform 49056000.gpio: Driver omap_gpio requests probe deferral
[ 0.381988] omap_gpio 49058000.gpio: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_hsusb1_pins, deferring probe
[ 0.382049] platform 49058000.gpio: Driver omap_gpio requests probe deferral
[ 0.393676] platform 49022000.mcbsp: alias fck already exists
[ 0.394683] platform 49024000.mcbsp: alias fck already exists
[ 0.406311] omap-gpmc 6e000000.gpmc: GPMC revision 5.0
[ 0.406677] gpmc_probe_nand_child: ti,elm-id property not found
[ 0.406921] gpmc_read_settings_dt: page/burst-length set but not used!
[ 0.406951] gpmc_read_settings_dt: read/write wait monitoring not enabled!
[ 0.408020] irq: no irq domain found for /ocp/gpio at 49056000 !
[ 0.408050] ------------[ cut here ]------------
[ 0.408081] WARNING: CPU: 0 PID: 1 at linux/drivers/of/platform.c:171 of_device_alloc+0x158/0x168()
[ 0.408081] Modules linked in:
[ 0.408111] CPU: 0 PID: 1 Comm: swapper Not tainted 3.14.0-rc2+ #856
[ 0.408172] [<c0012fc4>] (unwind_backtrace) from [<c0010e30>] (show_stack+0x10/0x14)
[ 0.408203] [<c0010e30>] (show_stack) from [<c003455c>] (warn_slowpath_common+0x64/0x84)
[ 0.408203] [<c003455c>] (warn_slowpath_common) from [<c0034598>] (warn_slowpath_null+0x1c/0x24)
[ 0.408233] [<c0034598>] (warn_slowpath_null) from [<c03e61d0>] (of_device_alloc+0x158/0x168)
[ 0.408264] [<c03e61d0>] (of_device_alloc) from [<c03e6210>] (of_platform_device_create_pdata+0x30/0x9c)
[ 0.408294] [<c03e6210>] (of_platform_device_create_pdata) from [<c001f0f4>] (gpmc_probe_generic_child+0xa4/0x2ac)
[ 0.408325] [<c001f0f4>] (gpmc_probe_generic_child) from [<c001f6fc>] (gpmc_probe+0x400/0x7b0)
[ 0.408325] [<c001f6fc>] (gpmc_probe) from [<c030312c>] (platform_drv_probe+0x18/0x48)
[ 0.408386] [<c030312c>] (platform_drv_probe) from [<c0301d80>] (driver_probe_device+0x110/0x230)
[ 0.408386] [<c0301d80>] (driver_probe_device) from [<c0300494>] (bus_for_each_drv+0x44/0x8c)
[ 0.408416] [<c0300494>] (bus_for_each_drv) from [<c0301c38>] (device_attach+0x74/0x8c)
[ 0.408447] [<c0301c38>] (device_attach) from [<c030132c>] (bus_probe_device+0x88/0xac)
[ 0.408477] [<c030132c>] (bus_probe_device) from [<c02ff930>] (device_add+0x3e8/0x4f0)
[ 0.408508] [<c02ff930>] (device_add) from [<c03e624c>] (of_platform_device_create_pdata+0x6c/0x9c)
[ 0.408508] [<c03e624c>] (of_platform_device_create_pdata) from [<c03e634c>] (of_platform_bus_create+0xd0/0x29c)
[ 0.408538] [<c03e634c>] (of_platform_bus_create) from [<c03e6398>] (of_platform_bus_create+0x11c/0x29c)
[ 0.408569] [<c03e6398>] (of_platform_bus_create) from [<c03e6574>] (of_platform_populate+0x5c/0x9c)
[ 0.408599] [<c03e6574>] (of_platform_populate) from [<c0771570>] (pdata_quirks_init+0x34/0x44)
[ 0.408599] [<c0771570>] (pdata_quirks_init) from [<c0766f38>] (customize_machine+0x1c/0x40)
[ 0.408630] [<c0766f38>] (customize_machine) from [<c000883c>] (do_one_initcall+0xe4/0x144)
[ 0.408660] [<c000883c>] (do_one_initcall) from [<c0765af8>] (kernel_init_freeable+0xe8/0x1b0)
[ 0.408691] [<c0765af8>] (kernel_init_freeable) from [<c05590f0>] (kernel_init+0x8/0xec)
[ 0.408721] [<c05590f0>] (kernel_init) from [<c000e4c8>] (ret_from_fork+0x14/0x2c)
[ 0.408905] ---[ end trace 2067aff632ad5d0c ]---
[ 0.409851] irq: no irq domain found for /ocp/gpio at 49054000 !
[ 0.409851] ------------[ cut here ]------------
[ 0.409881] WARNING: CPU: 0 PID: 1 at linux/drivers/of/platform.c:171 of_device_alloc+0x158/0x168()
[ 0.409912] Modules linked in:
[ 0.409942] CPU: 0 PID: 1 Comm: swapper Tainted: G W 3.14.0-rc2+ #856
[ 0.409973] [<c0012fc4>] (unwind_backtrace) from [<c0010e30>] (show_stack+0x10/0x14)
[ 0.409973] [<c0010e30>] (show_stack) from [<c003455c>] (warn_slowpath_common+0x64/0x84)
[ 0.410003] [<c003455c>] (warn_slowpath_common) from [<c0034598>] (warn_slowpath_null+0x1c/0x24)
[ 0.410034] [<c0034598>] (warn_slowpath_null) from [<c03e61d0>] (of_device_alloc+0x158/0x168)
[ 0.410064] [<c03e61d0>] (of_device_alloc) from [<c03e6210>] (of_platform_device_create_pdata+0x30/0x9c)
[ 0.410095] [<c03e6210>] (of_platform_device_create_pdata) from [<c001f0f4>] (gpmc_probe_generic_child+0xa4/0x2ac)
[ 0.410095] [<c001f0f4>] (gpmc_probe_generic_child) from [<c001f6fc>] (gpmc_probe+0x400/0x7b0)
[ 0.410125] [<c001f6fc>] (gpmc_probe) from [<c030312c>] (platform_drv_probe+0x18/0x48)
[ 0.410156] [<c030312c>] (platform_drv_probe) from [<c0301d80>] (driver_probe_device+0x110/0x230)
[ 0.410186] [<c0301d80>] (driver_probe_device) from [<c0300494>] (bus_for_each_drv+0x44/0x8c)
[ 0.410217] [<c0300494>] (bus_for_each_drv) from [<c0301c38>] (device_attach+0x74/0x8c)
[ 0.410217] [<c0301c38>] (device_attach) from [<c030132c>] (bus_probe_device+0x88/0xac)
[ 0.410247] [<c030132c>] (bus_probe_device) from [<c02ff930>] (device_add+0x3e8/0x4f0)
[ 0.410278] [<c02ff930>] (device_add) from [<c03e624c>] (of_platform_device_create_pdata+0x6c/0x9c)
[ 0.410308] [<c03e624c>] (of_platform_device_create_pdata) from [<c03e634c>] (of_platform_bus_create+0xd0/0x29c)
[ 0.410308] [<c03e634c>] (of_platform_bus_create) from [<c03e6398>] (of_platform_bus_create+0x11c/0x29c)
[ 0.410339] [<c03e6398>] (of_platform_bus_create) from [<c03e6574>] (of_platform_populate+0x5c/0x9c)
[ 0.410369] [<c03e6574>] (of_platform_populate) from [<c0771570>] (pdata_quirks_init+0x34/0x44)
[ 0.410400] [<c0771570>] (pdata_quirks_init) from [<c0766f38>] (customize_machine+0x1c/0x40)
[ 0.410400] [<c0766f38>] (customize_machine) from [<c000883c>] (do_one_initcall+0xe4/0x144)
[ 0.410430] [<c000883c>] (do_one_initcall) from [<c0765af8>] (kernel_init_freeable+0xe8/0x1b0)
[ 0.410461] [<c0765af8>] (kernel_init_freeable) from [<c05590f0>] (kernel_init+0x8/0xec)
[ 0.410491] [<c05590f0>] (kernel_init) from [<c000e4c8>] (ret_from_fork+0x14/0x2c)
[ 0.410491] ---[ end trace 2067aff632ad5d0d ]---
[ 0.413391] omap3_dbb056_legacy_init: Late Reparent clkout2 to 96M_FCK
[ 0.413421] omap3_dbb056_legacy_init: Set clkout2 to 24MHz for internal usb hub
[ 0.416900] No ATAGs?
[ 0.416931] hw-breakpoint: debug architecture 0x4 unsupported.
[ 0.420379] OMAP DMA hardware revision 5.0
[ 0.442382] bio: create slab <bio-0> at 0
[ 0.486419] omap-dma-engine 48056000.dma-controller: OMAP DMA engine driver
[ 0.488128] VCC3: 3300 mV
[ 0.490509] SCSI subsystem initialized
[ 0.491394] usbcore: registered new interface driver usbfs
[ 0.491577] usbcore: registered new interface driver hub
[ 0.492004] usbcore: registered new device driver usb
[ 0.494323] musb-omap2430 480ab000.usb_otg_hs: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_hsusb_otg_pins, deferring probe
[ 0.494354] platform 480ab000.usb_otg_hs: Driver musb-omap2430 requests probe deferral
[ 0.495086] omap_i2c 48070000.i2c: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_i2c1_pins, deferring probe
[ 0.495147] platform 48070000.i2c: Driver omap_i2c requests probe deferral
[ 0.495239] omap_i2c 48072000.i2c: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_i2c2_pins, deferring probe
[ 0.495269] platform 48072000.i2c: Driver omap_i2c requests probe deferral
[ 0.495361] omap_i2c 48060000.i2c: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_i2c3_pins, deferring probe
[ 0.495391] platform 48060000.i2c: Driver omap_i2c requests probe deferral
[ 0.495788] pps_core: LinuxPPS API ver. 1 registered
[ 0.495788] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.495849] PTP clock support registered
[ 0.497070] Advanced Linux Sound Architecture Driver Initialized.
[ 0.501129] cfg80211: Calling CRDA to update world regulatory domain
[ 0.501861] Switched to clocksource 32k_counter
[ 0.536651] NET: Registered protocol family 2
[ 0.538818] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.539031] TCP bind hash table entries: 1024 (order: 3, 36864 bytes)
[ 0.539581] TCP: Hash tables configured (established 1024 bind 1024)
[ 0.539825] TCP: reno registered
[ 0.539855] UDP hash table entries: 128 (order: 1, 10240 bytes)
[ 0.540008] UDP-Lite hash table entries: 128 (order: 1, 10240 bytes)
[ 0.541473] NET: Registered protocol family 1
[ 0.543060] RPC: Registered named UNIX socket transport module.
[ 0.543090] RPC: Registered udp transport module.
[ 0.543090] RPC: Registered tcp transport module.
[ 0.543121] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.543640] usbhs_omap 48064000.usbhshost: could not find pctldev for node /ocp/pinmux at 480025a0/pinmux_hsusb1_2_pins, deferring probe
[ 0.543701] platform 48064000.usbhshost: Driver usbhs_omap requests probe deferral
[ 0.544738] hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver, 5 counters available
[ 0.551605] futex hash table entries: 16 (order: -3, 640 bytes)
[ 0.555389] VFS: Disk quotas dquot_6.5.2
[ 0.555480] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 0.557891] NFS: Registering the id_resolver key type
[ 0.558349] Key type id_resolver registered
[ 0.558380] Key type id_legacy registered
[ 0.558532] fuse init (API version 7.22)
[ 0.559967] msgmni has been set to 224
[ 0.565155] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250)
[ 0.565277] io scheduler noop registered
[ 0.565307] io scheduler deadline registered
[ 0.565368] io scheduler cfq registered (default)
[ 0.573059] pinctrl-single 48002030.pinmux: 284 pins at pa fa002030 size 568
[ 0.574462] pinctrl-single 48002a00.pinmux: 46 pins at pa fa002a00 size 92
[ 0.576599] pinctrl-single 480025a0.pinmux: 46 pins at pa fa0025a0 size 92
[ 0.579772] OMAP DSS rev 2.0
[ 0.581298] platform panel-dpi.0: Driver panel-dpi requests probe deferral
[ 0.584259] omapfb omapfb: no displays
[ 0.586761] omapfb omapfb: failed to setup omapfb
[ 0.586791] platform omapfb: Driver omapfb requests probe deferral
[ 0.587677] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.596679] 4806a000.serial: ttyO0 at MMIO 0x4806a000 (irq = 88, base_baud = 3000000) is a OMAP UART0
[ 2.001129] console [ttyO0] enabled
[ 2.007598] 4806c000.serial: ttyO1 at MMIO 0x4806c000 (irq = 89, base_baud = 3000000) is a OMAP UART1
[ 2.019805] 49020000.serial: ttyO2 at MMIO 0x49020000 (irq = 90, base_baud = 3000000) is a OMAP UART2
[ 2.054382] brd: module loaded
[ 2.070831] loop: module loaded
[ 2.077209] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 2.085540] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xbc
[ 2.092285] nand: Micron NAND 512MiB 1,8V 16-bit
[ 2.097106] nand: 512MiB, SLC, page size: 2048, OOB size: 64
[ 2.103088] nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
[ 2.111755] 5 ofpart partitions found on MTD device omap2-nand.0
[ 2.118133] Creating 5 MTD partitions on "omap2-nand.0":
[ 2.123779] 0x000000000000-0x000000080000 : "MLO"
[ 2.135009] 0x000000080000-0x000000260000 : "u-boot"
[ 2.145141] 0x000000260000-0x000000280000 : "u-boot-environment"
[ 2.154785] 0x000000280000-0x000000780000 : "kernel"
[ 2.167388] 0x000000780000-0x000010000000 : "filesystem"
[ 2.391906] irq: no irq domain found for /ocp/gpio at 48310000 !
[ 2.404235] CAN device driver interface
[ 2.408294] sja1000 CAN netdevice driver
[ 2.414245] smsc911x: Driver version 2008-10-21
[ 2.418975] smsc911x: Could not allocate irq resource
[ 2.424926] smsc911x: Driver version 2008-10-21
[ 2.429656] smsc911x: Could not allocate irq resource
[ 2.435302] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 2.442230] ehci-omap: OMAP-EHCI Host Controller driver
[ 2.448120] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 2.454803] ohci-omap3: OHCI OMAP3 driver
[ 2.459625] usbcore: registered new interface driver usb-storage
[ 2.468322] mousedev: PS/2 mouse device common for all mice
[ 2.475463] ads7846: probe of spi2.0 failed with error -22
[ 2.482330] i2c /dev entries driver
[ 2.488983] omap_wdt: OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec
[ 2.498291] platform 4809c000.mmc: Driver omap_hsmmc requests probe deferral
[ 2.506469] platform 480b4000.mmc: Driver omap_hsmmc requests probe deferral
[ 2.514709] platform leds.3: Driver leds-gpio requests probe deferral
[ 2.522674] usbcore: registered new interface driver usbhid
[ 2.528503] usbhid: USB HID core driver
[ 2.544219] omap-twl4030 sound.4: ASoC: CODEC twl4030-codec not registered
[ 2.551727] omap-twl4030 sound.4: devm_snd_soc_register_card() failed: -517
[ 2.560516] platform sound.4: Driver omap-twl4030 requests probe deferral
[ 2.568359] TCP: cubic registered
[ 2.571838] Initializing XFRM netlink socket
[ 2.576721] NET: Registered protocol family 17
[ 2.581481] NET: Registered protocol family 15
[ 2.586273] can: controller area network core (rev 20120528 abi 9)
[ 2.592987] NET: Registered protocol family 29
[ 2.597656] can: raw protocol (rev 20120528)
[ 2.602355] can: broadcast manager protocol (rev 20120528 t)
[ 2.608306] can: netlink gateway (rev 20130117) max_hops=1
[ 2.614654] Key type dns_resolver registered
[ 2.622222] ThumbEE CPU extension supported.
[ 2.626770] Registering SWP/SWPB emulation handler
[ 2.633422] registered taskstats version 1
[ 2.654754] musb-omap2430 480ab000.usb_otg_hs: unable to find phy
[ 2.661224] HS USB OTG: no transceiver configured
[ 2.666381] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed with status -517
[ 2.674652] platform musb-hdrc.0.auto: Driver musb-hdrc requests probe deferral
[ 2.698242] twl 0-0048: PIH (irq 23) chaining IRQs 338..346
[ 2.704803] twl 0-0048: power (irq 343) chaining IRQs 346..353
[ 2.715057] twl_rtc rtc.8: Power up reset detected.
[ 2.720367] twl_rtc rtc.8: Enabling TWL-RTC
[ 2.729705] twl_rtc rtc.8: rtc core: registered rtc.8 as rtc0
[ 2.741180] VAUX1: at 3000 mV
[ 2.747283] VAUX2_4030: 2800 mV
[ 2.752990] VAUX3: at 2800 mV
[ 2.758209] VAUX4: at 2800 mV
[ 2.763671] VDD1: 600 <--> 1450 mV at 1200 mV
[ 2.770507] VDAC: 1800 mV
[ 2.775787] VIO: at 1800 mV
[ 2.780944] VINTANA1: 1500 mV
[ 2.786468] VINTANA2: at 2750 mV
[ 2.792266] VINTDIG: 1500 mV
[ 2.797485] VMMC1: 1850 <--> 3150 mV at 3000 mV
[ 2.804473] VMMC2: 1850 <--> 3150 mV at 2600 mV
[ 2.811157] VUSB1V5: 1500 mV
[ 2.816070] VUSB1V8: 1800 mV
[ 2.820800] VUSB3V1: 3100 mV
[ 2.826171] VPLL1: at 1800 mV
[ 2.831604] VPLL2: 1800 mV
[ 2.836639] VSIM: 1800 <--> 3000 mV at 1800 mV
[ 2.844085] twl4030_gpio twl4030-gpio: gpio (irq 338) chaining IRQs 354..371
[ 2.857788] twl4030_usb twl4030-usb.29: Initialized TWL4030 USB module
[ 2.869354] omap_i2c 48070000.i2c: bus 0 rev4.4 at 2600 kHz
[ 2.877777] omap_i2c 48072000.i2c: bus 1 rev4.4 at 2600 kHz
[ 2.890533] omap_i2c 48060000.i2c: bus 2 rev4.4 at 2600 kHz
[ 2.899658] omapdss_dpi.0 supply vdds_dsi not found, using dummy regulator
[ 2.918701] Console: switching to colour frame buffer device 80x30
[ 2.933471] omapfb omapfb: using display 'lcd' mode 640x480
[ 2.942535] 4809c000.mmc supply vmmc_aux not found, using dummy regulator
[ 2.995971] 480b4000.mmc supply vmmc_aux not found, using dummy regulator
[ 3.004150] VMMC1: Restricting voltage, 3100000-1950000uV
[ 3.009826] omap_hsmmc 480b4000.mmc: could not set regulator OCR (-22)
[ 3.143157] omap-twl4030 sound.4: twl4030-hifi <-> 49022000.mcbsp mapping ok
[ 3.179931] unable to find transceiver
[ 3.183959] musb-hdrc musb-hdrc.0.auto: MUSB HDRC host driver
[ 3.190765] musb-hdrc musb-hdrc.0.auto: new USB bus registered, assigned bus number 1
[ 3.200500] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 3.207702] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.215301] usb usb1: Product: MUSB HDRC host driver
[ 3.220520] usb usb1: Manufacturer: Linux 3.14.0-rc2+ musb-hcd
[ 3.226654] usb usb1: SerialNumber: musb-hdrc.0.auto
[ 3.236572] hub 1-0:1.0: USB hub found
[ 3.240997] hub 1-0:1.0: 1 port detected
[ 3.277343] twl_rtc rtc.8: setting system clock to 2000-01-01 00:00:00 UTC (946684800)
[ 15.472961] ALSA device list:
[ 15.476104] #0: lilly-a83x
[ 15.480895] omap_uart 4806a000.serial: no wakeirq for uart0
[ 15.487518] Root-NFS: no NFS server address
[ 15.491912] VFS: Unable to mount root fs via NFS, trying floppy.
[ 15.499755] VFS: Cannot open root device "nfs" or unknown-block(2,0): error -6
[ 15.507476] Please append a correct "root=" boot option; here are the available partitions:
[ 15.516479] 1f00 512 mtdblock0 (driver?)
[ 15.521789] 1f01 1920 mtdblock1 (driver?)
[ 15.527221] 1f02 128 mtdblock2 (driver?)
[ 15.532653] 1f03 5120 mtdblock3 (driver?)
[ 15.537963] 1f04 254464 mtdblock4 (driver?)
[ 15.543518] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0)
--
1.7.10.4
^ permalink raw reply
* [PATCH v4 1/4] ARM: dts: omap3: Add support for INCOstartec a83x module
From: Christoph Fritz @ 2014-02-14 14:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392387656-15186-1-git-send-email-chf.fritz@googlemail.com>
INCOstartec LILLY-A83X module is a TI DM3730xx100 (OMAP3) SoC
computer-on-module.
This patch adds device tree support for most of its features.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
---
arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 459 +++++++++++++++++++++++++++++++
1 file changed, 459 insertions(+)
create mode 100644 arch/arm/boot/dts/omap3-lilly-a83x.dtsi
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
new file mode 100644
index 0000000..6369d9f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -0,0 +1,459 @@
+/*
+ * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "omap36xx.dtsi"
+
+/ {
+ model = "INCOstartec LILLY-A83X module (DM3730)";
+ compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+
+ chosen {
+ bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x8000000>; /* 128 MB */
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "lilly-a83x::led1";
+ gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ };
+
+ sound {
+ compatible = "ti,omap-twl4030";
+ ti,model = "lilly-a83x";
+
+ ti,mcbsp = <&mcbsp2>;
+ ti,codec = <&twl_audio>;
+ };
+
+ reg_vcc3: vcc3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ hsusb1_phy: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <®_vcc3>;
+ };
+};
+
+&omap3_pmx_wkup {
+ pinctrl-names = "default";
+
+ lan9221_pins: pinmux_lan9221_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */
+ >;
+ };
+
+ tsc2048_pins: pinmux_tsc2048_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */
+ >;
+ };
+
+ mmc1cd_pins: pinmux_mmc1cd_pins {
+ pinctrl-single,pins = <
+ OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */
+ >;
+ };
+};
+
+&omap3_pmx_core {
+ pinctrl-names = "default";
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
+ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */
+ OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */
+ OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */
+ OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
+ OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
+ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
+ >;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
+ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
+ >;
+ };
+
+ hsusb1_pins: pinmux_hsusb1_pins {
+ pinctrl-single,pins = <
+
+ /* GPIO 182 controls USB-Hub reset. But USB-Phy its
+ * reset can't be controlled. So we clamp this GPIO to
+ * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub.
+ */
+
+ OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */
+ >;
+ };
+
+ hsusb_otg_pins: pinmux_hsusb_otg_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
+ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
+ OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
+ OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
+ OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
+ OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
+ OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
+ OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
+ OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
+ OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
+ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
+ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
+ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
+ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
+ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
+ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
+ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
+ >;
+ };
+
+ spi2_pins: pinmux_spi2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */
+ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */
+ OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */
+ OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &hsusb1_2_pins
+ >;
+
+ hsusb1_2_pins: pinmux_hsusb1_2_pins {
+ pinctrl-single,pins = <
+ OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
+ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
+ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */
+ OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */
+ OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */
+ OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */
+ OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */
+ OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */
+ OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */
+ OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */
+ OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */
+ OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */
+ >;
+ };
+
+ gpio1_pins: pinmux_gpio1_pins {
+ pinctrl-single,pins = <
+ OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */
+ >;
+ };
+
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_pins>;
+};
+
+&gpio6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_pins>;
+};
+
+&i2c1 {
+ clock-frequency = <2600000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ twl: twl at 48 {
+ reg = <0x48>;
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+
+ twl_audio: audio {
+ compatible = "ti,twl4030-audio";
+ codec {
+ };
+ };
+ };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&twl {
+ vmmc1: regulator-vmmc1 {
+ regulator-always-on;
+ };
+
+ vdd1: regulator-vdd1 {
+ regulator-always-on;
+ };
+
+ vdd2: regulator-vdd2 {
+ regulator-always-on;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <2600000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+};
+
+&i2c3 {
+ clock-frequency = <2600000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ gpiom1: gpio at 20 {
+ compatible = "mcp,mcp23017";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+};
+
+&uart4 {
+ status = "disabled";
+};
+
+&mmc1 {
+ cd-gpios = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
+ cd-inverted;
+ vmmc-supply = <&vmmc1>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins &mmc1cd_pins>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+};
+
+&mmc2 {
+ status = "disabled";
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&mcspi2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins>;
+
+ tsc2046 at 0 {
+ reg = <0>; /* CS0 */
+ compatible = "ti,tsc2046";
+ interrupt-parent = <&gpio1>;
+ interrupts = <8 0>; /* boot6 / gpio_8 */
+ spi-max-frequency = <1000000>;
+ pendown-gpio = <&gpio1 8 0>;
+ vcc-supply = <®_vcc3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsc2048_pins>;
+
+ ti,x-min = <300>;
+ ti,x-max = <3000>;
+ ti,y-min = <600>;
+ ti,y-max = <3600>;
+ ti,x-plate-ohms = <80>;
+ ti,pressure-max = <255>;
+ ti,swap-xy;
+
+ linux,wakeup;
+ };
+};
+
+&usbhsehci {
+ phys = <&hsusb1_phy>;
+};
+
+&usbhshost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_2_pins>;
+ num-ports = <2>;
+ port1-mode = "ehci-phy";
+};
+
+&usb_otg_hs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb_otg_pins>;
+ interface-type = <0>;
+ usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
+ mode = <3>;
+ power = <50>;
+};
+
+&gpmc {
+ ranges = <0 0 0x30000000 0x1000000>,
+ <7 0 0x15000000 0x01000000>;
+
+ nand at 0,0 {
+ reg = <0 0 0x1000000>;
+ nand-bus-width = <16>;
+ ti,nand-ecc-opt = "bch8";
+ /* no elm on omap3 */
+
+ gpmc,mux-add-data = <0>;
+ gpmc,device-nand;
+ gpmc,device-width = <2>;
+ gpmc,wait-pin = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,burst-length= <4>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <100>;
+ gpmc,cs-wr-off-ns = <100>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <100>;
+ gpmc,adv-wr-off-ns = <100>;
+ gpmc,oe-on-ns = <5>;
+ gpmc,oe-off-ns = <75>;
+ gpmc,we-on-ns = <5>;
+ gpmc,we-off-ns = <75>;
+ gpmc,rd-cycle-ns = <100>;
+ gpmc,wr-cycle-ns = <100>;
+ gpmc,access-ns = <60>;
+ gpmc,page-burst-access-ns = <5>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-samecsen;
+ gpmc,cycle2cycle-delay-ns = <50>;
+ gpmc,wr-data-mux-bus-ns = <75>;
+ gpmc,wr-access-ns = <155>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "MLO";
+ reg = <0 0x80000>;
+ };
+
+ partition at 0x80000 {
+ label = "u-boot";
+ reg = <0x80000 0x1e0000>;
+ };
+
+ partition at 0x260000 {
+ label = "u-boot-environment";
+ reg = <0x260000 0x20000>;
+ };
+
+ partition at 0x280000 {
+ label = "kernel";
+ reg = <0x280000 0x500000>;
+ };
+
+ partition at 0x780000 {
+ label = "filesystem";
+ reg = <0x780000 0xf880000>;
+ };
+ };
+
+ ethernet at 7,0 {
+ compatible = "smsc,lan9221", "smsc,lan9115";
+ bank-width = <2>;
+ gpmc,mux-add-data = <2>;
+ gpmc,cs-on-ns = <10>;
+ gpmc,cs-rd-off-ns = <60>;
+ gpmc,cs-wr-off-ns = <60>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <10>;
+ gpmc,adv-wr-off-ns = <10>;
+ gpmc,oe-on-ns = <10>;
+ gpmc,oe-off-ns = <60>;
+ gpmc,we-on-ns = <10>;
+ gpmc,we-off-ns = <60>;
+ gpmc,rd-cycle-ns = <100>;
+ gpmc,wr-cycle-ns = <100>;
+ gpmc,access-ns = <50>;
+ gpmc,page-burst-access-ns = <5>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <75>;
+ gpmc,wr-data-mux-bus-ns = <15>;
+ gpmc,wr-access-ns = <75>;
+ gpmc,cycle2cycle-samecsen;
+ gpmc,cycle2cycle-diffcsen;
+ vddvario-supply = <®_vcc3>;
+ vdd33a-supply = <®_vcc3>;
+ reg-io-width = <4>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <1 0x2>;
+ reg = <7 0 0xff>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan9221_pins>;
+ phy-mode = "mii";
+ };
+};
--
1.7.10.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox