* [PATCH v3] platform: Make platform_bus device a platform device
From: Pawel Moll @ 2014-07-23 14:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMgya9i=zc_AVO_mgrC_FjYz-RWxwXguNueVA=7gpq=5sA@mail.gmail.com>
On Tue, 2014-07-22 at 20:46 +0100, Olof Johansson wrote:
> > @@ -946,12 +946,18 @@ int __init platform_bus_init(void)
> >
> > early_platform_cleanup();
> >
> > - error = device_register(&platform_bus);
> > + dev_set_name(&platform_bus.dev, "%s", platform_bus.name);
> > + error = device_register(&platform_bus.dev);
> > if (error)
> > return error;
> > error = bus_register(&platform_bus_type);
> > - if (error)
> > - device_unregister(&platform_bus);
> > + if (!error) {
> > + platform_bus.dev.of_node = of_allnodes;
>
> This breaks all non-OF platforms:
>
> drivers/base/platform.c: In function 'platform_bus_init':
> drivers/base/platform.c:955:30: error: 'of_allnodes' undeclared (first
> use in this function)
> platform_bus.dev.of_node = of_allnodes;
Right, of course, my bad. I can't see any other way of getting the tree
root, so an #ifdef it will be...
Thanks for pointing this out!
Pawe?
^ permalink raw reply
* [PATCH] ARM: multi_v7_defconfig: major refresh
From: Pawel Moll @ 2014-07-23 14:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406052070-6207-1-git-send-email-olof@lixom.net>
On Tue, 2014-07-22 at 19:01 +0100, Olof Johansson wrote:
> This is a major refresh of the multi_v7_defconfig:
>
> - Bring over a bunch of Samsung drivers to make ODROID-U3 and Chromebooks usable
> * Enable big.LITTLE
> * MCPM
> * CYAPA touchpad
> * Samsung-related MTD/regulator/clk/pinmux drivers
> * Add some of the CrOS EC drivers
> - Turn on TPM, HW_RANDOM
> - OMAP_USB3 -> TI_PIPE3 option rename
> - Enable MCPM/b.L for VEXPRESS
> - Add new CONFIG_MTD_SPI_NOR since it otherwise masks off SPI NOR drivers
> - CONFIG_LOGO, because penguins.
>
> I took care to keep the new options that have been added for whose the
> drivers are not yet in our for-next branch. This was pretty awkward so
> we should sort out how to handle those better in the future.
>
> Signed-off-by: Olof Johansson <olof@lixom.net>
It doesn't apply cleanly on 3.16-rc6, but after manual merge VE still
boots :-) (for what it's worth)
Pawe?
^ permalink raw reply
* [PATCH 1/2] Added dts defintion for Lenovo ix4-300d nas
From: Andrew Lunn @ 2014-07-23 14:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140723134534.GF23220@titan.lakedaemon.net>
Hi Benoit,
>
> > + };
> > +
> > + serial at 12000 {
> > + clocks = <&coreclk 0>;
I don't think you need the clocks property. It should be already set
in armada-xp.dtsi.
> > + adt7473 at 2e {
> > + compatible = "adt7473";
Please include a vendor prefix here.
> > + reg = <0x2e>;
> > + };
> > +
> > + pcf8563 at 51 {
> > + compatible = "pcf8563";
and a vendor prefix here.
> > + /* warning: you need both eth1 & 0 to be initialize for poweroff to shutdown otherwise it reboots */
What do you mean by initialized? Driver loaded? Interface up?
> This is a great first version
I agree with Jason, well done.
Andrew
^ permalink raw reply
* [PATCH 3/3] crypto: Add Allwinner Security System crypto accelerator
From: Herbert Xu @ 2014-07-23 14:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201407231607.21106.marex@denx.de>
On Wed, Jul 23, 2014 at 04:07:20PM +0200, Marek Vasut wrote:
> On Wednesday, July 23, 2014 at 03:57:35 PM, Herbert Xu wrote:
> > On Sat, May 24, 2014 at 02:00:03PM +0200, Marek Vasut wrote:
> > > > + }
> > > > +#endif
> > > > +
> > > > +#ifdef CONFIG_CRYPTO_DEV_SUNXI_SS_MD5
> > > > + err = crypto_register_shash(&sunxi_md5_alg);
> > >
> > > Do not use shash for such device. This is clearly and ahash (and async in
> > > general) device. The rule of a thumb here is that you use sync algos only
> > > for devices which have dedicated instructions for computing the
> > > transformation. For devices which are attached to some kind of bus, you
> > > use async algos (ahash etc).
> >
> > I'm sorry that I didn't catch this earlier but there is no such
> > rule.
> >
> > Unless you need the async interface you should stick to the sync
> > interfaces for the sake of simplicity.
> >
> > We have a number of existing drivers that are synchronous but
> > using the async interface. They should either be converted
> > over to the sync interface or made interrupt-driven if possible.
>
> Sure, but this device is interrupt driven and uses DMA to feed the crypto
> engine, therefore async, right ?
If it's interrupt-driven, then yes it would certainly make sense to
be async. But all I see is polling in the latest posting, was the
first version different?
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH 3/3] crypto: Add Allwinner Security System crypto accelerator
From: Marek Vasut @ 2014-07-23 14:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140723135735.GA30132@gondor.apana.org.au>
On Wednesday, July 23, 2014 at 03:57:35 PM, Herbert Xu wrote:
> On Sat, May 24, 2014 at 02:00:03PM +0200, Marek Vasut wrote:
> > > + }
> > > +#endif
> > > +
> > > +#ifdef CONFIG_CRYPTO_DEV_SUNXI_SS_MD5
> > > + err = crypto_register_shash(&sunxi_md5_alg);
> >
> > Do not use shash for such device. This is clearly and ahash (and async in
> > general) device. The rule of a thumb here is that you use sync algos only
> > for devices which have dedicated instructions for computing the
> > transformation. For devices which are attached to some kind of bus, you
> > use async algos (ahash etc).
>
> I'm sorry that I didn't catch this earlier but there is no such
> rule.
>
> Unless you need the async interface you should stick to the sync
> interfaces for the sake of simplicity.
>
> We have a number of existing drivers that are synchronous but
> using the async interface. They should either be converted
> over to the sync interface or made interrupt-driven if possible.
Sure, but this device is interrupt driven and uses DMA to feed the crypto
engine, therefore async, right ?
Best regards,
Marek Vasut
^ permalink raw reply
* [PATCH] clocksource: sirf: disable counter before re-setting it
From: Barry Song @ 2014-07-23 14:03 UTC (permalink / raw)
To: linux-arm-kernel
From: Hao Liu <Hao.Liu@csr.com>
according to HW spec, we have to disable counter before setting
it, if we don't this, in pressure test, sometimes the timer might
not generate interrupt any more.
and this patch also fixes a typo for register set by changing 0x7
to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3.
Signed-off-by: Hao Liu <Hao.Liu@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
drivers/clocksource/timer-marco.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
index 330e930..caf7a20 100644
--- a/drivers/clocksource/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -63,7 +63,7 @@ static inline void sirfsoc_timer_count_disable(int idx)
/* enable count and interrupt */
static inline void sirfsoc_timer_count_enable(int idx)
{
- writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
+ writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}
@@ -103,6 +103,9 @@ static int sirfsoc_timer_set_next_event(unsigned long delta,
{
int cpu = smp_processor_id();
+ /* disable timer first, then modify the related registers */
+ sirfsoc_timer_count_disable(cpu);
+
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
4 * cpu);
writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 0/3] iommu: Remove OMAP IOVMM driver
From: Laurent Pinchart @ 2014-07-23 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140723135217.GE31450@8bytes.org>
Hi Joerg,
On Wednesday 23 July 2014 15:52:17 Joerg Roedel wrote:
> On Mon, Jul 21, 2014 at 11:19:29PM -0700, Tony Lindgren wrote:
> > > Tony, is there still time to get this (and especially patch 2/3, which
> > > touches arch/ code) in v3.17 ?
> >
> > Yes as long as Joerg is OK to merge that branch in :)
>
> Fine with me, I can take only patch 1 or all 3 into my arm/omap branch,
> given Tony's Acked-by.
>
> Then you guys can merge in this branch wherever you want :)
Thank you. Assuming there's currently no conflict to be resolved, I believe
the easiest would be for both you and Tony to merge my branch in your trees.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH v2 14/16] cpufreq: Add cpufreq driver for Tegra124
From: Thierry Reding @ 2014-07-23 13:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <53CFAC22.40106@nvidia.com>
On Wed, Jul 23, 2014 at 03:35:46PM +0300, Tuomas Tynkkynen wrote:
> On 23/07/14 10:09, Thierry Reding wrote:
> > On Mon, Jul 21, 2014 at 06:39:00PM +0300, Tuomas Tynkkynen wrote:
[...]
> >> diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
[...]
> >> + cpu_clk = of_clk_get_by_name(cpu_dev->of_node, "cpu_g");
> >> + if (IS_ERR(cpu_clk))
> >> + return PTR_ERR(cpu_clk);
[...]
> >> + pllp_clk = of_clk_get_by_name(cpu_dev->of_node, "pll_p");
> >> + if (IS_ERR(pllp_clk)) {
> >> + ret = PTR_ERR(pllp_clk);
> >> + goto out_put_pllx_clk;
> >> + }
> >
> > Can the above not be devm_clk_get(cpu_dev, "...") so that you can remove
> > all the clk_put() calls in the cleanup code below?
>
> That would allocate the clks under the cpu_dev's devres list, i.e. all the
> clk_puts wouldn't happen when the cpufreq driver goes away, but only when
> cpu_dev itself goes away.
I don't think so. devres_release_all() is called on driver detach as
well.
> > But is there even a reason why we need that? Couldn't we make the
> > driver's .remove() undo what .probe() did so that the driver can be
> > unloaded?
>
> I guess that could be done, though to fully undo everything the regulator
> voltage would also need to be saved/restored.
That would certainly be my prefered approach. that way the driver can
simply be unloaded, leaving the CPU in the same state as it was after
boot.
> > Otherwise it probably makes more sense not to use a driver (and dummy
> > device) at all as Viresh already mentioned.
> >
>
> The dummy platform device is only required for probe deferral, if that
> could be solved in a different way then yes.
I don't think it can. Probe deferral is pretty closely tied to devices
so it's unlikely to ever get implemented for regular initcalls. And in
this case I really think making the driver removable is a good thing.
> >> +};
> >> +
> >> +static const struct of_device_id soc_of_matches[] = {
> >> + { .compatible = "nvidia,tegra124", },
> >> + {}
> >> +};
> >> +
> >> +static int __init tegra_cpufreq_init(void)
> >> +{
> >> + int ret;
> >> + struct platform_device *pdev;
> >> +
> >> + if (!of_find_matching_node(NULL, soc_of_matches))
> >> + return -ENODEV;
> >
> > I think this could be of_machine_is_compatible() since there's only a
> > single entry in the match table. If there's a good chance that we may
> > end up with more entries, perhaps now would be a good time to add an
> > of_match_machine() function?
>
> I think this driver should work on Tegra132 without modifications.
> of_match_machine() does sound useful for some of the other cpufreq
> drivers as well and likely for your soc_is_tegra() from the PMC
> series as well.
Yes, indeed. I'll give it a shot if you don't beat me to it with this
series.
Thierry
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^ permalink raw reply
* [PATCH 3/3] crypto: Add Allwinner Security System crypto accelerator
From: Herbert Xu @ 2014-07-23 13:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201405241400.03456.marex@denx.de>
On Sat, May 24, 2014 at 02:00:03PM +0200, Marek Vasut wrote:
>
> > + }
> > +#endif
> > +
> > +#ifdef CONFIG_CRYPTO_DEV_SUNXI_SS_MD5
> > + err = crypto_register_shash(&sunxi_md5_alg);
>
> Do not use shash for such device. This is clearly and ahash (and async in
> general) device. The rule of a thumb here is that you use sync algos only for
> devices which have dedicated instructions for computing the transformation. For
> devices which are attached to some kind of bus, you use async algos (ahash etc).
I'm sorry that I didn't catch this earlier but there is no such
rule.
Unless you need the async interface you should stick to the sync
interfaces for the sake of simplicity.
We have a number of existing drivers that are synchronous but
using the async interface. They should either be converted
over to the sync interface or made interrupt-driven if possible.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH v4 3/3] crypto: Add Allwinner Security System crypto accelerator
From: Herbert Xu @ 2014-07-23 13:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140723134857.GO20328@lukather>
On Wed, Jul 23, 2014 at 03:48:57PM +0200, Maxime Ripard wrote:
>
> The exact opposite has been asked for during v1's review...
Indeed but unfortunately it was bogus advice. The async interface
brings with it a lot of complexity which should be avoided unless
you actually need it.
Even if you use the sync interface your driver will still be
available to all async users.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH v2 0/3] iommu: Remove OMAP IOVMM driver
From: Joerg Roedel @ 2014-07-23 13:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140722061929.GD18374@atomide.com>
On Mon, Jul 21, 2014 at 11:19:29PM -0700, Tony Lindgren wrote:
> > Tony, is there still time to get this (and especially patch 2/3, which touches
> > arch/ code) in v3.17 ?
>
> Yes as long as Joerg is OK to merge that branch in :)
Fine with me, I can take only patch 1 or all 3 into my arm/omap branch,
given Tony's Acked-by.
Then you guys can merge in this branch wherever you want :)
Cheers,
Joerg
^ permalink raw reply
* [PATCH v2 14/16] cpufreq: Add cpufreq driver for Tegra124
From: Thierry Reding @ 2014-07-23 13:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKohponfKzuK+TnQvWcvaT8hRX8XZJWXWGMQw138DCwP=qcx+A@mail.gmail.com>
On Wed, Jul 23, 2014 at 01:55:57PM +0530, Viresh Kumar wrote:
> On 23 July 2014 12:54, Thierry Reding <thierry.reding@gmail.com> wrote:
> > ARM_TEGRA_CPUFREQ is still optional, so the select only applies when the
> > Tegra cpufreq driver is enabled. This is mostly just out of convenience,
> > though. The Tegra cpufreq driver uses the generic CPU0 cpufreq driver so
> > a select will automatically pull in the necessary dependency. With a
>
> Not necessarily. cpufreq-cpu0 can have few unmet dependency. And so
> there are chances that tegra driver is compiled but cpufreq-cpu0 isn't as
> we didn't mention it as a *hard* dependency.
>
> And so at boot, there wouldn't be any cpufreq support even when tegra's
> cpufreq driver is available.
>
> Though, menuconfig may give some warnings no such situations.
>
> > "depends on" the Tegra cpufreq driver only becomes available after
> > you've selected GENERIC_CPUFREQ_CPU0, which is somewhat unintuitive.
> >
> > To illustrate with an example: as a user, I want to enable CPU frequency
> > scaling on Tegra. So I use menuconfig to navigate to the "CPU Frequency
> > scaling" menu (enable it if not available yet) and look for an entry
> > that says "Tegra". But I can't find it because it's hidden due to the
> > lack of GENERIC_CPUFREQ_CPU0. That the Tegra CPU frequency driver uses a
> > generic driver is an implementation detail that users shouldn't have to
> > be aware of.
>
> Don't know, the guy compiling out stuff should be knowledgeable enough to
> have a look why tegra cpufreq entry isn't shown in menu. As, probably the
> above problem I mentioned looks to be of more significance than this one,
> atleast to me :)
>
> And, another thing to mention is that CONFIG_TEGRA_CPUFREQ is valid
> for earlier platforms as well and so a select/depends wouldn't be valid for
> earlier platforms. We probably need another Kconfig entry here.
Yes, sounds like a new Kconfig entry for this specific driver would be a
better approach and should remove all the above concerns.
Thierry
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* [PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration
From: Jungseok Lee @ 2014-07-23 13:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140722153738.GJ2219@arm.com>
On Jul 23, 2014, at 12:37 AM, Catalin Marinas wrote:
> On Tue, Jul 22, 2014 at 04:13:27PM +0100, Jungseok Lee wrote:
>> On Jul 22, 2014, at 00:09 +900 Catalin Marinas wrote:
>>> This patch allows support for 3 levels of page tables with 64KB page
>>> configuration allowing 48-bit VA space. The pgd is no longer a full
>>> PAGE_SIZE (PTRS_PER_PGD is 64) and (swapper|idmap)_pg_dir are not fully
>>> populated (pgd_alloc falls back to kzalloc).
>>>
>>> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
>>> ---
>>
>> One more step :)
>
> The last before the upcoming merging window. I also updated the
> pgtable-4levels branch with the latest.
I've tested the latest potable-4levels branch and 64KB + 3 Levels
works fine on model.
Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
I hope that I'm not too late since this series is already in for-next/core
branch of arm64/linux.git repo.
- Jungseok Lee
^ permalink raw reply
* [PATCH 1/2] Added dts defintion for Lenovo ix4-300d nas
From: Jason Cooper @ 2014-07-23 13:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406117232-5962-1-git-send-email-yahoo@perenite.com>
Benoit,
On Wed, Jul 23, 2014 at 05:07:11AM -0700, benoitm974 wrote:
I forgot to mention, please add a commit message describing this device
and possibly a good link to the company website describing it.
thx,
Jason.
> Signed-off-by: benoitm974 <yahoo@perenite.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts | 267 +++++++++++++++++++++++++
> 2 files changed, 268 insertions(+)
> create mode 100644 arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index adb5ed9..f759dd2 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -438,6 +438,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
> armada-xp-db.dtb \
> armada-xp-gp.dtb \
> armada-xp-netgear-rn2120.dtb \
> + armada-xp-lenovo-ix4300d.dtb \
> armada-xp-matrix.dtb \
> armada-xp-openblocks-ax3-4.dtb
> dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
> diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts
> new file mode 100644
> index 0000000..e04e7a6
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts
> @@ -0,0 +1,267 @@
> +/*
> + * Device Tree file for LENOVO IX4-300d
> + *
> + * Copyright (C) 2014, Benoit Masson <yahoo@perenite.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include "armada-xp-mv78230.dtsi"
> +
> +/ {
> + model = "LENOVO IX4-300d";
> + compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
> +
> + chosen {
> + bootargs = "console=ttyS0,115200 earlyprintk";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x00000000 0 0x20000000>; /* 512MB */
> + };
> +
> + soc {
> + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
> + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
> +
> + pcie-controller {
> + status = "okay";
> +
> + pcie at 1,0 {
> + /* Port 0, Lane 0 */
> + status = "okay";
> + };
> + pcie at 5,0 {
> + /* Port 1, Lane 0 */
> + status = "okay";
> + };
> +
> + };
> +
> + internal-regs {
> + pinctrl {
> + poweroff: poweroff {
> + marvell,pins = "mpp24";
> + marvell,function = "gpio";
> + };
> +
> + power_button_pin: power-button-pin {
> + marvell,pins = "mpp44";
> + marvell,function = "gpio";
> + };
> +
> + reset_button_pin: reset-button-pin {
> + marvell,pins = "mpp45";
> + marvell,function = "gpio";
> + };
> + select_button_pin: select-button-pin {
> + marvell,pins = "mpp41";
> + marvell,function = "gpio";
> + };
> +
> + scroll_button_pin: scroll-button-pin {
> + marvell,pins = "mpp42";
> + marvell,function = "gpio";
> + };
> + hdd_led_pin: hdd-led-pin {
> + marvell,pins = "mpp26";
> + marvell,function = "gpio";
> + };
> + };
> +
> + serial at 12000 {
> + clocks = <&coreclk 0>;
> + status = "okay";
> + };
> +
> + mdio {
> + phy0: ethernet-phy at 0 { /* Marvell 88E1318 */
> + reg = <0>;
> + };
> +
> + phy1: ethernet-phy at 1 { /* Marvell 88E1318 */
> + reg = <1>;
> + };
> + };
> +
> + ethernet at 70000 {
> + status = "okay";
> + phy = <&phy0>;
> + phy-mode = "rgmii-id";
> + };
> +
> + ethernet at 74000 {
> + status = "okay";
> + phy = <&phy1>;
> + phy-mode = "rgmii-id";
> + };
> +
> + usb at 50000 {
> + status = "okay";
> + };
> +
> + usb at 51000 {
> + status = "okay";
> + };
> +
> + i2c at 11000 {
> + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + adt7473 at 2e {
> + compatible = "adt7473";
> + reg = <0x2e>;
> + };
> +
> + pcf8563 at 51 {
> + compatible = "pcf8563";
> + reg = <0x51>;
> + };
> +
> + };
> + nand at d0000 {
> + status = "okay";
> + num-cs = <1>;
> + marvell,nand-keep-config;
> + marvell,nand-enable-arbiter;
> + nand-on-flash-bbt;
> +
> + partition at 0 {
> + label = "u-boot";
> + reg = <0x0000000 0xe0000>;
> + read-only;
> + };
> +
> + partition at e0000 {
> + label = "u-boot-env";
> + reg = <0xe0000 0x20000>;
> + read-only;
> + };
> +
> + partition at 100000 {
> + label = "u-boot-env2";
> + reg = <0x100000 0x20000>;
> + read-only;
> + };
> +
> + partition at 120000 {
> + label = "zImage";
> + reg = <0x120000 0x400000>;
> + };
> +
> + partition at 520000 {
> + label = "initrd";
> + reg = <0x520000 0x400000>;
> + };
> + partition at xE00000 {
> + label = "boot";
> + reg = <0xE00000 0x3F200000>;
> + };
> + partition at flash {
> + label = "flash";
> + reg = <0x0 0x40000000>;
> + };
> + };
> +
> + };
> + };
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-0 = <&power_button_pin &reset_button_pin &select_button_pin &scroll_button_pin>;
> + pinctrl-names = "default";
> +
> + power-button {
> + label = "Power Button";
> + linux,code = <KEY_POWER>;
> + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
> + };
> + reset-button {
> + label = "Reset Button";
> + linux,code = <KEY_RESTART>;
> + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
> + };
> + select-button {
> + label = "Select Button";
> + linux,code = <BTN_SELECT>;
> + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> + };
> + scroll-button {
> + label = "Scroll Button";
> + linux,code = <KEY_SCROLLDOWN>;
> + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + spi3 {
> + compatible = "spi-gpio";
> + status = "okay";
> + gpio-sck = <&gpio0 25 0>;
> + gpio-mosi = <&gpio1 15 0>; /*gpio 47*/
> + cs-gpios = <&gpio0 27 0 >;
> + num-chipselects = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio2: gpio2 at 0 {
> + compatible = "fairchild,74hc595";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0>;
> + registers-number = <2>;
> + spi-max-frequency = <100000>;
> + };
> + };
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&hdd_led_pin>;
> + pinctrl-names = "default";
> +
> + hdd-led {
> + label = "ix4300d:blue:hdd";
> + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + power-led {
> + label = "ix4300d:power";
> + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
> + linux,default-trigger = "timer"; /* init blinking while booting */
> + default-state = "on";
> + };
> +
> + sysfail-led {
> + label = "ix4300d:sysfail:red";
> + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> + sys-led {
> + label = "ix4300d:sys:blue";
> + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> + hddfail-led {
> + label = "ix4300d:hddfail:red";
> + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + };
> + /* warning: you need both eth1 & 0 to be initialize for poweroff to shutdown otherwise it reboots */
> + gpio-poweroff {
> + compatible = "gpio-poweroff";
> + pinctrl-0 = <&poweroff>;
> + pinctrl-names = "default";
> + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
> + };
> +
> +};
> --
> 1.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v4 3/3] crypto: Add Allwinner Security System crypto accelerator
From: Maxime Ripard @ 2014-07-23 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140723131620.GC29178@gondor.apana.org.au>
Hi,
On Wed, Jul 23, 2014 at 09:16:20PM +0800, Herbert Xu wrote:
> On Sat, Jul 12, 2014 at 02:59:13PM +0200, LABBE Corentin wrote:
> > Add support for the Security System included in Allwinner SoC A20.
> > The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms.
> >
> > Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
>
> This is essentially a synchronous driver, no? If so please
> switch to the blkcipher/shash interface.
The exact opposite has been asked for during v1's review...
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 2/2] Adding lenovo in vendor
From: Jason Cooper @ 2014-07-23 13:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406117232-5962-2-git-send-email-yahoo@perenite.com>
Benoit,
The same comments regard patch submission apply to this one as well.
On Wed, Jul 23, 2014 at 05:07:12AM -0700, benoitm974 wrote:
Please add a commit entry here describing Lenovo. Keep it short and
sweet and maybe a link to their webpage.
> Signed-off-by: benoitm974 <yahoo@perenite.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 46a311e..de81a87 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -72,6 +72,7 @@ keymile Keymile GmbH
> lacie LaCie
> lantiq Lantiq Semiconductor
> lg LG Corporation
> +lenovo LENOVO
is this their official, registered company name?
> linux Linux-specific binding
> lsi LSI Corp. (LSI Logic)
> lltc Linear Technology Corporation
thx,
Jason.
^ permalink raw reply
* [PATCH 1/2] Added dts defintion for Lenovo ix4-300d nas
From: Jason Cooper @ 2014-07-23 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406117232-5962-1-git-send-email-yahoo@perenite.com>
Benoit,
Thanks for the patch! A few minor things:
Please Cc: the mvebu maintainers patches regarding Armada XP SoCs, I
almost missed this. ;-)
I know, we probably need to update MAINTAINERS for the dts{i} files...
Also, Please adjust your Subject line to start with "ARM: mvebu: ...",
you can use 'git log --oneline -- arch/arm/boot/dts/armada*' to get an
idea of what we prefer to see.
On Wed, Jul 23, 2014 at 05:07:11AM -0700, benoitm974 wrote:
> Signed-off-by: benoitm974 <yahoo@perenite.com>
Please use your real name here, as well as in the From: of the email.
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts | 267 +++++++++++++++++++++++++
> 2 files changed, 268 insertions(+)
> create mode 100644 arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index adb5ed9..f759dd2 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -438,6 +438,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
> armada-xp-db.dtb \
> armada-xp-gp.dtb \
> armada-xp-netgear-rn2120.dtb \
> + armada-xp-lenovo-ix4300d.dtb \
> armada-xp-matrix.dtb \
> armada-xp-openblocks-ax3-4.dtb
Please place in alphabetical order. Yes, I know it wasn't to begin
with. :( Feel free to fix it up while you are adding your line.
> dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
> diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts
> new file mode 100644
> index 0000000..e04e7a6
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts
> @@ -0,0 +1,267 @@
> +/*
> + * Device Tree file for LENOVO IX4-300d
> + *
> + * Copyright (C) 2014, Benoit Masson <yahoo@perenite.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include "armada-xp-mv78230.dtsi"
> +
> +/ {
> + model = "LENOVO IX4-300d";
> + compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
> +
> + chosen {
> + bootargs = "console=ttyS0,115200 earlyprintk";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x00000000 0 0x20000000>; /* 512MB */
> + };
> +
> + soc {
> + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
> + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
> +
> + pcie-controller {
> + status = "okay";
> +
> + pcie at 1,0 {
> + /* Port 0, Lane 0 */
> + status = "okay";
> + };
> + pcie at 5,0 {
> + /* Port 1, Lane 0 */
> + status = "okay";
> + };
> +
spurious extra line, and it looks like you have some whitespace issues.
Please make sure you use leading tabs.
> + };
> +
> + internal-regs {
> + pinctrl {
> + poweroff: poweroff {
> + marvell,pins = "mpp24";
> + marvell,function = "gpio";
> + };
> +
> + power_button_pin: power-button-pin {
> + marvell,pins = "mpp44";
> + marvell,function = "gpio";
> + };
> +
> + reset_button_pin: reset-button-pin {
> + marvell,pins = "mpp45";
> + marvell,function = "gpio";
> + };
> + select_button_pin: select-button-pin {
> + marvell,pins = "mpp41";
> + marvell,function = "gpio";
> + };
> +
> + scroll_button_pin: scroll-button-pin {
> + marvell,pins = "mpp42";
> + marvell,function = "gpio";
> + };
> + hdd_led_pin: hdd-led-pin {
> + marvell,pins = "mpp26";
> + marvell,function = "gpio";
> + };
More leading tabs issues in this block.
> + };
> +
> + serial at 12000 {
> + clocks = <&coreclk 0>;
> + status = "okay";
> + };
> +
> + mdio {
> + phy0: ethernet-phy at 0 { /* Marvell 88E1318 */
> + reg = <0>;
> + };
> +
> + phy1: ethernet-phy at 1 { /* Marvell 88E1318 */
> + reg = <1>;
> + };
> + };
> +
> + ethernet at 70000 {
> + status = "okay";
> + phy = <&phy0>;
> + phy-mode = "rgmii-id";
> + };
> +
> + ethernet at 74000 {
> + status = "okay";
> + phy = <&phy1>;
> + phy-mode = "rgmii-id";
> + };
> +
> + usb at 50000 {
> + status = "okay";
> + };
> +
> + usb at 51000 {
> + status = "okay";
> + };
And here.
> +
> + i2c at 11000 {
> + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
> + clock-frequency = <400000>;
And here.
> + status = "okay";
> +
> + adt7473 at 2e {
> + compatible = "adt7473";
> + reg = <0x2e>;
> + };
> +
> + pcf8563 at 51 {
> + compatible = "pcf8563";
> + reg = <0x51>;
> + };
> +
> + };
Need an empty line here.
> + nand at d0000 {
> + status = "okay";
> + num-cs = <1>;
> + marvell,nand-keep-config;
> + marvell,nand-enable-arbiter;
> + nand-on-flash-bbt;
> +
> + partition at 0 {
> + label = "u-boot";
> + reg = <0x0000000 0xe0000>;
> + read-only;
> + };
> +
> + partition at e0000 {
> + label = "u-boot-env";
> + reg = <0xe0000 0x20000>;
> + read-only;
> + };
> +
> + partition at 100000 {
> + label = "u-boot-env2";
> + reg = <0x100000 0x20000>;
> + read-only;
> + };
> +
> + partition at 120000 {
> + label = "zImage";
> + reg = <0x120000 0x400000>;
> + };
> +
> + partition at 520000 {
> + label = "initrd";
> + reg = <0x520000 0x400000>;
> + };
> + partition at xE00000 {
> + label = "boot";
> + reg = <0xE00000 0x3F200000>;
> + };
> + partition at flash {
> + label = "flash";
> + reg = <0x0 0x40000000>;
> + };
> + };
> +
Don't need this empty line.
> + };
> + };
Empty line here.
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-0 = <&power_button_pin &reset_button_pin &select_button_pin &scroll_button_pin>;
Yeah... I think you get the point ;-) please check the rest of the
patch. I'll stop mentioning it.
> + pinctrl-names = "default";
> +
> + power-button {
> + label = "Power Button";
> + linux,code = <KEY_POWER>;
> + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
> + };
> + reset-button {
> + label = "Reset Button";
> + linux,code = <KEY_RESTART>;
> + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
> + };
> + select-button {
> + label = "Select Button";
> + linux,code = <BTN_SELECT>;
> + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> + };
> + scroll-button {
> + label = "Scroll Button";
> + linux,code = <KEY_SCROLLDOWN>;
> + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + spi3 {
> + compatible = "spi-gpio";
> + status = "okay";
> + gpio-sck = <&gpio0 25 0>;
> + gpio-mosi = <&gpio1 15 0>; /*gpio 47*/
> + cs-gpios = <&gpio0 27 0 >;
I know no one else does it, but please use GPIO_ACTIVE_HIGH for these
three.
> + num-chipselects = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio2: gpio2 at 0 {
> + compatible = "fairchild,74hc595";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0>;
> + registers-number = <2>;
> + spi-max-frequency = <100000>;
> + };
> + };
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&hdd_led_pin>;
> + pinctrl-names = "default";
> +
> + hdd-led {
> + label = "ix4300d:blue:hdd";
> + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + power-led {
> + label = "ix4300d:power";
> + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
> + linux,default-trigger = "timer"; /* init blinking while booting */
Watch >80 char lines.
> + default-state = "on";
> + };
> +
> + sysfail-led {
> + label = "ix4300d:sysfail:red";
> + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> + sys-led {
> + label = "ix4300d:sys:blue";
> + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> + hddfail-led {
> + label = "ix4300d:hddfail:red";
> + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + };
> + /* warning: you need both eth1 & 0 to be initialize for poweroff to shutdown otherwise it reboots */
Same here, please convert to multi-line comment.
> + gpio-poweroff {
> + compatible = "gpio-poweroff";
> + pinctrl-0 = <&poweroff>;
> + pinctrl-names = "default";
> + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
> + };
> +
> +};
This is a great first version, it really just a bunch of minor details
to fixup for v2. Please Cc myself, Andrew, Gregory, and Sebastian when
you send v2. I've included them in the Cc.
thx,
Jason.
^ permalink raw reply
* [PATCH 1/4] tracepoint: add generic tracepoint definitions for IPI tracing
From: Daniel Lezcano @ 2014-07-23 13:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405660735-13408-2-git-send-email-nicolas.pitre@linaro.org>
On 07/18/2014 07:18 AM, Nicolas Pitre wrote:
> The Inter Processor Interrupt is used to make another processor do a
> specific action such as rescheduling tasks, signal a timer event or
> execute something in another CPU's context. IRQs are already traceable
> but IPIs were not. Tracing them is useful for monitoring IPI latency,
> or to verify when they are the source of CPU wake-ups with power
> management implications.
>
> Three trace hooks are defined: ipi_raise, ipi_entry and ipi_exit. To make
> them portable, a string is used to identify them and correlate related
> events. Additionally, ipi_raise records a bitmask representing targeted
> CPUs.
>
> Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
> include/trace/events/ipi.h | 89 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
> create mode 100644 include/trace/events/ipi.h
>
> diff --git a/include/trace/events/ipi.h b/include/trace/events/ipi.h
> new file mode 100644
> index 0000000000..834a7362a6
> --- /dev/null
> +++ b/include/trace/events/ipi.h
> @@ -0,0 +1,89 @@
> +#undef TRACE_SYSTEM
> +#define TRACE_SYSTEM ipi
> +
> +#if !defined(_TRACE_IPI_H) || defined(TRACE_HEADER_MULTI_READ)
> +#define _TRACE_IPI_H
> +
> +#include <linux/tracepoint.h>
> +
> +/**
> + * ipi_raise - called when a smp cross call is made
> + *
> + * @mask: mask of recipient CPUs for the IPI
> + * @reason: string identifying the IPI purpose
> + *
> + * It is necessary for @reason to be a static string declared with
> + * __tracepoint_string.
> + */
> +TRACE_EVENT(ipi_raise,
> +
> + TP_PROTO(const struct cpumask *mask, const char *reason),
> +
> + TP_ARGS(mask, reason),
> +
> + TP_STRUCT__entry(
> + __bitmask(target_cpus, nr_cpumask_bits)
> + __field(const char *, reason)
> + ),
> +
> + TP_fast_assign(
> + __assign_bitmask(target_cpus, cpumask_bits(mask), nr_cpumask_bits);
> + __entry->reason = reason;
> + ),
> +
> + TP_printk("target_mask=%s (%s)", __get_bitmask(target_cpus), __entry->reason)
> +);
> +
> +DECLARE_EVENT_CLASS(ipi_handler,
> +
> + TP_PROTO(const char *reason),
> +
> + TP_ARGS(reason),
> +
> + TP_STRUCT__entry(
> + __field(const char *, reason)
> + ),
> +
> + TP_fast_assign(
> + __entry->reason = reason;
> + ),
> +
> + TP_printk("(%s)", __entry->reason)
> +);
> +
> +/**
> + * ipi_entry - called immediately before the IPI handler
> + *
> + * @reason: string identifying the IPI purpose
> + *
> + * It is necessary for @reason to be a static string declared with
> + * __tracepoint_string, ideally the same as used with trace_ipi_raise
> + * for that IPI.
> + */
> +DEFINE_EVENT(ipi_handler, ipi_entry,
> +
> + TP_PROTO(const char *reason),
> +
> + TP_ARGS(reason)
> +);
> +
> +/**
> + * ipi_exit - called immediately after the IPI handler returns
> + *
> + * @reason: string identifying the IPI purpose
> + *
> + * It is necessary for @reason to be a static string declared with
> + * __tracepoint_string, ideally the same as used with trace_ipi_raise for
> + * that IPI.
> + */
> +DEFINE_EVENT(ipi_handler, ipi_exit,
> +
> + TP_PROTO(const char *reason),
> +
> + TP_ARGS(reason)
> +);
> +
> +#endif /* _TRACE_IPI_H */
> +
> +/* This part must be outside protection */
> +#include <trace/define_trace.h>
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH v4 3/3] crypto: Add Allwinner Security System crypto accelerator
From: Herbert Xu @ 2014-07-23 13:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405169953-13695-4-git-send-email-clabbe.montjoie@gmail.com>
On Sat, Jul 12, 2014 at 02:59:13PM +0200, LABBE Corentin wrote:
> Add support for the Security System included in Allwinner SoC A20.
> The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms.
>
> Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
This is essentially a synchronous driver, no? If so please
switch to the blkcipher/shash interface.
Thanks,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH] ARM: zynq: DT: Add CAN node
From: Michal Simek @ 2014-07-23 13:05 UTC (permalink / raw)
To: linux-arm-kernel
Add node describing Zynq's CAN controller.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/boot/dts/zynq-7000.dtsi | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 366ca6434f54..2287d9b4ed1a 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -71,7 +71,18 @@
interrupts = <0 7 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 12>;
- };
+ };
+
+ can0: can at e0008000 {
+ compatible = "xlnx,zynq-can-1.0";
+ clocks = <&clkc 19>, <&clkc 36>;
+ clock-names = "can_clk", "pclk";
+ reg = <0xe0008000 0x1000>;
+ interrupts = <0 28 4>;
+ interrupt-parent = <&intc>;
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
gpio0: gpio at e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
--
1.8.2.3
-------------- next part --------------
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^ permalink raw reply related
* [PATCH RFC] arm/mach-imximx/iomux-v3: Do not export symbol without public declaration
From: Alexander Stein @ 2014-07-23 13:02 UTC (permalink / raw)
To: linux-arm-kernel
Both mxc_iomux_v3_setup_pad and mxc_iomux_v3_setup_multiple_pads are
declared in iomux-v3.h which can't be used in any module. None of the
objects in this directory is tristate. Neither can the header be included
in out-of-tree modules.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
---
arch/arm/mach-imx/iomux-v3.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index 9dae74bf47fc..d61f9606fc56 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -55,7 +55,6 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
return 0;
}
-EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
{
@@ -71,7 +70,6 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
}
return 0;
}
-EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
{
--
1.8.5.5
^ permalink raw reply related
* [PATCHv3 16/16] ARM: mvebu: defconfig: enable cpuidle support in mvebu_v7_defconfig
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Marvell EBU SoCs such as Armada 370, Armada XP or Armada 38x now
support cpuidle, so this commit enables the appropriate Kconfig
options in mvebu_v7_defconfig.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/configs/mvebu_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index e11170e..b174072 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -28,6 +28,8 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_MVEBU_V7_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NET=y
CONFIG_INET=y
--
2.0.0
^ permalink raw reply related
* [PATCHv3 15/16] ARM: mvebu: add cpuidle support for Armada 38x
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Unlike the Armada XP and the Armada 370, this SoC uses a Cortex A9
core. Consequently, the procedure to enter the idle state is
different: interaction with the SCU, not disabling snooping, etc.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 85 ++++++++++++++++++++++++++++++++++++++++++-
arch/arm/mach-mvebu/pmsu_ll.S | 14 +++++++
2 files changed, 98 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 9190ae8..bd7c66a 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -29,6 +29,7 @@
#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
+#include <asm/smp_scu.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include <asm/tlbflush.h>
@@ -63,6 +64,18 @@
#define L2C_NFABRIC_PM_CTL 0x4
#define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
+/* PMSU delay registers */
+#define PMSU_POWERDOWN_DELAY 0xF04
+#define PMSU_POWERDOWN_DELAY_PMU BIT(1)
+#define PMSU_POWERDOWN_DELAY_MASK 0xFFFE
+#define PMSU_DFLT_ARMADA38X_DELAY 0x64
+
+/* CA9 MPcore SoC Control registers */
+
+#define MPCORE_RESET_CTL 0x64
+#define MPCORE_RESET_CTL_L2 BIT(0)
+#define MPCORE_RESET_CTL_DEBUG BIT(16)
+
#define SRAM_PHYS_BASE 0xFFFF0000
#define BOOTROM_BASE 0xFFF00000
#define BOOTROM_SIZE 0x100000
@@ -74,6 +87,8 @@ extern void ll_disable_coherency(void);
extern void ll_enable_coherency(void);
extern void armada_370_xp_cpu_resume(void);
+extern void armada_38x_cpu_resume(void);
+
static phys_addr_t pmsu_mp_phys_base;
static void __iomem *pmsu_mp_base;
@@ -287,6 +302,32 @@ static int armada_370_xp_cpu_suspend(unsigned long deepidle)
return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
}
+static int armada_38x_do_cpu_suspend(unsigned long deepidle)
+{
+ unsigned long flags = 0;
+
+ if (deepidle)
+ flags |= PMSU_PREPARE_DEEP_IDLE;
+
+ mvebu_v7_pmsu_idle_prepare(flags);
+ /*
+ * Already flushed cache, but do it again as the outer cache
+ * functions dirty the cache with spinlocks
+ */
+ v7_exit_coherency_flush(louis);
+
+ scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);
+
+ cpu_do_idle();
+
+ return 1;
+}
+
+static int armada_38x_cpu_suspend(unsigned long deepidle)
+{
+ return cpu_suspend(false, armada_38x_do_cpu_suspend);
+}
+
/* No locking is needed because we only access per-CPU registers */
void mvebu_v7_pmsu_idle_exit(void)
{
@@ -295,7 +336,6 @@ void mvebu_v7_pmsu_idle_exit(void)
if (pmsu_mp_base == NULL)
return;
-
/* cancel ask HW to power down the L2 Cache if possible */
reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
@@ -359,6 +399,47 @@ static __init int armada_370_cpuidle_init(void)
return 0;
}
+static __init int armada_38x_cpuidle_init(void)
+{
+ struct device_node *np;
+ void __iomem *mpsoc_base;
+ u32 reg;
+
+ np = of_find_compatible_node(NULL, NULL,
+ "marvell,armada-380-coherency-fabric");
+ if (!np)
+ return -ENODEV;
+ of_node_put(np);
+
+ np = of_find_compatible_node(NULL, NULL,
+ "marvell,armada-380-mpcore-soc-ctrl");
+ if (!np)
+ return -ENODEV;
+ mpsoc_base = of_iomap(np, 0);
+ BUG_ON(!mpsoc_base);
+ of_node_put(np);
+
+ /* Set up reset mask when powering down the cpus */
+ reg = readl(mpsoc_base + MPCORE_RESET_CTL);
+ reg |= MPCORE_RESET_CTL_L2;
+ reg |= MPCORE_RESET_CTL_DEBUG;
+ writel(reg, mpsoc_base + MPCORE_RESET_CTL);
+ iounmap(mpsoc_base);
+
+ /* Set up delay */
+ reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
+ reg &= ~PMSU_POWERDOWN_DELAY_MASK;
+ reg |= PMSU_DFLT_ARMADA38X_DELAY;
+ reg |= PMSU_POWERDOWN_DELAY_PMU;
+ writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
+
+ mvebu_cpu_resume = armada_38x_cpu_resume;
+ mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
+ mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
+
+ return 0;
+}
+
static __init int armada_xp_cpuidle_init(void)
{
struct device_node *np;
@@ -389,6 +470,8 @@ static int __init mvebu_v7_cpu_pm_init(void)
ret = armada_xp_cpuidle_init();
else if (of_machine_is_compatible("marvell,armada370"))
ret = armada_370_cpuidle_init();
+ else if (of_machine_is_compatible("marvell,armada380"))
+ ret = armada_38x_cpuidle_init();
else
return 0;
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index 17d7f3b..a945756 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -23,6 +23,20 @@ ARM_BE8(setend be ) @ go BE8 if entered LE
b cpu_resume
ENDPROC(armada_370_xp_cpu_resume)
+ENTRY(armada_38x_cpu_resume)
+ /* do we need it for Armada 38x*/
+ARM_BE8(setend be ) @ go BE8 if entered LE
+ bl v7_invalidate_l1
+ mrc p15, 4, r1, c15, c0 @ get SCU base address
+ orr r1, r1, #0x8 @ SCU CPU Power Status Register
+ mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
+ and r0, r0, #15
+ add r1, r1, r0
+ mov r0, #0x0
+ strb r0, [r1] @ switch SCU power state to Normal mode
+ b cpu_resume
+ENDPROC(armada_38x_cpu_resume)
+
.global mvebu_boot_wa_start
.global mvebu_boot_wa_end
--
2.0.0
^ permalink raw reply related
* [PATCHv3 14/16] ARM: mvebu: add cpuidle support for Armada 370
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit introduces the cpuidle support for Armada 370. The main
difference compared to the already supported Armada XP is that the
Armada 370 has an issue caused by "a slow exit process from the deep
idle state due to heavy L1/L2 cache cleanup operations performed by
the BootROM software" (cf errata GL-BootROM-10).
To work around this issue, we replace the restart code of the BootROM
by some custom code located in an internal SRAM. For this purpose, we
use the common function mvebu_boot_addr_wa() introduced in the commit
"ARM: mvebu: Add a common function for the boot address work around".
The message in case of failure to suspend the system was switched from
the warn level to the debug level. Indeed due to the "slow exit
process from the deep idle state" in Armada 370, this situation
happens quite often. Using the debug level avoids spamming the kernel
logs, but still allows to enable it if needed.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 51 +++++++++++++++++++++++++++++++++++++++-------
1 file changed, 44 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 0cd2d09..9190ae8 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -34,7 +34,6 @@
#include <asm/tlbflush.h>
#include "common.h"
-static void __iomem *pmsu_mp_base;
#define PMSU_BASE_OFFSET 0x100
#define PMSU_REG_SIZE 0x1000
@@ -68,17 +67,18 @@ static void __iomem *pmsu_mp_base;
#define BOOTROM_BASE 0xFFF00000
#define BOOTROM_SIZE 0x100000
+#define ARMADA_370_CRYPT0_ENG_TARGET 0x9
+#define ARMADA_370_CRYPT0_ENG_ATTR 0x1
+
extern void ll_disable_coherency(void);
extern void ll_enable_coherency(void);
extern void armada_370_xp_cpu_resume(void);
+static phys_addr_t pmsu_mp_phys_base;
+static void __iomem *pmsu_mp_base;
static void *mvebu_cpu_resume;
-static struct platform_device mvebu_v7_cpuidle_device = {
- .name = "cpuidle-armada-xp",
-};
-
static struct of_device_id of_pmsu_table[] = {
{ .compatible = "marvell,armada-370-pmsu", },
{ .compatible = "marvell,armada-370-xp-pmsu", },
@@ -165,6 +165,8 @@ static int __init mvebu_v7_pmsu_init(void)
goto out;
}
+ pmsu_mp_phys_base = res.start;
+
pmsu_mp_base = ioremap(res.start, resource_size(&res));
if (!pmsu_mp_base) {
pr_err("unable to map registers\n");
@@ -275,7 +277,7 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
"isb "
: : : "r0");
- pr_warn("Failed to suspend the system\n");
+ pr_debug("Failed to suspend the system\n");
return 0;
}
@@ -325,7 +327,39 @@ static struct notifier_block mvebu_v7_cpu_pm_notifier = {
.notifier_call = mvebu_v7_cpu_pm_notify,
};
-static int __init armada_xp_cpuidle_init(void)
+static struct platform_device mvebu_v7_cpuidle_device;
+
+static __init int armada_370_cpuidle_init(void)
+{
+ struct device_node *np;
+ phys_addr_t redirect_reg;
+
+ np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
+ if (!np)
+ return -ENODEV;
+ of_node_put(np);
+
+ /*
+ * On Armada 370, there is "a slow exit process from the deep
+ * idle state due to heavy L1/L2 cache cleanup operations
+ * performed by the BootROM software". To avoid this, we
+ * replace the restart code of the bootrom by a a simple jump
+ * to the boot address. Then the code located at this boot
+ * address will take care of the initialization.
+ */
+ redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
+ mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
+ ARMADA_370_CRYPT0_ENG_ATTR,
+ redirect_reg);
+
+ mvebu_cpu_resume = armada_370_xp_cpu_resume;
+ mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
+ mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
+
+ return 0;
+}
+
+static __init int armada_xp_cpuidle_init(void)
{
struct device_node *np;
@@ -336,6 +370,7 @@ static int __init armada_xp_cpuidle_init(void)
mvebu_cpu_resume = armada_370_xp_cpu_resume;
mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
+ mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
return 0;
}
@@ -352,6 +387,8 @@ static int __init mvebu_v7_cpu_pm_init(void)
if (of_machine_is_compatible("marvell,armadaxp"))
ret = armada_xp_cpuidle_init();
+ else if (of_machine_is_compatible("marvell,armada370"))
+ ret = armada_370_cpuidle_init();
else
return 0;
--
2.0.0
^ permalink raw reply related
* [PATCHv3 13/16] cpuidle: mvebu: add Armada 38x support
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
This commit adds the list of cpuidle states supported by the Armada
38x SoC in the cpuidle-mvebu-v7 driver, as well as the necessary logic
around it to support this SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/cpuidle/cpuidle-mvebu-v7.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/cpuidle/cpuidle-mvebu-v7.c b/drivers/cpuidle/cpuidle-mvebu-v7.c
index d23597f..45371bb 100644
--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
@@ -1,5 +1,5 @@
/*
- * Marvell Armada 370 and Armada XP SoC cpuidle driver
+ * Marvell Armada 370, 38x and XP SoC cpuidle driver
*
* Copyright (C) 2014 Marvell
*
@@ -86,6 +86,21 @@ static struct cpuidle_driver armada370_idle_driver = {
.state_count = 2,
};
+static struct cpuidle_driver armada38x_idle_driver = {
+ .name = "armada_38x_idle",
+ .states[0] = ARM_CPUIDLE_WFI_STATE,
+ .states[1] = {
+ .enter = mvebu_v7_enter_idle,
+ .exit_latency = 10,
+ .power_usage = 5,
+ .target_residency = 100,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .name = "Idle",
+ .desc = "CPU and SCU power down",
+ },
+ .state_count = 2,
+};
+
static int mvebu_v7_cpuidle_probe(struct platform_device *pdev)
{
mvebu_v7_cpu_suspend = pdev->dev.platform_data;
@@ -94,6 +109,8 @@ static int mvebu_v7_cpuidle_probe(struct platform_device *pdev)
return cpuidle_register(&armadaxp_idle_driver, NULL);
else if (!strcmp(pdev->dev.driver->name, "cpuidle-armada-370"))
return cpuidle_register(&armada370_idle_driver, NULL);
+ else if (!strcmp(pdev->dev.driver->name, "cpuidle-armada-38x"))
+ return cpuidle_register(&armada38x_idle_driver, NULL);
else
return -EINVAL;
}
@@ -118,6 +135,16 @@ static struct platform_driver armada370_cpuidle_plat_driver = {
module_platform_driver(armada370_cpuidle_plat_driver);
+static struct platform_driver armada38x_cpuidle_plat_driver = {
+ .driver = {
+ .name = "cpuidle-armada-38x",
+ .owner = THIS_MODULE,
+ },
+ .probe = mvebu_v7_cpuidle_probe,
+};
+
+module_platform_driver(armada38x_cpuidle_plat_driver);
+
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
MODULE_DESCRIPTION("Marvell EBU v7 cpuidle driver");
MODULE_LICENSE("GPL");
--
2.0.0
^ permalink raw reply related
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