Linux-ARM-Kernel Archive on lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH V6 1/5] PCI/ACPI: Extend pci_mcfg_lookup() responsibilities
From: Tomasz Nowicki @ 2016-09-09 19:24 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1473449047-10499-1-git-send-email-tn@semihalf.com>

In preparation for adding MCFG platform specific quirk handling move
CFG resource calculation and ECAM ops assignment to pci_mcfg_lookup().
It becomes the gate for further ops and CFG resource manipulation
in arch-agnostic code (drivers/acpi/pci_mcfg.c).

No functionality changes in this patch.

Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
---
 arch/arm64/kernel/pci.c  | 17 +++++------------
 drivers/acpi/pci_mcfg.c  | 28 +++++++++++++++++++++++++---
 include/linux/pci-acpi.h |  4 +++-
 3 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index acf3872..fb439c7 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -125,24 +125,17 @@ pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root)
 	u16 seg = root->segment;
 	struct pci_config_window *cfg;
 	struct resource cfgres;
-	unsigned int bsz;
+	struct pci_ecam_ops *ecam_ops;
+	int ret;
 
-	/* Use address from _CBA if present, otherwise lookup MCFG */
-	if (!root->mcfg_addr)
-		root->mcfg_addr = pci_mcfg_lookup(seg, bus_res);
-
-	if (!root->mcfg_addr) {
+	ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops);
+	if (ret) {
 		dev_err(&root->device->dev, "%04x:%pR ECAM region not found\n",
 			seg, bus_res);
 		return NULL;
 	}
 
-	bsz = 1 << pci_generic_ecam_ops.bus_shift;
-	cfgres.start = root->mcfg_addr + bus_res->start * bsz;
-	cfgres.end = cfgres.start + resource_size(bus_res) * bsz - 1;
-	cfgres.flags = IORESOURCE_MEM;
-	cfg = pci_ecam_create(&root->device->dev, &cfgres, bus_res,
-			      &pci_generic_ecam_ops);
+	cfg = pci_ecam_create(&root->device->dev, &cfgres, bus_res, ecam_ops);
 	if (IS_ERR(cfg)) {
 		dev_err(&root->device->dev, "%04x:%pR error %ld mapping ECAM\n",
 			seg, bus_res, PTR_ERR(cfg));
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index b5b376e..ffcc651 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -22,6 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/pci-acpi.h>
+#include <linux/pci-ecam.h>
 
 /* Structure to hold entries from the MCFG table */
 struct mcfg_entry {
@@ -35,9 +36,18 @@ struct mcfg_entry {
 /* List to save MCFG entries */
 static LIST_HEAD(pci_mcfg_list);
 
-phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res)
+int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
+		    struct pci_ecam_ops **ecam_ops)
 {
+	struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
+	struct resource *bus_res = &root->secondary;
+	u16 seg = root->segment;
 	struct mcfg_entry *e;
+	struct resource res;
+
+	/* Use address from _CBA if present, otherwise lookup MCFG */
+	if (root->mcfg_addr)
+		goto skip_lookup;
 
 	/*
 	 * We expect exact match, unless MCFG entry end bus covers more than
@@ -45,10 +55,22 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res)
 	 */
 	list_for_each_entry(e, &pci_mcfg_list, list) {
 		if (e->segment == seg && e->bus_start == bus_res->start &&
-		    e->bus_end >= bus_res->end)
-			return e->addr;
+		    e->bus_end >= bus_res->end) {
+			root->mcfg_addr = e->addr;
+		}
+
 	}
 
+	if (!root->mcfg_addr)
+		return -ENXIO;
+
+skip_lookup:
+	memset(&res, 0, sizeof(res));
+	res.start = root->mcfg_addr + (bus_res->start << 20);
+	res.end = res.start + (resource_size(bus_res) << 20) - 1;
+	res.flags = IORESOURCE_MEM;
+	*cfgres = res;
+	*ecam_ops = ops;
 	return 0;
 }
 
diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 7d63a66..7a4e83a 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -24,7 +24,9 @@ static inline acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev)
 }
 extern phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle);
 
-extern phys_addr_t pci_mcfg_lookup(u16 domain, struct resource *bus_res);
+struct pci_ecam_ops;
+extern int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
+			   struct pci_ecam_ops **ecam_ops);
 
 static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
 {
-- 
1.9.1

^ permalink raw reply related

* [PATCH V6 0/5] ECAM quirks handling for ARM64 platforms
From: Tomasz Nowicki @ 2016-09-09 19:24 UTC (permalink / raw)
  To: linux-arm-kernel

Quirk handling relies on an idea of simple static array which contains
quirk enties. Each entry consists of identification information (IDs from
standard header of MCFG table) along with custom pci_ecam_ops structure and 
configuration space resource structure. This way it is possible find
corresponding quirk entries and override pci_ecam_ops and PCI configuration
space regions.

As an example, the last 3 patches present quirk handling mechanism usage for
ThunderX.

v5 -> v6
- rebase against v4.8-rc5
- drop patch 1 form previous series
- keep pci_acpi_setup_ecam_mapping() in ARM64 arch directory
- move quirk code to pci_mcfg.c
- restrict quirk to override pci_ecam_ops and CFG resource structure
  only, no init call any more
- split ThunderX quirks into the smaller chunks
- add ThunderX pass1.x silicon revision support

v4 -> v5
- rebase against v4.8-rc1
- rework to exact MCFG OEM ID, TABLE ID, rev match
  - use memcmp instead of strncmp
  - no substring match
- fix typos and dmesg message

Tomasz Nowicki (5):
  PCI/ACPI: Extend pci_mcfg_lookup() responsibilities
  PCI/ACPI: Check platform specific ECAM quirks
  PCI: thunder-pem: Allow to probe PEM-specific register range for ACPI
    case
  PCI: thunder: Enable ACPI PCI controller for ThunderX pass2.x silicon
    version
  PCI: thunder: Enable ACPI PCI controller for ThunderX pass1.x silicon
    version

 arch/arm64/kernel/pci.c             |  17 ++--
 drivers/acpi/pci_mcfg.c             | 168 +++++++++++++++++++++++++++++++++++-
 drivers/pci/host/pci-thunder-ecam.c |   2 +-
 drivers/pci/host/pci-thunder-pem.c  |  63 +++++++++++---
 include/linux/pci-acpi.h            |   4 +-
 include/linux/pci-ecam.h            |   7 ++
 6 files changed, 230 insertions(+), 31 deletions(-)

-- 
1.9.1

^ permalink raw reply

* [PATCH 1/2] ARM: clk-imx35: fix name for ckil clk
From: Uwe Kleine-König @ 2016-09-09 19:15 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20160909181138.GD7243@codeaurora.org>

On Fri, Sep 09, 2016 at 11:11:38AM -0700, Stephen Boyd wrote:
> On 09/09, Uwe Kleine-K?nig wrote:
> > To += mturquette, sboyd
> > 
> > Hello Shawn, hello Michael, hello Stephen,
> > 
> > On Fri, Sep 09, 2016 at 02:16:31PM +0800, Shawn Guo wrote:
> > > On Thu, Sep 08, 2016 at 11:30:21AM +0200, Uwe Kleine-K?nig wrote:
> > > > This fixes
> > > > 	[    0.000000] i.MX clk 82: register failed with -17
> > > > because the name is duplicated.
> > > > 
> > > > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> > > 
> > > I did not queue any clock patches for this cycle.  Can you please send
> > > the patches directly to clock maintainers?
> > 
> > @shawnguo: Is this an ack?
> > @mturquette, sboyd: should I resend? IMHO the first patch should go in
> > soon.
> 
> Does the first patch need a fixes tag? We can apply them
> directly.

The breakage was introduced by v4.3-rc2~4^2~71^2, i.e.
3713e3f5e927 (clk: imx35: define two clocks for rtc).

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

^ permalink raw reply

* [RFC] misc: Add Allwinner Q8 tablet hardware manager
From: Pantelis Antoniou @ 2016-09-09 19:13 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20160901190820.21987-2-hdegoede@redhat.com>

Hi Hans,

> On Sep 1, 2016, at 22:08 , Hans de Goede <hdegoede@redhat.com> wrote:
> 
> Allwinnner A13 / A23 / A33 based Q8 tablets are popular cheap 7" tablets
> of which a new batch is produced every few weeks. Each batch uses a
> different mix of touchscreen, accelerometer and wifi peripherals.
> 
> Given that each batch is different creating a devicetree for each variant
> is not desirable. This commit adds a Q8 tablet hardware manager which
> auto-detects the touchscreen and accelerometer so that a single generic
> dts can be used for these tablets.
> 
> The wifi is connected to a discoverable bus (sdio or usb) and will be
> autodetected by the mmc resp. usb subsystems.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> .../misc/allwinner,sunxi-q8-hardwaremgr.txt        |  52 +++
> drivers/misc/Kconfig                               |  12 +
> drivers/misc/Makefile                              |   1 +
> drivers/misc/q8-hardwaremgr.c                      | 512 +++++++++++++++++++++
> 4 files changed, 577 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt
> create mode 100644 drivers/misc/q8-hardwaremgr.c
> 
> diff --git a/Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt b/Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt
> new file mode 100644
> index 0000000..f428bf5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt
> @@ -0,0 +1,52 @@
> +Q8 tablet hardware manager
> +--------------------------
> +
> +Allwinnner A13 / A23 / A33 based Q8 tablets are popular cheap 7" tablets of
> +which a new batch is produced every few weeks. Each batch uses a different
> +mix of touchscreen, accelerometer and wifi peripherals.
> +
> +Given that each batch is different creating a devicetree for each variant is
> +not desirable. The Q8 tablet hardware manager bindings are bindings for an os
> +module which auto-detects the touchscreen so that a single
> +generic dts can be used for these tablets.
> +
> +The wifi is connected to a discoverable bus and will be autodetected by the os.
> +
> +Required properties:
> + - compatible         : "allwinner,sunxi-q8-hardwaremgr"
> + - touchscreen        : phandle of a template touchscreen node, this must be a
> +		        child node of the touchscreen i2c bus
> +
> +Optional properties:
> + - touchscreen-supply : regulator phandle for the touchscreen vdd supply
> +
> +touschreen node required properties:
> + - interrupt-parent   : phandle pointing to the interrupt controller
> +			serving the touchscreen interrupt
> + - interrupts         : interrupt specification for the touchscreen interrupt
> + - power-gpios        : Specification for the pin connected to the touchscreen's
> +			enable / wake pin. This needs to be driven high to
> +			enable the touchscreen controller
> +
> +Example:
> +
> +/ {
> +	hwmgr {
> +		compatible = "allwinner,sunxi-q8-hardwaremgr";
> +		touchscreen = <&touchscreen>;
> +		touchscreen-supply = <&reg_ldo_io1>;
> +	};
> +};
> +
> +&i2c0 {
> +	touchscreen: touchscreen at 0 {
> +		interrupt-parent = <&pio>;
> +		interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */
> +		power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> +		/*
> +		 * Enabled by sunxi-q8-hardwaremgr if it detects a
> +		 * known model touchscreen.
> +		 */
> +		status = "disabled";
> +	};
> +};
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index a216b46..c3e7772 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -804,6 +804,18 @@ config PANEL_BOOT_MESSAGE
> 	  An empty message will only clear the display at driver init time. Any other
> 	  printf()-formatted message is valid with newline and escape codes.
> 
> +config Q8_HARDWAREMGR
> +	tristate "Allwinner Q8 tablet hardware manager"
> +	depends on GPIOLIB || COMPILE_TEST
> +	depends on I2C
> +	depends on OF
> +	default	n
> +	help
> +	  This option enables support for autodetecting the touchscreen
> +	  on Allwinner Q8 tablets.
> +
> +	  If unsure, say N.
> +
> source "drivers/misc/c2port/Kconfig"
> source "drivers/misc/eeprom/Kconfig"
> source "drivers/misc/cb710/Kconfig"
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index 7410c6d..cac76b7 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -57,6 +57,7 @@ obj-$(CONFIG_ECHO)		+= echo/
> obj-$(CONFIG_VEXPRESS_SYSCFG)	+= vexpress-syscfg.o
> obj-$(CONFIG_CXL_BASE)		+= cxl/
> obj-$(CONFIG_PANEL)             += panel.o
> +obj-$(CONFIG_Q8_HARDWAREMGR)    += q8-hardwaremgr.o
> 
> lkdtm-$(CONFIG_LKDTM)		+= lkdtm_core.o
> lkdtm-$(CONFIG_LKDTM)		+= lkdtm_bugs.o
> diff --git a/drivers/misc/q8-hardwaremgr.c b/drivers/misc/q8-hardwaremgr.c
> new file mode 100644
> index 0000000..e75625e
> --- /dev/null
> +++ b/drivers/misc/q8-hardwaremgr.c
> @@ -0,0 +1,512 @@
> +/*
> + * Allwinner q8 formfactor tablet hardware manager
> + *
> + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <asm/unaligned.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/i2c.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/slab.h>
> +
> +/*
> + * We can detect which touchscreen controller is used automatically,
> + * but some controllers can be wired up differently depending on the
> + * q8 PCB variant used, so they need different firmware files / settings.
> + *
> + * We allow the user to specify a firmware_variant to select a config
> + * from a list of known configs. We also allow overriding each setting
> + * individually.
> + */
> +
> +static int touchscreen_variant = -1;
> +module_param(touchscreen_variant, int, 0444);
> +MODULE_PARM_DESC(touchscreen_variant, "Touchscreen variant 0-x, -1 for auto");
> +
> +static int touchscreen_width = -1;
> +module_param(touchscreen_width, int, 0444);
> +MODULE_PARM_DESC(touchscreen_width, "Touchscreen width, -1 for auto");
> +
> +static int touchscreen_height = -1;
> +module_param(touchscreen_height, int, 0444);
> +MODULE_PARM_DESC(touchscreen_height, "Touchscreen height, -1 for auto");
> +
> +static int touchscreen_invert_x = -1;
> +module_param(touchscreen_invert_x, int, 0444);
> +MODULE_PARM_DESC(touchscreen_invert_x, "Touchscreen invert x, -1 for auto");
> +
> +static int touchscreen_invert_y = -1;
> +module_param(touchscreen_invert_y, int, 0444);
> +MODULE_PARM_DESC(touchscreen_invert_y, "Touchscreen invert y, -1 for auto");
> +
> +static int touchscreen_swap_x_y = -1;
> +module_param(touchscreen_swap_x_y, int, 0444);
> +MODULE_PARM_DESC(touchscreen_swap_x_y, "Touchscreen swap x y, -1 for auto");
> +
> +static char *touchscreen_fw_name;
> +module_param(touchscreen_fw_name, charp, 0444);
> +MODULE_PARM_DESC(touchscreen_fw_name, "Touchscreen firmware filename");
> +
> +#define TOUCHSCREEN_POWER_ON_DELAY	20
> +#define SILEAD_REG_ID			0xFC
> +#define EKTF2127_RESPONSE		0x52
> +#define EKTF2127_REQUEST		0x53
> +#define EKTF2127_WIDTH			0x63
> +
> +enum touchscreen_model {
> +	touchscreen_unknown,
> +	gsl1680_a082,
> +	gsl1680_b482,
> +	ektf2127,
> +	zet6251,
> +};
> +
> +struct q8_hardwaremgr_data {
> +	struct device *dev;
> +	bool touchscreen_needs_regulator;
> +	enum touchscreen_model touchscreen_model;
> +	int touchscreen_addr;
> +	int touchscreen_variant;
> +	int touchscreen_width;
> +	int touchscreen_height;
> +	int touchscreen_invert_x;
> +	int touchscreen_invert_y;
> +	int touchscreen_swap_x_y;
> +	const char *touchscreen_compatible;
> +	const char *touchscreen_fw_name;
> +};
> +
> +typedef int (*probe_func)(struct q8_hardwaremgr_data *data,
> +			  struct i2c_adapter *adap);
> +
> +#if 0
> +	ret = i2c_smbus_xfer(adap, 0x40, 0, I2C_SMBUS_WRITE, 0,
> +			     I2C_SMBUS_QUICK, NULL);
> +	if (ret < 0)
> +		return -ENODEV;
> +
> +#endif
> +

^^^ crud?

> +static int q8_hardwaremgr_probe_touchscreen(struct q8_hardwaremgr_data *data,
> +					    struct i2c_adapter *adap)
> +{
> +	struct i2c_client *client;
> +	unsigned char buff[24];
> +	__le32 chip_id;
> +	int ret;
> +
> +	msleep(TOUCHSCREEN_POWER_ON_DELAY);
> +
> +	/* Check for silead touchsceen at addr 0x40 */
> +	client = i2c_new_dummy(adap, 0x40);
> +	if (!client)
> +		return -ENOMEM;
> +
> +	ret = i2c_smbus_read_i2c_block_data(client, SILEAD_REG_ID,
> +					    sizeof(chip_id), (u8 *)&chip_id);
> +	if (ret == sizeof(chip_id)) {
> +		switch (le32_to_cpu(chip_id)) {
> +		case 0xa0820000:
> +			data->touchscreen_addr = 0x40;
> +			data->touchscreen_compatible = "silead,gsl1680";
> +			data->touchscreen_model = gsl1680_a082;
> +			dev_info(data->dev, "Found Silead touchscreen ID: 0xa0820000\n");
> +			break;
> +		case 0xb4820000:
> +			data->touchscreen_addr = 0x40;
> +			data->touchscreen_compatible = "silead,gsl1680";
> +			data->touchscreen_model = gsl1680_b482;
> +			dev_info(data->dev, "Found Silead touchscreen ID: 0xb4820000\n");
> +			break;

> +		default:
> +			dev_warn(data->dev, "Found Silead touchscreen with unknown ID: 0x%08x\n",
> +				 le32_to_cpu(chip_id));
> +		}
> +		ret = 0;
> +	}
> +	i2c_unregister_device(client);
> +	if (ret == 0 || ret == -ETIMEDOUT /* Bus stuck bail immediately */)
> +		return ret;
> +
> +	/* Check for Elan eKTF2127 touchsceen at addr 0x15 */
> +	client = i2c_new_dummy(adap, 0x15);
> +	if (!client)
> +		return -ENOMEM;
> +
> +	do {
> +		/* Read hello, ignore data, depends on initial power state */
> +		ret = i2c_master_recv(client, buff, 4);
> +		if (ret != 4)
> +			break;
> +
> +		/* Request width */
> +		buff[0] = EKTF2127_REQUEST;
> +		buff[1] = EKTF2127_WIDTH;
> +		buff[2] = 0x00;
> +		buff[3] = 0x00;
> +		ret = i2c_master_send(client, buff, 4);
> +		if (ret != 4)
> +			break;
> +
> +		msleep(20);
> +
> +		/* Read response */
> +		ret = i2c_master_recv(client, buff, 4);
> +		if (ret != 4)
> +			break;
> +			
> +		if (buff[0] == EKTF2127_RESPONSE && buff[1] == EKTF2127_WIDTH) {
> +			data->touchscreen_addr = 0x15;
> +			data->touchscreen_compatible = "elan,ektf2127";
> +			data->touchscreen_model = ektf2127;
> +			dev_info(data->dev, "Found Elan eKTF2127 touchscreen\n");
> +			ret = 0;
> +		}
> +	} while (0);
> +	i2c_unregister_device(client);
> +	if (ret == 0 || ret == -ETIMEDOUT /* Bus stuck bail immediately */)
> +		return ret;
> +
> +	/* Check for Zeitec zet6251 touchsceen at addr 0x76 */
> +	client = i2c_new_dummy(adap, 0x76);
> +	if (!client)
> +		return -ENOMEM;
> +
> +	/*
> +	 * We only do a simple read finger data packet test, because some
> +	 * versions require firmware to be loaded. If not firmware is loaded
> +	 * the buffer will be filed with 0xff, so we ignore the contents.
> +	 */
> +	ret = i2c_master_recv(client, buff, 24);
> +	if (ret == 24) {
> +		data->touchscreen_addr = 0x76;
> +		data->touchscreen_compatible = "zeitec,zet6251";
> +		data->touchscreen_model = zet6251;
> +		dev_info(data->dev, "Found Zeitec zet6251 touchscreen\n");
> +		ret = 0;
> +	}

I can understand having a switch here since it?s quite complicated but it would be better to
have a structure that defines them i.e.

struct touchscreen_detect_data {
	u32 chip_id;
	int addr;
	const char *compatible;
	enum touchscreen_model model;
	
};

static const struct touchscreen_detect_data ts_detect_data[] = {
	{
		.chip_id = 0xa0820000,
		.addr = 0x40,
		.compatible = ?silead,gsl1680?,
		.model = gsl1680_a082,
	}, ...
};
 
And so on, and restructuring by having different paths by touchscreen model type.


> +	i2c_unregister_device(client);
> +	if (ret == 0 || ret == -ETIMEDOUT /* Bus stuck bail immediately */)
> +		return ret;
> +
> +	return -ENODEV;
> +}
> +
> +static int q8_hardwaremgr_do_probe(struct q8_hardwaremgr_data *data,
> +				   const char *prefix, probe_func func)
> +{
> +	struct device *dev = data->dev;
> +	struct device_node *np;
> +	struct i2c_adapter *adap;
> +	struct regulator *reg;
> +	struct gpio_desc *gpio;
> +	int ret = 0;
> +
> +	np = of_parse_phandle(dev->of_node, prefix, 0);
> +	if (!np) {
> +		dev_err(dev, "Error %s not set\n", prefix);
> +		return -EINVAL;
> +	}
> +
> +	adap = of_get_i2c_adapter_by_node(np->parent);
> +	if (!adap) {
> +		ret = -EPROBE_DEFER;
> +		goto put_node;
> +	}
> +
> +	reg = regulator_get_optional(dev, prefix);
> +	if (IS_ERR(reg)) {
> +		ret = PTR_ERR(reg);
> +		if (ret == -EPROBE_DEFER)
> +			goto put_adapter;
> +		reg = NULL;
> +	}
> +
> +	gpio = fwnode_get_named_gpiod(&np->fwnode, "power-gpios");
> +	if (IS_ERR(gpio)) {
> +		ret = PTR_ERR(gpio);
> +		if (ret == -EPROBE_DEFER)
> +			goto put_reg;
> +		gpio = NULL;
> +	}
> +
> +	/* First try with only the power gpio driven high */
> +	if (gpio) {
> +		ret = gpiod_direction_output(gpio, 1);
> +		if (ret)
> +			goto put_gpio;
> +	}
> +
> +	dev_info(dev, "Looking for %s without a regulator\n", prefix);
> +	ret = func(data, adap);
> +	if (ret != 0 && reg) {
> +		/* Second try, also enable the regulator */
> +		ret = regulator_enable(reg);
> +		if (ret)
> +			goto restore_gpio;
> +
> +		dev_info(dev, "Looking for %s with a regulator\n", prefix);
> +		ret = func(data, adap);
> +		if (ret == 0)
> +			data->touchscreen_needs_regulator = true; 
> +
> +		regulator_disable(reg);
> +	}
> +	ret = 0; /* Not finding a device is not an error */
> +
> +restore_gpio:
> +	if (gpio)
> +		gpiod_direction_output(gpio, 0);
> +put_gpio:
> +	if (gpio)
> +		gpiod_put(gpio);
> +put_reg:
> +	if (reg)
> +		regulator_put(reg);
> +put_adapter:
> +	i2c_put_adapter(adap);
> +
> +put_node:
> +	of_node_put(np);
> +
> +	return ret;
> +}
> +
> +static void q8_hardwaremgr_apply_gsl1680_a082_variant(
> +	struct q8_hardwaremgr_data *data)
> +{
> +	if (touchscreen_variant != -1) {
> +		data->touchscreen_variant = touchscreen_variant;
> +	} else {
> +		if (of_machine_is_compatible("allwinner,sun8i-a33"))
> +			data->touchscreen_variant = 1;
> +		else
> +			data->touchscreen_variant = 0;
> +	}
> +
> +	switch (data->touchscreen_variant) {
> +	default:
> +		dev_warn(data->dev, "Error unknown touchscreen_variant %d using 0\n",
> +			 touchscreen_variant);
> +		/* Fall through */
> +	case 0:
> +		data->touchscreen_width = 1024;
> +		data->touchscreen_height = 600;
> +		data->touchscreen_fw_name = "gsl1680-a082-q8-700.fw";
> +		break;
> +	case 1:
> +		data->touchscreen_width = 480;
> +		data->touchscreen_height = 800;
> +		data->touchscreen_swap_x_y = 1;
> +		data->touchscreen_fw_name = "gsl1680-a082-q8-a70.fw";
> +		break;
> +	}
> +}
> +
> +static void q8_hardwaremgr_apply_gsl1680_b482_variant(
> +	struct q8_hardwaremgr_data *data)
> +{
> +	if (touchscreen_variant != -1)
> +		data->touchscreen_variant = touchscreen_variant;
> +
> +	switch (data->touchscreen_variant) {
> +	default:
> +		dev_warn(data->dev, "Error unknown touchscreen_variant %d using 0\n",
> +			 touchscreen_variant);
> +		/* Fall through */
> +	case 0:
> +		data->touchscreen_width = 960;
> +		data->touchscreen_height = 640;
> +		data->touchscreen_fw_name = "gsl1680-b482-q8-d702.fw";
> +		break;
> +	case 1:
> +		data->touchscreen_width = 960;
> +		data->touchscreen_height = 640;
> +		data->touchscreen_fw_name = "gsl1680-b482-q8-a70.fw";
> +		break;
> +	}
> +}
> +
> +static void q8_hardwaremgr_issue_gsl1680_warning(
> +	struct q8_hardwaremgr_data *data)
> +{
> +	dev_warn(data->dev, "gsl1680 touchscreen may require kernel cmdline parameters to function properly\n");
> +	dev_warn(data->dev, "Try q8_hardwaremgr.touchscreen_invert_x=1 if x coordinates are inverted\n");
> +	dev_warn(data->dev, "Try q8_hardwaremgr.touchscreen_variant=%d if coordinates are all over the place\n",
> +		 !data->touchscreen_variant);
> +
> +#define	show(x) \
> +	dev_info(data->dev, #x " %d (%s)\n", data->x, \
> +		 (x == -1) ? "auto" : "user supplied")
> +
> +	show(touchscreen_variant);
> +	show(touchscreen_width);
> +	show(touchscreen_height);
> +	show(touchscreen_invert_x);
> +	show(touchscreen_invert_y);
> +	show(touchscreen_swap_x_y);
> +	dev_info(data->dev, "touchscreen_fw_name %s (%s)\n",
> +		 data->touchscreen_fw_name,
> +		 (touchscreen_fw_name == NULL) ? "auto" : "user supplied");
> +#undef show
> +}
> +
> +static void q8_hardwaremgr_apply_touchscreen(struct q8_hardwaremgr_data *data)
> +{
> +	struct device *dev = data->dev;
> +	struct of_changeset cset;
> +	struct device_node *np;
> +
> +	switch (data->touchscreen_model) {
> +	case touchscreen_unknown:
> +		return;
> +	case gsl1680_a082:
> +		q8_hardwaremgr_apply_gsl1680_a082_variant(data);
> +		break;
> +	case gsl1680_b482:
> +		q8_hardwaremgr_apply_gsl1680_b482_variant(data);
> +		break;
> +	case ektf2127:
> +	case zet6251:
> +		/* These have only 1 variant */
> +		break;
> +	}
> +
> +	if (touchscreen_width != -1)
> +		data->touchscreen_width = touchscreen_width;
> +
> +	if (touchscreen_height != -1)
> +		data->touchscreen_height = touchscreen_height;
> +
> +	if (touchscreen_invert_x != -1)
> +		data->touchscreen_invert_x = touchscreen_invert_x;
> +
> +	if (touchscreen_invert_y != -1)
> +		data->touchscreen_invert_y = touchscreen_invert_y;
> +
> +	if (touchscreen_swap_x_y != -1)
> +		data->touchscreen_swap_x_y = touchscreen_swap_x_y;
> +
> +	if (touchscreen_fw_name)
> +		data->touchscreen_fw_name = touchscreen_fw_name;
> +
> +	if (data->touchscreen_model == gsl1680_a082 ||
> +	    data->touchscreen_model == gsl1680_b482)
> +		q8_hardwaremgr_issue_gsl1680_warning(data);
> +
> +	np = of_parse_phandle(data->dev->of_node, "touchscreen", 0);
> +	/* Never happens already checked in q8_hardwaremgr_do_probe() */
> +	if (WARN_ON(!np))
> +		return;
> +
> +	of_changeset_init(&cset);
> +	of_changeset_add_property_u32(&cset, np, "reg", data->touchscreen_addr);
> +	of_changeset_add_property_string(&cset, np, "compatible",
> +					 data->touchscreen_compatible);
> +
> +	if (data->touchscreen_width)
> +		of_changeset_add_property_u32(&cset, np, "touchscreen-size-x",
> +					      data->touchscreen_width);
> +	if (data->touchscreen_height)
> +		of_changeset_add_property_u32(&cset, np, "touchscreen-size-y",
> +					      data->touchscreen_height);
> +	if (data->touchscreen_invert_x)
> +		of_changeset_add_property_bool(&cset, np,
> +					       "touchscreen-inverted-x");
> +	if (data->touchscreen_invert_y)
> +		of_changeset_add_property_bool(&cset, np,
> +					       "touchscreen-inverted-y");
> +	if (data->touchscreen_swap_x_y)
> +		of_changeset_add_property_bool(&cset, np,
> +					       "touchscreen-swapped-x-y");
> +	if (data->touchscreen_fw_name)
> +		of_changeset_add_property_string(&cset, np, "firmware-name",
> +						 data->touchscreen_fw_name);
> +	if (data->touchscreen_needs_regulator) {
> +		struct property *p;
> +
> +		p = of_find_property(dev->of_node, "touchscreen-supply", NULL);
> +		/* Never happens already checked in q8_hardwaremgr_do_probe() */
> +		if (WARN_ON(!p))
> +			return;
> +
> +		of_changeset_add_property_copy(&cset, np, "vddio-supply",
> +					       p->value, p->length);
> +	}
> +
> +	of_changeset_update_property_string(&cset, np, "status", "okay");
> +	of_changeset_apply(&cset);
> +
> +	of_node_put(np);
> +}
> +
> +static int q8_hardwaremgr_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct q8_hardwaremgr_data *data;
> +	int ret = 0;
> +
> +	data = kzalloc(sizeof(*data), GFP_KERNEL);
> +	if (!data)
> +		return -ENOMEM;
> +
> +	data->dev = &pdev->dev;
> +
> +	ret = q8_hardwaremgr_do_probe(data, "touchscreen",
> +				      q8_hardwaremgr_probe_touchscreen);
> +	if (ret)
> +		goto error;
> +
> +	/*
> +	 * Our pinctrl may conflict with the pinctrl of the detected devices
> +	 * we're adding, so remove it before adding detected devices.
> +	 */
> +	if (dev->pins) {
> +		devm_pinctrl_put(dev->pins->p);
> +		devm_kfree(dev, dev->pins);
> +		dev->pins = NULL;
> +	}
> +

Hmm, that?s weird for sure. How can it happen?

> +	q8_hardwaremgr_apply_touchscreen(data);
> +
> +error:
> +	kfree(data);
> +
> +	return ret;
> +}
> +
> +static const struct of_device_id q8_hardwaremgr_of_match[] = {
> +	{ .compatible = "allwinner,sunxi-q8-hardwaremgr", },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, q8_hardwaremgr_of_match);
> +
> +static struct platform_driver q8_hardwaremgr_driver = {
> +	.driver = {
> +		.name	= "q8-hardwaremgr",
> +		.of_match_table = of_match_ptr(q8_hardwaremgr_of_match),
> +	},
> +	.probe	= q8_hardwaremgr_probe,
> +};
> +
> +module_platform_driver(q8_hardwaremgr_driver);
> +
> +MODULE_DESCRIPTION("Allwinner q8 formfactor tablet hardware manager");
> +MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
> +MODULE_LICENSE("GPL");
> -- 
> 2.9.3
> 

Regards

? Pantelis

^ permalink raw reply

* [PATCH] clk: sunxi-ng: a23: Assign base address for bus_spinlock_clk
From: Maxime Ripard @ 2016-09-09 19:12 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20160909035421.16119-1-wens@csie.org>

On Fri, Sep 09, 2016 at 11:54:21AM +0800, Chen-Yu Tsai wrote:
> bus_spinlock_clk was accidentally left out of the list of clks that
> need to be assigned the register base address.
> 
> Fixes: 8c9214b0e525 ("clk: sunxi-ng: Add A23 CCU")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

I squashed it into the A23 CCU patch.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160909/5ef50a54/attachment.sig>

^ permalink raw reply

* [PATCH V4 3/4] ARM: bcm2835: add thermal node to device-tree of bcm283x
From: Stefan Wahren @ 2016-09-09 19:02 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <185DA6B2-AFC0-4199-A361-0164381AD317@martin.sperl.org>

Hi Martin,

> Martin Sperl <kernel@martin.sperl.org> hat am 9. September 2016 um 20:12
> geschrieben:
> 
> 
> 
> > On 09.09.2016, at 17:36, Stefan Wahren <stefan.wahren@i2se.com> wrote:
> > 
> > 
> >> Martin Sperl <kernel@martin.sperl.org> hat am 9. September 2016 um 16:58
> >> geschrieben:
> >> 
> >> 
> >> 
> >>>> On 09.09.2016, at 16:25, Stefan Wahren <stefan.wahren@i2se.com> wrote:
> >>>> 
> >>>> Am 09.09.2016 um 09:49 schrieb kernel at martin.sperl.org:
> >>>> From: Martin Sperl <kernel@martin.sperl.org>
> >>>> 
> >>>> Add the node for the thermal sensor of the bcm2835-soc
> >>>> to the device tree.
> >>>> 
> >>>> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
> >>>> Reviewed-by: Eric Anholt <eric@anholt.net>
> >>>> ---
> >>>> arch/arm/boot/dts/bcm283x.dtsi | 6 ++++++
> >>>> 1 file changed, 6 insertions(+)
> >>>> 
> >>>> diff --git a/arch/arm/boot/dts/bcm283x.dtsi
> >>>> b/arch/arm/boot/dts/bcm283x.dtsi
> >>>> index b982522..e2e3a46 100644
> >>>> --- a/arch/arm/boot/dts/bcm283x.dtsi
> >>>> +++ b/arch/arm/boot/dts/bcm283x.dtsi
> >>>> @@ -186,6 +186,12 @@
> >>>>           interrupts = <2 14>; /* pwa1 */
> >>>>       };
> >>>> 
> >>>> +        thermal: thermal at 0x7e212000 {

please remove 0x here.

> >>>> +            compatible = "brcm,bcm2835-thermal";
> >>>> +            reg = <0x7e212000 0x8>;
> >>>> +            clocks = <&clocks BCM2835_CLOCK_TSENS>;
> >>>> +        };
> >>>> +
> >>> 
> >>> Since the driver handles 3 different SoC (2835, 2836, 2837). This node
> >>> should be defined in the SoC specific dtsi files, because the BCM2836
> >>> includes bcm283x.dtsi too.
> >>> 
> >>> Be aware the patch for bcm2837 must go to ARM64.
> >> 
> >> I can not really follow:
> >> * the node is defined in the dtsi included by all 3 soc,
> >>   and it is available on all so it sits where for example
> >>   spi0 or uart0 is located
> >> * as for arm64: this describes the registers that are
> >>   identical for arm and arm64 and the bcm2837.dtsi
> >>   is also including ../../../../arm/boot/dts/bcm283x.dtsi
> >> 
> >> So what is the problem?
> > 
> > The thermal driver specifies 3 different compatibles with partially
> > different
> > settings.
> > If this patch is applied, all SoC (bcm2835, bcm2836, bcm2837) would use the
> > bcm2835 settings.
> > I can't believe this is intended.
> > 
> > Why does the binding contains 3 different compatibles if only one is used?
> 
> Now I understand - did not think of that: good catch!
> 
> To minimize the patch: what about setting it to 2837 by default (in 283x.dtsi)
> and only change compatible in 2835.dtsi and 2836.dtsi - that is 3 files
> changed instead of 4 or 5...

Please don't do this in order avoid to confusion. We have compatible strings for
each SoC and we have dtsi files for each SoC. So i think the right way would be
the following:

bcm283x.dtsi

thermal: thermal at 7e212000 {
            reg = <0x7e212000 0x8>;
            clocks = <&clocks BCM2835_CLOCK_TSENS>;
};


bcm2835.dtsi

&thermal {
            compatible = "brcm,bcm2835-thermal";
            status = "okay";
};

bcm2836.dtsi

&thermal {
            compatible = "brcm,bcm2836-thermal";
            status = "okay";
};

bcm2837.dtsi

&thermal {
            compatible = "brcm,bcm2837-thermal";
            status = "okay";
};

> 
> Or any other ideas how to detect which Soc we run on during runtime?
> I.e: query the root compatible string in the device-tree?
> 
> Just before I create a new patch set to fix that.
> 
> Martin
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* [PATCH 2/5] mmc: bcm2835-sdhost: Add new driver for the internal SD controller.
From: Eric Anholt @ 2016-09-09 18:25 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1473347315.6698.53.camel@redhat.com>

Gerd Hoffmann <kraxel@redhat.com> writes:

> On Mi, 2016-08-31 at 14:58 +0200, Ulf Hansson wrote:
>> On 22 June 2016 at 13:42, Gerd Hoffmann <kraxel@redhat.com> wrote:
>> > From: Eric Anholt <eric@anholt.net>
>> >
>> > The 2835 has two SD controllers: The Arasan SDHCI controller that we
>> > currently use, and a custom SD controller.  The custom one runs faster
>> >
>> > The code was originally written by Phil Elwell in the downstream
>> > Rasbperry Pi tree, and I did a major cleanup on it (+319, -707 lines
>> > out of the original 2055) for inclusion.
>> >
>> > Signed-off-by: Eric Anholt <eric@anholt.net>
>> 
>> Apologize for the delay!
>
> No problem, I was on summer vacation anyway ...
>
>> Could you start by providing some more information about the driver
>> and the controller in change in the change log please.
>
> Eric?  I don't know much more than what the commit message above says.
>
> Beside the speedup mentioned above driving the sdcard with the custom sd
> controller allows to use the sdhci (handled by sdhci-iproc) to be used
> for the wifi on the rpi3.

Maybe just add that we need both controllers in order to do both wifi
and SD card?  I don't know exactly what Ulf wants to see here.

>> > +static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on)
>> > +{
>> > +       bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD);
>> 
>> What exactly does this power on/off?
>
> Dunno.  Eric?

Note: I don't know much about SD, so I'm just trying to play oracle for
you all here.

VDD bit 0 (POWER_ON) starts the power-on setup cycle by the sdhost once
power is already supplied to the card by some other means.  In the
SDHOST docs they assume you're going to use GPIO to control SD card
power, but for Raspberry Pi they just have the SD Card's VDD always on.
It's unclear to me what's controlling power to the Pi3 wifi/BT's SD
client, but I don't have specs to it.

Note that after you've set POWER_ON to 0, you can also set bit 1
(CLOCK_OFF) to 1 to turn off the clock to the power-on FSM.

>> > +       /* Need to send CMD12 if -
>> > +        * a) open-ended multiblock transfer (no CMD23)
>> > +        * b) error in multiblock transfer
>> > +        */
>> > +       if (host->mrq->stop && (data->error || !host->use_sbc)) {
>> > +               if (bcm2835_sdhost_send_command(host, host->mrq->stop)) {
>> > +                       /* No busy, so poll for completion */
>> > +                       if (!host->use_busy)
>> 
>> This looks a bit weird. Can you explain why this is needed?
>
> Eric, any clue?  Some hardware bug workaround?
> Have a pointer to hardware specs?

Would no-CMD23 transfers mean that data->blocks was 0 to mean
indefinite?  That's the only mention of CMD12 in the spec -- when you've
set HBLC to 0, you need to CMD12 or CMD52 when you're done with the
transfer.

>> > +static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> > +{
>> 
>> I don't find any place where you control power to the card here. Don't
>> you need to do that?
>
> Eric?

It looks like the card is always powered.  Do you mean something else by
power (like bringing up the FSM)?  Is there something else needed in
set_ios()?
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 800 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160909/8ee17a2b/attachment.sig>

^ permalink raw reply

* [PATCH v2 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching
From: Kees Cook @ 2016-09-09 18:24 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20160909163116.GA10792@leverpostej>

On Fri, Sep 9, 2016 at 9:31 AM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Thu, Sep 08, 2016 at 01:51:24PM +0100, Catalin Marinas wrote:
>> On Wed, Sep 07, 2016 at 04:20:55PM -0700, Kees Cook wrote:
>> > On Fri, Sep 2, 2016 at 8:02 AM, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > > This is the second version of the arm64 PAN emulation by disabling
>> > > TTBR0_EL1 accesses. The major change from v1 is the use of a thread_info
>> > > member to store the real TTBR0_EL1 value. The advantage is slightly
>> > > simpler assembler macros for uaccess_enable with the downside that
>> > > switch_mm() must always update the saved ttbr0 even if there is no mm
>> > > switch.
>> >
>> > Is arm64 thread_info attached to the kernel stack? (i.e. is this
>> > introducing a valuable target for stack-based attacks?)
>>
>> Currently yes, thread_info is on the kernel stack. At some point we'll
>> decouple it in a similar way to what x86 are doing/planning.
>
> FWIW, I'm currently working on this (atop of Andy's x86 patches). The
> IRQ stack work largely removed out dependence on the stack pointer to
> find thread_info, and I have a plan for the remaining places.
>
> There's a fair amount of ground work to do first (e.g. reworking headers
> to avoid circular dependencies), but hopefully I'll have something that
> I can share soon.

Fantastic! Thanks for the heads-up. :)

-Kees

-- 
Kees Cook
Nexus Security

^ permalink raw reply

* [PATCH 4.5/20] Docs: dt: document ARM SMMUv3 generic binding usage
From: Robin Murphy @ 2016-09-09 18:17 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1473173789.git.robin.murphy@arm.com>

Now that we've ratified SMMUv3's use of the generic binding, document it.

CC: Rob Herring <robh+dt@kernel.org>
CC: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
index 7b94c88cf2ee..69a694f70bea 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
@@ -27,6 +27,12 @@ the PCIe specification.
                       * "cmdq-sync" - CMD_SYNC complete
                       * "gerror"    - Global Error activated
 
+- #iommu-cells      : See the generic IOMMU binding described in
+                        devicetree/bindings/iommu/iommu.txt
+                      for details. For SMMUv3, must be 1, with each cell
+                      describing a single stream ID. All possible stream
+                      ID which a device may emit must be described.
+
 ** SMMUv3 optional properties:
 
 - dma-coherent      : Present if DMA operations made by the SMMU (page
@@ -54,6 +60,6 @@ the PCIe specification.
                              <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
                 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
                 dma-coherent;
-                #iommu-cells = <0>;
+                #iommu-cells = <1>;
                 msi-parent = <&its 0xff0000>;
         };
-- 
2.8.1.dirty

^ permalink raw reply related

* [PATCH 22/20] iommu/arm-smmu: Fall back to global bypass
From: Robin Murphy @ 2016-09-09 18:17 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1473173789.git.robin.murphy@arm.com>

Unlike SMMUv2, SMMUv3 has no easy way to bypass unknown stream IDs,
other than allocating and filling in the entire stream table with bypass
entries, which for some configurations would waste *gigabytes* of RAM.
Otherwise, all transactions on unknown stream IDs will simply be aborted
with a C_BAD_STREAMID event.

Rather than render the system unusable in the case of an invalid DT,
avoid enabling the SMMU altogether such that everything bypasses
(though letting the explicit disable_bypass option take precedence).

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 drivers/iommu/arm-smmu-v3.c | 28 +++++++++++++++++++++++-----
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index be293b5aa896..859b80c83946 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -126,6 +126,9 @@
 #define CR2_RECINVSID			(1 << 1)
 #define CR2_E2H				(1 << 0)
 
+#define ARM_SMMU_GBPA			0x44
+#define GBPA_ABORT			(1 << 20)
+
 #define ARM_SMMU_IRQ_CTRL		0x50
 #define IRQ_CTRL_EVTQ_IRQEN		(1 << 2)
 #define IRQ_CTRL_PRIQ_IRQEN		(1 << 1)
@@ -2242,7 +2245,7 @@ static int arm_smmu_device_disable(struct arm_smmu_device *smmu)
 	return ret;
 }
 
-static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
+static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
 {
 	int ret;
 	u32 reg, enables;
@@ -2343,8 +2346,14 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
 		return ret;
 	}
 
-	/* Enable the SMMU interface */
-	enables |= CR0_SMMUEN;
+
+	/* Enable the SMMU interface, or ensure bypass */
+	if (!bypass || disable_bypass) {
+		enables |= CR0_SMMUEN;
+	} else {
+		reg = readl_relaxed(smmu->base + ARM_SMMU_GBPA);
+		writel_relaxed(reg & ~GBPA_ABORT, smmu->base + ARM_SMMU_GBPA);
+	}
 	ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
 				      ARM_SMMU_CR0ACK);
 	if (ret) {
@@ -2543,6 +2552,15 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
 	struct resource *res;
 	struct arm_smmu_device *smmu;
 	struct device *dev = &pdev->dev;
+	bool bypass = true;
+	u32 cells;
+
+	if (of_property_read_u32(dev->of_node, "#iommu-cells", &cells))
+		dev_err(dev, "missing #iommu-cells property\n");
+	else if (cells != 1)
+		dev_err(dev, "invalid #iommu-cells value (%d)\n", cells);
+	else
+		bypass = false;
 
 	smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
 	if (!smmu) {
@@ -2595,8 +2613,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, smmu);
 
 	/* Reset the device */
-	ret = arm_smmu_device_reset(smmu);
-	if (ret)
+	ret = arm_smmu_device_reset(smmu, bypass);
+	if (ret || bypass)
 		return ret;
 
 	/* And we're up. Go go go! */
-- 
2.8.1.dirty

^ permalink raw reply related

* [PATCH 21/20] drm/exynos: Fix iommu_dma_init_domain prototype change
From: Robin Murphy @ 2016-09-09 18:17 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1473173789.git.robin.murphy@arm.com>

When adding an extra argument to a function, one really should try a bit
harder to catch *all* the callers...

CC: Marek Szyprowski <m.szyprowski@samsung.com>
CC: Inki Dae <inki.dae@samsung.com>
CC: David Airlie <airlied@linux.ie>
CC: dri-devel at lists.freedesktop.org
Signed-off-by: Robin Murphy <robin.murphy@arm.com>

---

Ideally, this should be squashed into "iommu/dma: Avoid PCI host bridge
windows" to avoid potential bisection breakage. Sorry!

 drivers/gpu/drm/exynos/exynos_drm_iommu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_iommu.h b/drivers/gpu/drm/exynos/exynos_drm_iommu.h
index c8de4913fdbe..87f6b5672e11 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_iommu.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_iommu.h
@@ -66,7 +66,7 @@ static inline int __exynos_iommu_create_mapping(struct exynos_drm_private *priv,
 	if (ret)
 		goto free_domain;
 
-	ret = iommu_dma_init_domain(domain, start, size);
+	ret = iommu_dma_init_domain(domain, start, size, NULL);
 	if (ret)
 		goto put_cookie;
 
-- 
2.8.1.dirty

^ permalink raw reply related

* [PATCH V4 3/4] ARM: bcm2835: add thermal node to device-tree of bcm283x
From: Martin Sperl @ 2016-09-09 18:12 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <2117811305.32861.15854341-2f8e-4e20-95f4-e76f81e6fd56.open-xchange@email.1und1.de>


> On 09.09.2016, at 17:36, Stefan Wahren <stefan.wahren@i2se.com> wrote:
> 
> 
>> Martin Sperl <kernel@martin.sperl.org> hat am 9. September 2016 um 16:58
>> geschrieben:
>> 
>> 
>> 
>>>> On 09.09.2016, at 16:25, Stefan Wahren <stefan.wahren@i2se.com> wrote:
>>>> 
>>>> Am 09.09.2016 um 09:49 schrieb kernel at martin.sperl.org:
>>>> From: Martin Sperl <kernel@martin.sperl.org>
>>>> 
>>>> Add the node for the thermal sensor of the bcm2835-soc
>>>> to the device tree.
>>>> 
>>>> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
>>>> Reviewed-by: Eric Anholt <eric@anholt.net>
>>>> ---
>>>> arch/arm/boot/dts/bcm283x.dtsi | 6 ++++++
>>>> 1 file changed, 6 insertions(+)
>>>> 
>>>> diff --git a/arch/arm/boot/dts/bcm283x.dtsi
>>>> b/arch/arm/boot/dts/bcm283x.dtsi
>>>> index b982522..e2e3a46 100644
>>>> --- a/arch/arm/boot/dts/bcm283x.dtsi
>>>> +++ b/arch/arm/boot/dts/bcm283x.dtsi
>>>> @@ -186,6 +186,12 @@
>>>>           interrupts = <2 14>; /* pwa1 */
>>>>       };
>>>> 
>>>> +        thermal: thermal at 0x7e212000 {
>>>> +            compatible = "brcm,bcm2835-thermal";
>>>> +            reg = <0x7e212000 0x8>;
>>>> +            clocks = <&clocks BCM2835_CLOCK_TSENS>;
>>>> +        };
>>>> +
>>> 
>>> Since the driver handles 3 different SoC (2835, 2836, 2837). This node
>>> should be defined in the SoC specific dtsi files, because the BCM2836
>>> includes bcm283x.dtsi too.
>>> 
>>> Be aware the patch for bcm2837 must go to ARM64.
>> 
>> I can not really follow:
>> * the node is defined in the dtsi included by all 3 soc,
>>   and it is available on all so it sits where for example
>>   spi0 or uart0 is located
>> * as for arm64: this describes the registers that are
>>   identical for arm and arm64 and the bcm2837.dtsi
>>   is also including ../../../../arm/boot/dts/bcm283x.dtsi
>> 
>> So what is the problem?
> 
> The thermal driver specifies 3 different compatibles with partially different
> settings.
> If this patch is applied, all SoC (bcm2835, bcm2836, bcm2837) would use the
> bcm2835 settings.
> I can't believe this is intended.
> 
> Why does the binding contains 3 different compatibles if only one is used?

Now I understand - did not think of that: good catch!

To minimize the patch: what about setting it to 2837 by default (in 283x.dtsi)
and only change compatible in 2835.dtsi and 2836.dtsi - that is 3 files
changed instead of 4 or 5...

Or any other ideas how to detect which Soc we run on during runtime?
I.e: query the root compatible string in the device-tree?

Just before I create a new patch set to fix that.

Martin

^ permalink raw reply

* [PATCH 1/2] ARM: clk-imx35: fix name for ckil clk
From: Stephen Boyd @ 2016-09-09 18:11 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20160909062034.tim2tzcihui6inoa@pengutronix.de>

On 09/09, Uwe Kleine-K?nig wrote:
> To += mturquette, sboyd
> 
> Hello Shawn, hello Michael, hello Stephen,
> 
> On Fri, Sep 09, 2016 at 02:16:31PM +0800, Shawn Guo wrote:
> > On Thu, Sep 08, 2016 at 11:30:21AM +0200, Uwe Kleine-K?nig wrote:
> > > This fixes
> > > 	[    0.000000] i.MX clk 82: register failed with -17
> > > because the name is duplicated.
> > > 
> > > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> > 
> > I did not queue any clock patches for this cycle.  Can you please send
> > the patches directly to clock maintainers?
> 
> @shawnguo: Is this an ack?
> @mturquette, sboyd: should I resend? IMHO the first patch should go in
> soon.

Does the first patch need a fixes tag? We can apply them
directly.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply

* [PATCH V4 2/4] thermal: bcm2835: add thermal driver for bcm2835 soc
From: Eric Anholt @ 2016-09-09 17:57 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1473407397-29395-3-git-send-email-kernel@martin.sperl.org>

kernel at martin.sperl.org writes:

> From: Martin Sperl <kernel@martin.sperl.org>
>
> Add basic thermal driver for bcm2835 SOC.
>
> This driver currently relies on the firmware setting up the
> tsense HW block and does not set it up itself.
>
> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>

Acked-by: Eric Anholt <eric@anholt.net>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 800 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160909/324bf9f8/attachment.sig>

^ permalink raw reply

* [PATCH 1/2] ARM: dts: imx6ul: Add DTS for liteSOM module
From: Fabio Estevam @ 2016-09-09 17:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20160909103906.15209-1-m.niestroj@grinn-global.com>

On Fri, Sep 9, 2016 at 7:39 AM, Marcin Niestroj
<m.niestroj@grinn-global.com> wrote:

> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi
> @@ -0,0 +1,52 @@
> +/*
> + * Copyright (C) 2016 Grinn
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */

Is it possible to use a dual GPLv2/X11 license?

Patches look good.

^ permalink raw reply

* [PATCH v6 00/20] Generic DT bindings for PCI IOMMUs and ARM SMMU
From: Will Deacon @ 2016-09-09 17:37 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1473173789.git.robin.murphy@arm.com>

Hi Robin,

On Tue, Sep 06, 2016 at 04:33:33PM +0100, Robin Murphy wrote:
> Here's v6 to address last week's comments. For the sake of honesty I've
> left Lorenzo's tested-by off everything I've changed since, and Eric's
> reviewed-by off patch 19 having non-trivially reworked the guts of it.
> 
> Patch 20 is new, but as it's currently a solution waiting for a problem
> as far as we're aware, oughtn't to get in the way; hopefully the rest is
> in good shape for 4.9 now.
> 
> Branch here, based on Will's iommu/devel queue:
> 
> git://linux-arm.org/linux-rm iommu/generic-v6

I'm pretty happy with this (modulo the binding docs update etc we
discussed off list), however I'm seeing an allmodconfig build failure
with this applied. Error below.

Please can you take a look and send a fixup patch?

Cheers,

Will

--->8

In file included from drivers/gpu/drm/exynos/exynos_drm_drv.c:33:0:
drivers/gpu/drm/exynos/exynos_drm_iommu.h: In function ?__exynos_iommu_create_mapping?:
drivers/gpu/drm/exynos/exynos_drm_iommu.h:69:8: error: too few arguments to function ?iommu_dma_init_domain?
  ret = iommu_dma_init_domain(domain, start, size);
        ^
In file included from drivers/gpu/drm/exynos/exynos_drm_iommu.h:53:0,
                 from drivers/gpu/drm/exynos/exynos_drm_drv.c:33:
./include/linux/dma-iommu.h:33:5: note: declared here
 int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
     ^
make[4]: *** [drivers/gpu/drm/exynos/exynos_drm_drv.o] Error 1
make[3]: *** [drivers/gpu/drm/exynos] Error 2
make[3]: *** Waiting for unfinished jobs....
make[2]: *** [drivers/gpu/drm] Error 2
make[1]: *** [drivers/gpu] Error 2
make[1]: *** Waiting for unfinished jobs....
make: *** [drivers] Error 2

^ permalink raw reply

* Improper TTBCR for arm 32bit kernel decompression
From: Nicolas Pitre @ 2016-09-09 17:36 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <57D2E47D.5030105@codeaurora.org>

On Fri, 9 Sep 2016, Srinivas Ramana wrote:

> Hello,
> 
> While trying to boot arm-32 bit kernel, I came across a problem where TTBCR is
> in improper state. If the bootloader uses the long descriptor format and jumps
> to kernel decompressor code, TTBCR may not be in the right state. So, as soon
> as the MMU is enabled, execution can not proceed further.
> 
> Before enabling the MMU, it is required to clear the TTBCR.PD0 field to use
> TTBR0 for translation table walks. Also, TTBCR.N should be reset to '0' to
> indicate the correct base address width. The 'commit dbece45894d3a ("ARM:
> 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores")' does the reset of
> TTBCR.N, but doesn't consider all the bits for the size of TTBCR.N.
> 
> when i tried the below change where i explicitly clear TTBCR.PD0 and use
> correct mask for TTBCR.N, I see proper memory after MMU is enabled and
> decompression succeeds.
> 
> Request your comments on the change below. If it looks good, I can submit a
> patch for inclusion.
> 
> ---------------------8<----------------------------------
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index af11c2f..5769f1f 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -779,7 +779,8 @@ __armv7_mmu_cache_on:
>                 orrne   r0, r0, #1              @ MMU enabled
>                 movne   r1, #0xfffffffd         @ domain 0 = client
>                 bic     r6, r6, #1 << 31        @ 32-bit translation system
> -               bic     r6, r6, #3 << 0         @ use only ttbr0
> +               bic     r6, r6, #7 << 0         @ width of base address field
> +               bic     r6, r6, #1 << 4         @ use only ttbr0

You could combine those instructions like this:

		bic	r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0


Nicolas

^ permalink raw reply

* [GIT PULL] arm64 fixes for 4.8-rc6
From: Catalin Marinas @ 2016-09-09 17:32 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Linus,

Please pull the arm64 fixes below. Thanks.

The following changes since commit c6935931c1894ff857616ff8549b61236a19148f:

  Linux 4.8-rc5 (2016-09-04 14:31:46 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes

for you to fetch changes up to 2b9743441a312e0b0a2d87deae363eccbe9d0f00:

  arm64: use preempt_disable_notrace in _percpu_read/write (2016-09-09 12:34:47 +0100)

----------------------------------------------------------------
- smp_mb__before_spinlock() changed to smp_mb() on arm64 since the
  generic definition to smp_wmb() is not sufficient

- avoid a recursive loop with the graph tracer by using using
  preempt_(enable|disable)_notrace in _percpu_(read|write)

----------------------------------------------------------------
Chunyan Zhang (1):
      arm64: use preempt_disable_notrace in _percpu_read/write

Will Deacon (1):
      arm64: spinlocks: implement smp_mb__before_spinlock() as smp_mb()

 arch/arm64/include/asm/percpu.h   |  8 ++++----
 arch/arm64/include/asm/spinlock.h | 10 ++++++++++
 2 files changed, 14 insertions(+), 4 deletions(-)

-- 
Catalin

^ permalink raw reply

* [GIT PULL] pxa for v4.9
From: Robert Jarzmik @ 2016-09-09 17:27 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Arnd, Kevin, Olof,

Please consider this pull request for pxa 4.8 cycle. The diffstat should look
nice as the legacy dma code is removed at last.

The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:

  Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)

are available in the git repository at:

  https://github.com/rjarzmik/linux.git tags/pxa-for-4.9

for you to fetch changes up to 9ba63e3cc849cdaf3b675c47cc51fe35419e5117:

  ARM: pxa: pxa_cplds: fix interrupt handling (2016-09-09 18:09:53 +0200)

----------------------------------------------------------------
This is the pxa changes for v4.9 cycle.

This cycle is covering :
 - the removal of the legacy DMA API
   This is the major contributor to the negative diffstat, as dmaengine
   have taken over in this area.
 - IDE subsystem defconfig fixes
 - preparation for pxa25x to be device-tree compliant
 - various irq related fixes

----------------------------------------------------------------
Bartlomiej Zolnierkiewicz (4):
      arm: colibri_pxa270_defconfig: disable IDE subsystem
      arm: lpda270_defconfig: disable IDE subsystem
      arm: pxa255-idp_defconfig: disable IDE subsystem
      arm: trizeps4_defconfig: disable IDE subsystem

Markus Elfring (1):
      ARM: pxa: Use kmalloc_array() in pxa_pm_init()

Petr Cvek (1):
      ARM: pxa: magician: Remove duplicated I2C pins declaration

Robert Jarzmik (7):
      ARM: pxa: remove devicetree boards from pxa_defconfig
      ARM: pxa: remove platform dma code
      ARM: pxa: prepare pxa25x interrupts for device-tree platforms
      ARM: pxa: add pxa25x device-tree support
      ARM: pxa: fix GPIO double shifts
      ARM: pxa: remove irq init from dt machines
      ARM: pxa: pxa_cplds: fix interrupt handling

 arch/arm/configs/colibri_pxa270_defconfig |   1 -
 arch/arm/configs/lpd270_defconfig         |   1 -
 arch/arm/configs/pxa255-idp_defconfig     |   1 -
 arch/arm/configs/pxa_defconfig            |   2 -
 arch/arm/configs/trizeps4_defconfig       |   2 -
 arch/arm/mach-pxa/Kconfig                 |  11 +
 arch/arm/mach-pxa/Makefile                |   3 +-
 arch/arm/mach-pxa/corgi_pm.c              |  13 +-
 arch/arm/mach-pxa/devices.h               |   1 +
 arch/arm/mach-pxa/generic.h               |   2 -
 arch/arm/mach-pxa/include/mach/dma.h      |   1 -
 arch/arm/mach-pxa/magician.c              |   4 -
 arch/arm/mach-pxa/pm.c                    |   5 +-
 arch/arm/mach-pxa/pxa-dt.c                |  35 ++-
 arch/arm/mach-pxa/pxa25x.c                |  26 +-
 arch/arm/mach-pxa/pxa27x.c                |  14 +-
 arch/arm/mach-pxa/pxa3xx.c                |  11 +-
 arch/arm/mach-pxa/pxa_cplds_irqs.c        |  24 +-
 arch/arm/mach-pxa/sharpsl_pm.c            |   2 +-
 arch/arm/mach-pxa/sharpsl_pm.h            |   2 +-
 arch/arm/mach-pxa/spitz_pm.c              |   9 +-
 arch/arm/plat-pxa/Makefile                |   2 -
 arch/arm/plat-pxa/dma.c                   | 386 ------------------------------
 arch/arm/plat-pxa/include/plat/dma.h      | 100 --------
 24 files changed, 95 insertions(+), 563 deletions(-)
 delete mode 100644 arch/arm/plat-pxa/dma.c
 delete mode 100644 arch/arm/plat-pxa/include/plat/dma.h

Cheers.

-- 
Robert

^ permalink raw reply

* [PATCH v8 8/9] arm64: pmu: Detect and enable multiple PMUs in an ACPI system
From: Will Deacon @ 2016-09-09 17:26 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1472507300-9844-9-git-send-email-jeremy.linton@arm.com>

On Mon, Aug 29, 2016 at 04:48:19PM -0500, Jeremy Linton wrote:
> +/* Count number and type of CPU cores in the system. */
> +static void __init arm_pmu_acpi_determine_cpu_types(struct list_head *pmus)
> +{
> +	int i;
> +	bool alloc_failure = false;
> +
> +	for_each_possible_cpu(i) {
> +		struct cpuinfo_arm64 *cinfo = per_cpu_ptr(&cpu_data, i);
> +		u32 partnum = MIDR_PARTNUM(cinfo->reg_midr);
> +		struct pmu_types *pmu;
> +
> +		list_for_each_entry(pmu, pmus, list) {
> +			if (pmu->cpu_type == partnum) {
> +				pmu->cpu_count++;
> +				break;
> +			}
> +		}
> +
> +		/* we didn't find the CPU type, add an entry to identify it */
> +		if ((&pmu->list == pmus) && (!alloc_failure)) {
> +			pmu = kzalloc(sizeof(struct pmu_types), GFP_KERNEL);
> +			if (!pmu) {
> +				pr_warn("Unable to allocate pmu_types\n");
> +				/*
> +				 * continue to count cpus for any pmu_types
> +				 * already allocated, but don't allocate any
> +				 * more pmu_types. This avoids undercounting.
> +				 */
> +				alloc_failure = true;

I thought we were ripping this out?

Will

^ permalink raw reply

* [PATCH 4/7] phy: meson: add USB2 PHY support for Meson8b and GXBB
From: Ben Dooks @ 2016-09-09 17:21 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <CAFBinCCDDwydB+RP0CZKoAW5Suxotn224ZFVWvt2OGW3gNJR1g@mail.gmail.com>

On 09/09/16 17:14, Martin Blumenstingl wrote:
> On Fri, Sep 9, 2016 at 5:33 PM, Kevin Hilman <khilman@baylibre.com> wrote:
>> However, the problem with all of the solutions proposed (runtime PM ones
>> included) is that we're forcing a board-specific design issue (2 devices
>> sharing a reset line) into a driver that should not have any
>> board-specific assumptions in it.
>>
>> For example, if this driver is used on another platform where different
>> PHYs have different reset lines, then one of them (the unlucky one who
>> is not probed first) will never get reset.  So any form of per-device
>> ref-counting is not a portable solution.
> maybe we should also consider Ben's solution: he played with the USB
> PHY on his Meson8b board. His approach was to have only one USB PHY
> driver instance which exposes two PHYs.
> The downside of this: the driver would have to know the offset of the
> PHYs (0x0 for the first PHY, 0x20 for the second), but we could handle
> the reset using runtime PM without any hacks.
>
> I checked the USB PHY reference driver: it seems that there will be a
> new USB PHY with the GXL/GXM SoCs.
> So maybe we could live with the assumption that the PHYs are at
> consecutive addresses.
>
>> I'm not sure yet how the reset framework is supposed to handle shared
>> reset lines, but that needs some investigation.  I quick glance and it
>> seems that reset controllers can have shared lines, so that should be
>> investigated.
> unfortunately shared resets are not allowed to use reset_control_reset, see [0]
>
>
> [0] http://lxr.free-electrons.com/source/drivers/reset/core.c#L102

If we didn't have the shared reset, we'd have one of node per phy
and not have to have two sub-nodes... I don't think any other bits
of the PHY framework are shared.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

^ permalink raw reply

* next build: 143 builds: 2 failed, 141 passed, 2 errors, 2 warnings (next-20160909)
From: Mark Brown @ 2016-09-09 17:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <m2oa3xgg98.fsf@baylibre.com>

On Fri, Sep 09, 2016 at 10:00:35AM -0700, Kevin Hilman wrote:
> Arnd Bergmann <arnd@arndb.de> writes:

> > Could we please update the gcc build on kernelci.org from "Linaro GCC 5.3-2016.02"
> > to the following version (Linaro GCC 5.3-2016.05) or later?

> I finally found the release tarballs for Linaro toolchains (the "latest"
> link on the linaro releases was stale, and pointing to 2016.02).

That link should be fixed now or shortly to avoid future confusion.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 473 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160909/dc2cea95/attachment.sig>

^ permalink raw reply

* [PATCH v2 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1
From: Catalin Marinas @ 2016-09-09 17:15 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1472828533-28197-4-git-send-email-catalin.marinas@arm.com>

On Fri, Sep 02, 2016 at 04:02:09PM +0100, Catalin Marinas wrote:
>  /*
>   * User access enabling/disabling.
>   */
> +#ifdef CONFIG_ARM64_TTBR0_PAN
> +static inline void uaccess_ttbr0_disable(void)
> +{
> +	unsigned long ttbr;
> +
> +	/* reserved_ttbr0 placed at the end of swapper_pg_dir */
> +	ttbr = read_sysreg(ttbr1_el1) + SWAPPER_DIR_SIZE;
> +	write_sysreg(ttbr, ttbr0_el1);
> +	isb();
> +}
> +
> +static inline void uaccess_ttbr0_enable(void)
> +{
> +	unsigned long flags;
> +
> +	/*
> +	 * Disable interrupts to avoid preemption and potential saved
> +	 * TTBR0_EL1 updates between reading the variable and the MSR.
> +	 */
> +	local_irq_save(flags);
> +	write_sysreg(current_thread_info()->ttbr0, ttbr0_el1);
> +	isb();
> +	local_irq_restore(flags);
> +}

I followed up with the ARM architects on potential improvements to this
sequence. In summary, changing TCR_EL1.A1 is not guaranteed to have an
effect unless it is followed by TLBI. IOW, we can't use this bit for a
quick switch to the reserved ASID.

Setting TCR_EL1.EPD0 to 1 would work as long as it is followed by an
ASID change to a reserved one with no entries in the TLB. However, the
code sequence above (and the corresponding asm ones) would become even
more complex, so I don't think we gain anything.

Untested, using EPD0 (the assembly version would look sligtly better
than the C version but still a few instructions more than what we
currently have):

static inline void uaccess_ttbr0_disable(void)
{
	unsigned long ttbr;
	unsigned long tcr;

	/* disable TTBR0 page table walks */
	tcr = read_sysreg(tcr_el1);
	tcr |= TCR_ELD0
	write_sysreg(tcr, tcr_el1);
	isb();

	/* mask out the ASID bits (zero is a reserved ASID) */
	ttbr = read_sysreg(ttbr0_el1);
	ttbr &= ~ASID_MASK;
	write_sysreg(ttbr, ttbr0_el1);
	isb();
}

static inline void uaccess_ttbr0_enable(void)
{
	unsigned long flags;

	local_irq_save(flags);

	ttbr = read_sysreg(ttbr0_el1);
	ttbr |= current_thread_info()->asid;
	write_sysreg(ttbr, ttbr0_el1);
	isb();

	/* enable TTBR0 page table walks */
	tcr = read_sysreg(tcr_el1);
	tcr |= TCR_ELD0
	write_sysreg(tcr, tcr_el1);
	isb();

	local_irq_restore(flags);
}

The IRQ disabling for the above sequence is still required since we need
to guarantee the atomicity of the ASID read with the TTBR0_EL1 write.

We may be able to avoid current_thread_info()->asid *if* we find some
other per-CPU place to store the ASID (unused TTBR1_EL1 bits was
suggested, though not sure about the architecture requirements on those
bits being zero when TCR_EL1.A1 is 0). But even with these in place, the
requirement to have to ISBs and the additional TCR_EL1 read/write
doesn't give us anything better.

In conclusion, I propose that we stick to the current TTBR0_EL1 switch
as per these patches.

-- 
Catalin

^ permalink raw reply

* [PATCH v3 1/8] arm64: KVM: Use static keys for selecting the GIC backend
From: Marc Zyngier @ 2016-09-09 17:06 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <57D2E0C6.1040608@arm.com>

On 09/09/16 17:18, Vladimir Murzin wrote:
> On 09/09/16 16:25, Marc Zyngier wrote:
>> On 09/09/16 16:14, Vladimir Murzin wrote:
>>> On 09/09/16 15:17, Marc Zyngier wrote:
>>>> On 09/09/16 14:45, Vladimir Murzin wrote:
>>>>> On 09/09/16 10:33, Vladimir Murzin wrote:
>>>>>> Hi Marc,
>>>>>>
>>>>>> On 09/09/16 10:19, Marc Zyngier wrote:
>>>>>>>> Hi Vladimir,
>>>>>>>>
>>>>>> ...
>>>>>>>>>>  
>>>>>>>>>> +extern struct static_key_false kvm_gicv3_cpuif;
>>>>>>>>
>>>>>>>> I think we should follow the model set by kvm_vgic_global_state, which
>>>>>>>> is declared in arm_vgic.h. Even better, we should *embed* the static key
>>>>>>>> in this structure. This will reduce the clutter and we wouldn't have to
>>>>>>>> deal with all the section stuff (the hyp_data thing is a good cleanup,
>>>>>>>> but I'd like to see it as a separate patch if possible).
>>>>>> Yes, it is what I was thinking about too, but was not sure about which
>>>>>> way to go, so hyp_data seemed me something we might reuse latter.
>>>>>> However, I agree that we can defer hyp_data thing...
>>>>>>
>>>>>
>>>>> I've just tried it out and it seems that static keys are not happy to
>>>>> accept a key after kern_hyp_va is applied at &kvm_vgic_global_state:
>>>>
>>>> Ah, there is a trick. You do not need kern_hyp_va at all, because this
>>>> is not evaluated as an expression at runtime (so the pointer doesn't matter).
>>>>
>>>
>>> Ah, right, thank for a tip! ;)
>>>
>>>>>> In file included from ./include/linux/jump_label.h:105:0,
>>>>>>                  from arch/arm64/kvm/hyp/switch.c:19:
>>>>>> ./arch/arm64/include/asm/jump_label.h: In function ?__guest_run?:
>>>>>> ./arch/arm64/include/asm/jump_label.h:31:2: warning: asm operand 0 probably doesn?t match constraints
>>>>>>   asm goto("1: nop\n\t"
>>>>>>   ^
>>>>>> ./arch/arm64/include/asm/jump_label.h:31:2: warning: asm operand 0 probably doesn?t match constraints
>>>>>>   asm goto("1: nop\n\t"
>>>>>>   ^
>>>>>> ./arch/arm64/include/asm/jump_label.h:31:2: error: impossible constraint in ?asm?
>>>>>>   asm goto("1: nop\n\t"
>>>>>>   ^
>>>>>> ./arch/arm64/include/asm/jump_label.h:31:2: error: impossible constraint in ?asm?
>>>>>>   asm goto("1: nop\n\t"
>>>>>>   ^
>>>>>> make[1]: *** [arch/arm64/kvm/hyp/switch.o] Error 1
>>>>>> make: *** [arch/arm64/kvm/hyp/switch.o] Error 2
>>>>>
>>>>> it looks like we cannot avoid hyp_data thing... if you don't mind I can
>>>>> do hyp_data clean-up in separate patch. Alternatively, we can do
>>>>> conversion to static keys for both architectures later as an
>>>>> optimisation step.
>>>>
>>>> Can you try the above first? I've just tried the same approach with my
>>>> vgic-trap series, and it compiles fine (untested though):
>>>
>>> I was about to try it out, but didn't manage to find a branch with
>>> vgic-trap series, so I did a quick fixup for my series and now it is
>>> running non-VHE boot tests and I don't expect issues with VHE one. I
>>> think diff bellow should work runtime too, but if you do want me to give
>>> it a try it'd be handy to have a branch I can pull from ;)
>>
>> I think Christoffer has pulled it into kvmarm/queue.
> 
> Nothing has exploded so far for both architectures.

Great. Hopefully you can respin the series next week.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply

* [PATCH v3 7/8] ARM: Move system register accessors to asm/cp15.h
From: Marc Zyngier @ 2016-09-09 17:05 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1473350810-10857-8-git-send-email-vladimir.murzin@arm.com>

On 08/09/16 17:06, Vladimir Murzin wrote:
> Headers linux/irqchip/arm-gic.v3.h and arch/arm/include/asm/kvm_hyp.h
> are included in virt/kvm/arm/hyp/vgic-v3-sr.c and both define macros
> called __ACCESS_CP15 and __ACCESS_CP15_64 which obviously creates a
> conflict. These macros were introduced independently for GIC and KVM
> and, in fact, do the same thing.
> 
> As an option we could add prefixes to KVM and GIC version of macros so
> they won't clash, but it'd introduce code duplication.  Alternatively,
> we could keep macro in, say, GIC header and include it in KVM one (or
> vice versa), but such dependency would not look nicer.
> 
> So we follow arm64 way (it handles this via sysreg.h) and move only
> single set of macros to asm/cp15.h
> 
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
>  arch/arm/include/asm/arch_gicv3.h |   27 +++++++++++----------------
>  arch/arm/include/asm/cp15.h       |   15 +++++++++++++++
>  arch/arm/include/asm/kvm_hyp.h    |   15 +--------------
>  3 files changed, 27 insertions(+), 30 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
> index e08d151..af25c32 100644
> --- a/arch/arm/include/asm/arch_gicv3.h
> +++ b/arch/arm/include/asm/arch_gicv3.h
> @@ -22,9 +22,7 @@
>  
>  #include <linux/io.h>
>  #include <asm/barrier.h>
> -
> -#define __ACCESS_CP15(CRn, Op1, CRm, Op2)	p15, Op1, %0, CRn, CRm, Op2
> -#define __ACCESS_CP15_64(Op1, CRm)		p15, Op1, %Q0, %R0, CRm
> +#include <asm/cp15.h>
>  
>  #define ICC_EOIR1			__ACCESS_CP15(c12, 0, c12, 1)
>  #define ICC_DIR				__ACCESS_CP15(c12, 0, c11, 1)
> @@ -102,58 +100,55 @@
>  
>  static inline void gic_write_eoir(u32 irq)
>  {
> -	asm volatile("mcr " __stringify(ICC_EOIR1) : : "r" (irq));
> +	write_sysreg(irq, ICC_EOIR1);
>  	isb();
>  }
>  
>  static inline void gic_write_dir(u32 val)
>  {
> -	asm volatile("mcr " __stringify(ICC_DIR) : : "r" (val));
> +	write_sysreg(val, ICC_DIR);
>  	isb();
>  }
>  
>  static inline u32 gic_read_iar(void)
>  {
> -	u32 irqstat;
> +	u32 irqstat = read_sysreg(ICC_IAR1);
>  
> -	asm volatile("mrc " __stringify(ICC_IAR1) : "=r" (irqstat));
>  	dsb(sy);
> +
>  	return irqstat;
>  }
>  
>  static inline void gic_write_pmr(u32 val)
>  {
> -	asm volatile("mcr " __stringify(ICC_PMR) : : "r" (val));
> +	write_sysreg(val, ICC_PMR);
>  }
>  
>  static inline void gic_write_ctlr(u32 val)
>  {
> -	asm volatile("mcr " __stringify(ICC_CTLR) : : "r" (val));
> +	write_sysreg(val, ICC_CTLR);
>  	isb();
>  }
>  
>  static inline void gic_write_grpen1(u32 val)
>  {
> -	asm volatile("mcr " __stringify(ICC_IGRPEN1) : : "r" (val));
> +	write_sysreg(val, ICC_IGRPEN1);
>  	isb();
>  }
>  
>  static inline void gic_write_sgi1r(u64 val)
>  {
> -	asm volatile("mcrr " __stringify(ICC_SGI1R) : : "r" (val));
> +	write_sysreg(val, ICC_SGI1R);
>  }
>  
>  static inline u32 gic_read_sre(void)
>  {
> -	u32 val;
> -
> -	asm volatile("mrc " __stringify(ICC_SRE) : "=r" (val));
> -	return val;
> +	return read_sysreg(ICC_SRE);
>  }
>  
>  static inline void gic_write_sre(u32 val)
>  {
> -	asm volatile("mcr " __stringify(ICC_SRE) : : "r" (val));
> +	write_sysreg(val, ICC_SRE);
>  	isb();
>  }
>  
> diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
> index c3f1152..f661732 100644
> --- a/arch/arm/include/asm/cp15.h
> +++ b/arch/arm/include/asm/cp15.h
> @@ -47,6 +47,21 @@
>  #define vectors_high()	(0)
>  #endif
>  
> +#define __ACCESS_CP15(CRn, Op1, CRm, Op2)	\
> +	"mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
> +#define __ACCESS_CP15_64(Op1, CRm)		\
> +	"mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
> +
> +#define __read_sysreg(r, w, c, t) ({				\
> +	t __val;						\
> +	asm volatile(r " " c : "=r" (__val));			\
> +	__val;							\
> +})
> +#define read_sysreg(...)		__read_sysreg(__VA_ARGS__)
> +
> +#define __write_sysreg(v, r, w, c, t)	asm volatile(w " " c : : "r" ((t)(v)))
> +#define write_sysreg(v, ...)		__write_sysreg(v, __VA_ARGS__)
> +

Shouldn't that be placed after the #ifdef below?

>  #ifdef CONFIG_CPU_CP15
>  
>  extern unsigned long cr_alignment;	/* defined in entry-armv.S */
> diff --git a/arch/arm/include/asm/kvm_hyp.h b/arch/arm/include/asm/kvm_hyp.h
> index bd9434e..0b475d2 100644
> --- a/arch/arm/include/asm/kvm_hyp.h
> +++ b/arch/arm/include/asm/kvm_hyp.h
> @@ -20,26 +20,13 @@
>  
>  #include <linux/compiler.h>
>  #include <linux/kvm_host.h>
> +#include <asm/cp15.h>
>  #include <asm/kvm_mmu.h>
>  #include <asm/vfp.h>
>  
> -#define __ACCESS_CP15(CRn, Op1, CRm, Op2)	\
> -	"mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
> -#define __ACCESS_CP15_64(Op1, CRm)		\
> -	"mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
>  #define __ACCESS_VFP(CRn)			\
>  	"mrc", "mcr", __stringify(p10, 7, %0, CRn, cr0, 0), u32
>  
> -#define __write_sysreg(v, r, w, c, t)	asm volatile(w " " c : : "r" ((t)(v)))
> -#define write_sysreg(v, ...)		__write_sysreg(v, __VA_ARGS__)
> -
> -#define __read_sysreg(r, w, c, t) ({				\
> -	t __val;						\
> -	asm volatile(r " " c : "=r" (__val));			\
> -	__val;							\
> -})
> -#define read_sysreg(...)		__read_sysreg(__VA_ARGS__)
> -
>  #define write_special(v, r)					\
>  	asm volatile("msr " __stringify(r) ", %0" : : "r" (v))
>  #define read_special(r) ({					\
> 

Could you please cc RMK on this, given that this touches a core arch/arm
file?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply


This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox