* [PATCH 4/7] phy: meson: add USB2 PHY support for Meson8b and GXBB
From: Martin Blumenstingl @ 2016-09-09 20:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b9730890-d98c-2c3a-8af1-96b8c394c30f@codethink.co.uk>
On Fri, Sep 9, 2016 at 7:21 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> On 09/09/16 17:14, Martin Blumenstingl wrote:
>>
>> On Fri, Sep 9, 2016 at 5:33 PM, Kevin Hilman <khilman@baylibre.com> wrote:
>>>
>>> However, the problem with all of the solutions proposed (runtime PM ones
>>> included) is that we're forcing a board-specific design issue (2 devices
>>> sharing a reset line) into a driver that should not have any
>>> board-specific assumptions in it.
>>>
>>> For example, if this driver is used on another platform where different
>>> PHYs have different reset lines, then one of them (the unlucky one who
>>> is not probed first) will never get reset. So any form of per-device
>>> ref-counting is not a portable solution.
>>
>> maybe we should also consider Ben's solution: he played with the USB
>> PHY on his Meson8b board. His approach was to have only one USB PHY
>> driver instance which exposes two PHYs.
>> The downside of this: the driver would have to know the offset of the
>> PHYs (0x0 for the first PHY, 0x20 for the second), but we could handle
>> the reset using runtime PM without any hacks.
>>
>> I checked the USB PHY reference driver: it seems that there will be a
>> new USB PHY with the GXL/GXM SoCs.
>> So maybe we could live with the assumption that the PHYs are at
>> consecutive addresses.
>>
>>> I'm not sure yet how the reset framework is supposed to handle shared
>>> reset lines, but that needs some investigation. I quick glance and it
>>> seems that reset controllers can have shared lines, so that should be
>>> investigated.
>>
>> unfortunately shared resets are not allowed to use reset_control_reset,
>> see [0]
>>
>>
>> [0] http://lxr.free-electrons.com/source/drivers/reset/core.c#L102
>
>
> If we didn't have the shared reset, we'd have one of node per phy
> and not have to have two sub-nodes... I don't think any other bits
> of the PHY framework are shared.
okay, sounds reasonable - so we should try to get this scenario
supported through by the reset framework -> see my other mail.
^ permalink raw reply
* [PATCH] hwmon: xgene: access mailbox as RAM
From: Hoan Tran @ 2016-09-09 20:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2852054.37zytD0HIa@wuerfel>
On Fri, Sep 9, 2016 at 12:58 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Friday, September 9, 2016 12:24:32 PM CEST Hoan Tran wrote:
>> On Fri, Sep 9, 2016 at 8:38 AM, Arnd Bergmann <arnd@arndb.de> wrote:
>> > The newly added hwmon driver fails to build in an allmodconfig
>> > index bc78a5d10182..e834dfb3acca 100644
>> > --- a/drivers/hwmon/xgene-hwmon.c
>> > +++ b/drivers/hwmon/xgene-hwmon.c
>> > @@ -34,7 +34,8 @@
>> > #include <linux/module.h>
>> > #include <linux/of.h>
>> > #include <linux/platform_device.h>
>> > -#include <acpi/acpi_io.h>
>> > +#include <linux/io.h>
>>
>> Alphabetical order.
>>
>> > struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;
>> > - void *ptr = generic_comm_base + 1;
>> > + u32 *ptr = (void*)(generic_comm_base + 1);
>>
>> Space before "*".
>
> Ok.
>
>> > @@ -652,9 +653,9 @@ static int xgene_hwmon_probe(struct platform_device *pdev)
>> > */
>> > ctx->comm_base_addr = cppc_ss->base_address;
>> > if (ctx->comm_base_addr) {
>> > - ctx->pcc_comm_addr =
>> > - acpi_os_ioremap(ctx->comm_base_addr,
>> > - cppc_ss->length);
>> > + ctx->pcc_comm_addr = memremap(ctx->comm_base_addr,
>> > + cppc_ss->length,
>> > + MEMREMAP_WT);
>>
>> It should be MEMREMAP_WB. As mailbox shared memory is on RAM and our
>> co-processor is also in the coherency domain.
>
> Right, I was wondering about this, since I could not figure out what
> the other side is (hardware, service processor or firmware).
> So MEMREMAP_WB makes sense here.
>
> Two more questions:
>
> * Any comment on the byte ordering of the data in this line:
>
> /* Copy the message to the PCC comm space */
> for (i = 0; i < sizeof(struct slimpro_resp_msg) / 4; i++)
> - writel_relaxed(msg[i], ptr + i * 4);
> + WRITE_ONCE(ptr[i], cpu_to_le32(msg[i]));
>
> This assumes that the old code was correct even when running on
> big-endian kernels and the message data consists of 32-bit data words.
> If the message has some other format instead, we would need to treat
> this as a byte stream and not do swapping here but instead do it
> (if any) in the code that reads or writes the actual data here.
This is 32-bit data words.
>
> * Are you sure you don't need any smp_rmb()/smp_wmb() barriers
> between the accesses?
No, we don't need a strict read/write during access PCC subspace. Just
make sure all access is committed before PCC send message to the
platform which done by PCC mailbox driver.
Thanks
Hoan
>
> Arnd
^ permalink raw reply
* [PATCH v2] hwmon: xgene: access mailbox as RAM
From: Hoan Tran @ 2016-09-09 20:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3475893.910N1IvcYZ@wuerfel>
Hi Arnd,
On Fri, Sep 9, 2016 at 1:10 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> The newly added hwmon driver fails to build in an allmodconfig
> kernel:
>
> ERROR: "memblock_is_memory" [drivers/hwmon/xgene-hwmon.ko] undefined!
>
> According to comments in the code, the mailbox is a shared memory region,
> not a set of MMIO registers, so we should use memremap() for mapping it
> instead of ioremap or acpi_os_ioremap, and pointer dereferences instead
> of readl/writel.
>
> The driver already uses plain kernel pointers, so it's a bit unusual
> to work with functions that operate on __iomem pointers, and this
> fixes that part too.
>
> I'm using READ_ONCE/WRITE_ONCE here to keep the existing behavior
> regarding the ordering of the accesses from the CPU, but note that
> there are no barriers (also unchanged from before).
>
> I'm also keeping the endianess behavior, though I'm unsure whether
> the message data was supposed to be in LE32 format in the first
> place, it's possible this was meant to be interpreted as a byte
> stream instead.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> v2: use write-back mapping instead of write-thru,
> minor coding style changes
>
> diff --git a/drivers/hwmon/xgene-hwmon.c b/drivers/hwmon/xgene-hwmon.c
> index bc78a5d10182..e5470bd49067 100644
> --- a/drivers/hwmon/xgene-hwmon.c
> +++ b/drivers/hwmon/xgene-hwmon.c
> @@ -27,6 +27,7 @@
> #include <linux/dma-mapping.h>
> #include <linux/hwmon.h>
> #include <linux/hwmon-sysfs.h>
> +#include <linux/io.h>
> #include <linux/interrupt.h>
> #include <linux/kfifo.h>
> #include <linux/mailbox_controller.h>
> @@ -34,7 +35,7 @@
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/platform_device.h>
> -#include <acpi/acpi_io.h>
> +
> #include <acpi/pcc.h>
>
> /* SLIMpro message defines */
> @@ -126,10 +127,10 @@ static u16 xgene_word_tst_and_clr(u16 *addr, u16 mask)
> {
> u16 ret, val;
>
> - val = readw_relaxed(addr);
> + val = le16_to_cpu(READ_ONCE(*addr));
> ret = val & mask;
> val &= ~mask;
> - writew_relaxed(val, addr);
> + WRITE_ONCE(*addr, cpu_to_le16(val));
>
> return ret;
> }
> @@ -137,7 +138,7 @@ static u16 xgene_word_tst_and_clr(u16 *addr, u16 mask)
> static int xgene_hwmon_pcc_rd(struct xgene_hwmon_dev *ctx, u32 *msg)
> {
> struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;
> - void *ptr = generic_comm_base + 1;
> + u32 *ptr = (void *)(generic_comm_base + 1);
> int rc, i;
> u16 val;
>
> @@ -146,21 +147,21 @@ static int xgene_hwmon_pcc_rd(struct xgene_hwmon_dev *ctx, u32 *msg)
> ctx->resp_pending = true;
>
> /* Write signature for subspace */
> - writel_relaxed(PCC_SIGNATURE_MASK | ctx->mbox_idx,
> - &generic_comm_base->signature);
> + WRITE_ONCE(generic_comm_base->signature,
> + cpu_to_le32(PCC_SIGNATURE_MASK | ctx->mbox_idx));
>
> /* Write to the shared command region */
> - writew_relaxed(MSG_TYPE(msg[0]) | PCCC_GENERATE_DB_INT,
> - &generic_comm_base->command);
> + WRITE_ONCE(generic_comm_base->command,
> + cpu_to_le16(MSG_TYPE(msg[0]) | PCCC_GENERATE_DB_INT));
>
> /* Flip CMD COMPLETE bit */
> - val = readw_relaxed(&generic_comm_base->status);
> + val = le16_to_cpu(READ_ONCE(generic_comm_base->status));
> val &= ~PCCS_CMD_COMPLETE;
> - writew_relaxed(val, &generic_comm_base->status);
> + WRITE_ONCE(generic_comm_base->status, cpu_to_le16(val));
>
> /* Copy the message to the PCC comm space */
> for (i = 0; i < sizeof(struct slimpro_resp_msg) / 4; i++)
> - writel_relaxed(msg[i], ptr + i * 4);
> + WRITE_ONCE(ptr[i], cpu_to_le32(msg[i]));
>
> /* Ring the doorbell */
> rc = mbox_send_message(ctx->mbox_chan, msg);
> @@ -652,9 +653,9 @@ static int xgene_hwmon_probe(struct platform_device *pdev)
> */
> ctx->comm_base_addr = cppc_ss->base_address;
> if (ctx->comm_base_addr) {
> - ctx->pcc_comm_addr =
> - acpi_os_ioremap(ctx->comm_base_addr,
> - cppc_ss->length);
> + ctx->pcc_comm_addr = memremap(ctx->comm_base_addr,
> + cppc_ss->length,
> + MEMREMAP_WB);
> } else {
> dev_err(&pdev->dev, "Failed to get PCC comm region\n");
> rc = -ENODEV;
>
Acked-by: Hoan Tran <hotran@apm.com>
Tested-by: Hoan Tran <hotran@apm.com>
Thanks
Hoan
^ permalink raw reply
* [PATCH] hwmon: xgene: access mailbox as RAM
From: Arnd Bergmann @ 2016-09-09 20:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFHUOYyGf0MFtDrYaAMSRjZ5hJ4yxV6wSa3BpGF73tyC6GQBxw@mail.gmail.com>
On Friday, September 9, 2016 1:43:17 PM CEST Hoan Tran wrote:
>
> > * Are you sure you don't need any smp_rmb()/smp_wmb() barriers
> > between the accesses?
>
> No, we don't need a strict read/write during access PCC subspace. Just
> make sure all access is committed before PCC send message to the
> platform which done by PCC mailbox driver.
>
Ok, got it. The PCC mailbox driver presumably uses writel() to
send the message, and that implies the necessary barrier
(unlike writel_relaxed), right?
Arnd
^ permalink raw reply
* [PATCH] hwmon: xgene: access mailbox as RAM
From: Hoan Tran @ 2016-09-09 20:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6198994.YhDCC7xNAM@wuerfel>
On Fri, Sep 9, 2016 at 1:50 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Friday, September 9, 2016 1:43:17 PM CEST Hoan Tran wrote:
>>
>> > * Are you sure you don't need any smp_rmb()/smp_wmb() barriers
>> > between the accesses?
>>
>> No, we don't need a strict read/write during access PCC subspace. Just
>> make sure all access is committed before PCC send message to the
>> platform which done by PCC mailbox driver.
>>
>
> Ok, got it. The PCC mailbox driver presumably uses writel() to
> send the message, and that implies the necessary barrier
> (unlike writel_relaxed), right?
Yes,
Hoan
>
> Arnd
>
^ permalink raw reply
* [PATCH v2 1/2] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support
From: Jagan Teki @ 2016-09-09 20:54 UTC (permalink / raw)
To: linux-arm-kernel
i.CoreM6 Quad/Dual modules are system on module solutions manufactured
by Engicam with following characteristics:
CPU NXP i.MX6 DQ, 800MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
Power supply Single 5V
MAX LCD RES FULLHD
and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- s/oaky/okay/g
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-icore.dts | 59 +++++++++++
arch/arm/boot/dts/imx6qdl-icore.dtsi | 186 +++++++++++++++++++++++++++++++++++
3 files changed, 246 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-icore.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-icore.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f79cac2..511510d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -374,6 +374,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw553x.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
+ imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-marsboard.dtb \
imx6q-nitrogen6x.dtb \
diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts
new file mode 100644
index 0000000..1645afd
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 Quad/Dual Starter Kit";
+ compatible = "fsl,imx6-icore", "fsl,imx6q";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
new file mode 100644
index 0000000..7bedfac
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,legacy-bch-geometry;
+ nand-on-flash-bbt;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpmi-nand {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
+ >;
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/2] ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support
From: Jagan Teki @ 2016-09-09 20:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473454481-6684-1-git-send-email-jagan@amarulasolutions.com>
i.CoreM6 DualLite/Solo modules are system on module solutions manufactured
by Engicam with following characteristics:
CPU NXP i.MX6 DL, 800MHz
RAM 1GB, 32, 64 bit, DDR3-800/1066
NAND SLC,512MB
Power supply Single 5V
MAX LCD RES FULLHD
and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- s/oaky/okay/g
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6dl-icore.dts | 59 ++++++++++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-icore.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 511510d..6175f44 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -333,6 +333,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw552x.dtb \
imx6dl-gw553x.dtb \
imx6dl-hummingboard.dtb \
+ imx6dl-icore.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts
new file mode 100644
index 0000000..55dd0e1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+ model = "Engicam i.CoreM6 DualLite/Solo Starter Kit";
+ compatible = "fsl,imx6-icore", "fsl,imx6dl";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support
From: Fabio Estevam @ 2016-09-09 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473453312-2786-1-git-send-email-jagan@amarulasolutions.com>
On Fri, Sep 9, 2016 at 5:35 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> +/dts-v1/;
> +
> +#include "imx6q.dtsi"
> +#include "imx6qdl-icore.dtsi"
> +
> +/ {
> + model = "Engicam i.CoreM6 Quad/Dual Starter Kit";
> + compatible = "fsl,imx6-icore", "fsl,imx6q";
Should be:
compatible = "engicam,imx6-icore", "fsl,imx6q";
You could also send a patch adding engicam entry to
Documentation/devicetree/bindings/vendor-prefixes.txt
> +};
> +
> +&can1 {
> + status = "oaky";
Should be "okay"
> +};
> +
> +&can2 {
> + status = "oaky";
Should be "okay"
> +&iomuxc {
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
> + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
No 0x80000000, please. Use the real IOMUX register value instead.
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
> + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
Same here.
^ permalink raw reply
* [PATCH v5] i2c: imx: make bus recovery through pinctrl optional
From: Uwe Kleine-König @ 2016-09-09 20:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <649e7e70becb94adf3b8c4ae2409ea00@agner.ch>
Hello,
On Fri, Sep 09, 2016 at 01:34:31PM -0700, Stefan Agner wrote:
> Yeah it is a bit a wording thing: In my understanding, pinctrl is
> required on SoC's witch have a pin controller... It is just that the
> driver does not need to get the pinctrl by itself because the stack is
> taking care of it implicitly. And yes, that makes the particular example
> not a real world example.
At first I thought, too, that it's a fatal problem if getting the
pinctrl stuff fails. IMHO that shows that the comments (or the code) are
still not good enough.
Maybe we should do something like that:
/*
* As the IP doesn't support bus recovery, we have to switch SCL and SDA
* to their GPIO function and do some bitbanging. These alternative
* pinmux settings can be described in the device tree by a separate
* pinctrl state "gpio". If this is missing this is not a big problem,
* the only implication is that we can't do bus recovery.
*/
static void i2c_imx_init_recovery_info(...)
{
...
and then put
i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
if (IS_ERR(i2c_imx->pinctrl))
return;
into this function (and remove it from i2c_imx_probe). This makes it
more obvious that .pinctrl is only ever used for recovery and as
i2c_imx_init_recovery_info is void there is no error to propagate.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH] ARM: dts: Configure panda SDIO WLAN wakeirq
From: Tony Lindgren @ 2016-09-09 21:00 UTC (permalink / raw)
To: linux-arm-kernel
Otherwise we have delays on noticing interrupts from the
WLAN card when idle.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap4-panda-common.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -446,6 +446,8 @@
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_pins>;
vmmc-supply = <&wl12xx_vmmc>;
+ interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0x10e>;
non-removable;
bus-width = <4>;
cap-power-off-card;
--
2.9.3
^ permalink raw reply
* [PATCHv2] ARM: dts: ARM: dts: Fix omap5 SDIO dat1 interrupt
From: Tony Lindgren @ 2016-09-09 21:02 UTC (permalink / raw)
To: linux-arm-kernel
Few changes to fix issues I've noticed while debugging omap5-uevm
wl18xx issues:
1. Move wlcore irq pin muxing under wlcore. This irq could be
different from gpio_wk14 on some board variants
2. Don't configure pull on wlcore irq pin. There is a 10k
pull up resistor R105 on the device to VDDS_1v8_MAIN
3. The padconf register for wlsdio_data1 is wrong, it's really
at 0x1a8 + 2 - 0x40 = 0x16a offset, not at 0x168 as that's
for wlsdio_data0
4. Mark the omap5-uevm wlan as compatible with ti,wl1837 as
that's what the TDK R078 part seems to be
Unfortunately all these changes still have no effect on getting
WLAN to work on omap5-uevm. I still keep getting constant errors
with wl12xx_queue_recovery_work.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap5-board-common.dtsi | 8 +++++---
arch/arm/boot/dts/omap5-uevm.dts | 4 ++++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -332,7 +332,7 @@
wlcore_irq_pin: pinmux_wlcore_irq_pin {
pinctrl-single,pins = <
- OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
+ OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
>;
};
};
@@ -355,15 +355,17 @@
non-removable;
cap-power-off-card;
pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins &wlcore_irq_pin>;
+ pinctrl-0 = <&mmc3_pins>;
interrupts-extended = <&gic GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
- &omap5_pmx_core 0x168>;
+ &omap5_pmx_core 0x16a>;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore at 2 {
compatible = "ti,wl1271";
reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlcore_irq_pin>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
ref-clock-frequency = <26000000>;
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -61,3 +61,7 @@
OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
>;
};
+
+&wlcore {
+ compatible = "ti,wl1837";
+};
--
2.9.3
^ permalink raw reply
* [PATCH] ARM: dts: Configure omap5 OTG ID pin
From: Tony Lindgren @ 2016-09-09 21:04 UTC (permalink / raw)
To: linux-arm-kernel
The ID pin GPIO comes from the PMIC. Let's configure it as a GPIO
for the driver to use, and also make sure the PMIC GPIO pin muxing
is correct. The PMIC pad1 and 2 values for omap5-uevm and igepv5 are
0x5a and 0x1b, we only need to clear bit 2 in pad1 register to make
the ID pin GPIO work.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap5-board-common.dtsi | 9 +++++++++
arch/arm/boot/dts/omap5.dtsi | 2 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index 6c5b0f8..10a466b 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -393,14 +393,23 @@
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
+ ti,mux-pad1 = <0xa1>;
+ ti,mux-pad2 = <0x1b>;
pinctrl-names = "default";
pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
+ palmas_gpio: gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
extcon_usb3: palmas_usb {
compatible = "ti,palmas-usb-vid";
ti,enable-vbus-detection;
ti,enable-id-detection;
ti,wakeup;
+ id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;
};
clk32kgaudio: palmas_clk32k at 1 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -863,7 +863,7 @@
#size-cells = <1>;
utmi-mode = <2>;
ranges;
- dwc3 at 4a030000 {
+ dwc3: dwc3 at 4a030000 {
compatible = "snps,dwc3";
reg = <0x4a030000 0x10000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
--
2.9.3
^ permalink raw reply related
* [PATCH] ARM: dts: Add support for more than 2GB of memory for omap5
From: Tony Lindgren @ 2016-09-09 21:05 UTC (permalink / raw)
To: linux-arm-kernel
Some omap5 variants have more than 2GB of memory available as
optional models. Let's update the dts files to use two address
cells similar to what dra7 is using with commit dae320ec3173
("ARM: dts: DRA7: change address-cells and size-cells").
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap5-cm-t54.dts | 2 +-
arch/arm/boot/dts/omap5-igep0050.dts | 2 +-
arch/arm/boot/dts/omap5-uevm.dts | 2 +-
arch/arm/boot/dts/omap5.dtsi | 22 +++++++++++-----------
4 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index c9390fa..b153f60 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -13,7 +13,7 @@
memory at 80000000 {
device_type = "memory";
- reg = <0x80000000 0x7F000000>; /* 2048 MB */
+ reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */
};
aliases {
diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts
index f24b449..078dd53 100644
--- a/arch/arm/boot/dts/omap5-igep0050.dts
+++ b/arch/arm/boot/dts/omap5-igep0050.dts
@@ -16,7 +16,7 @@
memory at 80000000 {
device_type = "memory";
- reg = <0x80000000 0x7f000000>; /* 2032 MB */
+ reg = <0x0 0x80000000 0 0x7f000000>; /* 2032 MB */
};
gpio_keys {
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 1770447..c3c23e4 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -15,7 +15,7 @@
memory at 80000000 {
device_type = "memory";
- reg = <0x80000000 0x7F000000>; /* 2032 MB */
+ reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
};
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -12,8 +12,8 @@
#include <dt-bindings/pinctrl/omap.h>
/ {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "ti,omap5";
interrupt-parent = <&wakeupgen>;
@@ -90,10 +90,10 @@
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
- reg = <0x48211000 0x1000>,
- <0x48212000 0x1000>,
- <0x48214000 0x2000>,
- <0x48216000 0x2000>;
+ reg = <0 0x48211000 0 0x1000>,
+ <0 0x48212000 0 0x1000>,
+ <0 0x48214000 0 0x2000>,
+ <0 0x48216000 0 0x2000>;
interrupt-parent = <&gic>;
};
@@ -101,7 +101,7 @@
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
- reg = <0x48281000 0x1000>;
+ reg = <0 0x48281000 0 0x1000>;
interrupt-parent = <&gic>;
};
@@ -129,11 +129,11 @@
compatible = "ti,omap5-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0 0 0 0xc0000000>;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
- reg = <0x44000000 0x2000>,
- <0x44800000 0x3000>,
- <0x45000000 0x4000>;
+ reg = <0 0x44000000 0 0x2000>,
+ <0 0x44800000 0 0x3000>,
+ <0 0x45000000 0 0x4000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
--
2.9.3
^ permalink raw reply related
* [PATCH] ARM: dts: Add power button support for igepv5
From: Tony Lindgren @ 2016-09-09 21:07 UTC (permalink / raw)
To: linux-arm-kernel
Add power button support for igepv5.
Cc: Agust? Fontquerni i Gorchs <afontquerni@iseebcn.com>
Cc: Enric Balletbo Serra <eballetbo@gmail.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Pau Pajuel <ppajuel@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap5-igep0050.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts
--- a/arch/arm/boot/dts/omap5-igep0050.dts
+++ b/arch/arm/boot/dts/omap5-igep0050.dts
@@ -7,6 +7,7 @@
*/
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include "omap5-board-common.dtsi"
/ {
@@ -17,6 +18,18 @@
device_type = "memory";
reg = <0x80000000 0x7f000000>; /* 2032 MB */
};
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&power_button_pin>;
+ pinctrl-names = "default";
+
+ power-button {
+ label = "Power Button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ };
+ };
};
&hdmi {
@@ -58,6 +71,12 @@
OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */
>;
};
+
+ power_button_pin: pinctrl_power_button_pin {
+ pinctrl-single,pins = <
+ OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */
+ >;
+ };
};
&tpd12s015 {
--
2.9.3
^ permalink raw reply
* [PATCH 1/8] ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.
From: Eric Anholt @ 2016-09-09 21:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473411924.6698.85.camel@redhat.com>
e<#secure method=pgpmime mode=sign>
Gerd Hoffmann <kraxel@redhat.com> writes:
> Hi,
>
>> According to this page [1] the pinctrl group for parallel display interface is
>> missing. Is it intended?
>>
>> [1] - http://elinux.org/RPi_BCM2835_GPIOs
>
> Just an oversight I guess. Eric?
>
> Does this look correct?
>
> + dpi_gpio4: dpi_gpio4 {
> + brcm,pins = <4 5 6 7 8 9 10 11 12 13
> + 14 15 16 17 18 19 20 21
> + 22 23 24 25 26 27>;
> + brcm,function = <BCM2835_FSEL_ALT2>;
> + };
For DPI, you also need pins 0-3 in there for clock and syncs.
That set of data pins would be for a 24-bit mode, which is what we
should be using for the Adafruit kippah + 7" panel combo.
^ permalink raw reply
* [PATCH 4/8] ARM: dts: bcm283x: Add a new EMMC pin group from the downstream tree.
From: Eric Anholt @ 2016-09-09 21:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87650770.23554.026b1e4b-e35d-48e6-9394-7eeea0ff9add.open-xchange@email.1und1.de>
Stefan Wahren <stefan.wahren@i2se.com> writes:
>> Gerd Hoffmann <kraxel@redhat.com> hat am 7. September 2016 um 12:31
>> geschrieben:
>>
>>
>> From: Eric Anholt <eric@anholt.net>
>>
>> This will be used for having EMMC (sdhci-bcm2835.c) drive the
>> wireless.
>
> sdhci-bcm2835.c has been replaced by sdhci-iproc.c
>
>>
>> Signed-off-by: Eric Anholt <eric@anholt.net>
>> ---
>> arch/arm/boot/dts/bcm283x.dtsi | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
>> index 062d09db..b6b1950 100644
>> --- a/arch/arm/boot/dts/bcm283x.dtsi
>> +++ b/arch/arm/boot/dts/bcm283x.dtsi
>> @@ -257,6 +257,11 @@
>> brcm,pins = <32 33>;
>> brcm,function = <BCM2835_FSEL_ALT3>;
>> };
>> + emmc_gpio34: emmc_gpio34 {
>> + brcm,pins = <34 35 36 37 38 39>;
>> + brcm,function = <BCM2835_FSEL_ALT3>;
>> + brcm,pull = <0 2 2 2 2 2>;
>
> How about adding pull defines to include/dt-bindings/pinctrl/bcm2835.h?
A fine idea, but it should not be a requirement for this series.
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^ permalink raw reply
* [PATCH 0/6] Enable Nomadik NHK15 graphics
From: Linus Walleij @ 2016-09-09 21:25 UTC (permalink / raw)
To: linux-arm-kernel
As all other pieces have been merged into the PWM and fbdev
subsystems, we can turn on graphics on the Nomadik NHK15
board.
Tested and works like a charm with boot penguin, console if
desired and fbsplash. Even blanks the screen properly to save
energy.
The missing DT bindings should probably have been merged in
the fbdev tree, but it doesn't matter where they are merged
so I plan to send this whole series as a pull request to
ARM SoC. The only non-DT change is the Kconfig change to
select MFD_SYSCON.
Linus Walleij (6):
ARM: dts: add STMPE PWM to the NHK15 device tree
dt-bindings: add vendor TPO
dt-bindings: Add TPO TPG110 binding
ARM: nomadik: select MFD_SYSCON
ARM: dts: add PMU to the NHK15 device tree
ARM: dts: add the CLCD LCD display to the NHK15
.../bindings/display/panel/tpo,tpg110.txt | 47 +++++++++++++++
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/arm/boot/dts/ste-nomadik-nhk15.dts | 68 ++++++++++++++++++++++
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 28 +++++++++
arch/arm/mach-nomadik/Kconfig | 1 +
5 files changed, 145 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt
--
2.7.4
^ permalink raw reply
* [PATCH 1/6] ARM: dts: add STMPE PWM to the NHK15 device tree
From: Linus Walleij @ 2016-09-09 21:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473456335-22767-1-git-send-email-linus.walleij@linaro.org>
This adds the STMPE PWM to the NHK15 device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-nomadik-nhk15.dts | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
index d35aa88791ad..3ec5c653ad56 100644
--- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -140,6 +140,10 @@
0x03020067 // Up
0x0303006c>; // Down
};
+ stmpe0_pwm: stmpe_pwm {
+ compatible = "st,stmpe-pwm";
+ #pwm-cells = <2>;
+ };
};
stmpe1: stmpe2401 at 44 {
compatible = "st,stmpe2401";
@@ -183,4 +187,24 @@
wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>;
};
};
+
+ bl: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&stmpe0_pwm 0 500000>;
+ pwm-names = "backlight";
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100
+ >;
+ default-brightness-level = <100>;
+ };
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/6] dt-bindings: add vendor TPO
From: Linus Walleij @ 2016-09-09 21:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473456335-22767-1-git-send-email-linus.walleij@linaro.org>
TPO was a merger on June 5 2006 of Toppoly Optoelectronics and
Philips Mobile Display Systems. They manufactured small and medium
mobile displays.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1992aa97d45a..65b7bbbc893f 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -270,6 +270,7 @@ toshiba Toshiba Corporation
toumaz Toumaz
tplink TP-LINK Technologies Co., Ltd.
tpk TPK U.S.A. LLC
+tpo TPO
tronfy Tronfy
tronsmart Tronsmart
truly Truly Semiconductors Limited
--
2.7.4
^ permalink raw reply related
* [PATCH 3/6] dt-bindings: Add TPO TPG110 binding
From: Linus Walleij @ 2016-09-09 21:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473456335-22767-1-git-send-email-linus.walleij@linaro.org>
This adds device tree bindings for the TPO TPG110 panel found
mounted in the Nomadik NHK8815.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
.../bindings/display/panel/tpo,tpg110.txt | 47 ++++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt
diff --git a/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt b/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt
new file mode 100644
index 000000000000..f5e3c6f2095a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt
@@ -0,0 +1,47 @@
+TPO TPG110 Panel
+================
+
+This binding builds on the DPI bindings, adding a few properties
+as a superset of a DPI. See panel-dpi.txt for the required DPI
+bindings.
+
+Required properties:
+- compatible : "tpo,tpg110"
+- grestb-gpios : panel reset GPIO
+- scen-gpios : serial control enable GPIO
+- scl-gpios : serial control clock line GPIO
+- sda-gpios : serial control data line GPIO
+
+Required nodes:
+- Video port for DPI input, see panel-dpi.txt
+- Panel timing for DPI setup, see panel-dpi.txt
+
+Example
+-------
+
+panel {
+ compatible = "tpo,tpg110", "panel-dpi";
+ grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>;
+ scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ backlight = <&bl>;
+
+ port {
+ nomadik_clcd_panel: endpoint {
+ remote-endpoint = <&nomadik_clcd_pads>;
+ };
+ };
+
+ panel-timing {
+ clock-frequency = <33200000>;
+ hactive = <800>;
+ hback-porch = <216>;
+ hfront-porch = <40>;
+ hsync-len = <1>;
+ vactive = <480>;
+ vback-porch = <35>;
+ vfront-porch = <10>;
+ vsync-len = <1>;
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 4/6] ARM: nomadik: select MFD_SYSCON
From: Linus Walleij @ 2016-09-09 21:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473456335-22767-1-git-send-email-linus.walleij@linaro.org>
Since the Power Management Unit is using syscon to access a
set of necessary hardware muxing, let's select MFD_SYSCON for
the Nomadik subarchitecture.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-nomadik/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index b7e9801fdaa4..3ae45b8d7b0a 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -7,6 +7,7 @@ menuconfig ARCH_NOMADIK
select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
select CPU_ARM926T
select GPIOLIB
+ select MFD_SYSCON
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select PINCTRL_NOMADIK
--
2.7.4
^ permalink raw reply related
* [PATCH 5/6] ARM: dts: add PMU to the NHK15 device tree
From: Linus Walleij @ 2016-09-09 21:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473456335-22767-1-git-send-email-linus.walleij@linaro.org>
The so-called Nomadik Power Mangament Unit is actually a set
of some power management registers and some miscellaneous
system control stuff like muxing of entire hardware units.
Add this as a system controller.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index d2d532a9d783..80a3c9ccccd9 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -168,6 +168,12 @@
};
};
+ /* Power Management Unit */
+ pmu: pmu at 101e9000 {
+ compatible = "stericsson,nomadik-pmu", "syscon";
+ reg = <0x101e0000 0x1000>;
+ };
+
src: src at 101e0000 {
compatible = "stericsson,nomadik-src";
reg = <0x101e0000 0x1000>;
--
2.7.4
^ permalink raw reply related
* [PATCH 6/6] ARM: dts: add the CLCD LCD display to the NHK15
From: Linus Walleij @ 2016-09-09 21:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473456335-22767-1-git-send-email-linus.walleij@linaro.org>
This adds the TPG110 TDO43MTEA2 24-bit RGB LCD panel and sets
up the Nomadik device tree to activate the CLCD and connect it
to this panel.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-nomadik-nhk15.dts | 44 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 22 +++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
index 3ec5c653ad56..1ec46a794a4d 100644
--- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -176,6 +176,50 @@
};
amba {
+ clcd at 10120000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&clcd_24bit_mux>;
+ port {
+ nomadik_clcd_pads: endpoint {
+ remote-endpoint = <&nomadik_clcd_panel>;
+ arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
+ };
+ };
+
+ /*
+ * WVGA connector 21
+ * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB
+ * with TPO touch screen.
+ */
+ panel {
+ compatible = "tpo,tpg110", "panel-dpi";
+ grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>;
+ scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ backlight = <&bl>;
+
+ port {
+ nomadik_clcd_panel: endpoint {
+ remote-endpoint = <&nomadik_clcd_pads>;
+ };
+ };
+
+ panel-timing {
+ clock-frequency = <33200000>;
+ hactive = <800>;
+ hback-porch = <216>;
+ hfront-porch = <40>;
+ hsync-len = <1>;
+ vactive = <480>;
+ vback-porch = <35>;
+ vfront-porch = <10>;
+ vsync-len = <1>;
+ };
+ };
+ };
+
/* Activate RX/TX and CTS/RTS on UART 0 */
uart0: uart at 101fd000 {
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 80a3c9ccccd9..adb1c0998b81 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -166,6 +166,18 @@
};
};
};
+ clcd {
+ /*
+ * This should be activated to use the additional
+ * 8 lines for bits 16 thru 23 from the CLCD block.
+ */
+ clcd_24bit_mux: clcd_mux {
+ clcd_24bit_mux {
+ function = "clcd";
+ groups = "clcd_16_23_b_1";
+ };
+ };
+ };
};
/* Power Management Unit */
@@ -732,6 +744,16 @@
#size-cells = <1>;
ranges;
+ clcd at 10120000 {
+ compatible = "arm,pl110", "arm,primecell";
+ reg = <0x10120000 0x1000>;
+ interrupt-names = "combined";
+ interrupts = <14>;
+ clocks = <&clcdclk>, <&hclkclcd>;
+ clock-names = "clcdclk", "apb_pclk";
+ status = "disabled";
+ };
+
vica: intc at 10140000 {
compatible = "arm,versatile-vic";
interrupt-controller;
--
2.7.4
^ permalink raw reply related
* [RFC 0/1] misc: Add Allwinner Q8 tablet hardware manager
From: Rob Herring @ 2016-09-09 21:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160901190820.21987-1-hdegoede@redhat.com>
On Thu, Sep 1, 2016 at 2:08 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi All,
>
> Here is a first RFC for the q8 tablet hw-manager I've been talking
> about for a while now.
>
> The touchscreen part is finished, I'll start working on the
> accelerometer bits next.
This at least partially overlaps with the "overlay manager" just
posted. A dev board having different devices attached and a production
device have 2nd source components are not really different problems.
We need a common solution and can't have each platform making up their
own scheme. What's different for you is how you select what changes or
overlay to apply and that is fine to be platform specific. I think you
should be using overlays here as well.
> Note that this requires the "of: changesets: Introduce changeset
> helper methods" patch from Pantelis. If that is still not upstream
> when I'm ready to post a non RFC, I'll post a new version of that
> myself.
I'm waiting for it to be reposted. IIRC, I only had some minor comments.
Rob
^ permalink raw reply
* [RFC] misc: Add Allwinner Q8 tablet hardware manager
From: Rob Herring @ 2016-09-09 21:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160901190820.21987-2-hdegoede@redhat.com>
On Thu, Sep 1, 2016 at 2:08 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Allwinnner A13 / A23 / A33 based Q8 tablets are popular cheap 7" tablets
> of which a new batch is produced every few weeks. Each batch uses a
> different mix of touchscreen, accelerometer and wifi peripherals.
>
> Given that each batch is different creating a devicetree for each variant
> is not desirable. This commit adds a Q8 tablet hardware manager which
> auto-detects the touchscreen and accelerometer so that a single generic
> dts can be used for these tablets.
>
> The wifi is connected to a discoverable bus (sdio or usb) and will be
> autodetected by the mmc resp. usb subsystems.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> .../misc/allwinner,sunxi-q8-hardwaremgr.txt | 52 +++
> drivers/misc/Kconfig | 12 +
> drivers/misc/Makefile | 1 +
> drivers/misc/q8-hardwaremgr.c | 512 +++++++++++++++++++++
> 4 files changed, 577 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt
> create mode 100644 drivers/misc/q8-hardwaremgr.c
>
> diff --git a/Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt b/Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt
> new file mode 100644
> index 0000000..f428bf5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt
> @@ -0,0 +1,52 @@
> +Q8 tablet hardware manager
> +--------------------------
> +
> +Allwinnner A13 / A23 / A33 based Q8 tablets are popular cheap 7" tablets of
> +which a new batch is produced every few weeks. Each batch uses a different
> +mix of touchscreen, accelerometer and wifi peripherals.
> +
> +Given that each batch is different creating a devicetree for each variant is
> +not desirable. The Q8 tablet hardware manager bindings are bindings for an os
> +module which auto-detects the touchscreen so that a single
> +generic dts can be used for these tablets.
> +
> +The wifi is connected to a discoverable bus and will be autodetected by the os.
> +
> +Required properties:
> + - compatible : "allwinner,sunxi-q8-hardwaremgr"
> + - touchscreen : phandle of a template touchscreen node, this must be a
> + child node of the touchscreen i2c bus
> +
> +Optional properties:
> + - touchscreen-supply : regulator phandle for the touchscreen vdd supply
While I said I think you should be using overlays here, you could also
do it without. However, this node has to go. It is not h/w, and you
are putting it here purely to instantiate a driver. For the
touchscreen property, surely you know where the touchscreen is located
in the DT? If not, of_find_node_by_name()? For touchscreen-supply, I
assume this is to turn on the supply so you can talk to the touch
controller. There's no reason the supply can't just be in the
touchscreen node itself.
> +
> +touschreen node required properties:
> + - interrupt-parent : phandle pointing to the interrupt controller
> + serving the touchscreen interrupt
> + - interrupts : interrupt specification for the touchscreen interrupt
> + - power-gpios : Specification for the pin connected to the touchscreen's
> + enable / wake pin. This needs to be driven high to
> + enable the touchscreen controller
> +
> +Example:
> +
> +/ {
> + hwmgr {
> + compatible = "allwinner,sunxi-q8-hardwaremgr";
> + touchscreen = <&touchscreen>;
> + touchscreen-supply = <®_ldo_io1>;
> + };
> +};
> +
> +&i2c0 {
> + touchscreen: touchscreen at 0 {
> + interrupt-parent = <&pio>;
> + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */
> + power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> + /*
> + * Enabled by sunxi-q8-hardwaremgr if it detects a
> + * known model touchscreen.
> + */
> + status = "disabled";
> + };
> +};
^ permalink raw reply
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