* [PATCH 5/5] arm/arm64: vgic-new: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl
From: Marc Zyngier @ 2016-09-12 8:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473510138-4719-6-git-send-email-vijay.kilari@gmail.com>
On 10/09/16 13:22, vijay.kilari at gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>
> Userspace requires to store and restore of line_level for
> level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> ---
> arch/arm64/include/uapi/asm/kvm.h | 6 +++++
> virt/kvm/arm/vgic/vgic-kvm-device.c | 48 ++++++++++++++++++++++++++++++++++++-
> virt/kvm/arm/vgic/vgic-mmio-v3.c | 11 +++++++++
> virt/kvm/arm/vgic/vgic-mmio.c | 29 ++++++++++++++++++++++
> virt/kvm/arm/vgic/vgic-mmio.h | 5 ++++
> virt/kvm/arm/vgic/vgic.h | 3 +++
> 6 files changed, 101 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
> index 91c7137..4100f8c 100644
> --- a/arch/arm64/include/uapi/asm/kvm.h
> +++ b/arch/arm64/include/uapi/asm/kvm.h
> @@ -211,6 +211,12 @@ struct kvm_arch_memory_slot {
> #define KVM_DEV_ARM_VGIC_GRP_CTRL 4
> #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
> #define KVM_DEV_ARM_VGIC_CPU_SYSREGS 6
> +#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
> +#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
> +#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
> + (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
> +#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
> +#define VGIC_LEVEL_INFO_LINE_LEVEL 0
>
> #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
>
> diff --git a/virt/kvm/arm/vgic/vgic-kvm-device.c b/virt/kvm/arm/vgic/vgic-kvm-device.c
> index e580b6d..41de527 100644
> --- a/virt/kvm/arm/vgic/vgic-kvm-device.c
> +++ b/virt/kvm/arm/vgic/vgic-kvm-device.c
> @@ -517,6 +517,23 @@ static int vgic_attr_regs_access_v3(struct kvm_device *dev,
> regid, reg);
> break;
> }
> + case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
> + unsigned int info, intid;
> +
> + info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
> + KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT;
> + if (info == VGIC_LEVEL_INFO_LINE_LEVEL) {
> + intid = attr->attr &
> + KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK;
> + ret = vgic_v3_line_level_info_uaccess(vcpu, is_write,
> + intid, &tmp32);
> + if (!is_write)
> + *reg = tmp32;
How is tmp32 initialized on a write?
> + } else {
> + ret = -EINVAL;
> + }
> + break;
> + }
> default:
> ret = -EINVAL;
> break;
> @@ -559,6 +576,17 @@ static int vgic_v3_set_attr(struct kvm_device *dev,
>
> return vgic_attr_regs_access_v3(dev, attr, ®, true);
> }
> + case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
> + u32 __user *uaddr = (u32 __user *)(long)attr->addr;
> + u64 reg;
> + u32 tmp32;
> +
> + if (get_user(tmp32, uaddr))
> + return -EFAULT;
> +
> + reg = tmp32;
> + return vgic_attr_regs_access_v3(dev, attr, ®, true);
> + }
> }
> return -ENXIO;
> }
> @@ -595,8 +623,18 @@ static int vgic_v3_get_attr(struct kvm_device *dev,
> return ret;
> return put_user(reg, uaddr);
> }
> - }
> + case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
> + u32 __user *uaddr = (u32 __user *)(long)attr->addr;
> + u64 reg;
> + u32 tmp32;
>
> + ret = vgic_attr_regs_access_v3(dev, attr, ®, false);
> + if (ret)
> + return ret;
> + tmp32 = reg;
> + return put_user(tmp32, uaddr);
> + }
> + }
> return -ENXIO;
> }
>
> @@ -617,11 +655,19 @@ static int vgic_v3_has_attr(struct kvm_device *dev,
> return vgic_v3_has_attr_regs(dev, attr);
> case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
> return 0;
> + case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
> + if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
> + KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) ==
> + VGIC_LEVEL_INFO_LINE_LEVEL)
> + return 0;
> + break;
> + }
> case KVM_DEV_ARM_VGIC_GRP_CTRL:
> switch (attr->attr) {
> case KVM_DEV_ARM_VGIC_CTRL_INIT:
> return 0;
> }
> + break;
> }
> return -ENXIO;
> }
> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c
> index 04e0f2c..826c618 100644
> --- a/virt/kvm/arm/vgic/vgic-mmio-v3.c
> +++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c
> @@ -748,3 +748,14 @@ int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
> return vgic_uaccess(vcpu, &rd_dev, is_write,
> offset, val);
> }
> +
> +int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
> + u32 intid, u32 *val)
> +{
> + if (is_write)
> + vgic_write_irq_line_level_info(vcpu, intid, *val);
> + else
> + *val = vgic_read_irq_line_level_info(vcpu, intid);
> +
> + return 0;
> +}
> diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
> index 81d851c..9cc3900 100644
> --- a/virt/kvm/arm/vgic/vgic-mmio.c
> +++ b/virt/kvm/arm/vgic/vgic-mmio.c
> @@ -425,6 +425,35 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
> }
> }
>
> +unsigned long vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
> +{
> + int i;
> + unsigned long val = 0;
> +
> + for (i = 0; i < 32; i++) {
> + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
> +
> + if (irq->line_level)
> + val |= (1U << i);
Missing vgic_put_irq().
> + }
> +
> + return val;
> +}
> +
> +void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
> + const unsigned long val)
> +{
> + int i;
> +
> + for_each_set_bit(i, &val, 32) {
> + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
> +
> + spin_lock(&irq->irq_lock);
> + irq->line_level = true;
> + spin_unlock(&irq->irq_lock);
Same here.
> + }
> +}
> +
> static int match_region(const void *key, const void *elt)
> {
> const unsigned int offset = (unsigned long)key;
> diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h
> index 9a0109b..83bf9f1 100644
> --- a/virt/kvm/arm/vgic/vgic-mmio.h
> +++ b/virt/kvm/arm/vgic/vgic-mmio.h
> @@ -188,6 +188,11 @@ int vgic_validate_mmio_region_addr(struct kvm_device *dev,
> const struct vgic_register_region *regions,
> int nr_regions, gpa_t addr);
>
> +unsigned long vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid);
> +
> +void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
> + const unsigned long val);
> +
> unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
>
> unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
> diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
> index 04a397c..52f4f71 100644
> --- a/virt/kvm/arm/vgic/vgic.h
> +++ b/virt/kvm/arm/vgic/vgic.h
> @@ -107,6 +107,9 @@ int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
> u64 id, u64 *val);
> int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
> u64 *reg);
> +int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
> + u32 intid, u32 *val);
> +
> #else
> static inline void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
> {
>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v4 1/5] arm/arm64: vgic-new: Implement support for userspace access
From: Marc Zyngier @ 2016-09-12 8:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALicx6sHYqwGdW_zwE9d8BWO2BucQM6gEoLZAtJ6XG0AjAuGGw@mail.gmail.com>
On 12/09/16 09:46, Vijay Kilari wrote:
> On Mon, Sep 12, 2016 at 1:55 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On 10/09/16 13:22, vijay.kilari at gmail.com wrote:
>>> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>>>
>>> +
>>> +void vgic_uaccess_write_pending(struct kvm_vcpu *vcpu,
>>> + gpa_t addr, unsigned int len,
>>> + unsigned long val)
>>> +{
>>> + u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
>>> + int i;
>>> +
>>> + for (i = 0; i < len * 8; i++) {
>>> + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
>>> +
>>> + spin_lock(&irq->irq_lock);
>>> + if (test_bit(i, &val)) {
>>> + irq->pending = true;
>>> + irq->soft_pending = true;
>>> + vgic_queue_irq_unlock(vcpu->kvm, irq);
>>> + } else {
>>> + irq->soft_pending = false;
>>> + if (irq->config == VGIC_CONFIG_EDGE ||
>>> + (irq->config == VGIC_CONFIG_LEVEL &&
>>> + !irq->line_level))
>>> + irq->pending = false;
>>> + spin_unlock(&irq->irq_lock);
>>> + }
>>> +
>>> + vgic_put_irq(vcpu->kvm, irq);
>>> + }
>>> +}
>>> +
>>
>> These two functions only seems to be called from the GICv3 code. What is
>> the rational for making them globally accessible? Or should they also be
>> wired into the GICv2 code?
>
> Yes, probably this might be required for V2. But I don't have GICv2 platform
> to implement and verify it. Also not aware if someone is looking at
> migration with GICv2
> platform with this new vgic code.
Migration is already supported, and we can always verify it once you've
made the change.
>
> Can be kept here for later to wire into GICv2 code.
I don't think so. You are implementing this code, so please wire it into
the potential users.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* Regmap regression in next caused by of_iomap change
From: Arnd Bergmann @ 2016-09-12 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160912085527.GA1873@dell>
On Monday, September 12, 2016 9:55:27 AM CEST Lee Jones wrote:
> On Thu, 08 Sep 2016, Arnd Bergmann wrote:
>
> > On Thursday, September 8, 2016 11:41:12 AM CEST Tony Lindgren wrote:
> > > Hi,
> > >
> > > Looks like commit 39de2c4275a9 ("mfd: syscon: Make use of of_iomap")
> > > makes at least MMC PBIAS regulator stop working on omap3.
> > >
> > > That's probably because of_syscon_register uses the now unintialized
> > > struct resource res to set syscon_config.max_register.
> >
> > Looks correct. Lee, please send a revert of that patch to Linus
> > along with any other fixes you may have.
>
> No need. It's not in Mainline.
>
Ah, good, I misread the history then.
Arnd
^ permalink raw reply
* Regmap regression in next caused by of_iomap change
From: Lee Jones @ 2016-09-12 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4088076.eNNe5WgnxT@wuerfel>
On Thu, 08 Sep 2016, Arnd Bergmann wrote:
> On Thursday, September 8, 2016 11:41:12 AM CEST Tony Lindgren wrote:
> > Hi,
> >
> > Looks like commit 39de2c4275a9 ("mfd: syscon: Make use of of_iomap")
> > makes at least MMC PBIAS regulator stop working on omap3.
> >
> > That's probably because of_syscon_register uses the now unintialized
> > struct resource res to set syscon_config.max_register.
>
> Looks correct. Lee, please send a revert of that patch to Linus
> along with any other fixes you may have.
No need. It's not in Mainline.
> > I have a strange deja vu feeling that we've been through this
> > before See commit ca668f0edfae ("mfd: syscon: Set regmap max_register
> > in of_syscon_register")
> >
> > Maybe we should add comments there instead?
>
> I wonder why gcc didn't detect this case. I usually do my
> test builds with -Wmaybe-uninitialized that should have
> caught it but didn't.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v7 2/8] arm: parse cpu capacity-dmips-mhz from DT
From: Juri Lelli @ 2016-09-12 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKfTPtDEmAwLR58hOFeAVgfKaSVCQaLrr3VyH_QMkcuty5YiKQ@mail.gmail.com>
Hi,
On 12/09/16 10:36, Vincent Guittot wrote:
> Hi Juri,
>
> On 5 September 2016 at 16:22, Juri Lelli <juri.lelli@arm.com> wrote:
> > With the introduction of cpu capacity-dmips-mhz bindings, CPU capacities
> > can now be calculated from values extracted from DT and information
> > coming from cpufreq. Add parsing of DT information at boot time, and
> > complement it with cpufreq information. We keep code that can produce
> > same information, based on different DT properties and hard-coded
> > values, as fall-back for backward compatibility.
> >
> > Caveat: the information provided by this patch will start to be used in
> > the future. We need to #define arch_scale_cpu_capacity to something
> > provided in arch, so that scheduler's default implementation (which gets
> > used if arch_scale_cpu_capacity is not defined) is overwritten.
> >
> > Cc: Russell King <linux@arm.linux.org.uk>
> > Signed-off-by: Juri Lelli <juri.lelli@arm.com>
>
> Acked-by: Vincent Guittot <vincent.guittot@linaro.org>
>
Thanks!
Best,
- Juri
^ permalink raw reply
* [PATCH v7 4/8] arm64: parse cpu capacity-dmips-mhz from DT
From: Juri Lelli @ 2016-09-12 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKfTPtCN9zMtL82zc_=-KZ6U+cMORi+JTBVLDxKccY2hbJ=3vw@mail.gmail.com>
Hi,
On 12/09/16 10:37, Vincent Guittot wrote:
> Hi Juri,
>
> On 5 September 2016 at 16:22, Juri Lelli <juri.lelli@arm.com> wrote:
> > With the introduction of cpu capacity-dmips-mhz bindings, CPU capacities
> > can now be calculated from values extracted from DT and information
> > coming from cpufreq. Add parsing of DT information at boot time, and
> > complement it with cpufreq information. Also, store such information
> > using per CPU variables, as we do for arm.
> >
> > Caveat: the information provided by this patch will start to be used in
> > the future. We need to #define arch_scale_cpu_capacity to something
> > provided in arch, so that scheduler's default implementation (which gets
> > used if arch_scale_cpu_capacity is not defined) is overwritten.
> >
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will.deacon@arm.com>
> > Cc: Mark Brown <broonie@kernel.org>
> > Cc: Sudeep Holla <sudeep.holla@arm.com>
> > Signed-off-by: Juri Lelli <juri.lelli@arm.com>
>
> Acked-by: Vincent Guittot <vincent.guittot@linaro.org>
>
Thanks!
Best,
- Juri
^ permalink raw reply
* [PATCH v4 4/5] arm/arm64: vgic-new: Implement VGICv3 CPU interface access
From: Vijay Kilari @ 2016-09-12 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160911085612.6bf785e1@arm.com>
()
On Sun, Sep 11, 2016 at 1:26 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On Sat, 10 Sep 2016 17:52:17 +0530
> vijay.kilari at gmail.com wrote:
>
>> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>>
>> VGICv3 CPU interface registers are accessed using
>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
>> as 64-bit. The cpu MPIDR value is passed along with register id.
>> is used to identify the cpu for registers access.
>>
>> The version of VGIC v3 specification is define here
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
>>
>> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>> ---
>> arch/arm64/include/uapi/asm/kvm.h | 3 +
>> arch/arm64/kvm/Makefile | 1 +
>> include/linux/irqchip/arm-gic-v3.h | 32 ++++-
>> virt/kvm/arm/vgic/vgic-kvm-device.c | 27 ++++
>> virt/kvm/arm/vgic/vgic-mmio-v2.c | 16 ---
>> virt/kvm/arm/vgic/vgic-mmio-v3.c | 18 +++
>> virt/kvm/arm/vgic/vgic-mmio.c | 16 +++
>> virt/kvm/arm/vgic/vgic-sys-reg-v3.c | 261 ++++++++++++++++++++++++++++++++++++
>> virt/kvm/arm/vgic/vgic-v3.c | 4 +
>> virt/kvm/arm/vgic/vgic.h | 15 +++
>> 10 files changed, 376 insertions(+), 17 deletions(-)
>>
>> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
>> index 56dc08d..91c7137 100644
>> --- a/arch/arm64/include/uapi/asm/kvm.h
>> +++ b/arch/arm64/include/uapi/asm/kvm.h
>> @@ -206,9 +206,12 @@ struct kvm_arch_memory_slot {
>> (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
>> #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
>> #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
>> +#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
>> #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
>> #define KVM_DEV_ARM_VGIC_GRP_CTRL 4
>> #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
>> +#define KVM_DEV_ARM_VGIC_CPU_SYSREGS 6
>> +
>> #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
>>
>> /* Device Control API on vcpu fd */
>> diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
>> index d50a82a..1a14e29 100644
>> --- a/arch/arm64/kvm/Makefile
>> +++ b/arch/arm64/kvm/Makefile
>> @@ -32,5 +32,6 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-mmio-v3.o
>> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-kvm-device.o
>> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-its.o
>> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/irqchip.o
>> +kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-sys-reg-v3.o
>> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
>> kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o
>> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
>> index 99ac022..22ec183 100644
>> --- a/include/linux/irqchip/arm-gic-v3.h
>> +++ b/include/linux/irqchip/arm-gic-v3.h
>> @@ -354,6 +354,24 @@
>> */
>> #define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)
>> #define ICC_CTLR_EL1_EOImode_drop (1U << 1)
>> +#define ICC_CTLR_EL1_CBPR_SHIFT (0)
>> +#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
>> +#define ICC_CTLR_EL1_EOImode_SHIFT (1)
>
> Since you're adding this, please rewrite the two existing EOImode
> macros to use this new define.
>
>> +#define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
>> +#define ICC_CTLR_EL1_PRI_BITS_SHIFT (8)
>> +#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
>> +#define ICC_CTLR_EL1_ID_BITS_SHIFT (11)
>> +#define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
>> +#define ICC_PMR_EL1_SHIFT (0)
>> +#define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
>> +#define ICC_BPR0_EL1_SHIFT (0)
>> +#define ICC_BPR0_EL1_MASK (0x7 << ICC_PMR_EL1_SHIFT)
>> +#define ICC_BPR1_EL1_SHIFT (0)
>> +#define ICC_BPR1_EL1_MASK (0x7 << ICC_PMR_EL1_SHIFT)
>> +#define ICC_IGRPEN0_EL1_SHIFT (0)
>> +#define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
>> +#define ICC_IGRPEN1_EL1_SHIFT (0)
>> +#define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
>> #define ICC_SRE_EL1_SRE (1U << 0)
>>
>> /*
>> @@ -383,7 +401,19 @@
>> #define ICH_HCR_UIE (1 << 1)
>>
>> #define ICH_VMCR_CTLR_SHIFT 0
>> -#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)
>> +#define ICH_VMCR_CTLR_MASK (0x210 << ICH_VMCR_CTLR_SHIFT)
>
> Why are you dropping the four control bits? You're now only covering
> VEOIM and VCBPR. Worse, you don't even use that modified macro in this
> patch.
I modified this macro to hold only VEOIM and VCBPR fields.
For the rest of the fields VENG1 and VENG0, struct vmcr is added with
vmcr.grpen0 and vmcr.grpen1 separately.
>
>> +#define ICH_VMCR_CBPR_SHIFT 4
>> +#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
>> +#define ICH_VMCR_EOIM_SHIFT 9
>> +#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
>> +#define ICH_VMCR_ENG0_SHIFT 0
>> +#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
>> +#define ICH_VMCR_ENG1_SHIFT 1
>> +#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
>> +#define ICH_VMCR_ENG0_SHIFT 0
>> +#define ICH_VMCR_ENG0 (1 << ICH_VMCR_ENG0_SHIFT)
>> +#define ICH_VMCR_ENG1_SHIFT 1
>> +#define ICH_VMCR_ENG1 (1 << ICH_VMCR_ENG1_SHIFT)
>> #define ICH_VMCR_BPR1_SHIFT 18
>> #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
>> #define ICH_VMCR_BPR0_SHIFT 21
>
> And here you're covering for all the bits. So what is now the purpose
> of ICH_VMCR_CTLR_MASK now?
OK. Can be replaced with CBPR and VEOIM macros.
>
> In general, I'd like this kind of change to be split from the rest of
> the patch so that it can be reviewed independently by the irqchip
> maintainers (tglx, Jason and myself).
>
OK. I will send separate patch for changing this macro and adding
vmcr.grpen0 and vmcr.grpen1 fields to struct vmcr
[...]
>> --- /dev/null
>> +++ b/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
>> @@ -0,0 +1,261 @@
>> +#include <linux/irqchip/arm-gic-v3.h>
>> +#include <linux/kvm.h>
>> +#include <linux/kvm_host.h>
>> +#include <kvm/iodev.h>
>> +#include <kvm/arm_vgic.h>
>> +#include <asm/kvm_emulate.h>
>> +#include <asm/kvm_arm.h>
>> +#include <asm/kvm_mmu.h>
>> +
>> +#include "vgic.h"
>> +#include "vgic-mmio.h"
>> +#include "sys_regs.h"
>> +
>> +static bool access_gic_ctlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> + const struct sys_reg_desc *r)
>> +{
>> + struct vgic_vmcr vmcr;
>> + u64 val;
>> + u32 id_bits;
>> +
>> + vgic_get_vmcr(vcpu, &vmcr);
>> + if (p->is_write) {
>> + val = p->regval;
>> + vmcr.ctlr &= ~(ICH_VMCR_CBPR_MASK | ICH_VMCR_EOIM_MASK);
>> + vmcr.ctlr |= ((val & ICC_CTLR_EL1_CBPR_MASK) >>
>> + ICC_CTLR_EL1_CBPR_SHIFT) << ICH_VMCR_CBPR_SHIFT;
>> + vmcr.ctlr |= ((val & ICC_CTLR_EL1_EOImode_MASK) >>
>> + ICC_CTLR_EL1_EOImode_SHIFT) << ICH_VMCR_EOIM_SHIFT;
>> + vgic_set_vmcr(vcpu, &vmcr);
>
> What if userspace writes something that is incompatible with the
> current configuration? Wrong number of ID bits, or number of priorities?
IDand PRI bits of ICC_CTLR_EL1 are read only. Not updated
>
>> + } else {
>> + val = 0;
>> + /* ICC_CTLR_EL1.A3V and ICC_CTRL_EL1.SEIS are not set */
>> + val |= VGIC_PRI_BITS << ICC_CTLR_EL1_PRI_BITS_SHIFT;
>
> Shouldn't that come from the actual HW?
Yes, want to expose only VGIC supported value instead of HW.
>
>> +
>> + if (vgic_has_its(vcpu->kvm))
>> + id_bits = INTERRUPT_ID_BITS_ITS;
>> + else
>> + id_bits = INTERRUPT_ID_BITS_SPIS;
>> +
>> + if (id_bits >= 24)
>> + val |= (1 << ICC_CTLR_EL1_ID_BITS_SHIFT);
>> + else
>> + val |= (0 << ICC_CTLR_EL1_ID_BITS_SHIFT);
>> +
>> + val |= ((vmcr.ctlr & ICH_VMCR_CBPR_MASK) >>
>> + ICH_VMCR_CBPR_SHIFT) << ICC_CTLR_EL1_CBPR_SHIFT;
>> + val |= ((vmcr.ctlr & ICH_VMCR_EOIM_MASK) >>
>> + ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
>> +
>> + p->regval = val;
>> + }
>> +
>> + return true;
>> +}
>> +
>> +static bool access_gic_pmr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> + const struct sys_reg_desc *r)
>> +{
>> + struct vgic_vmcr vmcr;
>> +
>> + vgic_get_vmcr(vcpu, &vmcr);
>> + if (p->is_write) {
>> + vmcr.pmr = (p->regval << ICC_PMR_EL1_SHIFT) & ICC_PMR_EL1_MASK;
>
> I don't get this. You're trying to extract a field from a register, and
> yet you're starting by shifting it *up* before masking it. This only
> works because your shift is 0. In general, I believe this should read:
>
> val = (regval & MASK) >> SHIFT;
>
>> + vgic_set_vmcr(vcpu, &vmcr);
>> + } else {
>> + p->regval = (vmcr.pmr & ICC_PMR_EL1_MASK) >> ICC_PMR_EL1_SHIFT;
>
> and this the other way around.
>
>> + }
>> +
>> + return true;
>> +}
>> +
>> +static bool access_gic_bpr0(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> + const struct sys_reg_desc *r)
>> +{
>> + struct vgic_vmcr vmcr;
>> +
>> + vgic_get_vmcr(vcpu, &vmcr);
>> + if (p->is_write) {
>> + vmcr.bpr = (p->regval << ICC_BPR0_EL1_SHIFT) &
>> + ICC_BPR0_EL1_MASK;
>> + vgic_set_vmcr(vcpu, &vmcr);
>> + } else {
>> + p->regval = (vmcr.bpr & ICC_BPR0_EL1_MASK) >>
>> + ICC_BPR0_EL1_SHIFT;
>> + }
>
> Same problems (and I'll stop commenting on this issue).
>
>> +
>> + return true;
>> +}
>> +
>> +static bool access_gic_bpr1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> + const struct sys_reg_desc *r)
>> +{
>> + struct vgic_vmcr vmcr;
>> +
>> + vgic_get_vmcr(vcpu, &vmcr);
>> + if (p->is_write) {
>> + vmcr.abpr = (p->regval << ICC_BPR1_EL1_SHIFT) &
>> + ICC_BPR1_EL1_MASK;
>
> nit: I'd prefer it if the binary points were called bpr0 and bpr1
> instead of bpr and abpr.
>
>> + vgic_set_vmcr(vcpu, &vmcr);
>> + } else {
>> + p->regval = (vmcr.abpr & ICC_BPR1_EL1_MASK) >>
>> + ICC_BPR1_EL1_SHIFT;
>> + }
>
> Shouldn't this account for the ICC_CTLR_EL1.CBPR setting?
>
>> +
>> + return true;
>> +}
>> +
>> +static bool access_gic_grpen0(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> + const struct sys_reg_desc *r)
>> +{
>> + struct vgic_vmcr vmcr;
>> +
>> + vgic_get_vmcr(vcpu, &vmcr);
>> + if (p->is_write) {
>> + vmcr.grpen0 = (p->regval << ICC_IGRPEN0_EL1_SHIFT) &
>> + ICC_IGRPEN0_EL1_MASK;
>> + vgic_set_vmcr(vcpu, &vmcr);
>> + } else {
>> + p->regval = (vmcr.grpen0 & ICC_IGRPEN0_EL1_MASK) >>
>> + ICC_IGRPEN0_EL1_SHIFT;
>> + }
>> +
>> + return true;
>> +}
>> +
>> +static bool access_gic_grpen1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> + const struct sys_reg_desc *r)
>> +{
>> + struct vgic_vmcr vmcr;
>> +
>> + vgic_get_vmcr(vcpu, &vmcr);
>> + if (p->is_write) {
>> + vmcr.grpen1 = (p->regval << ICC_IGRPEN1_EL1_SHIFT) &
>> + ICC_IGRPEN1_EL1_MASK;
>> + vgic_set_vmcr(vcpu, &vmcr);
>> + } else {
>> + p->regval = (vmcr.grpen1 & ICC_IGRPEN1_EL1_MASK) >>
>> + ICC_IGRPEN1_EL1_SHIFT;
>> + }
>> +
>> + return true;
>> +}
>> +
>> +static bool access_gic_ap0r(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> + const struct sys_reg_desc *r)
>> +{
>> + struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
>> + u8 idx = r->Op2 & 3;
>> +
>> + if (p->is_write)
>> + vgicv3->vgic_ap0r[idx] = p->regval;
>
> What if some of the priority levels are not implemented? Restoring such
> an active priority will result in a VM that silently breaks.
You suggest to read vtr_to_nr_pri_bits() i.e ICH_VTR_EL2.PRIbits
and save/restore only required apr registers?
>>
>
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny.
^ permalink raw reply
* [GIT PULL 1/5] i.MX cleanup for 4.9
From: Shawn Guo @ 2016-09-12 9:02 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-cleanup-4.9
for you to fetch changes up to 3481bdce6516a1872f3ac0af43ba56d0e1ee3afa:
ARM: imx: (trivial) fix typo and grammar (2016-09-05 10:36:19 +0800)
----------------------------------------------------------------
i.MX cleanup for 4.9:
- Drop i.MX1 board files and make i.MX1 a DT only platform.
- Remove obsolete ENET initialization code for TX28 board, since FEC
driver handles those setup well now.
- A couple of cleanups on i.MX31 IOMUX headers to drop duplications
- A few other random and trivial cleanups
----------------------------------------------------------------
Alexander Kurz (2):
ARM: i.MX31 iomux: remove plain duplicates
ARM: i.MX31 iomux: remove duplicates with alternate name
Alexander Shiyan (4):
ARM: i.MX: Remove i.MX1 Armadeus APF9328 board support
ARM: i.MX: Remove i.MX1 Synertronixx SCB9328 board support
ARM: i.MX: Remove i.MX1 non-DT support
ARM: i.MX: Move SOC_IMX1 into 'Device tree only'
Fabian Frederick (1):
ARM: imx: remove platform-mxc_rnga
Javier Martinez Canillas (1):
ARM: imx: use IS_ENABLED() instead of checking for built-in or module
Lothar Wa?mann (1):
ARM: mxs: remove obsolete startup code for TX28
Martin Kaiser (1):
ARM: imx: (trivial) fix typo and grammar
Vladimir Murzin (1):
ARM: imx: no need to select SMP_ON_UP explicitly
arch/arm/configs/imx_v4_v5_defconfig | 3 +-
arch/arm/configs/multi_v4t_defconfig | 4 +-
arch/arm/mach-imx/Kconfig | 50 ++------
arch/arm/mach-imx/Makefile | 7 +-
arch/arm/mach-imx/common.h | 5 -
arch/arm/mach-imx/devices-imx1.h | 30 -----
arch/arm/mach-imx/devices/Makefile | 1 -
arch/arm/mach-imx/devices/devices-common.h | 12 --
arch/arm/mach-imx/devices/platform-imx-fb.c | 5 -
arch/arm/mach-imx/devices/platform-imx-i2c.c | 5 -
arch/arm/mach-imx/devices/platform-imx-uart.c | 37 ------
arch/arm/mach-imx/devices/platform-spi_imx.c | 9 --
arch/arm/mach-imx/hardware.h | 3 +-
arch/arm/mach-imx/iomux-mx1.h | 155 -----------------------
arch/arm/mach-imx/iomux-mx3.h | 34 -----
arch/arm/mach-imx/mach-apf9328.c | 148 ----------------------
arch/arm/mach-imx/{imx1-dt.c => mach-imx1.c} | 23 +++-
arch/arm/mach-imx/mach-kzm_arm11_01.c | 6 +-
arch/arm/mach-imx/mach-pcm037.c | 2 +-
arch/arm/mach-imx/mach-scb9328.c | 143 ---------------------
arch/arm/mach-imx/mm-imx1.c | 67 ----------
arch/arm/mach-imx/mx1.h | 172 --------------------------
arch/arm/mach-mxs/mach-mxs.c | 77 ------------
drivers/clk/imx/clk-imx1.c | 46 +------
24 files changed, 46 insertions(+), 998 deletions(-)
delete mode 100644 arch/arm/mach-imx/devices-imx1.h
delete mode 100644 arch/arm/mach-imx/iomux-mx1.h
delete mode 100644 arch/arm/mach-imx/mach-apf9328.c
rename arch/arm/mach-imx/{imx1-dt.c => mach-imx1.c} (63%)
delete mode 100644 arch/arm/mach-imx/mach-scb9328.c
delete mode 100644 arch/arm/mach-imx/mm-imx1.c
delete mode 100644 arch/arm/mach-imx/mx1.h
^ permalink raw reply
* [GIT PULL 2/5] i.MX soc updates for 4.9
From: Shawn Guo @ 2016-09-12 9:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473670948-4265-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-soc-4.9
for you to fetch changes up to d64299daf44c7ff57120a379ceb4907f19bbf041:
ARM: imx: build cpuidle-imx6sx.o for imx6ul (2016-09-08 22:12:10 +0800)
----------------------------------------------------------------
i.MX SoC updates for 4.9:
- Set INT_MEM_CLK_LPM bit to get proper WAIT mode support on i.MX6SX.
This is a workaround for i.MX6SX WAIT mode hardware issue.
- Enable cpuidle support with 3 low-power states (WFI, WAIT, POWER-OFF)
for i.MX6UL.
----------------------------------------------------------------
Anson Huang (3):
ARM: imx: rename imx6q_set_int_mem_clk_lpm() function
ARM: imx: enable WAIT mode hardware workaround for imx6sx
ARM: imx: add cpuidle support for i.mx6ul
Arnd Bergmann (1):
ARM: imx: build cpuidle-imx6sx.o for imx6ul
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/common.h | 2 +-
arch/arm/mach-imx/cpuidle-imx6q.c | 2 +-
arch/arm/mach-imx/cpuidle-imx6sx.c | 11 +++++++++++
arch/arm/mach-imx/mach-imx6ul.c | 3 +++
arch/arm/mach-imx/pm-imx6.c | 8 ++++----
6 files changed, 21 insertions(+), 6 deletions(-)
^ permalink raw reply
* [GIT PULL 3/5] i.MX device tree updates for 4.9
From: Shawn Guo @ 2016-09-12 9:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473670948-4265-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt-4.9
for you to fetch changes up to bb728d662bed0fe91b152550e640cb3f6caa972c:
ARM: dts: add gpio-ranges property to iMX GPIO controllers (2016-09-09 14:21:55 +0800)
----------------------------------------------------------------
i.MX device tree changes for 4.9:
- Add SoC support for i.MX7 Solo which is a reduced version of i.MX7
Dual.
- New board support: Gateworks Ventana i.MX6Q/DL GW553x, Inverse Path
i.MX53 USB armory, i.MX6Q/DL TS-4900 from Technologic Systems,
i.MX6UL GEA M6UL modules from Engicam, i.MX7 Solo Warp7 board.
- Add DMA and IPU CSI devices for i.MX53 SoC support.
- Refine i.MX7 Dual SoC DTS as a preparation of i.MX7 Solo support.
- Use of_graph dt nodes to describe the panel for vf610-colibri and
ls1021a-twr boards.
- Add gpio-ranges property to i.MX6 GPIO controllers, which will be
useful when GPIO driver is changed to request pad configuration as
GPIO function.
- Random device additions or small changes for various board support.
----------------------------------------------------------------
Andrej Rosano (2):
devicetree: Add vendor prefix for Inverse Path
ARM: dts: imx53: add support for USB armory board
Anson Huang (1):
ARM: dts: imx6ul iomuxc syscon is compatible to imx6q
Breno Lima (1):
ARM: dts: imx7s-warp: Add MPL3115 sensor support
Christoph Fritz (1):
ARM: dts: imx6sx: document SION necessity of ENET1_REF_CLK1
Fabien Lahoudere (2):
ARM: dts: imx53: Add DMA configuration for UART
ARM: dts: imx53: Add IPU nodes for csi
Fabio Estevam (8):
ARM: dts: imx7s-warp: Add initial support
ARM: dts: imx7s: Add SDMA node
ARM: dts: imx7s: Add SAI nodes
ARM: dts: imx7s-warp: Add audio support
ARM: dts: imx7s-warp: Add Wifi support
ARM: dts: imx7s-warp: Use WDOG_B pin reset
ARM: dts: imx6ul-pico-hobbit: Use WDOG_B pin reset
ARM: dts: imx7s-warp: Let the codec control MCLK pinctrl
Joshua Clayton (1):
ARM: dts: imx6q-evi: Use GPIO_6 for fec irq
Ken Lin (1):
ARM: dts: imx6q-bx50v3: configure unused pca953x pins
Lucile Quirion (2):
of: documentation: add bindings documentation for TS-4900
ARM: dts: TS-4900: add basic device tree
Marek Vasut (1):
ARM: dts: imx6sx: Add GPU bindings
Meng Yi (1):
ARM: dts: ls1021a: Add of_graph dt nodes to describe the panel
Michael Trimarchi (1):
ARM: dts: imx6ul-geam: Add Engicam IMX6UL GEA M6UL initial support
Sascha Hauer (1):
ARM: i.MX6 Phytec PFLA02: Add supplies for the SoC internal regulators
Stefan Agner (8):
ARM: dts: imx7d: move ARM platform peripherals inside soc node
ARM: dts: imx7d: fix GIC nodes interrupt and register specification
ARM: dts: imx7d: move CPU operating points to imx7d.dtsi
ARM: dts: imx7d: add clock-frequency to CPU nodes
ARM: dts: imx7-colibri: move SD-card to module level
ARM: dts: imx7-colibri: add basic supply regulators
ARM: dts: imx7-colibri: add Audio support
ARM: dts: vf610-colibri: use of_graph dt nodes to describe the panel
Tim Harvey (3):
ARM: dts: imx: ventana: Add ext watchdog reset
ARM: dts: imx: add Gateworks Ventana GW553x support
ARM: dts: imx: ventana: add RS485 txen gpio support
Uwe Kleine-K?nig (2):
ARM: dts: imx6qdl: don't configure reserved pad settings
ARM: dts: imx35: add iim module to imx35.dtsi
Vanessa Maegima (4):
ARM: dts: imx6ul-pico-hobbit: Add Wifi support
ARM: dts: imx7s-warp: Enable I2C2 device support
ARM: dts: imx7s-warp: Add User Button support
ARM: dts: imx7s-warp: Add Bluetooth support
Vladimir Zapolskiy (1):
ARM: dts: add gpio-ranges property to iMX GPIO controllers
.../devicetree/bindings/arm/technologic.txt | 6 +
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/arm/boot/dts/Makefile | 9 +-
arch/arm/boot/dts/imx35.dtsi | 7 +
arch/arm/boot/dts/imx50.dtsi | 10 +
arch/arm/boot/dts/imx53-usbarmory.dts | 224 ++++++++++
arch/arm/boot/dts/imx53.dtsi | 18 +
arch/arm/boot/dts/imx6dl-gw553x.dts | 55 +++
arch/arm/boot/dts/imx6dl-riotboard.dts | 22 +-
arch/arm/boot/dts/imx6dl-ts4900.dts | 49 +++
arch/arm/boot/dts/imx6dl.dtsi | 53 +++
arch/arm/boot/dts/imx6q-arm2.dts | 24 +-
arch/arm/boot/dts/imx6q-b450v3.dts | 16 +
arch/arm/boot/dts/imx6q-b650v3.dts | 9 +
arch/arm/boot/dts/imx6q-ba16.dtsi | 24 +-
arch/arm/boot/dts/imx6q-bx50v3.dtsi | 70 +++
arch/arm/boot/dts/imx6q-cm-fx6.dts | 24 +-
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 24 +-
arch/arm/boot/dts/imx6q-evi.dts | 28 +-
arch/arm/boot/dts/imx6q-gw5400-a.dts | 24 +-
arch/arm/boot/dts/imx6q-gw553x.dts | 55 +++
arch/arm/boot/dts/imx6q-marsboard.dts | 24 +-
arch/arm/boot/dts/imx6q-novena.dts | 12 +-
arch/arm/boot/dts/imx6q-sbc6x.dts | 24 +-
arch/arm/boot/dts/imx6q-tbs2910.dts | 24 +-
arch/arm/boot/dts/imx6q-ts4900.dts | 53 +++
arch/arm/boot/dts/imx6q.dtsi | 37 ++
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 36 +-
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 39 +-
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 39 +-
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 44 +-
arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 12 +
arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 12 +
arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 433 +++++++++++++++++++
arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 12 +-
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 36 +-
arch/arm/boot/dts/imx6qdl-rex.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-ts4900.dtsi | 481 +++++++++++++++++++++
arch/arm/boot/dts/imx6qdl-udoo.dtsi | 24 +-
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 24 +-
arch/arm/boot/dts/imx6sl.dtsi | 47 ++
arch/arm/boot/dts/imx6sx-pinfunc.h | 14 +
arch/arm/boot/dts/imx6sx.dtsi | 22 +
arch/arm/boot/dts/imx6ul-geam-kit.dts | 101 +++++
arch/arm/boot/dts/imx6ul-geam.dtsi | 361 ++++++++++++++++
arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 33 ++
arch/arm/boot/dts/imx6ul.dtsi | 9 +-
arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 4 -
arch/arm/boot/dts/imx7-colibri.dtsi | 61 ++-
arch/arm/boot/dts/imx7d.dtsi | 42 +-
arch/arm/boot/dts/imx7s-warp.dts | 446 +++++++++++++++++++
arch/arm/boot/dts/imx7s.dtsi | 371 +++++++++-------
arch/arm/boot/dts/ls1021a-twr.dts | 13 +-
arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 13 +-
62 files changed, 3365 insertions(+), 506 deletions(-)
create mode 100644 arch/arm/boot/dts/imx53-usbarmory.dts
create mode 100644 arch/arm/boot/dts/imx6dl-gw553x.dts
create mode 100644 arch/arm/boot/dts/imx6dl-ts4900.dts
create mode 100644 arch/arm/boot/dts/imx6q-gw553x.dts
create mode 100644 arch/arm/boot/dts/imx6q-ts4900.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-gw553x.dtsi
create mode 100644 arch/arm/boot/dts/imx6qdl-ts4900.dtsi
create mode 100644 arch/arm/boot/dts/imx6ul-geam-kit.dts
create mode 100644 arch/arm/boot/dts/imx6ul-geam.dtsi
create mode 100644 arch/arm/boot/dts/imx7s-warp.dts
^ permalink raw reply
* [GIT PULL 4/5] Freescale arm64 device tree updates for 4.9
From: Shawn Guo @ 2016-09-12 9:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473670948-4265-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt64-4.9
for you to fetch changes up to e5f51a623a5d6dd24779e5136cf923611b032453:
arm64: dts: ls2080a: Add 'dma-coherent' for ls2080a PCI nodes (2016-09-09 14:04:21 +0800)
----------------------------------------------------------------
i.MX arm64 device tree changes for 4.9:
- Add property dma-coherent for ls2080a PCI device to save software
cache maintenance.
- Update serial aliases and use stdout-path to sepecify console for
ls2080a and ls1043a boards.
- Add DDR memory controller device node for ls2080a and ls1043a SoCs.
----------------------------------------------------------------
Liu Gang (1):
arm64: dts: ls2080a: Add 'dma-coherent' for ls2080a PCI nodes
Stuart Yoder (2):
arm64: dts: updates serial aliases for ls1043a rdb and qds boards
arm64: dts: add stdout-path to chosen node for ls2080a/ls1043a boards
York Sun (1):
arm64: dts: Add DDR memory controller for Layerscape SoCs
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 14 ++++++++------
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 8 ++++++++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 7 +++++++
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 4 ++++
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 18 ++++++++++++++++++
6 files changed, 48 insertions(+), 6 deletions(-)
^ permalink raw reply
* [GIT PULL 5/5] i.MX defconfig updates for 4.9
From: Shawn Guo @ 2016-09-12 9:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473670948-4265-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-defconfig-4.9
for you to fetch changes up to b2ab6f6cc3b1da42acf30e03ce2a4dad3f627272:
ARM: imx_v6_v7_defconfig: Select the wm8960 codec driver (2016-08-29 22:17:26 +0800)
----------------------------------------------------------------
i.MX defconfig updates for 4.9:
- Enable i.MX6 SATA and cpufreq driver support in multi_v7_defconfig.
- Enable MPL3115, Etnaviv GPU, WM8960 Codec driver and more USB
functions support in imx_v6_v7_defconfig.
----------------------------------------------------------------
Breno Lima (1):
ARM: imx_v6_v7_defconfig: Add CONFIG_MPL3115
Fabio Estevam (2):
ARM: imx_v6_v7_defconfig: Enable GPU support
ARM: imx_v6_v7_defconfig: Select the wm8960 codec driver
Peter Chen (1):
ARM: imx_v6_v7_defconfig: enable more USB configurations
Tuomas Tynkkynen (2):
ARM: multi_v7_defconfig: Enable AHCI_IMX
ARM: multi_v7_defconfig: Enable ARM_IMX6Q_CPUFREQ
arch/arm/configs/imx_v6_v7_defconfig | 17 +++++++++++------
arch/arm/configs/multi_v7_defconfig | 3 +++
2 files changed, 14 insertions(+), 6 deletions(-)
^ permalink raw reply
* [PATCH v2] gpio/gpiolib: Forbid irqchip default trigger if probed over DT
From: Linus Walleij @ 2016-09-12 9:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57D19C2C.2050906@arm.com>
On Thu, Sep 8, 2016 at 7:13 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On 07/09/16 23:18, Linus Walleij wrote:
>> On Wed, Sep 7, 2016 at 10:12 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>
>>> Using a default trigger is a bad idea if using DT to configure
>>> interrupts, as the device's interrupt specifier will always contain
>>> the trigger configuration.
>>>
>>> Let's warn about that particular situation, and revert to not
>>> having a default. Hopefully, the couple of drivers still using
>>> this feature will quickly be fixed.
>>>
>>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>>> ---
>>> Send the tested patch this time around...
>>
>> I got it the first time, don't worry :D
>
> Errrr, the first one didn't even compile (I'm such a moron sometimes).
> Please apply this one instead, which has actually been compile-tested.
>
> Sorry for the noise.
Sending premature patches is human.
Backed the buggy one out and applied this instead!
Yours,
Linus Walleij
^ permalink raw reply
* [PULL] clockevents for 4.9
From: Daniel Lezcano @ 2016-09-12 9:10 UTC (permalink / raw)
To: linux-arm-kernel
Hi Thomas, Ingo,
This pull request for 4.9 contains a few changes:
- Cleanup the atmel-pit timer (Alexander Belloni)
- Add the Aspeed support (Joel Stanley)
- Replaced setup_irq/request_irq and panic/pr_err on moxart (Daniel
Lezcano)
- Add the Ox820 compatible string for oxnas (Neil Armstrong)
Thanks !
-- Daniel
The following changes since commit 950d8381d915ee293a5b57f91e59dd8115684af1:
Merge branch 'linus' into timers/core, to refresh the branch
(2016-09-08 14:05:16 +0200)
are available in the git repository at:
http://git.linaro.org/people/daniel.lezcano/linux.git clockevents/4.9
for you to fetch changes up to 2ea3401e2a84eed3f5f55b2075706f88df160d85:
clocksource/drivers/oxnas: Add OX820 compatible (2016-09-12 07:28:46
+0200)
----------------------------------------------------------------
Alexandre Belloni (3):
clocksource/drivers/timer-atmel-pit: Drop at91sam926x_pit_common_init
clocksource/drivers/timer-atmel-pit: Remove uselesss WARN_ON_ONCE
clocksource/drivers/timer-atmel-pit: Simplify IRQ handler
Daniel Lezcano (2):
clocksource/drivers/moxart: Replace setup_irq by request_irq
clocksource/drivers/moxart: Replace panic by pr_err
Joel Stanley (3):
clocksource/drivers/moxart: Refactor enable/disable
clocksource/drivers/moxart: Use struct to hold state
clocksource/drivers/moxart: Add Aspeed support
Neil Armstrong (1):
clocksource/drivers/oxnas: Add OX820 compatible
Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt | 4 +++-
Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt | 2 +-
drivers/clocksource/moxart_timer.c | 193
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------------------
drivers/clocksource/timer-atmel-pit.c | 96
+++++++++++++++++++++++++++++++++++++-----------------------------------------------------------
drivers/clocksource/timer-oxnas-rps.c | 2 ++
5 files changed, 172 insertions(+), 125 deletions(-)
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH 22/20] iommu/arm-smmu: Fall back to global bypass
From: Will Deacon @ 2016-09-12 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9c467662ca0fb562cff6d5c9443d77eacb257060.1473443407.git.robin.murphy@arm.com>
On Fri, Sep 09, 2016 at 07:17:47PM +0100, Robin Murphy wrote:
> Unlike SMMUv2, SMMUv3 has no easy way to bypass unknown stream IDs,
> other than allocating and filling in the entire stream table with bypass
> entries, which for some configurations would waste *gigabytes* of RAM.
> Otherwise, all transactions on unknown stream IDs will simply be aborted
> with a C_BAD_STREAMID event.
>
> Rather than render the system unusable in the case of an invalid DT,
> avoid enabling the SMMU altogether such that everything bypasses
> (though letting the explicit disable_bypass option take precedence).
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
> drivers/iommu/arm-smmu-v3.c | 28 +++++++++++++++++++++++-----
> 1 file changed, 23 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index be293b5aa896..859b80c83946 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -126,6 +126,9 @@
> #define CR2_RECINVSID (1 << 1)
> #define CR2_E2H (1 << 0)
>
> +#define ARM_SMMU_GBPA 0x44
> +#define GBPA_ABORT (1 << 20)
> +
> #define ARM_SMMU_IRQ_CTRL 0x50
> #define IRQ_CTRL_EVTQ_IRQEN (1 << 2)
> #define IRQ_CTRL_PRIQ_IRQEN (1 << 1)
> @@ -2242,7 +2245,7 @@ static int arm_smmu_device_disable(struct arm_smmu_device *smmu)
> return ret;
> }
>
> -static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
> +static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
> {
> int ret;
> u32 reg, enables;
> @@ -2343,8 +2346,14 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
> return ret;
> }
>
> - /* Enable the SMMU interface */
> - enables |= CR0_SMMUEN;
> +
> + /* Enable the SMMU interface, or ensure bypass */
> + if (!bypass || disable_bypass) {
> + enables |= CR0_SMMUEN;
> + } else {
> + reg = readl_relaxed(smmu->base + ARM_SMMU_GBPA);
> + writel_relaxed(reg & ~GBPA_ABORT, smmu->base + ARM_SMMU_GBPA);
> + }
I think this invokes the CONSTRAINED UNPREDICTABLE monster, because the
GBPA register has some a special update procedure involving the 'update'
bit (bit 31).
You might be able to reuse arm_smmu_write_reg_sync to poll for completion
with offset 0. I'm happy to assume that the update bit is initially clear.
Will
^ permalink raw reply
* [PATCH v4 4/5] arm/arm64: vgic-new: Implement VGICv3 CPU interface access
From: Marc Zyngier @ 2016-09-12 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALicx6tG6jhNVs3DKfKKpyc8VMWjV-UWWtW1PuJSPpHC3g=wVg@mail.gmail.com>
On 12/09/16 10:00, Vijay Kilari wrote:
> ()
>
> On Sun, Sep 11, 2016 at 1:26 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On Sat, 10 Sep 2016 17:52:17 +0530
>> vijay.kilari at gmail.com wrote:
>>
>>> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>>>
>>> VGICv3 CPU interface registers are accessed using
>>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
>>> as 64-bit. The cpu MPIDR value is passed along with register id.
>>> is used to identify the cpu for registers access.
>>>
>>> The version of VGIC v3 specification is define here
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
>>>
>>> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
>>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>>> ---
>>> arch/arm64/include/uapi/asm/kvm.h | 3 +
>>> arch/arm64/kvm/Makefile | 1 +
>>> include/linux/irqchip/arm-gic-v3.h | 32 ++++-
>>> virt/kvm/arm/vgic/vgic-kvm-device.c | 27 ++++
>>> virt/kvm/arm/vgic/vgic-mmio-v2.c | 16 ---
>>> virt/kvm/arm/vgic/vgic-mmio-v3.c | 18 +++
>>> virt/kvm/arm/vgic/vgic-mmio.c | 16 +++
>>> virt/kvm/arm/vgic/vgic-sys-reg-v3.c | 261 ++++++++++++++++++++++++++++++++++++
>>> virt/kvm/arm/vgic/vgic-v3.c | 4 +
>>> virt/kvm/arm/vgic/vgic.h | 15 +++
>>> 10 files changed, 376 insertions(+), 17 deletions(-)
>>>
>>> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
>>> index 56dc08d..91c7137 100644
>>> --- a/arch/arm64/include/uapi/asm/kvm.h
>>> +++ b/arch/arm64/include/uapi/asm/kvm.h
>>> @@ -206,9 +206,12 @@ struct kvm_arch_memory_slot {
>>> (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
>>> #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
>>> #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
>>> +#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
>>> #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
>>> #define KVM_DEV_ARM_VGIC_GRP_CTRL 4
>>> #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
>>> +#define KVM_DEV_ARM_VGIC_CPU_SYSREGS 6
>>> +
>>> #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
>>>
>>> /* Device Control API on vcpu fd */
>>> diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
>>> index d50a82a..1a14e29 100644
>>> --- a/arch/arm64/kvm/Makefile
>>> +++ b/arch/arm64/kvm/Makefile
>>> @@ -32,5 +32,6 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-mmio-v3.o
>>> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-kvm-device.o
>>> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-its.o
>>> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/irqchip.o
>>> +kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-sys-reg-v3.o
>>> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
>>> kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o
>>> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
>>> index 99ac022..22ec183 100644
>>> --- a/include/linux/irqchip/arm-gic-v3.h
>>> +++ b/include/linux/irqchip/arm-gic-v3.h
>>> @@ -354,6 +354,24 @@
>>> */
>>> #define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)
>>> #define ICC_CTLR_EL1_EOImode_drop (1U << 1)
>>> +#define ICC_CTLR_EL1_CBPR_SHIFT (0)
>>> +#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
>>> +#define ICC_CTLR_EL1_EOImode_SHIFT (1)
>>
>> Since you're adding this, please rewrite the two existing EOImode
>> macros to use this new define.
>>
>>> +#define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
>>> +#define ICC_CTLR_EL1_PRI_BITS_SHIFT (8)
>>> +#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
>>> +#define ICC_CTLR_EL1_ID_BITS_SHIFT (11)
>>> +#define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
>>> +#define ICC_PMR_EL1_SHIFT (0)
>>> +#define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
>>> +#define ICC_BPR0_EL1_SHIFT (0)
>>> +#define ICC_BPR0_EL1_MASK (0x7 << ICC_PMR_EL1_SHIFT)
>>> +#define ICC_BPR1_EL1_SHIFT (0)
>>> +#define ICC_BPR1_EL1_MASK (0x7 << ICC_PMR_EL1_SHIFT)
>>> +#define ICC_IGRPEN0_EL1_SHIFT (0)
>>> +#define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
>>> +#define ICC_IGRPEN1_EL1_SHIFT (0)
>>> +#define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
>>> #define ICC_SRE_EL1_SRE (1U << 0)
>>>
>>> /*
>>> @@ -383,7 +401,19 @@
>>> #define ICH_HCR_UIE (1 << 1)
>>>
>>> #define ICH_VMCR_CTLR_SHIFT 0
>>> -#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)
>>> +#define ICH_VMCR_CTLR_MASK (0x210 << ICH_VMCR_CTLR_SHIFT)
>>
>> Why are you dropping the four control bits? You're now only covering
>> VEOIM and VCBPR. Worse, you don't even use that modified macro in this
>> patch.
>
> I modified this macro to hold only VEOIM and VCBPR fields.
> For the rest of the fields VENG1 and VENG0, struct vmcr is added with
> vmcr.grpen0 and vmcr.grpen1 separately.
>
>>
>>> +#define ICH_VMCR_CBPR_SHIFT 4
>>> +#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
>>> +#define ICH_VMCR_EOIM_SHIFT 9
>>> +#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
>>> +#define ICH_VMCR_ENG0_SHIFT 0
>>> +#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
>>> +#define ICH_VMCR_ENG1_SHIFT 1
>>> +#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
>>> +#define ICH_VMCR_ENG0_SHIFT 0
>>> +#define ICH_VMCR_ENG0 (1 << ICH_VMCR_ENG0_SHIFT)
>>> +#define ICH_VMCR_ENG1_SHIFT 1
>>> +#define ICH_VMCR_ENG1 (1 << ICH_VMCR_ENG1_SHIFT)
>>> #define ICH_VMCR_BPR1_SHIFT 18
>>> #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
>>> #define ICH_VMCR_BPR0_SHIFT 21
>>
>> And here you're covering for all the bits. So what is now the purpose
>> of ICH_VMCR_CTLR_MASK now?
>
> OK. Can be replaced with CBPR and VEOIM macros.
>
>>
>> In general, I'd like this kind of change to be split from the rest of
>> the patch so that it can be reviewed independently by the irqchip
>> maintainers (tglx, Jason and myself).
>>
> OK. I will send separate patch for changing this macro and adding
> vmcr.grpen0 and vmcr.grpen1 fields to struct vmcr
>
> [...]
>>> --- /dev/null
>>> +++ b/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
>>> @@ -0,0 +1,261 @@
>>> +#include <linux/irqchip/arm-gic-v3.h>
>>> +#include <linux/kvm.h>
>>> +#include <linux/kvm_host.h>
>>> +#include <kvm/iodev.h>
>>> +#include <kvm/arm_vgic.h>
>>> +#include <asm/kvm_emulate.h>
>>> +#include <asm/kvm_arm.h>
>>> +#include <asm/kvm_mmu.h>
>>> +
>>> +#include "vgic.h"
>>> +#include "vgic-mmio.h"
>>> +#include "sys_regs.h"
>>> +
>>> +static bool access_gic_ctlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>>> + const struct sys_reg_desc *r)
>>> +{
>>> + struct vgic_vmcr vmcr;
>>> + u64 val;
>>> + u32 id_bits;
>>> +
>>> + vgic_get_vmcr(vcpu, &vmcr);
>>> + if (p->is_write) {
>>> + val = p->regval;
>>> + vmcr.ctlr &= ~(ICH_VMCR_CBPR_MASK | ICH_VMCR_EOIM_MASK);
>>> + vmcr.ctlr |= ((val & ICC_CTLR_EL1_CBPR_MASK) >>
>>> + ICC_CTLR_EL1_CBPR_SHIFT) << ICH_VMCR_CBPR_SHIFT;
>>> + vmcr.ctlr |= ((val & ICC_CTLR_EL1_EOImode_MASK) >>
>>> + ICC_CTLR_EL1_EOImode_SHIFT) << ICH_VMCR_EOIM_SHIFT;
>>> + vgic_set_vmcr(vcpu, &vmcr);
>>
>> What if userspace writes something that is incompatible with the
>> current configuration? Wrong number of ID bits, or number of priorities?
>
> IDand PRI bits of ICC_CTLR_EL1 are read only. Not updated
Read again. You're migrating from a machine that implements 24 bits of
INTD to one that has 16 bits. Are you going to silently accept a bogus
value and leave most of the interrupts as undeliverable?
>
>>
>>> + } else {
>>> + val = 0;
>>> + /* ICC_CTLR_EL1.A3V and ICC_CTRL_EL1.SEIS are not set */
>>> + val |= VGIC_PRI_BITS << ICC_CTLR_EL1_PRI_BITS_SHIFT;
>>
>> Shouldn't that come from the actual HW?
>
> Yes, want to expose only VGIC supported value instead of HW.
What does it mean? If the HW doesn't support that range of priority,
nothing will work anyway.
>
>>
>>> +
>>> + if (vgic_has_its(vcpu->kvm))
>>> + id_bits = INTERRUPT_ID_BITS_ITS;
>>> + else
>>> + id_bits = INTERRUPT_ID_BITS_SPIS;
>>> +
>>> + if (id_bits >= 24)
>>> + val |= (1 << ICC_CTLR_EL1_ID_BITS_SHIFT);
>>> + else
>>> + val |= (0 << ICC_CTLR_EL1_ID_BITS_SHIFT);
>>> +
>>> + val |= ((vmcr.ctlr & ICH_VMCR_CBPR_MASK) >>
>>> + ICH_VMCR_CBPR_SHIFT) << ICC_CTLR_EL1_CBPR_SHIFT;
>>> + val |= ((vmcr.ctlr & ICH_VMCR_EOIM_MASK) >>
>>> + ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
>>> +
>>> + p->regval = val;
>>> + }
>>> +
>>> + return true;
>>> +}
>>> +
>>> +static bool access_gic_pmr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>>> + const struct sys_reg_desc *r)
>>> +{
>>> + struct vgic_vmcr vmcr;
>>> +
>>> + vgic_get_vmcr(vcpu, &vmcr);
>>> + if (p->is_write) {
>>> + vmcr.pmr = (p->regval << ICC_PMR_EL1_SHIFT) & ICC_PMR_EL1_MASK;
>>
>> I don't get this. You're trying to extract a field from a register, and
>> yet you're starting by shifting it *up* before masking it. This only
>> works because your shift is 0. In general, I believe this should read:
>>
>> val = (regval & MASK) >> SHIFT;
>>
>>> + vgic_set_vmcr(vcpu, &vmcr);
>>> + } else {
>>> + p->regval = (vmcr.pmr & ICC_PMR_EL1_MASK) >> ICC_PMR_EL1_SHIFT;
>>
>> and this the other way around.
>>
>>> + }
>>> +
>>> + return true;
>>> +}
>>> +
>>> +static bool access_gic_bpr0(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>>> + const struct sys_reg_desc *r)
>>> +{
>>> + struct vgic_vmcr vmcr;
>>> +
>>> + vgic_get_vmcr(vcpu, &vmcr);
>>> + if (p->is_write) {
>>> + vmcr.bpr = (p->regval << ICC_BPR0_EL1_SHIFT) &
>>> + ICC_BPR0_EL1_MASK;
>>> + vgic_set_vmcr(vcpu, &vmcr);
>>> + } else {
>>> + p->regval = (vmcr.bpr & ICC_BPR0_EL1_MASK) >>
>>> + ICC_BPR0_EL1_SHIFT;
>>> + }
>>
>> Same problems (and I'll stop commenting on this issue).
>>
>>> +
>>> + return true;
>>> +}
>>> +
>>> +static bool access_gic_bpr1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>>> + const struct sys_reg_desc *r)
>>> +{
>>> + struct vgic_vmcr vmcr;
>>> +
>>> + vgic_get_vmcr(vcpu, &vmcr);
>>> + if (p->is_write) {
>>> + vmcr.abpr = (p->regval << ICC_BPR1_EL1_SHIFT) &
>>> + ICC_BPR1_EL1_MASK;
>>
>> nit: I'd prefer it if the binary points were called bpr0 and bpr1
>> instead of bpr and abpr.
>>
>>> + vgic_set_vmcr(vcpu, &vmcr);
>>> + } else {
>>> + p->regval = (vmcr.abpr & ICC_BPR1_EL1_MASK) >>
>>> + ICC_BPR1_EL1_SHIFT;
>>> + }
>>
>> Shouldn't this account for the ICC_CTLR_EL1.CBPR setting?
>>
>>> +
>>> + return true;
>>> +}
>>> +
>>> +static bool access_gic_grpen0(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>>> + const struct sys_reg_desc *r)
>>> +{
>>> + struct vgic_vmcr vmcr;
>>> +
>>> + vgic_get_vmcr(vcpu, &vmcr);
>>> + if (p->is_write) {
>>> + vmcr.grpen0 = (p->regval << ICC_IGRPEN0_EL1_SHIFT) &
>>> + ICC_IGRPEN0_EL1_MASK;
>>> + vgic_set_vmcr(vcpu, &vmcr);
>>> + } else {
>>> + p->regval = (vmcr.grpen0 & ICC_IGRPEN0_EL1_MASK) >>
>>> + ICC_IGRPEN0_EL1_SHIFT;
>>> + }
>>> +
>>> + return true;
>>> +}
>>> +
>>> +static bool access_gic_grpen1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>>> + const struct sys_reg_desc *r)
>>> +{
>>> + struct vgic_vmcr vmcr;
>>> +
>>> + vgic_get_vmcr(vcpu, &vmcr);
>>> + if (p->is_write) {
>>> + vmcr.grpen1 = (p->regval << ICC_IGRPEN1_EL1_SHIFT) &
>>> + ICC_IGRPEN1_EL1_MASK;
>>> + vgic_set_vmcr(vcpu, &vmcr);
>>> + } else {
>>> + p->regval = (vmcr.grpen1 & ICC_IGRPEN1_EL1_MASK) >>
>>> + ICC_IGRPEN1_EL1_SHIFT;
>>> + }
>>> +
>>> + return true;
>>> +}
>>> +
>>> +static bool access_gic_ap0r(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>>> + const struct sys_reg_desc *r)
>>> +{
>>> + struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
>>> + u8 idx = r->Op2 & 3;
>>> +
>>> + if (p->is_write)
>>> + vgicv3->vgic_ap0r[idx] = p->regval;
>>
>> What if some of the priority levels are not implemented? Restoring such
>> an active priority will result in a VM that silently breaks.
>
> You suggest to read vtr_to_nr_pri_bits() i.e ICH_VTR_EL2.PRIbits
> and save/restore only required apr registers?
I strongly suggest that if you restore active priorities that are
outside of what the HW can represent, then the only possible value is zero.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v15.1 3/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399
From: Mark Brown @ 2016-09-12 9:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473480966-21572-1-git-send-email-zyw@rock-chips.com>
On Fri, Sep 09, 2016 at 09:16:06PM -0700, Chris Zhong wrote:
> Add support for cdn DP controller which is embedded in the rk3399
> SoCs. The DP is compliant with DisplayPort Specification,
Please don't new patches in reply to old serieses, especially not
individual patches in the middle of the series - it just makes
everything more confusing. It becomes difficult to tell what the
version of the series that's actually expected is. Please send the
whole series.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 473 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160912/5dbc680e/attachment.sig>
^ permalink raw reply
* [PATCH 9/9] clocksource/drivers/oxnas: Add OX820 compatible
From: Daniel Lezcano @ 2016-09-12 9:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473671747-9400-1-git-send-email-daniel.lezcano@linaro.org>
From: Neil Armstrong <narmstrong@baylibre.com>
In order to support the Oxford Semiconductor OX820 SoC, add new
compatible string to rps timer driver.
Also add new string in the dt-bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt | 2 +-
drivers/clocksource/timer-oxnas-rps.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt b/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt
index 3ca89cd..d191612 100644
--- a/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt
+++ b/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt
@@ -2,7 +2,7 @@ Oxford Semiconductor OXNAS SoCs Family RPS Timer
================================================
Required properties:
-- compatible: Should be "oxsemi,ox810se-rps-timer"
+- compatible: Should be "oxsemi,ox810se-rps-timer" or "oxsemi,ox820-rps-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The interrupts of the two timers
- clocks : The phandle of the timer clock source
diff --git a/drivers/clocksource/timer-oxnas-rps.c b/drivers/clocksource/timer-oxnas-rps.c
index bd887e2..d630bf4 100644
--- a/drivers/clocksource/timer-oxnas-rps.c
+++ b/drivers/clocksource/timer-oxnas-rps.c
@@ -295,3 +295,5 @@ err_alloc:
CLOCKSOURCE_OF_DECLARE(ox810se_rps,
"oxsemi,ox810se-rps-timer", oxnas_rps_timer_init);
+CLOCKSOURCE_OF_DECLARE(ox820_rps,
+ "oxsemi,ox820se-rps-timer", oxnas_rps_timer_init);
--
2.7.4
^ permalink raw reply related
* [PATCH 4.5/20] Docs: dt: document ARM SMMUv3 generic binding usage
From: Will Deacon @ 2016-09-12 9:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6067fc2b12b3bc681687753eedd941c8244c22fa.1473443407.git.robin.murphy@arm.com>
On Fri, Sep 09, 2016 at 07:17:48PM +0100, Robin Murphy wrote:
> Now that we've ratified SMMUv3's use of the generic binding, document it.
>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
> index 7b94c88cf2ee..69a694f70bea 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
> @@ -27,6 +27,12 @@ the PCIe specification.
> * "cmdq-sync" - CMD_SYNC complete
> * "gerror" - Global Error activated
>
> +- #iommu-cells : See the generic IOMMU binding described in
> + devicetree/bindings/iommu/iommu.txt
That file has a weird "Notes:" section describing the application of
"iommus" to a PCI host bridge. We should probably rip that out, because
it seems to be going directly against the approach we've ended up taking.
In fact, replacing that with a cross reference to
devicetree/bindings/pci/pci-iommu.txt
would make much more sense to me.
> + for details. For SMMUv3, must be 1, with each cell
> + describing a single stream ID. All possible stream
> + ID which a device may emit must be described.
IDs
Will
^ permalink raw reply
* [PATCH v3 2/8] arm64: KVM: Move GIC accessors to arch_gicv3.h
From: Vladimir Murzin @ 2016-09-12 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57D2E426.6000001@arm.com>
On 09/09/16 17:32, Marc Zyngier wrote:
> On 08/09/16 17:06, Vladimir Murzin wrote:
>> Since we are going to share vgic-v3 save/restore code with ARM keep
>> arch specific accessors separately.
>>
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>> Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>
Thanks!
Vladimir
> M.
>
^ permalink raw reply
* [PATCH 21/20] drm/exynos: Fix iommu_dma_init_domain prototype change
From: Will Deacon @ 2016-09-12 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <47cdafe035630f29aa1e8ff121c5a5306a2f1eb2.1473444220.git.robin.murphy@arm.com>
On Fri, Sep 09, 2016 at 07:17:46PM +0100, Robin Murphy wrote:
> When adding an extra argument to a function, one really should try a bit
> harder to catch *all* the callers...
>
> CC: Marek Szyprowski <m.szyprowski@samsung.com>
> CC: Inki Dae <inki.dae@samsung.com>
> CC: David Airlie <airlied@linux.ie>
> CC: dri-devel at lists.freedesktop.org
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>
> ---
>
> Ideally, this should be squashed into "iommu/dma: Avoid PCI host bridge
> windows" to avoid potential bisection breakage. Sorry!
I'll squash this in when I push out the final series..
Will
^ permalink raw reply
* [PATCH v5 2/3] mfd: add support for Allwinner SoCs ADC
From: Lee Jones @ 2016-09-12 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473344917-1524-3-git-send-email-quentin.schulz@free-electrons.com>
On Thu, 08 Sep 2016, Quentin Schulz wrote:
> The Allwinner SoCs all have an ADC that can also act as a touchscreen
> controller and a thermal sensor. For now, only the ADC and the thermal
> sensor drivers are probed by the MFD, the touchscreen controller support
> will be added later.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> ---
>
> v5:
> - correct mail address,
>
> v4:
> - rename files and variables from sunxi* to sun4i*,
> - rename defines from SUNXI_* to SUN4I_* or SUN6I_*,
> - remove TP in defines name,
> - rename SUNXI_IRQ_* to SUN4I_GPADC_IRQ_* for consistency,
> - use devm functions for regmap_add_irq_chip and mfd_add_devices,
> - remove remove functions (now empty thanks to devm functions),
>
> v3:
> - use defines in regmap_irq instead of hard coded BITs,
> - use of_device_id data field to chose which MFD cells to add considering
> the compatible responsible of the MFD probe,
> - remove useless initializations,
> - disable all interrupts before adding them to regmap_irqchip,
> - add goto error label in probe,
> - correct wrapping in header license,
> - move defines from IIO driver to header,
> - use GENMASK to limit the size of the variable passed to a macro,
> - prefix register BIT defines with the name of the register,
> - reorder defines,
>
> v2:
> - add license headers,
> - reorder alphabetically includes,
> - add SUNXI_GPADC_ prefixes for defines,
>
> drivers/mfd/Kconfig | 15 ++++
> drivers/mfd/Makefile | 2 +
> drivers/mfd/sun4i-gpadc-mfd.c | 174 ++++++++++++++++++++++++++++++++++++
> include/linux/mfd/sun4i-gpadc-mfd.h | 94 +++++++++++++++++++
> 4 files changed, 285 insertions(+)
> create mode 100644 drivers/mfd/sun4i-gpadc-mfd.c
> create mode 100644 include/linux/mfd/sun4i-gpadc-mfd.h
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 1bcf601..95b3c3e 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -29,6 +29,21 @@ config MFD_ACT8945A
> linear regulators, along with a complete ActivePath battery
> charger.
>
> +config MFD_SUN4I_GPADC
> + tristate "Allwinner sunxi platforms' GPADC MFD driver"
> + select MFD_CORE
> + select REGMAP_MMIO
> + depends on ARCH_SUNXI || COMPILE_TEST
> + help
> + Select this to get support for Allwinner SoCs (A10, A13 and A31) ADC.
> + This driver will only map the hardware interrupt and registers, you
> + have to select individual drivers based on this MFD to be able to use
> + the ADC or the thermal sensor. This will try to probe the ADC driver
> + sun4i-gpadc-iio and the hwmon driver iio_hwmon.
> +
> + To compile this driver as a module, choose M here: the module will be
> + called sun4i-gpadc-mfd.
Drop the -mfd.
> config MFD_AS3711
> bool "AMS AS3711"
> select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 42a66e1..3b964d7 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -205,3 +205,5 @@ intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
> intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o
> obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
> +
> +obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc-mfd.o
> diff --git a/drivers/mfd/sun4i-gpadc-mfd.c b/drivers/mfd/sun4i-gpadc-mfd.c
> new file mode 100644
> index 0000000..b499545
> --- /dev/null
> +++ b/drivers/mfd/sun4i-gpadc-mfd.c
Drop the -mfd.
> @@ -0,0 +1,174 @@
> +/* ADC MFD core driver for sunxi platforms
> + *
> + * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/core.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/regmap.h>
> +
> +#include <linux/mfd/sun4i-gpadc-mfd.h>
> +
> +static struct resource adc_resources[] = {
> + {
> + .name = "FIFO_DATA_PENDING",
> + .start = SUN4I_GPADC_IRQ_FIFO_DATA,
> + .end = SUN4I_GPADC_IRQ_FIFO_DATA,
> + .flags = IORESOURCE_IRQ,
> + }, {
> + .name = "TEMP_DATA_PENDING",
> + .start = SUN4I_GPADC_IRQ_TEMP_DATA,
> + .end = SUN4I_GPADC_IRQ_TEMP_DATA,
> + .flags = IORESOURCE_IRQ,
> + },
> +};
Use the RES_IRQ_* defines.
> +static const struct regmap_irq sun4i_gpadc_mfd_regmap_irq[] = {
> + REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_FIFO_DATA, 0,
> + SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN),
> + REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_TEMP_DATA, 0,
> + SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN),
> +};
> +
> +static const struct regmap_irq_chip sun4i_gpadc_mfd_regmap_irq_chip = {
> + .name = "sun4i_gpadc_mfd_irq_chip",
> + .status_base = SUN4I_GPADC_INT_FIFOS,
> + .ack_base = SUN4I_GPADC_INT_FIFOS,
> + .mask_base = SUN4I_GPADC_INT_FIFOC,
> + .init_ack_masked = true,
> + .mask_invert = true,
> + .irqs = sun4i_gpadc_mfd_regmap_irq,
> + .num_irqs = ARRAY_SIZE(sun4i_gpadc_mfd_regmap_irq),
> + .num_regs = 1,
> +};
> +
> +static struct mfd_cell sun4i_gpadc_mfd_cells[] = {
> + {
> + .name = "sun4i-a10-gpadc-iio",
> + .resources = adc_resources,
> + .num_resources = ARRAY_SIZE(adc_resources),
> + }, {
> + .name = "iio_hwmon",
> + }
Single line please
{ .name = "iio_hwmon" }
> +};
> +
> +static struct mfd_cell sun5i_gpadc_mfd_cells[] = {
> + {
> + .name = "sun5i-a13-gpadc-iio",
> + .resources = adc_resources,
> + .num_resources = ARRAY_SIZE(adc_resources),
> + }, {
> + .name = "iio_hwmon",
> + },
> +};
As above.
> +static struct mfd_cell sun6i_gpadc_mfd_cells[] = {
> + {
> + .name = "sun6i-a31-gpadc-iio",
> + .resources = adc_resources,
> + .num_resources = ARRAY_SIZE(adc_resources),
> + }, {
> + .name = "iio_hwmon",
> + },
> +};
As above.
> +static const struct regmap_config sun4i_gpadc_mfd_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .fast_io = true,
> +};
> +
> +static const struct of_device_id sun4i_gpadc_mfd_of_match[] = {
> + {
> + .compatible = "allwinner,sun4i-a10-ts",
> + .data = &sun4i_gpadc_mfd_cells,
> + }, {
> + .compatible = "allwinner,sun5i-a13-ts",
> + .data = &sun5i_gpadc_mfd_cells,
> + }, {
> + .compatible = "allwinner,sun6i-a31-ts",
> + .data = &sun6i_gpadc_mfd_cells,
> + }, { /* sentinel */ }
> +};
Don't mix OF and MFD functionality.
Why don't you create a node for "iio_hwmon" and have
platform_of_populate() do your bidding?
> +static int sun4i_gpadc_mfd_probe(struct platform_device *pdev)
Remove all mention of "mfd" from this file.
(Accept the calls to the MFD API of course).
> +{
> + struct sun4i_gpadc_mfd_dev *mfd_dev;
> + struct resource *mem;
> + const struct of_device_id *of_id;
> + const struct mfd_cell *mfd_cells;
> + unsigned int irq;
> + int ret;
> +
> + of_id = of_match_node(sun4i_gpadc_mfd_of_match, pdev->dev.of_node);
> + if (!of_id)
> + return -EINVAL;
> +
> + mfd_dev = devm_kzalloc(&pdev->dev, sizeof(*mfd_dev), GFP_KERNEL);
> + if (!mfd_dev)
> + return -ENOMEM;
> +
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + mfd_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
> + if (IS_ERR(mfd_dev->regs))
> + return PTR_ERR(mfd_dev->regs);
> +
> + mfd_dev->dev = &pdev->dev;
> + dev_set_drvdata(mfd_dev->dev, mfd_dev);
> +
> + mfd_dev->regmap = devm_regmap_init_mmio(mfd_dev->dev, mfd_dev->regs,
> + &sun4i_gpadc_mfd_regmap_config);
> + if (IS_ERR(mfd_dev->regmap)) {
> + ret = PTR_ERR(mfd_dev->regmap);
> + dev_err(&pdev->dev, "failed to init regmap: %d\n", ret);
> + return ret;
> + }
> +
> + /* Disable all interrupts */
> + regmap_write(mfd_dev->regmap, SUN4I_GPADC_INT_FIFOC, 0);
> +
> + irq = platform_get_irq(pdev, 0);
> + ret = devm_regmap_add_irq_chip(&pdev->dev, mfd_dev->regmap, irq,
> + IRQF_ONESHOT, 0,
> + &sun4i_gpadc_mfd_regmap_irq_chip,
> + &mfd_dev->regmap_irqc);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to add irq chip: %d\n", ret);
> + return ret;
> + }
> +
> + mfd_cells = of_id->data;
> + ret = devm_mfd_add_devices(mfd_dev->dev, 0, mfd_cells, 2, NULL, 0,
> + NULL);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to add MFD devices: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +MODULE_DEVICE_TABLE(of, sun4i_gpadc_mfd_of_match);
Place this directly under the table.
> +static struct platform_driver sun4i_gpadc_mfd_driver = {
> + .driver = {
> + .name = "sun4i-adc-mfd",
> + .of_match_table = of_match_ptr(sun4i_gpadc_mfd_of_match),
> + },
> + .probe = sun4i_gpadc_mfd_probe,
No .remove?
> +};
> +
> +module_platform_driver(sun4i_gpadc_mfd_driver);
> +
> +MODULE_DESCRIPTION("Allwinner sunxi platforms' GPADC MFD core driver");
> +MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/mfd/sun4i-gpadc-mfd.h b/include/linux/mfd/sun4i-gpadc-mfd.h
> new file mode 100644
> index 0000000..5cc7863
> --- /dev/null
> +++ b/include/linux/mfd/sun4i-gpadc-mfd.h
> @@ -0,0 +1,94 @@
> +/* Header of ADC MFD core driver for sunxi platforms
> + *
> + * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.mfd>
> + *
> + * This program is free software; you can redistribute it and/or modify it under
> + * the terms of the GNU General Public License version 2 as published by the
> + * Free Software Foundation.
> + */
> +
> +#ifndef __SUN4I_GPADC_MFD__H__
> +#define __SUN4I_GPADC_MFD__H__
> +
> +#define SUN4I_GPADC_CTRL0 0x00
> +
> +#define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x) ((GENMASK(7, 0) & (x)) << 24)
> +#define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY_MODE BIT(23)
> +#define SUN4I_GPADC_CTRL0_ADC_CLK_SELECT BIT(22)
> +#define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20)
> +#define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16)
> +#define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))
> +
> +#define SUN4I_GPADC_CTRL1 0x04
> +
> +#define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x) ((GENMASK(7, 0) & (x)) << 12)
> +#define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE_EN BIT(9)
> +#define SUN4I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(6)
> +#define SUN4I_GPADC_CTRL1_TP_DUAL_EN BIT(5)
> +#define SUN4I_GPADC_CTRL1_TP_MODE_EN BIT(4)
> +#define SUN4I_GPADC_CTRL1_TP_ADC_SELECT BIT(3)
> +#define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(2, 0) & (x))
> +
> +/* TP_CTRL1 bits for sun6i SOCs */
> +#define SUN6I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(7)
> +#define SUN6I_GPADC_CTRL1_TP_DUAL_EN BIT(6)
> +#define SUN6I_GPADC_CTRL1_TP_MODE_EN BIT(5)
> +#define SUN6I_GPADC_CTRL1_TP_ADC_SELECT BIT(4)
> +#define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))
> +
> +#define SUN4I_GPADC_CTRL2 0x08
> +
> +#define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x) ((GENMASK(3, 0) & (x)) << 28)
> +#define SUN4I_GPADC_CTRL2_TP_MODE_SELECT(x) ((GENMASK(1, 0) & (x)) << 26)
> +#define SUN4I_GPADC_CTRL2_PRE_MEA_EN BIT(24)
> +#define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x) (GENMASK(23, 0) & (x))
> +
> +#define SUN4I_GPADC_CTRL3 0x0c
> +
> +#define SUN4I_GPADC_CTRL3_FILTER_EN BIT(2)
> +#define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
> +
> +#define SUN4I_GPADC_TPR 0x18
> +
> +#define SUN4I_GPADC_TPR_TEMP_ENABLE BIT(16)
> +#define SUN4I_GPADC_TPR_TEMP_PERIOD(x) (GENMASK(15, 0) & (x))
> +
> +#define SUN4I_GPADC_INT_FIFOC 0x10
> +
> +#define SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN BIT(18)
> +#define SUN4I_GPADC_INT_FIFOC_TP_OVERRUN_IRQ_EN BIT(17)
> +#define SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN BIT(16)
> +#define SUN4I_GPADC_INT_FIFOC_TP_DATA_XY_CHANGE BIT(13)
> +#define SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(x) ((GENMASK(4, 0) & (x)) << 8)
> +#define SUN4I_GPADC_INT_FIFOC_TP_DATA_DRQ_EN BIT(7)
> +#define SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH BIT(4)
> +#define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN BIT(1)
> +#define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN BIT(0)
> +
> +#define SUN4I_GPADC_INT_FIFOS 0x14
> +
> +#define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING BIT(18)
> +#define SUN4I_GPADC_INT_FIFOS_FIFO_OVERRUN_PENDING BIT(17)
> +#define SUN4I_GPADC_INT_FIFOS_FIFO_DATA_PENDING BIT(16)
> +#define SUN4I_GPADC_INT_FIFOS_TP_IDLE_FLG BIT(2)
> +#define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING BIT(1)
> +#define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING BIT(0)
> +
> +#define SUN4I_GPADC_CDAT 0x1c
> +#define SUN4I_GPADC_TEMP_DATA 0x20
> +#define SUN4I_GPADC_DATA 0x24
> +
> +#define SUN4I_GPADC_IRQ_FIFO_DATA 0
> +#define SUN4I_GPADC_IRQ_TEMP_DATA 1
> +
> +/* 10s delay before suspending the IP */
> +#define SUN4I_GPADC_AUTOSUSPEND_DELAY 10000
> +
> +struct sun4i_gpadc_mfd_dev {
> + struct device *dev;
> + struct regmap *regmap;
> + struct regmap_irq_chip_data *regmap_irqc;
> + void __iomem *regs;
It's *much* more common to call this 'base'.
> +};
> +
> +#endif
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v3 3/8] arm64: KVM: Move vgic-v3 save/restore to virt/kvm/arm/hyp
From: Vladimir Murzin @ 2016-09-12 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57D2E448.304@arm.com>
On 09/09/16 17:33, Marc Zyngier wrote:
> On 08/09/16 17:06, Vladimir Murzin wrote:
>> So we can reuse the code under arch/arm
>>
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>
Thanks!
Vladimir
> M.
>
^ permalink raw reply
* [PATCH V4] perf tools: adding support for address filters
From: Adrian Hunter @ 2016-09-12 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473359122-1045-1-git-send-email-mathieu.poirier@linaro.org>
On 08/09/16 21:25, Mathieu Poirier wrote:
> This patch makes it possible to use the current filter
> framework with address filters. That way address filters for
> HW tracers such as CoreSight and IntelPT can be communicated
> to the kernel drivers.
>
> CC: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>
> ---
> Changes for V4:
> - Added support for address filters over more than one
> nibble.
> - Removed Jiri's ack, this version is too different from
> what was reviewed.
>
> Changes for V3:
> - Added Jiri's ack.
> - Rebased to v4.8-rc5.
>
> Changes for V2:
> - Rebased to v4.8-rc4.
> - Revisited error path.
> ---
> tools/perf/util/evsel.c | 17 +++++++++++++++++
> tools/perf/util/evsel.h | 2 ++
> tools/perf/util/parse-events.c | 39 ++++++++++++++++++++++++++++++++++-----
> 3 files changed, 53 insertions(+), 5 deletions(-)
>
> diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
> index d40f852d2de2..5d809ffb85bc 100644
> --- a/tools/perf/util/evsel.c
> +++ b/tools/perf/util/evsel.c
> @@ -1046,6 +1046,23 @@ int perf_evsel__set_filter(struct perf_evsel *evsel, const char *filter)
> return -1;
> }
>
> +int perf_evsel__append_addr_filter(struct perf_evsel *evsel,
> + const char *filter)
perf_evsel__append_filter() already parameterizes the conjunction. Perhaps it
should parameterize the format, then there is only one function e.g.
int perf_evsel__append_filter(struct perf_evsel *evsel,
const char *fmt, const char *filter)
{
char *new_filter;
if (evsel->filter == NULL)
return perf_evsel__set_filter(evsel, filter);
if (asprintf(&new_filter, fmt, evsel->filter, filter) > 0) {
free(evsel->filter);
evsel->filter = new_filter;
return 0;
}
return -1;
}
> +{
> + char *new_filter;
> +
> + if (evsel->filter == NULL)
> + return perf_evsel__set_filter(evsel, filter);
> +
> + if (asprintf(&new_filter, "%s,%s", evsel->filter, filter) > 0) {
> + free(evsel->filter);
> + evsel->filter = new_filter;
> + return 0;
> + }
> +
> + return -1;
> +}
> +
> int perf_evsel__append_filter(struct perf_evsel *evsel,
> const char *op, const char *filter)
> {
> diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
> index 8ceb7ebb51f5..15ca5f85e946 100644
> --- a/tools/perf/util/evsel.h
> +++ b/tools/perf/util/evsel.h
> @@ -235,6 +235,8 @@ void perf_evsel__set_sample_id(struct perf_evsel *evsel,
> bool use_sample_identifier);
>
> int perf_evsel__set_filter(struct perf_evsel *evsel, const char *filter);
> +int perf_evsel__append_addr_filter(struct perf_evsel *evsel,
> + const char *filter);
> int perf_evsel__append_filter(struct perf_evsel *evsel,
> const char *op, const char *filter);
> int perf_evsel__apply_filter(struct perf_evsel *evsel, int ncpus, int nthreads,
> diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
> index 2eb8b1ed4cc8..3e158ad7eeb8 100644
> --- a/tools/perf/util/parse-events.c
> +++ b/tools/perf/util/parse-events.c
> @@ -1760,20 +1760,49 @@ foreach_evsel_in_last_glob(struct perf_evlist *evlist,
> static int set_filter(struct perf_evsel *evsel, const void *arg)
> {
> const char *str = arg;
> + bool found = false;
> + int nr_addr_filters = 0;
> + struct perf_pmu *pmu = NULL;
>
> - if (evsel == NULL || evsel->attr.type != PERF_TYPE_TRACEPOINT) {
> - fprintf(stderr,
> - "--filter option should follow a -e tracepoint option\n");
> - return -1;
> + if (evsel == NULL)
> + goto err;
> +
> + if (evsel->attr.type == PERF_TYPE_TRACEPOINT) {
> + if (perf_evsel__append_filter(evsel, "&&", str) < 0) {
> + fprintf(stderr,
> + "not enough memory to hold filter string\n");
> + return -1;
> + }
> +
> + return 0;
> }
>
> - if (perf_evsel__append_filter(evsel, "&&", str) < 0) {
> + while ((pmu = perf_pmu__scan(pmu)) != NULL)
> + if (pmu->type == evsel->attr.type) {
> + found = true;
> + break;
> + }
> +
> + if (found)
> + perf_pmu__scan_file(pmu, "nr_addr_filters",
> + "%d", &nr_addr_filters);
> +
> + if (!nr_addr_filters)
> + goto err;
> +
> + if (perf_evsel__append_addr_filter(evsel, str) < 0) {
> fprintf(stderr,
> "not enough memory to hold filter string\n");
> return -1;
> }
>
> return 0;
> +
> +err:
> + fprintf(stderr,
> + "--filter option should follow a -e tracepoint or HW tracer option\n");
> +
> + return -1;
> }
>
> int parse_filter(const struct option *opt, const char *str,
>
^ permalink raw reply
* [PATCH v3 8/8] ARM: KVM: Support vgic-v3
From: Vladimir Murzin @ 2016-09-12 9:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57D2E746.7080300@arm.com>
On 09/09/16 17:45, Marc Zyngier wrote:
> On 08/09/16 17:06, Vladimir Murzin wrote:
>> This patch allows to build and use vgic-v3 in 32-bit mode.
>>
snip...
>> diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
>> index af25c32..f93f6bd 100644
>> --- a/arch/arm/include/asm/arch_gicv3.h
>> +++ b/arch/arm/include/asm/arch_gicv3.h
>> @@ -96,6 +96,70 @@
>> #define ICH_AP1R2 __AP1Rx(2)
>> #define ICH_AP1R3 __AP1Rx(3)
>>
>> +/* A32-to-A64 mappings used by VGIC save/restore */
>> +
>> +#define CPUIF_MAP(a32, a64) \
>> +static inline void write_ ## a64(u32 val) \
>> +{ \
>> + write_sysreg(val, a32); \
>> +} \
>> +static inline u32 read_ ## a64(void) \
>> +{ \
>> + return read_sysreg(a32); \
>> +} \
>> +
>> +#define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \
>> +static inline void write_ ## a64(u64 val) \
>> +{ \
>> + write_sysreg((u32)val, a32lo); \
>> + write_sysreg((u32)(val >> 32), a32hi); \
>
> Please use {lower,upper}_32_bits, which make the casting/shifting go away.
>
Will do.
>> +} \
>> +static inline u64 read_ ## a64(void) \
>> +{ \
>> + u64 val = read_sysreg(a32lo); \
>> + \
>> + val |= (u64)read_sysreg(a32hi) << 32; \
>> + \
>> + return val; \
>> +}
>> +
>> +CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
>> +CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
>> +CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
>> +CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
>> +CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2)
>> +CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
>> +CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
>> +CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
>> +CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
>> +CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
>> +CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
>> +CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
>> +CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
>> +CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
>> +CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
>> +CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
>> +
>> +CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
>> +CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
>> +
>> +#define read_gicreg(r) read_##r()
>> +#define write_gicreg(v, r) write_##r(v)
>> +
>
> Can you make this change a separate patch? It will make it easier to
> merge if I can ack it as a standalone change. It will also give the last
> patch a fantastic diffstat... ;-)
>
Yes, I can ;)
snip...
>> diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
>> index 1bb2b79..10c0244 100644
>> --- a/arch/arm/kvm/coproc.c
>> +++ b/arch/arm/kvm/coproc.c
>> @@ -228,6 +228,36 @@ bool access_vm_reg(struct kvm_vcpu *vcpu,
>> return true;
>> }
>>
>> +static bool access_gic_sgi(struct kvm_vcpu *vcpu,
>> + const struct coproc_params *p,
>> + const struct coproc_reg *r)
>> +{
>> + u64 reg;
>> +
>> + if (!p->is_write)
>> + return read_from_write_only(vcpu, p);
>> +
>> + reg = *vcpu_reg(vcpu, p->Rt2);
>> + reg <<= 32;
>
> nit: can you write this as
>
> reg = (u64)*vcpu_reg(vcpu, p->Rt2) << 32;
>
> which I find easier to read...
>
I'll rewrite it.
snip...
>> diff --git a/arch/arm/kvm/hyp/Makefile b/arch/arm/kvm/hyp/Makefile
>> index 8dfa5f7..3023bb5 100644
>> --- a/arch/arm/kvm/hyp/Makefile
>> +++ b/arch/arm/kvm/hyp/Makefile
>> @@ -5,6 +5,7 @@
>> KVM=../../../../virt/kvm
>>
>> obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v2-sr.o
>> +obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
>> obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
>>
>> obj-$(CONFIG_KVM_ARM_HOST) += tlb.o
>> diff --git a/arch/arm/kvm/hyp/switch.c b/arch/arm/kvm/hyp/switch.c
>> index b13caa9..8409dd5 100644
>> --- a/arch/arm/kvm/hyp/switch.c
>> +++ b/arch/arm/kvm/hyp/switch.c
>> @@ -14,6 +14,7 @@
>
> It otherwise looks good to me.
>
Thanks for feedback!
Cheers
Vladimir
> Thanks,
>
> M.
>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox