* [PATCH] ARM: dts: sun8i: Enable pull-ups for bananapi-m2-plus SD slot
From: Mark Kettenis @ 2016-09-18 17:25 UTC (permalink / raw)
To: linux-arm-kernel
Board doesn't seem to have external pull-ups and some (but not all) SD cards
don't work without pull-ups.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
---
Tested with an OpenBSD kernel where enabling the pull-ups makes an older 2G
SanDisk card work. A newer Samsung 32G microSD card doesn't seem to need
this. Note that u-boot always enables the pull-ups and boots just fine off
said 2G SanDisk card.
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index f3b1d5f..3737556 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -117,6 +117,10 @@
status = "okay";
};
+&mmc0_pins_a {
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
--
2.9.3
^ permalink raw reply related
* [PATCH] ASoC: samsung: make audio interface/controller explicitly
From: kbuild test robot @ 2016-09-18 17:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474207751-9804-2-git-send-email-ayaka@soulik.info>
Hi Randy,
[auto build test ERROR on asoc/for-next]
[also build test ERROR on v4.8-rc6 next-20160916]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]
url: https://github.com/0day-ci/linux/commits/Randy-Li/ASoC-samsung-make-audio-interface-controller-explicitly/20160918-222618
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
config: parisc-allmodconfig (attached as .config)
compiler: hppa-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=parisc
All error/warnings (new ones prefixed by >>):
>> sound/soc/samsung/i2s.c:106:26: error: field 'clk_data' has incomplete type
struct clk_onecell_data clk_data;
^~~~~~~~
sound/soc/samsung/i2s.c: In function 'i2s_unregister_clocks':
>> sound/soc/samsung/i2s.c:1141:4: error: implicit declaration of function 'clk_unregister' [-Werror=implicit-function-declaration]
clk_unregister(i2s->clk_table[i]);
^~~~~~~~~~~~~~
sound/soc/samsung/i2s.c: In function 'i2s_unregister_clock_provider':
>> sound/soc/samsung/i2s.c:1149:2: error: implicit declaration of function 'of_clk_del_provider' [-Werror=implicit-function-declaration]
of_clk_del_provider(pdev->dev.of_node);
^~~~~~~~~~~~~~~~~~~
sound/soc/samsung/i2s.c: In function 'i2s_register_clock_provider':
>> sound/soc/samsung/i2s.c:1172:16: error: implicit declaration of function '__clk_get_name' [-Werror=implicit-function-declaration]
p_names[i] = __clk_get_name(rclksrc);
^~~~~~~~~~~~~~
>> sound/soc/samsung/i2s.c:1172:14: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
p_names[i] = __clk_get_name(rclksrc);
^
>> sound/soc/samsung/i2s.c:1181:38: error: implicit declaration of function 'clk_register_mux' [-Werror=implicit-function-declaration]
i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(NULL,
^~~~~~~~~~~~~~~~
>> sound/soc/samsung/i2s.c:1183:5: error: 'CLK_SET_RATE_NO_REPARENT' undeclared (first use in this function)
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
^~~~~~~~~~~~~~~~~~~~~~~~
sound/soc/samsung/i2s.c:1183:5: note: each undeclared identifier is reported only once for each function it appears in
>> sound/soc/samsung/i2s.c:1183:32: error: 'CLK_SET_RATE_PARENT' undeclared (first use in this function)
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
^~~~~~~~~~~~~~~~~~~
>> sound/soc/samsung/i2s.c:1187:38: error: implicit declaration of function 'clk_register_divider' [-Werror=implicit-function-declaration]
i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(NULL,
^~~~~~~~~~~~~~~~~~~~
>> sound/soc/samsung/i2s.c:1198:34: error: implicit declaration of function 'clk_register_gate' [-Werror=implicit-function-declaration]
i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(NULL, clk_name[0],
^~~~~~~~~~~~~~~~~
>> sound/soc/samsung/i2s.c:1201:5: error: 'CLK_GATE_SET_TO_DISABLE' undeclared (first use in this function)
CLK_GATE_SET_TO_DISABLE, i2s->lock);
^~~~~~~~~~~~~~~~~~~~~~~
>> sound/soc/samsung/i2s.c:1206:8: error: implicit declaration of function 'of_clk_add_provider' [-Werror=implicit-function-declaration]
ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
^~~~~~~~~~~~~~~~~~~
>> sound/soc/samsung/i2s.c:1206:42: error: 'of_clk_src_onecell_get' undeclared (first use in this function)
ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
^~~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/clk_data +106 sound/soc/samsung/i2s.c
69e7a69a2 sound/soc/samsung/i2s.c Sylwester Nawrocki 2016-08-04 90 struct snd_dmaengine_dai_dma_data dma_playback;
69e7a69a2 sound/soc/samsung/i2s.c Sylwester Nawrocki 2016-08-04 91 struct snd_dmaengine_dai_dma_data dma_capture;
69e7a69a2 sound/soc/samsung/i2s.c Sylwester Nawrocki 2016-08-04 92 struct snd_dmaengine_dai_dma_data idma_playback;
9bdca822c sound/soc/samsung/i2s.c Arnd Bergmann 2015-11-18 93 dma_filter_fn filter;
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 94 u32 quirks;
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 95 u32 suspend_i2smod;
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 96 u32 suspend_i2scon;
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 97 u32 suspend_i2spsr;
a5a56871f sound/soc/samsung/i2s.c Padmavathi Venna 2014-11-07 98 const struct samsung_i2s_variant_regs *variant_regs;
f36705366 sound/soc/samsung/i2s.c Sylwester Nawrocki 2015-01-14 99
f36705366 sound/soc/samsung/i2s.c Sylwester Nawrocki 2015-01-14 100 /* Spinlock protecting access to the device's registers */
f36705366 sound/soc/samsung/i2s.c Sylwester Nawrocki 2015-01-14 101 spinlock_t spinlock;
f36705366 sound/soc/samsung/i2s.c Sylwester Nawrocki 2015-01-14 102 spinlock_t *lock;
074b89bb5 sound/soc/samsung/i2s.c Sylwester Nawrocki 2015-01-14 103
074b89bb5 sound/soc/samsung/i2s.c Sylwester Nawrocki 2015-01-14 104 /* Below fields are only valid if this is the primary FIFO */
074b89bb5 sound/soc/samsung/i2s.c Sylwester Nawrocki 2015-01-14 105 struct clk *clk_table[3];
074b89bb5 sound/soc/samsung/i2s.c Sylwester Nawrocki 2015-01-14 @106 struct clk_onecell_data clk_data;
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 107 };
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 108
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 109 /* Lock for cross i/f checks */
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 110 static DEFINE_SPINLOCK(lock);
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 111
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 112 /* If this is the 'overlay' stereo DAI */
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 113 static inline bool is_secondary(struct i2s_dai *i2s)
1c7ac0180 sound/soc/s3c24xx/i2s.c Jassi Brar 2010-11-22 114 {
:::::: The code at line 106 was first introduced by commit
:::::: 074b89bb5fb7e80e0f98f1b45f276b0386269e3d ASoC: samsung: i2s: Add clock provider for the I2S internal clocks
:::::: TO: Sylwester Nawrocki <s.nawrocki@samsung.com>
:::::: CC: Mark Brown <broonie@kernel.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v4] ARM: mmp: let clk_disable() return immediately if clk is NULL
From: Masahiro Yamada @ 2016-09-18 17:58 UTC (permalink / raw)
To: linux-arm-kernel
In many of clk_disable() implementations, it is a no-op for a NULL
pointer input, but this is one of the exceptions.
Making it treewide consistent will allow clock consumers to call
clk_disable() without NULL pointer check.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
Changes in v4:
- Split into per-arch patches
Changes in v3:
- Return only when clk is NULL. Do not take care of error pointer.
Changes in v2:
- Rebase on Linux 4.6-rc1
arch/arm/mach-mmp/clock.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
index ac6633d..28fe64c 100644
--- a/arch/arm/mach-mmp/clock.c
+++ b/arch/arm/mach-mmp/clock.c
@@ -67,6 +67,9 @@ void clk_disable(struct clk *clk)
{
unsigned long flags;
+ if (!clk)
+ return;
+
WARN_ON(clk->enabled == 0);
spin_lock_irqsave(&clocks_lock, flags);
--
1.9.1
^ permalink raw reply related
* [PATCH v4] ARM: w90x900: let clk_disable() return immediately if clk is NULL
From: Masahiro Yamada @ 2016-09-18 17:59 UTC (permalink / raw)
To: linux-arm-kernel
In many of clk_disable() implementations, it is a no-op for a NULL
pointer input, but this is one of the exceptions.
Making it treewide consistent will allow clock consumers to call
clk_disable() without NULL pointer check.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Wan Zongshun <mcuos.com@gmail.com>
---
Changes in v4:
- Split into per-arch patches
Changes in v3:
- Return only when clk is NULL. Do not take care of error pointer.
Changes in v2:
- Rebase on Linux 4.6-rc1
arch/arm/mach-w90x900/clock.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c
index 2c371ff..ac6fd1a 100644
--- a/arch/arm/mach-w90x900/clock.c
+++ b/arch/arm/mach-w90x900/clock.c
@@ -46,6 +46,9 @@ void clk_disable(struct clk *clk)
{
unsigned long flags;
+ if (!clk)
+ return;
+
WARN_ON(clk->enabled == 0);
spin_lock_irqsave(&clocks_lock, flags);
--
1.9.1
^ permalink raw reply related
* [PATCH v4] MIPS: bcm63xx: let clk_disable() return immediately if clk is NULL
From: Masahiro Yamada @ 2016-09-18 18:04 UTC (permalink / raw)
To: linux-arm-kernel
In many of clk_disable() implementations, it is a no-op for a NULL
pointer input, but this is one of the exceptions.
Making it treewide consistent will allow clock consumers to call
clk_disable() without NULL pointer check.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
Changes in v4:
- Split into per-arch patches
Changes in v3:
- Return only when clk is NULL. Do not take care of error pointer.
Changes in v2:
- Rebase on Linux 4.6-rc1
arch/mips/bcm63xx/clk.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 6375652..b49fc9c 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -326,6 +326,9 @@ EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
+ if (!clk)
+ return;
+
mutex_lock(&clocks_mutex);
clk_disable_unlocked(clk);
mutex_unlock(&clocks_mutex);
--
1.9.1
^ permalink raw reply related
* [PATCH] ASoC: samsung: make audio interface/controller explicitly
From: Krzysztof Kozlowski @ 2016-09-18 18:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1bc1a3db-8120-a2ae-0f55-a5c1bb154dc6@soulik.info>
On Sun, Sep 18, 2016 at 11:12:34PM +0800, ayaka wrote:
>
>
> On 09/18/2016 10:42 PM, Krzysztof Kozlowski wrote:
> >On Sun, Sep 18, 2016 at 10:09:11PM +0800, Randy Li wrote:
> >>It is simple sound card time, we could assign different codec
> >>to a interface without making a specific driver for it.
> >The description does not convince me and I do not see an example using
> >this. Could you provide one?
> Sorry, the board TOPEET iTop 4412 for exynos 4412 I posted supported codec
> with I2S interface using the simple sound card. Anyway, it is no harm to
> make them explicitly right?
kbuild gave you the answer...
> Or I have to enabled those codec support for
> SMDK, which is not needed for the other board.
If I understand correctly, the i2s/pcm etc are still needed but not
built in config choosing only simple-audio-card? I tried now such
configuration on Odroid XU and indeed the audio is missing.
The patch looks like needed but:
1. You need to describe the rationale in commit message, why it is
needed.
2. You need to fix it... kbuild pointed build issues.
Other solution would be to add a user-selectable option for generic
sound on Samsung using simple audio card. The option would then select
appropriate SND_SAMSUNG* options, just like specific drivers do. I see
that sh does like this. Personally this approach seems simpler to me -
the defconfig could just choose this generic sound instead of many
SND_SAMSUNG_* sub-options.
Best regards,
Krzysztof
> >
> >Best regards,
> >Krzysztof
> >
> >
> >>Signed-off-by: Randy Li <ayaka@soulik.info>
> >>---
> >> sound/soc/samsung/Kconfig | 8 ++++----
> >> 1 file changed, 4 insertions(+), 4 deletions(-)
> >>
> >>diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
> >>index 7b722b0..b7b3a38 100644
> >>--- a/sound/soc/samsung/Kconfig
> >>+++ b/sound/soc/samsung/Kconfig
> >>@@ -18,18 +18,18 @@ config SND_S3C2412_SOC_I2S
> >> select SND_S3C_I2SV2_SOC
> >> config SND_SAMSUNG_PCM
> >>- tristate
> >>+ tristate "Samsung PCM interface support"
> >> config SND_SAMSUNG_AC97
> >>- tristate
> >>+ tristate "Samsung AC97 controller support"
> >> select SND_SOC_AC97_BUS
> >> config SND_SAMSUNG_SPDIF
> >>- tristate
> >>+ tristate "Samsung SPDIF transmitter support"
> >> select SND_SOC_SPDIF
> >> config SND_SAMSUNG_I2S
> >>- tristate
> >>+ tristate "Samsung I2S interface support"
> >> config SND_SOC_SAMSUNG_NEO1973_WM8753
> >> tristate "Audio support for Openmoko Neo1973 Smartphones (GTA02)"
> >>--
> >>2.7.4
> >>
>
^ permalink raw reply
* [PATCH] ARM: mediatek: clean up mach-mediatek/Makefile
From: Masahiro Yamada @ 2016-09-18 18:11 UTC (permalink / raw)
To: linux-arm-kernel
Kbuild descends into arch/arm/mach-mediatek/Makefile only when
CONFIG_ARCH_MEDIATEK is enabled. So, obj-$(CONFIG_ARCH_MEDIATEK)
is always equivalent to obj-y in this Makefile.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-mediatek/Makefile | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 2116460..dadae67 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -1,4 +1,2 @@
-ifeq ($(CONFIG_SMP),y)
-obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
-endif
-obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
+obj-$(CONFIG_SMP) += platsmp.o
+obj-y += mediatek.o
--
1.9.1
^ permalink raw reply related
* [PATCH v2] dmaengine: s3c24xx: Add dma_slave_map for s3c2440 devices
From: Sam Van Den Berge @ 2016-09-18 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b8d6e8a9-4807-0dc0-95c8-a4aca89f18e7@samsung.com>
On Fri, Sep 16, 2016 at 01:00:12PM +0200, Sylwester Nawrocki wrote:
> On 09/15/2016 09:41 PM, Sam Van Den Berge wrote:
> > @@ -445,10 +446,44 @@ static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
> > [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
> > };
> >
> > +static const struct dma_slave_map s3c2440_dma_slave_map[] = {
> > + /* TODO: DMACH_XD0 */
> > + /* TODO: DMACH_XD1 */
> > + { "3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
>
> Thanks for the patch, still device name needs to be changed here
> to "s3c2440-sdi".
Thanks for spotting this! I guess I was too focused on the "rx-tx" part
that I totally missed the missing leading "s". I will fix this in v3.
Sam.
^ permalink raw reply
* [RFC PATCH v2 1/2] ARM: dts: samsung: add rga-lvds panel in itop elite
From: Krzysztof Kozlowski @ 2016-09-18 19:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474208859-10045-2-git-send-email-ayaka@soulik.info>
On Sun, Sep 18, 2016 at 10:27:38PM +0800, Randy Li wrote:
> It is actually a lvds panel connected through a rga-lvds bridge.
> The touchscreen is communicated with i2c bus but the driver is not
> support now.
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
Subject: ARM: dts: exynos
> ---
> arch/arm/boot/dts/exynos4412-itop-elite.dts | 54 +++++++++++++++++++++++++++--
> 1 file changed, 52 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
> index b08705e..9ef0505 100644
> --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts
> +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
> @@ -138,6 +138,36 @@
> assigned-clocks = <&clock CLK_MOUT_CAM0>;
> assigned-clock-parents = <&clock CLK_XUSBXTI>;
> };
> +
> + vcc_sys_lcd: sys-lcd {
No underscores, use hyphens.
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
Isn't this one of S5M8767 PMIC regulators? If so, then it should be
defined there... On the other hand, the PMIC supports GPIO enable
control only for buck9...
> + };
> +
> + panel: panel at 0 {
> + compatible = "chunghwa,claa070wp03xg";
> +
> + power-supply = <&vcc_sys_lcd>;
> + enable-gpios = <&gpl0 2 GPIO_ACTIVE_HIGH>;
> + backlight = <&bl>;
> +
> + port {
> + lcd_ep: endpoint {
lcd-ep
> + remote-endpoint = <&rga_lvds>;
> + };
> + };
> + };
> +
> + bl: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm 1 5000000 PWM_POLARITY_INVERTED>;
> + brightness-levels = <0 5 12 16 32 64 128 255>;
> + default-brightness-level = <5>;
> + power-supply = <&vcc_sys_lcd>;
> + };
> };
>
> &adc {
> @@ -215,9 +245,9 @@
>
> &pwm {
> status = "okay";
> - pinctrl-0 = <&pwm0_out>;
> + pinctrl-0 = <&pwm0_out &pwm1_out>;
> pinctrl-names = "default";
> - samsung,pwm-outputs = <0>;
> + samsung,pwm-outputs = <0>, <1>;
> };
>
> &sdhci_2 {
> @@ -238,3 +268,23 @@
> &serial_2 {
> status = "okay";
> };
> +
> +&i2c_3 {
> + status = "okay";
> +};
> +
> +&fimd {
Please put these nodes in alphabetical order. I asked about it for
initial DTS and it applies still.
> + pinctrl-0 = <&lcd_clk &lcd_data24>;
> + pinctrl-names = "default";
> + status = "okay";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port at 3 {
> + reg = <3>;
> + rga_lvds: endpoint {
rga-lvds
Best regards,
Krzysztof
> + remote-endpoint = <&lcd_ep>;
> + };
> + };
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH -next] drm/sun4i: backend: remove redundant dev_err call in sun4i_backend_bind()
From: Maxime Ripard @ 2016-09-18 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473909958-30216-1-git-send-email-weiyj.lk@gmail.com>
On Thu, Sep 15, 2016 at 03:25:58AM +0000, Wei Yongjun wrote:
> From: Wei Yongjun <weiyongjun1@huawei.com>
>
> There is a error message within devm_ioremap_resource
> already, so remove the dev_err call to avoid redundant
> error message.
>
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Queued, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [RFC PATCH v2 1/2] ARM: dts: samsung: add rga-lvds panel in itop elite
From: Krzysztof Kozlowski @ 2016-09-18 19:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160918190348.GA5556@kozik-book>
On Sun, Sep 18, 2016 at 09:03:48PM +0200, Krzysztof Kozlowski wrote:
> On Sun, Sep 18, 2016 at 10:27:38PM +0800, Randy Li wrote:
> > It is actually a lvds panel connected through a rga-lvds bridge.
> > The touchscreen is communicated with i2c bus but the driver is not
> > support now.
> >
> > Signed-off-by: Randy Li <ayaka@soulik.info>
>
> Subject: ARM: dts: exynos
>
> > ---
> > arch/arm/boot/dts/exynos4412-itop-elite.dts | 54 +++++++++++++++++++++++++++--
> > 1 file changed, 52 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
> > index b08705e..9ef0505 100644
> > --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts
> > +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
> > @@ -138,6 +138,36 @@
> > assigned-clocks = <&clock CLK_MOUT_CAM0>;
> > assigned-clock-parents = <&clock CLK_XUSBXTI>;
> > };
> > +
> > + vcc_sys_lcd: sys-lcd {
>
> No underscores, use hyphens.
Ah wait, it's a label, so underscore seems ok. My mistake.
>
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc_5v";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
>
> Isn't this one of S5M8767 PMIC regulators? If so, then it should be
> defined there... On the other hand, the PMIC supports GPIO enable
> control only for buck9...
>
> > + };
> > +
> > + panel: panel at 0 {
> > + compatible = "chunghwa,claa070wp03xg";
> > +
> > + power-supply = <&vcc_sys_lcd>;
> > + enable-gpios = <&gpl0 2 GPIO_ACTIVE_HIGH>;
> > + backlight = <&bl>;
> > +
> > + port {
> > + lcd_ep: endpoint {
>
> lcd-ep
No need, the same.
Best regards,
Krzysztof
>
> > + remote-endpoint = <&rga_lvds>;
> > + };
> > + };
> > + };
> > +
> > + bl: backlight {
> > + compatible = "pwm-backlight";
> > + pwms = <&pwm 1 5000000 PWM_POLARITY_INVERTED>;
> > + brightness-levels = <0 5 12 16 32 64 128 255>;
> > + default-brightness-level = <5>;
> > + power-supply = <&vcc_sys_lcd>;
> > + };
> > };
> >
> > &adc {
> > @@ -215,9 +245,9 @@
> >
> > &pwm {
> > status = "okay";
> > - pinctrl-0 = <&pwm0_out>;
> > + pinctrl-0 = <&pwm0_out &pwm1_out>;
> > pinctrl-names = "default";
> > - samsung,pwm-outputs = <0>;
> > + samsung,pwm-outputs = <0>, <1>;
> > };
> >
> > &sdhci_2 {
> > @@ -238,3 +268,23 @@
> > &serial_2 {
> > status = "okay";
> > };
> > +
> > +&i2c_3 {
> > + status = "okay";
> > +};
> > +
> > +&fimd {
>
> Please put these nodes in alphabetical order. I asked about it for
> initial DTS and it applies still.
>
> > + pinctrl-0 = <&lcd_clk &lcd_data24>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + port at 3 {
> > + reg = <3>;
> > + rga_lvds: endpoint {
>
> rga-lvds
>
> Best regards,
> Krzysztof
>
> > + remote-endpoint = <&lcd_ep>;
> > + };
> > + };
> > + };
> > +};
> > --
> > 2.7.4
> >
^ permalink raw reply
* [PATCH 1/4] drm/sun4i: rgb: Declare RGB encoder and connector as MIPI DPI
From: Maxime Ripard @ 2016-09-18 19:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915151402.15992-2-wens@csie.org>
Hi,
On Thu, Sep 15, 2016 at 11:13:59PM +0800, Chen-Yu Tsai wrote:
> The 18 or 24 bit parallel RGB LCD panel interface found on Allwinner
> SoCs matches the description of MIPI DPI. Declare the RGB encoder and
> connector as MIPI DPI.
Unfortunately, even it that patch might be true (is there a public
spec for that standard?), this breaks the user-space, so there's no
way we change this.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 3/4] drm/sun4i: dotclock: Allow divider = 127
From: Maxime Ripard @ 2016-09-18 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915151402.15992-4-wens@csie.org>
On Thu, Sep 15, 2016 at 11:14:01PM +0800, Chen-Yu Tsai wrote:
> The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127,
> or 6 ~ 127 if phase offsets are used. The 0 register value also
> represents a divider of 1 or bypass.
>
> Make the end condition of the for loop inclusive of 127 in the
> round_rate callback.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 2/4] drm/sun4i: dotclock: Fix clock rate read back calcation
From: Maxime Ripard @ 2016-09-18 19:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915151402.15992-3-wens@csie.org>
On Thu, Sep 15, 2016 at 11:14:00PM +0800, Chen-Yu Tsai wrote:
> When reading back the divider set in the register, we mask off the
> bits that aren't part of the divider. Unfortunately the mask used
> here was not converted from the field width.
>
> Fix this by converting the field width to a proper bit mask.
>
> Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v7 1/3] ARM: dts: Add TOPEET itop core board SCP package version
From: Krzysztof Kozlowski @ 2016-09-18 19:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474207279-9662-2-git-send-email-ayaka@soulik.info>
On Sun, Sep 18, 2016 at 10:01:17PM +0800, Randy Li wrote:
> The TOPEET itop is a samsung exnynos 4412 core board, which have
> two package versions. This patch add the support for SCP version.
>
> Currently supported are USB3503A HSIC, USB OTG, eMMC, rtc and
> PMIC. The future features are in the based board. Also MFC and
> watchdog have been enabled.
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> ---
> arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 491 ++++++++++++++++++++++++
> 1 file changed, 491 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
>
> diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
> new file mode 100644
> index 0000000..1b780cf
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
> @@ -0,0 +1,491 @@
> +/*
> + * TOPEET's Exynos4412 based itop board device tree source
> + *
> + * Copyright (c) 2016 SUMOMO Computer Association
> + * https://www.sumomo.mobi
> + * Randy Li <ayaka@soulik.info>
> + *
> + * Device tree source file for TOPEET iTop Exynos 4412 SCP package core
> + * board which is based on Samsung's Exynos4412 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/clock/samsung,s2mps11.h>
Please put above includes in alphabetical order, as it may reduce the
conflicts on simultaneous edits.
> +#include "exynos4412.dtsi"
> +#include "exynos4412-ppmu-common.dtsi"
> +#include "exynos-mfc-reserved-memory.dtsi"
> +
> +/ {
> + memory at 40000000 {
> + device_type = "memory";
> + reg = <0x40000000 0x40000000>;
> + };
> +
> + firmware at 0203F000 {
> + compatible = "samsung,secure-firmware";
> + reg = <0x0203F000 0x1000>;
> + };
> +
> + fixed-rate-clocks {
> + xxti {
> + compatible = "samsung,clock-xxti";
> + clock-frequency = <0>;
> + };
> +
> + xusbxti {
> + compatible = "samsung,clock-xusbxti";
> + clock-frequency = <24000000>;
> + };
> + };
> +
> + thermal-zones {
> + cpu_thermal: cpu-thermal {
> + cooling-maps {
> + map0 {
> + /* Corresponds to 800MHz at freq_table */
> + cooling-device = <&cpu0 7 7>;
> + };
> + map1 {
> + /* Corresponds to 200MHz at freq_table */
> + cooling-device = <&cpu0 13 13>;
> + };
> + };
> + };
> + };
> +
> + usb-hub {
> + compatible = "smsc,usb3503a";
> + reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>;
> + connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>;
> + intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hsic_reset>;
> + };
> +};
> +
> +&bus_dmc {
> + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
> + vdd-supply = <&buck1_reg>;
> + status = "okay";
> +};
> +
> +&bus_acp {
> + devfreq = <&bus_dmc>;
> + status = "okay";
> +};
> +
> +&bus_c2c {
> + devfreq = <&bus_dmc>;
> + status = "okay";
> +};
> +
> +&bus_leftbus {
> + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
> + vdd-supply = <&buck3_reg>;
> + status = "okay";
> +};
> +
> +&bus_rightbus {
> + devfreq = <&bus_leftbus>;
> + status = "okay";
> +};
> +
> +&bus_fsys {
> + devfreq = <&bus_leftbus>;
> + status = "okay";
> +};
> +
> +&bus_peri {
> + devfreq = <&bus_leftbus>;
> + status = "okay";
> +};
> +
> +&bus_mfc {
> + devfreq = <&bus_leftbus>;
> + status = "okay";
> +};
> +
> +&cpu0 {
> + cpu0-supply = <&buck2_reg>;
> +};
> +
> +&hsotg {
> + vusb_d-supply = <&ldo15_reg>;
> + vusb_a-supply = <&ldo12_reg>;
> +};
> +
> +&i2c_1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + samsung,i2c-sda-delay = <100>;
> + samsung,i2c-max-bus-freq = <400000>;
> + pinctrl-0 = <&i2c1_bus>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + s5m8767: s5m8767_pmic at 66 {
s5m8767-pmic at 66 (in node names underscores seems to be discouraged).
> + compatible = "samsung,s5m8767-pmic";
> + reg = <0x66>;
> +
> + s5m8767,pmic-buck-default-dvs-idx = <3>;
> +
> + s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>,
> + <&gpb 6 GPIO_ACTIVE_HIGH>,
> + <&gpb 7 GPIO_ACTIVE_HIGH>;
> +
> + s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>,
> + <&gpm3 6 GPIO_ACTIVE_HIGH>,
> + <&gpm3 7 GPIO_ACTIVE_HIGH>;
> +
> + /* VDD_ARM */
> + s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>,
> + <1243750>, <1118750>,
> + <1068750>, <1012500>,
> + <956250>, <900000>;
> + /* VDD_INT */
> + s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>,
> + <925000>, <925000>,
> + <887500>, <887500>,
> + <850000>, <850000>;
> + /* VDD_G3D */
> + s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>,
> + <1025000>, <950000>,
> + <918750>, <900000>,
> + <875000>, <831250>;
> +
> + regulators {
> + ldo1_reg: LDO1 {
> + regulator-name = "VDD_ALIVE";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + regulator-boot-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + /* SCP uses 1.5v, POP uses 1.2v */
> + ldo2_reg: LDO2 {
> + regulator-name = "VDDQ_M12";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo3_reg: LDO3 {
> + regulator-name = "VDDIOAP_18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo4_reg: LDO4 {
> + regulator-name = "VDDQ_PRE";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
I missed that previously:
You are missing LDO5. DT describes the hardware and LDO5 is still on the
board. Please add it.
> +
> + ldo6_reg: LDO6 {
> + regulator-name = "VDD10_MPLL";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo7_reg: LDO7 {
> + regulator-name = "VDD10_XPLL";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo8_reg: LDO8 {
> + regulator-name = "VDD10_MIPI";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo9_reg: LDO9 {
> + regulator-name = "VDD33_LCD";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo10_reg: LDO10 {
> + regulator-name = "VDD18_MIPI";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo11_reg: LDO11 {
> + regulator-name = "VDD18_ABB1";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo12_reg: LDO12 {
> + regulator-name = "VDD33_UOTG";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo13_reg: LDO13 {
> + regulator-name = "VDDIOPERI_18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo14_reg: LDO14 {
> + regulator-name = "VDD18_ABB02";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo15_reg: LDO15 {
> + regulator-name = "VDD10_USH";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo16_reg: LDO16 {
> + regulator-name = "VDD18_HSIC";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo17_reg: LDO17 {
> + regulator-name = "VDDIOAP_MMC012_28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + /* Used by HSIC */
> + ldo18_reg: LDO18 {
> + regulator-name = "VDDIOPERI_28";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
Ditto, LDO19.
Best regards,
Krzysztof
> +
> + ldo20_reg: LDO20 {
> + regulator-name = "VDD28_CAM";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2800000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo21_reg: LDO21 {
> + regulator-name = "VDD28_AF";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2800000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo22_reg: LDO22 {
> + regulator-name = "VDDA28_2M";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo23_reg: LDO23 {
> + regulator-name = "VDD28_TF";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo24_reg: LDO24 {
> + regulator-name = "VDD33_A31";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo25_reg: LDO25 {
> + regulator-name = "VDD18_CAM";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo26_reg: LDO26 {
> + regulator-name = "VDD18_A31";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo27_reg: LDO27 {
> + regulator-name = "GPS_1V8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + ldo28_reg: LDO28 {
> + regulator-name = "DVDD12";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + buck1_reg: BUCK1 {
> + regulator-name = "vdd_mif";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + regulator-boot-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + buck2_reg: BUCK2 {
> + regulator-name = "vdd_arm";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <1456250>;
> + regulator-always-on;
> + regulator-boot-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + buck3_reg: BUCK3 {
> + regulator-name = "vdd_int";
> + regulator-min-microvolt = <875000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-boot-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + buck4_reg: BUCK4 {
> + regulator-name = "vdd_g3d";
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + buck5_reg: BUCK5 {
> + regulator-name = "vdd_m12";
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + buck6_reg: BUCK6 {
> + regulator-name = "vdd12_5m";
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + buck7_reg: BUCK7 {
> + regulator-name = "pvdd_buck7";
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + buck8_reg: BUCK8 {
> + regulator-name = "pvdd_buck8";
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-boot-on;
> + regulator-always-on;
> + op_mode = <1>; /* Normal Mode */
> + };
> +
> + buck9_reg: BUCK9 {
> + regulator-name = "vddf28_emmc";
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <3000000>;
> + op_mode = <1>; /* Normal Mode */
> + };
> + };
> +
> + s5m8767_osc: clocks {
> + #clock-cells = <1>;
> + clock-output-names = "s5m8767_ap",
> + "s5m8767_cp", "s5m8767_bt";
> + };
> +
> + };
> +};
> +
> +&mfc {
> + status = "okay";
> +};
> +
> +&mshc_0 {
> + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
> + pinctrl-names = "default";
> + status = "okay";
> + vmmc-supply = <&buck9_reg>;
> + num-slots = <1>;
> + broken-cd;
> + card-detect-delay = <200>;
> + samsung,dw-mshc-ciu-div = <3>;
> + samsung,dw-mshc-sdr-timing = <2 3>;
> + samsung,dw-mshc-ddr-timing = <1 2>;
> + bus-width = <8>;
> + cap-mmc-highspeed;
> +};
> +
> +&pinctrl_1 {
> + hsic_reset: hsic-reset {
> + samsung,pins = "gpm2-4";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +};
> +
> +&rtc {
> + status = "okay";
> + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
> + clock-names = "rtc", "rtc_src";
> +};
> +
> +&tmu {
> + vtmu-supply = <&ldo16_reg>;
> + status = "okay";
> +};
> +
> +&watchdog {
> + status = "okay";
> +};
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 4/4] drm/sun4i: dotclock: Round to closest clock rate
From: Maxime Ripard @ 2016-09-18 19:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915151402.15992-5-wens@csie.org>
Hi,
On Thu, Sep 15, 2016 at 11:14:02PM +0800, Chen-Yu Tsai wrote:
> With display pixel clocks we want to have the closest possible clock
> rate, to minimize timing and refresh rate skews. Whether the actual
> clock rate is higher or lower than the requested rate is less important.
>
> Also check candidates against the requested rate, rather than the
> ideal parent rate, the varying dividers also influence the difference
> between the requested rate and the rounded rate.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> drivers/gpu/drm/sun4i/sun4i_dotclock.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
> index 3eb99784f371..d401156490f3 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
> @@ -90,7 +90,8 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
> goto out;
> }
>
> - if ((rounded < ideal) && (rounded > best_parent)) {
> + if (abs(rate - rounded / i) <
> + abs(rate - best_parent / best_div)) {
I'm not sure what you're trying to do here. Why is the divider involved?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v7 2/3] ARM: dts: add TOPEET itop elite based board
From: Krzysztof Kozlowski @ 2016-09-18 19:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474207279-9662-3-git-send-email-ayaka@soulik.info>
On Sun, Sep 18, 2016 at 10:01:18PM +0800, Randy Li wrote:
> The TOPEET itop exynos 4412 have three versions base board. The
> Elite version is the cheap one without too much peripheral devices
> on it.
>
> Currently supported are serial console, wired networking(USB),
> USB OTG in peripheral mode, USB host, SD storage, GPIO buttons,
> PWM beeper, ADC and LEDs. The WM8960 analog audio codec is also
> enabled.
>
> The FIMC is not used for camera currently, I enabled it just for a
> colorspace convertor.
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> ---
> .../bindings/arm/samsung/samsung-boards.txt | 3 +
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/exynos4412-itop-elite.dts | 240 +++++++++++++++++++++
> 3 files changed, 244 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos4412-itop-elite.dts
Looks good to me, for the record:
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
You don't need to resend the third patch. Rob took it.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH soc/next] ARM: BCM53573: Add custom init_time with arch timer workaroud
From: Rafał Miłecki @ 2016-09-18 19:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Rafa? Mi?ecki <rafal@milecki.pl>
BCM53573 uses ARM architected timer but CFE (bootloader) is bugged and
doesn't setup hardware properly. As the architecture requirement clock
should be enabled and CNTFRQ should be set before starting Linux.
Unfortunately it's impossible to have CFE fixed and updated on all
released devices. There are plenty of them on the market and updating
bootloader isn't a standard procedure. We also don't have CFE sources
for BCM53573 devices and no replacement bootloader.
We can't modify arch timer to simply accept specifying clock. Quoting
Mark: "The clock-frequency property is at best a dodgy workaround, and
this is even worse.". Marc also noted that other subsystems may rely on
CNTFRQ as well.
The only sane workaround seems to be fixing this CFE bug in BCM53573
arch code. It doesn't require modifying other drivers and should allow
all subsystems to work correctly.
Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
---
MAINTAINERS | 1 +
arch/arm/mach-bcm/Makefile | 3 +++
arch/arm/mach-bcm/bcm_53573.c | 62 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 66 insertions(+)
create mode 100644 arch/arm/mach-bcm/bcm_53573.c
diff --git a/MAINTAINERS b/MAINTAINERS
index a91bca7..0bb0c4b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2568,6 +2568,7 @@ BROADCOM BCM53573 ARM ARCHITECTURE
M: Rafa? Mi?ecki <rafal@milecki.pl>
L: linux-arm-kernel at lists.infradead.org
S: Maintained
+F: arch/arm/mach-bcm/bcm_53573.c
F: arch/arm/boot/dts/bcm53573*
F: arch/arm/boot/dts/bcm47189*
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 980f585..0d64778 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -50,6 +50,9 @@ ifeq ($(CONFIG_ARCH_BCM_5301X),y)
obj-$(CONFIG_SMP) += platsmp.o
endif
+# BCM53573
+obj-$(CONFIG_ARCH_BCM_53573) += bcm_53573.o
+
# BCM63XXx
ifeq ($(CONFIG_ARCH_BCM_63XX),y)
obj-y += bcm63xx.o
diff --git a/arch/arm/mach-bcm/bcm_53573.c b/arch/arm/mach-bcm/bcm_53573.c
new file mode 100644
index 0000000..540a247
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_53573.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2016 Rafa? Mi?ecki <rafal@milecki.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/mach/arch.h>
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/clk.h>
+
+static inline void arch_timer_set_cntfrq(u32 cntfrq)
+{
+ asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (cntfrq));
+}
+
+/*
+ * CFE bootloader doesn't meet arch requirements. It doesn't enable ILP clock
+ * which is required for arch timer and doesn't set CNTFRQ.
+ * Fix is up here.
+ */
+static void __init bcm_53573_setup_arch_timer(void)
+{
+ struct of_phandle_args out_args = { };
+ struct clk *clk;
+
+ out_args.np = of_find_compatible_node(NULL, NULL, "brcm,bcm53573-ilp");
+ if (!out_args.np) {
+ pr_warn("Failed to find ILP node\n");
+ return;
+ }
+
+ clk = of_clk_get_from_provider(&out_args);
+ if (!IS_ERR(clk)) {
+ if (!clk_prepare_enable(clk))
+ arch_timer_set_cntfrq(clk_get_rate(clk));
+ }
+
+ of_node_put(out_args.np);
+}
+
+/* A copy of ARM's time_init with workaround inserted */
+static void __init bcm_53573_init_time(void)
+{
+#ifdef CONFIG_COMMON_CLK
+ of_clk_init(NULL);
+#endif
+ bcm_53573_setup_arch_timer();
+ clocksource_probe();
+}
+
+static const char *const bcm_53573_dt_compat[] __initconst = {
+ "brcm,bcm53573",
+ NULL,
+};
+
+DT_MACHINE_START(BCM5301X, "BCM53573")
+ .init_time = bcm_53573_init_time,
+ .dt_compat = bcm_53573_dt_compat,
+MACHINE_END
--
2.9.3
^ permalink raw reply related
* [PATCH v4] MIPS: bcm63xx: let clk_disable() return immediately if clk is NULL
From: Florian Fainelli @ 2016-09-18 19:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474221875-22687-1-git-send-email-yamada.masahiro@socionext.com>
Le 18/09/2016 ? 11:04, Masahiro Yamada a ?crit :
> In many of clk_disable() implementations, it is a no-op for a NULL
> pointer input, but this is one of the exceptions.
>
> Making it treewide consistent will allow clock consumers to call
> clk_disable() without NULL pointer check.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply
* [PATCH 4/7] phy: meson: add USB2 PHY support for Meson8b and GXBB
From: Martin Blumenstingl @ 2016-09-18 19:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57DBAB2F.3040905@ti.com>
Hi Kishon,
On Fri, Sep 16, 2016 at 10:19 AM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
> Hi,
>
> On Friday 09 September 2016 09:44 PM, Martin Blumenstingl wrote:
>> On Fri, Sep 9, 2016 at 5:33 PM, Kevin Hilman <khilman@baylibre.com> wrote:
>>> However, the problem with all of the solutions proposed (runtime PM ones
>>> included) is that we're forcing a board-specific design issue (2 devices
>>> sharing a reset line) into a driver that should not have any
>>> board-specific assumptions in it.
>>>
>>> For example, if this driver is used on another platform where different
>>> PHYs have different reset lines, then one of them (the unlucky one who
>>> is not probed first) will never get reset. So any form of per-device
>>> ref-counting is not a portable solution.
>> maybe we should also consider Ben's solution: he played with the USB
>> PHY on his Meson8b board. His approach was to have only one USB PHY
>> driver instance which exposes two PHYs.
>> The downside of this: the driver would have to know the offset of the
>> PHYs (0x0 for the first PHY, 0x20 for the second), but we could handle
>> the reset using runtime PM without any hacks.
>
> I think the offset information can come from the devicetree too. The phy can be
> modeled something like below.
>
> usb-phys at c0000000 {
> compatible = "amlogic,meson-gxbb-usb2-phy";
> reg = <0x0 0xc0000000 0x0 0x40>;
> #address-cells = <2>;
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x40>;
> resets = <&reset 34>;
>
> usb0_phy: usb_phy at 0 {
> #phy-cells = <0>;
> reg = <0x0 0x0 0x0 0x20>;
> clocks = <&clkc CLKID_USB &clkc CLKID_USB0>;
> clock-names = "usb_general", "usb";
> status = "disabled";
> };
>
> usb1_phy: usb_phy at 20 {
> #phy-cells = <0>;
> reg = <0x0 0x20 0x0 0x20>;
> clocks = <&clkc CLKID_USB &clkc CLKID_USB1>;
> clock-names = "usb_general", "usb";
> status = "disabled";
> };
> };
>
> This way the driver will be probed only once (the reset can be done during
> probe). The phy driver should scan the dt node and for every sub-node it
> invokes phy_create?
I'll recap what we have discussed so far (so you don't have to re-read
the whole thread):
The reference driver treats both USB PHYs as separate devices (the
datasheet has no information about the PHYs though). The only
"special" thing is the shared reset line -> together with Philipp
Zabel (the reset framework maintainer) we decided to make
reset_control_reset work for shared reset lines.
That means we can keep the two PHYs as separate devices inside the
.dts, while keeping everything else separate (just like the reference
driver)
Is this fine for you and Arnd?
Regards,
Martin
^ permalink raw reply
* [PATCH v4 1/3] ASoC: sun4i-codec: rename sun4i_codec_widgets for consistency
From: Maxime Ripard @ 2016-09-18 20:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915163630.18026-2-dannym@scratchpost.org>
On Thu, Sep 15, 2016 at 06:36:28PM +0200, Danny Milosavljevic wrote:
> ASoC: sun4i-codec: Rename "sun4i_codec_widgets" to "sun4i_codec_controls" for
> consistency with the struct field name.
>
> Signed-off-by: Danny Milosavljevic <dannym@scratchpost.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v4 2/3] ASoC: rename some sun7i-only registers
From: Maxime Ripard @ 2016-09-18 20:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915163630.18026-3-dannym@scratchpost.org>
On Thu, Sep 15, 2016 at 06:36:29PM +0200, Danny Milosavljevic wrote:
> ASoC: sun4i-codec: Some of the registers are sun7i-only.
That line is useless, you already have the commit title.
>
> Therefore rename "SUN4I_CODEC_SYS_VERI" to "SUN7I_CODEC_AC_DAC_CAL" and
> rename "SUN4I_CODEC_AC_MIC_PHONE_CAL" to "SUN7I_CODEC_AC_MIC_PHONE_CAL".
And removing it, you could make a real sentence, like:
Some of the registers defined in the driver are only usable on the
A20. Rename these registers.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v4 3/3] ASoC: sun4i-codec: Add custom regmap configs
From: Maxime Ripard @ 2016-09-18 20:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915163630.18026-4-dannym@scratchpost.org>
On Thu, Sep 15, 2016 at 06:36:30PM +0200, Danny Milosavljevic wrote:
> ASoC: sun4i-codec: The A20 has a few extra registers that the A10
> doesn't have.
> Therefore, use different regmaps for A10 as compared to A20.
Same comment with the commit log.
>
> Signed-off-by: Danny Milosavljevic <dannym@scratchpost.org>
> ---
> sound/soc/sunxi/sun4i-codec.c | 33 ++++++++++++++++++++++++++++++---
> 1 file changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
> index 3b53b78..c5d6d84c 100644
> --- a/sound/soc/sunxi/sun4i-codec.c
> +++ b/sound/soc/sunxi/sun4i-codec.c
> @@ -682,12 +682,37 @@ static const struct regmap_config sun4i_codec_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> .val_bits = 32,
> + .max_register = SUN4I_CODEC_ADC_RXCNT,
> +};
> +
> +static const struct regmap_config sun7i_codec_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> .max_register = SUN7I_CODEC_AC_MIC_PHONE_CAL,
> };
>
> +struct sun4i_codec_quirks {
> + const struct regmap_config *regmap_config;
> +};
> +
> +static const struct sun4i_codec_quirks sun4i_codec_quirks = {
> + .regmap_config = &sun4i_codec_regmap_config,
> +};
> +
> +static const struct sun4i_codec_quirks sun7i_codec_quirks = {
> + .regmap_config = &sun7i_codec_regmap_config,
> +};
> +
> static const struct of_device_id sun4i_codec_of_match[] = {
> - { .compatible = "allwinner,sun4i-a10-codec" },
> - { .compatible = "allwinner,sun7i-a20-codec" },
> + {
> + .compatible = "allwinner,sun4i-a10-codec",
> + .data = &sun4i_codec_quirks,
> + },
> + {
> + .compatible = "allwinner,sun7i-a20-codec",
> + .data = &sun7i_codec_quirks,
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
> @@ -760,6 +785,7 @@ static int sun4i_codec_probe(struct platform_device *pdev)
> {
> struct snd_soc_card *card;
> struct sun4i_codec *scodec;
> + const struct sun4i_codec_quirks *quirks;
> struct resource *res;
> void __iomem *base;
> int ret;
> @@ -777,8 +803,9 @@ static int sun4i_codec_probe(struct platform_device *pdev)
> return PTR_ERR(base);
> }
>
> + quirks = of_device_get_match_data(&pdev->dev);
And you probably want to check that quirks isn't null there.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes
From: Maxime Ripard @ 2016-09-18 20:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <daee8cd5-c1a1-49c3-e0f8-e83bb9ed3263@codeaurora.org>
On Thu, Sep 15, 2016 at 04:11:32PM -0700, Stephen Boyd wrote:
> On 09/15/2016 01:34 AM, Maxime Ripard wrote:
> > Hi,
> >
> > On Thu, Sep 15, 2016 at 02:57:37PM +0800, Chen-Yu Tsai wrote:
> >> Hi,
> >>
> >> Here are 3 fixes for the new sunxi-ng clk driver for sun6i-a31 recently
> >> introduced for 4.9. The issues were noticed while working on the display
> >> pipeline for the A31/A31s. The second patch follows what Maxime has done
> >> for the A33 CCU driver. The third issue was noticed while doing the first
> >> patch.
> >>
> >> I hope we can get this into 4.9 as well, either right in -rc1, or in a
> >> later -rc.
> > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> >
> > Stephen, could you apply those patches directly on top of my previous
> > PR, or do you want me to send another one?
> >
>
> I can apply directly to clk-next.
Awesome, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v8 9/9] drm/mediatek: add support for Mediatek SoC MT2701
From: CK Hu @ 2016-09-19 1:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473681672-47144-10-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote:
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 17 +++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 7 +++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 29 +++++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_dsi.c | 1 +
> drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 6 ++++++
> 7 files changed, 72 insertions(+)
>
[snip...]
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 4b4e449..465819b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -112,6 +112,7 @@ struct mtk_ddp_comp_match {
>
> static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL },
> + [DDP_COMPONENT_BLS] = { MTK_DISP_PWM, 0, NULL },
I would like to move this modification to the patch of "Add BLS
component". Just like 'shadow register', even we first introduce it in
MT2701, we separate it in another independent patch because it may be
included in other Mediatek Soc. I prefer modification of this patch is
something which exist in MT8173 but is different in MT2701.
Regards,
CK
> [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
> [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
> [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
> @@ -130,11 +131,17 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> };
>
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