* [PATCH] ARM: dts: exynos: Add reboot reason support for Trats2
From: Wolfgang Wiedmeyer @ 2016-09-22 18:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922174606.GA4988@kozik-lap>
Krzysztof Kozlowski writes:
> On Thu, Sep 22, 2016 at 06:48:35PM +0200, Wolfgang Wiedmeyer wrote:
>> This allows to reboot the device into recovery mode and into the download
>> mode of the bootloader.
>
> Which bootloader? Probably UBoot... or Samsung stock one? Could you put
> that information here?
I'm only working with the stock one. I was under the impression that the
stock bootloader cannot be replaced on a i9300 because there's a
signature check. Is UBoot loaded after the stock one on Trats2 or how
does this work? I didn't find information on that.
>>
>> Signed-off-by: Wolfgang Wiedmeyer <wolfgit@wiedmeyer.de>
>> ---
>> arch/arm/boot/dts/exynos4412-trats2.dts | 14 ++++++++++++++
>> arch/arm/boot/dts/exynos4x12.dtsi | 2 +-
>> 2 files changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
>> index 129e973..a38d1e3 100644
>> --- a/arch/arm/boot/dts/exynos4412-trats2.dts
>> +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
>> @@ -1294,3 +1294,17 @@
>> vtmu-supply = <&ldo10_reg>;
>> status = "okay";
>> };
>> +
>> +&pmu {
>> + compatible = "syscon", "simple-mfd";
>> +
>> + reboot-mode {
>> + compatible = "syscon-reboot-mode";
>> + offset = <0x80c>;
>> +
>> + mode-normal = <0x12345670>;
>> + mode-bootloader = <0x12345671>;
>> + mode-download = <0x12345671>;
>> + mode-recovery = <0x12345674>;
>
> Hmmm, how did you get these values? Are they already supported?
I only have the vendor source drop as documentation. The magic mode
values [1] and the offset [2] can be found there.
> It would be nice to document them:
> 1. In Documentation/arm/Samsung/Bootloader-interface.txt
> 2. In header. I hate such magic numbers... you could add new header next
> to existing rockchip one:
> include/dt-bindings/soc/samsung,boot-mode.h
> (and update maintainers entry :) )
Thanks for the review! I will do the documentation and update the commit
message.
Best regards,
Wolfgang
[1] https://code.fossencdi.org/kernel_samsung_smdk4412.git/tree/arch/arm/mach-exynos/sec-reboot.c#n65
[2] https://code.fossencdi.org/kernel_samsung_smdk4412.git/tree/arch/arm/mach-exynos/include/mach/regs-pmu.h#n79
--
Website: https://fossencdi.org
Jabber: wolfgang at wiedmeyer.de
OpenPGP: 0F30 D1A0 2F73 F70A 6FEE 048E 5816 A24C 1075 7FC4
Key download: https://wiedmeyer.de/keys/ww.asc
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^ permalink raw reply
* [PATCH v3] dmaengine: s3c24xx: Add dma_slave_map for s3c2440 devices
From: Sam Van Den Berge @ 2016-09-22 18:51 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the s3c24xx dma driver to be able to pass a
dma_slave_map array via the platform data. This is needed to
be able to use the new, simpler dmaengine API [1].
I used the virtual DMA channels as a parameter for the dma_filter
function. By doing that, I could reuse the existing filter function in
drivers/dma/s3c24xx-dma.c.
I have tested this on my mini2440 board with the audio driver.
According to my observations, dma_request_slave_channel in the
function dmaengine_pcm_new in the file
sound/soc/soc-generic-dmaengine-pcm.c now returns a valid DMA channel
whereas before no DMA channel was returned at that point.
Entries for DMACH_XD0, DMACH_XD1 and DMACH_TIMER are missing because I
don't realy know which driver to use for these.
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/393635.html
Signed-off-by: Sam Van Den Berge <sam.van.den.berge@telenet.be>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
This patch depends on the audio fixes from Sylwester Nawrocki
(http://www.spinics.net/lists/arm-kernel/msg521918.html)
Changes since v2:
- s/3c2440-sdi/s3c2440-sdi/
- Removed reference to the audio fixes of Sylwester from the commit message
because I don't think it belongs in the commit message itself.
Changes since v1:
- rename arm into dmaengine in title
- one channel for s3c2440-sdi named "rx-tx"
arch/arm/mach-s3c24xx/common.c | 35 +++++++++++++++++++++++++++++++
drivers/dma/s3c24xx-dma.c | 3 +++
include/linux/platform_data/dma-s3c24xx.h | 6 ++++++
3 files changed, 44 insertions(+)
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index fe7485d..f6c3f15 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -33,6 +33,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/platform_data/dma-s3c24xx.h>
+#include <linux/dmaengine.h>
#include <mach/hardware.h>
#include <mach/regs-clock.h>
@@ -445,10 +446,44 @@ static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
};
+static const struct dma_slave_map s3c2440_dma_slave_map[] = {
+ /* TODO: DMACH_XD0 */
+ /* TODO: DMACH_XD1 */
+ { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
+ { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 },
+ { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 },
+ { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 },
+ { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 },
+ { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
+ { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
+ { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
+ { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
+ { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
+ { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
+ { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
+ { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
+ /* TODO: DMACH_TIMER */
+ { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
+ { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
+ { "samsung-ac97", "rx", (void *)DMACH_PCM_IN },
+ { "samsung-ac97", "tx", (void *)DMACH_PCM_OUT },
+ { "samsung-ac97", "rx", (void *)DMACH_MIC_IN },
+ { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
+ { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
+ { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
+ { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
+ { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
+ { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
+ { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
+ { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
+};
+
static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
.num_phy_channels = 4,
.channels = s3c2440_dma_channels,
.num_channels = DMACH_MAX,
+ .slave_map = s3c2440_dma_slave_map,
+ .slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map),
};
struct platform_device s3c2440_device_dma = {
diff --git a/drivers/dma/s3c24xx-dma.c b/drivers/dma/s3c24xx-dma.c
index ce67075..d5c85e7 100644
--- a/drivers/dma/s3c24xx-dma.c
+++ b/drivers/dma/s3c24xx-dma.c
@@ -1301,6 +1301,9 @@ static int s3c24xx_dma_probe(struct platform_device *pdev)
s3cdma->slave.device_prep_dma_cyclic = s3c24xx_dma_prep_dma_cyclic;
s3cdma->slave.device_config = s3c24xx_dma_set_runtime_config;
s3cdma->slave.device_terminate_all = s3c24xx_dma_terminate_all;
+ s3cdma->slave.filter.map = pdata->slave_map;
+ s3cdma->slave.filter.mapcnt = pdata->slavecnt;
+ s3cdma->slave.filter.fn = s3c24xx_dma_filter;
/* Register as many memcpy channels as there are physical channels */
ret = s3c24xx_dma_init_virtual_channels(s3cdma, &s3cdma->memcpy,
diff --git a/include/linux/platform_data/dma-s3c24xx.h b/include/linux/platform_data/dma-s3c24xx.h
index 89ba1b0..4f9aba4 100644
--- a/include/linux/platform_data/dma-s3c24xx.h
+++ b/include/linux/platform_data/dma-s3c24xx.h
@@ -30,16 +30,22 @@ struct s3c24xx_dma_channel {
u16 chansel;
};
+struct dma_slave_map;
+
/**
* struct s3c24xx_dma_platdata - platform specific settings
* @num_phy_channels: number of physical channels
* @channels: array of virtual channel descriptions
* @num_channels: number of virtual channels
+ * @slave_map: dma slave map matching table
+ * @slavecnt: number of elements in slave_map
*/
struct s3c24xx_dma_platdata {
int num_phy_channels;
struct s3c24xx_dma_channel *channels;
int num_channels;
+ const struct dma_slave_map *slave_map;
+ int slavecnt;
};
struct dma_chan;
--
1.9.1
^ permalink raw reply related
* [RFC/PATCH] usb: misc: Add a driver for TC7USB40MU
From: Stephen Boyd @ 2016-09-22 18:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160917011605.GB10392@b29397-desktop>
Quoting Peter Chen (2016-09-16 18:16:05)
> On Wed, Sep 14, 2016 at 01:55:02AM -0700, Stephen Boyd wrote:
> > Quoting Stephen Boyd (2016-09-13 18:42:46)
> > > On the db410c 96boards platform we have a TC7USB40MU[1] on the
> > > board to mux the D+/D- lines from the SoC between a micro usb
> > > "device" port and a USB hub for "host" roles. Upon a role switch,
> > > we need to change this mux to forward the D+/D- lines to either
> > > the port or the hub. Therefore, introduce a driver for this
> > > device that intercepts extcon USB_HOST events and logically
> > > asserts a gpio to mux the "host" D+/D- lines when a host cable is
> > > attached. When the cable goes away, it will logically deassert
> > > the gpio and mux the "device" lines.
> > >
> > > [1] https://toshiba.semicon-storage.com/ap-en/product/logic/bus-switch/detail.TC7USB40MU.html
> > >
> > > Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
> > > Cc: Chanwoo Choi <cw00.choi@samsung.com>
> > > Cc: <devicetree@vger.kernel.org>
> > > Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> > > ---
> > >
> > > Should I make the extcon part optional? I could see a case where there are two
> > > "OTG" ports connected to the mux (or two hubs), and for some reason the
> > > software may want to mux between them at runtime. If we mandate an extcon,
> > > that won't be possible to support. Perhaps it would be better to have
> > > the node, but connect it to the usb controller with a phandle (maybe of_graph
> > > endpoints would be useful too) so that when the controller wants to mux over
> > > a port it can do so.
> >
> > Here's some dts mock-up on top of the db410c for the of_graph stuff. I
> > haven't written any code around it, but the idea is to allow the binding
> > to specify how the mux is connected to upstream and downstream D+/D-
> > lines. This way, we can do some dt parsing of the endpoints and their
> > parent nodes to figure out if the mux needs to be set high or low to use
> > a device connector or a usb hub based on if the id cable is present.
> > Maybe I'm over thinking things though and we could just have a DT
> > property for that.
> >
> > soc {
> > usb at 78d9000 {
> > extcon = <&usb_id>, <&usb_id>;
>
> Why you have two same extcon phandler? From my mind, one should id,
> another should is vbus. Besides, I find extcon-usb-gpio.c is lack of
> vbus support, how you support vbus detection for
> connection/disconnection with PC for your chipidea msm patch set?
This was already in the dts files for db410c. In the chipidea binding
one is for EXTCON_USB (vbus) and one is for EXTCON_USB_HOST (id). My
understanding is that extcon-usb-gpio.c sends events for both EXTCON_USB
and EXTCON_USB_HOST when the gpio changes state. vbus detection is not
that great on this board because we only have on gpio for this.
^ permalink raw reply
* [PATCH v2] dmaengine: s3c24xx: Add dma_slave_map for s3c2440 devices
From: Sam Van Den Berge @ 2016-09-22 18:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b32bfb03-e0d1-09b4-95fc-5a6301a9bde5@kernel.org>
On Fri, Sep 16, 2016 at 01:16:31PM +0200, Krzysztof Kozlowski wrote:
> On 09/15/2016 09:41 PM, Sam Van Den Berge wrote:
> > This patch updates the s3c24xx dma driver to be able to pass a
> > dma_slave_map array via the platform data. This is needed to
> > be able to use the new, simpler dmaengine API [1].
> > I used the virtual DMA channels as a parameter for the dma_filter
> > function. By doing that, I could reuse the existing filter function in
> > drivers/dma/s3c24xx-dma.c.
> >
> > I have tested this on my mini2440 board with the audio driver.
> > (I first applied the audio fixes from Sylwester Nawrocki [2])
> > According to my observations, dma_request_slave_channel in the
> > function dmaengine_pcm_new in the file
> > sound/soc/soc-generic-dmaengine-pcm.c now returns a valid DMA channel
> > whereas before no DMA channel was returned at that point.
> >
> > Entries for DMACH_XD0, DMACH_XD1 and DMACH_TIMER are missing because I
> > don't realy know which driver to use for these.
> >
> > [1]
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/393635.html
> > [2] http://www.spinics.net/lists/arm-kernel/msg521918.html
> >
> > Signed-off-by: Sam Van Den Berge <sam.van.den.berge@telenet.be>
> > Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> > Acked-by: Arnd Bergmann <arnd@arndb.de>
> >
> > ---
> >
> > Changes since v1:
> > - rename arm into dmaengine in title
> > - one channel for s3c2440-sdi named "rx-tx"
> >
> > arch/arm/mach-s3c24xx/common.c | 35 +++++++++++++++++++++++++++++++
> > drivers/dma/s3c24xx-dma.c | 3 +++
> > include/linux/platform_data/dma-s3c24xx.h | 6 ++++++
> > 3 files changed, 44 insertions(+)
>
> Vinod, do you want to take it through your tree? Not much difference for
> me, so in such case:
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
I was kinda waiting for an answer on this question because I didn't know
if I should add the acked-by or not but I'm going to assume that it's ok
so I'll include it in the third version of this patch.
>
> Best regards,
> Krzysztof
>
>
^ permalink raw reply
* [PATCH v2] ARM: dts: exynos: Add entries for sound support on Odroid-XU board
From: Krzysztof Kozlowski @ 2016-09-22 18:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5fef2bec-adcf-0230-cd00-7fc29cbbcd32@samsung.com>
On Mon, Sep 19, 2016 at 10:47:46AM +0200, Sylwester Nawrocki wrote:
> On 09/17/2016 10:00 PM, Krzysztof Kozlowski wrote:
> > On Fri, Sep 16, 2016 at 01:58:32PM +0200, Krzysztof Kozlowski wrote:
> >> > On 09/16/2016 01:25 PM, Sylwester Nawrocki wrote:
> >>> > > On 09/16/2016 01:22 PM, Sylwester Nawrocki wrote:
> >>>> > >> This patch adds device nodes for the AUDSS clock controller,
> >>>> > >> peripheral DMA 0/1 controllers and the Audio Subsystem I2S controller.
> >>>> > >> These entries are required for sound support on Odroid-XU board.
> >>>> > >>
> >>>> > >> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> >>>> > >> ---
> >>>> > >> This patch depends on a patch adding clock ID macro definitions.
> >>>> > >> I'm going to provide a topic branch containing required changes.
> >>>> > >>
> >>>> > >> Changes since v1:
> >>>> > >> - GIC_SPI, IRQ_TYPE_NONE used in the PDMA and max98080 interrupt
> >>>> > >> specifiers,
> >>>> > >> - assigned-clock-* properties moved to respective controller
> >>>> > >> nodes.
> >>> > >
> >>> > > And here is a pull request containing clk dependency patches:
> >>> > >
> >>> > > The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
> >>> > >
> >>> > > Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
> >>> > >
> >>> > > are available in the git repository at:
> >>> > >
> >>> > > git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.9-exynos54x0-dt
> >>> > >
> >>> > > for you to fetch changes up to 58d6506f327e3d192998ba03632f546da221b8d8:
> >>> > >
> >>> > > clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks (2016-09-09
> >>> > > 10:13:02 +0200)
> >>> > >
> >> >
> >> > Pulled and applied, thanks!
> >
> > This does not boot...
> > http://www.krzk.eu/builders/boot-odroid-xu-exynos/builds/216
> > http://www.krzk.eu/builders/boot-odroid-xu-multi_v7/builds/195
> >
> > I am going to send pull request this weekend (or Monday) so probably this
> > won't be included. If by any chance you prepare a fix soon, then it
> > will save me from rebasing the branch.
>
> Oops, indeed, I didn't test with just that part of clk changes applied.
> The only resolution here I can see is to pull my whole clk branch,
> it has already been pulled to the upstream clk tree.
Hmmmm, why the clock implementation is needed? Usually it should work
without it. The driver will just handle ENODEV or DEFER... Maybe there
is similar issue to the serial: e51e4d8a185d ("serial: samsung: Fix ERR
pointer dereference on deferred probe")?
Anyway, the patch will wait till next window opens. I hope it will work
then. :)
Best regards,
Krzysztof
>
> The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
>
> Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
>
> are available in the git repository at:
>
> git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.9-samsung
>
> for you to fetch changes up to be95d2c7d918b2b7b973378a1e92bdc6559c21f9:
>
> clk: samsung: Add support for EPLL on exynos5410 (2016-09-09 17:35:13 +0200)
>
> ----------------------------------------------------------------
> In addition to a few clean up and code consolidation patches this
> includes:
> - addition of sound subsystem related clocks for Exynos5410 SoC
> (EPLL, PDMA) and support for "samsung,exynos5410-audss-clock"
> compatible in the clk-exynos-audss driver,
> - addition of DRAM controller related clocks for exynos5420,
> - MAINTAINERS update adding Chanwoo Choi as the Samsung SoC
> clock drivers co-maintainer.
>
> ----------------------------------------------------------------
> Chanwoo Choi (5):
> clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
> MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer
> clk: samsung: exynos5260: Move struct samsung_cmu_info to init section
> clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code
> clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
>
> Sylwester Nawrocki (7):
> clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks
> clk: samsung: exynos5410: Expose the peripheral DMA gate clocks
> clk: samsung: Use common registration function for pll2550x
> clk: samsung: clk-exynos-audss: controller variant handling rework
> clk: samsung: clk-exynos-audss: Add exynos5410 compatible
> clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup
> clk: samsung: Add support for EPLL on exynos5410
>
> .../devicetree/bindings/clock/clk-exynos-audss.txt | 4 +-
> .../devicetree/bindings/clock/exynos5410-clock.txt | 21 +-
> MAINTAINERS | 3 +
> drivers/clk/samsung/clk-exynos-audss.c | 84 +++--
> drivers/clk/samsung/clk-exynos5260.c | 350 ++++++++++-----------
> drivers/clk/samsung/clk-exynos5410.c | 61 ++--
> drivers/clk/samsung/clk-exynos5420.c | 37 +++
> drivers/clk/samsung/clk-exynos5440.c | 9 +-
> drivers/clk/samsung/clk-pll.c | 154 ++++++---
> drivers/clk/samsung/clk-pll.h | 2 +
> include/dt-bindings/clock/exynos5410.h | 3 +
> include/dt-bindings/clock/exynos5420.h | 11 +-
> include/dt-bindings/clock/exynos5440.h | 2 +
> 13 files changed, 453 insertions(+), 288 deletions(-)
>
> --
> Thanks,
> Sylwester
^ permalink raw reply
* [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
From: Stephen Boyd @ 2016-09-22 18:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6cf4c215-e8a3-a9db-fcf1-8b56b5c1fab9@redhat.com>
Quoting Jeremy McNicoll (2016-09-20 17:42:02)
> On 2016-07-08 10:41 AM, Andy Gross wrote:
> > On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
> >> +
> >> +#include "../qcom/msm8992.dtsi"
> >> +
> >> +/ {
> >> + model = "LGE MSM8992 BULLHEAD rev-1.01";
> >> + compatible = "qcom,msm8992";
> >> + qcom,board-id = <0xb64 0>;
> >
> > Please work with sboyd to add the board-id to the dtbTool. We don't put
> > board-ids in the dts file. We post-process the dtb file and add them then.
> >
>
> sboyd has all the info he needs for this, I believe its just with legal
> now. Will remove for V2.
I've pushed out an update for dtbtool to have these msm ids.
>
> >> +
> >> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> >> +
> >> +/ {
> >> + model = "Qualcomm Technologies, Inc. MSM 8992";
> >> + compatible = "qcom,msm8992";
> >> + qcom,msm-id = <251 0>, <252 0>;
>
> This is needed or else the LK provides the following error
>
> [5380] qcom,msm-id entry not found
>
> and refuses to boot.
>
>
> >> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
> >
> > See above comment on ids.
>
> removal of this (pmic-id) seems to be ok.
>
Having the msm ids (and the pmic ids) in dtbtool isn't going to help
here though. I believe the bootloader on these devices uses a design of
appended dtbs where each dtb has the qcom,{msm-id,board-id,pmic-id}
properties in them. The QCDT "header" that dtbtool generates is not
used.
To fix that problem we'll need to update dtbtool to inject these
properties into the dtbs based on the compatible strings. Or get
maintainers to accept that these ids are now necessary for proper
functionality.
Furthermore, the value of board-id (0xb64) is concerning. qcom only
supports a certain set of values there for their boards, but vendors are
free to do whatever they want with that value. This means they can reuse
existing values that would map to qcom's concept of the "mtp" or "cdp"
boards, or they can numbers that would alias with other vendors.
Thankfully, msm-id and pmic-id are values that are under qcom's control,
so those are always going to be unique and sane. Really all that could
alias is board-id.
What does this all mean? We can't support non-qcom boards in the same
boot.img because of the possibility for the board-id property to alias
between different dtbs. Or at least dtbtool will have to do some alias
analysis and eject one aliasing dtbs from the blob. It also means that
we have a lot of work to do in dtbtool to inject these properties based
on strings, and to have custom parsers for different vendor prefixes so
that we know what values to inject (the nightmare is growing).
I've asked the bootloader folks to fix this in future platforms so that
we match based on the compatible string, instead of having to do any
post processing. Basically, put dtbtool logic into the bootloader. The
discussion is still on-going, but I'm hopeful that we don't need to keep
doing things here with post-processing and the headache will be reduced.
That could totally backfire though if vendors decide to leave the
bootloader unchanged and boot the "qcom,msm8992-mtp" dtb that's been
slightly tweaked for their design. Let's hope that doesn't happen.
^ permalink raw reply
* [PATCH V6 3/5] PCI: thunder-pem: Allow to probe PEM-specific register range for ACPI case
From: Bjorn Helgaas @ 2016-09-22 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922124446.GA21681@red-moon>
On Thu, Sep 22, 2016 at 01:44:46PM +0100, Lorenzo Pieralisi wrote:
> On Thu, Sep 22, 2016 at 11:10:13AM +0000, Gabriele Paoloni wrote:
> > Hi Lorenzo, Bjorn
> >
> > > -----Original Message-----
> > > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi at arm.com]
> > > Sent: 22 September 2016 10:50
> > > To: Bjorn Helgaas
> > > Cc: Ard Biesheuvel; Tomasz Nowicki; David Daney; Will Deacon; Catalin
> > > Marinas; Rafael Wysocki; Arnd Bergmann; Hanjun Guo; Sinan Kaya;
> > > Jayachandran C; Christopher Covington; Duc Dang; Robert Richter; Marcin
> > > Wojtas; Liviu Dudau; Wangyijing; Mark Salter; linux-
> > > pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Linaro ACPI
> > > Mailman List; Jon Masters; Andrea Gallo; Jeremy Linton; liudongdong
> > > (C); Gabriele Paoloni; Jeff Hugo; linux-acpi at vger.kernel.org; linux-
> > > kernel at vger.kernel.org; Rafael J. Wysocki
> > > Subject: Re: [PATCH V6 3/5] PCI: thunder-pem: Allow to probe PEM-
> > > specific register range for ACPI case
> > >
> > > On Wed, Sep 21, 2016 at 01:04:57PM -0500, Bjorn Helgaas wrote:
> > > > On Wed, Sep 21, 2016 at 03:05:49PM +0100, Lorenzo Pieralisi wrote:
> > > > > On Tue, Sep 20, 2016 at 02:17:44PM -0500, Bjorn Helgaas wrote:
> > > > > > On Tue, Sep 20, 2016 at 04:09:25PM +0100, Ard Biesheuvel wrote:
> > > > >
> > > > > [...]
> > > > >
> > > > > > > None of these platforms can be fixed entirely in software, and
> > > given
> > > > > > > that we will not be adding quirks for new broken hardware, we
> > > should
> > > > > > > ask ourselves whether having two versions of a quirk, i.e., one
> > > for
> > > > > > > broken hardware + currently shipping firmware, and one for the
> > > same
> > > > > > > broken hardware with fixed firmware is really an improvement
> > > over what
> > > > > > > has been proposed here.
> > > > > >
> > > > > > We're talking about two completely different types of quirks:
> > > > > >
> > > > > > 1) MCFG quirks to use memory-mapped config space that doesn't
> > > quite
> > > > > > conform to the ECAM model in the PCIe spec, and
> > > > > >
> > > > > > 2) Some yet-to-be-determined method to describe address space
> > > > > > consumed by a bridge.
> > > > > >
> > > > > > The first two patches of this series are a nice implementation
> > > for 1).
> > > > > > The third patch (ThunderX-specific) is one possibility for 2),
> > > but I
> > > > > > don't like it because there's no way for generic software like
> > > the
> > > > > > ACPI core to discover these resources.
> > > > >
> > > > > Ok, so basically this means that to implement (2) we need to assign
> > > > > some sort of _HID to these quirky PCI bridges (so that we know what
> > > > > device they represent and we can retrieve their _CRS). I take from
> > > > > this discussion that the goal is to make sure that all non-config
> > > > > resources have to be declared through _CRS device objects, which is
> > > > > fine but that requires a FW update (unless we can fabricate ACPI
> > > > > devices and corresponding _CRS in the kernel whenever we match a
> > > > > given MCFG table signature).
> > > >
> > > > All resources consumed by ACPI devices should be declared through
> > > > _CRS. If you want to fabricate ACPI devices or _CRS via kernel
> > > > quirks, that's fine with me. This could be triggered via MCFG
> > > > signature, DMI info, host bridge _HID, etc.
> > >
> > > I think the PNP quirk approach + PNP0c02 resource put forward by Gab
> > > is enough.
> >
> > Great thanks as we take a final decision I will ask Dogndgong to submit
> > another RFC based on this approach
> >
> > >
> > > > > We discussed this already and I think we should make a decision:
> > > > >
> > > > > http://lists.infradead.org/pipermail/linux-arm-kernel/2016-
> > > March/414722.html
> > > > >
> > > > > > > > I'd like to step back and come up with some understanding of
> > > how
> > > > > > > > non-broken firmware *should* deal with this issue. Then, if
> > > we *do*
> > > > > > > > work around this particular broken firmware in the kernel, it
> > > would be
> > > > > > > > nice to do it in a way that fits in with that understanding.
> > > > > > > >
> > > > > > > > For example, if a companion ACPI device is the preferred
> > > solution, an
> > > > > > > > ACPI quirk could fabricate a device with the required
> > > resources. That
> > > > > > > > would address the problem closer to the source and make it
> > > more likely
> > > > > > > > that the rest of the system will work correctly: /proc/iomem
> > > could
> > > > > > > > make sense, things that look at _CRS generically would work
> > > (e.g,
> > > > > > > > /sys/, an admittedly hypothetical "lsacpi", etc.)
> > > > > > > >
> > > > > > > > Hard-coding stuff in drivers is a point solution that doesn't
> > > provide
> > > > > > > > any guidance for future platforms and makes it likely that
> > > the hack
> > > > > > > > will get copied into even more drivers.
> > > > > > > >
> > > > > > >
> > > > > > > OK, I see. But the guidance for future platforms should be 'do
> > > not
> > > > > > > rely on quirks', and what I am arguing here is that the more we
> > > polish
> > > > > > > up this code and make it clean and reusable, the more likely it
> > > is
> > > > > > > that will end up getting abused by new broken hardware that we
> > > set out
> > > > > > > to reject entirely in the first place.
> > > > > > >
> > > > > > > So of course, if the quirk involves claiming resources, let's
> > > make
> > > > > > > sure that this occurs in the cleanest and most compliant way
> > > possible.
> > > > > > > But any factoring/reuse concerns other than for the current
> > > crop of
> > > > > > > broken hardware should be avoided imo.
> > > > > >
> > > > > > If future hardware is completely ECAM-compliant and we don't need
> > > any
> > > > > > more MCFG quirks, that would be great.
> > > > >
> > > > > Yes.
> > > > >
> > > > > > But we'll still need to describe that memory-mapped config space
> > > > > > somewhere. If that's done with PNP0C02 or similar devices (as is
> > > done
> > > > > > on my x86 laptop), we'd be all set.
> > > > >
> > > > > I am not sure I understand what you mean here. Are you referring
> > > > > to MCFG regions reported as PNP0c02 resources through its _CRS ?
> > > >
> > > > Yes. PCI Firmware Spec r3.0, Table 4-2, note 2 says address ranges
> > > > reported via MCFG or _CBA should be reserved by _CRS of a PNP0C02
> > > > device.
> > >
> > > Ok, that's agreed. It goes without saying that since you are quoting
> > > the PCI spec, if FW fails to report MCFG regions in a PNP0c02 device
> > > _CRS I will consider that a FW bug.
> > >
> > > > > IIUC PNP0C02 is a reservation mechanism, but it does not help us
> > > > > associate its _CRS to a specific PCI host bridge instance, right ?
> > > >
> > > > Gab proposed a hierarchy that *would* associate a PNP0C02 device with
> > > > a PCI bridge:
> > > >
> > > > Device (PCI1) {
> > > > Name (_HID, "HISI0080") // PCI Express Root Bridge
> > > > Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
> > > > Method (_CRS, 0, Serialized) { // Root complex resources
> > > (windows) }
> > > > Device (RES0) {
> > > > Name (_HID, "HISI0081") // HiSi PCIe RC config base address
> > > > Name (_CID, "PNP0C02") // Motherboard reserved resource
> > > > Name (_CRS, ResourceTemplate () { ... }
> > > > }
> > > > }
> > > >
> > > > That's a possibility. The PCI Firmware Spec suggests putting RES0 at
> > > > the root (under \_SB), but I don't know why.
> > > >
> > > > Putting it at the root means we couldn't generically associate it
> > > with
> > > > a bridge, although I could imagine something like this:
> > > >
> > > > Device (RES1) {
> > > > Name (_HID, "HISI0081") // HiSi PCIe RC config base address
> > > > Name (_CID, "PNP0C02") // Motherboard reserved resource
> > > > Name (_CRS, ResourceTemplate () { ... }
> > > > Method (BRDG) { "PCI1" } // hand-wavy ASL
> > > > }
> > > > Device (PCI1) {
> > > > Name (_HID, "HISI0080") // PCI Express Root Bridge
> > > > Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
> > > > Method (_CRS, 0, Serialized) { // Root complex resources
> > > (windows) }
> > > > }
> > > >
> > > > Where you could search PNP0C02 devices for a cookie that matched the
> > > > host bridge.o
> > >
> > > Ok, I am fine with both and I think we are converging, but the way
> > > to solve this problem has to be uniform for all ARM partners (and
> > > not only ARM). Two points here:
> > >
> > > 1) Adding a device/subdevice allows people to add a _CRS reporting the
> > > non-window bridge resources. Fine. It also allows people to chuck in
> > > there all sorts of _DSD properties to describe their PCI host bridge
> > > as it is done with DT properties (those _DSD can contain eg clocks
> > > etc.), this may be tempting (so that they can reuse the same DT
> > > driver and do not have to update their firmware) but I want to be
> > > clear here: that must not happen. So, a subdevice with a _CRS to
> > > report resources, yes, but it will stop there.
> > > 2) It is unclear to me how to formalize the above. People should not
> > > write FW by reading the PCI mailing list, so these guidelines have
> > > to
> > > be written, somehow. I do not want to standardize quirks, I want
> > > to prevent random ACPI table content, which is different.
> > > Should I report this to the ACPI spec working group ? If we do
> > > not do that everyone will go solve this problem as they deem fit.
> > >
> >
> > Do we really need to formalize this?
> >
> > As we discussed in the Linaro call at the moment we have few vendors
> > that need quirks and we want to avoid promoting/accepting quirks for
> > the future.
> >
> > At the time of the call I think we decided to informally accept a set
> > of quirks for the current platforms and reject any other quirk coming
> > after a certain date/kernel version (this to be decided).
> >
> > I am not sure if there is a way to document/formalize a temporary
> > exception from the rule...
>
> - (1) will be enforced.
I'm not sure it's necessary or possible to enforce a "no future
quirks" rule. For one thing, there's already a pretty strong
incentive to avoid quirks: if your hardware doesn't require quirks,
it works with OSes already in the field.
MCFG quirks allow us to use the generic ACPI pci_root.c driver even if
the hardware doesn't support ECAM quite according to the spec.
PNP0C02 usage is a workaround for the failure of the Consumer/Producer
bit. PNP0C02 quirks compensate for firmware that doesn't describe
resource usage accurately. It's possible the ACPI spec folks could
come up with a better Consumer/Producer workaround, if that's needed.
Apparently x86 hasn't needed it yet.
If people add _DSD methods for clocks or whatnot, the hardware won't
work with the generic pci_root.c driver, so there's already an
incentive for avoiding them. x86 has managed without such methods;
arm64 should be able to do the same.
> - We do not know whether PNP0c02 can be used in non-root devices _CRS
> - Are we sure (given that we are implementing this to make sure we are
> able to validate resources) that it is valid to have a subdevice with
> a _CRS whose resources are not contained in its parent _CRS address
> space (because that's exactly the case for these quirks) ?
>
> That's what I mean by formalizing, I want to know how PNP0c02 should
> be used. We all want platforms with quirks to be enabled asap but only
> if we stick to the ACPI specifications. On top of that, with the
> bindings above, the kernel would end up creating a platform device for
> the "fake" device with a _CRS approach, which is questionable.
> > > [...]
> > >
> > > > > For FW that is immutable I really do not see what we can do apart
> > > > > from hardcoding the non-config resources (consumed by a bridge),
> > > > > somehow.
> > > >
> > > > Right. Well, I assume you mean we should hard-code "non-window
> > > > resources consumed directly by a bridge". If firmware in the field
> > > is
> > > > broken, we should work around it, and that may mean hard-coding some
> > > > resources.
> > > >
> > > > My point is that the hard-coding should not be buried in a driver
> > > > where it's invisible to the rest of the kernel. If we hard-code it
> > > in
> > > > a quirk that adds _CRS entries, then the kernel will work just like
> > > it
> > > > would if the firmware had been correct in the first place. The
> > > > resource will appear in /sys/devices/pnp*/*/resources and
> > > /proc/iomem,
> > > > and if we ever used _SRS to assign or move ACPI devices, we would
> > > know
> > > > to avoid the bridge resource.
> > >
> > > We are in complete agreement here.
> > >
> > > Thanks,
> > > Lorenzo
> >
^ permalink raw reply
* [PATCH] arm: dts: fix rk3066a based boards vdd_log voltage initialization
From: Boris Brezillon @ 2016-09-22 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922164752.GP7994@sirena.org.uk>
On Thu, 22 Sep 2016 17:47:52 +0100
Mark Brown <broonie@kernel.org> wrote:
> On Thu, Sep 22, 2016 at 05:12:17PM +0200, Boris Brezillon wrote:
> > +Mark
>
> > I realize Mark has been out of the discussion, and what started as a DT
> > problem actually turned into a PWM regulator discussion.
> > Maybe we should start a new thread.
>
> Probably, you're lucky I even looked at this - the number of irrelevant
> patches I get CCed on is such that I'll often delete things that look
> irrelevant unread. I'm unsure what the relevance is, it looks like it's
> mainly a discussion about pinctrl?
Not exactly, even if this involves pin muxing.
>
> > As I said, the problem you're describing (pins muxed to the PWM device
> > when it should actually stay in gpio+input mode) is not new, and the old
> > pwm-regulator and pwm-rockchip implementation (before my atomic PWM
> > changes) were behaving the same way.
>
> Why would this make any kind of sense?
>
> > What is new though, is the pwm_regulator_init_state() function [1], and
> > it seems it's now preventing the probe of a pwm-regulator device if the
> > initial PWM state is not described in the voltage-table.
>
> > The question is, what should we do?
>
> > 1/ Force users to put an entry matching this state (which means
> > breaking DT compat)
> > 2/ Put a valid value in drvdata->state even if it's not reflecting the
> > real state
> > 3/ Patch regulator core to support an "unknown-selector" return code.
>
> Could someone say what the actual problem was please?
Well, to sum-up, the discussion started because Andy notice that some
boards were no longer booting, and found out that commit 87248991a1de
("regulator: pwm: Properly initialize the ->state field") was causing
the regression, because ->get_voltage_sel() was returning -EINVAL,
which in turn was caused by a missing entry in the voltage table.
Doug also noted that Andy was expecting the pin connected to the PWM
regulator to stay in a GPIO+input state until the PWM is really
enabled, in order to avoid glitches. But this not the case currently,
since the PWM chip claims all the pins at probe time.
So, there are 2 different problems here:
1/ the board no longer boots because of commit 87248991a1de and a
missing entry in the voltage table
2/ claiming the PWM pins at probe time can cause glitches
I'm currently trying to solve #1, but most of the discussion in this
thread was about addressing #2.
> That was a very
> long e-mail so I might be missing something but the obvious thing seems
> to be to force a state since we'll be doing that when we enable anyway.
Hm, okay, but which state should we choose? The first entry in the
voltage-table?
> Or just not have the voltage table and use it as a continuous regulator.
Yes, but that means patching the DT, which means breaking the DT compat.
^ permalink raw reply
* Regression in next with "mfd: twl6040: The chip does not support bulk access"
From: Tony Lindgren @ 2016-09-22 18:07 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Looks like commit 7a17e47f6403 ("mfd: twl6040: The chip does not
support bulk access") breaks at least omap4-duovero. I now get
tons of errors:
Skipping twl internal clock init and using bootloader value (unknown osc rate)
twl 0-0048: PIH (irq 332) nested IRQs
of_get_named_gpiod_flags: parsed 'ti,audpwron-gpio' property of node '/ocp/i2c at 48070000/t
wl at 4b[0]' - status (0)
omap_i2c 48070000.i2c: bus 0 rev0.10 at 400 kHz
twl6040 0-004b: Failed to read IRQ status: -16
twl6040 0-004b: Failed to read IRQ status: -16
twl6040 0-004b: Failed to read IRQ status: -16
twl6040 0-004b: Failed to read IRQ status: -16
twl6040 0-004b: Failed to read IRQ status: -16
twl6040 0-004b: Failed to read IRQ status: -16
twl6040 0-004b: Failed to read IRQ status: -16
twl6040 0-004b: Failed to read IRQ status: -16
twl6040 0-004b: Failed to read IRQ status: -16
It seems the regmap irqs don't work with use_single_rw?
Also seems that twl6040 does support bulk access as things have been
working earlier?
Anyways, can you please revert?
Regards,
Tony
^ permalink raw reply
* [PATCH 0/2] Fix warnings for i2c-rk3x.c
From: Wolfram Sang @ 2016-09-22 17:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474543764-51135-1-git-send-email-david.wu@rock-chips.com>
On Thu, Sep 22, 2016 at 07:29:22PM +0800, David Wu wrote:
> David Wu (2):
> i2c: rk3x: Fix sparse warning
> i2c: rk3x: fix variable 'min_total_ns' unused warning
>
Applied to for-next, thanks!
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^ permalink raw reply
* [PATCH] ARM: dts: exynos: Add reboot reason support for Trats2
From: Krzysztof Kozlowski @ 2016-09-22 17:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474562915-4319-1-git-send-email-wolfgit@wiedmeyer.de>
Hi,
Thanks for the patch, it is nice that someone did this! When I saw the
syscon reboot mode driver, I though about such feature but never had
time or will to implement it. Great job!
Few comments below.
On Thu, Sep 22, 2016 at 06:48:35PM +0200, Wolfgang Wiedmeyer wrote:
> This allows to reboot the device into recovery mode and into the download
> mode of the bootloader.
Which bootloader? Probably UBoot... or Samsung stock one? Could you put
that information here?
>
> Signed-off-by: Wolfgang Wiedmeyer <wolfgit@wiedmeyer.de>
> ---
> arch/arm/boot/dts/exynos4412-trats2.dts | 14 ++++++++++++++
> arch/arm/boot/dts/exynos4x12.dtsi | 2 +-
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
> index 129e973..a38d1e3 100644
> --- a/arch/arm/boot/dts/exynos4412-trats2.dts
> +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
> @@ -1294,3 +1294,17 @@
> vtmu-supply = <&ldo10_reg>;
> status = "okay";
> };
> +
> +&pmu {
> + compatible = "syscon", "simple-mfd";
> +
> + reboot-mode {
> + compatible = "syscon-reboot-mode";
> + offset = <0x80c>;
> +
> + mode-normal = <0x12345670>;
> + mode-bootloader = <0x12345671>;
> + mode-download = <0x12345671>;
> + mode-recovery = <0x12345674>;
Hmmm, how did you get these values? Are they already supported?
It would be nice to document them:
1. In Documentation/arm/Samsung/Bootloader-interface.txt
2. In header. I hate such magic numbers... you could add new header next
to existing rockchip one:
include/dt-bindings/soc/samsung,boot-mode.h
(and update maintainers entry :) )
Best regards,
Krzysztof
> + };
> +};
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> index c452499..b58c14e 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -179,7 +179,7 @@
> ranges;
> status = "disabled";
>
> - pmu at 10020000 {
> + pmu: pmu at 10020000 {
> reg = <0x10020000 0x3000>;
> };
>
> --
> Website: https://fossencdi.org
> OpenPGP: 0F30 D1A0 2F73 F70A 6FEE 048E 5816 A24C 1075 7FC4
> Key download: https://wiedmeyer.de/keys/ww.asc
>
^ permalink raw reply
* [PATCH 2/2] net: thunderx: Support for byte queue limits
From: Florian Fainelli @ 2016-09-22 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474535121-13958-3-git-send-email-sunil.kovvuri@gmail.com>
On 09/22/2016 02:05 AM, sunil.kovvuri at gmail.com wrote:
> From: Sunil Goutham <sgoutham@cavium.com>
>
> This patch adds support for byte queue limits
>
> Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
Where is the code that calls netdev_tx_reset_queue()? This is needed in
the function that brings down the interface, did your test survive a
up/down/up sequence?
> ---
> drivers/net/ethernet/cavium/thunder/nicvf_main.c | 11 ++++++--
> drivers/net/ethernet/cavium/thunder/nicvf_queues.c | 30 ++++++++++++++--------
> 2 files changed, 29 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_main.c b/drivers/net/ethernet/cavium/thunder/nicvf_main.c
> index 7d00162..453e3a0 100644
> --- a/drivers/net/ethernet/cavium/thunder/nicvf_main.c
> +++ b/drivers/net/ethernet/cavium/thunder/nicvf_main.c
> @@ -516,7 +516,8 @@ static int nicvf_init_resources(struct nicvf *nic)
> static void nicvf_snd_pkt_handler(struct net_device *netdev,
> struct cmp_queue *cq,
> struct cqe_send_t *cqe_tx,
> - int cqe_type, int budget)
> + int cqe_type, int budget,
> + unsigned int *tx_pkts, unsigned int *tx_bytes)
> {
> struct sk_buff *skb = NULL;
> struct nicvf *nic = netdev_priv(netdev);
> @@ -547,6 +548,8 @@ static void nicvf_snd_pkt_handler(struct net_device *netdev,
> }
> nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
> prefetch(skb);
> + (*tx_pkts)++;
> + *tx_bytes += skb->len;
> napi_consume_skb(skb, budget);
> sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL;
> } else {
> @@ -662,6 +665,7 @@ static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
> struct cmp_queue *cq = &qs->cq[cq_idx];
> struct cqe_rx_t *cq_desc;
> struct netdev_queue *txq;
> + unsigned int tx_pkts = 0, tx_bytes = 0;
>
> spin_lock_bh(&cq->lock);
> loop:
> @@ -701,7 +705,7 @@ loop:
> case CQE_TYPE_SEND:
> nicvf_snd_pkt_handler(netdev, cq,
> (void *)cq_desc, CQE_TYPE_SEND,
> - budget);
> + budget, &tx_pkts, &tx_bytes);
> tx_done++;
> break;
> case CQE_TYPE_INVALID:
> @@ -730,6 +734,9 @@ done:
> netdev = nic->pnicvf->netdev;
> txq = netdev_get_tx_queue(netdev,
> nicvf_netdev_qidx(nic, cq_idx));
> + if (tx_pkts)
> + netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
> +
> nic = nic->pnicvf;
> if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) {
> netif_tx_start_queue(txq);
> diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
> index 178c5c7..a4fc501 100644
> --- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
> +++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
> @@ -1082,6 +1082,24 @@ static inline void nicvf_sq_add_cqe_subdesc(struct snd_queue *sq, int qentry,
> imm->len = 1;
> }
>
> +static inline void nicvf_sq_doorbell(struct nicvf *nic, struct sk_buff *skb,
> + int sq_num, int desc_cnt)
> +{
> + struct netdev_queue *txq;
> +
> + txq = netdev_get_tx_queue(nic->pnicvf->netdev,
> + skb_get_queue_mapping(skb));
> +
> + netdev_tx_sent_queue(txq, skb->len);
> +
> + /* make sure all memory stores are done before ringing doorbell */
> + smp_wmb();
> +
> + /* Inform HW to xmit all TSO segments */
> + nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR,
> + sq_num, desc_cnt);
> +}
> +
> /* Segment a TSO packet into 'gso_size' segments and append
> * them to SQ for transfer
> */
> @@ -1141,12 +1159,8 @@ static int nicvf_sq_append_tso(struct nicvf *nic, struct snd_queue *sq,
> /* Save SKB in the last segment for freeing */
> sq->skbuff[hdr_qentry] = (u64)skb;
>
> - /* make sure all memory stores are done before ringing doorbell */
> - smp_wmb();
> + nicvf_sq_doorbell(nic, skb, sq_num, desc_cnt);
>
> - /* Inform HW to xmit all TSO segments */
> - nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR,
> - sq_num, desc_cnt);
> nic->drv_stats.tx_tso++;
> return 1;
> }
> @@ -1219,12 +1233,8 @@ doorbell:
> nicvf_sq_add_cqe_subdesc(sq, qentry, tso_sqe, skb);
> }
>
> - /* make sure all memory stores are done before ringing doorbell */
> - smp_wmb();
> + nicvf_sq_doorbell(nic, skb, sq_num, subdesc_cnt);
>
> - /* Inform HW to xmit new packet */
> - nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR,
> - sq_num, subdesc_cnt);
> return 1;
>
> append_fail:
>
--
Florian
^ permalink raw reply
* [PATCH v2] musb: Export musb_root_disconnect for use in modules
From: Mark Brown @ 2016-09-22 17:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922172842.GA23726@kroah.com>
On Thu, Sep 22, 2016 at 07:28:42PM +0200, Greg Kroah-Hartman wrote:
> On Thu, Sep 22, 2016 at 06:15:26PM +0100, Mark Brown wrote:
> > On Thu, Sep 22, 2016 at 08:30:16AM -0500, Bin Liu wrote:
> > > Removed it from my tree, since Greg already picked it.
> > It's not showing in today's -next...
> It probably missed the cut-off, should be there tomorrow.
Ah, excellent thanks! Down to only one build break in all*config in -next :/
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^ permalink raw reply
* [PATCH v2] musb: Export musb_root_disconnect for use in modules
From: Greg Kroah-Hartman @ 2016-09-22 17:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922171526.GR7994@sirena.org.uk>
On Thu, Sep 22, 2016 at 06:15:26PM +0100, Mark Brown wrote:
> On Thu, Sep 22, 2016 at 08:30:16AM -0500, Bin Liu wrote:
> > On Wed, Sep 21, 2016 at 03:51:33PM -0500, Bin Liu wrote:
>
> > > Applied. Thanks.
>
> > Removed it from my tree, since Greg already picked it.
>
> It's not showing in today's -next...
It probably missed the cut-off, should be there tomorrow.
^ permalink raw reply
* [PATCH v3 2/4] regulator: axp20x: duplicate the MFD axp20x-rsb code
From: Jean-Francois Moine @ 2016-09-22 17:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1474621107.git.moinejf@free.fr>
The axp20x rsb driver handles many different devices.
Duplicating its code in a generic regulator driver permits
to probe/remove individual devices.
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
drivers/regulator/axp-regulator.c | 39 +++++++++++++++++++++++++++++++++++++++
drivers/regulator/axp-regulator.h | 6 ++++++
2 files changed, 45 insertions(+)
diff --git a/drivers/regulator/axp-regulator.c b/drivers/regulator/axp-regulator.c
index 0d7adb6..17943fb 100644
--- a/drivers/regulator/axp-regulator.c
+++ b/drivers/regulator/axp-regulator.c
@@ -303,6 +303,45 @@ int axp_regulator_create(struct device *dev,
}
EXPORT_SYMBOL_GPL(axp_regulator_create);
+/* probe/remove RSB devices */
+int axp_rsb_probe(struct sunxi_rsb_device *rdev,
+ struct axp20x_dev *axp20x,
+ const struct axp_cfg *axp_cfg)
+{
+ int ret;
+
+ axp20x->dev = &rdev->dev;
+ axp20x->irq = rdev->irq;
+ dev_set_drvdata(&rdev->dev, axp20x);
+
+ ret = axp20x_match_device(axp20x);
+ if (ret)
+ return ret;
+
+ axp20x->regmap = devm_regmap_init_sunxi_rsb(rdev,
+ axp20x->regmap_cfg);
+ if (IS_ERR(axp20x->regmap)) {
+ ret = PTR_ERR(axp20x->regmap);
+ dev_err(&rdev->dev, "regmap init failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = axp20x_device_probe(axp20x);
+ if (ret < 0)
+ return ret;
+
+ return axp_regulator_create(&rdev->dev, axp_cfg);
+}
+EXPORT_SYMBOL_GPL(axp_rsb_probe);
+
+int axp_rsb_remove(struct sunxi_rsb_device *rdev)
+{
+ struct axp20x_dev *axp20x = sunxi_rsb_device_get_drvdata(rdev);
+
+ return axp20x_device_remove(axp20x);
+}
+EXPORT_SYMBOL_GPL(axp_rsb_remove);
+
MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
MODULE_DESCRIPTION("Regulator Module for AXP PMIC");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/regulator/axp-regulator.h b/drivers/regulator/axp-regulator.h
index 0adf1b0..085eaa0 100644
--- a/drivers/regulator/axp-regulator.h
+++ b/drivers/regulator/axp-regulator.h
@@ -124,4 +124,10 @@ struct axp_cfg {
int axp_regulator_create(struct device *dev,
const struct axp_cfg *axp_cfg);
+struct sunxi_rsb_device;
+int axp_rsb_probe(struct sunxi_rsb_device *rdev,
+ struct axp20x_dev *axp20x,
+ const struct axp_cfg *axp_cfg);
+int axp_rsb_remove(struct sunxi_rsb_device *rdev);
+
#endif /* __AXP_REGULATOR_H__ */
--
2.10.0
^ permalink raw reply related
* [PATCH v2] musb: Export musb_root_disconnect for use in modules
From: Mark Brown @ 2016-09-22 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922133016.GE3970@uda0271908>
On Thu, Sep 22, 2016 at 08:30:16AM -0500, Bin Liu wrote:
> On Wed, Sep 21, 2016 at 03:51:33PM -0500, Bin Liu wrote:
> > Applied. Thanks.
> Removed it from my tree, since Greg already picked it.
It's not showing in today's -next...
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^ permalink raw reply
* [PATCH] PCI: rockchip: fix uninitialized variable use
From: Brian Norris @ 2016-09-22 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922094018.2138640-1-arnd@arndb.de>
On Thu, Sep 22, 2016 at 11:39:59AM +0200, Arnd Bergmann wrote:
> The newly added pcie-rockchip driver fails to initialize the
> io_size variable if the DT doesn't provide ranges for the PCI
> I/O space, as found by building it with -Wmaybe-uninitialized:
>
> drivers/pci/host/pcie-rockchip.c: In function 'rockchip_pcie_probe':
> drivers/pci/host/pcie-rockchip.c:1007:6: warning: 'io_size' may be used uninitialized in this function [-Wmaybe-uninitialized]
>
> This adds an appropriate initialization immediately in front of
> the loop, so the io_size is zero as expected afterwards for that
> case.
>
> Fixes: abe17181b16f ("PCI: rockchip: Add Rockchip PCIe controller support")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/pci/host/pcie-rockchip.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index c3593e633ccd..8bedc1e1ef80 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -1078,6 +1078,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> goto err_vpcie;
>
> /* Get the I/O and memory ranges from DT */
> + io_size = 0;
> resource_list_for_each_entry(win, &res) {
> switch (resource_type(win->res)) {
> case IORESOURCE_IO:
I feel like we've fixed this one before, but then it's been refactored
many times along the way...
Reviewed-by: Brian Norris <briannorris@chromium.org>
^ permalink raw reply
* [PATCH] arm64: Call numa_store_cpu_info() earlier.
From: Catalin Marinas @ 2016-09-22 17:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474397195-16520-1-git-send-email-ddaney.cavm@gmail.com>
On Tue, Sep 20, 2016 at 11:46:35AM -0700, David Daney wrote:
> From: David Daney <david.daney@cavium.com>
>
> The wq_numa_init() function makes a private CPU to node map by calling
> cpu_to_node() early in the boot process, before the non-boot CPUs are
> brought online. Since the default implementation of cpu_to_node()
> returns zero for CPUs that have never been brought online, the
> workqueue system's view is that *all* CPUs are on node zero.
>
> When the unbound workqueue for a non-zero node is created, the
> tsk_cpus_allowed() for the worker threads is the empty set because
> there are, in the view of the workqueue system, no CPUs on non-zero
> nodes. The code in try_to_wake_up() using this empty cpumask ends up
> using the cpumask empty set value of NR_CPUS as an index into the
> per-CPU area pointer array, and gets garbage as it is one past the end
> of the array. This results in:
Queued for 4.8. Thanks.
--
Catalin
^ permalink raw reply
* [PATCH v3 1/4] regulator: axp20x: move device independant parts to new files
From: Jean-Francois Moine @ 2016-09-22 17:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1474621107.git.moinejf@free.fr>
The axp20x driver contains device specific and device independant parts.
This patch moves the independant parts to new .c/.h files.
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
drivers/regulator/Makefile | 2 +-
drivers/regulator/axp-regulator.c | 308 ++++++++++++++++++++++++++
drivers/regulator/axp-regulator.h | 127 +++++++++++
drivers/regulator/axp20x-regulator.c | 415 +++--------------------------------
4 files changed, 464 insertions(+), 388 deletions(-)
create mode 100644 drivers/regulator/axp-regulator.c
create mode 100644 drivers/regulator/axp-regulator.h
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 2142a5d..225a026 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -21,7 +21,7 @@ obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
obj-$(CONFIG_REGULATOR_ARIZONA) += arizona-micsupp.o arizona-ldo1.o
obj-$(CONFIG_REGULATOR_AS3711) += as3711-regulator.o
obj-$(CONFIG_REGULATOR_AS3722) += as3722-regulator.o
-obj-$(CONFIG_REGULATOR_AXP20X) += axp20x-regulator.o
+obj-$(CONFIG_REGULATOR_AXP20X) += axp20x-regulator.o axp-regulator.o
obj-$(CONFIG_REGULATOR_BCM590XX) += bcm590xx-regulator.o
obj-$(CONFIG_REGULATOR_DA903X) += da903x.o
obj-$(CONFIG_REGULATOR_DA9052) += da9052-regulator.o
diff --git a/drivers/regulator/axp-regulator.c b/drivers/regulator/axp-regulator.c
new file mode 100644
index 0000000..0d7adb6
--- /dev/null
+++ b/drivers/regulator/axp-regulator.c
@@ -0,0 +1,308 @@
+/*
+ * AXP regulators driver
+ *
+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
+ * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/mfd/axp20x.h>
+#include <linux/sunxi-rsb.h>
+
+#include "axp-regulator.h"
+
+#define AXP20X_WORKMODE_DCDC2_MASK BIT(2)
+#define AXP20X_WORKMODE_DCDC3_MASK BIT(1)
+#define AXP22X_WORKMODE_DCDCX_MASK(x) BIT(x)
+
+#define AXP20X_FREQ_DCDC_MASK 0x0f
+
+#define AXP22X_MISC_N_VBUSEN_FUNC BIT(4)
+
+const struct regulator_ops axp_ops_fixed = {
+ .list_voltage = regulator_list_voltage_linear,
+};
+EXPORT_SYMBOL_GPL(axp_ops_fixed);
+
+const struct regulator_ops axp_ops_range = {
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .list_voltage = regulator_list_voltage_linear_range,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+};
+EXPORT_SYMBOL_GPL(axp_ops_range);
+
+const struct regulator_ops axp_ops = {
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .list_voltage = regulator_list_voltage_linear,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+};
+EXPORT_SYMBOL_GPL(axp_ops);
+
+const struct regulator_ops axp_ops_sw = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+};
+EXPORT_SYMBOL_GPL(axp_ops_sw);
+
+static const struct regulator_desc axp22x_drivevbus_regulator = {
+ .name = "drivevbus",
+ .supply_name = "drivevbus",
+ .of_match = of_match_ptr("drivevbus"),
+ .regulators_node = of_match_ptr("regulators"),
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ .enable_reg = AXP20X_VBUS_IPSOUT_MGMT,
+ .enable_mask = BIT(2),
+ .ops = &axp_ops_sw,
+};
+
+static int axp_set_dcdc_freq(struct device *dev,
+ u32 dcdcfreq)
+{
+ struct axp20x_dev *axp20x = dev_get_drvdata(dev);
+ unsigned int reg = AXP20X_DCDC_FREQ;
+ u32 min, max, def, step;
+
+ switch (axp20x->variant) {
+ case AXP202_ID:
+ case AXP209_ID:
+ min = 750;
+ max = 1875;
+ def = 1500;
+ step = 75;
+ break;
+ case AXP806_ID:
+ /*
+ * AXP806 DCDC work frequency setting has the same range and
+ * step as AXP22X, but at a different register.
+ * Fall through to the check below.
+ * (See include/linux/mfd/axp20x.h)
+ */
+ reg = AXP806_DCDC_FREQ_CTRL;
+ case AXP221_ID:
+ case AXP223_ID:
+ case AXP809_ID:
+ min = 1800;
+ max = 4050;
+ def = 3000;
+ step = 150;
+ break;
+ default:
+ dev_err(dev,
+ "Setting DCDC frequency for unsupported AXP variant\n");
+ return -EINVAL;
+ }
+
+ if (dcdcfreq == 0)
+ dcdcfreq = def;
+
+ if (dcdcfreq < min) {
+ dcdcfreq = min;
+ dev_warn(dev, "DCDC frequency too low. Set to %ukHz\n",
+ min);
+ }
+
+ if (dcdcfreq > max) {
+ dcdcfreq = max;
+ dev_warn(dev, "DCDC frequency too high. Set to %ukHz\n",
+ max);
+ }
+
+ dcdcfreq = (dcdcfreq - min) / step;
+
+ return regmap_update_bits(axp20x->regmap, reg,
+ AXP20X_FREQ_DCDC_MASK, dcdcfreq);
+}
+
+static int axp_regulator_parse_dt(struct device *dev)
+{
+ struct device_node *np, *regulators;
+ int ret;
+ u32 dcdcfreq = 0;
+
+ np = of_node_get(dev->of_node);
+ if (!np)
+ return 0;
+
+ regulators = of_get_child_by_name(np, "regulators");
+ if (!regulators) {
+ dev_warn(dev, "regulators node not found\n");
+ } else {
+ of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
+ ret = axp_set_dcdc_freq(dev, dcdcfreq);
+ if (ret < 0) {
+ dev_err(dev, "Error setting dcdc frequency: %d\n", ret);
+ return ret;
+ }
+
+ of_node_put(regulators);
+ }
+
+ return 0;
+}
+
+static int axp_set_dcdc_workmode(struct regulator_dev *rdev,
+ int id, u32 workmode)
+{
+ struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
+ unsigned int reg = AXP20X_DCDC_MODE;
+ unsigned int mask;
+
+ switch (axp20x->variant) {
+ case AXP202_ID:
+ case AXP209_ID:
+ if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
+ return -EINVAL;
+
+ mask = AXP20X_WORKMODE_DCDC2_MASK;
+ if (id == AXP20X_DCDC3)
+ mask = AXP20X_WORKMODE_DCDC3_MASK;
+
+ workmode <<= ffs(mask) - 1;
+ break;
+
+ case AXP806_ID:
+ reg = AXP806_DCDC_MODE_CTRL2;
+ /*
+ * AXP806 DCDC regulator IDs have the same range as AXP22X.
+ * Fall through to the check below.
+ * (See include/linux/mfd/axp20x.h)
+ */
+ case AXP221_ID:
+ case AXP223_ID:
+ case AXP809_ID:
+ if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
+ return -EINVAL;
+
+ mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
+ workmode <<= id - AXP22X_DCDC1;
+ break;
+
+ default:
+ /* should not happen */
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ return regmap_update_bits(rdev->regmap, reg, mask, workmode);
+}
+
+/* create the regulators */
+int axp_regulator_create(struct device *dev,
+ const struct axp_cfg *axp_cfg)
+{
+ struct regulator_dev *rdev;
+ struct axp20x_dev *axp20x = dev_get_drvdata(dev);
+ struct regulator_config config = {
+ .dev = dev,
+ .regmap = axp20x->regmap,
+ .driver_data = axp20x,
+ };
+ int ret, i;
+ u32 workmode;
+ const char *dcdc1_name = NULL;
+ const char *dcdc5_name = NULL;
+
+ /* This only sets the dcdc freq. Ignore any errors */
+ axp_regulator_parse_dt(dev);
+
+ for (i = 0; i < axp_cfg->nregulators; i++) {
+ const struct regulator_desc *desc = &axp_cfg->regulators[i];
+ struct regulator_desc *new_desc;
+
+ if (axp_cfg->skip_bitmap & (1 << i))
+ continue;
+
+ /*
+ * Regulators DC1SW and DC5LDO are connected internally,
+ * so we have to handle their supply names separately.
+ *
+ * We always register the regulators in proper sequence,
+ * so the supply names are correctly read. See the last
+ * part of this loop to see where we save the DT defined
+ * name.
+ */
+ if (i == axp_cfg->dc1sw_ix && dcdc1_name) {
+ new_desc = devm_kzalloc(dev, sizeof(*desc),
+ GFP_KERNEL);
+ *new_desc = *desc;
+ new_desc->supply_name = dcdc1_name;
+ desc = new_desc;
+ }
+
+ if (i == axp_cfg->dc5ldo_ix && dcdc5_name) {
+ new_desc = devm_kzalloc(dev, sizeof(*desc),
+ GFP_KERNEL);
+ *new_desc = *desc;
+ new_desc->supply_name = dcdc5_name;
+ desc = new_desc;
+ }
+
+ rdev = devm_regulator_register(dev, desc, &config);
+ if (IS_ERR(rdev)) {
+ dev_err(dev, "Failed to register %s\n",
+ axp_cfg->regulators[i].name);
+
+ return PTR_ERR(rdev);
+ }
+
+ ret = of_property_read_u32(rdev->dev.of_node,
+ "x-powers,dcdc-workmode",
+ &workmode);
+ if (!ret) {
+ if (axp_set_dcdc_workmode(rdev, i, workmode))
+ dev_err(dev, "Failed to set workmode on %s\n",
+ rdev->desc->name);
+ }
+
+ /*
+ * Save AXP22X DCDC1 / DCDC5 regulator names for later.
+ */
+ if (i == axp_cfg->dcdc1_ix)
+ of_property_read_string(rdev->dev.of_node,
+ "regulator-name",
+ &dcdc1_name);
+ if (i == axp_cfg->dcdc5_ix)
+ of_property_read_string(rdev->dev.of_node,
+ "regulator-name",
+ &dcdc5_name);
+ }
+
+ if (axp_cfg->drivevbus) {
+ /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
+ regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
+ AXP22X_MISC_N_VBUSEN_FUNC, 0);
+ rdev = devm_regulator_register(dev,
+ &axp22x_drivevbus_regulator,
+ &config);
+ if (IS_ERR(rdev)) {
+ dev_err(dev, "Failed to register drivevbus\n");
+ return PTR_ERR(rdev);
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(axp_regulator_create);
+
+MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
+MODULE_DESCRIPTION("Regulator Module for AXP PMIC");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/regulator/axp-regulator.h b/drivers/regulator/axp-regulator.h
new file mode 100644
index 0000000..0adf1b0
--- /dev/null
+++ b/drivers/regulator/axp-regulator.h
@@ -0,0 +1,127 @@
+#ifndef __AXP_REGULATOR_H__
+#define __AXP_REGULATOR_H__
+/*
+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#define AXP20X_IO_ENABLED 0x03
+#define AXP20X_IO_DISABLED 0x07
+
+#define AXP22X_IO_ENABLED 0x03
+#define AXP22X_IO_DISABLED 0x04
+
+#define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, _enable_val, _disable_val) \
+ [_family##_##_id] = { \
+ .name = (_match), \
+ .supply_name = (_supply), \
+ .of_match = of_match_ptr(_match), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .type = REGULATOR_VOLTAGE, \
+ .id = _family##_##_id, \
+ .n_voltages = (((_max) - (_min)) / (_step) + 1), \
+ .owner = THIS_MODULE, \
+ .min_uV = (_min) * 1000, \
+ .uV_step = (_step) * 1000, \
+ .vsel_reg = (_vreg), \
+ .vsel_mask = (_vmask), \
+ .enable_reg = (_ereg), \
+ .enable_mask = (_emask), \
+ .enable_val = (_enable_val), \
+ .disable_val = (_disable_val), \
+ .ops = &axp_ops, \
+ }
+
+#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask) \
+ [_family##_##_id] = { \
+ .name = (_match), \
+ .supply_name = (_supply), \
+ .of_match = of_match_ptr(_match), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .type = REGULATOR_VOLTAGE, \
+ .id = _family##_##_id, \
+ .n_voltages = (((_max) - (_min)) / (_step) + 1), \
+ .owner = THIS_MODULE, \
+ .min_uV = (_min) * 1000, \
+ .uV_step = (_step) * 1000, \
+ .vsel_reg = (_vreg), \
+ .vsel_mask = (_vmask), \
+ .enable_reg = (_ereg), \
+ .enable_mask = (_emask), \
+ .ops = &axp_ops, \
+ }
+
+#define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
+ [_family##_##_id] = { \
+ .name = (_match), \
+ .supply_name = (_supply), \
+ .of_match = of_match_ptr(_match), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .type = REGULATOR_VOLTAGE, \
+ .id = _family##_##_id, \
+ .owner = THIS_MODULE, \
+ .enable_reg = (_ereg), \
+ .enable_mask = (_emask), \
+ .ops = &axp_ops_sw, \
+ }
+
+#define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \
+ [_family##_##_id] = { \
+ .name = (_match), \
+ .supply_name = (_supply), \
+ .of_match = of_match_ptr(_match), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .type = REGULATOR_VOLTAGE, \
+ .id = _family##_##_id, \
+ .n_voltages = 1, \
+ .owner = THIS_MODULE, \
+ .min_uV = (_volt) * 1000, \
+ .ops = &axp_ops_fixed \
+ }
+
+#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
+ _vreg, _vmask, _ereg, _emask) \
+ [_family##_##_id] = { \
+ .name = (_match), \
+ .supply_name = (_supply), \
+ .of_match = of_match_ptr(_match), \
+ .regulators_node = of_match_ptr("regulators"), \
+ .type = REGULATOR_VOLTAGE, \
+ .id = _family##_##_id, \
+ .n_voltages = (_n_voltages), \
+ .owner = THIS_MODULE, \
+ .vsel_reg = (_vreg), \
+ .vsel_mask = (_vmask), \
+ .enable_reg = (_ereg), \
+ .enable_mask = (_emask), \
+ .linear_ranges = (_ranges), \
+ .n_linear_ranges = ARRAY_SIZE(_ranges), \
+ .ops = &axp_ops_range, \
+ }
+
+extern const struct regulator_ops axp_ops;
+extern const struct regulator_ops axp_ops_fixed;
+extern const struct regulator_ops axp_ops_range;
+extern const struct regulator_ops axp_ops_sw;
+
+struct axp_cfg {
+ const struct regulator_desc *regulators;
+ u8 nregulators;
+ s8 dcdc1_ix;
+ s8 dcdc5_ix;
+ s8 dc1sw_ix;
+ s8 dc5ldo_ix;
+ u32 skip_bitmap;
+ bool drivevbus;
+};
+
+int axp_regulator_create(struct device *dev,
+ const struct axp_cfg *axp_cfg);
+
+#endif /* __AXP_REGULATOR_H__ */
diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
index 244ddc3..9dd9ca3 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -24,137 +24,7 @@
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>
-#define AXP20X_IO_ENABLED 0x03
-#define AXP20X_IO_DISABLED 0x07
-
-#define AXP22X_IO_ENABLED 0x03
-#define AXP22X_IO_DISABLED 0x04
-
-#define AXP20X_WORKMODE_DCDC2_MASK BIT(2)
-#define AXP20X_WORKMODE_DCDC3_MASK BIT(1)
-#define AXP22X_WORKMODE_DCDCX_MASK(x) BIT(x)
-
-#define AXP20X_FREQ_DCDC_MASK 0x0f
-
-#define AXP22X_MISC_N_VBUSEN_FUNC BIT(4)
-
-#define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
- _vmask, _ereg, _emask, _enable_val, _disable_val) \
- [_family##_##_id] = { \
- .name = (_match), \
- .supply_name = (_supply), \
- .of_match = of_match_ptr(_match), \
- .regulators_node = of_match_ptr("regulators"), \
- .type = REGULATOR_VOLTAGE, \
- .id = _family##_##_id, \
- .n_voltages = (((_max) - (_min)) / (_step) + 1), \
- .owner = THIS_MODULE, \
- .min_uV = (_min) * 1000, \
- .uV_step = (_step) * 1000, \
- .vsel_reg = (_vreg), \
- .vsel_mask = (_vmask), \
- .enable_reg = (_ereg), \
- .enable_mask = (_emask), \
- .enable_val = (_enable_val), \
- .disable_val = (_disable_val), \
- .ops = &axp20x_ops, \
- }
-
-#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
- _vmask, _ereg, _emask) \
- [_family##_##_id] = { \
- .name = (_match), \
- .supply_name = (_supply), \
- .of_match = of_match_ptr(_match), \
- .regulators_node = of_match_ptr("regulators"), \
- .type = REGULATOR_VOLTAGE, \
- .id = _family##_##_id, \
- .n_voltages = (((_max) - (_min)) / (_step) + 1), \
- .owner = THIS_MODULE, \
- .min_uV = (_min) * 1000, \
- .uV_step = (_step) * 1000, \
- .vsel_reg = (_vreg), \
- .vsel_mask = (_vmask), \
- .enable_reg = (_ereg), \
- .enable_mask = (_emask), \
- .ops = &axp20x_ops, \
- }
-
-#define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
- [_family##_##_id] = { \
- .name = (_match), \
- .supply_name = (_supply), \
- .of_match = of_match_ptr(_match), \
- .regulators_node = of_match_ptr("regulators"), \
- .type = REGULATOR_VOLTAGE, \
- .id = _family##_##_id, \
- .owner = THIS_MODULE, \
- .enable_reg = (_ereg), \
- .enable_mask = (_emask), \
- .ops = &axp20x_ops_sw, \
- }
-
-#define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \
- [_family##_##_id] = { \
- .name = (_match), \
- .supply_name = (_supply), \
- .of_match = of_match_ptr(_match), \
- .regulators_node = of_match_ptr("regulators"), \
- .type = REGULATOR_VOLTAGE, \
- .id = _family##_##_id, \
- .n_voltages = 1, \
- .owner = THIS_MODULE, \
- .min_uV = (_volt) * 1000, \
- .ops = &axp20x_ops_fixed \
- }
-
-#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
- _vreg, _vmask, _ereg, _emask) \
- [_family##_##_id] = { \
- .name = (_match), \
- .supply_name = (_supply), \
- .of_match = of_match_ptr(_match), \
- .regulators_node = of_match_ptr("regulators"), \
- .type = REGULATOR_VOLTAGE, \
- .id = _family##_##_id, \
- .n_voltages = (_n_voltages), \
- .owner = THIS_MODULE, \
- .vsel_reg = (_vreg), \
- .vsel_mask = (_vmask), \
- .enable_reg = (_ereg), \
- .enable_mask = (_emask), \
- .linear_ranges = (_ranges), \
- .n_linear_ranges = ARRAY_SIZE(_ranges), \
- .ops = &axp20x_ops_range, \
- }
-
-static struct regulator_ops axp20x_ops_fixed = {
- .list_voltage = regulator_list_voltage_linear,
-};
-
-static struct regulator_ops axp20x_ops_range = {
- .set_voltage_sel = regulator_set_voltage_sel_regmap,
- .get_voltage_sel = regulator_get_voltage_sel_regmap,
- .list_voltage = regulator_list_voltage_linear_range,
- .enable = regulator_enable_regmap,
- .disable = regulator_disable_regmap,
- .is_enabled = regulator_is_enabled_regmap,
-};
-
-static struct regulator_ops axp20x_ops = {
- .set_voltage_sel = regulator_set_voltage_sel_regmap,
- .get_voltage_sel = regulator_get_voltage_sel_regmap,
- .list_voltage = regulator_list_voltage_linear,
- .enable = regulator_enable_regmap,
- .disable = regulator_disable_regmap,
- .is_enabled = regulator_is_enabled_regmap,
-};
-
-static struct regulator_ops axp20x_ops_sw = {
- .enable = regulator_enable_regmap,
- .disable = regulator_disable_regmap,
- .is_enabled = regulator_is_enabled_regmap,
-};
+#include "axp-regulator.h"
static const struct regulator_linear_range axp20x_ldo4_ranges[] = {
REGULATOR_LINEAR_RANGE(1250000, 0x0, 0x0, 0),
@@ -232,18 +102,6 @@ static const struct regulator_desc axp22x_regulators[] = {
AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
};
-static const struct regulator_desc axp22x_drivevbus_regulator = {
- .name = "drivevbus",
- .supply_name = "drivevbus",
- .of_match = of_match_ptr("drivevbus"),
- .regulators_node = of_match_ptr("regulators"),
- .type = REGULATOR_VOLTAGE,
- .owner = THIS_MODULE,
- .enable_reg = AXP20X_VBUS_IPSOUT_MGMT,
- .enable_mask = BIT(2),
- .ops = &axp20x_ops_sw,
-};
-
static const struct regulator_linear_range axp806_dcdca_ranges[] = {
REGULATOR_LINEAR_RANGE(600000, 0x0, 0x32, 10000),
REGULATOR_LINEAR_RANGE(1120000, 0x33, 0x47, 20000),
@@ -347,135 +205,6 @@ static const struct regulator_desc axp809_regulators[] = {
AXP_DESC_SW(AXP809, SW, "sw", "swin", AXP22X_PWR_OUT_CTRL2, BIT(6)),
};
-static int axp20x_set_dcdc_freq(struct device *dev, u32 dcdcfreq)
-{
- struct axp20x_dev *axp20x = dev_get_drvdata(dev);
- unsigned int reg = AXP20X_DCDC_FREQ;
- u32 min, max, def, step;
-
- switch (axp20x->variant) {
- case AXP202_ID:
- case AXP209_ID:
- min = 750;
- max = 1875;
- def = 1500;
- step = 75;
- break;
- case AXP806_ID:
- /*
- * AXP806 DCDC work frequency setting has the same range and
- * step as AXP22X, but at a different register.
- * Fall through to the check below.
- * (See include/linux/mfd/axp20x.h)
- */
- reg = AXP806_DCDC_FREQ_CTRL;
- case AXP221_ID:
- case AXP223_ID:
- case AXP809_ID:
- min = 1800;
- max = 4050;
- def = 3000;
- step = 150;
- break;
- default:
- dev_err(dev,
- "Setting DCDC frequency for unsupported AXP variant\n");
- return -EINVAL;
- }
-
- if (dcdcfreq == 0)
- dcdcfreq = def;
-
- if (dcdcfreq < min) {
- dcdcfreq = min;
- dev_warn(dev, "DCDC frequency too low. Set to %ukHz\n",
- min);
- }
-
- if (dcdcfreq > max) {
- dcdcfreq = max;
- dev_warn(dev, "DCDC frequency too high. Set to %ukHz\n",
- max);
- }
-
- dcdcfreq = (dcdcfreq - min) / step;
-
- return regmap_update_bits(axp20x->regmap, reg,
- AXP20X_FREQ_DCDC_MASK, dcdcfreq);
-}
-
-static int axp20x_regulator_parse_dt(struct device *dev)
-{
- struct device_node *np, *regulators;
- int ret;
- u32 dcdcfreq = 0;
-
- np = of_node_get(dev->of_node);
- if (!np)
- return 0;
-
- regulators = of_get_child_by_name(np, "regulators");
- if (!regulators) {
- dev_warn(dev, "regulators node not found\n");
- } else {
- of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
- ret = axp20x_set_dcdc_freq(dev, dcdcfreq);
- if (ret < 0) {
- dev_err(dev, "Error setting dcdc frequency: %d\n", ret);
- return ret;
- }
-
- of_node_put(regulators);
- }
-
- return 0;
-}
-
-static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
-{
- struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
- unsigned int reg = AXP20X_DCDC_MODE;
- unsigned int mask;
-
- switch (axp20x->variant) {
- case AXP202_ID:
- case AXP209_ID:
- if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
- return -EINVAL;
-
- mask = AXP20X_WORKMODE_DCDC2_MASK;
- if (id == AXP20X_DCDC3)
- mask = AXP20X_WORKMODE_DCDC3_MASK;
-
- workmode <<= ffs(mask) - 1;
- break;
-
- case AXP806_ID:
- reg = AXP806_DCDC_MODE_CTRL2;
- /*
- * AXP806 DCDC regulator IDs have the same range as AXP22X.
- * Fall through to the check below.
- * (See include/linux/mfd/axp20x.h)
- */
- case AXP221_ID:
- case AXP223_ID:
- case AXP809_ID:
- if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
- return -EINVAL;
-
- mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
- workmode <<= id - AXP22X_DCDC1;
- break;
-
- default:
- /* should not happen */
- WARN_ON(1);
- return -EINVAL;
- }
-
- return regmap_update_bits(rdev->regmap, reg, mask, workmode);
-}
-
/*
* This function checks which regulators are part of poly-phase
* output setups based on the registers settings.
@@ -500,60 +229,51 @@ static u32 axp20x_polyphase_slave(struct axp20x_dev *axp20x)
static int axp20x_regulator_probe(struct platform_device *pdev)
{
struct device *dev = pdev->dev.parent;
- struct regulator_dev *rdev;
struct axp20x_dev *axp20x = dev_get_drvdata(dev);
- const struct regulator_desc *regulators;
- struct regulator_config config = {
- .dev = dev,
- .regmap = axp20x->regmap,
- .driver_data = axp20x,
- };
- int ret, i, nregulators;
- u32 workmode;
- const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
- const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
- s8 dcdc1_ix = -1;
- s8 dcdc5_ix = -1;
- s8 dc1sw_ix = -1;
- s8 dc5ldo_ix = -1;
- bool drivevbus = false;
- u32 skip_bitmap = 0;
+ struct axp_cfg axp_cfg;
+
+ axp_cfg.dcdc1_ix = -1;
+ axp_cfg.dcdc5_ix = -1;
+ axp_cfg.dc1sw_ix = -1;
+ axp_cfg.dc5ldo_ix = -1;
+ axp_cfg.drivevbus = false;
+ axp_cfg.skip_bitmap = 0;
switch (axp20x->variant) {
case AXP202_ID:
case AXP209_ID:
- regulators = axp20x_regulators;
- nregulators = AXP20X_REG_ID_MAX;
+ axp_cfg.regulators = axp20x_regulators;
+ axp_cfg.nregulators = AXP20X_REG_ID_MAX;
break;
case AXP221_ID:
case AXP223_ID:
- regulators = axp22x_regulators;
- nregulators = AXP22X_REG_ID_MAX;
- dcdc1_ix = AXP22X_DCDC1;
- dcdc5_ix = AXP22X_DCDC5;
- dc1sw_ix = AXP22X_DC1SW;
- dc5ldo_ix = AXP22X_DC5LDO;
- drivevbus = of_property_read_bool(dev->of_node,
+ axp_cfg.regulators = axp22x_regulators;
+ axp_cfg.nregulators = AXP22X_REG_ID_MAX;
+ axp_cfg.dcdc1_ix = AXP22X_DCDC1;
+ axp_cfg.dcdc5_ix = AXP22X_DCDC5;
+ axp_cfg.dc1sw_ix = AXP22X_DC1SW;
+ axp_cfg.dc5ldo_ix = AXP22X_DC5LDO;
+ axp_cfg.drivevbus = of_property_read_bool(dev->of_node,
"x-powers,drive-vbus-en");
break;
case AXP806_ID:
- regulators = axp806_regulators;
- nregulators = AXP806_REG_ID_MAX;
+ axp_cfg.regulators = axp806_regulators;
+ axp_cfg.nregulators = AXP806_REG_ID_MAX;
/*
* The regulators which are slave in a poly-phase setup
* are skipped, as their controls are bound to the master
* regulator and won't work.
*/
- skip_bitmap |= axp20x_polyphase_slave(axp20x);
+ axp_cfg.skip_bitmap |= axp20x_polyphase_slave(axp20x);
break;
case AXP809_ID:
- regulators = axp809_regulators;
- nregulators = AXP809_REG_ID_MAX;
- dcdc1_ix = AXP809_DCDC1;
- dcdc5_ix = AXP809_DCDC5;
- dc1sw_ix = AXP809_DC1SW;
- dc5ldo_ix = AXP809_DC5LDO;
+ axp_cfg.regulators = axp809_regulators;
+ axp_cfg.nregulators = AXP809_REG_ID_MAX;
+ axp_cfg.dcdc1_ix = AXP809_DCDC1;
+ axp_cfg.dcdc5_ix = AXP809_DCDC5;
+ axp_cfg.dc1sw_ix = AXP809_DC1SW;
+ axp_cfg.dc5ldo_ix = AXP809_DC5LDO;
break;
default:
dev_err(dev, "Unsupported AXP variant: %ld\n",
@@ -561,86 +281,7 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
return -EINVAL;
}
- /* This only sets the dcdc freq. Ignore any errors */
- axp20x_regulator_parse_dt(dev);
-
- for (i = 0; i < nregulators; i++) {
- const struct regulator_desc *desc = ®ulators[i];
- struct regulator_desc *new_desc;
-
- if (skip_bitmap & (1 << i))
- continue;
-
- /*
- * Regulators DC1SW and DC5LDO are connected internally,
- * so we have to handle their supply names separately.
- *
- * We always register the regulators in proper sequence,
- * so the supply names are correctly read. See the last
- * part of this loop to see where we save the DT defined
- * name.
- */
- if (i == dc1sw_ix && dcdc1_name) {
- new_desc = devm_kzalloc(dev, sizeof(*desc),
- GFP_KERNEL);
- *new_desc = regulators[i];
- new_desc->supply_name = dcdc1_name;
- desc = new_desc;
- }
-
- if (i == dc5ldo_ix && dcdc5_name) {
- new_desc = devm_kzalloc(dev, sizeof(*desc),
- GFP_KERNEL);
- *new_desc = regulators[i];
- new_desc->supply_name = dcdc5_name;
- desc = new_desc;
- }
-
- rdev = devm_regulator_register(dev, desc, &config);
- if (IS_ERR(rdev)) {
- dev_err(dev, "Failed to register %s\n",
- regulators[i].name);
-
- return PTR_ERR(rdev);
- }
-
- ret = of_property_read_u32(rdev->dev.of_node,
- "x-powers,dcdc-workmode",
- &workmode);
- if (!ret) {
- if (axp20x_set_dcdc_workmode(rdev, i, workmode))
- dev_err(dev, "Failed to set workmode on %s\n",
- rdev->desc->name);
- }
-
- /*
- * Save AXP22X DCDC1 / DCDC5 regulator names for later.
- */
- if (i == dcdc1_ix)
- of_property_read_string(rdev->dev.of_node,
- "regulator-name",
- &dcdc1_name);
-
- if (i == dcdc5_ix)
- of_property_read_string(rdev->dev.of_node,
- "regulator-name",
- &dcdc5_name);
- }
-
- if (drivevbus) {
- /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
- regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
- AXP22X_MISC_N_VBUSEN_FUNC, 0);
- rdev = devm_regulator_register(dev,
- &axp22x_drivevbus_regulator,
- &config);
- if (IS_ERR(rdev)) {
- dev_err(dev, "Failed to register drivevbus\n");
- return PTR_ERR(rdev);
- }
- }
-
- return 0;
+ return axp_regulator_create(dev, &axp_cfg);
}
static struct platform_driver axp20x_regulator_driver = {
--
2.10.0
^ permalink raw reply related
* [PATCH 5/5] arm64: Add uprobe support
From: Catalin Marinas @ 2016-09-22 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922032328.GB29470@localhost.localdomain>
On Thu, Sep 22, 2016 at 08:53:28AM +0530, Pratyush Anand wrote:
> On 21/09/2016:06:04:04 PM, Catalin Marinas wrote:
> > On Wed, Sep 21, 2016 at 04:30:47PM +0530, Pratyush Anand wrote:
> > > On 20/09/2016:05:59:46 PM, Catalin Marinas wrote:
> > > > > +int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
> > > > > + unsigned long addr)
> > > > > +{
> > > > > + probe_opcode_t insn;
> > > > > +
> > > > > + /* TODO: Currently we do not support AARCH32 instruction probing */
> > > >
> > > > Is there a way to check (not necessarily in this file) that we don't
> > > > probe 32-bit tasks?
> > >
> > > - Well, I do not have complete idea about it that, how it can be done. I think
> > > we can not check that just by looking a single bit in an instruction.
> > > My understanding is that, we can only know about it when we are executing the
> > > instruction, by reading pstate, but that would not be useful for uprobe
> > > instruction analysis.
> > >
> > > I hope, instruction encoding for aarch32 and aarch64 are different, and by
> > > analyzing for all types of aarch32 instructions, we will be able to decide
> > > that whether instruction is 32 bit trace-able or not. Accordingly, we can use
> > > either BRK or BKPT instruction for breakpoint generation.
> >
> > We may have some unrelated instruction encoding overlapping but I
> > haven't checked. I was more thinking about whether we know which task is
> > being probed and check is_compat_task() or maybe using
> > compat_user_mode(regs).
>
> I had thought of this, but problem is that we might not have task in existence
> when we enable uprobes. For example: Lets say we are inserting a trace probe at
> offset 0x690 in a executable binary.
>
> echo "p test:0x690" > /sys/kernel/debug/tracing/uprobe_events
> echo 1 > /sys/kernel/debug/tracing/events/uprobes/enable
>
> In the 'enable' step, it is decided that whether instruction is traceable or
> not.
>
> (1) But at this point 'test' executable might not be running.
> (2) Even if it is running, is_compat_task() or compat_user_mode() might not be
> usable, as they work with 'current' task.
What I find strange is that uprobes allows you to insert a breakpoint
instruction that's not even compatible with the task (so it would
SIGILL rather than generate a debug exception).
> What I was thinking that, let it go with 'TODO' as of now.
Only that I don't have any guarantee that someone is going to fix it ;).
As a quick workaround you could check mm->task_size > TASK_SIZE_32 in
the arch_uprobe_analyze_insn() function.
> Later on, we propose some changes in core layer, so that we can read the elf
> headers of executable binary. ELFCLASS will be able to tell us, whether its a 32
> bit or 64 bit executable. I think, moving "struct uprobe" from
> kernel/events/uprobes.c to a include/linux header file will do the job. "struct
> arch_uprobe" is part of "struct uprobe". "struct arch_uprobe" is passed in
> arch_uprobe_analyze_insn(). So, we can access struct uprobe's "inode" element
> with this change.
You can get access to struct linux_binfmt via mm_struct but it doesn't
currently help much since all the members of this structure point to
static functions. Maybe an enum in struct linux_binfmt with format types
exposed to the rest of the kernel?
--
Catalin
^ permalink raw reply
* [PATCH] ARM: dts: exynos: Add reboot reason support for Trats2
From: Wolfgang Wiedmeyer @ 2016-09-22 16:48 UTC (permalink / raw)
To: linux-arm-kernel
This allows to reboot the device into recovery mode and into the download
mode of the bootloader.
Signed-off-by: Wolfgang Wiedmeyer <wolfgit@wiedmeyer.de>
---
arch/arm/boot/dts/exynos4412-trats2.dts | 14 ++++++++++++++
arch/arm/boot/dts/exynos4x12.dtsi | 2 +-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 129e973..a38d1e3 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -1294,3 +1294,17 @@
vtmu-supply = <&ldo10_reg>;
status = "okay";
};
+
+&pmu {
+ compatible = "syscon", "simple-mfd";
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x80c>;
+
+ mode-normal = <0x12345670>;
+ mode-bootloader = <0x12345671>;
+ mode-download = <0x12345671>;
+ mode-recovery = <0x12345674>;
+ };
+};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index c452499..b58c14e 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -179,7 +179,7 @@
ranges;
status = "disabled";
- pmu at 10020000 {
+ pmu: pmu at 10020000 {
reg = <0x10020000 0x3000>;
};
--
Website: https://fossencdi.org
OpenPGP: 0F30 D1A0 2F73 F70A 6FEE 048E 5816 A24C 1075 7FC4
Key download: https://wiedmeyer.de/keys/ww.asc
^ permalink raw reply related
* [PATCH] arm: dts: fix rk3066a based boards vdd_log voltage initialization
From: Mark Brown @ 2016-09-22 16:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922171217.09a6d13f@bbrezillon>
On Thu, Sep 22, 2016 at 05:12:17PM +0200, Boris Brezillon wrote:
> +Mark
> I realize Mark has been out of the discussion, and what started as a DT
> problem actually turned into a PWM regulator discussion.
> Maybe we should start a new thread.
Probably, you're lucky I even looked at this - the number of irrelevant
patches I get CCed on is such that I'll often delete things that look
irrelevant unread. I'm unsure what the relevance is, it looks like it's
mainly a discussion about pinctrl?
> As I said, the problem you're describing (pins muxed to the PWM device
> when it should actually stay in gpio+input mode) is not new, and the old
> pwm-regulator and pwm-rockchip implementation (before my atomic PWM
> changes) were behaving the same way.
Why would this make any kind of sense?
> What is new though, is the pwm_regulator_init_state() function [1], and
> it seems it's now preventing the probe of a pwm-regulator device if the
> initial PWM state is not described in the voltage-table.
> The question is, what should we do?
> 1/ Force users to put an entry matching this state (which means
> breaking DT compat)
> 2/ Put a valid value in drvdata->state even if it's not reflecting the
> real state
> 3/ Patch regulator core to support an "unknown-selector" return code.
Could someone say what the actual problem was please? That was a very
long e-mail so I might be missing something but the obvious thing seems
to be to force a state since we'll be doing that when we enable anyway.
Or just not have the voltage table and use it as a continuous regulator.
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^ permalink raw reply
* [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06
From: zhichang.yuan @ 2016-09-22 16:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9178320.n4yHmfyPA3@wuerfel>
On 09/22/2016 08:14 PM, Arnd Bergmann wrote:
> On Thursday, September 22, 2016 11:55:45 AM CEST Gabriele Paoloni wrote:
>>>> I think extending of_empty_ranges_quirk() may be a reasonable
>>> solution.
>>>> What do you think Arnd?
>>> I don't really like that idea, that quirk is meant to work around
>>> broken DTs, but we can just make the DT valid and implement the
>>> code properly.
>> Ok I understand your point where it is not right to use of_empty_ranges_quirk()
>> As a quirk is used to work around broken HW or broken FW (as in this case)
>> rather than to fix code
>>
>> What about the following? I think adding the check you suggested next to
>> of_empty_ranges_quirk() is adding the case we need in the right point (thus
>> avoiding any duplication)
>>
>> --- a/drivers/of/address.c
>> +++ b/drivers/of/address.c
>> @@ -457,6 +457,15 @@ static struct of_bus *of_match_bus(struct device_node *np)
>> return NULL;
>> }
>>
>> +static inline int of_isa_indirect_io(struct device_node *np)
>> +{
>> + /*
>> + * check if the current node is an isa bus and if indirectio operation
>> + * are registered
>> + */
>> + return (of_bus_isa_match(np) && arm64_extio_ops);
>> +}
>> +
>> static int of_empty_ranges_quirk(struct device_node *np)
>> {
>> if (IS_ENABLED(CONFIG_PPC)) {
>> @@ -503,7 +512,7 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus,
>> * This code is only enabled on powerpc. --gcl
>> */
>> ranges = of_get_property(parent, rprop, &rlen);
>> - if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
>> + if (ranges == NULL && !of_empty_ranges_quirk(parent) && !of_isa_indirect_io(parent)) {
>> pr_debug("OF: no ranges; cannot translate\n");
>> return 1;
>> }
> I don't see what effect that would have. What do you want to
> achieve with this?
>
> I think all we need from this function is to return '1' if
> we hit an ISA I/O window, and that should happen for the two
> interesting cases, either no 'ranges' at all, or no translation
> for the range in question, so that __of_translate_address can
> return OF_BAD_ADDR, and we can enter the special case
> handling in the caller, that handles it like
>
> diff --git a/drivers/of/address.c b/drivers/of/address.c
> index 02b2903fe9d2..a18d96843fae 100644
> --- a/drivers/of/address.c
> +++ b/drivers/of/address.c
> @@ -685,17 +685,24 @@ static int __of_address_to_resource(struct device_node *dev,
> if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
> return -EINVAL;
> taddr = of_translate_address(dev, addrp);
> - if (taddr == OF_BAD_ADDR)
> - return -EINVAL;
> memset(r, 0, sizeof(struct resource));
> +
> if (flags & IORESOURCE_IO) {
> unsigned long port;
> - port = pci_address_to_pio(taddr);
> +
> + if (taddr == OF_BAD_ADDR)
> + port = arch_of_address_to_pio(dev, addrp)
> + else
> + port = pci_address_to_pio(taddr);
> +
> if (port == (unsigned long)-1)
> return -EINVAL;
> r->start = port;
> r->end = port + size - 1;
> } else {
> + if (taddr == OF_BAD_ADDR)
> + return -EINVAL;
> +
> r->start = taddr;
> r->end = taddr + size - 1;
> }
>
For this patch sketch, I have a question.
Do we call pci_address_to_pio in arch_of_address_to_pio to get the
corresponding logical IO port
for LPC??
If we don't, it seems the LPC specific IO address will conflict with PCI
host bridges' logical IO.
Supposed our LPC populated the IO range from 0x100 to 0x3FF( this is
normal for ISA similar
devices), after arch_of_address_to_pio(), the r->start will be set as
0x100, r->end will be set as
0x3FF. And if there is one PCI host bridge who request a IO window size
over 0x400 at the same
time, the corresponding r->start and r->end will be set as 0x0, 0x3FF
after of_address_to_resource
for this host bridge. Then the IO conflict happens.
cheers,
Zhichang
>
> Arnd
^ permalink raw reply
* [PATCH v26 3/7] arm64: kdump: add kdump support
From: Matthias Brugger @ 2016-09-22 15:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160907042908.6232-4-takahiro.akashi@linaro.org>
On 09/07/2016 06:29 AM, AKASHI Takahiro wrote:
> On crash dump kernel, all the information about primary kernel's system
> memory (core image) is available in elf core header.
> The primary kernel will set aside this header with reserve_elfcorehdr()
> at boot time and inform crash dump kernel of its location via a new
> device-tree property, "linux,elfcorehdr".
>
> Please note that all other architectures use traditional "elfcorehdr="
> kernel parameter for this purpose.
>
> Then crash dump kernel will access the primary kernel's memory with
> copy_oldmem_page(), which reads one page by ioremap'ing it since it does
> not reside in linear mapping on crash dump kernel.
>
> We also need our own elfcorehdr_read() here since the header is placed
> within crash dump kernel's usable memory.
>
> Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
> ---
> arch/arm64/Kconfig | 11 +++++++
> arch/arm64/kernel/Makefile | 1 +
> arch/arm64/kernel/crash_dump.c | 71 ++++++++++++++++++++++++++++++++++++++++++
> arch/arm64/mm/init.c | 54 ++++++++++++++++++++++++++++++++
> 4 files changed, 137 insertions(+)
> create mode 100644 arch/arm64/kernel/crash_dump.c
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index bc3f00f..9c15c66 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -683,6 +683,17 @@ config KEXEC
> but it is independent of the system firmware. And like a reboot
> you can start any kernel with it, not just Linux.
>
> +config CRASH_DUMP
> + bool "Build kdump crash kernel"
> + help
> + Generate crash dump after being started by kexec. This should
> + be normally only set in special crash dump kernels which are
> + loaded in the main kernel with kexec-tools into a specially
> + reserved region and then later executed after a crash by
> + kdump/kexec.
> +
> + For more details see Documentation/kdump/kdump.txt
> +
> config XEN_DOM0
> def_bool y
> depends on XEN
> diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
> index 14f7b65..f1cbfc8 100644
> --- a/arch/arm64/kernel/Makefile
> +++ b/arch/arm64/kernel/Makefile
> @@ -48,6 +48,7 @@ arm64-obj-$(CONFIG_RANDOMIZE_BASE) += kaslr.o
> arm64-obj-$(CONFIG_HIBERNATION) += hibernate.o hibernate-asm.o
> arm64-obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o \
> cpu-reset.o
> +arm64-obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
>
> obj-y += $(arm64-obj-y) vdso/ probes/
> obj-m += $(arm64-obj-m)
> diff --git a/arch/arm64/kernel/crash_dump.c b/arch/arm64/kernel/crash_dump.c
> new file mode 100644
> index 0000000..bc5b932
> --- /dev/null
> +++ b/arch/arm64/kernel/crash_dump.c
> @@ -0,0 +1,71 @@
> +/*
> + * Routines for doing kexec-based kdump
> + *
> + * Copyright (C) 2014 Linaro Limited
> + * Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/crash_dump.h>
> +#include <linux/errno.h>
> +#include <linux/io.h>
> +#include <linux/memblock.h>
> +#include <linux/uaccess.h>
> +#include <asm/memory.h>
> +
> +/**
> + * copy_oldmem_page() - copy one page from old kernel memory
> + * @pfn: page frame number to be copied
> + * @buf: buffer where the copied page is placed
> + * @csize: number of bytes to copy
> + * @offset: offset in bytes into the page
> + * @userbuf: if set, @buf is in a user address space
> + *
> + * This function copies one page from old kernel memory into buffer pointed by
> + * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
> + * copied or negative error in case of failure.
> + */
> +ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
> + size_t csize, unsigned long offset,
> + int userbuf)
> +{
> + void *vaddr;
> +
> + if (!csize)
> + return 0;
> +
> + vaddr = memremap(__pfn_to_phys(pfn), PAGE_SIZE, MEMREMAP_WB);
> + if (!vaddr)
> + return -ENOMEM;
> +
> + if (userbuf) {
> + if (copy_to_user(buf, vaddr + offset, csize)) {
> + memunmap(vaddr);
> + return -EFAULT;
> + }
> + } else {
> + memcpy(buf, vaddr + offset, csize);
> + }
> +
> + memunmap(vaddr);
> +
> + return csize;
> +}
> +
> +/**
> + * elfcorehdr_read - read from ELF core header
> + * @buf: buffer where the data is placed
> + * @csize: number of bytes to read
> + * @ppos: address in the memory
> + *
> + * This function reads @count bytes from elf core header which exists
> + * on crash dump kernel's memory.
> + */
> +ssize_t elfcorehdr_read(char *buf, size_t count, u64 *ppos)
> +{
> + memcpy(buf, phys_to_virt((phys_addr_t)*ppos), count);
> + return count;
> +}
> diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
> index dd273ec..e4d9c38 100644
> --- a/arch/arm64/mm/init.c
> +++ b/arch/arm64/mm/init.c
> @@ -36,6 +36,7 @@
> #include <linux/efi.h>
> #include <linux/swiotlb.h>
> #include <linux/kexec.h>
> +#include <linux/crash_dump.h>
>
> #include <asm/boot.h>
> #include <asm/fixmap.h>
> @@ -186,6 +187,57 @@ static void __init reserve_crashkernel(void)
> }
> #endif /* CONFIG_KEXEC_CORE */
>
> +#ifdef CONFIG_CRASH_DUMP
> +static int __init early_init_dt_scan_elfcorehdr(unsigned long node,
> + const char *uname, int depth, void *data)
> +{
> + const __be32 *reg;
> + int len;
> +
> + if (depth != 1 || strcmp(uname, "chosen") != 0)
> + return 0;
> +
> + reg = of_get_flat_dt_prop(node, "linux,elfcorehdr", &len);
> + if (!reg || (len < (dt_root_addr_cells + dt_root_size_cells)))
> + return 1;
> +
> + elfcorehdr_addr = dt_mem_next_cell(dt_root_addr_cells, ®);
> + elfcorehdr_size = dt_mem_next_cell(dt_root_size_cells, ®);
> +
> + return 1;
> +}
> +
> +/*
> + * reserve_elfcorehdr() - reserves memory for elf core header
> + *
> + * This function reserves elf core header given in "elfcorehdr=" kernel
> + * command line parameter. This region contains all the information about
> + * primary kernel's core image and is used by a dump capture kernel to
> + * access the system memory on primary kernel.
> + */
> +static void __init reserve_elfcorehdr(void)
> +{
> + of_scan_flat_dt(early_init_dt_scan_elfcorehdr, NULL);
> +
Do I get that right that we can pass crashkernel address/size through
the kernel boot parameter, but elfcorehdr can only be provided via
device tree?
Why? If there is a reason for doing so, we should fix the documentation.
Regards,
Matthias
^ permalink raw reply
* [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06
From: zhichang.yuan @ 2016-09-22 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <EE11001F9E5DDD47B7634E2F8A612F2E1F882BB3@lhreml507-mbx>
On 09/22/2016 11:20 PM, Gabriele Paoloni wrote:
>
>> -----Original Message-----
>> From: Arnd Bergmann [mailto:arnd at arndb.de]
>> Sent: 22 September 2016 15:59
>> To: Gabriele Paoloni
>> Cc: zhichang; linux-arm-kernel at lists.infradead.org;
>> devicetree at vger.kernel.org; lorenzo.pieralisi at arm.com; minyard at acm.org;
>> linux-pci at vger.kernel.org; gregkh at linuxfoundation.org; John Garry;
>> will.deacon at arm.com; linux-kernel at vger.kernel.org; Yuanzhichang;
>> Linuxarm; xuwei (O); linux-serial at vger.kernel.org;
>> benh at kernel.crashing.org; zourongrong at gmail.com; liviu.dudau at arm.com;
>> kantyzc at 163.com
>> Subject: Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on
>> Hip06
>>
>> On Thursday, September 22, 2016 2:47:14 PM CEST Gabriele Paoloni wrote:
>>>>> static int of_empty_ranges_quirk(struct device_node *np)
>>>>> {
>>>>> if (IS_ENABLED(CONFIG_PPC)) {
>>>>> @@ -503,7 +512,7 @@ static int of_translate_one(struct
>> device_node
>>>> *parent, struct of_bus *bus,
>>>>> * This code is only enabled on powerpc. --gcl
>>>>> */
>>>>> ranges = of_get_property(parent, rprop, &rlen);
>>>>> - if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
>>>>> + if (ranges == NULL && !of_empty_ranges_quirk(parent) &&
>>>> !of_isa_indirect_io(parent)) {
>>>>> pr_debug("OF: no ranges; cannot translate\n");
>>>>> return 1;
>>>>> }
>>>> I don't see what effect that would have. What do you want to
>>>> achieve with this?
>>> If I read the code correctly adding the function above would end
>>> up in a 1:1 mapping:
>>> http://lxr.free-electrons.com/source/drivers/of/address.c#L513
>>>
>>> so taddr will be assigned with the cpu address space specified
>>> in the children nodes of LPC and we are not using a quirk function
>>> (we are just checking that we have the indirect io assigned and
>>> that we are on a ISA bus). Now probably there is a nit in my
>>> code sketch where of_isa_indirect_io should be probably an
>> architecture
>>> specific function...
>> But the point is that it would then return an incorrect address,
>> which in the worst case could be the same as another I/O space
>> if that happens to be at CPU address zero.
> If we do not touch __of_address_to_resource after taddr is returned
> by of_translate_address we will check for (flags & IORESOURCE_IO),
> then we call pci_address_to_pio to retrieve the unique token (remember
> that LPC driver will register the LPC io range to pci io_range_list).
>
> I do not think that we can have any conflict with any other I/O space
> as pci_register_io_range will guarantee that the LPC range does not
> overlap with any other I/O range...
If we don't bypass the calling of pci_address_to_pio after
of_translate_address,
there should no conflict between LPC logical IO range and other logical
IO ranges
of other devices.
I guess Arnd want to skip all the translation for our LPC IO address.
But if we do it
like that, it seems we can't avoid the possible conflict with the
logical IO ranges of
PCI host bridges without any changes on the pci_register_io_range and
pci_address_to_pio.
Because two completely separate I/O spaces are created without
synchronization.
Best,
Zhichang
>>>> I think all we need from this function is to return '1' if
>>>> we hit an ISA I/O window, and that should happen for the two
>>>> interesting cases, either no 'ranges' at all, or no translation
>>>> for the range in question, so that __of_translate_address can
>>>> return OF_BAD_ADDR, and we can enter the special case
>>>> handling in the caller, that handles it like
>>>>
>>> I don't think this is very right as you may fail for different
>>> reasons other than a missing range property, e.g:
>>> http://lxr.free-electrons.com/source/drivers/of/address.c#L575
>>>
>>> And even if the only failure case was a missing range if in the
>>> future __of_translate_address had to be reworked we would again
>>> make a wrong assumption...you get my point?
>> The newly introduced function would clearly have to make
>> some sanity checks. The idea is that treat the case of
>> not being able to translate a bus specific I/O address
>> into a CPU address literally and fall back to another method
>> of translating that address.
>>
>> This matches my mental model of how we find the resource:
>>
>> - start with the bus address
>> - try to translate that into a CPU address
>> - if we arrive at a CPU physical address for IORESOURCE_MEM, use that
>> - if we arrive at a CPU physical address for IORESOURCE_IO, translate
>> that into a Linux IORESOURCE_IO token
>> - if there is no valid CPU physical address, try to translate
>> the address into an IORESOURCE_IO using the ISA accessor
>> - if that fails too, give up.
>>
>> If you try to fake a CPU physical address inbetween, it just
>> gets more confusing.
>>
>> Arnd
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