* [PATCH 4/4] ARM: at91: debug: add samx7 support
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922222208.23798-1-alexandre.belloni@free-electrons.com>
From: Szemz? Andr?s <sza@esh.hu>
Add support for low level debugging on Atmel samx7.
Signed-off-by: Szemz? Andr?s <sza@esh.hu>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/Kconfig.debug | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a9693b6987a6..d209d0d78820 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -145,6 +145,15 @@ choice
Say Y here if you want kernel low-level debugging support
on the USART3 port of sama5d4.
+ config DEBUG_AT91_SAMX7_USART1
+ bool "Kernel low-level debugging via SAMX7 USART1"
+ select DEBUG_AT91_UART
+ depends on SOC_SAMX7
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the USART1 port on SAMX7 based
+ machines.
+
config DEBUG_BCM2835
bool "Kernel low-level debugging on BCM2835 PL011 UART"
depends on ARCH_BCM2835 && ARCH_MULTI_V6
@@ -1479,6 +1488,7 @@ config DEBUG_UART_PHYS
default 0x3f201000 if DEBUG_BCM2836
default 0x3e000000 if DEBUG_BCM_KONA_UART
default 0x4000e400 if DEBUG_LL_UART_EFM32
+ default 0x40028000 if DEBUG_AT91_SAMX7_USART1
default 0x40081000 if DEBUG_LPC18XX_UART0
default 0x40090000 if DEBUG_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
--
2.9.3
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: at91: add samx7 dtsi
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922222208.23798-1-alexandre.belloni@free-electrons.com>
From: Szemz? Andr?s <sza@esh.hu>
Add device tree support for Atmel samx7 SoCs family.
Signed-off-by: Szemz? Andr?s <sza@esh.hu>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/samx7.dtsi | 1166 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 1166 insertions(+)
create mode 100644 arch/arm/boot/dts/samx7.dtsi
diff --git a/arch/arm/boot/dts/samx7.dtsi b/arch/arm/boot/dts/samx7.dtsi
new file mode 100644
index 000000000000..fcef47c22413
--- /dev/null
+++ b/arch/arm/boot/dts/samx7.dtsi
@@ -0,0 +1,1166 @@
+/*
+ * samx7.dtsi - Device Tree Include file for SAMx7 family SoCs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armv7-m.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Atmel SAMx7 family SoC";
+ compatible = "atmel,samx7";
+
+ aliases {
+ serial0 = &usart0;
+ serial1 = &usart1;
+ serial2 = &usart2;
+ serial3 = &uart0;
+ serial4 = &uart1;
+ serial5 = &uart2;
+ serial6 = &uart3;
+ serial7 = &uart4;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ gpio3 = &pioD;
+ gpio4 = &pioE;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ tcb0 = &tcb0;
+ tcb1 = &tcb1;
+ tcb2 = &tcb2;
+ tcb3 = &tcb3;
+ pwm0 = &pwm0;
+ pwm1 = &pwm1;
+ };
+
+ clocks {
+
+ clk_slck: clk-slck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ clk_mck: clk-mck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+ };
+
+ soc {
+
+ pmc: pmc at 0x400e0600 {
+ compatible = "atmel,at91sam9x5-pmc", "syscon";
+ reg = <0x400e0600 0x200>;
+ interrupts = <5>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk_mck>;
+
+ uart0_clk: uart0_clk {
+ #clock-cells = <0>;
+ reg = <7>;
+ };
+
+ uart1_clk: uart1_clk {
+ #clock-cells = <0>;
+ reg = <8>;
+ };
+
+ smc_clk: smc_clk {
+ #clock-cells = <0>;
+ reg = <9>;
+ };
+
+ pioA_clk: pioA_clk {
+ #clock-cells = <0>;
+ reg = <10>;
+ };
+
+ pioB_clk: pioB_clk {
+ #clock-cells = <0>;
+ reg = <11>;
+ };
+
+ pioC_clk: pioC_clk {
+ #clock-cells = <0>;
+ reg = <12>;
+ };
+
+ usart0_clk: usart0_clk {
+ #clock-cells = <0>;
+ reg = <13>;
+ };
+
+ usart1_clk: usart1_clk {
+ #clock-cells = <0>;
+ reg = <14>;
+ };
+
+ usart2_clk: usart2_clk {
+ #clock-cells = <0>;
+ reg = <15>;
+ };
+
+ pioD_clk: pioD_clk {
+ #clock-cells = <0>;
+ reg = <16>;
+ };
+
+ pioE_clk: pioE_clk {
+ #clock-cells = <0>;
+ reg = <17>;
+ };
+
+ mci_clk: mci_clk {
+ #clock-cells = <0>;
+ reg = <18>;
+ };
+
+ twi0_clk: twi0_clk {
+ #clock-cells = <0>;
+ reg = <19>;
+ };
+
+ twi1_clk: twi1_clk {
+ #clock-cells = <0>;
+ reg = <20>;
+ };
+
+ spi0_clk: spi0_clk {
+ #clock-cells = <0>;
+ reg = <21>;
+ };
+
+ ssc_clk: ssc_clk {
+ #clock-cells = <0>;
+ reg = <22>;
+ };
+
+ tcb0_clk: tcb0_clk {
+ #clock-cells = <0>;
+ reg = <23>;
+ };
+
+ tcb1_clk: tcb1_clk {
+ #clock-cells = <0>;
+ reg = <24>;
+ };
+
+ tcb2_clk: tcb2_clk {
+ #clock-cells = <0>;
+ reg = <25>;
+ };
+
+ tcb3_clk: tcb3_clk {
+ #clock-cells = <0>;
+ reg = <26>;
+ };
+
+ tcb4_clk: tcb4_clk {
+ #clock-cells = <0>;
+ reg = <27>;
+ };
+
+ tcb5_clk: tcb5_clk {
+ #clock-cells = <0>;
+ reg = <28>;
+ };
+
+ afec0_clk: afec0_clk {
+ #clock-cells = <0>;
+ reg = <29>;
+ };
+
+ dacc_clk: dacc_clk {
+ #clock-cells = <0>;
+ reg = <30>;
+ };
+
+ pwm0_clk: pwm0_clk {
+ #clock-cells = <0>;
+ reg = <31>;
+ };
+
+ icm_clk: cim_clk {
+ #clock-cells = <0>;
+ reg = <32>;
+ };
+
+ acc_clk: acc_clk {
+ #clock-cells = <0>;
+ reg = <33>;
+ };
+
+ usbhs_clk: usbhs_clk {
+ #clock-cells = <0>;
+ reg = <34>;
+ };
+
+ can0_clk: can0_clk {
+ #clock-cells = <0>;
+ reg = <35>;
+ };
+
+ can1_clk: can1_clk {
+ #clock-cells = <0>;
+ reg = <37>;
+ };
+
+ macb_clk: macb_clk {
+ #clock-cells = <0>;
+ reg = <39>;
+ };
+
+ afec1_clk: afec1_clk {
+ #clock-cells = <0>;
+ reg = <40>;
+ };
+
+ twi2_clk: twi2_clk {
+ #clock-cells = <0>;
+ reg = <41>;
+ };
+
+ spi1_clk: spi1_clk {
+ #clock-cells = <0>;
+ reg = <42>;
+ };
+
+ qspi_clk: qspi_clk {
+ #clock-cells = <0>;
+ reg = <43>;
+ };
+
+ uart2_clk: uart2_clk {
+ #clock-cells = <0>;
+ reg = <44>;
+ };
+
+ uart3_clk: uart3_clk {
+ #clock-cells = <0>;
+ reg = <45>;
+ };
+
+ uart4_clk: uart4_clk {
+ #clock-cells = <0>;
+ reg = <46>;
+ };
+
+ tcb6_clk: tcb6_clk {
+ #clock-cells = <0>;
+ reg = <47>;
+ };
+
+ tcb7_clk: tcb7_clk {
+ #clock-cells = <0>;
+ reg = <48>;
+ };
+
+ tcb8_clk: tcb8_clk {
+ #clock-cells = <0>;
+ reg = <49>;
+ };
+
+ tcb9_clk: tcb9_clk {
+ #clock-cells = <0>;
+ reg = <50>;
+ };
+
+ tcb10_clk: tcb10_clk {
+ #clock-cells = <0>;
+ reg = <51>;
+ };
+
+ tcb11_clk: tcb11_clk {
+ #clock-cells = <0>;
+ reg = <52>;
+ };
+
+ aes_clk: aes_clk {
+ #clock-cells = <0>;
+ reg = <56>;
+ };
+
+ trng_clk: trng_clk {
+ #clock-cells = <0>;
+ reg = <57>;
+ };
+
+ dma_clk: dma_clk {
+ #clock-cells = <0>;
+ reg = <58>;
+ };
+
+ isi_clk: isi_clk {
+ #clock-cells = <0>;
+ reg = <59>;
+ };
+
+ pwm1_clk: pwm1_clk {
+ #clock-cells = <0>;
+ reg = <60>;
+ };
+
+ i2sc0_clk: i2sc0_clk {
+ #clock-cells = <0>;
+ reg = <69>;
+ };
+
+ i2sc1_clk: i2sc1_clk {
+ #clock-cells = <0>;
+ reg = <70>;
+ };
+ };
+ };
+
+ pinctrl at 0x400e0e00 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
+ ranges = <0x400e0e00 0x400e0e00 0xa00>;
+
+ pioA: gpio at 0x400e0e00 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e0e00 0x200>;
+ interrupts = <10>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ };
+
+ pioB: gpio at 0x400e1000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e1000 0x200>;
+ interrupts = <11>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ };
+
+ pioC: gpio at 0x400e1200 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e1200 0x200>;
+ interrupts = <12>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ };
+
+ pioD: gpio at 0x400e1400 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e1400 0x200>;
+ interrupts = <16>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioD_clk>;
+ };
+
+ pioE: gpio at 0x400e1600 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e1600 0x200>;
+ interrupts = <17>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioE_clk>;
+ };
+
+ macb {
+ pinctrl_macb_rmii: macb_rmii-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
+ AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
+ AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A */
+ AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
+ AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
+ AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD5 periph A */
+ AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A */
+ AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A */
+ AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A */
+ AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A */
+ >;
+ };
+ };
+
+ mmc {
+ pinctrl_mmc_clk_cmd_dat0: mmc_clk_cmd_dat0 {
+ atmel,pins =
+ <AT91_PIOA 25 AT91_PERIPH_D AT91_PINCTRL_NONE /* MCI_CK */
+ AT91_PIOA 28 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_CDA */
+ AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_DB0 */
+ >;
+ };
+ pinctrl_mmc_dat1_3: mmc_dat1_3 {
+ atmel,pins =
+ <AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_DB1 */
+ AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_DB2 */
+ AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_DB3 */
+ >;
+ };
+ };
+
+ i2c_gpio0 {
+ pinctrl_i2c_gpio0: i2c_gpio0-0 {
+ atmel,pins =
+ <AT91_PIOA 3 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA3 gpio multidrive I2C0 data */
+ AT91_PIOA 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA4 gpio multidrive I2C0 clock */
+ };
+ };
+
+ i2c_gpio1 {
+ pinctrl_i2c_gpio1: i2c_gpio1-0 {
+ atmel,pins =
+ <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C1 data */
+ AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C1 clock */
+ };
+ };
+
+ i2c_gpio2 {
+ pinctrl_i2c_gpio2: i2c_gpio2-0 {
+ atmel,pins =
+ <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PD27 gpio multidrive I2C2 data */
+ AT91_PIOD 28 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PD28 gpio multidrive I2C2 clock */
+ };
+ };
+
+ i2c0 {
+ pinctrl_i2c0: i2c0-0 {
+ atmel,pins =
+ <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A I2C0 data */
+ AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A I2C0 clock */
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1: i2c1-0 {
+ atmel,pins =
+ <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A I2C1 data */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A I2C1 clock */
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2: i2c2-0 {
+ atmel,pins =
+ <AT91_PIOD 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD27 periph C I2C2 data */
+ AT91_PIOD 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD28 periph C I2C2 clock */
+ };
+ };
+
+ qspi {
+ pinctrl_qspi: qspi-0 {
+ atmel,pins =
+ <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A QSCK */
+ AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A QCS */
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A QIO0 */
+ AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A QIO1 */
+ AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A QIO2 */
+ AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD31 periph A QIO3 */
+ >;
+ };
+ };
+
+ usart0 {
+ pinctrl_usart0: usart0-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PB0 periph C RXD */
+ AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PB1 periph C TXD */
+ >;
+ };
+
+ pinctrl_usart0_rts: usart0_rts-0 {
+ atmel,pins = <AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PB3 periph C */
+ };
+
+ pinctrl_usart0_cts: usart0_cts-0 {
+ atmel,pins = <AT91_PIOB 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PB2 periph C */
+ };
+ };
+
+ usart1 {
+ pinctrl_usart1: usart1-0 {
+ atmel,pins =
+ <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A RXD */
+ AT91_PIOB 4 AT91_PERIPH_D AT91_PINCTRL_PULL_UP /* PB4 periph D TXD */
+ >;
+ };
+
+ pinctrl_usart1_rts: usart1_rts-0 {
+ atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA24 periph A */
+ };
+
+ pinctrl_usart1_cts: usart1_cts-0 {
+ atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA25 periph A */
+ };
+ };
+
+ usart2 {
+ pinctrl_usart2: usart2-0 {
+ atmel,pins =
+ <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PD15 periph B RXD */
+ AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD16 periph B TXD */
+ >;
+ };
+
+ pinctrl_usart2_rts: usart2_rts-0 {
+ atmel,pins = <AT91_PIOD 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD18 periph B */
+ };
+
+ pinctrl_usart2_cts: usart2_cts-0 {
+ atmel,pins = <AT91_PIOD 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD19 periph B */
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0: spi0-0 {
+ atmel,pins =
+ <AT91_PIOD 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI0_MISO */
+ AT91_PIOD 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI0_MOSI */
+ AT91_PIOD 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI0_SPCK */
+ >;
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1: spi1-0 {
+ atmel,pins =
+ <AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* SPI1_MISO */
+ AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* SPI1_MOSI */
+ AT91_PIOC 24 AT91_PERIPH_C AT91_PINCTRL_NONE /* SPI1_SPCK */
+ >;
+ };
+ };
+
+ can0 {
+ pinctrl_can0_rx_tx: can0_rx_tx {
+ atmel,pins =
+ <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A RX */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A TX */
+ };
+ };
+
+ can1 {
+ pinctrl_can1_rx_tx: can1_rx_tx {
+ atmel,pins =
+ <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C RX */
+ AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC14 periph C TX */
+ };
+ };
+
+ pwm0 {
+ pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
+ atmel,pins =
+ <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_2: pwm0_pwmh0-2 {
+ atmel,pins =
+ <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_3: pwm0_pwmh0-3 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_4: pwm0_pwmh0-4 {
+ atmel,pins =
+ <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_5: pwm0_pwmh0-5 {
+ atmel,pins =
+ <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
+ atmel,pins =
+ <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
+ atmel,pins =
+ <AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
+ atmel,pins =
+ <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh1_3: pwm0_pwmh1-3 {
+ atmel,pins =
+ <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh1_4: pwm0_pwmh1-4 {
+ atmel,pins =
+ <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
+ atmel,pins =
+ <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
+ atmel,pins =
+ <AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh2_2: pwm0_pwmh2-2 {
+ atmel,pins =
+ <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh2_3: pwm0_pwmh2-3 {
+ atmel,pins =
+ <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh2_4: pwm0_pwmh2-4 {
+ atmel,pins =
+ <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
+ atmel,pins =
+ <AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
+ atmel,pins =
+ <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_2: pwm0_pwmh3-2 {
+ atmel,pins =
+ <AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_3: pwm0_pwmh3-3 {
+ atmel,pins =
+ <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_4: pwm0_pwmh3-4 {
+ atmel,pins =
+ <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_5: pwm0_pwmh3-5 {
+ atmel,pins =
+ <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ pwm1 {
+ pinctrl_pwm1_pwmh0_0: pwm1_pwmh0-0 {
+ atmel,pins =
+ <AT91_PIOA 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm1_pwmh0_1: pwm1_pwmh0-1 {
+ atmel,pins =
+ <AT91_PIOD 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm1_pwmh1_0: pwm1_pwmh1-0 {
+ atmel,pins =
+ <AT91_PIOA 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm1_pwmh1_1: pwm1_pwmh1-1 {
+ atmel,pins =
+ <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm1_pwmh2_0: pwm1_pwmh2-0 {
+ atmel,pins =
+ <AT91_PIOA 31 AT91_PERIPH_D AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm1_pwmh2_1: pwm1_pwmh2-1 {
+ atmel,pins =
+ <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm1_pwmh3_0: pwm1_pwmh3-0 {
+ atmel,pins =
+ <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm1_pwmh3_1: pwm1_pwmh3-1 {
+ atmel,pins =
+ <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ ssc {
+ pinctrl_ssc_tx: ssc_tx {
+ atmel,pins =
+ <AT91_PIOB 1 AT91_PERIPH_D AT91_PINCTRL_NONE /* PB1 periph D TK */
+ AT91_PIOB 0 AT91_PERIPH_D AT91_PINCTRL_NONE /* PB0 periph D TF */
+ AT91_PIOD 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD26 periph B TD */
+ };
+
+ pinctrl_ssc_rx: ssc_rx {
+ atmel,pins =
+ <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A RK */
+ AT91_PIOD 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PD24 periph B RF */
+ AT91_PIOA 10 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA10 periph C RD */
+ };
+ };
+ };
+
+ chipid: chipid at 0x400e0940 {
+ compatible = "atmel,sama5d2-chipid";
+ reg = <0x400e0940 0xc0>;
+ };
+
+ rstc at 400e1800 {
+ compatible = "atmel,samx7-rstc";
+ reg = <0x400e1800 0x10>;
+ clocks = <&clk_slck>;
+ };
+
+ ssc: ssc at 40004000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0x40004000 0x4000>;
+ interrupts = <22>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(32))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(33))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc_tx &pinctrl_ssc_rx>;
+ clocks = <&ssc_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ pwm0: pwm at 40020000 {
+ compatible = "atmel,sama5d3-pwm";
+ reg = <0x40020000 0x4000>;
+ interrupts = <31>;
+ #pwm-cells = <3>;
+ clocks = <&pwm0_clk>;
+ status = "disabled";
+ };
+
+ pwm1: pwm at 4005c000 {
+ compatible = "atmel,sama5d3-pwm";
+ reg = <0x4005c000 0x4000>;
+ interrupts = <60>;
+ #pwm-cells = <3>;
+ clocks = <&pwm1_clk>;
+ status = "disabled";
+ };
+
+ watchdog at 400e1850 {
+ compatible = "atmel,at91sam9260-wdt";
+ reg = <0x400e1850 0x10>;
+ interrupts = <4>;
+ clocks = <&clk_slck>;
+ atmel,watchdog-type = "hardware";
+ atmel,reset-type = "all";
+ atmel,dbg-halt;
+ status = "disabled";
+ };
+
+ tcb0: timer at 4000c000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0x4000c000 0x4000>;
+ interrupts = <23 24 25>;
+ clocks = <&tcb0_clk>, <&tcb1_clk>, <&tcb2_clk>, <&clk_slck>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ tcb1: timer at 40010000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0x40010000 0x4000>;
+ interrupts = <26 27 28>;
+ clocks = <&tcb3_clk>, <&tcb4_clk>, <&tcb5_clk>, <&clk_slck>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ tcb2: timer at 40014000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0x40014000 0x4000>;
+ interrupts = <47 48 49>;
+ clocks = <&tcb6_clk>, <&tcb7_clk>, <&tcb8_clk>, <&clk_slck>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ tcb3: timer at 40054000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0x40054000 0x4000>;
+ interrupts = <50 51 52>;
+ clocks = <&tcb9_clk>, <&tcb10_clk>, <&tcb11_clk>, <&clk_slck>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ dma: dma-controller at 40078000 {
+ compatible = "atmel,sama5d4-dma";
+ reg = <0x40078000 0x4000>;
+ interrupts = <58>;
+ #dma-cells = <1>;
+ clocks = <&dma_clk>;
+ clock-names = "dma_clk";
+ status = "disabled";
+ };
+
+ qspi: qspi at 4007c000 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0x4007c000 0x4000>, <0x80000000 0x20000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <43>;
+ clocks = <&qspi_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "disabled";
+ };
+
+ aes at 4006c000 {
+ compatible = "atmel,at91sam9g46-aes";
+ reg = <0x4006c000 0x4000>;
+ interrupts = <56>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(37))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(38))>;
+ dma-names = "tx", "rx";
+ clocks = <&aes_clk>;
+ clock-names = "aes_clk";
+ status = "disabled";
+ };
+
+ i2c0: i2c at 40018000 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x40018000 0x4000>;
+ interrupts = <19>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(14))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(15))>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi0_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 4001c000 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x4001c000 0x4000>;
+ interrupts = <20>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(16))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(17))>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi1_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 40060000 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x40060000 0x4000>;
+ interrupts = <41>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(18))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(19))>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi2_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "disabled";
+ };
+
+ macb: ethernet at 40050000 {
+ compatible = "atmel,samx7-gem";
+ reg = <0x40050000 0x4000>;
+ interrupts = <39 66 67>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-mode = "rmii";
+ clocks = <&macb_clk>, <&macb_clk>;
+ clock-names = "hclk", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_phy_irq>;
+ status = "disabled";
+ };
+
+ mmc0: mmc at 40000000 {
+ compatible = "atmel,hsmci";
+ reg = <0x40000000 0x4000>;
+ interrupts = <18>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+ | AT91_XDMAC_DT_PERID(0))>;
+ dma-names = "rxtx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc_clk_cmd_dat0 &pinctrl_mmc_dat1_3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mci_clk>;
+ clock-names = "mci_clk";
+ status = "disabled";
+ };
+
+ spi0: spi at 40008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x40008000 0x4000>;
+ interrupts = <21>;
+ atmel,fifo-size = <0>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(1))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(2))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&spi0_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ trng at 4007000 {
+ compatible = "atmel,at91sam9g45-trng";
+ reg = <0x40070000 0x4000>;
+ interrupts = <57>;
+ clocks = <&trng_clk>;
+ status = "disabled";
+ };
+
+ rtc at 400e1860 {
+ compatible = "atmel,at91rm9200-rtc";
+ reg = <0x400e1860 0x30>;
+ interrupts = <2>;
+ clocks = <&clk_slck>;
+ status = "disabled";
+ };
+
+ usart0: serial at 40024000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x40024000 0x4000>;
+ interrupts = <13>;
+ clocks = <&usart0_clk>;
+ clock-names = "usart";
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(7))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(8))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart0>;
+ status = "disabled";
+ };
+
+ usart1: serial at 40028000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x40028000 0x4000>;
+ interrupts = <14>;
+ clocks = <&usart1_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(9))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(10))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart1>;
+ status = "disabled";
+ };
+
+ usart2: serial at 4002c000 {
+ compatible = "atmel,same70-usart";
+ reg = <0x4002c000 0x4000>;
+ interrupts = <15>;
+ clocks = <&usart2_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(12))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart2>;
+ status = "disabled";
+ };
+
+ uart0: serial at 400e0800 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e0800 0x140>;
+ interrupts = <7>;
+ clocks = <&uart0_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(20))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(21))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart1: serial at 400e0a00 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e0a00 0x200>;
+ interrupts = <8>;
+ clocks = <&uart1_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(22))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(23))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart2: serial at 400e1a00 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e1a00 0x200>;
+ interrupts = <44>;
+ clocks = <&uart2_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(24))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(25))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart3: serial at 400e1c00 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e1c00 0x200>;
+ interrupts = <45>;
+ clocks = <&uart3_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(26))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(27))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart4: serial at 400e1e00 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e1e00 0x200>;
+ interrupts = <46>;
+ clocks = <&uart4_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(28))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(29))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+};
--
2.9.3
^ permalink raw reply related
* [PATCH 2/4] ARM: at91: handle CONFIG_PM for armv7m configurations
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922222208.23798-1-alexandre.belloni@free-electrons.com>
There is currently no PM support for samx7 but the symbol can still be
selected. This avoids compilation issues.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Kconfig | 6 ++++++
arch/arm/mach-at91/Makefile | 3 +--
arch/arm/mach-at91/samx7.c | 10 ++++++++++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 3ca2724a6ca6..df3b6efa888d 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -59,6 +59,7 @@ config SOC_AT91RM9200
bool "AT91RM9200"
depends on ARCH_MULTI_V4T
select ATMEL_AIC_IRQ
+ select ATMEL_PM if PM
select ATMEL_ST
select CPU_ARM920T
select HAVE_AT91_USB_CLK
@@ -73,6 +74,7 @@ config SOC_AT91SAM9
bool "AT91SAM9"
depends on ARCH_MULTI_V5
select ATMEL_AIC_IRQ
+ select ATMEL_PM if PM
select ATMEL_SDRAMC
select CPU_ARM926T
select HAVE_AT91_SMD
@@ -131,9 +133,13 @@ config SOC_SAM_V7
config SOC_SAMA5
bool
select ATMEL_AIC5_IRQ
+ select ATMEL_PM if PM
select ATMEL_SDRAMC
select MEMORY
select SOC_SAM_V7
select SRAM if PM
+config ATMEL_PM
+ bool
+
endif
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 84956a18d604..116691714bb8 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,8 +10,7 @@ obj-$(CONFIG_SOC_SAMA5) += sama5.o
obj-$(CONFIG_SOC_SAMX7) += samx7.o
# Power Management
-obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM) += pm_suspend.o
+obj-$(CONFIG_ATMEL_PM) += pm.o pm_suspend.o
ifeq ($(CONFIG_CPU_V7),y)
AFLAGS_pm_suspend.o := -march=armv7-a
diff --git a/arch/arm/mach-at91/samx7.c b/arch/arm/mach-at91/samx7.c
index bd33bc56278e..240f8cda79ee 100644
--- a/arch/arm/mach-at91/samx7.c
+++ b/arch/arm/mach-at91/samx7.c
@@ -16,6 +16,16 @@
#include "generic.h"
#include "soc.h"
+
+#ifdef CONFIG_PM
+/* This function has to be defined for various drivers that are using it */
+int at91_suspend_entering_slow_clock(void)
+{
+ return 0;
+}
+EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
+#endif
+
static const struct at91_soc samx7_socs[] = {
AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
"same70q21", "samx7"),
--
2.9.3
^ permalink raw reply related
* [PATCH 1/4] ARM: at91: Add armv7m support
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922222208.23798-1-alexandre.belloni@free-electrons.com>
From: Szemz? Andr?s <sza@esh.hu>
Add Atmel SAME70/SAMS70/SAMV71 SoC support and detection.
Signed-off-by: Szemz? Andr?s <sza@esh.hu>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Kconfig | 9 +++++-
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/Makefile.boot | 3 ++
arch/arm/mach-at91/samx7.c | 62 ++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-at91/soc.h | 21 ++++++++++++++
5 files changed, 95 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-at91/Makefile.boot
create mode 100644 arch/arm/mach-at91/samx7.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 5204395efda8..3ca2724a6ca6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,12 +1,19 @@
menuconfig ARCH_AT91
bool "Atmel SoCs"
- depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7
+ depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
select COMMON_CLK_AT91
select GPIOLIB
select PINCTRL
select SOC_BUS
if ARCH_AT91
+config SOC_SAMX7
+ bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
+ select COMMON_CLK_AT91
+ select PINCTRL_AT91
+ help
+ Select this if you are using one of Atmel's SAMx7 family SoC.
+
config SOC_SAMA5D2
bool "SAMA5D2 family"
depends on ARCH_MULTI_V7
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c5bbf8bb8c0f..84956a18d604 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,6 +7,7 @@ obj-y := soc.o
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
obj-$(CONFIG_SOC_SAMA5) += sama5.o
+obj-$(CONFIG_SOC_SAMX7) += samx7.o
# Power Management
obj-$(CONFIG_PM) += pm.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
new file mode 100644
index 000000000000..eacfc3f5c33e
--- /dev/null
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -0,0 +1,3 @@
+# Empty file waiting for deletion once Makefile.boot isn't needed any more.
+# Patch waits for application at
+# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
diff --git a/arch/arm/mach-at91/samx7.c b/arch/arm/mach-at91/samx7.c
new file mode 100644
index 000000000000..bd33bc56278e
--- /dev/null
+++ b/arch/arm/mach-at91/samx7.c
@@ -0,0 +1,62 @@
+/*
+ * Setup code for SAMx7
+ *
+ * Copyright (C) 2013 Atmel,
+ * 2016 Andras Szemzo <szemzo.andras@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/system_misc.h>
+#include "generic.h"
+#include "soc.h"
+
+static const struct at91_soc samx7_socs[] = {
+ AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
+ "same70q21", "samx7"),
+ AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,
+ "same70q20", "samx7"),
+ AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,
+ "same70q19", "samx7"),
+ AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,
+ "sams70q21", "samx7"),
+ AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,
+ "sams70q20", "samx7"),
+ AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,
+ "sams70q19", "samx7"),
+ AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,
+ "samv71q21", "samx7"),
+ AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,
+ "samv71q20", "samx7"),
+ AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,
+ "samv71q19", "samx7"),
+ { /* sentinel */ },
+};
+
+static void __init samx7_dt_device_init(void)
+{
+ struct soc_device *soc;
+ struct device *soc_dev = NULL;
+
+ soc = at91_soc_init(samx7_socs);
+ if (soc)
+ soc_dev = soc_device_to_device(soc);
+
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
+}
+
+static const char *const samx7_dt_board_compat[] __initconst = {
+ "atmel,samx7",
+ NULL
+};
+
+DT_MACHINE_START(samx7_dt, "Atmel SAMx7")
+ .init_machine = samx7_dt_device_init,
+ .dt_compat = samx7_dt_board_compat,
+MACHINE_END
+
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 228efded5085..0f97e9c5da7e 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -88,4 +88,25 @@ at91_soc_init(const struct at91_soc *socs);
#define SAMA5D43_EXID_MATCH 0x00000003
#define SAMA5D44_EXID_MATCH 0x00000004
+#define SAME70Q21_CIDR_MATCH 0x21020e00
+#define SAME70Q21_EXID_MATCH 0x00000002
+#define SAME70Q20_CIDR_MATCH 0x21020c00
+#define SAME70Q20_EXID_MATCH 0x00000002
+#define SAME70Q19_CIDR_MATCH 0x210d0a00
+#define SAME70Q19_EXID_MATCH 0x00000002
+
+#define SAMS70Q21_CIDR_MATCH 0x21120e00
+#define SAMS70Q21_EXID_MATCH 0x00000002
+#define SAMS70Q20_CIDR_MATCH 0x21120c00
+#define SAMS70Q20_EXID_MATCH 0x00000002
+#define SAMS70Q19_CIDR_MATCH 0x211d0a00
+#define SAMS70Q19_EXID_MATCH 0x00000002
+
+#define SAMV71Q21_CIDR_MATCH 0x21220e00
+#define SAMV71Q21_EXID_MATCH 0x00000002
+#define SAMV71Q20_CIDR_MATCH 0x21220c00
+#define SAMV71Q20_EXID_MATCH 0x00000002
+#define SAMV71Q19_CIDR_MATCH 0x212d0a00
+#define SAMV71Q19_EXID_MATCH 0x00000002
+
#endif /* __AT91_SOC_H */
--
2.9.3
^ permalink raw reply related
* [PATCH 0/4] ARM: at91: initial samx7 support
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series adds initial support for Atmel armv7m SoCs.
Most of the work has been done and tested by Andr?s, thanks!
Alexandre Belloni (1):
ARM: at91: handle CONFIG_PM for armv7m configurations
Szemz? Andr?s (3):
ARM: at91: Add armv7m support
ARM: dts: at91: add samx7 dtsi
ARM: at91: debug: add samx7 support
arch/arm/Kconfig.debug | 10 +
arch/arm/boot/dts/samx7.dtsi | 1166 ++++++++++++++++++++++++++++++++++++++
arch/arm/mach-at91/Kconfig | 15 +-
arch/arm/mach-at91/Makefile | 4 +-
arch/arm/mach-at91/Makefile.boot | 3 +
arch/arm/mach-at91/samx7.c | 72 +++
arch/arm/mach-at91/soc.h | 21 +
7 files changed, 1288 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boot/dts/samx7.dtsi
create mode 100644 arch/arm/mach-at91/Makefile.boot
create mode 100644 arch/arm/mach-at91/samx7.c
--
2.9.3
^ permalink raw reply
* [PATCH V6 3/5] PCI: thunder-pem: Allow to probe PEM-specific register range for ACPI case
From: Bjorn Helgaas @ 2016-09-22 22:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922183101.GA14510@localhost>
On Thu, Sep 22, 2016 at 01:31:01PM -0500, Bjorn Helgaas wrote:
> On Thu, Sep 22, 2016 at 01:44:46PM +0100, Lorenzo Pieralisi wrote:
> > On Thu, Sep 22, 2016 at 11:10:13AM +0000, Gabriele Paoloni wrote:
> > > Hi Lorenzo, Bjorn
> > >
> > > > -----Original Message-----
> > > > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi at arm.com]
> > > > Sent: 22 September 2016 10:50
> > > > To: Bjorn Helgaas
> > > > Cc: Ard Biesheuvel; Tomasz Nowicki; David Daney; Will Deacon; Catalin
> > > > Marinas; Rafael Wysocki; Arnd Bergmann; Hanjun Guo; Sinan Kaya;
> > > > Jayachandran C; Christopher Covington; Duc Dang; Robert Richter; Marcin
> > > > Wojtas; Liviu Dudau; Wangyijing; Mark Salter; linux-
> > > > pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Linaro ACPI
> > > > Mailman List; Jon Masters; Andrea Gallo; Jeremy Linton; liudongdong
> > > > (C); Gabriele Paoloni; Jeff Hugo; linux-acpi at vger.kernel.org; linux-
> > > > kernel at vger.kernel.org; Rafael J. Wysocki
> > > > Subject: Re: [PATCH V6 3/5] PCI: thunder-pem: Allow to probe PEM-
> > > > specific register range for ACPI case
> > > >
> > > > On Wed, Sep 21, 2016 at 01:04:57PM -0500, Bjorn Helgaas wrote:
> > > > > On Wed, Sep 21, 2016 at 03:05:49PM +0100, Lorenzo Pieralisi wrote:
> > > > > > On Tue, Sep 20, 2016 at 02:17:44PM -0500, Bjorn Helgaas wrote:
> > > > > > > On Tue, Sep 20, 2016 at 04:09:25PM +0100, Ard Biesheuvel wrote:
> > > > > >
> > > > > > [...]
> > > > > >
> > > > > > > > None of these platforms can be fixed entirely in software, and
> > > > given
> > > > > > > > that we will not be adding quirks for new broken hardware, we
> > > > should
> > > > > > > > ask ourselves whether having two versions of a quirk, i.e., one
> > > > for
> > > > > > > > broken hardware + currently shipping firmware, and one for the
> > > > same
> > > > > > > > broken hardware with fixed firmware is really an improvement
> > > > over what
> > > > > > > > has been proposed here.
> > > > > > >
> > > > > > > We're talking about two completely different types of quirks:
> > > > > > >
> > > > > > > 1) MCFG quirks to use memory-mapped config space that doesn't
> > > > quite
> > > > > > > conform to the ECAM model in the PCIe spec, and
> > > > > > >
> > > > > > > 2) Some yet-to-be-determined method to describe address space
> > > > > > > consumed by a bridge.
> > > > > > >
> > > > > > > The first two patches of this series are a nice implementation
> > > > for 1).
> > > > > > > The third patch (ThunderX-specific) is one possibility for 2),
> > > > but I
> > > > > > > don't like it because there's no way for generic software like
> > > > the
> > > > > > > ACPI core to discover these resources.
> > > > > >
> > > > > > Ok, so basically this means that to implement (2) we need to assign
> > > > > > some sort of _HID to these quirky PCI bridges (so that we know what
> > > > > > device they represent and we can retrieve their _CRS). I take from
> > > > > > this discussion that the goal is to make sure that all non-config
> > > > > > resources have to be declared through _CRS device objects, which is
> > > > > > fine but that requires a FW update (unless we can fabricate ACPI
> > > > > > devices and corresponding _CRS in the kernel whenever we match a
> > > > > > given MCFG table signature).
> > > > >
> > > > > All resources consumed by ACPI devices should be declared through
> > > > > _CRS. If you want to fabricate ACPI devices or _CRS via kernel
> > > > > quirks, that's fine with me. This could be triggered via MCFG
> > > > > signature, DMI info, host bridge _HID, etc.
> > > >
> > > > I think the PNP quirk approach + PNP0c02 resource put forward by Gab
> > > > is enough.
> > >
> > > Great thanks as we take a final decision I will ask Dogndgong to submit
> > > another RFC based on this approach
> > >
> > > >
> > > > > > We discussed this already and I think we should make a decision:
> > > > > >
> > > > > > http://lists.infradead.org/pipermail/linux-arm-kernel/2016-
> > > > March/414722.html
> > > > > >
> > > > > > > > > I'd like to step back and come up with some understanding of
> > > > how
> > > > > > > > > non-broken firmware *should* deal with this issue. Then, if
> > > > we *do*
> > > > > > > > > work around this particular broken firmware in the kernel, it
> > > > would be
> > > > > > > > > nice to do it in a way that fits in with that understanding.
> > > > > > > > >
> > > > > > > > > For example, if a companion ACPI device is the preferred
> > > > solution, an
> > > > > > > > > ACPI quirk could fabricate a device with the required
> > > > resources. That
> > > > > > > > > would address the problem closer to the source and make it
> > > > more likely
> > > > > > > > > that the rest of the system will work correctly: /proc/iomem
> > > > could
> > > > > > > > > make sense, things that look at _CRS generically would work
> > > > (e.g,
> > > > > > > > > /sys/, an admittedly hypothetical "lsacpi", etc.)
> > > > > > > > >
> > > > > > > > > Hard-coding stuff in drivers is a point solution that doesn't
> > > > provide
> > > > > > > > > any guidance for future platforms and makes it likely that
> > > > the hack
> > > > > > > > > will get copied into even more drivers.
> > > > > > > > >
> > > > > > > >
> > > > > > > > OK, I see. But the guidance for future platforms should be 'do
> > > > not
> > > > > > > > rely on quirks', and what I am arguing here is that the more we
> > > > polish
> > > > > > > > up this code and make it clean and reusable, the more likely it
> > > > is
> > > > > > > > that will end up getting abused by new broken hardware that we
> > > > set out
> > > > > > > > to reject entirely in the first place.
> > > > > > > >
> > > > > > > > So of course, if the quirk involves claiming resources, let's
> > > > make
> > > > > > > > sure that this occurs in the cleanest and most compliant way
> > > > possible.
> > > > > > > > But any factoring/reuse concerns other than for the current
> > > > crop of
> > > > > > > > broken hardware should be avoided imo.
> > > > > > >
> > > > > > > If future hardware is completely ECAM-compliant and we don't need
> > > > any
> > > > > > > more MCFG quirks, that would be great.
> > > > > >
> > > > > > Yes.
> > > > > >
> > > > > > > But we'll still need to describe that memory-mapped config space
> > > > > > > somewhere. If that's done with PNP0C02 or similar devices (as is
> > > > done
> > > > > > > on my x86 laptop), we'd be all set.
> > > > > >
> > > > > > I am not sure I understand what you mean here. Are you referring
> > > > > > to MCFG regions reported as PNP0c02 resources through its _CRS ?
> > > > >
> > > > > Yes. PCI Firmware Spec r3.0, Table 4-2, note 2 says address ranges
> > > > > reported via MCFG or _CBA should be reserved by _CRS of a PNP0C02
> > > > > device.
> > > >
> > > > Ok, that's agreed. It goes without saying that since you are quoting
> > > > the PCI spec, if FW fails to report MCFG regions in a PNP0c02 device
> > > > _CRS I will consider that a FW bug.
> > > >
> > > > > > IIUC PNP0C02 is a reservation mechanism, but it does not help us
> > > > > > associate its _CRS to a specific PCI host bridge instance, right ?
> > > > >
> > > > > Gab proposed a hierarchy that *would* associate a PNP0C02 device with
> > > > > a PCI bridge:
> > > > >
> > > > > Device (PCI1) {
> > > > > Name (_HID, "HISI0080") // PCI Express Root Bridge
> > > > > Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
> > > > > Method (_CRS, 0, Serialized) { // Root complex resources
> > > > (windows) }
> > > > > Device (RES0) {
> > > > > Name (_HID, "HISI0081") // HiSi PCIe RC config base address
> > > > > Name (_CID, "PNP0C02") // Motherboard reserved resource
> > > > > Name (_CRS, ResourceTemplate () { ... }
> > > > > }
> > > > > }
> > > > >
> > > > > That's a possibility. The PCI Firmware Spec suggests putting RES0 at
> > > > > the root (under \_SB), but I don't know why.
> > > > >
> > > > > Putting it at the root means we couldn't generically associate it
> > > > with
> > > > > a bridge, although I could imagine something like this:
> > > > >
> > > > > Device (RES1) {
> > > > > Name (_HID, "HISI0081") // HiSi PCIe RC config base address
> > > > > Name (_CID, "PNP0C02") // Motherboard reserved resource
> > > > > Name (_CRS, ResourceTemplate () { ... }
> > > > > Method (BRDG) { "PCI1" } // hand-wavy ASL
> > > > > }
> > > > > Device (PCI1) {
> > > > > Name (_HID, "HISI0080") // PCI Express Root Bridge
> > > > > Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
> > > > > Method (_CRS, 0, Serialized) { // Root complex resources
> > > > (windows) }
> > > > > }
> > > > >
> > > > > Where you could search PNP0C02 devices for a cookie that matched the
> > > > > host bridge.o
> > > >
> > > > Ok, I am fine with both and I think we are converging, but the way
> > > > to solve this problem has to be uniform for all ARM partners (and
> > > > not only ARM). Two points here:
> > > >
> > > > 1) Adding a device/subdevice allows people to add a _CRS reporting the
> > > > non-window bridge resources. Fine. It also allows people to chuck in
> > > > there all sorts of _DSD properties to describe their PCI host bridge
> > > > as it is done with DT properties (those _DSD can contain eg clocks
> > > > etc.), this may be tempting (so that they can reuse the same DT
> > > > driver and do not have to update their firmware) but I want to be
> > > > clear here: that must not happen. So, a subdevice with a _CRS to
> > > > report resources, yes, but it will stop there.
> > > > 2) It is unclear to me how to formalize the above. People should not
> > > > write FW by reading the PCI mailing list, so these guidelines have
> > > > to
> > > > be written, somehow. I do not want to standardize quirks, I want
> > > > to prevent random ACPI table content, which is different.
> > > > Should I report this to the ACPI spec working group ? If we do
> > > > not do that everyone will go solve this problem as they deem fit.
> > > >
> > >
> > > Do we really need to formalize this?
> > >
> > > As we discussed in the Linaro call at the moment we have few vendors
> > > that need quirks and we want to avoid promoting/accepting quirks for
> > > the future.
> > >
> > > At the time of the call I think we decided to informally accept a set
> > > of quirks for the current platforms and reject any other quirk coming
> > > after a certain date/kernel version (this to be decided).
> > >
> > > I am not sure if there is a way to document/formalize a temporary
> > > exception from the rule...
> >
> > - (1) will be enforced.
>
> I'm not sure it's necessary or possible to enforce a "no future
> quirks" rule. For one thing, there's already a pretty strong
> incentive to avoid quirks: if your hardware doesn't require quirks,
> it works with OSes already in the field.
>
> MCFG quirks allow us to use the generic ACPI pci_root.c driver even if
> the hardware doesn't support ECAM quite according to the spec.
>
> PNP0C02 usage is a workaround for the failure of the Consumer/Producer
> bit. PNP0C02 quirks compensate for firmware that doesn't describe
> resource usage accurately. It's possible the ACPI spec folks could
> come up with a better Consumer/Producer workaround, if that's needed.
> Apparently x86 hasn't needed it yet.
>
> If people add _DSD methods for clocks or whatnot, the hardware won't
> work with the generic pci_root.c driver, so there's already an
> incentive for avoiding them. x86 has managed without such methods;
> arm64 should be able to do the same.
Re-reading this, I'm afraid my response sounds a little dismissive,
and I feel like I'm missing some important information. So I
apologize if I missed your whole point, Lorenzo.
Bjorn
^ permalink raw reply
* [PATCH v5] KVM: arm/arm64: Route vtimer events to user space
From: Christoffer Dall @ 2016-09-22 21:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474548769-195643-1-git-send-email-agraf@suse.de>
On Thu, Sep 22, 2016 at 02:52:49PM +0200, Alexander Graf wrote:
> We have 2 modes for dealing with interrupts in the ARM world. We can either
> handle them all using hardware acceleration through the vgic or we can emulate
> a gic in user space and only drive CPU IRQ pins from there.
>
> Unfortunately, when driving IRQs from user space, we never tell user space
> about timer events that may result in interrupt line state changes, so we
> lose out on timer events if we run with user space gic emulation.
>
> This patch fixes that by syncing user space's view of the vtimer irq line
> with the kvm view of that same line.
>
> With this patch I can successfully run edk2 and Linux with user space gic
> emulation.
>
> Signed-off-by: Alexander Graf <agraf@suse.de>
>
> ---
>
> v1 -> v2:
>
> - Add back curly brace that got lost
>
> v2 -> v3:
>
> - Split into patch set
>
> v3 -> v4:
>
> - Improve documentation
>
> v4 -> v5:
>
> - Rewrite to use pending state sync in sregs (marc)
> - Remove redundant checks of vgic_initialized()
> - qemu tree to try this out: https://github.com/agraf/u-boot.git no-kvm-irqchip-for-v5
huh, qemu=u-boot?
> ---
> Documentation/virtual/kvm/api.txt | 26 ++++++++
> arch/arm/include/uapi/asm/kvm.h | 3 +
> arch/arm/kvm/arm.c | 14 ++---
> arch/arm64/include/uapi/asm/kvm.h | 3 +
> include/kvm/arm_arch_timer.h | 2 +-
> include/uapi/linux/kvm.h | 6 ++
> virt/kvm/arm/arch_timer.c | 129 ++++++++++++++++++++++++++------------
> 7 files changed, 134 insertions(+), 49 deletions(-)
>
> diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
> index 739db9a..8049327 100644
> --- a/Documentation/virtual/kvm/api.txt
> +++ b/Documentation/virtual/kvm/api.txt
> @@ -3928,3 +3928,29 @@ In order to use SynIC, it has to be activated by setting this
> capability via KVM_ENABLE_CAP ioctl on the vcpu fd. Note that this
> will disable the use of APIC hardware virtualization even if supported
> by the CPU, as it's incompatible with SynIC auto-EOI behavior.
> +
> +8.3 KVM_CAP_ARM_TIMER
> +
> +Architectures: arm, arm64
> +This capability, if KVM_CHECK_EXTENSION indicates that it is available and no
> +in-kernel interrupt controller is in use, means that that the kernel populates
> +the vcpu's run->s.regs.kernel_timer_pending field with timers that are currently
> +considered pending by kvm.
Be careful with the word 'pending' here. I think this could be
misleading, because pending is a state in the GIC, but not really
something I can find specific to the timer. It would be more
descriptive to say that the kernel maintained generic timer's output
signal is asserted.
> +
> +If active, it also allows user space to propagate its own pending state of timer
> +interrupt lines using run->s.regs.user_timer_pending. If those two fields
> +mismatch during CPU execution, kvm will exit to user space to give it a chance
I don't quite understand the semantics here. The only entity that knows
what the level state of the output of the timer is, is the kernel, which
emulates the timer. Userspace knows interrupt controller state, but if
it has a different view of the timer state than the kernel, it's because
the kernel failed to notify userspace of a change or userspace failed to
listen?
> +to update its own interrupt pending status. This usually involves triggering
> +an interrupt line on a user space emulated interrupt controller.
To me it feels like the semantics should be that userspace can always
derive the status of the timer and the level of the output signal from
the timer by simply looking at kvm_run structure.
The remaining two problems are:
(1) when should the kernel trigger exits to userspace? Presumably on
any change in the timer's output level, because this change has to be
propagated to the userspace interrupt controller.
(2) the kernel needs to somehow mask the underlying hardware timer
interrupt signal when it's active, because otherwise the guest won't
proceed. If we simply mask the hardware signal after telling userspace
the output signal is asserted and until the output signal ever becomes
deasserted, why do we need to listen to anything userspace has to say?
> +
> +The fields run->s.regs.kernel_timer_pending and run->s.regs.user_timer_pending
> +are available independent of run->kvm_valid_regs or run->kvm_dirty_regs bits.
> +If no in-kernel interrupt controller is used and the capability exists, they
> +will always be available and used.
> +
> +Currently the following bits are defined for both bitmaps:
> +
> + KVM_ARM_TIMER_VTIMER - virtual timer
> +
> +Future versions of kvm may implement additional timer events. These will get
> +indicated by additional KVM_CAP extensions.
> diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
> index a2b3eb3..caad81d 100644
> --- a/arch/arm/include/uapi/asm/kvm.h
> +++ b/arch/arm/include/uapi/asm/kvm.h
> @@ -105,6 +105,9 @@ struct kvm_debug_exit_arch {
> };
>
> struct kvm_sync_regs {
> + /* Used with KVM_CAP_ARM_TIMER */
> + u8 kernel_timer_pending;
> + u8 user_timer_pending;
> };
>
> struct kvm_arch_memory_slot {
> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> index 75f130e..dc19221 100644
> --- a/arch/arm/kvm/arm.c
> +++ b/arch/arm/kvm/arm.c
> @@ -187,6 +187,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
> case KVM_CAP_ARM_PSCI_0_2:
> case KVM_CAP_READONLY_MEM:
> case KVM_CAP_MP_STATE:
> + case KVM_CAP_ARM_TIMER:
> r = 1;
> break;
> case KVM_CAP_COALESCED_MMIO:
> @@ -474,13 +475,7 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
> return ret;
> }
>
> - /*
> - * Enable the arch timers only if we have an in-kernel VGIC
> - * and it has been properly initialized, since we cannot handle
> - * interrupts from the virtual timer with a userspace gic.
> - */
> - if (irqchip_in_kernel(kvm) && vgic_initialized(kvm))
> - ret = kvm_timer_enable(vcpu);
> + ret = kvm_timer_enable(vcpu);
>
> return ret;
> }
> @@ -588,7 +583,10 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
> */
> preempt_disable();
> kvm_pmu_flush_hwstate(vcpu);
> - kvm_timer_flush_hwstate(vcpu);
> + if (kvm_timer_flush_hwstate(vcpu)) {
> + ret = -EINTR;
> + run->exit_reason = KVM_EXIT_INTR;
> + }
> kvm_vgic_flush_hwstate(vcpu);
>
> local_irq_disable();
> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
> index 3051f86..9aac860 100644
> --- a/arch/arm64/include/uapi/asm/kvm.h
> +++ b/arch/arm64/include/uapi/asm/kvm.h
> @@ -143,6 +143,9 @@ struct kvm_debug_exit_arch {
> #define KVM_GUESTDBG_USE_HW (1 << 17)
>
> struct kvm_sync_regs {
> + /* Used with KVM_CAP_ARM_TIMER */
> + u8 kernel_timer_pending;
> + u8 user_timer_pending;
> };
>
> struct kvm_arch_memory_slot {
> diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
> index dda39d8..8cd7240 100644
> --- a/include/kvm/arm_arch_timer.h
> +++ b/include/kvm/arm_arch_timer.h
> @@ -63,7 +63,7 @@ void kvm_timer_init(struct kvm *kvm);
> int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
> const struct kvm_irq_level *irq);
> void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
> -void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
> +int kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
> void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
> void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
>
> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> index 300ef25..1fc02d7 100644
> --- a/include/uapi/linux/kvm.h
> +++ b/include/uapi/linux/kvm.h
> @@ -870,6 +870,7 @@ struct kvm_ppc_smmu_info {
> #define KVM_CAP_S390_USER_INSTR0 130
> #define KVM_CAP_MSI_DEVID 131
> #define KVM_CAP_PPC_HTM 132
> +#define KVM_CAP_ARM_TIMER 133
>
> #ifdef KVM_CAP_IRQ_ROUTING
>
> @@ -1327,4 +1328,9 @@ struct kvm_assigned_msix_entry {
> #define KVM_X2APIC_API_USE_32BIT_IDS (1ULL << 0)
> #define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK (1ULL << 1)
>
> +/* Available with KVM_CAP_ARM_TIMER */
> +
> +/* Bits for run->s.regs.{user,kernel}_timer_pending */
> +#define KVM_ARM_TIMER_VTIMER (1 << 0)
> +
> #endif /* __LINUX_KVM_H */
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index 4309b60..0c6fc38 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -166,21 +166,36 @@ bool kvm_timer_should_fire(struct kvm_vcpu *vcpu)
> return cval <= now;
> }
>
> +/*
> + * Synchronize the timer IRQ state with the interrupt controller.
> + */
> static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
> {
> int ret;
> struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
>
> - BUG_ON(!vgic_initialized(vcpu->kvm));
> -
> timer->active_cleared_last = false;
> timer->irq.level = new_level;
> - trace_kvm_timer_update_irq(vcpu->vcpu_id, timer->irq.irq,
> + trace_kvm_timer_update_irq(vcpu->vcpu_id, host_vtimer_irq,
> timer->irq.level);
> - ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id,
> - timer->irq.irq,
> - timer->irq.level);
> - WARN_ON(ret);
> +
> + if (irqchip_in_kernel(vcpu->kvm)) {
> + BUG_ON(!vgic_initialized(vcpu->kvm));
> +
> + /* Fire the timer in the VGIC */
> + ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id,
> + timer->irq.irq,
> + timer->irq.level);
> +
> + WARN_ON(ret);
> + } else {
> + struct kvm_sync_regs *regs = &vcpu->run->s.regs;
> +
> + /* Populate the timer bitmap for user space */
> + regs->kernel_timer_pending &= ~KVM_ARM_TIMER_VTIMER;
> + if (new_level)
> + regs->kernel_timer_pending |= KVM_ARM_TIMER_VTIMER;
I think if you got here, it means you have to exit to userspace to
update it of the new state. If you don't want to propagate a return
value from here, I think you should just not do anything an then later
compare timer->irq.level with whatever was last written to
run->kernel_timer_pending (which should be named something else than
pending).
> + }
> }
>
> /*
> @@ -197,7 +212,8 @@ static int kvm_timer_update_state(struct kvm_vcpu *vcpu)
> * because the guest would never see the interrupt. Instead wait
> * until we call this function from kvm_timer_flush_hwstate.
> */
> - if (!vgic_initialized(vcpu->kvm) || !timer->enabled)
> + if ((irqchip_in_kernel(vcpu->kvm) && !vgic_initialized(vcpu->kvm)) ||
> + !timer->enabled)
> return -ENODEV;
>
> if (kvm_timer_should_fire(vcpu) != timer->irq.level)
> @@ -248,15 +264,20 @@ void kvm_timer_unschedule(struct kvm_vcpu *vcpu)
> *
> * Check if the virtual timer has expired while we were running in the host,
> * and inject an interrupt if that was the case.
> + *
> + * Returns:
> + *
> + * 0 - success
> + * 1 - need exit to user space
this is opposite to all other exit-related APIs we have. Why not just
return -EINTR?
> */
> -void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
> +int kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
> {
> struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
> bool phys_active;
> int ret;
>
> if (kvm_timer_update_state(vcpu))
> - return;
> + return 0;
>
> /*
> * If we enter the guest with the virtual input level to the VGIC
> @@ -275,38 +296,61 @@ void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
> * to ensure that hardware interrupts from the timer triggers a guest
> * exit.
> */
> - phys_active = timer->irq.level ||
> - kvm_vgic_map_is_active(vcpu, timer->irq.irq);
> -
> - /*
> - * We want to avoid hitting the (re)distributor as much as
> - * possible, as this is a potentially expensive MMIO access
> - * (not to mention locks in the irq layer), and a solution for
> - * this is to cache the "active" state in memory.
> - *
> - * Things to consider: we cannot cache an "active set" state,
> - * because the HW can change this behind our back (it becomes
> - * "clear" in the HW). We must then restrict the caching to
> - * the "clear" state.
> - *
> - * The cache is invalidated on:
> - * - vcpu put, indicating that the HW cannot be trusted to be
> - * in a sane state on the next vcpu load,
> - * - any change in the interrupt state
> - *
> - * Usage conditions:
> - * - cached value is "active clear"
> - * - value to be programmed is "active clear"
> - */
> - if (timer->active_cleared_last && !phys_active)
> - return;
> -
> - ret = irq_set_irqchip_state(host_vtimer_irq,
> - IRQCHIP_STATE_ACTIVE,
> - phys_active);
> - WARN_ON(ret);
> + if (irqchip_in_kernel(vcpu->kvm)) {
> + phys_active = timer->irq.level ||
> + kvm_vgic_map_is_active(vcpu, timer->irq.irq);
> +
> + /*
> + * We want to avoid hitting the (re)distributor as much as
> + * possible, as this is a potentially expensive MMIO access
> + * (not to mention locks in the irq layer), and a solution for
> + * this is to cache the "active" state in memory.
> + *
> + * Things to consider: we cannot cache an "active set" state,
> + * because the HW can change this behind our back (it becomes
> + * "clear" in the HW). We must then restrict the caching to
> + * the "clear" state.
> + *
> + * The cache is invalidated on:
> + * - vcpu put, indicating that the HW cannot be trusted to be
> + * in a sane state on the next vcpu load,
> + * - any change in the interrupt state
> + *
> + * Usage conditions:
> + * - cached value is "active clear"
> + * - value to be programmed is "active clear"
> + */
> + if (timer->active_cleared_last && !phys_active)
> + return 0;
> +
> + ret = irq_set_irqchip_state(host_vtimer_irq,
> + IRQCHIP_STATE_ACTIVE,
> + phys_active);
> + WARN_ON(ret);
> + } else {
> + struct kvm_sync_regs *regs = &vcpu->run->s.regs;
> +
> + /*
> + * User space handles timer events, so we need to check whether
> + * its view of the world is in sync with ours.
> + */
> + if (regs->kernel_timer_pending != regs->user_timer_pending) {
> + /* Return to user space */
> + return 1;
> + }
Maybe I'm misunderstanding and user_timer_pending is just a cached
verison of what you said last, but as I said above, I think you can just
compare timer->irq.level with the last value the kvm_run struct, and if
something changed, you have to exit.
> +
> + /*
> + * As long as user space is aware that the timer is pending,
> + * we do not need to get new host timer events.
> + */
yes, correct, but I don't think this concept was clearly reflected in
your API text above.
> + if (timer->irq.level)
> + disable_percpu_irq(host_vtimer_irq);
> + else
> + enable_percpu_irq(host_vtimer_irq, 0);
> + }
could we move these two blocks into their own functions instead? That
would also give nice names to the huge chunk of complicated
functionality, e.g. flush_timer_state_to_user() and
flush_timer_state_to_vgic().
>
> timer->active_cleared_last = !phys_active;
> + return 0;
> }
>
> /**
> @@ -479,6 +523,10 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
> if (timer->enabled)
> return 0;
>
> + /* No need to route physical IRQs when we don't use the vgic */
> + if (!irqchip_in_kernel(vcpu->kvm))
> + goto no_vgic;
> +
> /*
> * Find the physical IRQ number corresponding to the host_vtimer_irq
> */
> @@ -502,6 +550,7 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
> if (ret)
> return ret;
>
> +no_vgic:
>
> /*
> * There is a potential race here between VCPUs starting for the first
> --
> 1.8.5.6
>
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH 0/2] Add R8A7792 MSIOF support
From: Sergei Shtylyov @ 2016-09-22 21:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2481458.x1iQg26kO7@wasted.cogentembedded.com>
Hello.
On 09/05/2016 11:54 PM, Sergei Shtylyov wrote:
> Here's the set of 2 patches against Simon Horman's 'renesas.git' repo,
> 'renesas-devel-20160905-v4.8-rc5' tag. We're adding the R8A7792 MSIOF clocks
> and device nodes. I'm not posting the board patches because the MSIOF driver
> seems erratic ATM...
>
> [1/2] ARM: dts: r8a7792: add MSIOF clock
> [2/2] ARM: dts: r8a7792: add MSIOF support
These seem stuck for no apparent reason. Simon?
WBR, Sergei
^ permalink raw reply
* [PATCH 08/15] perf tools: Add sink configuration for cs_etm PMU
From: Arnaldo Carvalho de Melo @ 2016-09-22 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474578779-14095-1-git-send-email-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
Using the PMU::set_drv_config() callback to enable the CoreSight sink
that will be used for the trace session.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/1474041004-13956-8-git-send-email-mathieu.poirier at linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/arch/arm/util/cs-etm.c | 58 +++++++++++++++++++++++++++++++++++++++
tools/perf/arch/arm/util/cs-etm.h | 3 ++
tools/perf/arch/arm/util/pmu.c | 2 ++
3 files changed, 63 insertions(+)
diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c
index 829c479614f1..47d584da5819 100644
--- a/tools/perf/arch/arm/util/cs-etm.c
+++ b/tools/perf/arch/arm/util/cs-etm.c
@@ -27,12 +27,16 @@
#include "../../util/auxtrace.h"
#include "../../util/cpumap.h"
#include "../../util/evlist.h"
+#include "../../util/evsel.h"
#include "../../util/pmu.h"
#include "../../util/thread_map.h"
#include "../../util/cs-etm.h"
#include <stdlib.h>
+#define ENABLE_SINK_MAX 128
+#define CS_BUS_DEVICE_PATH "/bus/coresight/devices/"
+
struct cs_etm_recording {
struct auxtrace_record itr;
struct perf_pmu *cs_etm_pmu;
@@ -557,3 +561,57 @@ struct auxtrace_record *cs_etm_record_init(int *err)
out:
return NULL;
}
+
+static FILE *cs_device__open_file(const char *name)
+{
+ struct stat st;
+ char path[PATH_MAX];
+ const char *sysfs;
+
+ sysfs = sysfs__mountpoint();
+ if (!sysfs)
+ return NULL;
+
+ snprintf(path, PATH_MAX,
+ "%s" CS_BUS_DEVICE_PATH "%s", sysfs, name);
+
+ printf("path: %s\n", path);
+
+ if (stat(path, &st) < 0)
+ return NULL;
+
+ return fopen(path, "w");
+
+}
+
+static __attribute__((format(printf, 2, 3)))
+int cs_device__print_file(const char *name, const char *fmt, ...)
+{
+ va_list args;
+ FILE *file;
+ int ret = -EINVAL;
+
+ va_start(args, fmt);
+ file = cs_device__open_file(name);
+ if (file) {
+ ret = vfprintf(file, fmt, args);
+ fclose(file);
+ }
+ va_end(args);
+ return ret;
+}
+
+int cs_etm_set_drv_config(struct perf_evsel_config_term *term)
+{
+ int ret;
+ char enable_sink[ENABLE_SINK_MAX];
+
+ snprintf(enable_sink, ENABLE_SINK_MAX, "%s/%s",
+ term->val.drv_cfg, "enable_sink");
+
+ ret = cs_device__print_file(enable_sink, "%d", 1);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
diff --git a/tools/perf/arch/arm/util/cs-etm.h b/tools/perf/arch/arm/util/cs-etm.h
index 909f486d02d1..5256741be549 100644
--- a/tools/perf/arch/arm/util/cs-etm.h
+++ b/tools/perf/arch/arm/util/cs-etm.h
@@ -18,6 +18,9 @@
#ifndef INCLUDE__PERF_CS_ETM_H__
#define INCLUDE__PERF_CS_ETM_H__
+#include "../../util/evsel.h"
+
struct auxtrace_record *cs_etm_record_init(int *err);
+int cs_etm_set_drv_config(struct perf_evsel_config_term *term);
#endif
diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c
index af9fb666b44f..98d67399a0d6 100644
--- a/tools/perf/arch/arm/util/pmu.c
+++ b/tools/perf/arch/arm/util/pmu.c
@@ -19,6 +19,7 @@
#include <linux/coresight-pmu.h>
#include <linux/perf_event.h>
+#include "cs-etm.h"
#include "../../util/pmu.h"
struct perf_event_attr
@@ -28,6 +29,7 @@ struct perf_event_attr
if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) {
/* add ETM default config here */
pmu->selectable = true;
+ pmu->set_drv_config = cs_etm_set_drv_config;
}
#endif
return NULL;
--
2.7.4
^ permalink raw reply related
* [PATCH 07/15] perf tools: Add PMU configuration to tools
From: Arnaldo Carvalho de Melo @ 2016-09-22 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474578779-14095-1-git-send-email-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
Now that the required mechanic is there to deal with PMU specific
configuration, add the functionality to the tools where events can be
selected.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/1474041004-13956-7-git-send-email-mathieu.poirier at linaro.org
[ Fix the build on XSI-compliant systems, using str_error_r() to make sure we return a string, not an integer ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/builtin-record.c | 10 ++++++++++
tools/perf/builtin-stat.c | 9 +++++++++
tools/perf/builtin-top.c | 13 +++++++++++++
3 files changed, 32 insertions(+)
diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c
index 03251c7f14ec..2d0d69be3bf8 100644
--- a/tools/perf/builtin-record.c
+++ b/tools/perf/builtin-record.c
@@ -22,6 +22,7 @@
#include "util/evlist.h"
#include "util/evsel.h"
#include "util/debug.h"
+#include "util/drv_configs.h"
#include "util/session.h"
#include "util/tool.h"
#include "util/symbol.h"
@@ -383,6 +384,7 @@ static int record__open(struct record *rec)
struct perf_evlist *evlist = rec->evlist;
struct perf_session *session = rec->session;
struct record_opts *opts = &rec->opts;
+ struct perf_evsel_config_term *err_term;
int rc = 0;
perf_evlist__config(evlist, opts, &callchain_param);
@@ -412,6 +414,14 @@ try_again:
goto out;
}
+ if (perf_evlist__apply_drv_configs(evlist, &pos, &err_term)) {
+ error("failed to set config \"%s\" on event %s with %d (%s)\n",
+ err_term->val.drv_cfg, perf_evsel__name(pos), errno,
+ str_error_r(errno, msg, sizeof(msg)));
+ rc = -1;
+ goto out;
+ }
+
rc = record__mmap(rec);
if (rc)
goto out;
diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
index 90882b1d6a91..688dea7cb08f 100644
--- a/tools/perf/builtin-stat.c
+++ b/tools/perf/builtin-stat.c
@@ -52,6 +52,7 @@
#include "util/evlist.h"
#include "util/evsel.h"
#include "util/debug.h"
+#include "util/drv_configs.h"
#include "util/color.h"
#include "util/stat.h"
#include "util/header.h"
@@ -540,6 +541,7 @@ static int __run_perf_stat(int argc, const char **argv)
int status = 0;
const bool forks = (argc > 0);
bool is_pipe = STAT_RECORD ? perf_stat.file.is_pipe : false;
+ struct perf_evsel_config_term *err_term;
if (interval) {
ts.tv_sec = interval / USEC_PER_MSEC;
@@ -611,6 +613,13 @@ try_again:
return -1;
}
+ if (perf_evlist__apply_drv_configs(evsel_list, &counter, &err_term)) {
+ error("failed to set config \"%s\" on event %s with %d (%s)\n",
+ err_term->val.drv_cfg, perf_evsel__name(counter), errno,
+ str_error_r(errno, msg, sizeof(msg)));
+ return -1;
+ }
+
if (STAT_RECORD) {
int err, fd = perf_data_file__fd(&perf_stat.file);
diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c
index 400785702566..fe3af9535e85 100644
--- a/tools/perf/builtin-top.c
+++ b/tools/perf/builtin-top.c
@@ -24,6 +24,7 @@
#include "util/annotate.h"
#include "util/config.h"
#include "util/color.h"
+#include "util/drv_configs.h"
#include "util/evlist.h"
#include "util/evsel.h"
#include "util/machine.h"
@@ -913,6 +914,10 @@ static int callchain_param__setup_sample_type(struct callchain_param *callchain)
static int __cmd_top(struct perf_top *top)
{
+ char msg[512];
+ struct perf_evsel *pos;
+ struct perf_evsel_config_term *err_term;
+ struct perf_evlist *evlist = top->evlist;
struct record_opts *opts = &top->record_opts;
pthread_t thread;
int ret;
@@ -947,6 +952,14 @@ static int __cmd_top(struct perf_top *top)
if (ret)
goto out_delete;
+ ret = perf_evlist__apply_drv_configs(evlist, &pos, &err_term);
+ if (ret) {
+ error("failed to set config \"%s\" on event %s with %d (%s)\n",
+ err_term->val.drv_cfg, perf_evsel__name(pos), errno,
+ str_error_r(errno, msg, sizeof(msg)));
+ goto out_delete;
+ }
+
top->session->evlist = top->evlist;
perf_session__set_id_hdr_size(top->session);
--
2.7.4
^ permalink raw reply related
* [PATCH 06/15] perf pmu: Push configuration down to PMU driver
From: Arnaldo Carvalho de Melo @ 2016-09-22 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474578779-14095-1-git-send-email-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
This patch adds a PMU callback and the required mechanic so that drivers
can process the command line configuration elements found in
evsel::config_terms.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/1474041004-13956-6-git-send-email-mathieu.poirier at linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/util/Build | 1 +
tools/perf/util/drv_configs.c | 77 +++++++++++++++++++++++++++++++++++++++++++
tools/perf/util/drv_configs.h | 26 +++++++++++++++
tools/perf/util/pmu.h | 2 ++
4 files changed, 106 insertions(+)
create mode 100644 tools/perf/util/drv_configs.c
create mode 100644 tools/perf/util/drv_configs.h
diff --git a/tools/perf/util/Build b/tools/perf/util/Build
index 96f99d608d00..eb60e613d795 100644
--- a/tools/perf/util/Build
+++ b/tools/perf/util/Build
@@ -86,6 +86,7 @@ libperf-y += term.o
libperf-y += help-unknown-cmd.o
libperf-y += mem-events.o
libperf-y += vsprintf.o
+libperf-y += drv_configs.o
libperf-$(CONFIG_LIBBPF) += bpf-loader.o
libperf-$(CONFIG_BPF_PROLOGUE) += bpf-prologue.o
diff --git a/tools/perf/util/drv_configs.c b/tools/perf/util/drv_configs.c
new file mode 100644
index 000000000000..1647f285c629
--- /dev/null
+++ b/tools/perf/util/drv_configs.c
@@ -0,0 +1,77 @@
+/*
+ * drv_configs.h: Interface to apply PMU specific configuration
+ * Copyright (c) 2016-2018, Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include "drv_configs.h"
+#include "evlist.h"
+#include "evsel.h"
+#include "pmu.h"
+
+static int
+perf_evsel__apply_drv_configs(struct perf_evsel *evsel,
+ struct perf_evsel_config_term **err_term)
+{
+ bool found = false;
+ int err = 0;
+ struct perf_evsel_config_term *term;
+ struct perf_pmu *pmu = NULL;
+
+ while ((pmu = perf_pmu__scan(pmu)) != NULL)
+ if (pmu->type == evsel->attr.type) {
+ found = true;
+ break;
+ }
+
+ list_for_each_entry(term, &evsel->config_terms, list) {
+ if (term->type != PERF_EVSEL__CONFIG_TERM_DRV_CFG)
+ continue;
+
+ /*
+ * We have a configuration term, report an error if we
+ * can't find the PMU or if the PMU driver doesn't support
+ * cmd line driver configuration.
+ */
+ if (!found || !pmu->set_drv_config) {
+ err = -EINVAL;
+ *err_term = term;
+ break;
+ }
+
+ err = pmu->set_drv_config(term);
+ if (err) {
+ *err_term = term;
+ break;
+ }
+ }
+
+ return err;
+}
+
+int perf_evlist__apply_drv_configs(struct perf_evlist *evlist,
+ struct perf_evsel **err_evsel,
+ struct perf_evsel_config_term **err_term)
+{
+ struct perf_evsel *evsel;
+ int err = 0;
+
+ evlist__for_each_entry(evlist, evsel) {
+ err = perf_evsel__apply_drv_configs(evsel, err_term);
+ if (err) {
+ *err_evsel = evsel;
+ break;
+ }
+ }
+
+ return err;
+}
diff --git a/tools/perf/util/drv_configs.h b/tools/perf/util/drv_configs.h
new file mode 100644
index 000000000000..32bc9babc2e0
--- /dev/null
+++ b/tools/perf/util/drv_configs.h
@@ -0,0 +1,26 @@
+/*
+ * drv_configs.h: Interface to apply PMU specific configuration
+ * Copyright (c) 2016-2018, Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef __PERF_DRV_CONFIGS_H
+#define __PERF_DRV_CONFIGS_H
+
+#include "drv_configs.h"
+#include "evlist.h"
+#include "evsel.h"
+
+int perf_evlist__apply_drv_configs(struct perf_evlist *evlist,
+ struct perf_evsel **err_evsel,
+ struct perf_evsel_config_term **term);
+#endif
diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h
index 5d7e84466bee..743422ad900b 100644
--- a/tools/perf/util/pmu.h
+++ b/tools/perf/util/pmu.h
@@ -4,6 +4,7 @@
#include <linux/bitmap.h>
#include <linux/perf_event.h>
#include <stdbool.h>
+#include "evsel.h"
#include "parse-events.h"
enum {
@@ -25,6 +26,7 @@ struct perf_pmu {
struct list_head format; /* HEAD struct perf_pmu_format -> list */
struct list_head aliases; /* HEAD struct perf_pmu_alias -> list */
struct list_head list; /* ELEM */
+ int (*set_drv_config) (struct perf_evsel_config_term *term);
};
struct perf_pmu_info {
--
2.7.4
^ permalink raw reply related
* [PATCH 05/15] perf tools: Add coresight etm PMU record capabilities
From: Arnaldo Carvalho de Melo @ 2016-09-22 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474578779-14095-1-git-send-email-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
Coresight ETMs are IP blocks used to perform HW assisted tracing on a
CPU core. This patch introduce the required auxiliary API functions
allowing the perf core to interact with a tracer.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/1474041004-13956-4-git-send-email-mathieu.poirier at linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
MAINTAINERS | 4 +
tools/perf/arch/arm/util/Build | 2 +-
tools/perf/arch/arm/util/auxtrace.c | 54 ++++
tools/perf/arch/arm/util/cs-etm.c | 559 ++++++++++++++++++++++++++++++++++++
tools/perf/arch/arm/util/cs-etm.h | 23 ++
tools/perf/arch/arm64/util/Build | 4 +-
tools/perf/util/auxtrace.c | 1 +
tools/perf/util/auxtrace.h | 1 +
tools/perf/util/cs-etm.h | 74 +++++
9 files changed, 720 insertions(+), 2 deletions(-)
create mode 100644 tools/perf/arch/arm/util/auxtrace.c
create mode 100644 tools/perf/arch/arm/util/cs-etm.c
create mode 100644 tools/perf/arch/arm/util/cs-etm.h
create mode 100644 tools/perf/util/cs-etm.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 7407fe779053..ac29d5453750 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1124,6 +1124,10 @@ F: Documentation/trace/coresight.txt
F: Documentation/devicetree/bindings/arm/coresight.txt
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
F: tools/perf/arch/arm/util/pmu.c
+F: tools/perf/arch/arm/util/auxtrace.c
+F: tools/perf/arch/arm/util/cs-etm.c
+F: tools/perf/arch/arm/util/cs-etm.h
+F: tools/perf/util/cs-etm.h
ARM/CORGI MACHINE SUPPORT
M: Richard Purdie <rpurdie@rpsys.net>
diff --git a/tools/perf/arch/arm/util/Build b/tools/perf/arch/arm/util/Build
index 4093fd146f46..e64c5f216448 100644
--- a/tools/perf/arch/arm/util/Build
+++ b/tools/perf/arch/arm/util/Build
@@ -3,4 +3,4 @@ libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
libperf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
-libperf-$(CONFIG_AUXTRACE) += pmu.o
+libperf-$(CONFIG_AUXTRACE) += pmu.o auxtrace.o cs-etm.o
diff --git a/tools/perf/arch/arm/util/auxtrace.c b/tools/perf/arch/arm/util/auxtrace.c
new file mode 100644
index 000000000000..8edf2cb71564
--- /dev/null
+++ b/tools/perf/arch/arm/util/auxtrace.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdbool.h>
+#include <linux/coresight-pmu.h>
+
+#include "../../util/auxtrace.h"
+#include "../../util/evlist.h"
+#include "../../util/pmu.h"
+#include "cs-etm.h"
+
+struct auxtrace_record
+*auxtrace_record__init(struct perf_evlist *evlist, int *err)
+{
+ struct perf_pmu *cs_etm_pmu;
+ struct perf_evsel *evsel;
+ bool found_etm = false;
+
+ cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME);
+
+ if (evlist) {
+ evlist__for_each_entry(evlist, evsel) {
+ if (cs_etm_pmu &&
+ evsel->attr.type == cs_etm_pmu->type)
+ found_etm = true;
+ }
+ }
+
+ if (found_etm)
+ return cs_etm_record_init(err);
+
+ /*
+ * Clear 'err' even if we haven't found a cs_etm event - that way perf
+ * record can still be used even if tracers aren't present. The NULL
+ * return value will take care of telling the infrastructure HW tracing
+ * isn't available.
+ */
+ *err = 0;
+ return NULL;
+}
diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c
new file mode 100644
index 000000000000..829c479614f1
--- /dev/null
+++ b/tools/perf/arch/arm/util/cs-etm.c
@@ -0,0 +1,559 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <api/fs/fs.h>
+#include <linux/bitops.h>
+#include <linux/coresight-pmu.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include <linux/types.h>
+
+#include "cs-etm.h"
+#include "../../perf.h"
+#include "../../util/auxtrace.h"
+#include "../../util/cpumap.h"
+#include "../../util/evlist.h"
+#include "../../util/pmu.h"
+#include "../../util/thread_map.h"
+#include "../../util/cs-etm.h"
+
+#include <stdlib.h>
+
+struct cs_etm_recording {
+ struct auxtrace_record itr;
+ struct perf_pmu *cs_etm_pmu;
+ struct perf_evlist *evlist;
+ bool snapshot_mode;
+ size_t snapshot_size;
+};
+
+static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu);
+
+static int cs_etm_parse_snapshot_options(struct auxtrace_record *itr,
+ struct record_opts *opts,
+ const char *str)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ unsigned long long snapshot_size = 0;
+ char *endptr;
+
+ if (str) {
+ snapshot_size = strtoull(str, &endptr, 0);
+ if (*endptr || snapshot_size > SIZE_MAX)
+ return -1;
+ }
+
+ opts->auxtrace_snapshot_mode = true;
+ opts->auxtrace_snapshot_size = snapshot_size;
+ ptr->snapshot_size = snapshot_size;
+
+ return 0;
+}
+
+static int cs_etm_recording_options(struct auxtrace_record *itr,
+ struct perf_evlist *evlist,
+ struct record_opts *opts)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+ struct perf_evsel *evsel, *cs_etm_evsel = NULL;
+ const struct cpu_map *cpus = evlist->cpus;
+ bool privileged = (geteuid() == 0 || perf_event_paranoid() < 0);
+
+ ptr->evlist = evlist;
+ ptr->snapshot_mode = opts->auxtrace_snapshot_mode;
+
+ evlist__for_each_entry(evlist, evsel) {
+ if (evsel->attr.type == cs_etm_pmu->type) {
+ if (cs_etm_evsel) {
+ pr_err("There may be only one %s event\n",
+ CORESIGHT_ETM_PMU_NAME);
+ return -EINVAL;
+ }
+ evsel->attr.freq = 0;
+ evsel->attr.sample_period = 1;
+ cs_etm_evsel = evsel;
+ opts->full_auxtrace = true;
+ }
+ }
+
+ /* no need to continue if at least one event of interest was found */
+ if (!cs_etm_evsel)
+ return 0;
+
+ if (opts->use_clockid) {
+ pr_err("Cannot use clockid (-k option) with %s\n",
+ CORESIGHT_ETM_PMU_NAME);
+ return -EINVAL;
+ }
+
+ /* we are in snapshot mode */
+ if (opts->auxtrace_snapshot_mode) {
+ /*
+ * No size were given to '-S' or '-m,', so go with
+ * the default
+ */
+ if (!opts->auxtrace_snapshot_size &&
+ !opts->auxtrace_mmap_pages) {
+ if (privileged) {
+ opts->auxtrace_mmap_pages = MiB(4) / page_size;
+ } else {
+ opts->auxtrace_mmap_pages =
+ KiB(128) / page_size;
+ if (opts->mmap_pages == UINT_MAX)
+ opts->mmap_pages = KiB(256) / page_size;
+ }
+ } else if (!opts->auxtrace_mmap_pages && !privileged &&
+ opts->mmap_pages == UINT_MAX) {
+ opts->mmap_pages = KiB(256) / page_size;
+ }
+
+ /*
+ * '-m,xyz' was specified but no snapshot size, so make the
+ * snapshot size as big as the auxtrace mmap area.
+ */
+ if (!opts->auxtrace_snapshot_size) {
+ opts->auxtrace_snapshot_size =
+ opts->auxtrace_mmap_pages * (size_t)page_size;
+ }
+
+ /*
+ * -Sxyz was specified but no auxtrace mmap area, so make the
+ * auxtrace mmap area big enough to fit the requested snapshot
+ * size.
+ */
+ if (!opts->auxtrace_mmap_pages) {
+ size_t sz = opts->auxtrace_snapshot_size;
+
+ sz = round_up(sz, page_size) / page_size;
+ opts->auxtrace_mmap_pages = roundup_pow_of_two(sz);
+ }
+
+ /* Snapshost size can't be bigger than the auxtrace area */
+ if (opts->auxtrace_snapshot_size >
+ opts->auxtrace_mmap_pages * (size_t)page_size) {
+ pr_err("Snapshot size %zu must not be greater than AUX area tracing mmap size %zu\n",
+ opts->auxtrace_snapshot_size,
+ opts->auxtrace_mmap_pages * (size_t)page_size);
+ return -EINVAL;
+ }
+
+ /* Something went wrong somewhere - this shouldn't happen */
+ if (!opts->auxtrace_snapshot_size ||
+ !opts->auxtrace_mmap_pages) {
+ pr_err("Failed to calculate default snapshot size and/or AUX area tracing mmap pages\n");
+ return -EINVAL;
+ }
+ }
+
+ /* We are in full trace mode but '-m,xyz' wasn't specified */
+ if (opts->full_auxtrace && !opts->auxtrace_mmap_pages) {
+ if (privileged) {
+ opts->auxtrace_mmap_pages = MiB(4) / page_size;
+ } else {
+ opts->auxtrace_mmap_pages = KiB(128) / page_size;
+ if (opts->mmap_pages == UINT_MAX)
+ opts->mmap_pages = KiB(256) / page_size;
+ }
+
+ }
+
+ /* Validate auxtrace_mmap_pages provided by user */
+ if (opts->auxtrace_mmap_pages) {
+ unsigned int max_page = (KiB(128) / page_size);
+ size_t sz = opts->auxtrace_mmap_pages * (size_t)page_size;
+
+ if (!privileged &&
+ opts->auxtrace_mmap_pages > max_page) {
+ opts->auxtrace_mmap_pages = max_page;
+ pr_err("auxtrace too big, truncating to %d\n",
+ max_page);
+ }
+
+ if (!is_power_of_2(sz)) {
+ pr_err("Invalid mmap size for %s: must be a power of 2\n",
+ CORESIGHT_ETM_PMU_NAME);
+ return -EINVAL;
+ }
+ }
+
+ if (opts->auxtrace_snapshot_mode)
+ pr_debug2("%s snapshot size: %zu\n", CORESIGHT_ETM_PMU_NAME,
+ opts->auxtrace_snapshot_size);
+
+ if (cs_etm_evsel) {
+ /*
+ * To obtain the auxtrace buffer file descriptor, the auxtrace
+ * event must come first.
+ */
+ perf_evlist__to_front(evlist, cs_etm_evsel);
+ /*
+ * In the case of per-cpu mmaps, we need the CPU on the
+ * AUX event.
+ */
+ if (!cpu_map__empty(cpus))
+ perf_evsel__set_sample_bit(cs_etm_evsel, CPU);
+ }
+
+ /* Add dummy event to keep tracking */
+ if (opts->full_auxtrace) {
+ struct perf_evsel *tracking_evsel;
+ int err;
+
+ err = parse_events(evlist, "dummy:u", NULL);
+ if (err)
+ return err;
+
+ tracking_evsel = perf_evlist__last(evlist);
+ perf_evlist__set_tracking_event(evlist, tracking_evsel);
+
+ tracking_evsel->attr.freq = 0;
+ tracking_evsel->attr.sample_period = 1;
+
+ /* In per-cpu case, always need the time of mmap events etc */
+ if (!cpu_map__empty(cpus))
+ perf_evsel__set_sample_bit(tracking_evsel, TIME);
+ }
+
+ return 0;
+}
+
+static u64 cs_etm_get_config(struct auxtrace_record *itr)
+{
+ u64 config = 0;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+ struct perf_evlist *evlist = ptr->evlist;
+ struct perf_evsel *evsel;
+
+ evlist__for_each_entry(evlist, evsel) {
+ if (evsel->attr.type == cs_etm_pmu->type) {
+ /*
+ * Variable perf_event_attr::config is assigned to
+ * ETMv3/PTM. The bit fields have been made to match
+ * the ETMv3.5 ETRMCR register specification. See the
+ * PMU_FORMAT_ATTR() declarations in
+ * drivers/hwtracing/coresight/coresight-perf.c for
+ * details.
+ */
+ config = evsel->attr.config;
+ break;
+ }
+ }
+
+ return config;
+}
+
+static size_t
+cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
+ struct perf_evlist *evlist __maybe_unused)
+{
+ int i;
+ int etmv3 = 0, etmv4 = 0;
+ const struct cpu_map *cpus = evlist->cpus;
+
+ /* cpu map is not empty, we have specific CPUs to work with */
+ if (!cpu_map__empty(cpus)) {
+ for (i = 0; i < cpu_map__nr(cpus); i++) {
+ if (cs_etm_is_etmv4(itr, cpus->map[i]))
+ etmv4++;
+ else
+ etmv3++;
+ }
+ } else {
+ /* get configuration for all CPUs in the system */
+ for (i = 0; i < cpu__max_cpu(); i++) {
+ if (cs_etm_is_etmv4(itr, i))
+ etmv4++;
+ else
+ etmv3++;
+ }
+ }
+
+ return (CS_ETM_HEADER_SIZE +
+ (etmv4 * CS_ETMV4_PRIV_SIZE) +
+ (etmv3 * CS_ETMV3_PRIV_SIZE));
+}
+
+static const char *metadata_etmv3_ro[CS_ETM_PRIV_MAX] = {
+ [CS_ETM_ETMCCER] = "mgmt/etmccer",
+ [CS_ETM_ETMIDR] = "mgmt/etmidr",
+};
+
+static const char *metadata_etmv4_ro[CS_ETMV4_PRIV_MAX] = {
+ [CS_ETMV4_TRCIDR0] = "trcidr/trcidr0",
+ [CS_ETMV4_TRCIDR1] = "trcidr/trcidr1",
+ [CS_ETMV4_TRCIDR2] = "trcidr/trcidr2",
+ [CS_ETMV4_TRCIDR8] = "trcidr/trcidr8",
+ [CS_ETMV4_TRCAUTHSTATUS] = "mgmt/trcauthstatus",
+};
+
+static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu)
+{
+ bool ret = false;
+ char path[PATH_MAX];
+ int scan;
+ unsigned int val;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+
+ /* Take any of the RO files for ETMv4 and see if it present */
+ snprintf(path, PATH_MAX, "cpu%d/%s",
+ cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]);
+ scan = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val);
+
+ /* The file was read successfully, we have a winner */
+ if (scan == 1)
+ ret = true;
+
+ return ret;
+}
+
+static int cs_etm_get_ro(struct perf_pmu *pmu, int cpu, const char *path)
+{
+ char pmu_path[PATH_MAX];
+ int scan;
+ unsigned int val = 0;
+
+ /* Get RO metadata from sysfs */
+ snprintf(pmu_path, PATH_MAX, "cpu%d/%s", cpu, path);
+
+ scan = perf_pmu__scan_file(pmu, pmu_path, "%x", &val);
+ if (scan != 1)
+ pr_err("%s: error reading: %s\n", __func__, pmu_path);
+
+ return val;
+}
+
+static void cs_etm_get_metadata(int cpu, u32 *offset,
+ struct auxtrace_record *itr,
+ struct auxtrace_info_event *info)
+{
+ u32 increment;
+ u64 magic;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+
+ /* first see what kind of tracer this cpu is affined to */
+ if (cs_etm_is_etmv4(itr, cpu)) {
+ magic = __perf_cs_etmv4_magic;
+ /* Get trace configuration register */
+ info->priv[*offset + CS_ETMV4_TRCCONFIGR] =
+ cs_etm_get_config(itr);
+ /* Get traceID from the framework */
+ info->priv[*offset + CS_ETMV4_TRCTRACEIDR] =
+ coresight_get_trace_id(cpu);
+ /* Get read-only information from sysFS */
+ info->priv[*offset + CS_ETMV4_TRCIDR0] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro[CS_ETMV4_TRCIDR0]);
+ info->priv[*offset + CS_ETMV4_TRCIDR1] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro[CS_ETMV4_TRCIDR1]);
+ info->priv[*offset + CS_ETMV4_TRCIDR2] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro[CS_ETMV4_TRCIDR2]);
+ info->priv[*offset + CS_ETMV4_TRCIDR8] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro[CS_ETMV4_TRCIDR8]);
+ info->priv[*offset + CS_ETMV4_TRCAUTHSTATUS] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro
+ [CS_ETMV4_TRCAUTHSTATUS]);
+
+ /* How much space was used */
+ increment = CS_ETMV4_PRIV_MAX;
+ } else {
+ magic = __perf_cs_etmv3_magic;
+ /* Get configuration register */
+ info->priv[*offset + CS_ETM_ETMCR] = cs_etm_get_config(itr);
+ /* Get traceID from the framework */
+ info->priv[*offset + CS_ETM_ETMTRACEIDR] =
+ coresight_get_trace_id(cpu);
+ /* Get read-only information from sysFS */
+ info->priv[*offset + CS_ETM_ETMCCER] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv3_ro[CS_ETM_ETMCCER]);
+ info->priv[*offset + CS_ETM_ETMIDR] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv3_ro[CS_ETM_ETMIDR]);
+
+ /* How much space was used */
+ increment = CS_ETM_PRIV_MAX;
+ }
+
+ /* Build generic header portion */
+ info->priv[*offset + CS_ETM_MAGIC] = magic;
+ info->priv[*offset + CS_ETM_CPU] = cpu;
+ /* Where the next CPU entry should start from */
+ *offset += increment;
+}
+
+static int cs_etm_info_fill(struct auxtrace_record *itr,
+ struct perf_session *session,
+ struct auxtrace_info_event *info,
+ size_t priv_size)
+{
+ int i;
+ u32 offset;
+ u64 nr_cpu, type;
+ const struct cpu_map *cpus = session->evlist->cpus;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+
+ if (priv_size != cs_etm_info_priv_size(itr, session->evlist))
+ return -EINVAL;
+
+ if (!session->evlist->nr_mmaps)
+ return -EINVAL;
+
+ /* If the cpu_map is empty all CPUs are involved */
+ nr_cpu = cpu_map__empty(cpus) ? cpu__max_cpu() : cpu_map__nr(cpus);
+ /* Get PMU type as dynamically assigned by the core */
+ type = cs_etm_pmu->type;
+
+ /* First fill out the session header */
+ info->type = PERF_AUXTRACE_CS_ETM;
+ info->priv[CS_HEADER_VERSION_0] = 0;
+ info->priv[CS_PMU_TYPE_CPUS] = type << 32;
+ info->priv[CS_PMU_TYPE_CPUS] |= nr_cpu;
+ info->priv[CS_ETM_SNAPSHOT] = ptr->snapshot_mode;
+
+ offset = CS_ETM_SNAPSHOT + 1;
+
+ /* cpu map is not empty, we have specific CPUs to work with */
+ if (!cpu_map__empty(cpus)) {
+ for (i = 0; i < cpu_map__nr(cpus) && offset < priv_size; i++)
+ cs_etm_get_metadata(cpus->map[i], &offset, itr, info);
+ } else {
+ /* get configuration for all CPUs in the system */
+ for (i = 0; i < cpu__max_cpu(); i++)
+ cs_etm_get_metadata(i, &offset, itr, info);
+ }
+
+ return 0;
+}
+
+static int cs_etm_find_snapshot(struct auxtrace_record *itr __maybe_unused,
+ int idx, struct auxtrace_mmap *mm,
+ unsigned char *data __maybe_unused,
+ u64 *head, u64 *old)
+{
+ pr_debug3("%s: mmap index %d old head %zu new head %zu size %zu\n",
+ __func__, idx, (size_t)*old, (size_t)*head, mm->len);
+
+ *old = *head;
+ *head += mm->len;
+
+ return 0;
+}
+
+static int cs_etm_snapshot_start(struct auxtrace_record *itr)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_evsel *evsel;
+
+ evlist__for_each_entry(ptr->evlist, evsel) {
+ if (evsel->attr.type == ptr->cs_etm_pmu->type)
+ return perf_evsel__disable(evsel);
+ }
+ return -EINVAL;
+}
+
+static int cs_etm_snapshot_finish(struct auxtrace_record *itr)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_evsel *evsel;
+
+ evlist__for_each_entry(ptr->evlist, evsel) {
+ if (evsel->attr.type == ptr->cs_etm_pmu->type)
+ return perf_evsel__enable(evsel);
+ }
+ return -EINVAL;
+}
+
+static u64 cs_etm_reference(struct auxtrace_record *itr __maybe_unused)
+{
+ return (((u64) rand() << 0) & 0x00000000FFFFFFFFull) |
+ (((u64) rand() << 32) & 0xFFFFFFFF00000000ull);
+}
+
+static void cs_etm_recording_free(struct auxtrace_record *itr)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ free(ptr);
+}
+
+static int cs_etm_read_finish(struct auxtrace_record *itr, int idx)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_evsel *evsel;
+
+ evlist__for_each_entry(ptr->evlist, evsel) {
+ if (evsel->attr.type == ptr->cs_etm_pmu->type)
+ return perf_evlist__enable_event_idx(ptr->evlist,
+ evsel, idx);
+ }
+
+ return -EINVAL;
+}
+
+struct auxtrace_record *cs_etm_record_init(int *err)
+{
+ struct perf_pmu *cs_etm_pmu;
+ struct cs_etm_recording *ptr;
+
+ cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME);
+
+ if (!cs_etm_pmu) {
+ *err = -EINVAL;
+ goto out;
+ }
+
+ ptr = zalloc(sizeof(struct cs_etm_recording));
+ if (!ptr) {
+ *err = -ENOMEM;
+ goto out;
+ }
+
+ ptr->cs_etm_pmu = cs_etm_pmu;
+ ptr->itr.parse_snapshot_options = cs_etm_parse_snapshot_options;
+ ptr->itr.recording_options = cs_etm_recording_options;
+ ptr->itr.info_priv_size = cs_etm_info_priv_size;
+ ptr->itr.info_fill = cs_etm_info_fill;
+ ptr->itr.find_snapshot = cs_etm_find_snapshot;
+ ptr->itr.snapshot_start = cs_etm_snapshot_start;
+ ptr->itr.snapshot_finish = cs_etm_snapshot_finish;
+ ptr->itr.reference = cs_etm_reference;
+ ptr->itr.free = cs_etm_recording_free;
+ ptr->itr.read_finish = cs_etm_read_finish;
+
+ *err = 0;
+ return &ptr->itr;
+out:
+ return NULL;
+}
diff --git a/tools/perf/arch/arm/util/cs-etm.h b/tools/perf/arch/arm/util/cs-etm.h
new file mode 100644
index 000000000000..909f486d02d1
--- /dev/null
+++ b/tools/perf/arch/arm/util/cs-etm.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef INCLUDE__PERF_CS_ETM_H__
+#define INCLUDE__PERF_CS_ETM_H__
+
+struct auxtrace_record *cs_etm_record_init(int *err);
+
+#endif
diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build
index 3876dd05bb8b..cef6fb38d17e 100644
--- a/tools/perf/arch/arm64/util/Build
+++ b/tools/perf/arch/arm64/util/Build
@@ -1,4 +1,6 @@
libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
-libperf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o
+libperf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o \
+ ../../arm/util/auxtrace.o \
+ ../../arm/util/cs-etm.o
diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c
index c9169011e55e..c0aba8e839aa 100644
--- a/tools/perf/util/auxtrace.c
+++ b/tools/perf/util/auxtrace.c
@@ -892,6 +892,7 @@ int perf_event__process_auxtrace_info(struct perf_tool *tool __maybe_unused,
return intel_pt_process_auxtrace_info(event, session);
case PERF_AUXTRACE_INTEL_BTS:
return intel_bts_process_auxtrace_info(event, session);
+ case PERF_AUXTRACE_CS_ETM:
case PERF_AUXTRACE_UNKNOWN:
default:
return -EINVAL;
diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h
index ac5f0d7167e6..09286f193532 100644
--- a/tools/perf/util/auxtrace.h
+++ b/tools/perf/util/auxtrace.h
@@ -41,6 +41,7 @@ enum auxtrace_type {
PERF_AUXTRACE_UNKNOWN,
PERF_AUXTRACE_INTEL_PT,
PERF_AUXTRACE_INTEL_BTS,
+ PERF_AUXTRACE_CS_ETM,
};
enum itrace_period_type {
diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h
new file mode 100644
index 000000000000..3cc6bc3263fe
--- /dev/null
+++ b/tools/perf/util/cs-etm.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
+#define INCLUDE__UTIL_PERF_CS_ETM_H__
+
+/* Versionning header in case things need tro change in the future. That way
+ * decoding of old snapshot is still possible.
+ */
+enum {
+ /* Starting with 0x0 */
+ CS_HEADER_VERSION_0,
+ /* PMU->type (32 bit), total # of CPUs (32 bit) */
+ CS_PMU_TYPE_CPUS,
+ CS_ETM_SNAPSHOT,
+ CS_HEADER_VERSION_0_MAX,
+};
+
+/* Beginning of header common to both ETMv3 and V4 */
+enum {
+ CS_ETM_MAGIC,
+ CS_ETM_CPU,
+};
+
+/* ETMv3/PTM metadata */
+enum {
+ /* Dynamic, configurable parameters */
+ CS_ETM_ETMCR = CS_ETM_CPU + 1,
+ CS_ETM_ETMTRACEIDR,
+ /* RO, taken from sysFS */
+ CS_ETM_ETMCCER,
+ CS_ETM_ETMIDR,
+ CS_ETM_PRIV_MAX,
+};
+
+/* ETMv4 metadata */
+enum {
+ /* Dynamic, configurable parameters */
+ CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1,
+ CS_ETMV4_TRCTRACEIDR,
+ /* RO, taken from sysFS */
+ CS_ETMV4_TRCIDR0,
+ CS_ETMV4_TRCIDR1,
+ CS_ETMV4_TRCIDR2,
+ CS_ETMV4_TRCIDR8,
+ CS_ETMV4_TRCAUTHSTATUS,
+ CS_ETMV4_PRIV_MAX,
+};
+
+#define KiB(x) ((x) * 1024)
+#define MiB(x) ((x) * 1024 * 1024)
+
+#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
+
+static const u64 __perf_cs_etmv3_magic = 0x3030303030303030ULL;
+static const u64 __perf_cs_etmv4_magic = 0x4040404040404040ULL;
+#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
+#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
+
+#endif
--
2.7.4
^ permalink raw reply related
* [PATCH 04/15] perf tools: Make coresight PMU listable
From: Arnaldo Carvalho de Melo @ 2016-09-22 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474578779-14095-1-git-send-email-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
Adding the required mechanic allowing 'perf list pmu' to discover
coresight ETM/PTM tracers.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/1474041004-13956-3-git-send-email-mathieu.poirier at linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
MAINTAINERS | 1 +
tools/perf/arch/arm/util/Build | 2 ++
tools/perf/arch/arm/util/pmu.c | 34 ++++++++++++++++++++++++++++++++++
tools/perf/arch/arm64/util/Build | 2 ++
4 files changed, 39 insertions(+)
create mode 100644 tools/perf/arch/arm/util/pmu.c
diff --git a/MAINTAINERS b/MAINTAINERS
index db814a89599c..7407fe779053 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1123,6 +1123,7 @@ F: drivers/hwtracing/coresight/*
F: Documentation/trace/coresight.txt
F: Documentation/devicetree/bindings/arm/coresight.txt
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
+F: tools/perf/arch/arm/util/pmu.c
ARM/CORGI MACHINE SUPPORT
M: Richard Purdie <rpurdie@rpsys.net>
diff --git a/tools/perf/arch/arm/util/Build b/tools/perf/arch/arm/util/Build
index f98da17357c0..4093fd146f46 100644
--- a/tools/perf/arch/arm/util/Build
+++ b/tools/perf/arch/arm/util/Build
@@ -2,3 +2,5 @@ libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
libperf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
+
+libperf-$(CONFIG_AUXTRACE) += pmu.o
diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c
new file mode 100644
index 000000000000..af9fb666b44f
--- /dev/null
+++ b/tools/perf/arch/arm/util/pmu.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+#include <linux/coresight-pmu.h>
+#include <linux/perf_event.h>
+
+#include "../../util/pmu.h"
+
+struct perf_event_attr
+*perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused)
+{
+#ifdef HAVE_AUXTRACE_SUPPORT
+ if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) {
+ /* add ETM default config here */
+ pmu->selectable = true;
+ }
+#endif
+ return NULL;
+}
diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build
index 02f41dba4f4f..3876dd05bb8b 100644
--- a/tools/perf/arch/arm64/util/Build
+++ b/tools/perf/arch/arm64/util/Build
@@ -1,2 +1,4 @@
libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
+
+libperf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o
--
2.7.4
^ permalink raw reply related
* [PATCH 03/15] perf tools: Confine __get_cpuid() to x86 architecture
From: Arnaldo Carvalho de Melo @ 2016-09-22 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474578779-14095-1-git-send-email-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
The __get_cpuid() test is only valid when compiling for x86. When
compiling for other architectures like ARM/ARM64 the test fails event if
the functionality is not required.
This patch isolate the build-in feature check to x86 platform, allowing
the compilation and usage of PMUs that use the AUXTRACE infrastructure
on other architectures (i.e ARM CoreSight).
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/1474041004-13956-2-git-send-email-mathieu.poirier at linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/Makefile.config | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
index 24803c58049a..72edf83d76b7 100644
--- a/tools/perf/Makefile.config
+++ b/tools/perf/Makefile.config
@@ -746,10 +746,13 @@ ifdef LIBBABELTRACE
endif
ifndef NO_AUXTRACE
- ifeq ($(feature-get_cpuid), 0)
- msg := $(warning Your gcc lacks the __get_cpuid() builtin, disables support for auxtrace/Intel PT, please install a newer gcc);
- NO_AUXTRACE := 1
- else
+ ifeq ($(ARCH),x86)
+ ifeq ($(feature-get_cpuid), 0)
+ msg := $(warning Your gcc lacks the __get_cpuid() builtin, disables support for auxtrace/Intel PT, please install a newer gcc);
+ NO_AUXTRACE := 1
+ endif
+ endif
+ ifndef NO_AUXTRACE
$(call detected,CONFIG_AUXTRACE)
CFLAGS += -DHAVE_AUXTRACE_SUPPORT
endif
--
2.7.4
^ permalink raw reply related
* [GIT PULL 00/15] perf/core improvements and fixes
From: Arnaldo Carvalho de Melo @ 2016-09-22 21:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Hi Ingo,
Please consider pulling,
- Arnaldo
The following changes since commit 89f1c2c59c4aef8e26edbc7db5175e6ffb0e9ec7:
Merge tag 'perf-core-for-mingo-20160920' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2016-09-20 23:32:02 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-20160922
for you to fetch changes up to 2d831454140f28fa643b78deede4511b9e2c9e5f:
perf hists: Make hists__fprintf_headers function global (2016-09-22 13:08:59 -0300)
----------------------------------------------------------------
perf/core improvements:
New features:
- Add support for interacting with Coresight PMU ETMs/PTMs, that are IP blocks
to perform hardware assisted tracing on a ARM CPU core (Mathieu Poirier)
Infrastructure:
- Histogram prep work for the upcoming c2c tool (Jiri Olsa)
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
----------------------------------------------------------------
Jiri Olsa (9):
perf evsel: Remove superfluous initialization of weight
perf hists: Use bigger buffer for stdio headers
perf hists: Add __hist_entry__snprintf function
perf tools: Make reset_dimensions global
perf tools: Make output_field_add and sort_dimension__add global
perf tools: Make several sorting functions global
perf tools: Make several display functions global
perf hists: Make __hist_entry__snprintf function global
perf hists: Make hists__fprintf_headers function global
Mathieu Poirier (6):
perf tools: Confine __get_cpuid() to x86 architecture
perf tools: Make coresight PMU listable
perf tools: Add coresight etm PMU record capabilities
perf pmu: Push configuration down to PMU driver
perf tools: Add PMU configuration to tools
perf tools: Add sink configuration for cs_etm PMU
MAINTAINERS | 5 +
tools/perf/Makefile.config | 11 +-
tools/perf/arch/arm/util/Build | 2 +
tools/perf/arch/arm/util/auxtrace.c | 54 ++++
tools/perf/arch/arm/util/cs-etm.c | 617 ++++++++++++++++++++++++++++++++++++
tools/perf/arch/arm/util/cs-etm.h | 26 ++
tools/perf/arch/arm/util/pmu.c | 36 +++
tools/perf/arch/arm64/util/Build | 4 +
tools/perf/builtin-record.c | 10 +
tools/perf/builtin-stat.c | 9 +
tools/perf/builtin-top.c | 13 +
tools/perf/ui/browsers/hists.c | 2 +-
tools/perf/ui/hist.c | 2 +-
tools/perf/ui/stdio/hist.c | 14 +-
tools/perf/util/Build | 1 +
tools/perf/util/auxtrace.c | 1 +
tools/perf/util/auxtrace.h | 1 +
tools/perf/util/cs-etm.h | 74 +++++
tools/perf/util/drv_configs.c | 77 +++++
tools/perf/util/drv_configs.h | 26 ++
tools/perf/util/evsel.c | 2 -
tools/perf/util/hist.h | 5 +
tools/perf/util/pmu.h | 2 +
tools/perf/util/sort.c | 16 +-
tools/perf/util/sort.h | 11 +
25 files changed, 1001 insertions(+), 20 deletions(-)
create mode 100644 tools/perf/arch/arm/util/auxtrace.c
create mode 100644 tools/perf/arch/arm/util/cs-etm.c
create mode 100644 tools/perf/arch/arm/util/cs-etm.h
create mode 100644 tools/perf/arch/arm/util/pmu.c
create mode 100644 tools/perf/util/cs-etm.h
create mode 100644 tools/perf/util/drv_configs.c
create mode 100644 tools/perf/util/drv_configs.h
[root at zoo ~]# time dm
1 73.911 alpine:3.4: Ok
2 26.890 android-ndk:r12b-arm: Ok
3 77.833 archlinux:latest: Ok
4 40.814 centos:5: Ok
5 64.151 centos:6: Ok
6 75.720 centos:7: Ok
7 68.960 debian:7: Ok
8 75.606 debian:8: Ok
9 75.127 fedora:20: Ok
10 80.186 fedora:21: Ok
11 80.157 fedora:22: Ok
12 83.273 fedora:23: Ok
13 91.566 fedora:24: Ok
14 37.720 fedora:24-x-ARC-uClibc: Ok
15 98.492 fedora:rawhide: Ok
16 100.555 mageia:5: Ok
17 94.140 opensuse:13.2: Ok
18 95.476 opensuse:42.1: Ok
19 106.037 opensuse:tumbleweed: Ok
20 75.951 ubuntu:12.04.5: Ok
21 52.138 ubuntu:14.04: Ok
22 94.814 ubuntu:14.04.4: Ok
23 100.525 ubuntu:15.10: Ok
24 93.813 ubuntu:16.04: Ok
25 85.214 ubuntu:16.04-x-arm: Ok
26 83.487 ubuntu:16.04-x-arm64: Ok
27 82.918 ubuntu:16.04-x-powerpc64: Ok
28 84.189 ubuntu:16.04-x-powerpc64el: Ok
29 93.162 ubuntu:16.10: Ok
real 38m13.568s
user 0m2.379s
sys 0m2.402s
[root at zoo ~]#
[root at jouet ~]# perf test
1: vmlinux symtab matches kallsyms : Ok
2: detect openat syscall event : Ok
3: detect openat syscall event on all cpus : Ok
4: read samples using the mmap interface : Ok
5: parse events tests : Ok
6: Validate PERF_RECORD_* events & perf_sample fields : Ok
7: Test perf pmu format parsing : Ok
8: Test dso data read : Ok
9: Test dso data cache : Ok
10: Test dso data reopen : Ok
11: roundtrip evsel->name check : Ok
12: Check parsing of sched tracepoints fields : Ok
13: Generate and check syscalls:sys_enter_openat event fields: Ok
14: struct perf_event_attr setup : Ok
15: Test matching and linking multiple hists : Ok
16: Try 'import perf' in python, checking link problems : Ok
17: Test breakpoint overflow signal handler : Ok
18: Test breakpoint overflow sampling : Ok
19: Test number of exit event of a simple workload : Ok
20: Test software clock events have valid period values : Ok
21: Test object code reading : Ok
22: Test sample parsing : Ok
23: Test using a dummy software event to keep tracking : Ok
24: Test parsing with no sample_id_all bit set : Ok
25: Test filtering hist entries : Ok
26: Test mmap thread lookup : Ok
27: Test thread mg sharing : Ok
28: Test output sorting of hist entries : Ok
29: Test cumulation of child hist entries : Ok
30: Test tracking with sched_switch : Ok
31: Filter fds with revents mask in a fdarray : Ok
32: Add fd to a fdarray, making it autogrow : Ok
33: Test kmod_path__parse function : Ok
34: Test thread map : Ok
35: Test LLVM searching and compiling :
35.1: Basic BPF llvm compiling test : Ok
35.2: Test kbuild searching : Ok
35.3: Compile source for BPF prologue generation test : Ok
35.4: Compile source for BPF relocation test : Ok
36: Test topology in session : Ok
37: Test BPF filter :
37.1: Test basic BPF filtering : Ok
37.2: Test BPF prologue generation : Ok
37.3: Test BPF relocation checker : Ok
38: Test thread map synthesize : Ok
39: Test cpu map synthesize : Ok
40: Test stat config synthesize : Ok
41: Test stat synthesize : Ok
42: Test stat round synthesize : Ok
43: Test attr update synthesize : Ok
44: Test events times : Ok
45: Test backward reading from ring buffer : Ok
46: Test cpu map print : Ok
47: Test SDT event probing : Ok
48: Test is_printable_array function : Ok
49: Test bitmap print : Ok
50: x86 rdpmc test : Ok
51: Test converting perf time to TSC : Ok
52: Test dwarf unwind : Ok
53: Test x86 instruction decoder - new instructions : Ok
54: Test intel cqm nmi context read : Skip
[root at jouet ~]#
^ permalink raw reply
* [PATCH v2] ARM: dts: wheat: add DU support
From: Sergei Shtylyov @ 2016-09-22 21:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <34968644.DhifNderY8@wasted.cogentembedded.com>
Define the Wheat board dependent part of the DU device node.
Add the device nodes for the Analog Devices ADV7513 HDMI transmitters
connected to DU0/1. Add the necessary subnodes to interconnect DU with
HDMI transmitters/connectors.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20160919-v4.8-rc7' of Simon Horman's
'renesas.git' repo...
The patch depends on the 2 DRM patches (already merged by the maintainers) in
order to work correctly.
Changes in version 2:
- refreshed the patch.
arch/arm/boot/dts/r8a7792-wheat.dts | 126 ++++++++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7792-wheat.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792-wheat.dts
+++ renesas/arch/arm/boot/dts/r8a7792-wheat.dts
@@ -86,6 +86,34 @@
gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ hdmi-out0 {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con0: endpoint {
+ remote-endpoint = <&adv7513_0_out>;
+ };
+ };
+ };
+
+ hdmi-out1 {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con1: endpoint {
+ remote-endpoint = <&adv7513_1_out>;
+ };
+ };
+ };
+
+ osc2_clk: osc2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
};
&extal_clk {
@@ -128,6 +156,16 @@
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
+
+ du0_pins: du0 {
+ groups = "du0_rgb888", "du0_sync", "du0_disp";
+ function = "du0";
+ };
+
+ du1_pins: du1 {
+ groups = "du1_rgb666", "du1_sync", "du1_disp";
+ function = "du1";
+ };
};
&scif0 {
@@ -196,4 +234,92 @@
};
};
};
+};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ hdmi at 3d {
+ compatible = "adi,adv7513";
+ reg = <0x3d>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ adv7513_0_in: endpoint {
+ remote-endpoint = <&du_out_rgb0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ adv7513_0_out: endpoint {
+ remote-endpoint = <&hdmi_con0>;
+ };
+ };
+ };
+ };
+
+ hdmi at 39 {
+ compatible = "adi,adv7513";
+ reg = <0x39>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ adv7513_1_in: endpoint {
+ remote-endpoint = <&du_out_rgb1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ adv7513_1_out: endpoint {
+ remote-endpoint = <&hdmi_con1>;
+ };
+ };
+ };
+ };
+};
+
+&du {
+ pinctrl-0 = <&du0_pins &du1_pins>;
+ pinctrl-names = "default";
+
+ clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>,
+ <&osc2_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0";
+ status = "okay";
+
+ ports {
+ port at 0 {
+ endpoint {
+ remote-endpoint = <&adv7513_0_in>;
+ };
+ };
+ port at 1 {
+ endpoint {
+ remote-endpoint = <&adv7513_1_in>;
+ };
+ };
+ };
};
^ permalink raw reply
* Regression in next with "softirq: fix tasklet_kill() and its users"
From: Tony Lindgren @ 2016-09-22 20:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a305129a-e2b4-9ba1-9e94-7998277da035@oracle.com>
* Santosh Shilimkar <santosh.shilimkar@oracle.com> [160922 13:59]:
> On 9/22/2016 1:51 PM, Tony Lindgren wrote:
> > Hi Santosh,
> >
> > Looks like commit 1f5e9c3bc47f ("softirq: fix tasklet_kill() and
> > its users") causes pandaboard es to not get any IP address on the
> > smsc95xx USB Ethernet.
> >
> > Reverting the commits fixes the issue. Any ideas?
> >
> Yep. It was discussed today morning and Stephen was suppose to
> revert that commit from next for now.
>
> The tasklet core fix even though fixes the issue, there are many
> bad users of tasklet which are using tasklet APIs without
> doing any sort of tasklet initialization. So there is more
> work to do before the tasklet core can be fixed.
OK thanks for the info.
Regards,
Tony
^ permalink raw reply
* [PATCH v2] arm: dts: zynq: Add MicroZed board support
From: Sören Brinkmann @ 2016-09-22 20:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474550489-7005-1-git-send-email-jagan@amarulasolutions.com>
On Thu, 2016-09-22 at 18:51:29 +0530, Jagan Teki wrote:
> From: Jagan Teki <jteki@openedev.com>
>
> Added basic dts support for MicroZed board.
>
> - UART
> - SDHCI
> - Ethernet
>
> Cc: Soren Brinkmann <soren.brinkmann@xilinx.com>
> Cc: Michal Simek <michal.simek@xilinx.com>
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> ---
> Changes for v2:
> - Add SDHCI
> - Add Ethernet
>
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/zynq-microzed.dts | 95 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 96 insertions(+)
> create mode 100644 arch/arm/boot/dts/zynq-microzed.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index faacd52..4d7b858 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -862,6 +862,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \
> wm8750-apc8750.dtb \
> wm8850-w70v2.dtb
> dtb-$(CONFIG_ARCH_ZYNQ) += \
> + zynq-microzed.dtb \
> zynq-parallella.dtb \
> zynq-zc702.dtb \
> zynq-zc706.dtb \
> diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts
> new file mode 100644
> index 0000000..9e64496
> --- /dev/null
> +++ b/arch/arm/boot/dts/zynq-microzed.dts
> @@ -0,0 +1,95 @@
> +/*
> + * Copyright (C) 2015 Jagan Teki <jteki@openedev.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +/dts-v1/;
> +/include/ "zynq-7000.dtsi"
> +
> +/ {
> + model = "Zynq MicroZED Development Board";
> + compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
> +
> + aliases {
> + ethernet0 = &gem0;
> + serial0 = &uart1;
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x0 0x40000000>;
> + };
> +
> + chosen {
> + bootargs = "earlycon";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + usb_phy0: phy0 {
> + compatible = "usb-nop-xceiv";
> + #phy-cells = <0>;
> + };
> +};
> +
> +&clkc {
> + ps-clk-frequency = <33333333>;
> +};
> +
> +&gem0 {
> + status = "okay";
> + phy-mode = "rgmii-id";
> + phy-handle = <ðernet_phy>;
> +
> + ethernet_phy: ethernet-phy at 0 {
> + reg = <0>;
> + };
> +};
> +
> +&sdhci0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&usb0 {
> + status = "okay";
> + dr_mode = "host";
> + usb-phy = <&usb_phy0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb0_default>;
> +};
> +
> +&pinctrl0 {
> + pinctrl_usb0_default: usb0-default {
> + mux {
> + groups = "usb0_0_grp";
> + function = "usb0";
> + };
> +
> + conf {
> + groups = "usb0_0_grp";
> + slew-rate = <0>;
> + io-standard = <1>;
> + };
> +
> + conf-rx {
> + pins = "MIO29", "MIO31", "MIO36";
> + bias-high-impedance;
> + };
> +
> + conf-tx {
> + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
> + "MIO35", "MIO37", "MIO38", "MIO39";
> + bias-disable;
> + };
> + };
> +};
I guess it's not strictly required, but shouldn't there be pinctrl
descriptions for all devices?
S?ren
^ permalink raw reply
* Regression in next with "softirq: fix tasklet_kill() and its users"
From: Santosh Shilimkar @ 2016-09-22 20:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922205122.ezsxjint2l6lytyi@atomide.com>
On 9/22/2016 1:51 PM, Tony Lindgren wrote:
> Hi Santosh,
>
> Looks like commit 1f5e9c3bc47f ("softirq: fix tasklet_kill() and
> its users") causes pandaboard es to not get any IP address on the
> smsc95xx USB Ethernet.
>
> Reverting the commits fixes the issue. Any ideas?
>
Yep. It was discussed today morning and Stephen was suppose to
revert that commit from next for now.
The tasklet core fix even though fixes the issue, there are many
bad users of tasklet which are using tasklet APIs without
doing any sort of tasklet initialization. So there is more
work to do before the tasklet core can be fixed.
Regards,
Santosh
^ permalink raw reply
* [PATCH] ARM: dts: exynos: Add reboot reason support for Trats2
From: Krzysztof Kozlowski @ 2016-09-22 20:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87shsrlq1f.fsf@monsta.com>
On Thu, Sep 22, 2016 at 08:59:03PM +0200, Wolfgang Wiedmeyer wrote:
>
> Krzysztof Kozlowski writes:
>
> > On Thu, Sep 22, 2016 at 06:48:35PM +0200, Wolfgang Wiedmeyer wrote:
> >> This allows to reboot the device into recovery mode and into the download
> >> mode of the bootloader.
> >
> > Which bootloader? Probably UBoot... or Samsung stock one? Could you put
> > that information here?
>
> I'm only working with the stock one. I was under the impression that the
> stock bootloader cannot be replaced on a i9300 because there's a
> signature check. Is UBoot loaded after the stock one on Trats2 or how
> does this work? I didn't find information on that.
+CC Marek,
Trats2 is working with U-Boot. Just U-Boot. However I never converted S3
into Trats2 on my own. I always used targets prepared to be "Trats2"
type.
Of course kernel is independent to bootloader but in that case you want
to use a specific interface between kernel and specific bootloader
type/version. In that case - this should be U-Boot, I think.
>
> >>
> >> Signed-off-by: Wolfgang Wiedmeyer <wolfgit@wiedmeyer.de>
> >> ---
> >> arch/arm/boot/dts/exynos4412-trats2.dts | 14 ++++++++++++++
> >> arch/arm/boot/dts/exynos4x12.dtsi | 2 +-
> >> 2 files changed, 15 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
> >> index 129e973..a38d1e3 100644
> >> --- a/arch/arm/boot/dts/exynos4412-trats2.dts
> >> +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
> >> @@ -1294,3 +1294,17 @@
> >> vtmu-supply = <&ldo10_reg>;
> >> status = "okay";
> >> };
> >> +
> >> +&pmu {
> >> + compatible = "syscon", "simple-mfd";
> >> +
> >> + reboot-mode {
> >> + compatible = "syscon-reboot-mode";
> >> + offset = <0x80c>;
> >> +
> >> + mode-normal = <0x12345670>;
> >> + mode-bootloader = <0x12345671>;
> >> + mode-download = <0x12345671>;
> >> + mode-recovery = <0x12345674>;
> >
> > Hmmm, how did you get these values? Are they already supported?
>
> I only have the vendor source drop as documentation. The magic mode
> values [1] and the offset [2] can be found there.
It would be useful to mention that in commit msg (just the source)...
however as I wrote above, these values should be for U-Boot, not the
stock one.
Best regards,
Krzysztof
>
> > It would be nice to document them:
> > 1. In Documentation/arm/Samsung/Bootloader-interface.txt
> > 2. In header. I hate such magic numbers... you could add new header next
> > to existing rockchip one:
> > include/dt-bindings/soc/samsung,boot-mode.h
> > (and update maintainers entry :) )
>
> Thanks for the review! I will do the documentation and update the commit
> message.
>
> Best regards,
> Wolfgang
>
> [1] https://code.fossencdi.org/kernel_samsung_smdk4412.git/tree/arch/arm/mach-exynos/sec-reboot.c#n65
>
> [2] https://code.fossencdi.org/kernel_samsung_smdk4412.git/tree/arch/arm/mach-exynos/include/mach/regs-pmu.h#n79
>
>
> --
> Website: https://fossencdi.org
> Jabber: wolfgang at wiedmeyer.de
> OpenPGP: 0F30 D1A0 2F73 F70A 6FEE 048E 5816 A24C 1075 7FC4
> Key download: https://wiedmeyer.de/keys/ww.asc
^ permalink raw reply
* Regression in next with "softirq: fix tasklet_kill() and its users"
From: Tony Lindgren @ 2016-09-22 20:51 UTC (permalink / raw)
To: linux-arm-kernel
Hi Santosh,
Looks like commit 1f5e9c3bc47f ("softirq: fix tasklet_kill() and
its users") causes pandaboard es to not get any IP address on the
smsc95xx USB Ethernet.
Reverting the commits fixes the issue. Any ideas?
Regards,
Tony
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* [PATCH 3/3] arm64: Add the Raspberry Pi firmware's interface to the FXL6408.
From: Gerd Hoffmann @ 2016-09-22 20:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160919161314.25858-3-eric@anholt.net>
On Mo, 2016-09-19 at 17:13 +0100, Eric Anholt wrote:
> This gets us hotplug detection of HDMI, so that graphics now works at
> boot. Tested with watching the output of xrandr while plugging and
> unplugging the HDMI cable.
Very nice. Whole patch series:
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
/me hopes this lands in the 4.9 merge window.
cheers,
Gerd
^ permalink raw reply
* [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support
From: atull @ 2016-09-22 19:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160809160039.GX29630@windriver.com>
On Tue, 9 Aug 2016, Paul Gortmaker wrote:
> [Re: [PATCH v18 6/6] ARM: socfpga: fpga bridge driver support] On 08/08/2016 (Mon 13:44) Moritz Fischer wrote:
>
> > Hi Alan,
> >
> > On Mon, Aug 8, 2016 at 12:18 PM, atull <atull@opensource.altera.com> wrote:
> >
> > >> Please don't use module.h in drivers controlled by a bool
> > >> Kconfig setting.
> > >>
> > >> THanks,
> > >> Paul.
> > >>
> > >
> > > Thanks for the feedback. Can you provide an example of what you
> > > would consider to be proper usage in the kernel?
> >
> >
> > I think Paul is suggesting to use
> >
> > static int __init alt_fpga_bridge_init(void)
> > {
> > platform_driver_register(&alt_fpga_bridge_driver);
> > }
> >
> > device_initcall(alt_fpga_bridge_init);
> >
> > or better:
> >
> > builtin_platform_driver(&alt_fpga_bridge_driver);
> >
> > Like for example in: drivers/cpuidle/cpuidle-mvebu-v7.c
>
> Yes, pretty much that -- if you have a bool Kconfig, you should be using
> builtin registration functions, and have no need for module.h or
> anything MODULE_<xyz> or any module_init/module_exit calls.
>
> An empty file containing nothing but #include <linux/module.h> will
> cause cpp to emit about 750k of goop, so we really should only be using
> it for drivers that are genuinely modular; i.e. tristate Kconfig.
>
> Thanks,
> Paul.
> --
>
> >
> > Cheers,
> >
> > Moritz
>
Thanks for the feedback and explanations!
I've retested my stuff with it all built as modules (mgr, bridged,
and fpga-region) and it all works that way as well as built in.
So I'll fix up the Kconfig as tristates for everybody. Also
I'll add some dependencies as FPGA_REGION should be dependent
on FPGA_BRIDGE.
Alan
^ permalink raw reply
* [PATCH] arm: dts: fix rk3066a based boards vdd_log voltage initialization
From: Mark Brown @ 2016-09-22 19:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922201301.0157a292@bbrezillon>
On Thu, Sep 22, 2016 at 08:13:01PM +0200, Boris Brezillon wrote:
> So, there are 2 different problems here:
> 1/ the board no longer boots because of commit 87248991a1de and a
> missing entry in the voltage table
> 2/ claiming the PWM pins at probe time can cause glitches
> I'm currently trying to solve #1, but most of the discussion in this
> thread was about addressing #2.
Well, if you actually want the entry in the voltage table then adding it
does seem the most sensible fix.
> > That was a very
> > long e-mail so I might be missing something but the obvious thing seems
> > to be to force a state since we'll be doing that when we enable anyway.
> Hm, okay, but which state should we choose? The first entry in the
> voltage-table?
That's why we don't do this currently. Probably the closest one if we
can work out what it was trying to achieve.
> > Or just not have the voltage table and use it as a continuous regulator.
> Yes, but that means patching the DT, which means breaking the DT compat.
It sounds like you want to fix the DT anyway though?
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* [PATCH] ARM: dts: exynos: Add reboot reason support for Trats2
From: Wolfgang Wiedmeyer @ 2016-09-22 18:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922174606.GA4988@kozik-lap>
Krzysztof Kozlowski writes:
> On Thu, Sep 22, 2016 at 06:48:35PM +0200, Wolfgang Wiedmeyer wrote:
>> This allows to reboot the device into recovery mode and into the download
>> mode of the bootloader.
>
> Which bootloader? Probably UBoot... or Samsung stock one? Could you put
> that information here?
I'm only working with the stock one. I was under the impression that the
stock bootloader cannot be replaced on a i9300 because there's a
signature check. Is UBoot loaded after the stock one on Trats2 or how
does this work? I didn't find information on that.
>>
>> Signed-off-by: Wolfgang Wiedmeyer <wolfgit@wiedmeyer.de>
>> ---
>> arch/arm/boot/dts/exynos4412-trats2.dts | 14 ++++++++++++++
>> arch/arm/boot/dts/exynos4x12.dtsi | 2 +-
>> 2 files changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
>> index 129e973..a38d1e3 100644
>> --- a/arch/arm/boot/dts/exynos4412-trats2.dts
>> +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
>> @@ -1294,3 +1294,17 @@
>> vtmu-supply = <&ldo10_reg>;
>> status = "okay";
>> };
>> +
>> +&pmu {
>> + compatible = "syscon", "simple-mfd";
>> +
>> + reboot-mode {
>> + compatible = "syscon-reboot-mode";
>> + offset = <0x80c>;
>> +
>> + mode-normal = <0x12345670>;
>> + mode-bootloader = <0x12345671>;
>> + mode-download = <0x12345671>;
>> + mode-recovery = <0x12345674>;
>
> Hmmm, how did you get these values? Are they already supported?
I only have the vendor source drop as documentation. The magic mode
values [1] and the offset [2] can be found there.
> It would be nice to document them:
> 1. In Documentation/arm/Samsung/Bootloader-interface.txt
> 2. In header. I hate such magic numbers... you could add new header next
> to existing rockchip one:
> include/dt-bindings/soc/samsung,boot-mode.h
> (and update maintainers entry :) )
Thanks for the review! I will do the documentation and update the commit
message.
Best regards,
Wolfgang
[1] https://code.fossencdi.org/kernel_samsung_smdk4412.git/tree/arch/arm/mach-exynos/sec-reboot.c#n65
[2] https://code.fossencdi.org/kernel_samsung_smdk4412.git/tree/arch/arm/mach-exynos/include/mach/regs-pmu.h#n79
--
Website: https://fossencdi.org
Jabber: wolfgang at wiedmeyer.de
OpenPGP: 0F30 D1A0 2F73 F70A 6FEE 048E 5816 A24C 1075 7FC4
Key download: https://wiedmeyer.de/keys/ww.asc
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