* [PATCH] clk: uniphier: add system clock support for sLD3 SoC
From: Masahiro Yamada @ 2016-10-16 15:11 UTC (permalink / raw)
To: linux-arm-kernel
I do not know why, but I missed to add this compatible string in
the initial commit of this driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/clk/uniphier/clk-uniphier-core.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 5ffb898..f4e0f6b 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -111,6 +111,10 @@ static int uniphier_clk_remove(struct platform_device *pdev)
static const struct of_device_id uniphier_clk_match[] = {
/* System clock */
{
+ .compatible = "socionext,uniphier-sld3-clock",
+ .data = uniphier_sld3_sys_clk_data,
+ },
+ {
.compatible = "socionext,uniphier-ld4-clock",
.data = uniphier_ld4_sys_clk_data,
},
--
1.9.1
^ permalink raw reply related
* [PATCH] clk: uniphier: fix type of variable passed to regmap_read()
From: Masahiro Yamada @ 2016-10-16 15:25 UTC (permalink / raw)
To: linux-arm-kernel
The 3rd argument of regmap_read() takes a pointer to unsigned int.
This driver is saved just because u32 happens to be typedef'ed as
unsigned int, but we should not rely on that fact. Change the
variable type just in case.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/clk/uniphier/clk-uniphier-mux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/uniphier/clk-uniphier-mux.c b/drivers/clk/uniphier/clk-uniphier-mux.c
index 15a2f2c..2c243a8 100644
--- a/drivers/clk/uniphier/clk-uniphier-mux.c
+++ b/drivers/clk/uniphier/clk-uniphier-mux.c
@@ -42,7 +42,7 @@ static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
int num_parents = clk_hw_get_num_parents(hw);
int ret;
- u32 val;
+ unsigned int val;
u8 i;
ret = regmap_read(mux->regmap, mux->reg, &val);
--
1.9.1
^ permalink raw reply related
* [PATCH] ARM/orion/gpio: Replace three seq_printf() calls by seq_puts() in orion_gpio_dbg_show()
From: Andrew Lunn @ 2016-10-16 15:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <92ba3c30-386a-bb86-623d-0917cd9e61a2@users.sourceforge.net>
On Sun, Oct 16, 2016 at 12:38:26PM +0200, SF Markus Elfring wrote:
> From: Markus Elfring <elfring@users.sourceforge.net>
> Date: Sun, 16 Oct 2016 12:30:48 +0200
>
> Strings which did not contain data format specifications should be put
> into a sequence. Thus use the corresponding function "seq_puts".
>
> This issue was detected by using the Coccinelle software.
>
> Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH] watchdog: at91sam9: keep watchdog running in idle mode
From: Sylvain Rochet @ 2016-10-16 15:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20151007110112.GD3485@piout.net>
Hi,
On Wed, Oct 07, 2015 at 01:01:12PM +0200, Alexandre Belloni wrote:
> On 06/10/2015 at 22:28:45 +0200, Sylvain Rochet wrote :
> > Since turning on idle-halt in commit 5161b31dc39a (watchdog:
> > at91sam9_wdt: better watchdog support"), SoCs compatible with
> > at91sam9260-wdt not using a device tree no longer reboot if the watchdog
> > times out while the CPU is in idle state. Removing the
> > AT91_WDT_WDIDLEHLT flag that was set by default fixes this.
> >
> > Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
> > Fixes: 5161b31dc39a ("watchdog: at91sam9_wdt: better watchdog support")
> > Cc: <stable@vger.kernel.org> # 3.14+
>
> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
>
> However, we don't really care about that for kernels after 3.18 as no
> users are using pdata anymore.
> I think you could send a follow-up patch removing pdata support
> completely.
Looks like this one falls through the cracks, it didn't reach mainline
and therefore wasn't applied to stable branches.
I just checked, it still apply properly on today's linux-next branch.
Cheers,
Sylvain
^ permalink raw reply
* [PATCH 1/2] arm64: dts: uniphier: increase register region size of sysctrl node
From: Masahiro Yamada @ 2016-10-16 15:42 UTC (permalink / raw)
To: linux-arm-kernel
The System Control node has 0x10000 byte of registers. The current
reg size must be expanded to use the cpufreq driver because the
registers controlling CPU frequency are located at offset 0x8000.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 3eb4c42..da3cdd8 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -320,7 +320,7 @@
sysctrl at 61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
+ reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-ld11-clock";
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 08fd7cf..efb47ea 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -311,7 +311,7 @@
sysctrl at 61840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
+ reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-ld20-clock";
--
1.9.1
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: uniphier: increase register region size of sysctrl node
From: Masahiro Yamada @ 2016-10-16 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476632563-7446-1-git-send-email-yamada.masahiro@socionext.com>
The System Control node has 0x10000 byte of registers. The current
reg size must be expanded to use the cpufreq driver because the
registers controlling CPU frequency are located at offset 0x8000.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-common32.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi
index 8c8a851..d067f38 100644
--- a/arch/arm/boot/dts/uniphier-common32.dtsi
+++ b/arch/arm/boot/dts/uniphier-common32.dtsi
@@ -183,7 +183,7 @@
sysctrl at 61840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
+ reg = <0x61840000 0x10000>;
sys_clk: clock {
#clock-cells = <1>;
--
1.9.1
^ permalink raw reply related
* [PATCH] watchdog: at91sam9: keep watchdog running in idle mode
From: Guenter Roeck @ 2016-10-16 15:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161016153316.rsrcgnki6kn7gola@finsecur.com>
On 10/16/2016 08:33 AM, Sylvain Rochet wrote:
> Hi,
>
> On Wed, Oct 07, 2015 at 01:01:12PM +0200, Alexandre Belloni wrote:
>> On 06/10/2015 at 22:28:45 +0200, Sylvain Rochet wrote :
>>> Since turning on idle-halt in commit 5161b31dc39a (watchdog:
>>> at91sam9_wdt: better watchdog support"), SoCs compatible with
>>> at91sam9260-wdt not using a device tree no longer reboot if the watchdog
>>> times out while the CPU is in idle state. Removing the
>>> AT91_WDT_WDIDLEHLT flag that was set by default fixes this.
>>>
>>> Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
>>> Fixes: 5161b31dc39a ("watchdog: at91sam9_wdt: better watchdog support")
>>> Cc: <stable@vger.kernel.org> # 3.14+
>>
>> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
>>
>> However, we don't really care about that for kernels after 3.18 as no
>> users are using pdata anymore.
>> I think you could send a follow-up patch removing pdata support
>> completely.
>
> Looks like this one falls through the cracks, it didn't reach mainline
> and therefore wasn't applied to stable branches.
>
Possibly that happened because you did not copy the watchdog mailing list.
Guenter
> I just checked, it still apply properly on today's linux-next branch.
>
> Cheers,
> Sylvain
>
^ permalink raw reply
* [PATCH] watchdog: at91sam9: keep watchdog running in idle mode
From: Guenter Roeck @ 2016-10-16 15:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <67fe262e-31e4-b9dc-da71-af601079bfec@roeck-us.net>
On 10/16/2016 08:50 AM, Guenter Roeck wrote:
> On 10/16/2016 08:33 AM, Sylvain Rochet wrote:
>> Hi,
>>
>> On Wed, Oct 07, 2015 at 01:01:12PM +0200, Alexandre Belloni wrote:
>>> On 06/10/2015 at 22:28:45 +0200, Sylvain Rochet wrote :
>>>> Since turning on idle-halt in commit 5161b31dc39a (watchdog:
>>>> at91sam9_wdt: better watchdog support"), SoCs compatible with
>>>> at91sam9260-wdt not using a device tree no longer reboot if the watchdog
>>>> times out while the CPU is in idle state. Removing the
>>>> AT91_WDT_WDIDLEHLT flag that was set by default fixes this.
>>>>
>>>> Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
>>>> Fixes: 5161b31dc39a ("watchdog: at91sam9_wdt: better watchdog support")
>>>> Cc: <stable@vger.kernel.org> # 3.14+
>>>
>>> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
>>>
>>> However, we don't really care about that for kernels after 3.18 as no
>>> users are using pdata anymore.
>>> I think you could send a follow-up patch removing pdata support
>>> completely.
>>
>> Looks like this one falls through the cracks, it didn't reach mainline
>> and therefore wasn't applied to stable branches.
>>
> Possibly that happened because you did not copy the watchdog mailing list.
>
... and your other patches were not sent to the watchdog mailing list either,
so you should not expect them to be picked up either.
Seriously, how do you expect _any_ patch to be picked up if you neither copy
the subsystem mailing list nor the subsystem maintainer ?
Guenter
^ permalink raw reply
* [PATCH v2] ARM: at91/dt: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx
From: Sylvain Rochet @ 2016-10-16 16:21 UTC (permalink / raw)
To: linux-arm-kernel
Changes since v1:
* While we are at it, remove useless pinctrl comments, as suggested
by Alexandre.
* Remove consumption story about the pull-up on a push-pull output
in the commit message, it does not seem to be the case, or rather
the contrary, as per
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-September/368643.html
results, the dt must be logical anyway.
Sylvain Rochet (1):
ARM: at91/dt: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx
arch/arm/boot/dts/at91rm9200.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9260.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9261.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9263.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9g45.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9n12.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9rl.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++--
arch/arm/boot/dts/sama5d3.dtsi | 4 ++--
arch/arm/boot/dts/sama5d4.dtsi | 4 ++--
10 files changed, 20 insertions(+), 20 deletions(-)
--
2.9.3
^ permalink raw reply
* [PATCH v2] ARM: at91/dt: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx
From: Sylvain Rochet @ 2016-10-16 16:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161016162145.26193-1-sylvain.rochet@finsecur.com>
Remove pullup on dbgu DTXD signal, it is a push-pull output thus the
pullup is pointless.
Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left
floating and so consuming a useless extra amount of power in crowbarred
state if nothing is externally connected to dbgu.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
---
arch/arm/boot/dts/at91rm9200.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9260.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9261.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9263.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9g45.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9n12.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9rl.dtsi | 4 ++--
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++--
arch/arm/boot/dts/sama5d3.dtsi | 4 ++--
arch/arm/boot/dts/sama5d4.dtsi | 4 ++--
10 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 4e913c2..f057e0b 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -481,8 +481,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
- AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
+ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index a3e363d..9e035b2 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -412,8 +412,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
- AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */
+ <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 32752d7..3fe77c3 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -302,8 +302,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
- <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index aeb1a36..a1888f6 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -412,8 +412,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
- AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
+ <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index b3501ae..e567d5f 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -478,8 +478,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 3b3eb3e..f43d769 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -500,8 +500,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 70adf94..f4c129a 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -438,8 +438,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
- <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index ed4e4bd..f66bae9 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -460,8 +460,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 4c84d33..b06448b 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -549,8 +549,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
- AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
+ <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 65e725f..d136ebd 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1461,8 +1461,8 @@
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
- <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
- <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
+ <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
--
2.9.3
^ permalink raw reply related
* [PATCH] ARM: at91/dt: pullup dbgu rx instead of tx
From: Sylvain Rochet @ 2016-10-16 16:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6d2d5aba-cca3-93c6-0c59-3acbbd7b6169@lysator.liu.se>
Hi Peter,
On Sun, Oct 16, 2016 at 12:57:09PM +0200, Peter Rosin wrote:
> Hi again,
>
> I forgot about this, and it's been a year. But isn't it time to
> upstream those pull-up fixes that Sylvain provided?
Thank you for your reminder, actually I waited an answer on this nice
subject: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-September/368643.html
But this is not relevant for this change anyway, if we should set a
pull-(up|down) on all push-pull pads to reduce power consumption it
should be enforced in the pinctrl driver, the dt must stay logical.
I just sent a v2 with all useless comments removed as suggested by
Alexandre and without the explanation about the removed extra power
consumption when removing a pull-(up|down) on a push-pull output because
it does even seem to be the contrary on Atmel SoCs.
Sylvain
^ permalink raw reply
* [PATCH] ARM64-cpuinfo: Combine six calls for sequence output into one seq_printf() call in c_show()
From: SF Markus Elfring @ 2016-10-16 19:03 UTC (permalink / raw)
To: linux-arm-kernel
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Sun, 16 Oct 2016 20:48:28 +0200
Some data were printed into a sequence by six separate function calls.
Print the same data by a single function call instead.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
arch/arm64/kernel/cpuinfo.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index b3d5b3e..f22687d 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -148,14 +148,17 @@ static int c_show(struct seq_file *m, void *v)
if (elf_hwcap & (1 << j))
seq_printf(m, " %s", hwcap_str[j]);
}
- seq_puts(m, "\n");
-
- seq_printf(m, "CPU implementer\t: 0x%02x\n",
- MIDR_IMPLEMENTOR(midr));
- seq_printf(m, "CPU architecture: 8\n");
- seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
- seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
- seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
+ seq_printf(m,
+ "\n"
+ "CPU implementer\t: 0x%02x\n"
+ "CPU architecture: 8\n"
+ "CPU variant\t: 0x%x\n"
+ "CPU part\t: 0x%03x\n"
+ "CPU revision\t: %d\n\n",
+ MIDR_IMPLEMENTOR(midr),
+ MIDR_VARIANT(midr),
+ MIDR_PARTNUM(midr),
+ MIDR_REVISION(midr));
}
return 0;
--
2.10.1
^ permalink raw reply related
* [PATCH v2] ARM: dts: rockchip: temporarily remove emmc hs200 speed from rk3288-veyron-speedy.
From: Paul Kocialkowski @ 2016-10-16 19:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87twd1vzc5.fsf@aikidev.net>
Hi,
Le mardi 27 septembre 2016 ? 13:53 -0700, Vagrant Cascadian a ?crit?:
> This essentially mimics what was done with rk3288-veyron-minnie in
> commit 984926781122f034d5bc9962815d135b6c4a8e1d.
>
> The eMMC of the speedy Chromebook also appears to need the same tuning
> workaround, as it frequently fails to recognize the eMMC without it.
I have a device where (without this patch) eMMC sometimes fails, with:
[????3.561010] dwmmc_rockchip ff0f0000.dwmmc: Successfully tuned phase to 175
[????3.571742] mmc2: new HS200 MMC card at address 0001
[????3.571943] mmcblk2: mmc2:0001 HAG2e 14.7 GiB?
[????3.572026] mmcblk2boot0: mmc2:0001 HAG2e partition 1 4.00 MiB
[????3.572107] mmcblk2boot1: mmc2:0001 HAG2e partition 2 4.00 MiB
[????3.572181] mmcblk2rpmb: mmc2:0001 HAG2e partition 3 4.00 MiB
[????3.685647] mmcblk2: error -110 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
And sometimes works, with:
[????3.451058] dwmmc_rockchip ff0f0000.dwmmc: Successfully tuned phase to 176
[????3.491093] mmc2: new HS200 MMC card at address 0001
[????3.491277] mmcblk2: mmc2:0001 HAG2e 14.7 GiB?
[????3.491345] mmcblk2boot0: mmc2:0001 HAG2e partition 1 4.00 MiB
[????3.491409] mmcblk2boot1: mmc2:0001 HAG2e partition 2 4.00 MiB
[????3.491474] mmcblk2rpmb: mmc2:0001 HAG2e partition 3 4.00 MiB
[????3.493548]??mmcblk2: p1 p2
However, with this change, it always fails, with:
[????3.322129] mmc_host mmc2: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)
[????3.333174] mmc2: error -110 whilst initialising MMC card
I don't have so much time to investigate this issue, but it's clear that this
patch doesn't fix the issue (and actually worsens it) for my device.
Cheers!
> Signed-off-by: Vagrant Cascadian <vagrantc@aikidev.net>
> ---
> Changes in v2:
> ?- Added Signed-off-by.
>
> ?arch/arm/boot/dts/rk3288-veyron-speedy.dts | 5 +++++
> ?1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
> b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
> index a0d033f..500fd18 100644
> --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
> +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
> @@ -124,6 +124,11 @@
> ????????????&sdmmc_bus4>;
> ?};
>
> +
> +&emmc {
> +???????/delete-property/mmc-hs200-1_8v;
> +};
> +
> ?&vcc_5v {
> ????enable-active-high;
> ????gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
--
Paul Kocialkowski, developer of free digital technology at the lower levels
Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/
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* RK3288 USB issues with ath9k_htc Wi-Fi dongles on veyron devices
From: Paul Kocialkowski @ 2016-10-16 20:01 UTC (permalink / raw)
To: linux-arm-kernel
I'm trying to use ath9k_htc Wi-Fi dongles with various rk3288 veyron devices,
which currently do not work.
I have a bunch of different dongles, that all work nicely with other devices.
The kernel I'm running is 4.9-rc1 and the USB connectors I'm using are linked to
OTG and HOST1 (both DWC2 controllers).
I have applied the latest version of Randy Li's patches, that fix an USB error
with these controllers. They do not fix my issue, or otherwise change the
behavior I'm seeing. The very same device running with the chromeos-3.14 kernel
works nicely and doesn't have this issue.
There are two different cases, that happen interchangeably and randomly:
1. The dongle is detected and the driver is probed but the first register reads
fail:
[??322.841142] usb 2-1: new high-speed USB device number 3 using dwc2
[??323.104591] usb 2-1: ath9k_htc: Firmware ath9k_htc/htc_9271-1.4.0.fw requested
[??323.113489] usb 2-1: Direct firmware load for ath9k_htc/htc_9271-1.4.0.fw failed with error -2
[??323.122204] usb 2-1: ath9k_htc: Firmware htc_9271.fw requested
[??323.414012] usb 2-1: ath9k_htc: Transferred FW: htc_9271.fw, size: 51008
[??323.665556] ath9k_htc 2-1:1.0: ath9k_htc: HTC initialized with 33 credits
[??324.710992] ath: phy1: Timeout waiting for WMI command: WMI_REG_READ_CMDID
[??324.717899] ath: phy1: REGISTER READ FAILED: (0x4020, -110)
[??324.723525] ath: phy1: Mac Chip Rev 0x0f.3 is not supported by this driver
[??324.730416] ath: phy1: Unable to initialize hardware; initialization status: -95
[??324.737853] ath: phy1: Unable to initialize hardware; initialization status: -95
[??324.745296] ath9k_htc: Failed to initialize the device
[??324.755440] usb 2-1: ath9k_htc: USB layer deinitialized
2. The dongle is detected, the first few register reads succeed but register
reads fail as soon as the dongle enters power-saving mode:
[???68.070377] ath: phy0: Removed a station entry for VIF 0 (idx: 0)
[???68.078752] ath: phy0: Detach Interface at idx: 0
[???68.085260] ath: phy0: AWAKE -> FULL-SLEEP
[???68.090766] ath: phy0: FULL-SLEEP -> AWAKE
[???68.107512] ath: phy0: AWAKE -> FULL-SLEEP
[???68.112756] ath: phy0: Driver halt
[???68.117108] ath: phy0: Starting driver with initial channel: 2412 MHz
[???68.123577] ath: phy0: FULL-SLEEP -> AWAKE
[???69.191104] ath: phy0: Timeout waiting for WMI command: WMI_REG_READ_CMDID
[???69.197987] ath: phy0: REGISTER READ FAILED: (0x7044, -110)
[???70.231015] ath: phy0: Timeout waiting for WMI command: WMI_REG_RMW_CMDID
What could be causing these issues?
Cheers!
--
Paul Kocialkowski, developer of free digital technology at the lower levels
Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/
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^ permalink raw reply
* [PATCH] watchdog: at91sam9: keep watchdog running in idle mode
From: Sylvain Rochet @ 2016-10-16 20:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <59c665f8-de09-c11c-f62a-5064016cd8fd@roeck-us.net>
Hi Guenter,
On Sun, Oct 16, 2016 at 08:55:41AM -0700, Guenter Roeck wrote:
> On 10/16/2016 08:50 AM, Guenter Roeck wrote:
> > On 10/16/2016 08:33 AM, Sylvain Rochet wrote:
> > >
> > > Looks like this one falls through the cracks, it didn't reach mainline
> > > and therefore wasn't applied to stable branches.
> >
> > Possibly that happened because you did not copy the watchdog mailing list.
>
> ... and your other patches were not sent to the watchdog mailing list either,
> so you should not expect them to be picked up either.
>
> Seriously, how do you expect _any_ patch to be picked up if you neither copy
> the subsystem mailing list nor the subsystem maintainer ?
Whoops, thanks for the heads up, I wonder how I managed to mess up that
at that time, I usually take care of that. The other series need
respinning anyway so I can fix it for v2 (if any).
Cheers,
Sylvain
^ permalink raw reply
* rockchip: drm: analogix_dp-rockchip would stock the kernel
From: Mark yao @ 2016-10-17 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1a7ebbe4-a9d8-610d-7cd5-41f5fe8355a5@soulik.info>
On 2016?10?16? 02:03, ayaka wrote:
> Hello:
> I meet a problem with eDP in rk3288 with the linux next 20161006,
> it is just like the early stage of 4.4
> kernel. I have added a eDP panel entry in the firefly reload board,
> once the kernel loaded analogix_dp-rockchip.ko, after printed the
> following two lines, the kernel stop working.
> rockchip-drm display-subsystem: bound ff940000.vop (ops
> vop_component_ops [rockchipdrm])
> rockchip-drm display-subsystem: bound ff930000.vop (ops
> vop_component_ops [rockchipdrm])
Hi ayaka
This log seems no problem.
How about tested it with build-in? we had test it with build-in.
Maybe this patch can help you, you can have a try.
https://patchwork.kernel.org/patch/9374135
Thanks.
> In the early June of the 4.4 kernel, I meet the same problem with
> rk3288 evb board with different error message, I have to disable the
> display system that time.
> In the today test, I meet the same problem with rk3399 evb board in
> 4.4.
> I have no idea what caused that, and it is a little hard to debug as
> kernel still would never kill that task.
> Randy Li
>
>
>
--
?ark Yao
^ permalink raw reply
* rockchip: drm: analogix_dp-rockchip would stock the kernel
From: Randy Li @ 2016-10-17 1:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <580421E5.9030609@rock-chips.com>
On 10/17/2016 08:57 AM, Mark yao wrote:
> On 2016?10?16? 02:03, ayaka wrote:
>> Hello:
>> I meet a problem with eDP in rk3288 with the linux next 20161006,
>> it is just like the early stage of 4.4
>> kernel. I have added a eDP panel entry in the firefly reload board,
>> once the kernel loaded analogix_dp-rockchip.ko, after printed the
>> following two lines, the kernel stop working.
>> rockchip-drm display-subsystem: bound ff940000.vop (ops
>> vop_component_ops [rockchipdrm])
>> rockchip-drm display-subsystem: bound ff930000.vop (ops
>> vop_component_ops [rockchipdrm])
>
> Hi ayaka
>
> This log seems no problem.
I found the problem, it is the eDP_AVDD_1V0 and eDP_AVDD_1V8 must have a
proper power supply. I would submit a patch to enable the regulator at
DP driver.
>
> How about tested it with build-in? we had test it with build-in.
>
> Maybe this patch can help you, you can have a try.
> https://patchwork.kernel.org/patch/9374135
>
> Thanks.
>
>> In the early June of the 4.4 kernel, I meet the same problem with
>> rk3288 evb board with different error message, I have to disable the
>> display system that time.
>> In the today test, I meet the same problem with rk3399 evb board in
>> 4.4.
>> I have no idea what caused that, and it is a little hard to debug as
>> kernel still would never kill that task.
>> Randy Li
>>
>>
>>
>
>
--
Randy Li
The third produce department
===========================================================================
This email message, including any attachments, is for the sole
use of the intended recipient(s) and may contain confidential and
privileged information. Any unauthorized review, use, disclosure or
distribution is prohibited. If you are not the intended recipient, please
contact the sender by reply e-mail and destroy all copies of the original
message. [Fuzhou Rockchip Electronics, INC. China mainland]
===========================================================================
^ permalink raw reply
* [PATCH v8 0/8] power: add power sequence library
From: Peter Chen @ 2016-10-17 1:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5097336.earU4jV2qd@vostro.rjw.lan>
On Fri, Oct 14, 2016 at 02:09:31PM +0200, Rafael J. Wysocki wrote:
> On Friday, October 14, 2016 10:59:47 AM Peter Chen wrote:
> > Hi all,
> >
> > This is a follow-up for my last power sequence framework patch set [1].
> > According to Rob Herring and Ulf Hansson's comments[2]. The kinds of
> > power sequence instances will be added at postcore_initcall, the match
> > criteria is compatible string first, if the compatible string is not
> > matched between dts and library, it will try to use generic power sequence.
> >
> > The host driver just needs to call of_pwrseq_on/of_pwrseq_off
> > if only one power sequence instance is needed, for more power sequences
> > are used, using of_pwrseq_on_list/of_pwrseq_off_list instead (eg, USB hub driver).
> >
> > In future, if there are special power sequence requirements, the special
> > power sequence library can be created.
> >
> > This patch set is tested on i.mx6 sabresx evk using a dts change, I use
> > two hot-plug devices to simulate this use case, the related binding
> > change is updated at patch [1/6], The udoo board changes were tested
> > using my last power sequence patch set.[3]
> >
> > Except for hard-wired MMC and USB devices, I find the USB ULPI PHY also
> > need to power on itself before it can be found by ULPI bus.
> >
> > [1] http://www.spinics.net/lists/linux-usb/msg142755.html
> > [2] http://www.spinics.net/lists/linux-usb/msg143106.html
> > [3] http://www.spinics.net/lists/linux-usb/msg142815.html
> >
> > Changes for v8:
> > - Allocate one extra pwrseq instance if pwrseq_get has succeed, it can avoid
> > preallocate instances problem which the number of instance is decided at
> > compile time, thanks for Heiko Stuebner's suggestion [Patch 2/8]
> > - Delete pwrseq_compatible_sample.c which is the demo purpose to show compatible
> > match method. [Patch 2/8]
> > - Add Maciej S. Szmigiero's tested-by. [Patch 7/8]
> >
> > Changes for v7:
> > - Create kinds of power sequence instance at postcore_initcall, and match
> > the instance with node using compatible string, the beneit of this is
> > the host driver doesn't need to consider which pwrseq instance needs
> > to be used, and pwrseq core will match it, however, it eats some memories
> > if less power sequence instances are used. [Patch 2/8]
> > - Add pwrseq_compatible_sample.c to test match pwrseq using device_id. [Patch 2/8]
> > - Fix the comments Vaibhav Hiremath adds for error path for clock and do not
> > use device_node for parameters at pwrseq_on. [Patch 2/8]
> > - Simplify the caller to use power sequence, follows Alan's commnets [Patch 4/8]
> > - Tested three pwrseq instances together using both specific compatible string and
> > generic libraries.
> >
> > Changes for v6:
> > - Add Matthias Kaehlcke's Reviewed-by and Tested-by. (patch [2/6])
> > - Change chipidea core of_node assignment for coming user. (patch [5/6])
> > - Applies Joshua Clayton's three dts changes for two boards,
> > the USB device's reg has only #address-cells, but without #size-cells.
> >
> > Changes for v5:
> > - Delete pwrseq_register/pwrseq_unregister, which is useless currently
> > - Fix the linker error when the pwrseq user is compiled as module
> >
> > Changes for v4:
> > - Create the patch on next-20160722
> > - Fix the of_node is not NULL after chipidea driver is unbinded [Patch 5/6]
> > - Using more friendly wait method for reset gpio [Patch 2/6]
> > - Support multiple input clocks [Patch 2/6]
> > - Add Rob Herring's ack for DT changes
> > - Add Joshua Clayton's Tested-by
> >
> > Changes for v3:
> > - Delete "power-sequence" property at binding-doc, and change related code
> > at both library and user code.
> > - Change binding-doc example node name with Rob's comments
> > - of_get_named_gpio_flags only gets the gpio, but without setting gpio flags,
> > add additional code request gpio with proper gpio flags
> > - Add Philipp Zabel's Ack and MAINTAINER's entry
> >
> > Changes for v2:
> > - Delete "pwrseq" prefix and clock-names for properties at dt binding
> > - Should use structure not but its pointer for kzalloc
> > - Since chipidea core has no of_node, let core's of_node equals glue
> > layer's at core's probe
> >
> > Joshua Clayton (2):
> > ARM: dts: imx6qdl: Enable usb node children with <reg>
> > ARM: dts: imx6q-evi: Fix onboard hub reset line
> >
> > Peter Chen (6):
> > binding-doc: power: pwrseq-generic: add binding doc for generic power
> > sequence library
> > power: add power sequence library
> > binding-doc: usb: usb-device: add optional properties for power
> > sequence
> > usb: core: add power sequence handling for USB devices
> > usb: chipidea: let chipidea core device of_node equal's glue layer
> > device of_node
> > ARM: dts: imx6qdl-udoo.dtsi: fix onboard USB HUB property
> >
> > .../bindings/power/pwrseq/pwrseq-generic.txt | 48 ++++++
> > .../devicetree/bindings/usb/usb-device.txt | 10 +-
> > MAINTAINERS | 9 +
> > arch/arm/boot/dts/imx6q-evi.dts | 25 +--
> > arch/arm/boot/dts/imx6qdl-udoo.dtsi | 26 ++-
> > arch/arm/boot/dts/imx6qdl.dtsi | 6 +
> > drivers/power/Kconfig | 1 +
> > drivers/power/Makefile | 1 +
> > drivers/power/pwrseq/Kconfig | 19 ++
> > drivers/power/pwrseq/Makefile | 2 +
> > drivers/power/pwrseq/core.c | 191 +++++++++++++++++++++
> > drivers/power/pwrseq/pwrseq_generic.c | 183 ++++++++++++++++++++
> > drivers/usb/chipidea/core.c | 27 ++-
> > drivers/usb/core/hub.c | 41 ++++-
> > drivers/usb/core/hub.h | 1 +
> > include/linux/power/pwrseq.h | 72 ++++++++
> > 16 files changed, 621 insertions(+), 41 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/power/pwrseq/pwrseq-generic.txt
> > create mode 100644 drivers/power/pwrseq/Kconfig
> > create mode 100644 drivers/power/pwrseq/Makefile
> > create mode 100644 drivers/power/pwrseq/core.c
> > create mode 100644 drivers/power/pwrseq/pwrseq_generic.c
> > create mode 100644 include/linux/power/pwrseq.h
>
> Meta question: Who's the maintainer you are targetting this at?
>
Sebastian Reichel mentioned it is better through your tree.
I could be the maintainer for it, and send "GIT PULL" for you
through my git
(https://git.kernel.org/cgit/linux/kernel/git/peter.chen/usb.git/)
Is it ok for you?
--
Best Regards,
Peter Chen
^ permalink raw reply
* [PATCH 2/2] ARM: dts: da850: add a node for the LCD controller
From: Tomi Valkeinen @ 2016-10-17 5:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2d276e51-9d37-8648-4aad-283bb2b23626@ti.com>
On 15/10/16 20:42, Sekhar Nori wrote:
>> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
>> index f79e1b9..32908ae 100644
>> --- a/arch/arm/boot/dts/da850.dtsi
>> +++ b/arch/arm/boot/dts/da850.dtsi
>
>> @@ -399,6 +420,14 @@
>> <&edma0 0 1>;
>> dma-names = "tx", "rx";
>> };
>> +
>> + display: display at 213000 {
>> + compatible = "ti,am33xx-tilcdc", "ti,da850-tilcdc";
>
> This should instead be:
>
> compatible = "ti,da850-tilcdc", "ti,am33xx-tilcdc";
>
> as the closest match should appear first in the list.
Actually I don't think that's correct. The LCDC on da850 is not
compatible with the LCDC on AM335x. I think it should be just
"ti,da850-tilcdc".
Tomi
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* [PATCH v2] spi: spi-fsl-dspi: Add DMA support for Vybrid
From: maitysanchayan at gmail.com @ 2016-10-17 6:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <607397542d083f13dc98909958672eeb0d326c79.1475578195.git.maitysanchayan@gmail.com>
Hello,
Ping?
Regards,
Sanchayan.
On 16-10-04 16:28:33, Sanchayan Maity wrote:
> Add DMA support for Vybrid.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> ---
> Changes since v1:
> - Change in the dspi_dma_xfer function. Use more apt DSPI_FIFO_SIZE
> instead of sizeof(u32)
> - Do not set RSER on every iteration of loop
>
> Tested on Toradex Colibri Vybrid VF61 module with spi based MCP CAN 251x
> and spidev using RX/TX loopback and based on shawn's for-next branch
> currently at 4.8-rc1.
>
> Regards,
> Sanchayan.
> ---
> drivers/spi/spi-fsl-dspi.c | 291 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 291 insertions(+)
>
> diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
> index 9e9dadb..0f81075 100644
> --- a/drivers/spi/spi-fsl-dspi.c
> +++ b/drivers/spi/spi-fsl-dspi.c
> @@ -15,6 +15,8 @@
>
> #include <linux/clk.h>
> #include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> #include <linux/err.h>
> #include <linux/errno.h>
> #include <linux/interrupt.h>
> @@ -40,6 +42,7 @@
> #define TRAN_STATE_WORD_ODD_NUM 0x04
>
> #define DSPI_FIFO_SIZE 4
> +#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
>
> #define SPI_MCR 0x00
> #define SPI_MCR_MASTER (1 << 31)
> @@ -71,6 +74,11 @@
> #define SPI_SR_EOQF 0x10000000
> #define SPI_SR_TCFQF 0x80000000
>
> +#define SPI_RSER_TFFFE BIT(25)
> +#define SPI_RSER_TFFFD BIT(24)
> +#define SPI_RSER_RFDFE BIT(17)
> +#define SPI_RSER_RFDFD BIT(16)
> +
> #define SPI_RSER 0x30
> #define SPI_RSER_EOQFE 0x10000000
> #define SPI_RSER_TCFQE 0x80000000
> @@ -108,6 +116,8 @@
>
> #define SPI_TCR_TCNT_MAX 0x10000
>
> +#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
> +
> struct chip_data {
> u32 mcr_val;
> u32 ctar_val;
> @@ -117,6 +127,7 @@ struct chip_data {
> enum dspi_trans_mode {
> DSPI_EOQ_MODE = 0,
> DSPI_TCFQ_MODE,
> + DSPI_DMA_MODE,
> };
>
> struct fsl_dspi_devtype_data {
> @@ -139,6 +150,22 @@ static const struct fsl_dspi_devtype_data ls2085a_data = {
> .max_clock_factor = 8,
> };
>
> +struct fsl_dspi_dma {
> + u32 curr_xfer_len;
> +
> + u32 *tx_dma_buf;
> + struct dma_chan *chan_tx;
> + dma_addr_t tx_dma_phys;
> + struct completion cmd_tx_complete;
> + struct dma_async_tx_descriptor *tx_desc;
> +
> + u32 *rx_dma_buf;
> + struct dma_chan *chan_rx;
> + dma_addr_t rx_dma_phys;
> + struct completion cmd_rx_complete;
> + struct dma_async_tx_descriptor *rx_desc;
> +};
> +
> struct fsl_dspi {
> struct spi_master *master;
> struct platform_device *pdev;
> @@ -165,6 +192,7 @@ struct fsl_dspi {
> u32 waitflags;
>
> u32 spi_tcnt;
> + struct fsl_dspi_dma *dma;
> };
>
> static inline int is_double_byte_mode(struct fsl_dspi *dspi)
> @@ -368,6 +396,259 @@ static void dspi_tcfq_read(struct fsl_dspi *dspi)
> dspi_data_from_popr(dspi, rx_word);
> }
>
> +static void dspi_tx_dma_callback(void *arg)
> +{
> + struct fsl_dspi *dspi = arg;
> + struct fsl_dspi_dma *dma = dspi->dma;
> +
> + complete(&dma->cmd_tx_complete);
> +}
> +
> +static void dspi_rx_dma_callback(void *arg)
> +{
> + struct fsl_dspi *dspi = arg;
> + struct fsl_dspi_dma *dma = dspi->dma;
> + int rx_word;
> + int i, len;
> + u16 d;
> +
> + rx_word = is_double_byte_mode(dspi);
> +
> + len = rx_word ? (dma->curr_xfer_len / 2) : dma->curr_xfer_len;
> +
> + if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) {
> + for (i = 0; i < len; i++) {
> + d = dspi->dma->rx_dma_buf[i];
> + rx_word ? (*(u16 *)dspi->rx = d) :
> + (*(u8 *)dspi->rx = d);
> + dspi->rx += rx_word + 1;
> + }
> + }
> +
> + complete(&dma->cmd_rx_complete);
> +}
> +
> +static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
> +{
> + struct fsl_dspi_dma *dma = dspi->dma;
> + struct device *dev = &dspi->pdev->dev;
> + int time_left;
> + int tx_word;
> + int i, len;
> + u16 val;
> +
> + tx_word = is_double_byte_mode(dspi);
> +
> + len = tx_word ? (dma->curr_xfer_len / 2) : dma->curr_xfer_len;
> +
> + for (i = 0; i < len - 1; i++) {
> + val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx;
> + dspi->dma->tx_dma_buf[i] =
> + SPI_PUSHR_TXDATA(val) | SPI_PUSHR_PCS(dspi->cs) |
> + SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT;
> + dspi->tx += tx_word + 1;
> + }
> +
> + val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx;
> + dspi->dma->tx_dma_buf[i] = SPI_PUSHR_TXDATA(val) |
> + SPI_PUSHR_PCS(dspi->cs) |
> + SPI_PUSHR_CTAS(0);
> + dspi->tx += tx_word + 1;
> +
> + dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
> + dma->tx_dma_phys,
> + DSPI_DMA_BUFSIZE, DMA_MEM_TO_DEV,
> + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> + if (!dma->tx_desc) {
> + dev_err(dev, "Not able to get desc for DMA xfer\n");
> + return -EIO;
> + }
> +
> + dma->tx_desc->callback = dspi_tx_dma_callback;
> + dma->tx_desc->callback_param = dspi;
> + if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
> + dev_err(dev, "DMA submit failed\n");
> + return -EINVAL;
> + }
> +
> + dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
> + dma->rx_dma_phys,
> + DSPI_DMA_BUFSIZE, DMA_DEV_TO_MEM,
> + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> + if (!dma->rx_desc) {
> + dev_err(dev, "Not able to get desc for DMA xfer\n");
> + return -EIO;
> + }
> +
> + dma->rx_desc->callback = dspi_rx_dma_callback;
> + dma->rx_desc->callback_param = dspi;
> + if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
> + dev_err(dev, "DMA submit failed\n");
> + return -EINVAL;
> + }
> +
> + reinit_completion(&dspi->dma->cmd_rx_complete);
> + reinit_completion(&dspi->dma->cmd_tx_complete);
> +
> + dma_async_issue_pending(dma->chan_rx);
> + dma_async_issue_pending(dma->chan_tx);
> +
> + time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
> + DMA_COMPLETION_TIMEOUT);
> + if (time_left == 0) {
> + dev_err(dev, "DMA tx timeout\n");
> + dmaengine_terminate_all(dma->chan_tx);
> + dmaengine_terminate_all(dma->chan_rx);
> + return -ETIMEDOUT;
> + }
> +
> + time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
> + DMA_COMPLETION_TIMEOUT);
> + if (time_left == 0) {
> + dev_err(dev, "DMA rx timeout\n");
> + dmaengine_terminate_all(dma->chan_tx);
> + dmaengine_terminate_all(dma->chan_rx);
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static int dspi_dma_xfer(struct fsl_dspi *dspi)
> +{
> + struct fsl_dspi_dma *dma = dspi->dma;
> + struct device *dev = &dspi->pdev->dev;
> + int curr_remaining_bytes;
> + int ret = 0;
> +
> + curr_remaining_bytes = dspi->len;
> + while (curr_remaining_bytes) {
> + /* Check if current transfer fits the DMA buffer */
> + dma->curr_xfer_len = curr_remaining_bytes;
> + if (curr_remaining_bytes > DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE)
> + dma->curr_xfer_len = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
> +
> + ret = dspi_next_xfer_dma_submit(dspi);
> + if (ret) {
> + dev_err(dev, "DMA transfer failed\n");
> + goto exit;
> +
> + } else {
> + curr_remaining_bytes -= dma->curr_xfer_len;
> + if (curr_remaining_bytes < 0)
> + curr_remaining_bytes = 0;
> + dspi->len = curr_remaining_bytes;
> + }
> + }
> +
> +exit:
> + return ret;
> +}
> +
> +static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
> +{
> + struct fsl_dspi_dma *dma;
> + struct dma_slave_config cfg;
> + struct device *dev = &dspi->pdev->dev;
> + int ret;
> +
> + dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
> + if (!dma)
> + return -ENOMEM;
> +
> + dma->chan_rx = dma_request_slave_channel(dev, "rx");
> + if (!dma->chan_rx) {
> + dev_err(dev, "rx dma channel not available\n");
> + ret = -ENODEV;
> + return ret;
> + }
> +
> + dma->chan_tx = dma_request_slave_channel(dev, "tx");
> + if (!dma->chan_tx) {
> + dev_err(dev, "tx dma channel not available\n");
> + ret = -ENODEV;
> + goto err_tx_channel;
> + }
> +
> + dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
> + &dma->tx_dma_phys, GFP_KERNEL);
> + if (!dma->tx_dma_buf) {
> + ret = -ENOMEM;
> + goto err_tx_dma_buf;
> + }
> +
> + dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
> + &dma->rx_dma_phys, GFP_KERNEL);
> + if (!dma->rx_dma_buf) {
> + ret = -ENOMEM;
> + goto err_rx_dma_buf;
> + }
> +
> + cfg.src_addr = phy_addr + SPI_POPR;
> + cfg.dst_addr = phy_addr + SPI_PUSHR;
> + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> + cfg.src_maxburst = 1;
> + cfg.dst_maxburst = 1;
> +
> + cfg.direction = DMA_DEV_TO_MEM;
> + ret = dmaengine_slave_config(dma->chan_rx, &cfg);
> + if (ret) {
> + dev_err(dev, "can't configure rx dma channel\n");
> + ret = -EINVAL;
> + goto err_slave_config;
> + }
> +
> + cfg.direction = DMA_MEM_TO_DEV;
> + ret = dmaengine_slave_config(dma->chan_tx, &cfg);
> + if (ret) {
> + dev_err(dev, "can't configure tx dma channel\n");
> + ret = -EINVAL;
> + goto err_slave_config;
> + }
> +
> + dspi->dma = dma;
> + dspi->devtype_data->trans_mode = DSPI_DMA_MODE;
> + init_completion(&dma->cmd_tx_complete);
> + init_completion(&dma->cmd_rx_complete);
> +
> + return 0;
> +
> +err_slave_config:
> + devm_kfree(dev, dma->rx_dma_buf);
> +err_rx_dma_buf:
> + devm_kfree(dev, dma->tx_dma_buf);
> +err_tx_dma_buf:
> + dma_release_channel(dma->chan_tx);
> +err_tx_channel:
> + dma_release_channel(dma->chan_rx);
> +
> + devm_kfree(dev, dma);
> + dspi->dma = NULL;
> +
> + return ret;
> +}
> +
> +static void dspi_release_dma(struct fsl_dspi *dspi)
> +{
> + struct fsl_dspi_dma *dma = dspi->dma;
> + struct device *dev = &dspi->pdev->dev;
> +
> + if (dma) {
> + if (dma->chan_tx) {
> + dma_unmap_single(dev, dma->tx_dma_phys,
> + DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
> + dma_release_channel(dma->chan_tx);
> + }
> +
> + if (dma->chan_rx) {
> + dma_unmap_single(dev, dma->rx_dma_phys,
> + DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
> + dma_release_channel(dma->chan_rx);
> + }
> + }
> +}
> +
> static int dspi_transfer_one_message(struct spi_master *master,
> struct spi_message *message)
> {
> @@ -424,6 +705,12 @@ static int dspi_transfer_one_message(struct spi_master *master,
> regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
> dspi_tcfq_write(dspi);
> break;
> + case DSPI_DMA_MODE:
> + regmap_write(dspi->regmap, SPI_RSER,
> + SPI_RSER_TFFFE | SPI_RSER_TFFFD |
> + SPI_RSER_RFDFE | SPI_RSER_RFDFD);
> + status = dspi_dma_xfer(dspi);
> + goto out;
> default:
> dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
> trans_mode);
> @@ -730,6 +1017,9 @@ static int dspi_probe(struct platform_device *pdev)
> }
> clk_prepare_enable(dspi->clk);
>
> + if (dspi_request_dma(dspi, res->start))
> + dev_warn(&pdev->dev, "can't get dma channels\n");
> +
> master->max_speed_hz =
> clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
>
> @@ -758,6 +1048,7 @@ static int dspi_remove(struct platform_device *pdev)
> struct fsl_dspi *dspi = spi_master_get_devdata(master);
>
> /* Disconnect from the SPI framework */
> + dspi_release_dma(dspi);
> clk_disable_unprepare(dspi->clk);
> spi_unregister_master(dspi->master);
> spi_master_put(dspi->master);
> --
> 2.10.0
>
^ permalink raw reply
* [PATCH] ARM: dts: imx6: Add support for Toradex Colibri iMX6 module
From: maitysanchayan at gmail.com @ 2016-10-17 6:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921112438.8661-1-maitysanchayan@gmail.com>
Hello,
Ping?
- Sanchayan.
On 16-09-21 16:54:38, Sanchayan Maity wrote:
> Add support for Toradex Colibri iMX6 module.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 253 ++++++++
> arch/arm/boot/dts/imx6qdl-colibri.dtsi | 890 +++++++++++++++++++++++++++
> 3 files changed, 1144 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> create mode 100644 arch/arm/boot/dts/imx6qdl-colibri.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f79cac2..44ff380 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -323,6 +323,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> imx6dl-aristainetos_7.dtb \
> imx6dl-aristainetos2_4.dtb \
> imx6dl-aristainetos2_7.dtb \
> + imx6dl-colibri-eval-v3.dtb \
> imx6dl-cubox-i.dtb \
> imx6dl-dfi-fs700-m60.dtb \
> imx6dl-gw51xx.dtb \
> diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> new file mode 100644
> index 0000000..e0c2172
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> @@ -0,0 +1,253 @@
> +/*
> + * Copyright 2014-2016 Toradex AG
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This file is distributed in the hope that it will be useful
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-colibri.dtsi"
> +
> +/ {
> + model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
> + compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
> + "fsl,imx6dl";
> +
> + aliases {
> + i2c0 = &i2c2;
> + i2c1 = &i2c3;
> + };
> +
> + aliases {
> + rtc0 = &rtc_i2c;
> + rtc1 = &snvs_rtc;
> + };
> +
> + clocks {
> + /* Fixed crystal dedicated to mcp251x */
> + clk16m: clk at 1 {
> + compatible = "fixed-clock";
> + reg = <1>;
> + #clock-cells = <0>;
> + clock-frequency = <16000000>;
> + clock-output-names = "clk16m";
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> + wakeup {
> + label = "Wake-Up";
> + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
> + linux,code = <KEY_WAKEUP>;
> + debounce-interval = <10>;
> + wakeup-source;
> + };
> + };
> +
> + lcd_display: display at di0 {
> + compatible = "fsl,imx-parallel-display";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interface-pix-fmt = "bgr666";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ipu1_lcdif>;
> + status = "okay";
> +
> + port at 0 {
> + reg = <0>;
> +
> + lcd_display_in: endpoint {
> + remote-endpoint = <&ipu1_di0_disp0>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> +
> + lcd_display_out: endpoint {
> + remote-endpoint = <&lcd_panel_in>;
> + };
> + };
> + };
> +
> + panel: panel {
> + /*
> + * edt,et057090dhu: EDT 5.7" LCD TFT
> + * edt,et070080dh6: EDT 7.0" LCD TFT
> + */
> + compatible = "edt,et057090dhu";
> + backlight = <&backlight>;
> +
> + port {
> + lcd_panel_in: endpoint {
> + remote-endpoint = <&lcd_display_out>;
> + };
> + };
> + };
> +};
> +
> +&backlight {
> + brightness-levels = <0 127 191 223 239 247 251 255>;
> + default-brightness-level = <1>;
> + status = "okay";
> +};
> +
> +/* Colibri SSP */
> +&ecspi4 {
> + status = "okay";
> +
> + mcp251x0: mcp251x at 1 {
> + compatible = "microchip,mcp2515";
> + reg = <0>;
> + clocks = <&clk16m>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <27 0x2>;
> + spi-max-frequency = <10000000>;
> + status = "okay";
> + };
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +/*
> + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
> + */
> +&i2c3 {
> + status = "okay";
> +
> + /* M41T0M6 real time clock on carrier board */
> + rtc_i2c: rtc at 68 {
> + compatible = "st,m41t00";
> + reg = <0x68>;
> + };
> +};
> +
> +&ipu1_di0_disp0 {
> + remote-endpoint = <&lcd_display_in>;
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +&pwm2 {
> + status = "okay";
> +};
> +
> +&pwm3 {
> + status = "okay";
> +};
> +
> +&pwm4 {
> + status = "okay";
> +};
> +
> +®_usb_host_vbus {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&usbh1 {
> + vbus-supply = <®_usb_host_vbus>;
> + status = "okay";
> +};
> +
> +&usbotg {
> + status = "okay";
> +};
> +
> +/* Colibri MMC */
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mmc_cd>;
> + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
> + status = "okay";
> +};
> +
> +&weim {
> + status = "okay";
> +
> + /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */
> + ranges = <0 0 0x08000000 0x02000000
> + 1 0 0x0a000000 0x02000000
> + 2 0 0x0c000000 0x02000000>;
> +
> + /* SRAM on Colibri nEXT_CS0 */
> + sram at 0,0 {
> + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
> + reg = <0 0 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bank-width = <2>;
> + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
> + 0x00000000 0x04000040 0x00000000>;
> + };
> +
> + /* SRAM on Colibri nEXT_CS1 */
> + sram at 1,0 {
> + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
> + reg = <1 0 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bank-width = <2>;
> + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
> + 0x00000000 0x04000040 0x00000000>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> new file mode 100644
> index 0000000..e6faa65
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> @@ -0,0 +1,890 @@
> +/*
> + * Copyright 2014-2016 Toradex AG
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This file is distributed in the hope that it will be useful
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Toradex Colibri iMX6DL/S Module";
> + compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_bl_on>;
> + pwms = <&pwm3 0 5000000>;
> + enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
> + status = "disabled";
> + };
> +
> + reg_1p8v: regulator-1p8v {
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_2p5v: regulator-2p5v {
> + compatible = "regulator-fixed";
> + regulator-name = "2P5V";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-always-on;
> + };
> +
> + reg_3p3v: regulator-3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_usb_host_vbus: regulator-usb-host-vbus {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
> + regulator-name = "usb_host_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
> + status = "disabled";
> + };
> +
> + sound {
> + compatible = "fsl,imx-audio-sgtl5000";
> + model = "imx6dl-colibri-sgtl5000";
> + ssi-controller = <&ssi1>;
> + audio-codec = <&codec>;
> + audio-routing =
> + "Headphone Jack", "HP_OUT",
> + "LINE_IN", "Line In Jack",
> + "MIC_IN", "Mic Jack",
> + "Mic Jack", "Mic Bias";
> + mux-int-port = <1>;
> + mux-ext-port = <5>;
> + };
> +
> + /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
> + sound_spdif: sound-spdif {
> + compatible = "fsl,imx-audio-spdif";
> + model = "imx-spdif";
> + spdif-controller = <&spdif>;
> + spdif-in;
> + spdif-out;
> + status = "disabled";
> + };
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
> + status = "okay";
> +};
> +
> +/* Optional on SODIMM 55/63 */
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + status = "disabled";
> +};
> +
> +/* Optional on SODIMM 178/188 */
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + status = "disabled";
> +};
> +
> +/* Colibri SSP */
> +&ecspi4 {
> + fsl,spi-num-chipselects = <1>;
> + cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi4>;
> + status = "disabled";
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rmii";
> + status = "okay";
> +};
> +
> +&hdmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmi_ddc>;
> + status = "disabled";
> +};
> +
> +/*
> + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
> + * touch screen controller
> + */
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + pmic: pfuze100 at 08 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1ab {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw1c_reg: sw1c {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw3a_reg: sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* vgen1: unused */
> +
> + vgen2_reg: vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* vgen3: unused */
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + codec: sgtl5000 at 0a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&clks IMX6QDL_CLK_CKO>;
> + VDDA-supply = <®_2p5v>;
> + VDDIO-supply = <®_3p3v>;
> + };
> +
> + /* STMPE811 touch screen controller */
> + stmpe811 at 41 {
> + compatible = "st,stmpe811";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_touch_int>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x41>;
> + interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-parent = <&gpio6>;
> + interrupt-controller;
> + id = <0>;
> + blocks = <0x5>;
> + irq-trigger = <0x1>;
> +
> + stmpe_touchscreen {
> + compatible = "st,stmpe-ts";
> + reg = <0>;
> + /* 3.25 MHz ADC clock speed */
> + st,adc-freq = <1>;
> + /* 8 sample average control */
> + st,ave-ctrl = <3>;
> + /* 7 length fractional part in z */
> + st,fraction-z = <7>;
> + /*
> + * 50 mA typical 80 mA max touchscreen drivers
> + * current limit value
> + */
> + st,i-drive = <1>;
> + /* 12-bit ADC */
> + st,mod-12b = <1>;
> + /* internal ADC reference */
> + st,ref-sel = <0>;
> + /* ADC converstion time: 80 clocks */
> + st,sample-time = <4>;
> + /* 1 ms panel driver settling time */
> + st,settling = <3>;
> + /* 5 ms touch detect interrupt delay */
> + st,touch-det-delay = <5>;
> + };
> + };
> +};
> +
> +/*
> + * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
> + */
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "recovery";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + pinctrl-1 = <&pinctrl_i2c3_recovery>;
> + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
> + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<B> */
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<D> */
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<A> */
> +&pwm3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm3>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<C> */
> +&pwm4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm4>;
> + status = "disabled";
> +};
> +
> +/* Optional S/PDIF out on SODIMM 137 */
> +&spdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spdif>;
> + status = "disabled";
> +};
> +
> +&ssi1 {
> + status = "okay";
> +};
> +
> +/* Colibri UART_A */
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
> + fsl,dte-mode;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +/* Colibri UART_B */
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2_dte>;
> + fsl,dte-mode;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +/* Colibri UART_C */
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3_dte>;
> + fsl,dte-mode;
> + status = "disabled";
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + disable-over-current;
> + dr_mode = "peripheral";
> + status = "disabled";
> +};
> +
> +/* Colibri MMC */
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + vqmmc-supply = <®_3p3v>;
> + bus-width = <4>;
> + voltage-ranges = <3300 3300>;
> + status = "disabled";
> +};
> +
> +/* eMMC */
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + vqmmc-supply = <®_3p3v>;
> + bus-width = <8>;
> + voltage-ranges = <3300 3300>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&weim {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
> + &pinctrl_weim_cs1 &pinctrl_weim_cs2
> + &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + pinctrl_audmux: audmuxgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
> + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
> + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
> + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
> + /* SGTL5000 sys_mclk */
> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
> + >;
> + };
> +
> + pinctrl_cam_mclk: cammclkgrp {
> + fsl,pins = <
> + /* Parallel Camera CAM sys_mclk */
> + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
> + >;
> + };
> +
> + pinctrl_ecspi4: ecspi4grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
> + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
> + /* SPI CS */
> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
> + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
> + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
> + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
> + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
> + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
> + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
> + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
> + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpio_bl_on: gpioblon {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpio_keys: gpiokeys {
> + fsl,pins = <
> + /* Power button */
> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0
> + >;
> + };
> +
> + pinctrl_hdmi_ddc: hdmiddcgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3_recovery: i2c3recoverygrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
> + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
> + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
> + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
> + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
> + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
> + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
> + MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
> + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
> + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
> + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
> + /* Disable PWM pins on camera interface */
> + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
> + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
> + >;
> + };
> +
> + pinctrl_ipu1_lcdif: ipu1lcdifgrp {
> + fsl,pins = <
> + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
> + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
> + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
> + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
> + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
> + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
> + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
> + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
> + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
> + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
> + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
> + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
> + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
> + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
> + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
> + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
> + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
> + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
> + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
> + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
> + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
> + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
> + >;
> + };
> +
> + pinctrl_mic_gnd: gpiomicgnd {
> + fsl,pins = <
> + /* Controls Mic GND, PU or '1' pull Mic GND to GND */
> + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
> + >;
> + };
> +
> + pinctrl_mmc_cd: gpiommccd {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
> + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
> + >;
> + };
> +
> + pinctrl_pwm3: pwm3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
> + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
> + >;
> + };
> +
> + pinctrl_pwm4: pwm4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
> + fsl,pins = <
> + /* USBH_EN */
> + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
> + >;
> + };
> +
> + pinctrl_spdif: spdifgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
> + >;
> + };
> +
> + pinctrl_touch_int: gpiotouchintgrp {
> + fsl,pins = <
> + /* STMPE811 interrupt */
> + MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
> + >;
> + };
> +
> + pinctrl_uart1_dce: uart1dcegrp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + /* DTE mode */
> + pinctrl_uart1_dte: uart1dtegrp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
> + >;
> + };
> +
> + /* Additional DTR, DSR, DCD */
> + pinctrl_uart1_ctrl: uart1ctrlgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
> + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
> + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
> + >;
> + };
> +
> + pinctrl_uart2_dte: uart2dtegrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
> + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
> + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
> + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart3_dte: uart3dtegrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbc_det: usbcdetgrp {
> + fsl,pins = <
> + /* USBC_DET */
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
> + /* USBC_DET_EN */
> + MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
> + /* USBC_DET_OVERWRITE */
> + MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + /* eMMC reset */
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
> + /* eMMC reset */
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
> + >;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
> + /* eMMC reset */
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
> + >;
> + };
> +
> + pinctrl_weim_cs0: weimcs0grp {
> + fsl,pins = <
> + /* nEXT_CS0 */
> + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_cs1: weimcs1grp {
> + fsl,pins = <
> + /* nEXT_CS1 */
> + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_cs2: weimcs2grp {
> + fsl,pins = <
> + /* nEXT_CS2 */
> + MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_sram: weimsramgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
> + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
> + /* Data */
> + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
> + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
> + /* Address */
> + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
> + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
> + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
> + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
> + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
> + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
> + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
> + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
> + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
> + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
> + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
> + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
> + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
> + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
> + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
> + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_rdnwr: weimrdnwr {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
> + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
> + >;
> + };
> +
> + pinctrl_weim_npwe: weimnpwe {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
> + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
> + >;
> + };
> +
> + /* ADDRESS[16:18] [25] used as GPIO */
> + pinctrl_weim_gpio_1: weimgpio-1 {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
> + >;
> + };
> +
> + /* ADDRESS[19:24] used as GPIO */
> + pinctrl_weim_gpio_2: weimgpio-2 {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
> + >;
> + };
> +
> + /* DATA[16:31] used as GPIO */
> + pinctrl_weim_gpio_3: weimgpio-3 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
> + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
> + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
> + >;
> + };
> +
> + /* DQM[0:3] used as GPIO */
> + pinctrl_weim_gpio_4: weimgpio-4 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
> + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
> + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
> + >;
> + };
> +
> + /* RDY used as GPIO */
> + pinctrl_weim_gpio_5: weimgpio-5 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
> + >;
> + };
> +
> + /* ADDRESS[16] DATA[30] used as GPIO */
> + pinctrl_weim_gpio_6: weimgpio-6 {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
> + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
> + >;
> + };
> +};
> --
> 2.10.0
>
^ permalink raw reply
* [PATCH 2/2] mmc: sdhci-iproc: support standard byte register accesses
From: Adrian Hunter @ 2016-10-17 6:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476297352-7812-3-git-send-email-scott.branden@broadcom.com>
On 12/10/16 21:35, Scott Branden wrote:
> Add bytewise register accesses support for newer versions of IPROC
> SDHCI controllers.
> Previous sdhci-iproc versions of SDIO controllers
> (such as Raspberry Pi and Cygnus) only allowed for 32-bit register
> accesses.
>
> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
> Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
^ permalink raw reply
* [STLinux Kernel] [PATCH 28/57] [media] c8sectpfe: don't break long lines
From: Peter Griffin @ 2016-10-17 6:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b82cb64c6328c81104143d8a509d4ab6f77873a2.1476475771.git.mchehab@s-opensource.com>
On Fri, 14 Oct 2016, Mauro Carvalho Chehab wrote:
> Due to the 80-cols checkpatch warnings, several strings
> were broken into multiple lines. This is not considered
> a good practice anymore, as it makes harder to grep for
> strings at the source code. So, join those continuation
> lines.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
> ---
> drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c | 15 +++++----------
Acked-by: Peter Griffin <peter.griffin@linaro.org>
^ permalink raw reply
* [PATCH V3 0/8] IOMMU probe deferral support
From: Sricharan @ 2016-10-17 6:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <12cfb59f-f7ca-d4df-eb7f-42348e357979@samsung.com>
>-----Original Message-----
>From: Sricharan [mailto:sricharan at codeaurora.org]
>Sent: Wednesday, October 12, 2016 11:55 AM
>To: 'Marek Szyprowski' <m.szyprowski@samsung.com>; 'will.deacon at arm.com' <will.deacon@arm.com>; 'robin.murphy at arm.com'
><robin.murphy@arm.com>; 'joro at 8bytes.org' <joro@8bytes.org>; 'iommu at lists.linux-foundation.org' <iommu@lists.linux-
>foundation.org>; 'linux-arm-kernel at lists.infradead.org' <linux-arm-kernel@lists.infradead.org>; 'linux-arm-msm at vger.kernel.org'
><linux-arm-msm@vger.kernel.org>; 'laurent.pinchart at ideasonboard.com' <laurent.pinchart@ideasonboard.com>;
>'tfiga at chromium.org' <tfiga@chromium.org>; 'srinivas.kandagatla at linaro.org' <srinivas.kandagatla@linaro.org>
>Subject: RE: [PATCH V3 0/8] IOMMU probe deferral support
>
>Hi Marek,
>
>>Hi Sricharan,
>>
>>
>>On 2016-10-04 19:03, Sricharan R wrote:
>>> Initial post from Laurent Pinchart[1]. This is
>>> series calls the dma ops configuration for the devices
>>> at a generic place so that it works for all busses.
>>> The dma_configure_ops for a device is now called during
>>> the device_attach callback just before the probe of the
>>> bus/driver is called. Similarly dma_deconfigure is called during
>>> device/driver_detach path.
>>>
>>>
>>> pci_bus_add_devices (platform/amba)(_device_create/driver_register)
>>> | |
>>> pci_bus_add_device (device_add/driver_register)
>>> | |
>>> device_attach device_initial_probe
>>> | |
>>> __device_attach_driver __device_attach_driver
>>> |
>>> driver_probe_device
>>> |
>>> really_probe
>>> |
>>> dma_configure
>>>
>>> Similarly on the device/driver_unregister path __device_release_driver is
>>> called which inturn calls dma_deconfigure.
>>>
>>> If the ACPI bus code follows the same, we can add acpi_dma_configure
>>> at the same place as of_dma_configure.
>>>
>>> This series is based on the recently merged Generic DT bindings for
>>> PCI IOMMUs and ARM SMMU from Robin Murphy robin.murphy at arm.com [2]
>>>
>>> This time tested this with platform and pci device for probe deferral
>>> and reprobe on arm64 based platform. There is an issue on the cleanup
>>> path for arm64 though, where there is WARN_ON if the dma_ops is reset while
>>> device is attached to an domain in arch_teardown_dma_ops.
>>> But with iommu_groups created from the iommu driver, the device is always
>>> attached to a domain/default_domain. So so the WARN has to be removed/handled
>>> probably.
>>
>>Thanks for continuing work on this feature! Your can add my:
>>
>>Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>
Hi Will,Robin,Joerg,
I have tested the probe deferral for platform/pcie bus devices based on latest Generic bindings
series merged [1], for pci/arm-smmu.
It will good to know from you on whats the right way to take this forward ?
Regards,
Sricharan
^ permalink raw reply
* [PATCH V3 0/8] IOMMU probe deferral support
From: Sricharan @ 2016-10-17 7:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <12cfb59f-f7ca-d4df-eb7f-42348e357979@samsung.com>
Resending, missed out on the link last time.
>-----Original Message-----
From: linux-arm-msm-owner@vger.kernel.org [mailto:linux-arm-msm-owner at vger.kernel.org] On Behalf Of Marek Szyprowski
>Sent: Monday, October 10, 2016 6:07 PM
>To: Sricharan R <sricharan@codeaurora.org>; will.deacon at arm.com; robin.murphy at arm.com; joro at 8bytes.org; iommu at lists.linux-
>foundation.org; linux-arm-kernel at lists.infradead.org; linux-arm-msm at vger.kernel.org; laurent.pinchart at ideasonboard.com;
>tfiga at chromium.org; srinivas.kandagatla at linaro.org
>Subject: Re: [PATCH V3 0/8] IOMMU probe deferral support
>
>Hi Sricharan,
>
>
>On 2016-10-04 19:03, Sricharan R wrote:
>> Initial post from Laurent Pinchart[1]. This is
>> series calls the dma ops configuration for the devices
>> at a generic place so that it works for all busses.
>> The dma_configure_ops for a device is now called during
>> the device_attach callback just before the probe of the
>> bus/driver is called. Similarly dma_deconfigure is called during
>> device/driver_detach path.
>>
>>
>> pci_bus_add_devices (platform/amba)(_device_create/driver_register)
>> | |
>> pci_bus_add_device (device_add/driver_register)
>> | |
>> device_attach device_initial_probe
>> | |
>> __device_attach_driver __device_attach_driver
>> |
>> driver_probe_device
>> |
>> really_probe
>> |
>> dma_configure
>>
>> Similarly on the device/driver_unregister path __device_release_driver
>> is
>> called which inturn calls dma_deconfigure.
>>
>> If the ACPI bus code follows the same, we can add acpi_dma_configure
>> at the same place as of_dma_configure.
>>
>> This series is based on the recently merged Generic DT bindings for
>> PCI IOMMUs and ARM SMMU from Robin Murphy robin.murphy at arm.com [2]
>>
>> This time tested this with platform and pci device for probe deferral
>> and reprobe on arm64 based platform. There is an issue on the cleanup
>> path for arm64 though, where there is WARN_ON if the dma_ops is reset
>> while
>> device is attached to an domain in arch_teardown_dma_ops.
>> But with iommu_groups created from the iommu driver, the device is
>> always
>> attached to a domain/default_domain. So so the WARN has to be
>> removed/handled
>> probably.
>
>Thanks for continuing work on this feature! Your can add my:
>
>Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
>
Hi Will,Robin,Joerg,
I have tested the probe deferral for platform/pcie bus devices based on latest Generic DT bindings
series merged [1], for pci/arm-smmu.
It will be good to know from you on whats the right way to take this forward ?
[1] http://www.spinics.net/lists/devicetree/msg142943.html
Regards,
Sricharan
^ permalink raw reply
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