* [PATCH] clk: mvebu: armada-37xx-periph: Fix the clock provider registration
From: Stephen Boyd @ 2016-10-17 22:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160929142855.30408-1-gregory.clement@free-electrons.com>
On 09/29, Gregory CLEMENT wrote:
> While trying using a peripheral clock on a driver, I saw that the clock
> pointer returned by the provider was NULL.
>
> The problem was a missing indirection. It was the pointer stored in the
> hws array which needed to be updated not the value it contains.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v2] clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.
From: Stephen Boyd @ 2016-10-17 22:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930170727.32544-1-eric@anholt.net>
On 09/30, Eric Anholt wrote:
> Fixes setting low-resolution video modes on HDMI. Now the PLLH_PIX
> divider adjusts itself until the PLLH is within bounds.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] clk: mvebu: armada-37xx-periph: Fix the clock gate flag
From: Stephen Boyd @ 2016-10-17 22:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160930083359.14943-1-gregory.clement@free-electrons.com>
On 09/30, Gregory CLEMENT wrote:
> For the gate part of the peripheral clock setting the bit disables the
> clock and clearing it enables the clock. This is not the default behavior
> of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init
From: Stephen Boyd @ 2016-10-17 22:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475933892-16021-1-git-send-email-shawn.guo@linaro.org>
On 10/08, Shawn Guo wrote:
> The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but
> also reset controller. It worked fine that single sysctrl/mediactrl
> device node in DT can be used to initialize clock driver and populate
> platform device for reset controller. But it stops working after
> commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks")
> gets merged. The commit sets flag OF_POPULATED during clock
> initialization to skip the platform device populating for the same
> device node. On hi6220, it effectively makes hi6220-sysctrl reset
> driver not probe any more.
>
> The patch changes hi6220 sysctrl and mediactrl clock init macro from
> CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using
> the same hardware block can continue working.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] bus: qcom-ebi2: depend on ARCH_QCOM or COMPILE_TEST
From: Stephen Boyd @ 2016-10-17 23:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475582179-5085-1-git-send-email-linus.walleij@linaro.org>
On 10/04, Linus Walleij wrote:
> This hides the option for people who do not want their Kconfig
> vision cluttered (i.e. x86) and enables compile testing apart
> from the supported main arch.
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v2] arm64: defconfig: enable EEPROM_AT25 config option
From: Scott Branden @ 2016-10-17 23:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMijByw1FYt42toNF6pAEykks_agetQybhgMQj8nAc6xdg@mail.gmail.com>
Hi Olof,
On 16-10-17 02:58 PM, Olof Johansson wrote:
> Hi,
>
> On Wed, Oct 12, 2016 at 11:51 AM, Scott Branden
> <scott.branden@broadcom.com> wrote:
>> Enable support for on board SPI EEPROM by turning on
>> CONFIG_EEPROM_AT25. This needs to be on in order to
>> boot and test the kernel with a static rootfs image
>> that is not rebuilt everytime the kernel is rebuilt.
>
> If we did this for every kernel option we'd get a huge kernel.
>
> In general, we've said that static options for what's needed to boot
> to rootfs (i.e. storage and network drivers for nfsroot) are fine to
> enable statically.
>
> I doubt you need the EEPROM driver to boot to rootfs on your system,
> so please enable it as a module instead.
>
> Look into using config fragments in case you need to modify the
> options for local builds, it should be a convenient way to have a
> small delta to apply to fit your internal needs, instead of completely
> forking the config file.
Do you allow such config fragments to be upstreamed or do we need to
maintain these in our tree?
>
>
> -Olof
>
Thanks,
Scott
^ permalink raw reply
* [PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding
From: Scott Branden @ 2016-10-17 23:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6f96a6cc-7e12-6827-ce88-65e2accda576@broadcom.com>
Florian,
Could you add this to the queue?
On 16-10-17 02:50 PM, Ray Jui wrote:
> Hi Robin,
>
> On 10/17/2016 5:13 AM, Robin Murphy wrote:
>> With the "mmu-masters" property now deprecated and optional, the
>> generic binding offers a more efficient way to specify no masters.
>>
>> CC: Ray Jui <rjui@broadcom.com>
>> CC: Scott Branden <sbranden@broadcom.com>
>> CC: Jon Mason <jonmason@broadcom.com>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> index d95dc408629a..65530e193e8a 100644
>> --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> @@ -248,7 +248,7 @@
>> <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
>> - mmu-masters;
>> + #iommu-cells = <1>;
>> };
>>
>> pinctrl: pinctrl at 6501d130 {
>>
>
> Thanks!
>
> Acked-by: Ray Jui <ray.jui@broadcom.com>
Thanks,
Scott
^ permalink raw reply
* [PATCH 2/5] staging/vchi: Fix build warnings when formatting pointers on aarch64.
From: Eric Anholt @ 2016-10-17 23:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017202834.GA30101@kroah.com>
Greg Kroah-Hartman <gregkh@linuxfoundation.org> writes:
> On Mon, Oct 17, 2016 at 12:44:03PM -0700, Eric Anholt wrote:
>> The code was generally using "%x" to print and "(unsigned int)" to
>> cast the pointers, but we have %p for printing pointers in the same
>> format without any broken casts.
>
> I already did this work, it's all checked into my tree, and is in
> linux-next now. You were cc:ed on the patches as well.
I actually haven't seen any of those messages about the patches. It
looks like it's actually that notmuch is still failing to parse some
mails (they apparently disagree with postfix on how maildir files should
be formatted, so they just drop some mail on the floor).
I did check the staging-testing branch before I started, since that's
where things were last I knew, and didn't know it had moved to -next.
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^ permalink raw reply
* [PATCH v2] arm64: defconfig: enable EEPROM_AT25 config option
From: Olof Johansson @ 2016-10-18 0:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <207706e2-8fd4-748f-2ee7-3c372b447a7d@broadcom.com>
On Mon, Oct 17, 2016 at 4:24 PM, Scott Branden
<scott.branden@broadcom.com> wrote:
> Hi Olof,
>
> On 16-10-17 02:58 PM, Olof Johansson wrote:
>>
>> Hi,
>>
>> On Wed, Oct 12, 2016 at 11:51 AM, Scott Branden
>> <scott.branden@broadcom.com> wrote:
>>>
>>> Enable support for on board SPI EEPROM by turning on
>>> CONFIG_EEPROM_AT25. This needs to be on in order to
>>> boot and test the kernel with a static rootfs image
>>> that is not rebuilt everytime the kernel is rebuilt.
>>
>>
>> If we did this for every kernel option we'd get a huge kernel.
>>
>> In general, we've said that static options for what's needed to boot
>> to rootfs (i.e. storage and network drivers for nfsroot) are fine to
>> enable statically.
>>
>> I doubt you need the EEPROM driver to boot to rootfs on your system,
>> so please enable it as a module instead.
>>
>> Look into using config fragments in case you need to modify the
>> options for local builds, it should be a convenient way to have a
>> small delta to apply to fit your internal needs, instead of completely
>> forking the config file.
>
>
> Do you allow such config fragments to be upstreamed or do we need to
> maintain these in our tree?
There's no place for them upstream. Maintain locally or in a separate repo.
-Olof
^ permalink raw reply
* [PATCH] extcon: qcom-spmi-misc: Sync the extcon state on interrupt
From: Stephen Boyd @ 2016-10-18 0:16 UTC (permalink / raw)
To: linux-arm-kernel
The driver was changed after submission to use the new style APIs
like extcon_set_state(). Unfortunately, that only sets the state,
and doesn't notify any consumers that the cable state has
changed. Use extcon_set_state_sync() here instead so that we
notify cable consumers of the state change. This fixes USB
host-device role switching on the db8074 platform.
Fixes: 38085c987f52 ("extcon: Add support for qcom SPMI PMIC USB id detection hardware")
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
---
drivers/extcon/extcon-qcom-spmi-misc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/extcon/extcon-qcom-spmi-misc.c b/drivers/extcon/extcon-qcom-spmi-misc.c
index ca957a5f4291..b8cde096a808 100644
--- a/drivers/extcon/extcon-qcom-spmi-misc.c
+++ b/drivers/extcon/extcon-qcom-spmi-misc.c
@@ -51,7 +51,7 @@ static void qcom_usb_extcon_detect_cable(struct work_struct *work)
if (ret)
return;
- extcon_set_state(info->edev, EXTCON_USB_HOST, !id);
+ extcon_set_state_sync(info->edev, EXTCON_USB_HOST, !id);
}
static irqreturn_t qcom_usb_irq_handler(int irq, void *dev_id)
--
2.10.0.297.gf6727b0
^ permalink raw reply related
* [PATCH RESEND 1/3] clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf
From: Fabio Estevam @ 2016-10-18 0:29 UTC (permalink / raw)
To: linux-arm-kernel
From: Philipp Zabel <p.zabel@pengutronix.de>
MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the
parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never
succeed.
Disable the handshake mechanism to allow changing the frequency of
mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI
clock.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
drivers/clk/imx/clk-imx6q.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index ce8ea10..66825a8 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -156,6 +156,19 @@ static struct clk ** const uart_clks[] __initconst = {
NULL
};
+#define CCM_CCDR 0x04
+
+#define CCDR_MMDC_CH1_MASK BIT(16)
+
+static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base)
+{
+ unsigned int reg;
+
+ reg = readl_relaxed(ccm_base + CCM_CCDR);
+ reg |= CCDR_MMDC_CH1_MASK;
+ writel_relaxed(reg, ccm_base + CCM_CCDR);
+}
+
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
@@ -297,6 +310,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
base = of_iomap(np, 0);
WARN_ON(!base);
+ imx6q_mmdc_ch1_mask_handshake(base);
+
/* name reg shift width parent_names num_parents */
clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
--
2.7.4
^ permalink raw reply related
* [PATCH RESEND 2/3] clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only
From: Fabio Estevam @ 2016-10-18 0:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476750554-21961-1-git-send-email-festevam@gmail.com>
From: Philipp Zabel <p.zabel@pengutronix.de>
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. As this can not be guaranteed by
the clock framework during runtime, make the ldb_di[x]_sel muxes read-only.
A workaround to set the muxes once during boot could be added to the
kernel or bootloader.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
drivers/clk/imx/clk-imx6q.c | 10 ++--------
drivers/clk/imx/clk.h | 8 ++++++++
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 66825a8..a4f4de5 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -345,8 +345,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
- clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
- clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+ clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
+ clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
@@ -597,12 +597,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
- if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
- clk_on_imx6dl()) {
- clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
- clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
- }
-
clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
if (clk_on_imx6dl())
clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 3799ff8..4afad3b 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -75,6 +75,14 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate)
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
+static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char **parents, int num_parents)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
+ shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_fixed_factor(const char *name,
const char *parent, unsigned int mult, unsigned int div)
{
--
2.7.4
^ permalink raw reply related
* [PATCH RESEND 3/3] clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK
From: Fabio Estevam @ 2016-10-18 0:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476750554-21961-1-git-send-email-festevam@gmail.com>
From: Fabio Estevam <fabio.estevam@nxp.com>
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. This patch ensures that correct
steps are followed when ldb_di_clk parent is switched in the beginning
of boot. The glitchy muxes are then registered as read-only. The clock
parent can be selected using the assigned-clocks and
assigned-clock-parents properties of the ccm device tree node:
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
};
The issue is explained in detail in EB821 ("LDB Clock Switch Procedure &
i.MX6 Asynchronous Clock Switching Guidelines") [1].
[1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>
Tested-by Joshua Clayton <stillcompiling@gmail.com>
Tested-by: Charles Kang <Charles.Kang@advantech.com.tw>
Acked-by: Shawn Guo <shawnguo@kernel.org>
---
drivers/clk/imx/clk-imx6q.c | 264 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 259 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index a4f4de5..42ffc1c 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -156,9 +156,90 @@ static struct clk ** const uart_clks[] __initconst = {
NULL
};
+static int ldb_di_sel_by_clock_id(int clock_id)
+{
+ switch (clock_id) {
+ case IMX6QDL_CLK_PLL5_VIDEO_DIV:
+ if (clk_on_imx6q() &&
+ imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
+ return -ENOENT;
+ return 0;
+ case IMX6QDL_CLK_PLL2_PFD0_352M:
+ return 1;
+ case IMX6QDL_CLK_PLL2_PFD2_396M:
+ return 2;
+ case IMX6QDL_CLK_MMDC_CH1_AXI:
+ return 3;
+ case IMX6QDL_CLK_PLL3_USB_OTG:
+ return 4;
+ default:
+ return -ENOENT;
+ }
+}
+
+static void of_assigned_ldb_sels(struct device_node *node,
+ unsigned int *ldb_di0_sel,
+ unsigned int *ldb_di1_sel)
+{
+ struct of_phandle_args clkspec;
+ int index, rc, num_parents;
+ int parent, child, sel;
+
+ num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
+ "#clock-cells");
+ for (index = 0; index < num_parents; index++) {
+ rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
+ "#clock-cells", index, &clkspec);
+ if (rc < 0) {
+ /* skip empty (null) phandles */
+ if (rc == -ENOENT)
+ continue;
+ else
+ return;
+ }
+ if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
+ pr_err("ccm: parent clock %d not in ccm\n", index);
+ return;
+ }
+ parent = clkspec.args[0];
+
+ rc = of_parse_phandle_with_args(node, "assigned-clocks",
+ "#clock-cells", index, &clkspec);
+ if (rc < 0)
+ return;
+ if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
+ pr_err("ccm: child clock %d not in ccm\n", index);
+ return;
+ }
+ child = clkspec.args[0];
+
+ if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
+ child != IMX6QDL_CLK_LDB_DI1_SEL)
+ continue;
+
+ sel = ldb_di_sel_by_clock_id(parent);
+ if (sel < 0) {
+ pr_err("ccm: invalid ldb_di%d parent clock: %d\n",
+ child == IMX6QDL_CLK_LDB_DI1_SEL, parent);
+ continue;
+ }
+
+ if (child == IMX6QDL_CLK_LDB_DI0_SEL)
+ *ldb_di0_sel = sel;
+ if (child == IMX6QDL_CLK_LDB_DI1_SEL)
+ *ldb_di1_sel = sel;
+ }
+}
+
#define CCM_CCDR 0x04
+#define CCM_CCSR 0x0c
+#define CCM_CS2CDR 0x2c
+
+#define CCDR_MMDC_CH1_MASK BIT(16)
+#define CCSR_PLL3_SW_CLK_SEL BIT(0)
-#define CCDR_MMDC_CH1_MASK BIT(16)
+#define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9
+#define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12
static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base)
{
@@ -169,10 +250,173 @@ static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base)
writel_relaxed(reg, ccm_base + CCM_CCDR);
}
+/*
+ * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk
+ * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the
+ * bypass clock source, since there is no CG bit for mmdc_ch1.
+ */
+static void mmdc_ch1_disable(void __iomem *ccm_base)
+{
+ unsigned int reg;
+
+ clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL],
+ clk[IMX6QDL_CLK_PLL3_USB_OTG]);
+
+ /*
+ * Handshake with mmdc_ch1 module must be masked when changing
+ * periph2_clk_sel.
+ */
+ clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]);
+
+ /* Disable pll3_sw_clk by selecting the bypass clock source */
+ reg = readl_relaxed(ccm_base + CCM_CCSR);
+ reg |= CCSR_PLL3_SW_CLK_SEL;
+ writel_relaxed(reg, ccm_base + CCM_CCSR);
+}
+
+static void mmdc_ch1_reenable(void __iomem *ccm_base)
+{
+ unsigned int reg;
+
+ /* Enable pll3_sw_clk by disabling the bypass */
+ reg = readl_relaxed(ccm_base + CCM_CCSR);
+ reg &= ~CCSR_PLL3_SW_CLK_SEL;
+ writel_relaxed(reg, ccm_base + CCM_CCSR);
+
+ clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]);
+}
+
+/*
+ * We have to follow a strict procedure when changing the LDB clock source,
+ * otherwise we risk introducing a glitch that can lock up the LDB divider.
+ * Things to keep in mind:
+ *
+ * 1. The current and new parent clock inputs to the mux must be disabled.
+ * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which
+ * has no CG bit.
+ * 3. pll2_pfd2_396m can not be gated if it is used as memory clock.
+ * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four
+ * options are in one mux and the PLL3 option along with three unused
+ * inputs is in a second mux. There is a third mux with two inputs used
+ * to decide between the first and second 4-port mux:
+ *
+ * pll5_video_div 0 --|\
+ * pll2_pfd0_352m 1 --| |_
+ * pll2_pfd2_396m 2 --| | `-|\
+ * mmdc_ch1_axi 3 --|/ | |
+ * | |--
+ * pll3_usb_otg 4 --|\ | |
+ * 5 --| |_,-|/
+ * 6 --| |
+ * 7 --|/
+ *
+ * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes@the same time.
+ * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below
+ * switches the parent to the bottom mux first and then manipulates the top
+ * mux to ensure that no glitch will enter the divider.
+ */
+static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base)
+{
+ unsigned int reg;
+ unsigned int sel[2][4];
+ int i;
+
+ reg = readl_relaxed(ccm_base + CCM_CS2CDR);
+ sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7;
+ sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7;
+
+ sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0];
+ sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0];
+
+ of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
+
+ for (i = 0; i < 2; i++) {
+ /* Warn if a glitch might have been introduced already */
+ if (sel[i][0] != 3) {
+ pr_warn("ccm: ldb_di%d_sel already changed from reset value: %d\n",
+ i, sel[i][0]);
+ }
+
+ if (sel[i][0] == sel[i][3])
+ continue;
+
+ /* Only switch to or from pll2_pfd2_396m if it is disabled */
+ if ((sel[i][0] == 2 || sel[i][3] == 2) &&
+ (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) ==
+ clk[IMX6QDL_CLK_PLL2_PFD2_396M])) {
+ pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n",
+ i);
+ sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0];
+ continue;
+ }
+
+ /* First switch to the bottom mux */
+ sel[i][1] = sel[i][0] | 4;
+
+ /* Then configure the top mux before switching back to it */
+ sel[i][2] = sel[i][3] | 4;
+
+ pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i,
+ sel[i][0], sel[i][1], sel[i][2], sel[i][3]);
+ }
+
+ if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3])
+ return;
+
+ mmdc_ch1_disable(ccm_base);
+
+ for (i = 1; i < 4; i++) {
+ reg = readl_relaxed(ccm_base + CCM_CS2CDR);
+ reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
+ (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
+ reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
+ (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
+ writel_relaxed(reg, ccm_base + CCM_CS2CDR);
+ }
+
+ mmdc_ch1_reenable(ccm_base);
+}
+
+#define CCM_ANALOG_PLL_VIDEO 0xa0
+#define CCM_ANALOG_PFD_480 0xf0
+#define CCM_ANALOG_PFD_528 0x100
+
+#define PLL_ENABLE BIT(13)
+
+#define PFD0_CLKGATE BIT(7)
+#define PFD1_CLKGATE BIT(15)
+#define PFD2_CLKGATE BIT(23)
+#define PFD3_CLKGATE BIT(31)
+
+static void disable_anatop_clocks(void __iomem *anatop_base)
+{
+ unsigned int reg;
+
+ /* Make sure PLL2 PFDs 0-2 are gated */
+ reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528);
+ /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */
+ if (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) ==
+ clk[IMX6QDL_CLK_PLL2_PFD2_396M])
+ reg |= PFD0_CLKGATE | PFD1_CLKGATE;
+ else
+ reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE;
+ writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528);
+
+ /* Make sure PLL3 PFDs 0-3 are gated */
+ reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480);
+ reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE;
+ writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480);
+
+ /* Make sure PLL5 is disabled */
+ reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO);
+ reg &= ~PLL_ENABLE;
+ writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO);
+}
+
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
- void __iomem *base;
+ void __iomem *anatop_base, *base;
int i;
int ret;
@@ -185,7 +429,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
- base = of_iomap(np, 0);
+ anatop_base = base = of_iomap(np, 0);
WARN_ON(!base);
/* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
@@ -310,8 +554,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
base = of_iomap(np, 0);
WARN_ON(!base);
- imx6q_mmdc_ch1_mask_handshake(base);
-
/* name reg shift width parent_names num_parents */
clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
@@ -345,6 +587,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
+
+ disable_anatop_clocks(anatop_base);
+
+ imx6q_mmdc_ch1_mask_handshake(base);
+
+ /*
+ * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
+ * bug. Set the muxes to the requested values before registering the
+ * ldb_di_sel clocks.
+ */
+ init_ldb_clks(np, base);
+
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
--
2.7.4
^ permalink raw reply related
* [PATCH v8 0/8] power: add power sequence library
From: Rafael J. Wysocki @ 2016-10-18 0:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017013058.GA1301@b29397-desktop>
On Monday, October 17, 2016 09:30:59 AM Peter Chen wrote:
> On Fri, Oct 14, 2016 at 02:09:31PM +0200, Rafael J. Wysocki wrote:
> > On Friday, October 14, 2016 10:59:47 AM Peter Chen wrote:
> > > Hi all,
> > >
> > > This is a follow-up for my last power sequence framework patch set [1].
> > > According to Rob Herring and Ulf Hansson's comments[2]. The kinds of
> > > power sequence instances will be added at postcore_initcall, the match
> > > criteria is compatible string first, if the compatible string is not
> > > matched between dts and library, it will try to use generic power sequence.
> > >
> > > The host driver just needs to call of_pwrseq_on/of_pwrseq_off
> > > if only one power sequence instance is needed, for more power sequences
> > > are used, using of_pwrseq_on_list/of_pwrseq_off_list instead (eg, USB hub driver).
> > >
> > > In future, if there are special power sequence requirements, the special
> > > power sequence library can be created.
> > >
> > > This patch set is tested on i.mx6 sabresx evk using a dts change, I use
> > > two hot-plug devices to simulate this use case, the related binding
> > > change is updated at patch [1/6], The udoo board changes were tested
> > > using my last power sequence patch set.[3]
> > >
> > > Except for hard-wired MMC and USB devices, I find the USB ULPI PHY also
> > > need to power on itself before it can be found by ULPI bus.
> > >
> > > [1] http://www.spinics.net/lists/linux-usb/msg142755.html
> > > [2] http://www.spinics.net/lists/linux-usb/msg143106.html
> > > [3] http://www.spinics.net/lists/linux-usb/msg142815.html
> > >
> > > Changes for v8:
> > > - Allocate one extra pwrseq instance if pwrseq_get has succeed, it can avoid
> > > preallocate instances problem which the number of instance is decided at
> > > compile time, thanks for Heiko Stuebner's suggestion [Patch 2/8]
> > > - Delete pwrseq_compatible_sample.c which is the demo purpose to show compatible
> > > match method. [Patch 2/8]
> > > - Add Maciej S. Szmigiero's tested-by. [Patch 7/8]
> > >
> > > Changes for v7:
> > > - Create kinds of power sequence instance at postcore_initcall, and match
> > > the instance with node using compatible string, the beneit of this is
> > > the host driver doesn't need to consider which pwrseq instance needs
> > > to be used, and pwrseq core will match it, however, it eats some memories
> > > if less power sequence instances are used. [Patch 2/8]
> > > - Add pwrseq_compatible_sample.c to test match pwrseq using device_id. [Patch 2/8]
> > > - Fix the comments Vaibhav Hiremath adds for error path for clock and do not
> > > use device_node for parameters at pwrseq_on. [Patch 2/8]
> > > - Simplify the caller to use power sequence, follows Alan's commnets [Patch 4/8]
> > > - Tested three pwrseq instances together using both specific compatible string and
> > > generic libraries.
> > >
> > > Changes for v6:
> > > - Add Matthias Kaehlcke's Reviewed-by and Tested-by. (patch [2/6])
> > > - Change chipidea core of_node assignment for coming user. (patch [5/6])
> > > - Applies Joshua Clayton's three dts changes for two boards,
> > > the USB device's reg has only #address-cells, but without #size-cells.
> > >
> > > Changes for v5:
> > > - Delete pwrseq_register/pwrseq_unregister, which is useless currently
> > > - Fix the linker error when the pwrseq user is compiled as module
> > >
> > > Changes for v4:
> > > - Create the patch on next-20160722
> > > - Fix the of_node is not NULL after chipidea driver is unbinded [Patch 5/6]
> > > - Using more friendly wait method for reset gpio [Patch 2/6]
> > > - Support multiple input clocks [Patch 2/6]
> > > - Add Rob Herring's ack for DT changes
> > > - Add Joshua Clayton's Tested-by
> > >
> > > Changes for v3:
> > > - Delete "power-sequence" property at binding-doc, and change related code
> > > at both library and user code.
> > > - Change binding-doc example node name with Rob's comments
> > > - of_get_named_gpio_flags only gets the gpio, but without setting gpio flags,
> > > add additional code request gpio with proper gpio flags
> > > - Add Philipp Zabel's Ack and MAINTAINER's entry
> > >
> > > Changes for v2:
> > > - Delete "pwrseq" prefix and clock-names for properties at dt binding
> > > - Should use structure not but its pointer for kzalloc
> > > - Since chipidea core has no of_node, let core's of_node equals glue
> > > layer's at core's probe
> > >
> > > Joshua Clayton (2):
> > > ARM: dts: imx6qdl: Enable usb node children with <reg>
> > > ARM: dts: imx6q-evi: Fix onboard hub reset line
> > >
> > > Peter Chen (6):
> > > binding-doc: power: pwrseq-generic: add binding doc for generic power
> > > sequence library
> > > power: add power sequence library
> > > binding-doc: usb: usb-device: add optional properties for power
> > > sequence
> > > usb: core: add power sequence handling for USB devices
> > > usb: chipidea: let chipidea core device of_node equal's glue layer
> > > device of_node
> > > ARM: dts: imx6qdl-udoo.dtsi: fix onboard USB HUB property
> > >
> > > .../bindings/power/pwrseq/pwrseq-generic.txt | 48 ++++++
> > > .../devicetree/bindings/usb/usb-device.txt | 10 +-
> > > MAINTAINERS | 9 +
> > > arch/arm/boot/dts/imx6q-evi.dts | 25 +--
> > > arch/arm/boot/dts/imx6qdl-udoo.dtsi | 26 ++-
> > > arch/arm/boot/dts/imx6qdl.dtsi | 6 +
> > > drivers/power/Kconfig | 1 +
> > > drivers/power/Makefile | 1 +
> > > drivers/power/pwrseq/Kconfig | 19 ++
> > > drivers/power/pwrseq/Makefile | 2 +
> > > drivers/power/pwrseq/core.c | 191 +++++++++++++++++++++
> > > drivers/power/pwrseq/pwrseq_generic.c | 183 ++++++++++++++++++++
> > > drivers/usb/chipidea/core.c | 27 ++-
> > > drivers/usb/core/hub.c | 41 ++++-
> > > drivers/usb/core/hub.h | 1 +
> > > include/linux/power/pwrseq.h | 72 ++++++++
> > > 16 files changed, 621 insertions(+), 41 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/power/pwrseq/pwrseq-generic.txt
> > > create mode 100644 drivers/power/pwrseq/Kconfig
> > > create mode 100644 drivers/power/pwrseq/Makefile
> > > create mode 100644 drivers/power/pwrseq/core.c
> > > create mode 100644 drivers/power/pwrseq/pwrseq_generic.c
> > > create mode 100644 include/linux/power/pwrseq.h
> >
> > Meta question: Who's the maintainer you are targetting this at?
> >
>
> Sebastian Reichel mentioned it is better through your tree.
> I could be the maintainer for it, and send "GIT PULL" for you
> through my git
> (https://git.kernel.org/cgit/linux/kernel/git/peter.chen/usb.git/)
> Is it ok for you?
Let me review the series first. :-)
Thanks,
Rafael
^ permalink raw reply
* [PATCH v5 0/2] qcom OTG regulator support
From: Stephen Boyd @ 2016-10-18 0:42 UTC (permalink / raw)
To: linux-arm-kernel
This is a resend/resurrection of Tim's patches to add support
for the OTG regulator on some of qcom's PMICs[1]. I've made
some minor modifications to the driver to make it work, but
otherwise it works fine with my USB otg testing. Changes
are noted in a maintainer tag.
Tim, did you want to me to fix the name? I pulled these from patchwork
and it seems you sent it as "Bird, Tim" which may have not been
intentional.
https://patchwork.kernel.org/patch/7857021/
Bird, Tim (2):
dt-binding: power: Add otg regulator binding
power: qcom_smbb: Add otg regulator for control of vbus
.../devicetree/bindings/power/supply/qcom_smbb.txt | 19 ++++++
drivers/power/supply/qcom_smbb.c | 70 ++++++++++++++++++++++
2 files changed, 89 insertions(+)
--
2.10.0.297.gf6727b0
^ permalink raw reply
* [PATCH v5 1/2] dt-binding: power: Add otg regulator binding
From: Stephen Boyd @ 2016-10-18 0:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018004251.28733-1-stephen.boyd@linaro.org>
From: "Bird, Tim" <Tim.Bird@sonymobile.com>
Add a binding for the regulator which controls the OTG chargepath switch.
The OTG switch gets its power from pm8941_5vs1, and that should be
expressed as a usb_otg_in-supply property in the DT node for the
charger driver. The regulator name is "otg-vbus".
Signed-off-by: Tim Bird <tim.bird@sonymobile.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
---
.../devicetree/bindings/power/supply/qcom_smbb.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/supply/qcom_smbb.txt b/Documentation/devicetree/bindings/power/supply/qcom_smbb.txt
index 65b88fac854b..06f8a5ddb68e 100644
--- a/Documentation/devicetree/bindings/power/supply/qcom_smbb.txt
+++ b/Documentation/devicetree/bindings/power/supply/qcom_smbb.txt
@@ -105,6 +105,22 @@ PROPERTIES
regulation must be done externally to fully comply with
the JEITA safety guidelines if this flag is set.
+- usb_otg_in-supply:
+ Usage: optional
+ Value type: <phandle>
+ Description: Reference to the regulator supplying power to the USB_OTG_IN
+ pin.
+
+child nodes:
+- otg-vbus:
+ Usage: optional
+ Description: This node defines a regulator used to control the direction
+ of VBUS voltage - specifically: whether to supply voltage
+ to VBUS for host mode operation of the OTG port, or allow
+ input voltage from external VBUS for charging. In the
+ hardware, the supply for this regulator comes from
+ usb_otg_in-supply.
+
EXAMPLE
charger at 1000 {
compatible = "qcom,pm8941-charger";
@@ -128,4 +144,7 @@ charger at 1000 {
qcom,fast-charge-current-limit = <1000000>;
qcom,dc-charge-current-limit = <1000000>;
+ usb_otg_in-supply = <&pm8941_5vs1>;
+
+ otg-vbus {};
};
--
2.10.0.297.gf6727b0
^ permalink raw reply related
* [PATCH v5 2/2] power: qcom_smbb: Add otg regulator for control of vbus
From: Stephen Boyd @ 2016-10-18 0:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018004251.28733-1-stephen.boyd@linaro.org>
From: "Bird, Tim" <Tim.Bird@sonymobile.com>
Add a regulator to control the OTG chargepath switch. This
is used by USB code to control VBUS direction - out for host mode
on the OTG port, and in for charging mode.
Signed-off-by: Tim Bird <tim.bird@sonymobile.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
[stephen.boyd at linaro.org: Fix supply name, constify ops, drop
machine.h and of_regulator.h includes]
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
---
drivers/power/supply/qcom_smbb.c | 70 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/drivers/power/supply/qcom_smbb.c b/drivers/power/supply/qcom_smbb.c
index b5896ba2a602..5bdde6108c12 100644
--- a/drivers/power/supply/qcom_smbb.c
+++ b/drivers/power/supply/qcom_smbb.c
@@ -35,6 +35,7 @@
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/extcon.h>
+#include <linux/regulator/driver.h>
#define SMBB_CHG_VMAX 0x040
#define SMBB_CHG_VSAFE 0x041
@@ -72,6 +73,8 @@
#define BTC_CTRL_HOT_EXT_N BIT(0)
#define SMBB_USB_IMAX 0x344
+#define SMBB_USB_OTG_CTL 0x348
+#define OTG_CTL_EN BIT(0)
#define SMBB_USB_ENUM_TIMER_STOP 0x34e
#define ENUM_TIMER_STOP BIT(0)
#define SMBB_USB_SEC_ACCESS 0x3d0
@@ -125,6 +128,9 @@ struct smbb_charger {
struct power_supply *dc_psy;
struct power_supply *bat_psy;
struct regmap *regmap;
+
+ struct regulator_desc otg_rdesc;
+ struct regulator_dev *otg_reg;
};
static const unsigned int smbb_usb_extcon_cable[] = {
@@ -787,12 +793,56 @@ static const struct power_supply_desc dc_psy_desc = {
.property_is_writeable = smbb_charger_writable_property,
};
+static int smbb_chg_otg_enable(struct regulator_dev *rdev)
+{
+ struct smbb_charger *chg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = regmap_update_bits(chg->regmap, chg->addr + SMBB_USB_OTG_CTL,
+ OTG_CTL_EN, OTG_CTL_EN);
+ if (rc)
+ dev_err(chg->dev, "failed to update OTG_CTL\n");
+ return rc;
+}
+
+static int smbb_chg_otg_disable(struct regulator_dev *rdev)
+{
+ struct smbb_charger *chg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = regmap_update_bits(chg->regmap, chg->addr + SMBB_USB_OTG_CTL,
+ OTG_CTL_EN, 0);
+ if (rc)
+ dev_err(chg->dev, "failed to update OTG_CTL\n");
+ return rc;
+}
+
+static int smbb_chg_otg_is_enabled(struct regulator_dev *rdev)
+{
+ struct smbb_charger *chg = rdev_get_drvdata(rdev);
+ unsigned int value = 0;
+ int rc;
+
+ rc = regmap_read(chg->regmap, chg->addr + SMBB_USB_OTG_CTL, &value);
+ if (rc)
+ dev_err(chg->dev, "failed to read OTG_CTL\n");
+
+ return !!(value & OTG_CTL_EN);
+}
+
+static const struct regulator_ops smbb_chg_otg_ops = {
+ .enable = smbb_chg_otg_enable,
+ .disable = smbb_chg_otg_disable,
+ .is_enabled = smbb_chg_otg_is_enabled,
+};
+
static int smbb_charger_probe(struct platform_device *pdev)
{
struct power_supply_config bat_cfg = {};
struct power_supply_config usb_cfg = {};
struct power_supply_config dc_cfg = {};
struct smbb_charger *chg;
+ struct regulator_config config = { };
int rc, i;
chg = devm_kzalloc(&pdev->dev, sizeof(*chg), GFP_KERNEL);
@@ -905,6 +955,26 @@ static int smbb_charger_probe(struct platform_device *pdev)
}
}
+ /*
+ * otg regulator is used to control VBUS voltage direction
+ * when USB switches between host and gadget mode
+ */
+ chg->otg_rdesc.id = -1;
+ chg->otg_rdesc.name = "otg-vbus";
+ chg->otg_rdesc.ops = &smbb_chg_otg_ops;
+ chg->otg_rdesc.owner = THIS_MODULE;
+ chg->otg_rdesc.type = REGULATOR_VOLTAGE;
+ chg->otg_rdesc.supply_name = "usb-otg-in";
+ chg->otg_rdesc.of_match = "otg-vbus";
+
+ config.dev = &pdev->dev;
+ config.driver_data = chg;
+
+ chg->otg_reg = devm_regulator_register(&pdev->dev, &chg->otg_rdesc,
+ &config);
+ if (IS_ERR(chg->otg_reg))
+ return PTR_ERR(chg->otg_reg);
+
chg->jeita_ext_temp = of_property_read_bool(pdev->dev.of_node,
"qcom,jeita-extended-temp-range");
--
2.10.0.297.gf6727b0
^ permalink raw reply related
* [PATCH] media: s5p-mfc include buffer size in error message
From: Shuah Khan @ 2016-10-18 0:43 UTC (permalink / raw)
To: linux-arm-kernel
Include buffer size in s5p_mfc_alloc_priv_buf() the error message when it
fails to allocate the buffer. Remove the debug message that does the same.
Signed-off-by: Shuah Khan <shuahkh@osg.samsung.com>
---
drivers/media/platform/s5p-mfc/s5p_mfc_opr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c
index 1e72502..eee16a1 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.c
@@ -40,12 +40,11 @@ void s5p_mfc_init_regs(struct s5p_mfc_dev *dev)
int s5p_mfc_alloc_priv_buf(struct device *dev, dma_addr_t base,
struct s5p_mfc_priv_buf *b)
{
- mfc_debug(3, "Allocating priv: %zu\n", b->size);
-
b->virt = dma_alloc_coherent(dev, b->size, &b->dma, GFP_KERNEL);
if (!b->virt) {
- mfc_err("Allocating private buffer failed\n");
+ mfc_err("Allocating private buffer of size %zu failed\n",
+ b->size);
return -ENOMEM;
}
--
2.7.4
^ permalink raw reply related
* [PATCH -next] PCI: rockchip: Add missing of_node_put() in rockchip_pcie_init_irq_domain()
From: Shawn Lin @ 2016-10-18 0:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476716242-31684-1-git-send-email-weiyj.lk@gmail.com>
? 2016/10/17 22:57, Wei Yongjun ??:
> From: Wei Yongjun <weiyongjun1@huawei.com>
>
> This node pointer is returned by of_get_next_child() with refcount
> incremented in this function. of_node_put() on it before exitting
> this function on error.
>
> This is detected by Coccinelle semantic patch.
Thanks for fixing this.
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
> ---
> drivers/pci/host/pcie-rockchip.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index e0b22da..ab88859 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -949,6 +949,7 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
> &intx_domain_ops, rockchip);
> if (!rockchip->irq_domain) {
> dev_err(dev, "failed to get a INTx IRQ domain\n");
> + of_node_put(intc);
> return -EINVAL;
> }
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Best Regards
Shawn Lin
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: Updated NAND DT properties for NS2 SVK
From: Florian Fainelli @ 2016-10-18 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8832e18c-cd77-9fe1-8bd8-a2d65390666a@broadcom.com>
On 10/17/2016 01:49 PM, Ray Jui wrote:
> Hi Florian,
>
> Would you be able to help to queue the following patch for v4.10? Sorry
> I did not include you in the "To" field of the original email.
Applied, thanks!
--
Florian
^ permalink raw reply
* [PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding
From: Florian Fainelli @ 2016-10-18 0:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f2de1b15adb2f57529734a4769ef04d9cde3cc5d.1476706244.git.robin.murphy@arm.com>
On 10/17/2016 05:13 AM, Robin Murphy wrote:
> With the "mmu-masters" property now deprecated and optional, the
> generic binding offers a more efficient way to specify no masters.
>
> CC: Ray Jui <rjui@broadcom.com>
> CC: Scott Branden <sbranden@broadcom.com>
> CC: Jon Mason <jonmason@broadcom.com>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Applied, did you use get_maintainers.pl for this file? It did not land
in bcm-kernel-feedback-list at broadcom.com and as such did not get picked
by the patchwork instance behind..
--
Florian
^ permalink raw reply
* Can s3c2416 use two usb host?
From: jiangyanpin77 @ 2016-10-18 1:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
I am working on samsung s3c2416 ARM based Soc on
linux 3.1.8 kernel. By default, the Soc has one
USB host and one USB device/host. My USB host is
working fine. Since I need to use two USB host on my system,
I need to enable the USB device/host as a USB host.
I am using ARM9 based s3c2416 processor. The SoC has one USB host
controller and one USB host/device controller. What are the
register settings that should be done to enable both USB
interfaces as USB host controller. ? There is a register PHYCTRL
with address 0x4C00_0080. Its bit[0] says something on USB host
mode and USB device mode. Is it this register which I should
work on or any more register configurations are required ?
The following are the changes I have made for the same:
Register Address value
-----------------------------
PHYPWR 0x4C00_0084 0x0
PWRCFG 0x4C00_0060 (1<<4)
URSTCON 0x4C00_0088 (0<<2)|(1<<1)|(1<<0)
URSTCON 0x4C00_0088 (0<<2)|(0<<1)|(0<<0)
PHYCTRL 0x4C00_0080 (0<<3)|(0<<2)|(1<<1)|(1<<0)
UCLKCON 0x4C00_008C 0<<31)|(0<<2)|(1<<1)|(1<<0)
Once I try to plug in a USB mass storage device (whose driver is present in
kernel), I get the following error:
usb 1-2: new full speed USB device using s3c2410-ohci and address 10
usb 1-2: device descriptor read/64, error -62
usb 1-2: device descriptor read/64, error -62
usb 1-2: new full speed USB device using s3c2410-ohci and address 11
usb 1-2: device descriptor read/64, error -62
usb 1-2: device descriptor read/64, error -62
usb 1-2: new full speed USB device using s3c2410-ohci and address 12
usb 1-2: device not accepting address 12, error -62
usb 1-2: new full speed USB device using s3c2410-ohci and address 13
usb 1-2: device not accepting address 13, error -62
Why is it throwing this error ? Is there any driver for USB hub missing in
linux 3.1.8 kernel, or do I need to modify more on register settings.
Please help.
Thank You
YanpinJiang
^ permalink raw reply
* [PATCH v8 0/8] power: add power sequence library
From: Peter Chen @ 2016-10-18 1:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5513671.XlE8bb9pVt@vostro.rjw.lan>
On Tue, Oct 18, 2016 at 02:35:38AM +0200, Rafael J. Wysocki wrote:
> On Monday, October 17, 2016 09:30:59 AM Peter Chen wrote:
> > On Fri, Oct 14, 2016 at 02:09:31PM +0200, Rafael J. Wysocki wrote:
> > > On Friday, October 14, 2016 10:59:47 AM Peter Chen wrote:
> > > > Hi all,
> > > >
> > > > This is a follow-up for my last power sequence framework patch set [1].
> > > > According to Rob Herring and Ulf Hansson's comments[2]. The kinds of
> > > > power sequence instances will be added at postcore_initcall, the match
> > > > criteria is compatible string first, if the compatible string is not
> > > > matched between dts and library, it will try to use generic power sequence.
> > > >
> > > > The host driver just needs to call of_pwrseq_on/of_pwrseq_off
> > > > if only one power sequence instance is needed, for more power sequences
> > > > are used, using of_pwrseq_on_list/of_pwrseq_off_list instead (eg, USB hub driver).
> > > >
> > > > In future, if there are special power sequence requirements, the special
> > > > power sequence library can be created.
> > > >
> > > > This patch set is tested on i.mx6 sabresx evk using a dts change, I use
> > > > two hot-plug devices to simulate this use case, the related binding
> > > > change is updated at patch [1/6], The udoo board changes were tested
> > > > using my last power sequence patch set.[3]
> > > >
> > > > Except for hard-wired MMC and USB devices, I find the USB ULPI PHY also
> > > > need to power on itself before it can be found by ULPI bus.
> > > >
> > > > [1] http://www.spinics.net/lists/linux-usb/msg142755.html
> > > > [2] http://www.spinics.net/lists/linux-usb/msg143106.html
> > > > [3] http://www.spinics.net/lists/linux-usb/msg142815.html
> > > >
> > > > Changes for v8:
> > > > - Allocate one extra pwrseq instance if pwrseq_get has succeed, it can avoid
> > > > preallocate instances problem which the number of instance is decided at
> > > > compile time, thanks for Heiko Stuebner's suggestion [Patch 2/8]
> > > > - Delete pwrseq_compatible_sample.c which is the demo purpose to show compatible
> > > > match method. [Patch 2/8]
> > > > - Add Maciej S. Szmigiero's tested-by. [Patch 7/8]
> > > >
> > > > Changes for v7:
> > > > - Create kinds of power sequence instance at postcore_initcall, and match
> > > > the instance with node using compatible string, the beneit of this is
> > > > the host driver doesn't need to consider which pwrseq instance needs
> > > > to be used, and pwrseq core will match it, however, it eats some memories
> > > > if less power sequence instances are used. [Patch 2/8]
> > > > - Add pwrseq_compatible_sample.c to test match pwrseq using device_id. [Patch 2/8]
> > > > - Fix the comments Vaibhav Hiremath adds for error path for clock and do not
> > > > use device_node for parameters at pwrseq_on. [Patch 2/8]
> > > > - Simplify the caller to use power sequence, follows Alan's commnets [Patch 4/8]
> > > > - Tested three pwrseq instances together using both specific compatible string and
> > > > generic libraries.
> > > >
> > > > Changes for v6:
> > > > - Add Matthias Kaehlcke's Reviewed-by and Tested-by. (patch [2/6])
> > > > - Change chipidea core of_node assignment for coming user. (patch [5/6])
> > > > - Applies Joshua Clayton's three dts changes for two boards,
> > > > the USB device's reg has only #address-cells, but without #size-cells.
> > > >
> > > > Changes for v5:
> > > > - Delete pwrseq_register/pwrseq_unregister, which is useless currently
> > > > - Fix the linker error when the pwrseq user is compiled as module
> > > >
> > > > Changes for v4:
> > > > - Create the patch on next-20160722
> > > > - Fix the of_node is not NULL after chipidea driver is unbinded [Patch 5/6]
> > > > - Using more friendly wait method for reset gpio [Patch 2/6]
> > > > - Support multiple input clocks [Patch 2/6]
> > > > - Add Rob Herring's ack for DT changes
> > > > - Add Joshua Clayton's Tested-by
> > > >
> > > > Changes for v3:
> > > > - Delete "power-sequence" property at binding-doc, and change related code
> > > > at both library and user code.
> > > > - Change binding-doc example node name with Rob's comments
> > > > - of_get_named_gpio_flags only gets the gpio, but without setting gpio flags,
> > > > add additional code request gpio with proper gpio flags
> > > > - Add Philipp Zabel's Ack and MAINTAINER's entry
> > > >
> > > > Changes for v2:
> > > > - Delete "pwrseq" prefix and clock-names for properties at dt binding
> > > > - Should use structure not but its pointer for kzalloc
> > > > - Since chipidea core has no of_node, let core's of_node equals glue
> > > > layer's at core's probe
> > > >
> > > > Joshua Clayton (2):
> > > > ARM: dts: imx6qdl: Enable usb node children with <reg>
> > > > ARM: dts: imx6q-evi: Fix onboard hub reset line
> > > >
> > > > Peter Chen (6):
> > > > binding-doc: power: pwrseq-generic: add binding doc for generic power
> > > > sequence library
> > > > power: add power sequence library
> > > > binding-doc: usb: usb-device: add optional properties for power
> > > > sequence
> > > > usb: core: add power sequence handling for USB devices
> > > > usb: chipidea: let chipidea core device of_node equal's glue layer
> > > > device of_node
> > > > ARM: dts: imx6qdl-udoo.dtsi: fix onboard USB HUB property
> > > >
> > > > .../bindings/power/pwrseq/pwrseq-generic.txt | 48 ++++++
> > > > .../devicetree/bindings/usb/usb-device.txt | 10 +-
> > > > MAINTAINERS | 9 +
> > > > arch/arm/boot/dts/imx6q-evi.dts | 25 +--
> > > > arch/arm/boot/dts/imx6qdl-udoo.dtsi | 26 ++-
> > > > arch/arm/boot/dts/imx6qdl.dtsi | 6 +
> > > > drivers/power/Kconfig | 1 +
> > > > drivers/power/Makefile | 1 +
> > > > drivers/power/pwrseq/Kconfig | 19 ++
> > > > drivers/power/pwrseq/Makefile | 2 +
> > > > drivers/power/pwrseq/core.c | 191 +++++++++++++++++++++
> > > > drivers/power/pwrseq/pwrseq_generic.c | 183 ++++++++++++++++++++
> > > > drivers/usb/chipidea/core.c | 27 ++-
> > > > drivers/usb/core/hub.c | 41 ++++-
> > > > drivers/usb/core/hub.h | 1 +
> > > > include/linux/power/pwrseq.h | 72 ++++++++
> > > > 16 files changed, 621 insertions(+), 41 deletions(-)
> > > > create mode 100644 Documentation/devicetree/bindings/power/pwrseq/pwrseq-generic.txt
> > > > create mode 100644 drivers/power/pwrseq/Kconfig
> > > > create mode 100644 drivers/power/pwrseq/Makefile
> > > > create mode 100644 drivers/power/pwrseq/core.c
> > > > create mode 100644 drivers/power/pwrseq/pwrseq_generic.c
> > > > create mode 100644 include/linux/power/pwrseq.h
> > >
> > > Meta question: Who's the maintainer you are targetting this at?
> > >
> >
> > Sebastian Reichel mentioned it is better through your tree.
> > I could be the maintainer for it, and send "GIT PULL" for you
> > through my git
> > (https://git.kernel.org/cgit/linux/kernel/git/peter.chen/usb.git/)
> > Is it ok for you?
>
> Let me review the series first. :-)
>
Thanks, Rafael.
--
Best Regards,
Peter Chen
^ permalink raw reply
* [PATCH v5 0/3] MT8173 HDMI 4K support
From: CK Hu @ 2016-10-18 1:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475118135-56780-1-git-send-email-bibby.hsieh@mediatek.com>
On Thu, 2016-09-29 at 11:02 +0800, Bibby Hsieh wrote:
> This is MT8173 HDMI 4K support PATCH v5, based on 4.8-rc1.
>
> In order to support HDMI 4K on MT8173,
> we have to make some modifications.
> 1) Make sure that mtk_hdmi_send_infoframe is sent successfully.
> 2) Enhance the HDMI driving current to improve performance.
> 3) Make sure that pixel clock is 297MHz when resolution is 4K.
>
For this series,
Acked-by: CK Hu <ck.hu@mediatek.com>
> Changes since v4:
> - Update commit message and patch title.
>
> Changes since v3:
> - Rebase to 4.8-rc1.
> - The valid range of tvdpll is 1G to 2G Hz, so, we Change the
> if statement of mode->clock to fit that and add a comment.
>
> Changes since v2:
> - Remove the change about preparation for MT2701 support.
>
> Changes since v1:
> - According to the suggestion from philipp, We use the new
> dpi0_sel rate set method.
> - calls clk_set_rate to set the dpi0_sel according to the
> pixel clock.
> - Remove the direct access to all the intermediate clock part.
> - Remove the intermediate tvdpll_d* clocks in dts.
> - According to suggestion from CK, we rename the clock parse
> function and remove it from mtk_dpi_conf struct.
> - Merges the hdmi Pll set rate for pixel clock greater than
> 165MHz and smaller parts.
>
> The PATCH depends on the following patch:
> https://patchwork.kernel.org/patch/9262575/
> (arm64: dts: mt8173: add mmsel clocks for 4K support)
>
> Junzhi Zhao (3):
> drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable
> drm/mediatek: enhance the HDMI driving current
> drm/mediatek: modify the factor to make the pll_rate set in the 1G-2G
> range
>
> drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++--
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 17 ++++++----
> drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 42 +++++++++++++++++-------
> 3 files changed, 48 insertions(+), 20 deletions(-)
>
^ permalink raw reply
* [PATCH] ARM: dts: vf610: fix IRQ flag of global timer
From: Stefan Agner @ 2016-10-18 1:51 UTC (permalink / raw)
To: linux-arm-kernel
The global timer IRQ (PPI[0], PPI 11 in device tree terms) is a
rising edge interrupt. The ARM Cortex-A5 MPCore TRM in Chapter
10.1.2. Interrupt types and sources says:
"Interrupt is rising-edge sensitive."
The bits seem to be read-only, hence this missconfiguration had
no negative effect. However, with commit 992345a58e0c
("irqchip/gic: WARN if setting the interrupt type for a PPI fails")
warnings such as this get printed:
GIC: PPI11 is secure or misconfigured
With this change the new configuration matches the default
configuration and no warning is printed anymore.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/vf500.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index a3824e6..d7fdb2a 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -70,7 +70,7 @@
global_timer: timer at 40002200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x40002200 0x20>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
clocks = <&clks VF610_CLK_PLATFORM_BUS>;
};
--
2.10.0
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