* [PATCH v20 03/10] add bindings document for altera freeze bridge
From: atull @ 2016-10-18 18:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018162656.dsx7hnip3xqm7j26@rob-hp-laptop>
On Tue, 18 Oct 2016, Rob Herring wrote:
> On Mon, Oct 17, 2016 at 11:09:34AM -0500, Alan Tull wrote:
> > Add bindings document for the Altera Freeze Bridge. A Freeze
> > Bridge is used to gate traffic to/from a region of a FPGA
> > such that that region can be reprogrammed. The Freeze Bridge
> > exist in FPGA fabric that is not currently being reconfigured.
> >
> > Signed-off-by: Alan Tull <atull@opensource.altera.com>
> > Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
> > ---
> > v19: Added in v19 of patchset, uses fpga image info struct
> > v20: fix one underscore to hyphen
> > ---
> > .../bindings/fpga/altera-freeze-bridge.txt | 23 ++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
>
> Acked-by: Rob Herring <robh@kernel.org>
>
Thanks!
Alan
^ permalink raw reply
* [PATCH v20 02/10] doc: fpga-mgr: add fpga image info to api
From: atull @ 2016-10-18 18:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAAtXAHcpwmW_7f2F9vk49hAHpOTs4rk9fFvLzn5zNdPZCy_O7A@mail.gmail.com>
On Mon, 17 Oct 2016, Moritz Fischer wrote:
> Hi Alan,
>
> couple of nits inline and some comments on ordering the patches ;-)
>
> On Mon, Oct 17, 2016 at 6:09 PM, Alan Tull <atull@opensource.altera.com> wrote:
> > This patch adds a minor change in the FPGA Mangager API
>
> s/Mangager/Manager/
Yup!
>
> > to hold information that is specific to an FPGA image
> > file. This change is expected to bring little, if any,
> > pain.
> >
> > An FPGA image file will have particulars that affect how the
> > image is programmed to the FPGA. One example is that
> > current 'flags' currently has one bit which shows whether the
> > FPGA image was built for full reconfiguration or partial
> > reconfiguration. Another example is timeout values for
> > enabling or disabling the bridges in the FPGA. As the
> > complexity of the FPGA design increases, the bridges in the
> > FPGA may take longer times to enable or disable.
>
> According for the current ordering bridges are not yet defined if we
> merge patches in this order?
> Not terrible imho, but I thought I'd point it out. Would swapping the
> order make sense?
Probably, yes.
>
> I also think [5/10] should be squashed together with this commit to
> make it an atomic change.
So far my bindings and code have gone in separately.
Bindings through Rob and code through Greg KH or Dinh.
>
> Apart from my comments above feel free to add my Acked-by
>
> Thanks for keeping this going,
>
> Moritz
>
Thanks for all the code reviews!
Alan
^ permalink raw reply
* [PATCH 20/28] net: bcm63xx: avoid referencing uninitialized variable
From: David Miller @ 2016-10-18 18:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161017221650.1902729-1-arnd@arndb.de>
From: Arnd Bergmann <arnd@arndb.de>
Date: Tue, 18 Oct 2016 00:16:08 +0200
> gcc found a reference to an uninitialized variable in the error handling
> of bcm_enet_open, introduced by a recent cleanup:
>
> drivers/net/ethernet/broadcom/bcm63xx_enet.c: In function 'bcm_enet_open'
> drivers/net/ethernet/broadcom/bcm63xx_enet.c:1129:2: warning: 'phydev' may be used uninitialized in this function [-Wmaybe-uninitialized]
>
> This makes the use of that variable conditional, so we only reference it
> here after it has been used before. Unlike my normal patches, I have not
> build-tested this one, as I don't currently have mips test in my
> randconfig setup.
>
> Fixes: 625eb8667d6f ("net: ethernet: broadcom: bcm63xx: use phydev from struct net_device")
> Cc: Philippe Reynes <tremyfr@gmail.com>
> Reported-by: kbuild test robot <fengguang.wu@intel.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Applied.
^ permalink raw reply
* [BUG] LPC32xx gpio driver broken by commit 762c2e46 in 4.9-rc1
From: Sylvain Lemieux @ 2016-10-18 18:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6e71451a-9392-92cf-c7f5-a5bcbf9d4dd1@mleia.com>
Hi Vladimir,
On Tue, 2016-10-18 at 21:06 +0300, Vladimir Zapolskiy wrote:
> Hi Sylvain,
>
> On 18.10.2016 19:23, Sylvain Lemieux wrote:
> > Vladimir, Linus, Alexandre,
> >
> > the current LPC32xx GPIO driver is broken by commit 762c2e46
> > (gpio: of: remove of_gpiochip_and_xlate() and struct gg_data).
>
> I do confirm, as well I've noticed that the driver is broken on v4.9,
> however I didn't find time to bisect the problematic commit, thank
> you to pinning it out.
>
> > A call to "of_get_named_gpio" to retrieve the GPIO will
> > always return -EINVAL, except for the first GPIO bank.
> >
> > Prior to this commit, the driver was working properly
> > because of the side-effect of the match function called by
> > "gpiochip_find" inside "of_get_named_gpiod_flags" function.
> >
> > I think, the proper long-term solution is to replace the
> > LPC32xx GPIO driver; an initial version was previously
> > submitted, by Vladimir Zapolskiy, to the mailing list:
> > http://www.spinics.net/lists/linux-gpio/msg09746.html
>
> I still cherish a hope for submitting v2 for v4.10, the difference
> from v1 is expected to be relatively big (e.g. there will be 5
> banks instead of 6, on hardware level banks P0 and P1 are on the
> single controller, there will be other lesser differences also).
>
I will be available to test the new driver, once submitted
on the mailing list.
> > Is there any short-term solution that can be done with
> > the existing driver to keep the LPC32xx platform working
> > properly in the 4.9 mainline kernel?
>
> Unfortunately I didn't spend enough time to fix the problem,
> but in two words the root cause is that from the OF description
> there is only one on-SoC GPIO controller, but the GPIO controller
> driver registers multiple gpiochips (6 in this particular case),
> consumers specify a bank as a value in the first cell.
> The referenced commit simplifies the matter by assuming that
> a number of gpiochips for consumers is the same as the number
> of registered GPIO controllers from OF description.
>
> I don't think that the problem is specific only to the legacy
> LPC32xx GPIO controller driver, but at the moment I don't have
> any more examples to share. Probably another 3-cell GPIO
> controller driver gpio-etraxfs.c is also broken, a good enough
> implicit indicator for potentially broken drivers might be if
> you see gpiochip_add_data() call inside a loop:
> * gpio-sch311x.c
> * gpio-ml-ioh.c
> * gpio-etraxfs.c
> * gpio-htc-egpio.c
> * gpio-davinci.c
> * gpio-lpc32xx.c
>
As a temporary solution, locally I reverted the following
commits to be able to have a working platform on 4.9-rc1:
* "gpio: of: factor out common code to a new helper function"
(99468c1af913bb5662c223b68e783b4bf9200184)
* "gpio: of: remove of_gpiochip_and_xlate() and struct gg_data"
(762c2e46c0591d207289105c8718e4adf29b2b34)
Regards,
Sylvain
^ permalink raw reply
* [PATCH v3 0/4] support smc91x on mainstone and devicetree
From: David Miller @ 2016-10-18 18:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476733532-29716-1-git-send-email-robert.jarzmik@free.fr>
From: Robert Jarzmik <robert.jarzmik@free.fr>
Date: Mon, 17 Oct 2016 21:45:28 +0200
> This serie aims at bringing support to mainstone board on a device-tree based
> build, as what is already in place for legacy mainstone.
>
> The bulk of the mainstone "specific" behavior is that a u16 write doesn't work
> on a address of the form 4*n + 2, while it works on 4*n.
>
> The legacy workaround was in SMC_outw(), with calls to
> machine_is_mainstone(). These calls don't work with a pxa27x-dt machine type,
> which is used when a generic device-tree pxa27x machine is used to boot the
> mainstone board.
>
> Therefore, this serie enables the smc91c111 adapter of the mainstone board to
> work on a device-tree build, exaclty as it's been working for years with the
> legacy arch/arm/mach-pxa/mainstone.c definition.
>
> As a sum up, this extends an existing mechanism to device-tree based pxa platforms.
Series applied, thanks.
^ permalink raw reply
* [BUG] LPC32xx gpio driver broken by commit 762c2e46 in 4.9-rc1
From: Vladimir Zapolskiy @ 2016-10-18 18:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476807799.10214.25.camel@localhost>
Hi Sylvain,
On 18.10.2016 19:23, Sylvain Lemieux wrote:
> Vladimir, Linus, Alexandre,
>
> the current LPC32xx GPIO driver is broken by commit 762c2e46
> (gpio: of: remove of_gpiochip_and_xlate() and struct gg_data).
I do confirm, as well I've noticed that the driver is broken on v4.9,
however I didn't find time to bisect the problematic commit, thank
you to pinning it out.
> A call to "of_get_named_gpio" to retrieve the GPIO will
> always return -EINVAL, except for the first GPIO bank.
>
> Prior to this commit, the driver was working properly
> because of the side-effect of the match function called by
> "gpiochip_find" inside "of_get_named_gpiod_flags" function.
>
> I think, the proper long-term solution is to replace the
> LPC32xx GPIO driver; an initial version was previously
> submitted, by Vladimir Zapolskiy, to the mailing list:
> http://www.spinics.net/lists/linux-gpio/msg09746.html
I still cherish a hope for submitting v2 for v4.10, the difference
from v1 is expected to be relatively big (e.g. there will be 5
banks instead of 6, on hardware level banks P0 and P1 are on the
single controller, there will be other lesser differences also).
> Is there any short-term solution that can be done with
> the existing driver to keep the LPC32xx platform working
> properly in the 4.9 mainline kernel?
Unfortunately I didn't spend enough time to fix the problem,
but in two words the root cause is that from the OF description
there is only one on-SoC GPIO controller, but the GPIO controller
driver registers multiple gpiochips (6 in this particular case),
consumers specify a bank as a value in the first cell.
The referenced commit simplifies the matter by assuming that
a number of gpiochips for consumers is the same as the number
of registered GPIO controllers from OF description.
I don't think that the problem is specific only to the legacy
LPC32xx GPIO controller driver, but at the moment I don't have
any more examples to share. Probably another 3-cell GPIO
controller driver gpio-etraxfs.c is also broken, a good enough
implicit indicator for potentially broken drivers might be if
you see gpiochip_add_data() call inside a loop:
* gpio-sch311x.c
* gpio-ml-ioh.c
* gpio-etraxfs.c
* gpio-htc-egpio.c
* gpio-davinci.c
* gpio-lpc32xx.c
--
With best wishes,
Vladimir
^ permalink raw reply
* [PATCH v9 2/2] ARM: dts: add TOPEET itop elite based board
From: Krzysztof Kozlowski @ 2016-10-18 17:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018174732.GC30003@kozik-lap>
On Tue, Oct 18, 2016 at 8:47 PM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Tue, Oct 18, 2016 at 08:37:48PM +0300, Krzysztof Kozlowski wrote:
>> On Wed, Oct 19, 2016 at 01:18:49AM +0800, Randy Li wrote:
>> > The TOPEET itop exynos 4412 have three versions base board. The
>> > Elite version is the cheap one without too much peripheral devices
>> > on it.
>> >
>> > Currently supported are serial console, wired networking(USB),
>> > USB OTG in peripheral mode, USB host, SD storage, GPIO buttons,
>> > PWM beeper, ADC and LEDs. The WM8960 analog audio codec is also
>> > enabled.
>> >
>> > The FIMC is not used for camera currently, I enabled it just for a
>> > colorspace converter.
>> >
>> > Signed-off-by: Randy Li <ayaka@soulik.info>
>> > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
>>
>> Thanks, applied, with missing Rob's ack, minor changes in commit msg and
>> fix in pin function (you used macro for pull up/down instead of
>> function).
>
> I also changed your name in commit message from "ayaka" to "Randy Li".
> The author of a patch (equal to "From:" in email) should match the
> Signed-off-by. For the future, please fix your gitconfig and/or mail
> transfer program.
Ahhh, it is not your fault but patchwork's. Damn it. Patchwork stores
the first username he encounters and uses it further even if From is
different.
I will send an email to kernel.org Patchwork admin about this.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 0/5] drm/sun4i: Handle TV overscan
From: Jean-Francois Moine @ 2016-10-18 17:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018100349.qm2f554oiwyjwrsi@lukather>
On Tue, 18 Oct 2016 12:03:49 +0200
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> The fourth one being the major one. Every time I raised the issue on
> IRC, the answer basically was "we don't care about analog", so I'm a
> bit pessimistic about whether dealing with this in the core would be
> accepted, hence why I chose to deal with this at the driver level.
The same problem exists with HDMI and old TVs (mine is an ASUS 22T1E):
these TVs overscan as soon as AVI frames are in the stream.
--
Ken ar c'henta? | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
^ permalink raw reply
* [PATCH v9 2/2] ARM: dts: add TOPEET itop elite based board
From: Krzysztof Kozlowski @ 2016-10-18 17:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018173748.GB30003@kozik-lap>
On Tue, Oct 18, 2016 at 08:37:48PM +0300, Krzysztof Kozlowski wrote:
> On Wed, Oct 19, 2016 at 01:18:49AM +0800, Randy Li wrote:
> > The TOPEET itop exynos 4412 have three versions base board. The
> > Elite version is the cheap one without too much peripheral devices
> > on it.
> >
> > Currently supported are serial console, wired networking(USB),
> > USB OTG in peripheral mode, USB host, SD storage, GPIO buttons,
> > PWM beeper, ADC and LEDs. The WM8960 analog audio codec is also
> > enabled.
> >
> > The FIMC is not used for camera currently, I enabled it just for a
> > colorspace converter.
> >
> > Signed-off-by: Randy Li <ayaka@soulik.info>
> > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> Thanks, applied, with missing Rob's ack, minor changes in commit msg and
> fix in pin function (you used macro for pull up/down instead of
> function).
I also changed your name in commit message from "ayaka" to "Randy Li".
The author of a patch (equal to "From:" in email) should match the
Signed-off-by. For the future, please fix your gitconfig and/or mail
transfer program.
Sample gitconfig regarding this:
[user]
name = Mr Foo Bar
email = foobar at gmail.com
[sendemail]
smtpencryption = tls
smtpserver = smtp.gmail.com
smtpuser = foobar at gmail.com
smtpserverport = 587
confirm = auto
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v2 1/2] remoteproc: core: Add rproc OF look-up functions
From: Bjorn Andersson @ 2016-10-18 17:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160816143824.4120-1-lee.jones@linaro.org>
On Tue 16 Aug 07:38 PDT 2016, Lee Jones wrote:
> - of_rproc_by_index(): look-up and obtain a reference to a rproc
> using the DT phandle "rprocs" and a index.
>
> - of_rproc_by_name(): lookup and obtain a reference to a rproc
> using the DT phandle "rprocs" and "rproc-names".
>
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
For the record; I have not picked these patches because I have not yet
seen an acceptable proposal for a client - there are concerns about DT
bindings of such client and questions on how to notify the client about
life cycle changes in the remoteproc (i.e. crash recovery events).
I think the patches looks good, so once these open questions gets
answered (or some new use case appear) I will pick these up again.
Regards,
Bjorn
> ---
>
> v1 => v2:
> - s/ti,rprocs/ti,rproc
>
> drivers/remoteproc/remoteproc_core.c | 78 +++++++++++++++++++++++++++++++++++-
> include/linux/remoteproc.h | 25 +++++++++++-
> 2 files changed, 101 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
> index fe0539e..fe362fb 100644
> --- a/drivers/remoteproc/remoteproc_core.c
> +++ b/drivers/remoteproc/remoteproc_core.c
> @@ -41,6 +41,8 @@
> #include <linux/virtio_ids.h>
> #include <linux/virtio_ring.h>
> #include <asm/byteorder.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
>
> #include "remoteproc_internal.h"
>
> @@ -1191,6 +1193,81 @@ out:
> }
> EXPORT_SYMBOL(rproc_shutdown);
>
> +#ifdef CONFIG_OF
> +/**
> + * of_get_rproc_by_index() - lookup and obtain a reference to an rproc
> + * @np: node to search for rproc phandle
> + * @index: index into the phandle list
> + *
> + * This function increments the remote processor's refcount, so always
> + * use rproc_put() to decrement it back once rproc isn't needed anymore.
> + *
> + * Returns a pointer to the rproc struct on success or an appropriate error
> + * code otherwise.
> + */
> +struct rproc *of_get_rproc_by_index(struct device_node *np, int index)
> +{
> + struct rproc *rproc = NULL, *r;
> + struct device_node *rproc_np;
> +
> + if (index < 0) {
> + pr_err("Invalid index: %d\n", index);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + rproc_np = of_parse_phandle(np, "rprocs", index);
> + if (!rproc_np) {
> + /* Unfortunately we have to support this, at least for now */
> + rproc_np = of_parse_phandle(np, "ti,rproc", index);
> + if (!rproc_np) {
> + pr_err("Failed to obtain phandle\n");
> + return ERR_PTR(-ENODEV);
> + }
> + }
> +
> + mutex_lock(&rproc_list_mutex);
> + list_for_each_entry(r, &rproc_list, node) {
> + if (r->dev.parent && r->dev.parent->of_node == rproc_np) {
> + get_device(&r->dev);
> + rproc = r;
> + break;
> + }
> + }
> + mutex_unlock(&rproc_list_mutex);
> +
> + of_node_put(rproc_np);
> +
> + if (!rproc)
> + pr_err("Could not find rproc, deferring\n");
> +
> + return rproc ?: ERR_PTR(-EPROBE_DEFER);
> +}
> +EXPORT_SYMBOL(of_get_rproc_by_index);
> +
> +/**
> + * of_get_rproc_by_name() - lookup and obtain a reference to an rproc
> + * @np: node to search for rproc
> + * @name: name of the remoteproc from device's point of view
> + *
> + * This function increments the remote processor's refcount, so always
> + * use rproc_put() to decrement it back once rproc isn't needed anymore.
> + *
> + * Returns a pointer to the rproc struct on success or an appropriate error
> + * code otherwise.
> + */
> +struct rproc *of_get_rproc_by_name(struct device_node *np, const char *name)
> +{
> + int index;
> +
> + if (unlikely(!name))
> + return ERR_PTR(-EINVAL);
> +
> + index = of_property_match_string(np, "rproc-names", name);
> +
> + return of_get_rproc_by_index(np, index);
> +}
> +EXPORT_SYMBOL(of_get_rproc_by_name);
> +
> /**
> * rproc_get_by_phandle() - find a remote processor by phandle
> * @phandle: phandle to the rproc
> @@ -1203,7 +1280,6 @@ EXPORT_SYMBOL(rproc_shutdown);
> *
> * Returns the rproc handle on success, and NULL on failure.
> */
> -#ifdef CONFIG_OF
> struct rproc *rproc_get_by_phandle(phandle phandle)
> {
> struct rproc *rproc = NULL, *r;
> diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
> index 1c457a8..f130938 100644
> --- a/include/linux/remoteproc.h
> +++ b/include/linux/remoteproc.h
> @@ -487,7 +487,6 @@ struct rproc_vdev {
> u32 rsc_offset;
> };
>
> -struct rproc *rproc_get_by_phandle(phandle phandle);
> struct rproc *rproc_alloc(struct device *dev, const char *name,
> const struct rproc_ops *ops,
> const char *firmware, int len);
> @@ -511,4 +510,28 @@ static inline struct rproc *vdev_to_rproc(struct virtio_device *vdev)
> return rvdev->rproc;
> }
>
> +#ifdef CONFIG_OF
> +extern struct rproc *of_get_rproc_by_index(struct device_node *np,
> + int index);
> +extern struct rproc *of_get_rproc_by_name(struct device_node *np,
> + const char *name);
> +extern struct rproc *rproc_get_by_phandle(phandle phandle);
> +#else
> +static inline
> +struct rproc *of_get_rproc_by_index(struct device_node *np, int index)
> +{
> + return NULL;
> +}
> +static inline
> +struct rproc *of_get_rproc_by_name(struct device_node *np, const char *name)
> +{
> + return NULL;
> +}
> +static inline
> +struct rproc *rproc_get_by_phandle(phandle phandle)
> +{
> + return NULL;
> +}
> +#endif /* CONFIG_OF */
> +
> #endif /* REMOTEPROC_H */
> --
> 2.9.0
>
^ permalink raw reply
* [PATCH V5 2/2] irqchip: qcom: Add IRQ combiner driver
From: Agustin Vega-Frias @ 2016-10-18 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476812509-2760-1-git-send-email-agustinv@codeaurora.org>
Driver for interrupt combiners in the Top-level Control and Status
Registers (TCSR) hardware block in Qualcomm Technologies chips.
An interrupt combiner in this block combines a set of interrupts by
OR'ing the individual interrupt signals into a summary interrupt
signal routed to a parent interrupt controller, and provides read-
only, 32-bit registers to query the status of individual interrupts.
The status bit for IRQ n is bit (n % 32) within register (n / 32)
of the given combiner. Thus, each combiner can be described as a set
of register offsets and the number of IRQs managed.
Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
---
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/qcom-irq-combiner.c | 332 ++++++++++++++++++++++++++++++++++++
3 files changed, 341 insertions(+)
create mode 100644 drivers/irqchip/qcom-irq-combiner.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 82b0b5d..8e0cbbb 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -279,3 +279,11 @@ config EZNPS_GIC
config STM32_EXTI
bool
select IRQ_DOMAIN
+
+config QCOM_IRQ_COMBINER
+ bool "QCOM IRQ combiner support"
+ depends on ARCH_QCOM && ACPI
+ select IRQ_DOMAIN
+ help
+ Say yes here to add support for the IRQ combiner devices embedded
+ in Qualcomm Technologies chips.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e4dbfc8..1818a0b 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -74,3 +74,4 @@ obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
+obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
diff --git a/drivers/irqchip/qcom-irq-combiner.c b/drivers/irqchip/qcom-irq-combiner.c
new file mode 100644
index 0000000..b117cd7
--- /dev/null
+++ b/drivers/irqchip/qcom-irq-combiner.c
@@ -0,0 +1,332 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Driver for interrupt combiners in the Top-level Control and Status
+ * Registers (TCSR) hardware block in Qualcomm Technologies chips.
+ * An interrupt combiner in this block combines a set of interrupts by
+ * OR'ing the individual interrupt signals into a summary interrupt
+ * signal routed to a parent interrupt controller, and provides read-
+ * only, 32-bit registers to query the status of individual interrupts.
+ * The status bit for IRQ n is bit (n % 32) within register (n / 32)
+ * of the given combiner. Thus, each combiner can be described as a set
+ * of register offsets and the number of IRQs managed.
+ */
+
+#include <linux/acpi.h>
+#include <linux/err.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+
+#define REG_SIZE 32
+
+struct combiner_reg {
+ void __iomem *addr;
+ unsigned long mask;
+};
+
+struct combiner {
+ struct irq_chip irq_chip;
+ struct irq_domain *domain;
+ int parent_irq;
+ u32 nirqs;
+ u32 nregs;
+ struct combiner_reg regs[0];
+};
+
+static inline u32 irq_register(int irq)
+{
+ return irq / REG_SIZE;
+}
+
+static inline u32 irq_bit(int irq)
+{
+ return irq % REG_SIZE;
+
+}
+
+static inline int irq_nr(u32 reg, u32 bit)
+{
+ return reg * REG_SIZE + bit;
+}
+
+/*
+ * Handler for the cascaded IRQ.
+ */
+static void combiner_handle_irq(struct irq_desc *desc)
+{
+ struct combiner *combiner = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ u32 reg;
+
+ chained_irq_enter(chip, desc);
+
+ for (reg = 0; reg < combiner->nregs; reg++) {
+ int virq;
+ int hwirq;
+ u32 bit;
+ u32 status;
+
+ if (combiner->regs[reg].mask == 0)
+ continue;
+
+ status = readl_relaxed(combiner->regs[reg].addr);
+ status &= combiner->regs[reg].mask;
+
+ while (status) {
+ bit = __ffs(status);
+ status &= ~(1 << bit);
+ hwirq = irq_nr(reg, bit);
+ virq = irq_find_mapping(combiner->domain, hwirq);
+ if (virq >= 0)
+ generic_handle_irq(virq);
+
+ }
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+/*
+ * irqchip callbacks
+ */
+
+static void combiner_irq_chip_mask_irq(struct irq_data *data)
+{
+ struct combiner *combiner = irq_data_get_irq_chip_data(data);
+ struct combiner_reg *reg = combiner->regs + irq_register(data->hwirq);
+
+ clear_bit(irq_bit(data->hwirq), ®->mask);
+}
+
+static void combiner_irq_chip_unmask_irq(struct irq_data *data)
+{
+ struct combiner *combiner = irq_data_get_irq_chip_data(data);
+ struct combiner_reg *reg = combiner->regs + irq_register(data->hwirq);
+
+ set_bit(irq_bit(data->hwirq), ®->mask);
+}
+
+/*
+ * irq_domain_ops callbacks
+ */
+
+static int combiner_irq_map(struct irq_domain *domain, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ struct combiner *combiner = domain->host_data;
+
+ if (hwirq >= combiner->nirqs)
+ return -EINVAL;
+
+ irq_set_chip_and_handler(irq, &combiner->irq_chip, handle_level_irq);
+ irq_set_chip_data(irq, combiner);
+ irq_set_parent(irq, combiner->parent_irq);
+ irq_set_noprobe(irq);
+ return 0;
+}
+
+static void combiner_irq_unmap(struct irq_domain *domain, unsigned int irq)
+{
+ irq_set_chip_and_handler(irq, NULL, NULL);
+ irq_set_chip_data(irq, NULL);
+ irq_set_parent(irq, -1);
+}
+
+#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
+static int combiner_irq_translate(struct irq_domain *d, struct irq_fwspec *fws,
+ unsigned long *hwirq, unsigned int *type)
+{
+ if (is_acpi_node(fws->fwnode)) {
+ if (fws->param_count != 2)
+ return -EINVAL;
+
+ *hwirq = fws->param[0];
+ *type = fws->param[1];
+ return 0;
+ }
+
+ return -EINVAL;
+}
+#endif
+
+static const struct irq_domain_ops domain_ops = {
+ .map = combiner_irq_map,
+ .unmap = combiner_irq_unmap,
+#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
+ .translate = combiner_irq_translate
+#endif
+};
+
+/*
+ * Device probing
+ */
+
+static acpi_status count_registers_cb(struct acpi_resource *ares, void *context)
+{
+ int *count = context;
+
+ if (ares->type == ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
+ ++(*count);
+ return AE_OK;
+}
+
+static int count_registers(struct acpi_device *adev)
+{
+ acpi_status status;
+ int count = 0;
+
+ if (!acpi_has_method(adev->handle, METHOD_NAME__CRS))
+ return -EINVAL;
+
+ status = acpi_walk_resources(adev->handle, METHOD_NAME__CRS,
+ count_registers_cb, &count);
+ if (ACPI_FAILURE(status))
+ return -EINVAL;
+ return count;
+}
+
+struct get_registers_context {
+ struct device *dev;
+ struct combiner *combiner;
+ int err;
+};
+
+static acpi_status get_registers_cb(struct acpi_resource *ares, void *context)
+{
+ struct get_registers_context *ctx = context;
+ struct acpi_resource_generic_register *reg;
+ phys_addr_t paddr;
+ void __iomem *vaddr;
+
+ if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
+ return AE_OK;
+
+ reg = &ares->data.generic_reg;
+ paddr = reg->address;
+ if ((reg->space_id != ACPI_SPACE_MEM) ||
+ (reg->bit_offset != 0) ||
+ (reg->bit_width > REG_SIZE)) {
+ dev_err(ctx->dev, "Bad register resource @%pa\n", &paddr);
+ ctx->err = -EINVAL;
+ return AE_ERROR;
+ }
+
+ vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
+ if (IS_ERR(vaddr)) {
+ dev_err(ctx->dev, "Can't map register @%pa\n", &paddr);
+ ctx->err = PTR_ERR(vaddr);
+ return AE_ERROR;
+ }
+
+ ctx->combiner->regs[ctx->combiner->nregs].addr = vaddr;
+ ctx->combiner->nirqs += reg->bit_width;
+ ctx->combiner->nregs++;
+ return AE_OK;
+}
+
+static int get_registers(struct acpi_device *adev, struct combiner *comb)
+{
+ acpi_status status;
+ struct get_registers_context ctx;
+
+ if (!acpi_has_method(adev->handle, METHOD_NAME__CRS))
+ return -EINVAL;
+
+ ctx.dev = &adev->dev;
+ ctx.combiner = comb;
+ ctx.err = 0;
+
+ status = acpi_walk_resources(adev->handle, METHOD_NAME__CRS,
+ get_registers_cb, &ctx);
+ if (ACPI_FAILURE(status))
+ return ctx.err;
+ return 0;
+}
+
+static acpi_status get_parent_irq_cb(struct acpi_resource *ares, void *context)
+{
+ int *irq = context;
+ struct acpi_resource_extended_irq *eirq;
+
+ if (ares->type != ACPI_RESOURCE_TYPE_EXTENDED_IRQ)
+ return AE_OK;
+
+ eirq = &ares->data.extended_irq;
+ *irq = acpi_irq_domain_register_irq(&eirq->resource_source,
+ eirq->interrupts[0],
+ eirq->triggering, eirq->polarity);
+ return AE_OK;
+}
+
+static int get_parent_irq(struct acpi_device *adev)
+{
+ acpi_status status;
+ int irq = -1;
+
+ if (!acpi_has_method(adev->handle, METHOD_NAME__CRS))
+ return -EINVAL;
+
+ status = acpi_walk_resources(adev->handle, METHOD_NAME__CRS,
+ get_parent_irq_cb, &irq);
+ if (ACPI_FAILURE(status))
+ return -EINVAL;
+ return irq;
+}
+
+static int __init combiner_probe(struct acpi_device *adev)
+{
+ struct combiner *combiner;
+ size_t alloc_sz;
+ u32 nregs;
+ int err;
+
+ nregs = count_registers(adev);
+ if (nregs <= 0) {
+ dev_err(&adev->dev, "Error reading register resources\n");
+ return -EINVAL;
+ }
+
+ alloc_sz = sizeof(*combiner) + sizeof(struct combiner_reg) * nregs;
+ combiner = devm_kzalloc(&adev->dev, alloc_sz, GFP_KERNEL);
+ if (!combiner)
+ return -ENOMEM;
+
+ err = get_registers(adev, combiner);
+ if (err < 0)
+ return err;
+
+ combiner->parent_irq = get_parent_irq(adev);
+ if (combiner->parent_irq <= 0) {
+ dev_err(&adev->dev, "Error getting IRQ resource\n");
+ return -EINVAL;
+ }
+
+ combiner->domain = irq_domain_create_linear(
+ &adev->fwnode, combiner->nirqs, &domain_ops, combiner);
+ if (!combiner->domain)
+ /* Errors printed by irq_domain_create_linear */
+ return -ENODEV;
+
+ irq_set_chained_handler_and_data(combiner->parent_irq,
+ combiner_handle_irq, combiner);
+ combiner->irq_chip.irq_mask = combiner_irq_chip_mask_irq;
+ combiner->irq_chip.irq_unmask = combiner_irq_chip_unmask_irq;
+ combiner->irq_chip.name = dev_name(&adev->dev);
+
+ dev_info(&adev->dev, "Initialized with [p=%d,n=%d,r=%p]\n",
+ combiner->parent_irq, combiner->nirqs, combiner->regs[0].addr);
+ return 0;
+}
+
+IRQCHIP_ACPI_DECLARE(qcom_combiner, "QCOM80B1", combiner_probe);
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* [PATCH V5 1/2] ACPI: Add support for ResourceSource/IRQ domain mapping
From: Agustin Vega-Frias @ 2016-10-18 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476812509-2760-1-git-send-email-agustinv@codeaurora.org>
This allows irqchip drivers to associate an ACPI DSDT device to
an IRQ domain and provides support for using the ResourceSource
in Extended IRQ Resources to find the domain and map the IRQs
specified on that domain.
Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
---
drivers/acpi/Makefile | 1 +
drivers/acpi/irqdomain.c | 141 ++++++++++++++++++++++++++++++++++++++
drivers/acpi/resource.c | 21 +++---
include/asm-generic/vmlinux.lds.h | 1 +
include/linux/acpi.h | 71 +++++++++++++++++++
include/linux/irqchip.h | 17 ++++-
6 files changed, 240 insertions(+), 12 deletions(-)
create mode 100644 drivers/acpi/irqdomain.c
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index 9ed0878..880401b 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -57,6 +57,7 @@ acpi-$(CONFIG_ACPI_PROCFS_POWER) += cm_sbs.o
acpi-y += acpi_lpat.o
acpi-$(CONFIG_ACPI_GENERIC_GSI) += gsi.o
acpi-$(CONFIG_ACPI_WATCHDOG) += acpi_watchdog.o
+acpi-$(CONFIG_IRQ_DOMAIN) += irqdomain.o
# These are (potentially) separate modules
diff --git a/drivers/acpi/irqdomain.c b/drivers/acpi/irqdomain.c
new file mode 100644
index 0000000..c53b9f4
--- /dev/null
+++ b/drivers/acpi/irqdomain.c
@@ -0,0 +1,141 @@
+/*
+ * ACPI ResourceSource/IRQ domain mapping support
+ *
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/acpi.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+
+/**
+ * acpi_irq_domain_ensure_probed() - Check if the device has registered
+ * an IRQ domain and probe as necessary
+ *
+ * @device: Device to check and probe
+ *
+ * Returns: 0 on success, -ENODEV otherwise
+ */
+static int acpi_irq_domain_ensure_probed(struct acpi_device *device)
+{
+ struct acpi_dsdt_probe_entry *entry;
+
+ if (irq_find_matching_fwnode(&device->fwnode, DOMAIN_BUS_ANY) != 0)
+ return 0;
+
+ for (entry = &__dsdt_acpi_probe_table;
+ entry < &__dsdt_acpi_probe_table_end; entry++)
+ if (strcmp(entry->_hid, acpi_device_hid(device)) == 0)
+ return entry->probe(device);
+
+ return -ENODEV;
+}
+
+/**
+ * acpi_irq_domain_register_irq() - Register the mapping for an IRQ produced
+ * by the given acpi_resource_source to a
+ * Linux IRQ number
+ * @source: IRQ source
+ * @hwirq: Hardware IRQ number
+ * @trigger: trigger type of the IRQ number to be mapped
+ * @polarity: polarity of the IRQ to be mapped
+ *
+ * Returns: a valid linux IRQ number on success
+ * -ENODEV if the given acpi_resource_source cannot be found
+ * -EPROBE_DEFER if the IRQ domain has not been registered
+ * -EINVAL for all other errors
+ */
+int acpi_irq_domain_register_irq(const struct acpi_resource_source *source,
+ u32 hwirq, int trigger, int polarity)
+{
+ struct irq_fwspec fwspec;
+ struct acpi_device *device;
+ acpi_handle handle;
+ acpi_status status;
+ int ret;
+
+ /* An empty acpi_resource_source means it is a GSI */
+ if (!source->string_length)
+ return acpi_register_gsi(NULL, hwirq, trigger, polarity);
+
+ status = acpi_get_handle(NULL, source->string_ptr, &handle);
+ if (ACPI_FAILURE(status))
+ return -ENODEV;
+
+ device = acpi_bus_get_acpi_device(handle);
+ if (!device)
+ return -ENODEV;
+
+ ret = acpi_irq_domain_ensure_probed(device);
+ if (ret)
+ goto out_put_device;
+
+ fwspec.fwnode = &device->fwnode;
+ fwspec.param[0] = hwirq;
+ fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
+ fwspec.param_count = 2;
+
+ ret = irq_create_fwspec_mapping(&fwspec);
+
+out_put_device:
+ acpi_bus_put_acpi_device(device);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(acpi_irq_domain_register_irq);
+
+/**
+ * acpi_irq_domain_unregister_irq() - Delete the mapping for an IRQ produced
+ * by the given acpi_resource_source to a
+ * Linux IRQ number
+ * @source: IRQ source
+ * @hwirq: Hardware IRQ number
+ *
+ * Returns: 0 on success
+ * -ENODEV if the given acpi_resource_source cannot be found
+ * -EINVAL for all other errors
+ */
+int acpi_irq_domain_unregister_irq(const struct acpi_resource_source *source,
+ u32 hwirq)
+{
+ struct irq_domain *domain;
+ struct acpi_device *device;
+ acpi_handle handle;
+ acpi_status status;
+ int ret = 0;
+
+ if (!source->string_length) {
+ acpi_unregister_gsi(hwirq);
+ return 0;
+ }
+
+ status = acpi_get_handle(NULL, source->string_ptr, &handle);
+ if (ACPI_FAILURE(status))
+ return -ENODEV;
+
+ device = acpi_bus_get_acpi_device(handle);
+ if (!device)
+ return -ENODEV;
+
+ domain = irq_find_matching_fwnode(&device->fwnode, DOMAIN_BUS_ANY);
+ if (!domain) {
+ ret = -EINVAL;
+ goto out_put_device;
+ }
+
+ irq_dispose_mapping(irq_find_mapping(domain, hwirq));
+
+out_put_device:
+ acpi_bus_put_acpi_device(device);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(acpi_irq_domain_unregister_irq);
diff --git a/drivers/acpi/resource.c b/drivers/acpi/resource.c
index 56241eb..3fb7abf 100644
--- a/drivers/acpi/resource.c
+++ b/drivers/acpi/resource.c
@@ -381,14 +381,15 @@ static void acpi_dev_irqresource_disabled(struct resource *res, u32 gsi)
res->flags = IORESOURCE_IRQ | IORESOURCE_DISABLED | IORESOURCE_UNSET;
}
-static void acpi_dev_get_irqresource(struct resource *res, u32 gsi,
+static void acpi_dev_get_irqresource(struct resource *res, u32 hwirq,
+ const struct acpi_resource_source *source,
u8 triggering, u8 polarity, u8 shareable,
bool legacy)
{
int irq, p, t;
- if (!valid_IRQ(gsi)) {
- acpi_dev_irqresource_disabled(res, gsi);
+ if ((source->string_length == 0) && !valid_IRQ(hwirq)) {
+ acpi_dev_irqresource_disabled(res, hwirq);
return;
}
@@ -402,25 +403,25 @@ static void acpi_dev_get_irqresource(struct resource *res, u32 gsi,
* using extended IRQ descriptors we take the IRQ configuration
* from _CRS directly.
*/
- if (legacy && !acpi_get_override_irq(gsi, &t, &p)) {
+ if (legacy && !acpi_get_override_irq(hwirq, &t, &p)) {
u8 trig = t ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
u8 pol = p ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH;
if (triggering != trig || polarity != pol) {
- pr_warning("ACPI: IRQ %d override to %s, %s\n", gsi,
- t ? "level" : "edge", p ? "low" : "high");
+ pr_warn("ACPI: IRQ %d override to %s, %s\n", hwirq,
+ t ? "level" : "edge", p ? "low" : "high");
triggering = trig;
polarity = pol;
}
}
res->flags = acpi_dev_irq_flags(triggering, polarity, shareable);
- irq = acpi_register_gsi(NULL, gsi, triggering, polarity);
+ irq = acpi_irq_domain_register_irq(source, hwirq, triggering, polarity);
if (irq >= 0) {
res->start = irq;
res->end = irq;
} else {
- acpi_dev_irqresource_disabled(res, gsi);
+ acpi_dev_irqresource_disabled(res, hwirq);
}
}
@@ -446,6 +447,7 @@ static void acpi_dev_get_irqresource(struct resource *res, u32 gsi,
bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
struct resource *res)
{
+ const struct acpi_resource_source dummy = { 0, 0, NULL };
struct acpi_resource_irq *irq;
struct acpi_resource_extended_irq *ext_irq;
@@ -460,7 +462,7 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
acpi_dev_irqresource_disabled(res, 0);
return false;
}
- acpi_dev_get_irqresource(res, irq->interrupts[index],
+ acpi_dev_get_irqresource(res, irq->interrupts[index], &dummy,
irq->triggering, irq->polarity,
irq->sharable, true);
break;
@@ -471,6 +473,7 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
return false;
}
acpi_dev_get_irqresource(res, ext_irq->interrupts[index],
+ &ext_irq->resource_source,
ext_irq->triggering, ext_irq->polarity,
ext_irq->sharable, false);
break;
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 3074796..f808afdc 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -563,6 +563,7 @@
IRQCHIP_OF_MATCH_TABLE() \
ACPI_PROBE_TABLE(irqchip) \
ACPI_PROBE_TABLE(clksrc) \
+ ACPI_PROBE_TABLE(dsdt) \
EARLYCON_TABLE()
#define INIT_TEXT \
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index ddbeda6..bb1a838 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -26,6 +26,7 @@
#include <linux/resource_ext.h>
#include <linux/device.h>
#include <linux/property.h>
+#include <linux/irqdomain.h>
#ifndef _LINUX
#define _LINUX
@@ -321,6 +322,31 @@ void acpi_set_irq_model(enum acpi_irq_model_id model,
*/
void acpi_unregister_gsi (u32 gsi);
+#ifdef CONFIG_IRQ_DOMAIN
+
+int acpi_irq_domain_register_irq(const struct acpi_resource_source *source,
+ u32 hwirq, int trigger, int polarity);
+int acpi_irq_domain_unregister_irq(const struct acpi_resource_source *source,
+ u32 hwirq);
+
+#else
+
+static inline int acpi_irq_domain_register_irq(
+ const struct acpi_resource_source *source, u32 hwirq, int trigger,
+ int polarity)
+{
+ return acpi_register_gsi(NULL, hwirq, trigger, polarity);
+}
+
+static inline int acpi_irq_domain_unregister_irq(
+ const struct acpi_resource_source *source, u32 hwirq)
+{
+ acpi_unregister_gsi(hwirq);
+ return 0;
+}
+
+#endif /* CONFIG_IRQ_DOMAIN */
+
struct pci_dev;
int acpi_pci_irq_enable (struct pci_dev *dev);
@@ -1024,6 +1050,34 @@ struct acpi_probe_entry {
(&ACPI_PROBE_TABLE_END(t) - \
&ACPI_PROBE_TABLE(t))); \
})
+
+/* Length of Hardware ID field in DSDT entries as per ACPI spec */
+#define ACPI_HID_LEN 9
+
+typedef int (*acpi_dsdt_handler)(struct acpi_device *);
+
+/**
+ * struct acpi_probe_dsdt_entry - boot-time probing entry for DSDT devices
+ * @hid: _HID of the device
+ * @fn: Callback to the driver being probed
+ * @driver_data: Sideband data provided back to the driver
+ */
+struct acpi_dsdt_probe_entry {
+ __u8 _hid[ACPI_HID_LEN];
+ acpi_dsdt_handler probe;
+};
+
+#define ACPI_DECLARE_DSDT_PROBE_ENTRY(name, hid, fn) \
+ static const struct acpi_dsdt_probe_entry __acpi_probe_##name \
+ __used __section(__dsdt_acpi_probe_table) = \
+ { \
+ ._hid = hid, \
+ .probe = fn, \
+ }
+
+extern struct acpi_dsdt_probe_entry __dsdt_acpi_probe_table;
+extern struct acpi_dsdt_probe_entry __dsdt_acpi_probe_table_end;
+
#else
static inline int acpi_dev_get_property(struct acpi_device *adev,
const char *name, acpi_object_type type,
@@ -1101,8 +1155,25 @@ static inline struct fwnode_handle *acpi_get_next_subnode(struct device *dev,
(void *) data }
#define acpi_probe_device_table(t) ({ int __r = 0; __r;})
+
+#define ACPI_DECLARE_DSDT_PROBE_ENTRY(name, hid, fn) \
+ static const void *__acpi_probe_##name[] \
+ __attribute__((unused)) \
+ = { (void *) hid, \
+ (void *) fn }
+
#endif
+#define MADT_IRQCHIP_ACPI_DECLARE(name, subtable, validate, data, fn) \
+ ACPI_DECLARE_PROBE_ENTRY(irqchip, name, ACPI_SIG_MADT, \
+ subtable, validate, data, fn)
+
+#define DSDT_IRQCHIP_ACPI_DECLARE(name, hid, fn) \
+ ACPI_DECLARE_DSDT_PROBE_ENTRY(name, hid, fn)
+
+#define __IRQCHIP_ACPI_DECLARE(_a1, _a2, _a3, _a4, _a5, type, ...) \
+ type##_IRQCHIP_ACPI_DECLARE
+
#ifdef CONFIG_ACPI_TABLE_UPGRADE
void acpi_table_upgrade(void);
#else
diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h
index 89c34b2..c2d0c12 100644
--- a/include/linux/irqchip.h
+++ b/include/linux/irqchip.h
@@ -29,6 +29,10 @@
/*
* This macro must be used by the different irqchip drivers to declare
* the association between their version and their initialization function.
+ * Two syntaxes are supported depending on the table where the irqchip device
+ * is declared:
+ *
+ * - MADT irqchip syntax, which requires the following five arguments:
*
* @name: name that must be unique accross all IRQCHIP_ACPI_DECLARE of the
* same file.
@@ -37,10 +41,17 @@
* Can be NULL.
* @data: data to be checked by the validate function.
* @fn: initialization function
+ *
+ * - DSDT irqchip syntax, which requires the following three arguments:
+ *
+ * @name: name that must be unique across all IRQCHIP_ACPI_DECLARE of the
+ * same file.
+ * @hid: _HID of the DSDT device
+ * @fn: initialization function
*/
-#define IRQCHIP_ACPI_DECLARE(name, subtable, validate, data, fn) \
- ACPI_DECLARE_PROBE_ENTRY(irqchip, name, ACPI_SIG_MADT, \
- subtable, validate, data, fn)
+
+#define IRQCHIP_ACPI_DECLARE(...) \
+ __IRQCHIP_ACPI_DECLARE(__VA_ARGS__, MADT, _unused, DSDT)(__VA_ARGS__)
#ifdef CONFIG_IRQCHIP
void irqchip_init(void);
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* [PATCH V5 0/2] irqchip: qcom: Add IRQ combiner driver
From: Agustin Vega-Frias @ 2016-10-18 17:41 UTC (permalink / raw)
To: linux-arm-kernel
Add support for IRQ combiners in the Top-level Control and Status
Registers (TCSR) hardware block in Qualcomm Technologies chips.
The first patch adds support for ResourceSource/IRQ domain mapping
when using Extended IRQ Resources with a specific ResourceSource.
The core ACPI resource management code has been changed to lookup
the IRQ domain when an IRQ resource indicates a ResourceSource,
and register the IRQ on that domain, instead of a GSI.
The second patch takes advantage of the new capabilities to implement
the driver for the IRQ combiners.
Changes V1 -> V2:
* Remove use of GPIO library for the combiner
* Refactor to use fwnode/ResourceSource to IRQ domain mapping
introduced in ACPI core
Changes V2 -> V3:
* Removed parsing of _PRS to find IRQs
* Removed acpi_irq_domain_create and acpi_irq_domain_remove
Changes V3 -> V4:
* Add a DSDT device probe table that is used to probe DSDT IRQ chips
as necessary when converting HW IRQs to Linux IRQs
* Describe IRQ combiner registers as ACPI Register resources
Changes V4 -> V5:
* Fix issues flagged by the 0-DAY build bot
* Fix some minor style issues raised by Timur
Agustin Vega-Frias (2):
ACPI: Add support for ResourceSource/IRQ domain mapping
irqchip: qcom: Add IRQ combiner driver
drivers/acpi/Makefile | 1 +
drivers/acpi/irqdomain.c | 141 +++++++++++++++
drivers/acpi/resource.c | 21 ++-
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/qcom-irq-combiner.c | 332 ++++++++++++++++++++++++++++++++++++
include/asm-generic/vmlinux.lds.h | 1 +
include/linux/acpi.h | 71 ++++++++
include/linux/irqchip.h | 17 +-
9 files changed, 581 insertions(+), 12 deletions(-)
create mode 100644 drivers/acpi/irqdomain.c
create mode 100644 drivers/irqchip/qcom-irq-combiner.c
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH v9 2/2] ARM: dts: add TOPEET itop elite based board
From: Krzysztof Kozlowski @ 2016-10-18 17:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476811129-4450-3-git-send-email-ayaka@soulik.info>
On Wed, Oct 19, 2016 at 01:18:49AM +0800, Randy Li wrote:
> The TOPEET itop exynos 4412 have three versions base board. The
> Elite version is the cheap one without too much peripheral devices
> on it.
>
> Currently supported are serial console, wired networking(USB),
> USB OTG in peripheral mode, USB host, SD storage, GPIO buttons,
> PWM beeper, ADC and LEDs. The WM8960 analog audio codec is also
> enabled.
>
> The FIMC is not used for camera currently, I enabled it just for a
> colorspace converter.
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Thanks, applied, with missing Rob's ack, minor changes in commit msg and
fix in pin function (you used macro for pull up/down instead of
function).
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v9 1/2] ARM: dts: Add TOPEET itop core board SCP package version
From: Krzysztof Kozlowski @ 2016-10-18 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476811129-4450-2-git-send-email-ayaka@soulik.info>
On Wed, Oct 19, 2016 at 01:18:48AM +0800, Randy Li wrote:
> The TOPEET itop is a samsung exnynos 4412 core board, which have
> two package versions. This patch add the support for SCP version.
>
> Currently supported are USB3503A HSIC, USB OTG, eMMC, rtc and
> PMIC. The future features are in the based board. Also MFC and
> watchdog have been enabled.
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> ---
> arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 501 ++++++++++++++++++++++++
> 1 file changed, 501 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
Thanks, applied, with minor changes in commit msg and fix in pin
function (you used macro for pull up/down instead of function).
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v9 2/2] ARM: dts: add TOPEET itop elite based board
From: Randy Li @ 2016-10-18 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476811129-4450-1-git-send-email-ayaka@soulik.info>
The TOPEET itop exynos 4412 have three versions base board. The
Elite version is the cheap one without too much peripheral devices
on it.
Currently supported are serial console, wired networking(USB),
USB OTG in peripheral mode, USB host, SD storage, GPIO buttons,
PWM beeper, ADC and LEDs. The WM8960 analog audio codec is also
enabled.
The FIMC is not used for camera currently, I enabled it just for a
colorspace converter.
Signed-off-by: Randy Li <ayaka@soulik.info>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/arm/samsung/samsung-boards.txt | 3 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos4412-itop-elite.dts | 240 +++++++++++++++++++++
3 files changed, 244 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-elite.dts
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index 0ea7f14..5160fa5 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -22,6 +22,9 @@ Required root node properties:
* FriendlyARM
- "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
TINY4412 board.
+ * TOPEET
+ - "topeet,itop4412-elite" - for Exynos4412-based TOPEET
+ Elite base board.
* Google
- "google,pi" - for Exynos5800-based Google Peach Pi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd26..d709f74 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
exynos4210-universal_c210.dtb \
+ exynos4412-itop-elite.dtb \
exynos4412-odroidu3.dtb \
exynos4412-odroidx.dtb \
exynos4412-odroidx2.dtb \
diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
new file mode 100644
index 0000000..7440e54
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
@@ -0,0 +1,240 @@
+/*
+ * TOPEET's Exynos4412 based itop board device tree source
+ *
+ * Copyright (c) 2016 SUMOMO Computer Association
+ * https://www.sumomo.mobi
+ * Randy Li <ayaka@soulik.info>
+ *
+ * Device tree source file for TOPEET iTop Exynos 4412 core board
+ * which is based on Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/sound/samsung-i2s.h>
+#include "exynos4412-itop-scp-core.dtsi"
+
+/ {
+ model = "TOPEET iTop 4412 Elite board based on Exynos4412";
+ compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4";
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait";
+ stdout-path = "serial2:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led2 {
+ label = "red:system";
+ gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led3 {
+ label = "red:user";
+ gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ home {
+ label = "GPIO Key Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpx1 1 GPIO_ACTIVE_LOW>;
+ };
+
+ back {
+ label = "GPIO Key Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ sleep {
+ label = "GPIO Key Sleep";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
+ };
+
+ vol-up {
+ label = "GPIO Key Vol+";
+ linux,code = <KEY_UP>;
+ gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ vol-down {
+ label = "GPIO Key Vol-";
+ linux,code = <KEY_DOWN>;
+ gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm-sound";
+
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>,
+ <&clock_audss EXYNOS_DOUT_SRP>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-rates = <0>,
+ <0>,
+ <112896000>,
+ <11289600>;
+
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&link0_codec>;
+ simple-audio-card,frame-master = <&link0_codec>;
+
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Speaker", "Speaker",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Speaker", "SPK_LP",
+ "Speaker", "SPK_LN",
+ "Speaker", "SPK_RP",
+ "Speaker", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "LINPUT3", "Mic Jack",
+ "RINPUT1", "Mic Jack",
+ "RINPUT2", "Mic Jack";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0 0>;
+ };
+
+ link0_codec: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ clocks = <&i2s0 CLK_I2S_CDCLK>;
+ system-clock-frequency = <11289600>;
+ };
+ };
+
+ beep {
+ compatible = "pwm-beeper";
+ pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>;
+ };
+
+ camera: camera {
+ pinctrl-0 = <&cam_port_a_clk_active>;
+ pinctrl-names = "default";
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_CAM0>;
+ assigned-clock-parents = <&clock CLK_XUSBXTI>;
+ };
+};
+
+&adc {
+ vdd-supply = <&ldo3_reg>;
+ status = "okay";
+};
+
+&ehci {
+ status = "okay";
+ /* In order to reset USB ethernet */
+ samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
+
+ port at 0 {
+ status = "okay";
+ };
+
+ port at 2 {
+ status = "okay";
+ };
+};
+
+&exynos_usbphy {
+ status = "okay";
+};
+
+&fimc_0 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+ <&clock CLK_SCLK_FIMC0>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+};
+
+&hsotg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&i2c_4 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ pinctrl-0 = <&i2c4_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ codec: wm8960 at 1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "MCLK1";
+ wlf,shared-lrclk;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2s0 {
+ pinctrl-0 = <&i2s0_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+};
+
+&pinctrl_1 {
+ ether-reset {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pwm {
+ status = "okay";
+ pinctrl-0 = <&pwm0_out>;
+ pinctrl-names = "default";
+ samsung,pwm-outputs = <0>;
+};
+
+&sdhci_2 {
+ bus-width = <4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+ pinctrl-names = "default";
+ cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>;
+ cap-sd-highspeed;
+ vmmc-supply = <&ldo23_reg>;
+ vqmmc-supply = <&ldo17_reg>;
+ status = "okay";
+};
+
+&serial_1 {
+ status = "okay";
+};
+
+&serial_2 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v9 1/2] ARM: dts: Add TOPEET itop core board SCP package version
From: Randy Li @ 2016-10-18 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476811129-4450-1-git-send-email-ayaka@soulik.info>
The TOPEET itop is a samsung exnynos 4412 core board, which have
two package versions. This patch add the support for SCP version.
Currently supported are USB3503A HSIC, USB OTG, eMMC, rtc and
PMIC. The future features are in the based board. Also MFC and
watchdog have been enabled.
Signed-off-by: Randy Li <ayaka@soulik.info>
---
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 501 ++++++++++++++++++++++++
1 file changed, 501 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
new file mode 100644
index 0000000..881dc76
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
@@ -0,0 +1,501 @@
+/*
+ * TOPEET's Exynos4412 based itop board device tree source
+ *
+ * Copyright (c) 2016 SUMOMO Computer Association
+ * https://www.sumomo.mobi
+ * Randy Li <ayaka@soulik.info>
+ *
+ * Device tree source file for TOPEET iTop Exynos 4412 SCP package core
+ * board which is based on Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
+#include "exynos-mfc-reserved-memory.dtsi"
+
+/ {
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+
+ firmware at 0203F000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0203F000 0x1000>;
+ };
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>;
+ };
+ map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>;
+ };
+ };
+ };
+ };
+
+ usb-hub {
+ compatible = "smsc,usb3503a";
+ reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>;
+ connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>;
+ intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsic_reset>;
+ };
+};
+
+&bus_dmc {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-supply = <&buck1_reg>;
+ status = "okay";
+};
+
+&bus_acp {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_c2c {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_leftbus {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-supply = <&buck3_reg>;
+ status = "okay";
+};
+
+&bus_rightbus {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_fsys {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_peri {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_mfc {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&buck2_reg>;
+};
+
+&hsotg {
+ vusb_d-supply = <&ldo15_reg>;
+ vusb_a-supply = <&ldo12_reg>;
+};
+
+&i2c_1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <400000>;
+ pinctrl-0 = <&i2c1_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ s5m8767: s5m8767-pmic at 66 {
+ compatible = "samsung,s5m8767-pmic";
+ reg = <0x66>;
+
+ s5m8767,pmic-buck-default-dvs-idx = <3>;
+
+ s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>,
+ <&gpb 6 GPIO_ACTIVE_HIGH>,
+ <&gpb 7 GPIO_ACTIVE_HIGH>;
+
+ s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>,
+ <&gpm3 6 GPIO_ACTIVE_HIGH>,
+ <&gpm3 7 GPIO_ACTIVE_HIGH>;
+
+ /* VDD_ARM */
+ s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>,
+ <1243750>, <1118750>,
+ <1068750>, <1012500>,
+ <956250>, <900000>;
+ /* VDD_INT */
+ s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>,
+ <925000>, <925000>,
+ <887500>, <887500>,
+ <850000>, <850000>;
+ /* VDD_G3D */
+ s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>,
+ <1025000>, <950000>,
+ <918750>, <900000>,
+ <875000>, <831250>;
+
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "VDD_ALIVE";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ /* SCP uses 1.5v, POP uses 1.2v */
+ ldo2_reg: LDO2 {
+ regulator-name = "VDDQ_M12";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VDDIOAP_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VDDQ_PRE";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VDD_LDO5";
+ op_mode = <0>; /* Always off Mode */
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VDD10_MPLL";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VDD10_XPLL";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VDD10_MIPI";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "VDD33_LCD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VDD18_MIPI";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VDD18_ABB1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VDD33_UOTG";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VDDIOPERI_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VDD18_ABB02";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VDD10_USH";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VDD18_HSIC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VDDIOAP_MMC012_28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ /* Used by HSIC */
+ ldo18_reg: LDO18 {
+ regulator-name = "VDDIOPERI_28";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "VDD_LDO19";
+ op_mode = <0>; /* Always off Mode */
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VDD28_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "VDD28_AF";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VDDA28_2M";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-name = "VDD28_TF";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-name = "VDD33_A31";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "VDD18_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-name = "VDD18_A31";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo27_reg: LDO27 {
+ regulator-name = "GPS_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo28_reg: LDO28 {
+ regulator-name = "DVDD12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1456250>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "vdd_m12";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "vdd12_5m";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "pvdd_buck7";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "pvdd_buck8";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "vddf28_emmc";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3000000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+ };
+
+ s5m8767_osc: clocks {
+ #clock-cells = <1>;
+ clock-output-names = "s5m8767_ap",
+ "s5m8767_cp", "s5m8767_bt";
+ };
+
+ };
+};
+
+&mfc {
+ status = "okay";
+};
+
+&mshc_0 {
+ pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc-supply = <&buck9_reg>;
+ num-slots = <1>;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+};
+
+&pinctrl_1 {
+ hsic_reset: hsic-reset {
+ samsung,pins = "gpm2-4";
+ samsung,pin-function = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ };
+};
+
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
+};
+
+&tmu {
+ vtmu-supply = <&ldo16_reg>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v9 0/2] Add a new board TOPEET iTOP for Exynos 4412
From: Randy Li @ 2016-10-18 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <devicetree@vger.kernel.org>
Changelog:
- v9:
- fix some warnings.
- use the new pin defined for pinctrl.
- v8:
- add the missing LDOs for PMIC, the pins for LDOs are not avaiabled in core
board.
- re-order the header files in core board.
- skip the vendor prefix file
- v7:
- add a missing header file
- add a rootdelay to bootargs or it can't mount root filesystem
- fix the memory node
- v6:
- move pwms pinctrl to pwms node
- fix the order of the dtb file in Makefile
- v5:
- correct the mail format
- v4:
- re-order some nodes in alphabetical order
- fix some minor bugs
- add a entry in vendor list
- v3:
- fixing the rtc clock, using clock source from PMIC
- enable the tmu
- enable the fimc for elite board
- suuport the audio codec at elite board, but the audio sound a little
distortion
- fixing minor bugs in the last commit
- v2:
- removing rtc node
the clock source driver is not done yet.
- adding exynos-bus
- fixing the MFC
Randy Li (2):
ARM: dts: Add TOPEET itop core board SCP package version
ARM: dts: add TOPEET itop elite based board
.../bindings/arm/samsung/samsung-boards.txt | 3 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos4412-itop-elite.dts | 240 ++++++++++
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 501 +++++++++++++++++++++
4 files changed, 745 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-elite.dts
create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
--
2.7.4
^ permalink raw reply
* [PATCH] [ARM] Fix stack alignment when processing backtraces
From: Jason Gunthorpe @ 2016-10-18 17:05 UTC (permalink / raw)
To: linux-arm-kernel
The dumpstm helper within c_backtrace pushed 5 dwords onto the stack
causing the stack to become unaligned and then calls printk. This
causes memory corruption in the kernel which assumes AAPCS calling
convention.
Since this bit of asm doesn't use the standard prologue just add
another register to restore alignment.
Fixes: 7ab3f8d595a1b ("[ARM] Add ability to dump exception stacks to kernel backtraces")
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
arch/arm/lib/backtrace.S | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
In my case the kernel was hitting a WARN_ON during boot and then
reliably failed to start the compiled-in initramfs.
I'm inferring that the stack misalignment caused some kind of memory
corruption which wiped out the unpacked initramfs.
Saw with gcc 5.4.0 on a kirkwood armv5te
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index fab5a50503ae..25e1cce19991 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -116,7 +116,8 @@ ENDPROC(c_backtrace)
#define reg r5
#define stack r6
-.Ldumpstm: stmfd sp!, {instr, reg, stack, r7, lr}
+ /* Must maintain 8 byte stack alignment */
+.Ldumpstm: stmfd sp!, {r3, instr, reg, stack, r7, lr}
mov stack, r0
mov instr, r1
mov reg, #10
@@ -140,7 +141,7 @@ ENDPROC(c_backtrace)
teq r7, #0
adrne r0, .Lcr
blne printk
- ldmfd sp!, {instr, reg, stack, r7, pc}
+ ldmfd sp!, {r3, instr, reg, stack, r7, pc}
.Lfp: .asciz " r%d:%08x%s"
.Lcr: .asciz "\n"
--
2.1.4
^ permalink raw reply related
* [PATCH v5 23/23] phy: Add support for Qualcomm's USB HS phy
From: Rob Herring @ 2016-10-18 16:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018015636.11701-24-stephen.boyd@linaro.org>
On Mon, Oct 17, 2016 at 06:56:36PM -0700, Stephen Boyd wrote:
> The high-speed phy on qcom SoCs is controlled via the ULPI
> viewport.
>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: <devicetree@vger.kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> ---
> .../devicetree/bindings/phy/qcom,usb-hs-phy.txt | 86 +++++++
Acked-by: Rob Herring <robh@kernel.org>
> drivers/phy/Kconfig | 8 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-qcom-usb-hs.c | 286 +++++++++++++++++++++
> 4 files changed, 381 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt
> create mode 100644 drivers/phy/phy-qcom-usb-hs.c
^ permalink raw reply
* [PATCH v5 23/23] phy: Add support for Qualcomm's USB HS phy
From: Rob Herring @ 2016-10-18 16:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018015636.11701-24-stephen.boyd@linaro.org>
On Mon, Oct 17, 2016 at 06:56:36PM -0700, Stephen Boyd wrote:
> The high-speed phy on qcom SoCs is controlled via the ULPI
> viewport.
>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: <devicetree@vger.kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> ---
> .../devicetree/bindings/phy/qcom,usb-hs-phy.txt | 86 +++++++
Acked-by: Rob Herring <robh@kernel.org>
> drivers/phy/Kconfig | 8 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-qcom-usb-hs.c | 286 +++++++++++++++++++++
> 4 files changed, 381 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt
> create mode 100644 drivers/phy/phy-qcom-usb-hs.c
^ permalink raw reply
* [PATCH v5 03/23] usb: ulpi: Support device discovery via DT
From: Rob Herring @ 2016-10-18 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018015636.11701-4-stephen.boyd@linaro.org>
On Mon, Oct 17, 2016 at 06:56:16PM -0700, Stephen Boyd wrote:
> The qcom HSIC ULPI phy doesn't have any bits set in the vendor or
> product ID registers. This makes it impossible to make a ULPI
> driver match against the ID registers. Add support to discover
> the ULPI phys via DT help alleviate this problem. In the DT case,
> we'll look for a ULPI bus node underneath the device registering
> the ULPI viewport (or the parent of that device to support
> chipidea's device layout) and then match up the phy node
> underneath that with the ULPI device that's created.
>
> The side benefit of this is that we can use standard properties
> in the phy node like clks, regulators, gpios, etc. because we
> don't have firmware like ACPI to turn these things on for us. And
> we can use the DT phy binding to point our phy consumer to the
> phy provider.
>
> The ULPI bus code supports native enumeration by reading the
> vendor ID and product ID registers at device creation time, but
> we can't be certain that those register reads will succeed if the
> phy is not powered up. To avoid any problems with reading the ID
> registers before the phy is powered we fallback to DT matching
> when the ID reads fail.
>
> If the ULPI spec had some generic power sequencing for these
> registers we could put that into the ULPI bus layer and power up
> the device before reading the ID registers. Unfortunately this
> doesn't exist and the power sequence is usually device specific.
> By having the device matched up with DT we can avoid this
> problem.
>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> Cc: <devicetree@vger.kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> ---
> Documentation/devicetree/bindings/usb/ulpi.txt | 20 +++++++
> drivers/usb/common/ulpi.c | 79 ++++++++++++++++++++++++--
> 2 files changed, 93 insertions(+), 6 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/usb/ulpi.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 4/4] net: smsc91x: add u16 workaround for pxa platforms
From: Rob Herring @ 2016-10-18 16:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476733532-29716-5-git-send-email-robert.jarzmik@free.fr>
On Mon, Oct 17, 2016 at 09:45:32PM +0200, Robert Jarzmik wrote:
> Add a workaround for mainstone, idp and stargate2 boards, for u16 writes
> which must be aligned on 32 bits addresses.
>
> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
> Cc: Jeremy Linton <jeremy.linton@arm.com>
> ---
> Since v1: rename dt property to pxa-u16-align4
> change the binding documentation file
> ---
> Documentation/devicetree/bindings/net/smsc-lan91c111.txt | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v2] ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
From: Eric Anholt @ 2016-10-18 16:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
The idea is to give useful names to GPIO lines that an implementer
will be using from userspace, e.g. for maker type projects. These are
user-visible using tools/gpio/lsgpio.c
v2: Major rewrite by anholt: Flatten each GPIO line to a line in the
file for better diffing, prefix all expansion header pins with
"P<number>" or "P5HEADER_P<number>" and drop the mostly-unused
GPIO_GEN<smallnumber> names in favor of GPIO<socgpionumber>, fix
extra '[]' on a couple of lines, fix locations of SD_CARD_DETECT,
CAM_GPIO and STATUS_LED, fix HDMI_HPD polarities, rewrite A+ using
unreleased schematics.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
Note: I haven't actually booted these and checked that the names line
up, just tried to visually review them. Hopefully with more
GPIO<number> values, it's easier to spot errors.
The only other thing here I think I would do is drop the [] around
names for behavior when pinmuxed. I find it more confusing than
helpful.
Linus, are these names considered ABI? Will we be locked into
whatever set of names we merge and release? My assumption would be
"yes".
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 66 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-a.dts | 68 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 67 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 67 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-b.dts | 68 ++++++++++++++++++++++++++++++++
5 files changed, 336 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
index 21507c922783..cec4c6e49e7b 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -22,6 +22,72 @@
};
&gpio {
+ /*
+ * This is based on the unreleased schematic for the Model A+.
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "[FOO]" = pin is muxed for peripheral FOO (not GPIO)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "[SDA0]",
+ "[SCL0]",
+ "[P3_SDA1]",
+ "[P5_SCL1]",
+ "[P7_GPIO_GCLK]",
+ "P29_GPIO5",
+ "P31_GPIO6",
+ "[P26_SPI_CE1_N]",
+ "[P24_SPI_CE0_N]",
+ "[P21_SPI_MISO]",
+ "[P19_SPI_MOSI]",
+ "[P23_SPI_SCLK]",
+ "P32_GPIO12",
+ "P33_GPIO13",
+ /* Serial port */
+ "[P8_TXD0]",
+ "[P10_RXD0]",
+ "P36_GPIO16",
+ "P11_GPIO17",
+ "P12_GPIO18",
+ "P35_GPIO19",
+ "P38_GPIO20",
+ "P40_GPIO21",
+ "P15_GPIO22",
+ "P16_GPIO23",
+ "P18_GPIO24",
+ "P22_GPIO25",
+ "P37_GPIO26",
+ "P13_GPIO27",
+ "[SDA0]",
+ "[SCL0]",
+ "NC", /* GPIO30 */
+ "NC", /* GPIO31 */
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "PWR_LOW_N", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "[PWM0_OUT]", /* GPIO40 */
+ "CAM_GPIO0", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "[PWM1_OUT]", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED",
+ /* Used by SD Card */
+ "[SD_CLK_R]",
+ "[SD_CMD_R]",
+ "[SD_DATA0_R]",
+ "[SD_DATA1_R]",
+ "[SD_DATA2_R]",
+ "[SD_DATA3_R]";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts
index 5afba0900449..0ff96ed4d15b 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
@@ -15,6 +15,74 @@
};
&gpio {
+ /*
+ * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
+ * RPI00021 sheet 02
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "[FOO]" = pin is muxed for peripheral FOO (not GPIO)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "[P3_SDA0]",
+ "[P5_SCL0]",
+ "[SDA1]",
+ "[SCL1]",
+ "[P7_GPIO_GCLK]",
+ "[CAM_CLK]",
+ "LAN_RUN",
+ "[P26_SPI_CE1_N]",
+ "[P24_SPI_CE0_N]",
+ "[P21_SPI_MISO]",
+ "[P19_SPI_MOSI]",
+ "[P23_SPI_SCLK]",
+ "NC", /* GPIO12 */
+ "NC", /* GPIO13 */
+ /* Serial port */
+ "[P8_TXD0]",
+ "[P10_RXD0]",
+ "STATUS_LED_N",
+ "P11_GPIO17",
+ "P12_GPIO18",
+ "NC", /* GPIO19 */
+ "NC", /* GPIO20 */
+ "P13_GPIO21",
+ "P15_GPIO22",
+ "P16_GPIO23",
+ "P18_GPIO24",
+ "P22_GPIO25",
+ "NC", /* GPIO26 */
+ "CAM_GPIO",
+ /* Binary number representing build/revision */
+ "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "CONFIG3",
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "[PWM0_OUT]",
+ "NC", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "[PWM1_OUT]",
+ "HDMI_HPD_P",
+ "SD_CARD_DET",
+ /* Used by SD Card */
+ "[SD_CLK_R]",
+ "[SD_CMD_R]",
+ "[SD_DATA0_R]",
+ "[SD_DATA1_R]",
+ "[SD_DATA2_R]",
+ "[SD_DATA3_R]";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index 38f66aa244fe..0e04fc2eb65e 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -23,6 +23,73 @@
};
&gpio {
+ /*
+ * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf
+ * RPI-BPLUS sheet 1
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "[FOO]" = pin is muxed for peripheral FOO (not GPIO)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "[ID_SD]",
+ "[ID_SC]",
+ "[P3_SDA1]",
+ "[P5_SCL1]",
+ "[P7_GPIO_GCLK]",
+ "P29_GPIO5",
+ "P31_GPIO6",
+ "[P26_SPI_CE1_N]",
+ "[P24_SPI_CE0_N]",
+ "[P21_SPI_MISO]",
+ "[P19_SPI_MOSI]",
+ "[P23_SPI_SCLK]",
+ "P23_GPIO12",
+ "P33_GPIO13",
+ /* Serial port */
+ "[P8_TXD0]",
+ "[P10_RXD0]",
+ "P36_GPIO16",
+ "P11_GPIO17",
+ "P12_GPIO18",
+ "P35_GPIO19",
+ "P38_GPIO20",
+ "P40_GPIO21",
+ "P15_GPIO22",
+ "P16_GPIO23",
+ "P18_GPIO24",
+ "P22_GPIO25",
+ "P37_GPIO26",
+ "P13_GPIO27",
+ "[SDA0]",
+ "[SCL0]",
+ "NC", /* GPIO30 */
+ "LAN_RUN", /* GPIO31 */
+ "CAM_GPIO1", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "PWR_LOW_N", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "[PWM0_OUT]", /* GPIO40 */
+ "CAM_GPIO0", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "ETHCLK", /* GPIO44 */
+ "[PWM1_OUT]", /* GPIO45 */
+ "HDMI_HPD_N",
+ "STATUS_LED",
+ /* Used by SD Card */
+ "[SD_CLK_R]",
+ "[SD_CMD_R]",
+ "[SD_DATA0_R]",
+ "[SD_DATA1_R]",
+ "[SD_DATA2_R]",
+ "[SD_DATA3_R]";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
index 75e045aba7ce..6c91c9f0536c 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
@@ -16,6 +16,73 @@
};
&gpio {
+ /*
+ * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf
+ * RPI00022 sheet 02
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "[FOO]" = pin is muxed for peripheral FOO (not GPIO)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "[SDA0]",
+ "[SCL0]",
+ "[P3_SDA1]",
+ "[P5_SCL1]",
+ "[P7_GPIO_GCLK]",
+ "[CAM_CLK]",
+ "LAN_RUN",
+ "[P26_SPI_CE1_N]",
+ "[P24_SPI_CE0_N]",
+ "[P21_SPI_MISO]",
+ "[P19_SPI_MOSI]",
+ "[P23_SPI_SCLK]",
+ "NC", /* GPIO12 */
+ "NC", /* GPIO13 */
+ /* Serial port */
+ "[P8_TXD0]",
+ "[P10_RXD0]",
+ "STATUS_LED_N",
+ "P11_GPIO17",
+ "P12_GPIO18",
+ "NC", /* GPIO19 */
+ "NC", /* GPIO20 */
+ "CAM_GPIO",
+ "P15_GPIO22",
+ "P16_GPIO23",
+ "P18_GPIO24",
+ "P22_GPIO25",
+ "NC", /* GPIO 26 */
+ "P13_GPIO27",
+ "P5HEADER_P3_GPIO28",
+ "P5HEADER_P4_GPIO29",
+ "P5HEADER_P5_GPIO30",
+ "P5HEADER_P6_GPIO31",
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "[PWM0_OUT]",
+ "NC", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "[PWM1_OUT]",
+ "HDMI_HPD_P",
+ "SD_CARD_DET",
+ /* Used by SD Card */
+ "[SD_CLK_R]",
+ "[SD_CMD_R]",
+ "[SD_DATA0_R]",
+ "[SD_DATA1_R]",
+ "[SD_DATA2_R]",
+ "[SD_DATA3_R]";
+
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 76a254b3219a..023239946826 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -16,6 +16,74 @@
};
&gpio {
+ /*
+ * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf
+ * RPI00021 sheet 02
+ *
+ * Legend:
+ * "NC" = not connected (no rail from the SoC)
+ * "[FOO]" = pin is muxed for peripheral FOO (not GPIO)
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "[P3_SDA0]",
+ "[P5_SCL0]",
+ "[SDA1]",
+ "[SCL1]",
+ "[P7_GPIO_GCLK]",
+ "[CAM_CLK]",
+ "LAN_RUN",
+ "[P26_SPI_CE1_N]",
+ "[P24_SPI_CE0_N]",
+ "[P21_SPI_MISO]",
+ "[P19_SPI_MOSI]",
+ "[P23_SPI_SCLK]",
+ "NC", /* GPIO12 */
+ "NC", /* GPIO13 */
+ /* Serial port */
+ "[P8_TXD0]",
+ "[P10_RXD0]",
+ "STATUS_LED_N",
+ "P11_GPIO17",
+ "P12_GPIO18",
+ "NC", /* GPIO19 */
+ "NC", /* GPIO20 */
+ "P13_GPIO21",
+ "P15_GPIO22",
+ "P16_GPIO23",
+ "P18_GPIO24",
+ "P22_GPIO25",
+ "NC", /* GPIO26 */
+ "CAM_GPIO",
+ /* Binary number representing build/revision */
+ "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "CONFIG3",
+ "NC", /* GPIO32 */
+ "NC", /* GPIO33 */
+ "NC", /* GPIO34 */
+ "NC", /* GPIO35 */
+ "NC", /* GPIO36 */
+ "NC", /* GPIO37 */
+ "NC", /* GPIO38 */
+ "NC", /* GPIO39 */
+ "[PWM0_OUT]",
+ "NC", /* GPIO41 */
+ "NC", /* GPIO42 */
+ "NC", /* GPIO43 */
+ "NC", /* GPIO44 */
+ "[PWM1_OUT]",
+ "HDMI_HPD_P",
+ "SD_CARD_DET",
+ /* Used by SD Card */
+ "[SD_CLK_R]",
+ "[SD_CMD_R]",
+ "[SD_DATA0_R]",
+ "[SD_DATA1_R]",
+ "[SD_DATA2_R]",
+ "[SD_DATA3_R]";
+
pinctrl-0 = <&gpioout &alt0>;
};
--
2.9.3
^ permalink raw reply related
* [PATCH v2] scripts/gdb: add lx-fdtdump command
From: Peter Griffin @ 2016-10-18 16:33 UTC (permalink / raw)
To: linux-arm-kernel
lx-fdtdump dumps the flattened device tree passed to the kernel
from the bootloader to the filename specified as the command
argument. If no argument is provided it defaults to fdtdump.dtb.
This then allows further post processing on the machine running GDB.
The fdt header is also also printed in the GDB console. For example:
(gdb) lx-fdtdump
fdt_magic: 0xD00DFEED
fdt_totalsize: 0xC108
off_dt_struct: 0x38
off_dt_strings: 0x3804
off_mem_rsvmap: 0x28
version: 17
last_comp_version: 16
Dumped fdt to fdtdump.dtb
>fdtdump fdtdump.dtb | less
This command is useful as the bootloader can often re-write parts
of the device tree, and this can sometimes cause the kernel to not
boot.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Changes since v1
- s/flatenned/flattened/ (Kieran)
- Add filename as argument to command (Jan / Kieran)
- Check LX_CONFIG_OF early to reduce indendation (Kieran)
- Add gdb.COMPLETE_FILENAME to get auto completion (Jan)
- Squash pep8 fixup patch (Kieran)
---
scripts/gdb/linux/constants.py.in | 8 +++++
scripts/gdb/linux/proc.py | 73 +++++++++++++++++++++++++++++++++++++++
2 files changed, 81 insertions(+)
diff --git a/scripts/gdb/linux/constants.py.in b/scripts/gdb/linux/constants.py.in
index 7986f4e..43c6241 100644
--- a/scripts/gdb/linux/constants.py.in
+++ b/scripts/gdb/linux/constants.py.in
@@ -14,6 +14,7 @@
#include <linux/fs.h>
#include <linux/mount.h>
+#include <linux/of_fdt.h>
/* We need to stringify expanded macros so that they can be parsed */
@@ -50,3 +51,10 @@ LX_VALUE(MNT_NOEXEC)
LX_VALUE(MNT_NOATIME)
LX_VALUE(MNT_NODIRATIME)
LX_VALUE(MNT_RELATIME)
+
+/* linux/of_fdt.h> */
+LX_VALUE(OF_DT_HEADER)
+
+/* Kernel Configs */
+LX_CONFIG(CONFIG_OF)
+
diff --git a/scripts/gdb/linux/proc.py b/scripts/gdb/linux/proc.py
index 38b1f09..086d272 100644
--- a/scripts/gdb/linux/proc.py
+++ b/scripts/gdb/linux/proc.py
@@ -16,6 +16,7 @@ from linux import constants
from linux import utils
from linux import tasks
from linux import lists
+from struct import *
class LxCmdLine(gdb.Command):
@@ -195,3 +196,75 @@ values of that process namespace"""
info_opts(MNT_INFO, m_flags)))
LxMounts()
+
+
+class LxFdtDump(gdb.Command):
+ """Output Flattened Device Tree header and dump FDT blob to the filename
+ specified as the command argument. Equivalent to
+ 'cat /proc/fdt > fdtdump.dtb' on a running target"""
+
+ def __init__(self):
+ super(LxFdtDump, self).__init__("lx-fdtdump", gdb.COMMAND_DATA,
+ gdb.COMPLETE_FILENAME)
+
+ def fdthdr_to_cpu(self, fdt_header):
+
+ fdt_header_be = ">IIIIIII"
+ fdt_header_le = "<IIIIIII"
+
+ if utils.get_target_endianness() == 1:
+ output_fmt = fdt_header_le
+ else:
+ output_fmt = fdt_header_be
+
+ return unpack(output_fmt, pack(fdt_header_be,
+ fdt_header['magic'],
+ fdt_header['totalsize'],
+ fdt_header['off_dt_struct'],
+ fdt_header['off_dt_strings'],
+ fdt_header['off_mem_rsvmap'],
+ fdt_header['version'],
+ fdt_header['last_comp_version']))
+
+ def invoke(self, arg, from_tty):
+
+ if not constants.LX_CONFIG_OF:
+ raise gdb.GdbError("Kernel not compiled with CONFIG_OF\n")
+
+ if len(arg) == 0:
+ filename = "fdtdump.dtb"
+ else:
+ filename = arg
+
+ py_fdt_header_ptr = gdb.parse_and_eval(
+ "(const struct fdt_header *) initial_boot_params")
+ py_fdt_header = py_fdt_header_ptr.dereference()
+
+ fdt_header = self.fdthdr_to_cpu(py_fdt_header)
+
+ if fdt_header[0] != constants.LX_OF_DT_HEADER:
+ raise gdb.GdbError("No flattened device tree magic found\n")
+
+ gdb.write("fdt_magic: 0x{:02X}\n".format(fdt_header[0]))
+ gdb.write("fdt_totalsize: 0x{:02X}\n".format(fdt_header[1]))
+ gdb.write("off_dt_struct: 0x{:02X}\n".format(fdt_header[2]))
+ gdb.write("off_dt_strings: 0x{:02X}\n".format(fdt_header[3]))
+ gdb.write("off_mem_rsvmap: 0x{:02X}\n".format(fdt_header[4]))
+ gdb.write("version: {}\n".format(fdt_header[5]))
+ gdb.write("last_comp_version: {}\n".format(fdt_header[6]))
+
+ inf = gdb.inferiors()[0]
+ fdt_buf = utils.read_memoryview(inf, py_fdt_header_ptr,
+ fdt_header[1]).tobytes()
+
+ try:
+ f = open(filename, 'wb')
+ except:
+ raise gdb.GdbError("Could not open file to dump fdt")
+
+ f.write(fdt_buf)
+ f.close()
+
+ gdb.write("Dumped fdt blob to " + filename + "\n")
+
+LxFdtDump()
--
1.9.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox