* [PATCH 3/3] dt-bindings: oxnas: Update Pinctrl and GPIO for OX820 Support
From: Linus Walleij @ 2016-10-20 13:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161004134148.23028-4-narmstrong@baylibre.com>
On Tue, Oct 4, 2016 at 3:41 PM, Neil Armstrong <narmstrong@baylibre.com> wrote:
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [linux-sunxi] Re: [PATCH 0/3] pinctrl: sunxi: Support generic pinconf functions
From: Chen-Yu Tsai @ 2016-10-20 13:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZHTQqnsuHcm3+iYQJc2picLu95W2OKeMiXFq+XNzDV3g@mail.gmail.com>
On Thu, Oct 20, 2016 at 9:13 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Tue, Oct 4, 2016 at 3:51 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>
>> This series fixes up generic pinconf support for the sunxi pinctrl driver
>> library. The driver was doing some bits wrong, like a) storing the pinconf
>> config value in its struct, and not actually reading the hardware to get
>> the current config, and b) not using the right arguments for the bias
>> parameters.
>
> Looks OK to me, Maxime are you OK with me applying this, or
> are we waiting for a new iteration of this patch set?
>
> I have started to apply Maxime's generic binding rework, will it
> clash with these?
They will, as my patches also touch the pinconf .get/.set functions.
ChenYu
>
> Yours,
> Linus Walleij
>
> --
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^ permalink raw reply
* Bunch of CRC errors in next with arm: move exports to definitions
From: Tony Lindgren @ 2016-10-20 13:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5893445.41LAZjK8v5@wuerfel>
* Arnd Bergmann <arnd@arndb.de> [161018 03:02]:
> On Tuesday, October 18, 2016 10:36:28 AM CEST Russell King - ARM Linux wrote:
> > On Tue, Oct 18, 2016 at 11:13:31AM +0200, Arnd Bergmann wrote:
> > > On Tuesday, October 18, 2016 6:59:44 AM CEST Sebastian Reichel wrote:
> > > > Hi,
> > > >
> > > > On Mon, Aug 22, 2016 at 09:25:13AM -0700, Tony Lindgren wrote:
> > > > > Looks like starting with next-20160818 I'm now getting close to
> > > > > 800 lines of WARNINGs on ARM with omap2plus_defconfig while doing
> > > > > make modules:
> > > > >
> > > > > Building modules, stage 2.
> > > > > MODPOST 399 modules
> > > > > WARNING: "__memzero" [sound/usb/snd-usbmidi-lib.ko] has no CRC!
> > > > > WARNING: "memset" [sound/usb/snd-usbmidi-lib.ko] has no CRC!
> > > > > WARNING: "memcpy" [sound/usb/snd-usbmidi-lib.ko] has no CRC!
> > > > > WARNING: "_set_bit" [sound/usb/snd-usbmidi-lib.ko] has no CRC!
> > > > > WARNING: "_test_and_set_bit" [sound/usb/snd-usbmidi-lib.ko] has no CRC!
> > > > > WARNING: "_clear_bit" [sound/usb/snd-usbmidi-lib.ko] has no CRC!
> > > > > WARNING: "__aeabi_uidivmod" [sound/usb/snd-usb-audio.ko] has no CRC!
> > > > > WARNING: "_test_and_clear_bit" [sound/usb/snd-usb-audio.ko] has no CRC!
> > > > > WARNING: "arm_copy_to_user" [sound/usb/snd-usb-audio.ko] has no CRC!
> > > > > WARNING: "__aeabi_uidiv" [sound/usb/snd-usb-audio.ko] has no CRC!
> > > > > ...
> > > > > WARNING: "memset" [crypto/drbg.ko] has no CRC!
> > > > > WARNING: "memcpy" [crypto/ctr.ko] has no CRC!
> > > > > WARNING: "memcpy" [crypto/cmac.ko] has no CRC!
> > > > > WARNING: "__memzero" [crypto/cmac.ko] has no CRC!
> > > > > WARNING: "memcpy" [crypto/ccm.ko] has no CRC!
> > > > > WARNING: "__memzero" [crypto/ccm.ko] has no CRC!
> > > >
> > > > Any update on this one? I just updated my power-supply next branch
> > > > to v4.9-rc1 and now get almost 18000 CRC warnings for allmodconfig.
> > > > (I use arm-linux-gnueabihf-gcc (Debian 6.1.1-9) 6.1.1 20160705)
> > >
> > > Nick did a patch to fix this in general, and in powerpc specifically,
> > > I sent a patch yesterday to fix the ARM specific symbols.
> >
> > Did you now? You failed to _at least_ copy me on that. This is clearly
> > about core ARM code and not arm-soc stuff, you should always copy me on
> > such changes, and if I were Lee Jones, I'd insist that it was merged
> > through my tree.
>
> Right, sorry for missing the Cc, this was one of many build-time
> bugfix patches I sent out recently.
>
> Nick's patch is still under discussion on linux-arch, and my patch
> is part of that discussion, but of course you should have been
> included in the discussion as well.
For reference, that thread seems to be at:
http://lkml.org/lkml/2016/10/19/221
Tony
^ permalink raw reply
* [PATCH 0/2] STM32 pinctrl: remove dependency between pinctrl driver and device tree
From: Alexandre TORGUE @ 2016-10-20 13:26 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Currently 4.9-rc1 is not booting correctly on STM32F4.
By adding gpios irqs support to stm32 pinctrl, a dependency has been
added between pinctrl stm32 and stm32f4 device tree (my mistake).
This series breaks this dependency and has to be taken on 4.9_rcs.
Regards
Alex
Alexandre TORGUE (2):
pinctrl: stm32: remove dependency with interrupt controller
pinctrl: stm32: move gpio irqs binding to optional
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 10 +++++-----
drivers/pinctrl/stm32/pinctrl-stm32.c | 8 +++++---
2 files changed, 10 insertions(+), 8 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH 1/2] pinctrl: stm32: remove dependency with interrupt controller
From: Alexandre TORGUE @ 2016-10-20 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476970012-7838-1-git-send-email-alexandre.torgue@st.com>
This patch allows to probe stm32 pinctrl driver even if no interrupt
controller is defined to manage gpio irqs.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 200667f..efc4371 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -1092,9 +1092,11 @@ int stm32_pctl_probe(struct platform_device *pdev)
return -EINVAL;
}
- ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
- if (ret)
- return ret;
+ if (of_find_property(np, "interrupt-parent", NULL)) {
+ ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
+ if (ret)
+ return ret;
+ }
for_each_child_of_node(np, child)
if (of_property_read_bool(child, "gpio-controller"))
--
1.9.1
^ permalink raw reply related
* [PATCH 2/2] pinctrl: stm32: move gpio irqs binding to optional
From: Alexandre TORGUE @ 2016-10-20 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476970012-7838-1-git-send-email-alexandre.torgue@st.com>
stm32 pinctrl driver could be probed even if no interrupt controller
is defined to manage gpio irqs. Entries related to gpio irq management
are moved to optional.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index f9753c4..b24583a 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -14,11 +14,6 @@ Required properies:
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
gpio-bank node (children).
- - interrupt-parent: phandle of the interrupt parent to which the external
- GPIO interrupts are forwarded to.
- - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
- which includes IRQ mux selection register, and the offset of the IRQ mux
- selection register.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
@@ -37,6 +32,11 @@ Required properties:
Optional properties:
- reset: : Reference to the reset controller
+ - interrupt-parent: phandle of the interrupt parent to which the external
+ GPIO interrupts are forwarded to.
+ - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
+ which includes IRQ mux selection register, and the offset of the IRQ mux
+ selection register.
Example:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
--
1.9.1
^ permalink raw reply related
* [PATCH 2/2] arm64/numa: fix incorrect print of end_pfn
From: Hanjun Guo @ 2016-10-20 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020125511.GG10234@leverpostej>
On 2016/10/20 20:55, Mark Rutland wrote:
> On Thu, Oct 20, 2016 at 08:21:37PM +0800, Hanjun Guo wrote:
>> On 2016/10/20 18:51, Will Deacon wrote:
>>> On Thu, Oct 20, 2016 at 11:52:56AM +0800, Hanjun Guo wrote:
>>>> From: Hanjun Guo <hanjun.guo@linaro.org>
>>>>
>>>> When booting on NUMA system with memory-less node (no
>>>> memory dimm on this memory controller), the print
>>>> for setup_node_data() is incorrect:
>>>>
>>>> NUMA: Initmem setup node 2 [mem 0x00000000-0xffffffffffffffff]
>>>>
>>>> It should be 0, not 0xffffffffffffffff as there is
>>>> no memory on that node.
>>> Wouldn't it make more sense to print something useful, like "memory-less
>>> node"?
>> in the log,
>>
>> [ 0.000000] NUMA: Initmem setup node 0 [mem 0x00000000-0x13fbffffff]
>> [ 0.000000] NUMA: NODE_DATA [mem 0x13fbffe500-0x13fbffffff]
>> [ 0.000000] NUMA: Initmem setup node 1 [mem 0x1400000000-0x17fbffffff]
>> [ 0.000000] NUMA: NODE_DATA [mem 0x17fbfec500-0x17fbfedfff]
>> [ 0.000000] NUMA: Initmem setup node 2 [mem 0x00000000-0xffffffffffffffff]
>> [ 0.000000] NUMA: NODE_DATA [mem 0x17fbfeaa00-0x17fbfec4ff]
>> [ 0.000000] NUMA: NODE_DATA(2) on node 1
>> [ 0.000000] NUMA: Initmem setup node 3 [mem 0x00000000-0xffffffffffffffff]
>> [ 0.000000] NUMA: NODE_DATA [mem 0x17fbfe8f00-0x17fbfea9ff]
>> [ 0.000000] NUMA: NODE_DATA(3) on node 1
>>
>> if printing "NUMA: Initmem setup node 2 [mem 0x00000000-0x00000000]",
> Seeing "NUMA: Initmem setup node 2 [<memoryless node>]" would be far
> more obvious as a memoryless node, and I don't see that this would be
> inconsistent.
I misunderstood Will's intention, I though printing "NUMA: memory-less node 2".
so do you mean code like below?
diff --git a/arch/arm64/mm/numa.c b/arch/arm64/mm/numa.c
index 34415fc..bf4e39b 100644
--- a/arch/arm64/mm/numa.c
+++ b/arch/arm64/mm/numa.c
@@ -226,8 +226,11 @@ static void __init setup_node_data(int nid, u64 start_pfn, u64 end_pfn)
void *nd;
int tnid;
- pr_info("Initmem setup node %d [mem %#010Lx-%#010Lx]\n",
- nid, start_pfn << PAGE_SHIFT, (end_pfn << PAGE_SHIFT) - 1);
+ if ((end_pfn - start_pfn) != 0)
+ pr_info("Initmem setup node %d [mem %#010Lx-%#010Lx]\n", nid,
+ start_pfn << PAGE_SHIFT, (end_pfn << PAGE_SHIFT) - 1);
+ else
+ pr_info("Initmem setup node %d [<memory-less node>]\n", nid);
nd_pa = memblock_alloc_try_nid(nd_size, SMP_CACHE_BYTES, nid);
nd = __va(nd_pa);
Thanks
Hanjun
^ permalink raw reply related
* [PATCH v2] drivers: psci: PSCI checker module
From: Kevin Brodsky @ 2016-10-20 13:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e57565e8-bec9-0460-32d5-fb9f868cc4f8@arm.com>
Hi Jean-Philippe,
On 18/10/16 20:21, Jean-Philippe Brucker wrote:
> Hi Kevin,
>
> On 21/09/16 15:39, Kevin Brodsky wrote:
>> On arm and arm64, PSCI is one of the possible firmware interfaces
>> used for power management. This includes both turning CPUs on and off,
>> and suspending them (entering idle states).
>>
>> This patch adds a PSCI checker module that enables basic testing of
>> PSCI operations during startup. There are two main tests: CPU
>> hotplugging and suspending.
>>
>> In the hotplug tests, the hotplug API is used to turn off and on again
>> all CPUs in the system, and then all CPUs in each cluster, checking
>> the consistency of the return codes.
>>
>> In the suspend tests, a high-priority thread is created on each core
>> and uses low-level cpuidle functionalities to enter suspend, in all
>> the possible states and multiple times. This should allow a maximum
>> number of CPUs to enter the same sleep state at the same or slightly
>> different time.
>>
>> In essence, the suspend tests use a principle similar to that of the
>> intel_powerclamp driver (drivers/thermal/intel_powerclamp.c), but the
>> threads are only kept for the duration of the test (they are already
>> gone when userspace is started).
>>
>> While in theory power management PSCI functions (CPU_{ON,OFF,SUSPEND})
>> could be directly called, this proved too difficult as it would imply
>> the duplication of all the logic used by the kernel to allow for a
>> clean shutdown/bringup/suspend of the CPU (the deepest sleep states
>> implying potentially the shutdown of the CPU).
>>
>> Note that this file cannot be compiled as a loadable module, since it
>> uses a number of non-exported identifiers (essentially for
>> PSCI-specific checks and direct use of cpuidle) and relies on the
>> absence of userspace to avoid races when calling hotplug and cpuidle
>> functions.
>>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Kevin Hilman <khilman@kernel.org>
>> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
>> Cc: Peter Zijlstra <peterz@infradead.org>
>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
>> ---
>> Changelog v1..v2:
>> * Do not count tick_broadcast_enter() failures as errors, as they may
>> be unavoidable. When it happens, fall back to WFI.
>> * Do not count unexpected sleep states as errors (currently, the only
>> case is when falling back to WFI). Instead, report the number of
>> times it happens before the suspend thread exits.
>> * Use usecs_to_jiffies() to compute the suspend timeout. The previous
>> version resulted in a zero timeout if the target residency was
>> shorter than a jiffy.
>> * Various cleanup.
>>
>> Thanks to Lorenzo for his help with improving this patch!
>>
>> Kevin
> [...]
>> +
>> +static int suspend_tests(void)
>> +{
>> + int i, cpu, err = 0;
>> + struct task_struct **threads;
>> + int nb_threads = 0;
>> +
>> + threads = kmalloc_array(nb_available_cpus, sizeof(*threads),
>> + GFP_KERNEL);
>> + if (!threads)
>> + return -ENOMEM;
>> +
>> + for_each_online_cpu(cpu) {
>> + struct task_struct *thread;
>> + /* Check that cpuidle is available on that CPU. */
>> + struct cpuidle_device *dev = per_cpu(cpuidle_devices, cpu);
>> + struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev);
>> +
>> + if (cpuidle_not_available(drv, dev)) {
>> + pr_warn("cpuidle not available on CPU %d, ignoring\n",
>> + cpu);
>> + continue;
>> + }
>> +
>> + thread = kthread_create_on_cpu(suspend_stress_thread,
>> + (void *)(long)cpu, cpu,
>> + "psci_suspend_stress");
>> + if (IS_ERR(thread))
>> + pr_err("Failed to create kthread on CPU %d\n", cpu);
>> + else
>> + threads[nb_threads++] = thread;
>> + }
>> + if (nb_threads < 1) {
>> + kfree(threads);
>> + return -ENODEV;
>> + }
>> +
>> + atomic_set(&nb_active_threads, nb_threads);
>> +
>> + /*
>> + * Stop cpuidle to prevent the idle tasks from entering a deep sleep
>> + * mode, as it might interfere with the suspend threads on other CPUs.
>> + * This does not prevent the suspend threads from using cpuidle (only
>> + * the idle tasks check this status).
>> + */
>> + cpuidle_pause();
>> +
>> + /*
>> + * Unpark the suspend threads. To avoid the main thread being preempted
>> + * before all the threads have been unparked, the suspend threads will
>> + * wait for the completion of suspend_threads_started.
>> + */
>> + for (i = 0; i < nb_threads; ++i)
>> + kthread_unpark(threads[i]);
> Just a heads up: this doesn't work anymore, since a65d4096
> (kthread/smpboot: do not park in kthread_create_on_cpu()), in 4.9-rc1. I
> think that the unpark call could be replaced by wake_up_process. The
> comment of kthread_create_on_cpu is now misleading.
>
> Thanks,
> Jean-Philippe
>
Thanks for the heads-up! I'll rebase on 4.9-rc1 and see what needs to be done.
Thanks,
Kevin
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply
* [PATCH] ARM: dts: rockchip: add i2c-bus subnode to edp
From: Heiko Stübner @ 2016-10-20 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476950845-28242-1-git-send-email-tomeu.vizoso@collabora.com>
Am Donnerstag, 20. Oktober 2016, 10:07:25 schrieb Tomeu Vizoso:
> Add an empty 'i2c-bus' subnode to the edp node just so that the I2C core
> doesn't attemp to parse the 'ports' subnode as containing i2c devices.
>
> This is to avoid spurious failure messages such as:
>
> i2c i2c-6: of_i2c: modalias failure on /dp at ff970000/ports
On the one hand, the edp really has an i2c bus - with its only client the EDID
listening at 0x50 (and maybe 0x30).
On the other hand, adding an empty bus to the (implementation independent)
devicetree just to make the Linux i2c subsystem happy sounds heavily like a
implementation-specific hack, as the edp i2c bus doesn't leak into the outside
world otherwise.
I guess this empty i2c bus not being part of the binding document points
heavily into the implementation-specific corner :-) .
My short search on other patches touching this didn't reveal anything but
maybe this was already discussed somewhere and found to be ok?
Another option could be to just make of_i2c_register_device silent if
of_modalias_node returns -ENODEV?
Heiko
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Cc: Randy Li <randy.li@rock-chips.com>
> Cc: Jon Hunter <jonathanh@nvidia.com>
> ---
> arch/arm/boot/dts/rk3288.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 2f814ffeb605..94f4b7eecca2 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -1075,6 +1075,11 @@
> };
> };
> };
> +
> + i2c-bus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> };
>
> hdmi: hdmi at ff980000 {
^ permalink raw reply
* [PATCH v2 4/9] pinctrl: sunxi: Deal with configless pins
From: Maxime Ripard @ 2016-10-20 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdY3+OnQ6Oo_nx+BrWebeTa=kYhHWSzirk1MxfWWJ--0Sg@mail.gmail.com>
Hi Linus,
On Thu, Oct 20, 2016 at 02:52:54PM +0200, Linus Walleij wrote:
> On Wed, Oct 19, 2016 at 2:16 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Tue, Oct 18, 2016 at 03:47:03PM +0800, Chen-Yu Tsai wrote:
> >> > @@ -342,6 +365,8 @@ static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
> >> > struct pinctrl_map *map,
> >> > unsigned num_maps)
> >> > {
> >> > + unsigned long *pinconfig;
> >>
> >> This looks out of place and context?
> >
> > Yeah, sorry, it's just a leftover from the previous version. This has
> > been removed.
>
> Do you mean you will send a v3 of this series?
Yes, I was waiting for your input to do that, but I guess you're ok
with it :)
> OK stopping to apply then.
>
> But I have already applied patches 1, 2 and 3 so just resend the rest :)
Ack, I'll send it in a moment.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH] ARM: dts: rockchip: add i2c-bus subnode to edp
From: Tomeu Vizoso @ 2016-10-20 13:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7604646.6yosK0XMNL@diego>
On 10/20/2016 03:45 PM, Heiko St?bner wrote:
> Am Donnerstag, 20. Oktober 2016, 10:07:25 schrieb Tomeu Vizoso:
>> Add an empty 'i2c-bus' subnode to the edp node just so that the I2C core
>> doesn't attemp to parse the 'ports' subnode as containing i2c devices.
>>
>> This is to avoid spurious failure messages such as:
>>
>> i2c i2c-6: of_i2c: modalias failure on /dp at ff970000/ports
>
> On the one hand, the edp really has an i2c bus - with its only client the EDID
> listening at 0x50 (and maybe 0x30).
>
> On the other hand, adding an empty bus to the (implementation independent)
> devicetree just to make the Linux i2c subsystem happy sounds heavily like a
> implementation-specific hack, as the edp i2c bus doesn't leak into the outside
> world otherwise.
>
> I guess this empty i2c bus not being part of the binding document points
> heavily into the implementation-specific corner :-) .
>
> My short search on other patches touching this didn't reveal anything but
> maybe this was already discussed somewhere and found to be ok?
Here it is:
http://www.spinics.net/lists/linux-tegra/msg27862.html
Regards,
Tomeu
> Another option could be to just make of_i2c_register_device silent if
> of_modalias_node returns -ENODEV?
>
>
> Heiko
>
>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>> Cc: Randy Li <randy.li@rock-chips.com>
>> Cc: Jon Hunter <jonathanh@nvidia.com>
>> ---
>> arch/arm/boot/dts/rk3288.dtsi | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
>> index 2f814ffeb605..94f4b7eecca2 100644
>> --- a/arch/arm/boot/dts/rk3288.dtsi
>> +++ b/arch/arm/boot/dts/rk3288.dtsi
>> @@ -1075,6 +1075,11 @@
>> };
>> };
>> };
>> +
>> + i2c-bus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> };
>>
>> hdmi: hdmi at ff980000 {
>
^ permalink raw reply
* [PATCH v3 0/6] pinctrl: sunxi: Generic bindings rework
From: Maxime Ripard @ 2016-10-20 13:49 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patch set reworks the Allwinner pinctrl driver to support the generic
pin configuration and multiplexing bindings.
In the process, we also covered some lasting issues that were found: we
were ignoring the case where no pull-up was set, and while our binding was
saying that the allwinner,drive and allwinner,pull properties were
optional, the code was not able to deal with the case where they were not
present.
Changes from v2:
- Added Rob, Linus and Chen-Yu's acked-by
- Removed unused variable
- Dropped the patches already applied by Linus
Changes from v1:
- Realloced the pinctrl_map array
- Detailed the generic properties we support
- Directly return the parsing functions return code
- Called kfree on the pinconfig directly
- Added Chen-Yu Acked-by
- Changed the patch 2 commit log as suggested
Maxime Ripard (6):
pinctrl: sunxi: Deal with configless pins
pinctrl: sunxi: Support generic binding
dt-bindings: pinctrl: Deprecate sunxi pinctrl bindings
ARM: sunxi: Remove useless allwinner,drive property
ARM: sunxi: Remove useless allwinner,pull property
ARM: sunxi: Convert pinctrl nodes to generic bindings
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 16 ++++-
arch/arm/boot/dts/ntc-gr8-evb.dts | 24 ++----
arch/arm/boot/dts/ntc-gr8.dtsi | 104 +++++++++------------------
arch/arm/boot/dts/sun4i-a10-a1000.dts | 12 +--
arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 14 +---
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 14 +---
arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 38 +++-------
arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 6 +--
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 12 +--
arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 16 +---
arch/arm/boot/dts/sun4i-a10-inet1.dts | 26 ++-----
arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 14 +---
arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 29 +++-----
arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 12 +--
arch/arm/boot/dts/sun4i-a10-marsboard.dts | 13 +--
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-mk802.dts | 18 +----
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 27 ++-----
arch/arm/boot/dts/sun4i-a10-pcduino.dts | 19 +----
arch/arm/boot/dts/sun4i-a10-pcduino2.dts | 6 +--
arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 32 +++-----
arch/arm/boot/dts/sun4i-a10.dtsi | 169 +++++++++++++++-----------------------------
arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 18 ++---
arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 29 +++-----
arch/arm/boot/dts/sun5i-a10s-mk802.dts | 19 +----
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 36 +++------
arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 20 ++---
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 21 +----
arch/arm/boot/dts/sun5i-a10s.dtsi | 61 ++++++----------
arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 23 ++----
arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 22 ++----
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 40 ++++------
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 36 +++------
arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 17 +---
arch/arm/boot/dts/sun5i-a13.dtsi | 24 ++----
arch/arm/boot/dts/sun5i-r8-chip.dts | 12 +--
arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 33 +++------
arch/arm/boot/dts/sun5i.dtsi | 57 +++++----------
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 6 +--
arch/arm/boot/dts/sun6i-a31-colombus.dts | 22 ++----
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 23 ++----
arch/arm/boot/dts/sun6i-a31-i7.dts | 19 +----
arch/arm/boot/dts/sun6i-a31-m9.dts | 19 +----
arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 19 +----
arch/arm/boot/dts/sun6i-a31.dtsi | 136 ++++++++++++++---------------------
arch/arm/boot/dts/sun6i-a31s-primo81.dts | 20 ++---
arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 13 +--
arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 29 +++-----
arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 9 +--
arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi | 14 +---
arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 27 ++-----
arch/arm/boot/dts/sun7i-a20-bananapi.dts | 26 ++-----
arch/arm/boot/dts/sun7i-a20-bananapro.dts | 37 +++-------
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 13 +--
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 38 +++-------
arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 24 ++----
arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 26 ++-----
arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 7 +--
arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 30 +++-----
arch/arm/boot/dts/sun7i-a20-m3.dts | 6 +--
arch/arm/boot/dts/sun7i-a20-mk808c.dts | 12 +--
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 32 +++-----
arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 27 ++-----
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 6 +--
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 33 +++------
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 28 +++----
arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 45 ++++--------
arch/arm/boot/dts/sun7i-a20-orangepi.dts | 38 +++-------
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 25 ++----
arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 21 +----
arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 25 ++----
arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 13 +--
arch/arm/boot/dts/sun7i-a20.dtsi | 277 ++++++++++++++++++++++++++----------------------------------------------
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 95 ++++++++++---------------
arch/arm/boot/dts/sun8i-a23-evb.dts | 7 +--
arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 8 +--
arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 8 +--
arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 9 +--
arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 18 +----
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 11 +--
arch/arm/boot/dts/sun8i-a33.dtsi | 6 +--
arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +----
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 18 +----
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 12 +--
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 26 ++-----
arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 18 +----
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 18 +----
arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 4 +-
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 18 +----
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 10 +--
arch/arm/boot/dts/sun8i-h3.dtsi | 92 +++++++++---------------
arch/arm/boot/dts/sun8i-q8-common.dtsi | 9 +--
arch/arm/boot/dts/sun8i-r16-parrot.dts | 36 +++------
arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 26 ++-----
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 15 +---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 33 +++------
arch/arm/boot/dts/sun9i-a80.dtsi | 54 +++++---------
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 24 ++----
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 99 +++++++++++++++++++++-----
100 files changed, 1176 insertions(+), 1757 deletions(-)
--
git-series 0.8.10
^ permalink raw reply
* [PATCH v3 1/6] pinctrl: sunxi: Deal with configless pins
From: Maxime Ripard @ 2016-10-20 13:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.f893b02a9f816dad8fad3986672b05c4b211e2b1.1476971126.git-series.maxime.ripard@free-electrons.com>
Even though the our binding had the assumption that the allwinner,pull and
allwinner,drive properties were optional, the code never took that into
account.
Fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 51 ++++++++++++++++++++--------
1 file changed, 37 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index c44bf1320e08..12650904bd96 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -217,20 +217,29 @@ static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
{
unsigned long *pinconfig;
unsigned int configlen = 0, idx = 0;
+ int ret;
if (sunxi_pctrl_has_drive_prop(node))
configlen++;
if (sunxi_pctrl_has_bias_prop(node))
configlen++;
+ /*
+ * If we don't have any configuration, bail out
+ */
+ if (!configlen)
+ return NULL;
+
pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
if (!pinconfig)
- return NULL;
+ return ERR_PTR(-ENOMEM);
if (sunxi_pctrl_has_drive_prop(node)) {
int drive = sunxi_pctrl_parse_drive_prop(node);
- if (drive < 0)
+ if (drive < 0) {
+ ret = drive;
goto err_free;
+ }
pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
drive);
@@ -238,8 +247,10 @@ static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
if (sunxi_pctrl_has_bias_prop(node)) {
int pull = sunxi_pctrl_parse_bias_prop(node);
- if (pull < 0)
+ if (pull < 0) {
+ ret = pull;
goto err_free;
+ }
pinconfig[idx++] = pinconf_to_config_packed(pull, 0);
}
@@ -250,7 +261,7 @@ static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
err_free:
kfree(pinconfig);
- return NULL;
+ return ERR_PTR(ret);
}
static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
@@ -284,7 +295,10 @@ static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
/*
* We have two maps for each pin: one for the function, one
- * for the configuration (bias, strength, etc)
+ * for the configuration (bias, strength, etc).
+ *
+ * We might be slightly overshooting, since we might not have
+ * any configuration.
*/
nmaps = npins * 2;
*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
@@ -292,8 +306,8 @@ static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
return -ENOMEM;
pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
- if (!pinconfig) {
- ret = -EINVAL;
+ if (IS_ERR(pinconfig)) {
+ ret = PTR_ERR(pinconfig);
goto err_free_map;
}
@@ -320,15 +334,24 @@ static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
i++;
- (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
- (*map)[i].data.configs.group_or_pin = group;
- (*map)[i].data.configs.configs = pinconfig;
- (*map)[i].data.configs.num_configs = configlen;
-
- i++;
+ if (pinconfig) {
+ (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+ (*map)[i].data.configs.group_or_pin = group;
+ (*map)[i].data.configs.configs = pinconfig;
+ (*map)[i].data.configs.num_configs = configlen;
+ i++;
+ }
}
- *num_maps = nmaps;
+ *num_maps = i;
+
+ /*
+ * We know have the number of maps we need, we can resize our
+ * map array
+ */
+ *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
+ if (!map)
+ return -ENOMEM;
return 0;
--
git-series 0.8.10
^ permalink raw reply related
* [PATCH v3 2/6] pinctrl: sunxi: Support generic binding
From: Maxime Ripard @ 2016-10-20 13:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.f893b02a9f816dad8fad3986672b05c4b211e2b1.1476971126.git-series.maxime.ripard@free-electrons.com>
Our bindings are mostly irrelevant now that we have generic pinctrl
bindings that cover exactly the same uses cases.
Add support for the new ones, and obviously keep our old binding support in
order to keep the ABI stable.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 48 ++++++++++++++++++++++++++--
1 file changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 12650904bd96..ebe2c73d211e 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -149,18 +149,33 @@ static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
{
- return of_find_property(node, "allwinner,pull", NULL);
+ return of_find_property(node, "bias-pull-up", NULL) ||
+ of_find_property(node, "bias-pull-down", NULL) ||
+ of_find_property(node, "bias-disable", NULL) ||
+ of_find_property(node, "allwinner,pull", NULL);
}
static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
{
- return of_find_property(node, "allwinner,drive", NULL);
+ return of_find_property(node, "drive-strength", NULL) ||
+ of_find_property(node, "allwinner,drive", NULL);
}
static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
{
u32 val;
+ /* Try the new style binding */
+ if (of_find_property(node, "bias-pull-up", NULL))
+ return PIN_CONFIG_BIAS_PULL_UP;
+
+ if (of_find_property(node, "bias-pull-down", NULL))
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+
+ if (of_find_property(node, "bias-disable", NULL))
+ return PIN_CONFIG_BIAS_DISABLE;
+
+ /* And fall back to the old binding */
if (of_property_read_u32(node, "allwinner,pull", &val))
return -EINVAL;
@@ -180,6 +195,21 @@ static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
{
u32 val;
+ /* Try the new style binding */
+ if (!of_property_read_u32(node, "drive-strength", &val)) {
+ /* We can't go below 10mA ... */
+ if (val < 10)
+ return -EINVAL;
+
+ /* ... and only up to 40 mA ... */
+ if (val > 40)
+ val = 40;
+
+ /* by steps of 10 mA */
+ return rounddown(val, 10);
+ }
+
+ /* And then fall back to the old binding */
if (of_property_read_u32(node, "allwinner,drive", &val))
return -EINVAL;
@@ -191,6 +221,12 @@ static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
const char *function;
int ret;
+ /* Try the generic binding */
+ ret = of_property_read_string(node, "function", &function);
+ if (!ret)
+ return function;
+
+ /* And fall back to our legacy one */
ret = of_property_read_string(node, "allwinner,function", &function);
if (!ret)
return function;
@@ -203,6 +239,14 @@ static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
{
int count;
+ /* Try the generic binding */
+ count = of_property_count_strings(node, "pins");
+ if (count > 0) {
+ *npins = count;
+ return "pins";
+ }
+
+ /* And fall back to our legacy one */
count = of_property_count_strings(node, "allwinner,pins");
if (count > 0) {
*npins = count;
--
git-series 0.8.10
^ permalink raw reply related
* [PATCH v3 3/6] dt-bindings: pinctrl: Deprecate sunxi pinctrl bindings
From: Maxime Ripard @ 2016-10-20 13:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.f893b02a9f816dad8fad3986672b05c4b211e2b1.1476971126.git-series.maxime.ripard@free-electrons.com>
The generic pin configuration and multiplexing should be preferred now,
even though we still support the old one.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 1685821eea41..35eef433e518 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -37,6 +37,22 @@ pins it needs, and how they should be configured, with regard to muxer
configuration, drive strength and pullups. If one of these options is
not set, its actual value will be unspecified.
+This driver supports the generic pin multiplexing and configuration
+bindings. For details on each properties, you can refer to
+./pinctrl-bindings.txt.
+
+Required sub-node properties:
+ - pins
+ - function
+
+Optional sub-node properties:
+ - bias-disable
+ - bias-pull-up
+ - bias-pull-down
+ - drive-strength
+
+*** Deprecated pin configuration and multiplexing binding
+
Required subnode-properties:
- allwinner,pins: List of strings containing the pin name.
--
git-series 0.8.10
^ permalink raw reply related
* [PATCH v3 5/6] ARM: sunxi: Remove useless allwinner,pull property
From: Maxime Ripard @ 2016-10-20 13:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.f893b02a9f816dad8fad3986672b05c4b211e2b1.1476971126.git-series.maxime.ripard@free-electrons.com>
The allwinner,pull property set to NO_PULL was really considered our
default (and wasn't even changing the default value in the code).
Remove these properties to make it obvious that we do not set anything in
such a case.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ntc-gr8-evb.dts | 4 +-
arch/arm/boot/dts/ntc-gr8.dtsi | 14 +-----
arch/arm/boot/dts/sun4i-a10-a1000.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 1 +-
arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 4 +-
arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 1 +-
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-inet1.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-marsboard.dts | 1 +-
arch/arm/boot/dts/sun4i-a10-mk802.dts | 3 +-
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-pcduino.dts | 2 +-
arch/arm/boot/dts/sun4i-a10-pcduino2.dts | 1 +-
arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 3 +-
arch/arm/boot/dts/sun4i-a10.dtsi | 24 +--------
arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 1 +-
arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s-mk802.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 2 +-
arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +--
arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 1 +-
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 3 +-
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 2 +-
arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 1 +-
arch/arm/boot/dts/sun5i-a13.dtsi | 3 +-
arch/arm/boot/dts/sun5i-r8-chip.dts | 2 +-
arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 2 +-
arch/arm/boot/dts/sun5i.dtsi | 7 +--
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 1 +-
arch/arm/boot/dts/sun6i-a31-colombus.dts | 1 +-
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +-
arch/arm/boot/dts/sun6i-a31-i7.dts | 2 +-
arch/arm/boot/dts/sun6i-a31-m9.dts | 2 +-
arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 +-
arch/arm/boot/dts/sun6i-a31.dtsi | 13 +----
arch/arm/boot/dts/sun6i-a31s-primo81.dts | 1 +-
arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 1 +-
arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 3 +-
arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 3 +-
arch/arm/boot/dts/sun7i-a20-bananapi.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-bananapro.dts | 5 +--
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 1 +-
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 6 +--
arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 4 +-
arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 4 +-
arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 1 +-
arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-m3.dts | 1 +-
arch/arm/boot/dts/sun7i-a20-mk808c.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 4 +-
arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 1 +-
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 3 +-
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 1 +-
arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 4 +-
arch/arm/boot/dts/sun7i-a20-orangepi.dts | 4 +-
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 3 +-
arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 2 +-
arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 3 +-
arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 1 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 37 +------------
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 10 +---
arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 1 +-
arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 1 +-
arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 1 +-
arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 3 +-
arch/arm/boot/dts/sun8i-a33.dtsi | 1 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 3 +-
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 3 +-
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 2 +-
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 +-
arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 3 +-
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 3 +-
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 +-
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 1 +-
arch/arm/boot/dts/sun8i-h3.dtsi | 12 +----
arch/arm/boot/dts/sun8i-r16-parrot.dts | 3 +-
arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 1 +-
arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 6 +--
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 4 +-
85 files changed, 0 insertions(+), 302 deletions(-)
diff --git a/arch/arm/boot/dts/ntc-gr8-evb.dts b/arch/arm/boot/dts/ntc-gr8-evb.dts
index 04a474471adc..5a97dea32f98 100644
--- a/arch/arm/boot/dts/ntc-gr8-evb.dts
+++ b/arch/arm/boot/dts/ntc-gr8-evb.dts
@@ -228,25 +228,21 @@
mmc0_cd_pin_gr8_evb: mmc0-cd-pin at 0 {
allwinner,pins = "PG0";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_pin_gr8_evb: usb0-id-pin at 0 {
allwinner,pins = "PG2";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_vbus_det_pin_gr8_evb: usb0-vbus-det-pin at 0 {
allwinner,pins = "PG1";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb1_vbus_pin_gr8_evb: usb1-vbus-pin at 0 {
allwinner,pins = "PG13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/ntc-gr8.dtsi b/arch/arm/boot/dts/ntc-gr8.dtsi
index d6a499bfd795..1c46cd38d999 100644
--- a/arch/arm/boot/dts/ntc-gr8.dtsi
+++ b/arch/arm/boot/dts/ntc-gr8.dtsi
@@ -766,37 +766,31 @@
i2c0_pins_a: i2c0 at 0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "i2c0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins_a: i2c1 at 0 {
allwinner,pins = "PB15", "PB16";
allwinner,function = "i2c1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins_a: i2c2 at 0 {
allwinner,pins = "PB17", "PB18";
allwinner,function = "i2c2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2s0_data_pins_a: i2s0-data at 0 {
allwinner,pins = "PB6", "PB7", "PB8", "PB9";
allwinner,function = "i2s0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2s0_mclk_pins_a: i2s0-mclk at 0 {
allwinner,pins = "PB6", "PB7", "PB8", "PB9";
allwinner,function = "i2s0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir0_rx_pins_a: ir0 at 0 {
allwinner,pins = "PB4";
allwinner,function = "ir0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
lcd_rgb666_pins: lcd-rgb666 at 0 {
@@ -805,7 +799,6 @@
"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
"PD24", "PD25", "PD26", "PD27";
allwinner,function = "lcd0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins_a: mmc0 at 0 {
@@ -813,7 +806,6 @@
"PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
nand_pins_a: nand-base0 at 0 {
@@ -822,25 +814,21 @@
"PC11", "PC12", "PC13", "PC14",
"PC15";
allwinner,function = "nand0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
nand_cs0_pins_a: nand-cs at 0 {
allwinner,pins = "PC4";
allwinner,function = "nand0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
nand_rb0_pins_a: nand-rb at 0 {
allwinner,pins = "PC6";
allwinner,function = "nand0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
pwm0_pins_a: pwm0 at 0 {
allwinner,pins = "PB2";
allwinner,function = "pwm0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spdif_tx_pins_a: spdif at 0 {
@@ -852,13 +840,11 @@
uart1_pins_a: uart1 at 1 {
allwinner,pins = "PG3", "PG4";
allwinner,function = "uart1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_cts_rts_pins_a: uart1-cts-rts at 0 {
allwinner,pins = "PG5", "PG6";
allwinner,function = "uart1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 035395a32212..4d8164afc671 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -188,13 +188,11 @@
emac_power_pin_a1000: emac_power_pin at 0 {
allwinner,pins = "PH15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_a1000: led_pins at 0 {
allwinner,pins = "PH10", "PH20";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index f11dcd82f468..e7188d2fb303 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -168,7 +168,6 @@
allwinner,pins = "PH20", "PH21";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
index e01bdd1f1b2b..b4b829d6008d 100644
--- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
+++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
@@ -180,25 +180,21 @@
bl_en_pin_dsrv9703c: bl_en_pin at 0 {
allwinner,pins = "PH7";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
codec_pa_pin: codec_pa_pin at 0 {
allwinner,pins = "PH15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
motor_pins: motor_pins at 0 {
allwinner,pins = "PB3";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
touchscreen_pins: touchscreen_pins at 0 {
allwinner,pins = "PB13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
index fbd02c7a5d43..57496a38b94a 100644
--- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
+++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
@@ -158,7 +158,6 @@
codec_pa_pin: codec_pa_pin at 0 {
allwinner,pins = "PH15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 9b8134cb968d..de10ae48c6f6 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -131,13 +131,11 @@
hackberry_hogs: hogs at 0 {
allwinner,pins = "PH19";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb2_vbus_pin_hackberry: usb2_vbus_pin at 0 {
allwinner,pins = "PH12";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts
index bb64e466c4e0..f78c17a9a298 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet1.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts
@@ -182,13 +182,11 @@
bl_en_pin_inet: bl_en_pin at 0 {
allwinner,pins = "PH7";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
touchscreen_wake_pin: touchscreen_wake_pin at 0 {
allwinner,pins = "PB13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
index 65273bc7998c..e6ffaefed42d 100644
--- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
+++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
@@ -165,13 +165,11 @@
emac_power_pin_q5: emac_power_pin at 0 {
allwinner,pins = "PH19";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_q5: led_pins at 0 {
allwinner,pins = "PH20";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
index c5916125bea8..001656eb9171 100644
--- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
@@ -166,7 +166,6 @@
led_pins_marsboard: led_pins at 0 {
allwinner,pins = "PB5", "PB6", "PB7", "PB8";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts
index 204e2b68d09f..9ce39f75188e 100644
--- a/arch/arm/boot/dts/sun4i-a10-mk802.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts
@@ -93,19 +93,16 @@
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin at 0 {
allwinner,pins = "PH5";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb2_vbus_pin_mk802: usb2_vbus_pin at 0 {
allwinner,pins = "PH12";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index e8e14a53b764..203d399f0f7b 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -170,14 +170,12 @@
ahci_pwr_pin_olinuxinolime: ahci_pwr_pin at 1 {
allwinner,pins = "PC3";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_olinuxinolime: led_pins at 0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 7e94334420af..94cdef53ac11 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -172,13 +172,11 @@
led_pins_pcduino: led_pins at 0 {
allwinner,pins = "PH15", "PH16";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
key_pins_pcduino: key_pins at 0 {
allwinner,pins = "PH17", "PH18", "PH19";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts b/arch/arm/boot/dts/sun4i-a10-pcduino2.dts
index 05de4050a831..9656ec9b51ae 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino2.dts
@@ -59,7 +59,6 @@
usb2_vbus_pin_pcduino2: usb2_vbus_pin at 0 {
allwinner,pins = "PD2";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
index 459c7a2dbee7..9dedd808bde8 100644
--- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
@@ -166,19 +166,16 @@
bl_en_pin_protab: bl_en_pin at 0 {
allwinner,pins = "PH7";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
codec_pa_pin: codec_pa_pin at 0 {
allwinner,pins = "PH15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
touchscreen_pins: touchscreen_pins at 0 {
allwinner,pins = "PA5", "PB13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ae562272589c..36f3416c4c32 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -980,49 +980,41 @@
"PA11", "PA12", "PA13", "PA14",
"PA15", "PA16";
allwinner,function = "emac";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c0_pins_a: i2c0 at 0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "i2c0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins_a: i2c1 at 0 {
allwinner,pins = "PB18", "PB19";
allwinner,function = "i2c1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins_a: i2c2 at 0 {
allwinner,pins = "PB20", "PB21";
allwinner,function = "i2c2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir0_rx_pins_a: ir0 at 0 {
allwinner,pins = "PB4";
allwinner,function = "ir0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir0_tx_pins_a: ir0 at 1 {
allwinner,pins = "PB3";
allwinner,function = "ir0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir1_rx_pins_a: ir1 at 0 {
allwinner,pins = "PB23";
allwinner,function = "ir1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir1_tx_pins_a: ir1 at 1 {
allwinner,pins = "PB22";
allwinner,function = "ir1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins_a: mmc0 at 0 {
@@ -1030,7 +1022,6 @@
"PF3", "PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
@@ -1042,25 +1033,21 @@
ps20_pins_a: ps20 at 0 {
allwinner,pins = "PI20", "PI21";
allwinner,function = "ps2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ps21_pins_a: ps21 at 0 {
allwinner,pins = "PH12", "PH13";
allwinner,function = "ps2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
pwm0_pins_a: pwm0 at 0 {
allwinner,pins = "PB2";
allwinner,function = "pwm";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
pwm1_pins_a: pwm1 at 0 {
allwinner,pins = "PI3";
allwinner,function = "pwm";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spdif_tx_pins_a: spdif at 0 {
@@ -1072,67 +1059,56 @@
spi0_pins_a: spi0 at 0 {
allwinner,pins = "PI11", "PI12", "PI13";
allwinner,function = "spi0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi0_cs0_pins_a: spi0_cs0 at 0 {
allwinner,pins = "PI10";
allwinner,function = "spi0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi1_pins_a: spi1 at 0 {
allwinner,pins = "PI17", "PI18", "PI19";
allwinner,function = "spi1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi1_cs0_pins_a: spi1_cs0 at 0 {
allwinner,pins = "PI16";
allwinner,function = "spi1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_pins_a: spi2 at 0 {
allwinner,pins = "PC20", "PC21", "PC22";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_pins_b: spi2 at 1 {
allwinner,pins = "PB15", "PB16", "PB17";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_cs0_pins_a: spi2_cs0 at 0 {
allwinner,pins = "PC19";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_cs0_pins_b: spi2_cs0 at 1 {
allwinner,pins = "PB14";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart0_pins_a: uart0 at 0 {
allwinner,pins = "PB22", "PB23";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart0_pins_b: uart0 at 1 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_pins_a: uart1 at 0 {
allwinner,pins = "PA10", "PA11";
allwinner,function = "uart1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
index 813e18c011da..8d1e414c0a3a 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
@@ -118,7 +118,6 @@
allwinner,pins = "PB2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
index 3c79e3536521..e3438a685c71 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
@@ -144,14 +144,12 @@
mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin at 0 {
allwinner,pins = "PB18";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_t004: led_pins at 0 {
allwinner,pins = "PB2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
index 940139145fd5..405c1d519301 100644
--- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
@@ -118,7 +118,6 @@
led_pins_mk802: led_pins at 0 {
allwinner,pins = "PB2";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_mk802: mmc0_cd_pin at 0 {
@@ -130,7 +129,6 @@
usb1_vbus_pin_mk802: usb1_vbus_pin at 0 {
allwinner,pins = "PB10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 26d74958bd57..125243305525 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -217,13 +217,11 @@
allwinner,pins = "PE3";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb1_vbus_pin_olinuxino_m: usb1_vbus_pin at 0 {
allwinner,pins = "PB10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
index 84a3bf817c3b..e2dceda4889b 100644
--- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -110,13 +110,11 @@
allwinner,pins = "PB2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb1_vbus_pin_r7: usb1_vbus_pin at 0 {
allwinner,pins = "PG13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
index 56a6982773a9..f40451bffb84 100644
--- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
@@ -148,7 +148,6 @@
led_pins_wobo_i5: led_pins at 0 {
allwinner,pins = "PB2";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_wobo_i5: mmc0_cd_pin at 0 {
@@ -160,7 +159,6 @@
emac_power_pin_wobo: emac_power_pin at 0 {
allwinner,pins = "PA02";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 9aa80630e00f..4e014cb11e81 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -202,13 +202,11 @@
uart0_pins_a: uart0 at 0 {
allwinner,pins = "PB19", "PB20";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart2_pins_a: uart2 at 0 {
allwinner,pins = "PC18", "PC19";
allwinner,function = "uart2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
emac_pins_a: emac0 at 0 {
@@ -218,7 +216,6 @@
"PA11", "PA12", "PA13", "PA14",
"PA15", "PA16";
allwinner,function = "emac";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
emac_pins_b: emac0 at 1 {
@@ -228,7 +225,6 @@
"PD21", "PD22", "PD23", "PD24",
"PD25", "PD26", "PD27";
allwinner,function = "emac";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc1_pins_a: mmc1 at 0 {
@@ -236,19 +232,16 @@
"PG6", "PG7", "PG8";
allwinner,function = "mmc1";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_pins_a: spi2 at 0 {
allwinner,pins = "PB12", "PB13", "PB14";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_cs0_pins_a: spi2_cs0 at 0 {
allwinner,pins = "PB11";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index aa4484ac50b2..f5d1a04f3a16 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -150,7 +150,6 @@
usb0_vbus_detect_pin: usb0_vbus_detect_pin at 0 {
allwinner,pins = "PG1";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index 8aec90ac28a4..df9315e5c850 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -124,7 +124,6 @@
allwinner,pins = "PG9";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
@@ -142,13 +141,11 @@
usb0_vbus_pin_olinuxinom: usb0_vbus_pin at 0 {
allwinner,pins = "PG12";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb1_vbus_pin_olinuxinom: usb1_vbus_pin at 0 {
allwinner,pins = "PG11";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 86ae19ba70d4..0f035adfbc57 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -174,7 +174,6 @@
allwinner,pins = "PG9";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
@@ -192,7 +191,6 @@
usb1_vbus_pin_olinuxino: usb1_vbus_pin at 0 {
allwinner,pins = "PG11";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
index 663cfa414dc2..3b7f2097824d 100644
--- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
+++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
@@ -124,7 +124,6 @@
ts_wake_pin_p66: ts_wake_pin at 0 {
allwinner,pins = "PB3";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index d79db1525448..1f4c5f773226 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -355,18 +355,15 @@
"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
"PD24", "PD25", "PD26", "PD27";
allwinner,function = "lcd0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_pins_a: uart1 at 0 {
allwinner,pins = "PE10", "PE11";
allwinner,function = "uart1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_pins_b: uart1 at 1 {
allwinner,pins = "PG3", "PG4";
allwinner,function = "uart1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index 398a17a5d2e6..8f7f01bf1f0c 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -152,13 +152,11 @@
chip_vbus_pin: chip_vbus_pin at 0 {
allwinner,pins = "PB10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
chip_id_det_pin: chip_id_det_pin at 0 {
allwinner,pins = "PG2";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
index 600bd3c0e231..b29c4d1fad40 100644
--- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
@@ -114,7 +114,6 @@
codec_pa_pin: codec_pa_pin at 0 {
allwinner,pins = "PG10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin: mmc0_cd_pin at 0 {
@@ -138,7 +137,6 @@
usb0_vbus_pin_a: usb0_vbus_pin at 0 {
allwinner,pins = "PG12";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index fe84703d3c14..76b696944514 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -556,19 +556,16 @@
i2c0_pins_a: i2c0 at 0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "i2c0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins_a: i2c1 at 0 {
allwinner,pins = "PB15", "PB16";
allwinner,function = "i2c1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins_a: i2c2 at 0 {
allwinner,pins = "PB17", "PB18";
allwinner,function = "i2c2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins_a: mmc0 at 0 {
@@ -576,7 +573,6 @@
"PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc2_pins_a: mmc2 at 0 {
@@ -591,19 +587,16 @@
uart3_pins_a: uart3 at 0 {
allwinner,pins = "PG9", "PG10";
allwinner,function = "uart3";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart3_pins_cts_rts_a: uart3-cts-rts at 0 {
allwinner,pins = "PG11", "PG12";
allwinner,function = "uart3";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
pwm0_pins: pwm0 {
allwinner,pins = "PB2";
allwinner,function = "pwm";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
index e723dedeb614..cbc99ce6ab1a 100644
--- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
+++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
@@ -70,7 +70,6 @@
usb1_vbus_pin_a: usb1_vbus_pin at 0 {
allwinner,pins = "PH27";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 4057e91c7cb5..24909c8c1186 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -137,7 +137,6 @@
usb2_vbus_pin_colombus: usb2_vbus_pin at 0 {
allwinner,pins = "PH24";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c_lcd_pins: i2c_lcd_pin at 0 {
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index a82c4674a3fc..7ec5f5fcdaac 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -155,7 +155,6 @@
gmac_phy_reset_pin_hummingbird: gmac_phy_reset_pin at 0 {
allwinner,pins = "PA21";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_hummingbird: mmc0_cd_pin at 0 {
@@ -167,7 +166,6 @@
wifi_reset_pin_hummingbird: wifi_reset_pin at 0 {
allwinner,pins = "PG10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts
index a2d6a92dac29..61e3ef4528ec 100644
--- a/arch/arm/boot/dts/sun6i-a31-i7.dts
+++ b/arch/arm/boot/dts/sun6i-a31-i7.dts
@@ -111,7 +111,6 @@
led_pins_i7: led_pins at 0 {
allwinner,pins = "PH13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_i7: mmc0_cd_pin at 0 {
@@ -123,7 +122,6 @@
usb1_vbus_pin_i7: usb1_vbus_pin at 0 {
allwinner,pins = "PC27";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index 0ae5ab2f06fa..96ad1fe9bbc8 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -130,7 +130,6 @@
led_pins_m9: led_pins at 0 {
allwinner,pins = "PH13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_m9: mmc0_cd_pin at 0 {
@@ -142,7 +141,6 @@
usb1_vbus_pin_m9: usb1_vbus_pin at 0 {
allwinner,pins = "PC27";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
index a551673aca68..a29ea186b964 100644
--- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
+++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
@@ -130,7 +130,6 @@
led_pins_m9: led_pins at 0 {
allwinner,pins = "PH13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_m9: mmc0_cd_pin at 0 {
@@ -142,7 +141,6 @@
usb1_vbus_pin_m9: usb1_vbus_pin at 0 {
allwinner,pins = "PC27";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 19ccf7a89759..1a00c67cc1b6 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -437,25 +437,21 @@
uart0_pins_a: uart0 at 0 {
allwinner,pins = "PH20", "PH21";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c0_pins_a: i2c0 at 0 {
allwinner,pins = "PH14", "PH15";
allwinner,function = "i2c0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins_a: i2c1 at 0 {
allwinner,pins = "PH16", "PH17";
allwinner,function = "i2c1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins_a: i2c2 at 0 {
allwinner,pins = "PH18", "PH19";
allwinner,function = "i2c2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins_a: mmc0 at 0 {
@@ -463,7 +459,6 @@
"PF3", "PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc1_pins_a: mmc1 at 0 {
@@ -471,7 +466,6 @@
"PG4", "PG5";
allwinner,function = "mmc1";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc2_pins_a: mmc2 at 0 {
@@ -489,7 +483,6 @@
"PC24";
allwinner,function = "mmc2";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc3_8bit_emmc_pins: mmc3 at 1 {
@@ -499,7 +492,6 @@
"PC24";
allwinner,function = "mmc3";
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_pins_mii_a: gmac_mii at 0 {
@@ -509,7 +501,6 @@
"PA20", "PA21", "PA22", "PA23",
"PA24", "PA26", "PA27";
allwinner,function = "gmac";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_pins_gmii_a: gmac_gmii at 0 {
@@ -526,7 +517,6 @@
* might need a higher signal drive strength
*/
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_pins_rgmii_a: gmac_rgmii at 0 {
@@ -540,7 +530,6 @@
* and need a higher signal drive strength
*/
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -892,13 +881,11 @@
ir_pins_a: ir at 0 {
allwinner,pins = "PL4";
allwinner,function = "s_ir";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
p2wi_pins: p2wi {
allwinner,pins = "PL0", "PL1";
allwinner,function = "s_p2wi";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
index 4332cde8d6ca..f511aa0e250d 100644
--- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
@@ -136,7 +136,6 @@
gt911_int_primo81: gt911_int_pin at 0 {
allwinner,pins = "PA3";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mma8452_int_primo81: mma8452_int_pin at 0 {
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index d0304f51a5c6..2beb867d095a 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
@@ -130,7 +130,6 @@
led_pin_sina31s: led_pin at 0 {
allwinner,pins = "PH13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_sina31s: mmc0_cd_pin at 0 {
diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 83e47a1c93bd..3731cf22abc1 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -155,13 +155,11 @@
gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin at 0 {
allwinner,pins = "PA21";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_bpi_m2: led_pins at 0 {
allwinner,pins = "PG5", "PG10", "PG11";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_bpi_m2: mmc0_cd_pin at 0 {
@@ -175,7 +173,6 @@
mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin at 0 {
allwinner,pins = "PL8";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
index e10630e59c05..2018f074ff05 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -196,13 +196,11 @@
gmac_power_pin_bpi_m1p: gmac_power_pin at 0 {
allwinner,pins = "PH23";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_bpi_m1p: led_pins at 0 {
allwinner,pins = "PH24", "PH25";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_bpi_m1p: mmc0_cd_pin at 0 {
@@ -214,7 +212,6 @@
mmc3_pwrseq_pin_bpi_m1p: mmc3_pwrseq_pin at 0 {
allwinner,pins = "PH22";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index 158ab889dce7..7cd6a74d104c 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -193,13 +193,11 @@
gmac_power_pin_bananapi: gmac_power_pin at 0 {
allwinner,pins = "PH23";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_bananapi: led_pins at 0 {
allwinner,pins = "PH24";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts
index 4aaf137376de..366636451e7e 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts
@@ -184,13 +184,11 @@
gmac_power_pin_bananapro: gmac_power_pin at 0 {
allwinner,pins = "PH23";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_bananapro: led_pins at 0 {
allwinner,pins = "PH24", "PG2";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_bananapro: mmc0_cd_pin at 0 {
@@ -202,19 +200,16 @@
usb1_vbus_pin_bananapro: usb1_vbus_pin at 0 {
allwinner,pins = "PH0";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb2_vbus_pin_bananapro: usb2_vbus_pin at 0 {
allwinner,pins = "PH1";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
vmmc3_pin_bananapro: vmmc3_pin at 0 {
allwinner,pins = "PH22";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 42779aeb7297..e635dd6ac47d 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -162,7 +162,6 @@
led_pins_cubieboard2: led_pins at 0 {
allwinner,pins = "PH20", "PH21";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index a0b7ffb6196d..be8fa4879453 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -226,37 +226,31 @@
ahci_pwr_pin_cubietruck: ahci_pwr_pin at 1 {
allwinner,pins = "PH12";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_cubietruck: led_pins at 0 {
allwinner,pins = "PH7", "PH11", "PH20", "PH21";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc3_pwrseq_pin_cubietruck: mmc3_pwrseq_pin at 0 {
allwinner,pins = "PH9";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_vbus_pin_a: usb0_vbus_pin at 0 {
allwinner,pins = "PH17";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
allwinner,pins = "PH19";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin at 0 {
allwinner,pins = "PH22";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
index 714a463e24ed..6719c701a45f 100644
--- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
+++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
@@ -190,25 +190,21 @@
ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin at 0 {
allwinner,pins = "PH15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin at 0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin at 0 {
allwinner,pins = "PH9";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin at 0 {
allwinner,pins = "PH16";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index 4d1e102ea4b9..d64c11134dd7 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -200,25 +200,21 @@
vmmc3_pin_i12_tvbox: vmmc3_pin at 0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
vmmc3_io_pin_i12_tvbox: vmmc3_io_pin at 0 {
allwinner,pins = "PH12";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_power_pin_i12_tvbox: gmac_power_pin at 0 {
allwinner,pins = "PH21";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_i12_tvbox: led_pins at 0 {
allwinner,pins = "PH9", "PH20";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
index 10d48cbf81ff..44f09642c893 100644
--- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
@@ -134,7 +134,6 @@
allwinner,pins = "PH20","PH21";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
index 57c05e69d012..79cee00a85de 100644
--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -236,13 +236,11 @@
gmac_power_pin_lamobo_r1: gmac_power_pin at 0 {
allwinner,pins = "PH23";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_lamobo_r1: led_pins at 0 {
allwinner,pins = "PH24";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts
index cfaa5b45b159..97ce27da445f 100644
--- a/arch/arm/boot/dts/sun7i-a20-m3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
@@ -147,7 +147,6 @@
led_pins_m3: led_pins at 0 {
allwinner,pins = "PH20";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
index edd397d796be..c5890617382c 100644
--- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts
+++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
@@ -134,13 +134,11 @@
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin at 0 {
allwinner,pins = "PH5";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
index edf735c10b63..de2863651b44 100644
--- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
@@ -206,14 +206,12 @@
ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin at 1 {
allwinner,pins = "PC3";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_olimex_som_evb: led_pins at 0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc3_cd_pin_olimex_som_evb: mmc3_cd_pin at 0 {
@@ -225,13 +223,11 @@
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin at 0 {
allwinner,pins = "PH5";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index 632ad580e09f..21946497789e 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -155,14 +155,12 @@
ahci_pwr_pin_olinuxinolime: ahci_pwr_pin at 1 {
allwinner,pins = "PC3";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_olinuxinolime: led_pins at 0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts
index a64c2b3a1125..6858d6aafea3 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts
@@ -59,7 +59,6 @@
mmc2_pins_nrst: mmc2 at 0 {
allwinner,pins = "PC16";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
index b47b67765aec..3dcd745126a9 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -204,14 +204,12 @@
ahci_pwr_pin_olinuxinolime: ahci_pwr_pin at 1 {
allwinner,pins = "PC3";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_olinuxinolime: led_pins at 0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
@@ -229,7 +227,6 @@
usb0_vbus_pin_lime2: usb0_vbus_pin at 0 {
allwinner,pins = "PC17";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index 2dddbf148d8e..3773926df96e 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -236,7 +236,6 @@
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
index 69ad2345613f..8e05256f7c1b 100644
--- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
@@ -186,25 +186,21 @@
usb2_vbus_pin_bananapro: usb2_vbus_pin at 0 {
allwinner,pins = "PH22";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_power_pin_orangepi: gmac_power_pin at 0 {
allwinner,pins = "PH23";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_orangepi: led_pins at 0 {
allwinner,pins = "PH24", "PH25";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb1_vbus_pin_bananapro: usb1_vbus_pin at 0 {
allwinner,pins = "PH26";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
index d6608ed6cdf3..d168b8f08e30 100644
--- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
@@ -161,25 +161,21 @@
usb2_vbus_pin_bananapro: usb2_vbus_pin at 0 {
allwinner,pins = "PH22";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_power_pin_orangepi: gmac_power_pin at 0 {
allwinner,pins = "PH23";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_orangepi: led_pins at 0 {
allwinner,pins = "PH24";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb1_vbus_pin_bananapro: usb1_vbus_pin at 0 {
allwinner,pins = "PH26";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index 4a292a12616d..cdcbee74274e 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -154,13 +154,11 @@
ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin at 0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
led_pins_pcduino3_nano: led_pins at 0 {
allwinner,pins = "PH16", "PH15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
@@ -172,7 +170,6 @@
usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin at 0 {
allwinner,pins = "PD2";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index a416b3a47cee..fd2b4b8af9ea 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -185,13 +185,11 @@
led_pins_pcduino3: led_pins at 0 {
allwinner,pins = "PH15", "PH16";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
key_pins_pcduino3: key_pins at 0 {
allwinner,pins = "PH17", "PH18", "PH19";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
index a10c4ccd741d..688f75ceab58 100644
--- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
@@ -175,19 +175,16 @@
bl_enable_pin: bl_enable_pin at 0 {
allwinner,pins = "PH7";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
codec_pa_pin: codec_pa_pin at 0 {
allwinner,pins = "PH15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ts_reset_pin: ts_reset_pin at 0 {
allwinner,pins = "PB13";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
index 87901259582b..b12493350ee3 100644
--- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
@@ -162,7 +162,6 @@
vmmc3_pin_ap6xxx_wl_regon: vmmc3_pin at 0 {
allwinner,pins = "PH9";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f672df81106c..5585b25c2acd 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1094,13 +1094,11 @@
clk_out_a_pins_a: clk_out_a at 0 {
allwinner,pins = "PI12";
allwinner,function = "clk_out_a";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
clk_out_b_pins_a: clk_out_b at 0 {
allwinner,pins = "PI13";
allwinner,function = "clk_out_b";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
emac_pins_a: emac0 at 0 {
@@ -1110,7 +1108,6 @@
"PA11", "PA12", "PA13", "PA14",
"PA15", "PA16";
allwinner,function = "emac";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_pins_mii_a: gmac_mii at 0 {
@@ -1120,7 +1117,6 @@
"PA11", "PA12", "PA13", "PA14",
"PA15", "PA16";
allwinner,function = "gmac";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_pins_rgmii_a: gmac_rgmii at 0 {
@@ -1135,55 +1131,46 @@
* and need a higher signal drive strength
*/
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c0_pins_a: i2c0 at 0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "i2c0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins_a: i2c1 at 0 {
allwinner,pins = "PB18", "PB19";
allwinner,function = "i2c1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins_a: i2c2 at 0 {
allwinner,pins = "PB20", "PB21";
allwinner,function = "i2c2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c3_pins_a: i2c3 at 0 {
allwinner,pins = "PI0", "PI1";
allwinner,function = "i2c3";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir0_rx_pins_a: ir0 at 0 {
allwinner,pins = "PB4";
allwinner,function = "ir0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir0_tx_pins_a: ir0 at 1 {
allwinner,pins = "PB3";
allwinner,function = "ir0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir1_rx_pins_a: ir1 at 0 {
allwinner,pins = "PB23";
allwinner,function = "ir1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir1_tx_pins_a: ir1 at 1 {
allwinner,pins = "PB22";
allwinner,function = "ir1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins_a: mmc0 at 0 {
@@ -1191,7 +1178,6 @@
"PF3", "PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
@@ -1213,31 +1199,26 @@
"PI7", "PI8", "PI9";
allwinner,function = "mmc3";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ps20_pins_a: ps20 at 0 {
allwinner,pins = "PI20", "PI21";
allwinner,function = "ps2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ps21_pins_a: ps21 at 0 {
allwinner,pins = "PH12", "PH13";
allwinner,function = "ps2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
pwm0_pins_a: pwm0 at 0 {
allwinner,pins = "PB2";
allwinner,function = "pwm";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
pwm1_pins_a: pwm1 at 0 {
allwinner,pins = "PI3";
allwinner,function = "pwm";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spdif_tx_pins_a: spdif at 0 {
@@ -1249,109 +1230,91 @@
spi0_pins_a: spi0 at 0 {
allwinner,pins = "PI11", "PI12", "PI13";
allwinner,function = "spi0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi0_cs0_pins_a: spi0_cs0 at 0 {
allwinner,pins = "PI10";
allwinner,function = "spi0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi0_cs1_pins_a: spi0_cs1 at 0 {
allwinner,pins = "PI14";
allwinner,function = "spi0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi1_pins_a: spi1 at 0 {
allwinner,pins = "PI17", "PI18", "PI19";
allwinner,function = "spi1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi1_cs0_pins_a: spi1_cs0 at 0 {
allwinner,pins = "PI16";
allwinner,function = "spi1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_pins_a: spi2 at 0 {
allwinner,pins = "PC20", "PC21", "PC22";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_pins_b: spi2 at 1 {
allwinner,pins = "PB15", "PB16", "PB17";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_cs0_pins_a: spi2_cs0 at 0 {
allwinner,pins = "PC19";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_cs0_pins_b: spi2_cs0 at 1 {
allwinner,pins = "PB14";
allwinner,function = "spi2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart0_pins_a: uart0 at 0 {
allwinner,pins = "PB22", "PB23";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart2_pins_a: uart2 at 0 {
allwinner,pins = "PI16", "PI17", "PI18", "PI19";
allwinner,function = "uart2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart3_pins_a: uart3 at 0 {
allwinner,pins = "PG6", "PG7", "PG8", "PG9";
allwinner,function = "uart3";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart3_pins_b: uart3 at 1 {
allwinner,pins = "PH0", "PH1";
allwinner,function = "uart3";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart4_pins_a: uart4 at 0 {
allwinner,pins = "PG10", "PG11";
allwinner,function = "uart4";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart4_pins_b: uart4 at 1 {
allwinner,pins = "PH4", "PH5";
allwinner,function = "uart4";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart5_pins_a: uart5 at 0 {
allwinner,pins = "PI10", "PI11";
allwinner,function = "uart5";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart6_pins_a: uart6 at 0 {
allwinner,pins = "PI12", "PI13";
allwinner,function = "uart6";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart7_pins_a: uart7 at 0 {
allwinner,pins = "PI20", "PI21";
allwinner,function = "uart7";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 3f9b0f0f9b4c..3d2ad7da2564 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -275,7 +275,6 @@
uart0_pins_a: uart0 at 0 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_pins_a: uart1 at 0 {
@@ -293,7 +292,6 @@
"PF3", "PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc1_pins_a: mmc1 at 0 {
@@ -301,7 +299,6 @@
"PG3", "PG4", "PG5";
allwinner,function = "mmc1";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc2_8bit_pins: mmc2_8bit {
@@ -311,31 +308,26 @@
"PC15", "PC16";
allwinner,function = "mmc2";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
pwm0_pins: pwm0 {
allwinner,pins = "PH0";
allwinner,function = "pwm0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c0_pins_a: i2c0 at 0 {
allwinner,pins = "PH2", "PH3";
allwinner,function = "i2c0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins_a: i2c1 at 0 {
allwinner,pins = "PH4", "PH5";
allwinner,function = "i2c1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins_a: i2c2 at 0 {
allwinner,pins = "PE12", "PE13";
allwinner,function = "i2c2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
lcd_rgb666_pins: lcd-rgb666 at 0 {
@@ -344,7 +336,6 @@
"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
"PD24", "PD25", "PD26", "PD27";
allwinner,function = "lcd0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -584,7 +575,6 @@
r_uart_pins_a: r_uart at 0 {
allwinner,pins = "PL2", "PL3";
allwinner,function = "s_uart";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
index fea9db3ee9ad..89f68a78ab32 100644
--- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
+++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
@@ -93,7 +93,6 @@
wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin at 0 {
allwinner,pins = "PL6";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts
index abcd94ea5e86..e8367deaa587 100644
--- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts
+++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts
@@ -86,7 +86,6 @@
wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin at 0 {
allwinner,pins = "PL6";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
index fb4665576dff..442db91b943a 100644
--- a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
+++ b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
@@ -92,7 +92,6 @@
allwinner,pins = "PL5";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
index 7eaf610eabd7..59a64d2d695c 100644
--- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
+++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
@@ -94,19 +94,16 @@
led_pin_olinuxino: led_pins at 0 {
allwinner,pins = "PB7";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_olinuxino: mmc0_cd_pin at 0 {
allwinner,pins = "PB4";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
allwinner,pins = "PB3";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index e60c4c8c6976..310a38cf7f18 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -240,7 +240,6 @@
uart0_pins_b: uart0 at 1 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c03d7f4cac83..cec6bfc2d3c9 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -171,19 +171,16 @@
"PF3", "PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart0_pins_a: uart0 at 0 {
allwinner,pins = "PF2", "PF4";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart0_pins_b: uart0 at 1 {
allwinner,pins = "PB9", "PB10";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index e02314a2d643..49194c38d56b 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -158,19 +158,16 @@
pwr_led_bpi_m2p: led_pins at 0 {
allwinner,pins = "PL10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
sw_r_bpi_m2p: key_pins at 0 {
allwinner,pins = "PL3";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
wifi_en_bpi_m2p: wifi_en_pin {
allwinner,pins = "PL7";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 277935e10543..1c6e96e8ec98 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -99,7 +99,6 @@
leds_opc: led-pins {
allwinner,pins = "PA10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -107,7 +106,6 @@
leds_r_opc: led-pins {
allwinner,pins = "PL10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index e44af3446514..dfd9bc2008fd 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -147,7 +147,6 @@
leds_opc: led_pins at 0 {
allwinner,pins = "PA15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -155,19 +154,16 @@
leds_r_opc: led_pins at 0 {
allwinner,pins = "PL10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
sw_r_opc: key_pins at 0 {
allwinner,pins = "PL3", "PL4";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin at 0 {
allwinner,pins = "PL7";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
index ce5b1086b580..77d29bae7739 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
@@ -145,7 +145,6 @@
leds_opc: led_pins at 0 {
allwinner,pins = "PA15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -153,13 +152,11 @@
leds_r_opc: led_pins at 0 {
allwinner,pins = "PL10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
sw_r_opc: key_pins at 0 {
allwinner,pins = "PL3";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index fbdd239175d4..49529d9ca26d 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -112,7 +112,6 @@
leds_opc: led_pins at 0 {
allwinner,pins = "PA15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -120,13 +119,11 @@
leds_r_opc: led_pins at 0 {
allwinner,pins = "PL10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
sw_r_opc: key_pins at 0 {
allwinner,pins = "PL3";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 638720c3d04e..0d56d33d43ea 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -134,7 +134,6 @@
leds_opc: led_pins at 0 {
allwinner,pins = "PA15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -142,13 +141,11 @@
leds_r_opc: led_pins at 0 {
allwinner,pins = "PL10";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
sw_r_opc: key_pins at 0 {
allwinner,pins = "PL3";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index 1236583caf64..ab8593d1d3df 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -85,7 +85,6 @@
usb3_vbus_pin_a: usb3_vbus_pin at 0 {
allwinner,pins = "PG11";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 098373ce38eb..9510d785bd12 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -330,19 +330,16 @@
i2c0_pins: i2c0 {
allwinner,pins = "PA11", "PA12";
allwinner,function = "i2c0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins: i2c1 {
allwinner,pins = "PA18", "PA19";
allwinner,function = "i2c1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins: i2c2 {
allwinner,pins = "PE12", "PE13";
allwinner,function = "i2c2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins_a: mmc0 at 0 {
@@ -350,7 +347,6 @@
"PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin: mmc0_cd_pin at 0 {
@@ -364,7 +360,6 @@
"PG4", "PG5";
allwinner,function = "mmc1";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc2_8bit_pins: mmc2_8bit {
@@ -374,37 +369,31 @@
"PC15", "PC16";
allwinner,function = "mmc2";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart0_pins_a: uart0 at 0 {
allwinner,pins = "PA4", "PA5";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_pins: uart1 {
allwinner,pins = "PG6", "PG7";
allwinner,function = "uart1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_rts_cts_pins: uart1_rts_cts {
allwinner,pins = "PG8", "PG9";
allwinner,function = "uart1";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart2_pins: uart2 {
allwinner,pins = "PA0", "PA1";
allwinner,function = "uart2";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart3_pins: uart3 {
allwinner,pins = "PG13", "PG14";
allwinner,function = "uart3";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -569,7 +558,6 @@
ir_pins_a: ir at 0 {
allwinner,pins = "PL11";
allwinner,function = "s_cir_rx";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
};
diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts
index 6161ec441df5..0588fceb0636 100644
--- a/arch/arm/boot/dts/sun8i-r16-parrot.dts
+++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts
@@ -167,7 +167,6 @@
led_pins_parrot: led_pins at 0 {
allwinner,pins = "PE16", "PE17";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_det: usb0_id_detect_pin at 0 {
@@ -179,7 +178,6 @@
usb1_vbus_pin_parrot: usb1_vbus_pin at 0 {
allwinner,pins = "PD12";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -187,7 +185,6 @@
wifi_reset_pin_parrot: wifi_reset_pin at 0 {
allwinner,pins = "PL6";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index ae95e5969681..dea852b2a4f3 100644
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -96,7 +96,6 @@
bl_en_pin: bl_en_pin at 0 {
allwinner,pins = "PH6";
allwinner,function = "gpio_in";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin: mmc0_cd_pin at 0 {
@@ -108,7 +107,6 @@
ts_power_pin: ts_power_pin at 0 {
allwinner,pins = "PH1";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_detect_pin: usb0_id_detect_pin at 0 {
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index e1be9fca86c7..e0ae76088f7e 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -112,7 +112,6 @@
led_pins_cubieboard4: led-pins at 0 {
allwinner,pins = "PH6", "PH17";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_cubieboard4: mmc0_cd_pin at 0 {
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 0b2f7042bddf..a2e540fc5725 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -162,7 +162,6 @@
led_pins_optimus: led-pins at 0 {
allwinner,pins = "PH0", "PH1";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_optimus: mmc0_cd_pin at 0 {
@@ -174,13 +173,11 @@
usb1_vbus_pin_optimus: usb1_vbus_pin at 1 {
allwinner,pins = "PH4";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb3_vbus_pin_optimus: usb3_vbus_pin at 1 {
allwinner,pins = "PH5";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -192,7 +189,6 @@
led_r_pins_optimus: led-pins at 1 {
allwinner,pins = "PM15";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 293b41ac8e37..d03f7481401c 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -688,7 +688,6 @@
i2c3_pins_a: i2c3 at 0 {
allwinner,pins = "PG10", "PG11";
allwinner,function = "i2c3";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins: mmc0 {
@@ -696,7 +695,6 @@
"PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc2_8bit_pins: mmc2_8bit {
@@ -706,19 +704,16 @@
"PC16";
allwinner,function = "mmc2";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart0_pins_a: uart0 at 0 {
allwinner,pins = "PH12", "PH13";
allwinner,function = "uart0";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart4_pins_a: uart4 at 0 {
allwinner,pins = "PG12", "PG13", "PG14", "PG15";
allwinner,function = "uart4";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
@@ -901,7 +896,6 @@
r_ir_pins: r_ir {
allwinner,pins = "PL6";
allwinner,function = "s_cir_rx";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
r_rsb_pins: r_rsb {
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index 7809e18d30bd..358b8d9b4703 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -49,25 +49,21 @@
ahci_pwr_pin_a: ahci_pwr_pin at 0 {
allwinner,pins = "PB8";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_vbus_pin_a: usb0_vbus_pin at 0 {
allwinner,pins = "PB9";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb1_vbus_pin_a: usb1_vbus_pin at 0 {
allwinner,pins = "PH6";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb2_vbus_pin_a: usb2_vbus_pin at 0 {
allwinner,pins = "PH3";
allwinner,function = "gpio_out";
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
--
git-series 0.8.10
^ permalink raw reply related
* [PATCH] ARM: sti: stih410-clocks: Add PROC_STFE as a critical clock
From: Patrice Chotard @ 2016-10-20 13:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476804957-24000-1-git-send-email-peter.griffin@linaro.org>
On 10/18/2016 05:35 PM, Peter Griffin wrote:
> Once the ST frontend demux HW IP has been enabled, the clock can't
> be disabled otherwise the system will hang and the board will
> be unserviceable.
>
> To allow balanced clock enable/disable calls in the driver we use
> the critical clock infrastructure to take an extra reference on the
> clock so the clock will never actually be disabled.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm/boot/dts/stih410-clock.dtsi | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
> index 8598eff..07c8ef9 100644
> --- a/arch/arm/boot/dts/stih410-clock.dtsi
> +++ b/arch/arm/boot/dts/stih410-clock.dtsi
> @@ -208,7 +208,8 @@
> "clk-clust-hades",
> "clk-hwpe-hades",
> "clk-fc-hades";
> - clock-critical = <CLK_ICN_CPU>,
> + clock-critical = <CLK_PROC_STFE>,
> + <CLK_ICN_CPU>,
> <CLK_TX_ICN_DMU>,
> <CLK_EXT2F_A9>,
> <CLK_ICN_LMI>,
>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Applied on sti-dt-for-4.10 branch
Thanks
^ permalink raw reply
* [PATCH v3 2/3] drm: zte: add initial vou drm driver
From: Sean Paul @ 2016-10-20 13:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476948625-8521-3-git-send-email-shawn.guo@linaro.org>
On Thu, Oct 20, 2016 at 3:30 AM, Shawn Guo <shawn.guo@linaro.org> wrote:
> It adds the initial ZTE VOU display controller DRM driver. There are
> still some features to be added, like overlay plane, scaling, and more
> output devices support. But it's already useful with dual CRTCs and
> HDMI monitor working.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/zte/Kconfig | 8 +
> drivers/gpu/drm/zte/Makefile | 7 +
> drivers/gpu/drm/zte/zx_drm_drv.c | 267 +++++++++++++
> drivers/gpu/drm/zte/zx_drm_drv.h | 36 ++
> drivers/gpu/drm/zte/zx_hdmi.c | 678 +++++++++++++++++++++++++++++++++
> drivers/gpu/drm/zte/zx_plane.c | 375 ++++++++++++++++++
> drivers/gpu/drm/zte/zx_plane.h | 26 ++
> drivers/gpu/drm/zte/zx_vou.c | 799 +++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/zte/zx_vou.h | 46 +++
> 11 files changed, 2245 insertions(+)
> create mode 100644 drivers/gpu/drm/zte/Kconfig
> create mode 100644 drivers/gpu/drm/zte/Makefile
> create mode 100644 drivers/gpu/drm/zte/zx_drm_drv.c
> create mode 100644 drivers/gpu/drm/zte/zx_drm_drv.h
> create mode 100644 drivers/gpu/drm/zte/zx_hdmi.c
> create mode 100644 drivers/gpu/drm/zte/zx_plane.c
> create mode 100644 drivers/gpu/drm/zte/zx_plane.h
> create mode 100644 drivers/gpu/drm/zte/zx_vou.c
> create mode 100644 drivers/gpu/drm/zte/zx_vou.h
>
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index 483059a22b1b..a91f8cecbe0f 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -223,6 +223,8 @@ source "drivers/gpu/drm/hisilicon/Kconfig"
>
> source "drivers/gpu/drm/mediatek/Kconfig"
>
> +source "drivers/gpu/drm/zte/Kconfig"
> +
> # Keep legacy drivers last
>
> menuconfig DRM_LEGACY
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 25c720454017..f3251750c92b 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -86,3 +86,4 @@ obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/
> obj-$(CONFIG_DRM_ETNAVIV) += etnaviv/
> obj-$(CONFIG_DRM_ARCPGU)+= arc/
> obj-y += hisilicon/
> +obj-$(CONFIG_DRM_ZTE) += zte/
> diff --git a/drivers/gpu/drm/zte/Kconfig b/drivers/gpu/drm/zte/Kconfig
> new file mode 100644
> index 000000000000..4065b2840f1c
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/Kconfig
> @@ -0,0 +1,8 @@
> +config DRM_ZTE
> + tristate "DRM Support for ZTE SoCs"
> + depends on DRM && ARCH_ZX
> + select DRM_KMS_CMA_HELPER
> + select DRM_KMS_FB_HELPER
> + select DRM_KMS_HELPER
> + help
> + Choose this option to enable DRM on ZTE ZX SoCs.
> diff --git a/drivers/gpu/drm/zte/Makefile b/drivers/gpu/drm/zte/Makefile
> new file mode 100644
> index 000000000000..699180bfd57c
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/Makefile
> @@ -0,0 +1,7 @@
> +zxdrm-y := \
> + zx_drm_drv.o \
> + zx_hdmi.o \
> + zx_plane.o \
> + zx_vou.o
> +
> +obj-$(CONFIG_DRM_ZTE) += zxdrm.o
> diff --git a/drivers/gpu/drm/zte/zx_drm_drv.c b/drivers/gpu/drm/zte/zx_drm_drv.c
> new file mode 100644
> index 000000000000..2476a9b92cea
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_drm_drv.c
> @@ -0,0 +1,267 @@
> +/*
> + * Copyright 2016 Linaro Ltd.
> + * Copyright 2016 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/list.h>
> +#include <linux/module.h>
> +#include <linux/of_graph.h>
> +#include <linux/of_platform.h>
> +#include <linux/spinlock.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_fb_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_of.h>
> +#include <drm/drmP.h>
> +
> +#include "zx_drm_drv.h"
> +#include "zx_vou.h"
> +
> +struct zx_drm_private {
> + struct drm_fbdev_cma *fbdev;
> +};
> +
> +static void zx_drm_fb_output_poll_changed(struct drm_device *drm)
> +{
> + struct zx_drm_private *priv = drm->dev_private;
> +
> + drm_fbdev_cma_hotplug_event(priv->fbdev);
> +}
> +
> +static const struct drm_mode_config_funcs zx_drm_mode_config_funcs = {
> + .fb_create = drm_fb_cma_create,
> + .output_poll_changed = zx_drm_fb_output_poll_changed,
> + .atomic_check = drm_atomic_helper_check,
> + .atomic_commit = drm_atomic_helper_commit,
> +};
> +
> +static void zx_drm_lastclose(struct drm_device *drm)
> +{
> + struct zx_drm_private *priv = drm->dev_private;
> +
> + drm_fbdev_cma_restore_mode(priv->fbdev);
> +}
> +
> +static const struct file_operations zx_drm_fops = {
> + .owner = THIS_MODULE,
> + .open = drm_open,
> + .release = drm_release,
> + .unlocked_ioctl = drm_ioctl,
> +#ifdef CONFIG_COMPAT
> + .compat_ioctl = drm_compat_ioctl,
> +#endif
> + .poll = drm_poll,
> + .read = drm_read,
> + .llseek = noop_llseek,
> + .mmap = drm_gem_cma_mmap,
> +};
> +
> +static struct drm_driver zx_drm_driver = {
> + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
> + DRIVER_ATOMIC,
> + .lastclose = zx_drm_lastclose,
> + .get_vblank_counter = drm_vblank_no_hw_counter,
> + .enable_vblank = zx_vou_enable_vblank,
> + .disable_vblank = zx_vou_disable_vblank,
> + .gem_free_object = drm_gem_cma_free_object,
> + .gem_vm_ops = &drm_gem_cma_vm_ops,
> + .dumb_create = drm_gem_cma_dumb_create,
> + .dumb_map_offset = drm_gem_cma_dumb_map_offset,
> + .dumb_destroy = drm_gem_dumb_destroy,
> + .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> + .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> + .gem_prime_export = drm_gem_prime_export,
> + .gem_prime_import = drm_gem_prime_import,
> + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> + .gem_prime_vmap = drm_gem_cma_prime_vmap,
> + .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
> + .gem_prime_mmap = drm_gem_cma_prime_mmap,
> + .fops = &zx_drm_fops,
> + .name = "zx-vou",
> + .desc = "ZTE VOU Controller DRM",
> + .date = "20160811",
> + .major = 1,
> + .minor = 0,
> +};
> +
> +static int zx_drm_bind(struct device *dev)
> +{
> + struct drm_device *drm;
> + struct zx_drm_private *priv;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + drm = drm_dev_alloc(&zx_drm_driver, dev);
> + if (!drm)
> + return -ENOMEM;
> +
> + drm->dev_private = priv;
> + dev_set_drvdata(dev, drm);
> +
> + drm_mode_config_init(drm);
> + drm->mode_config.min_width = 16;
> + drm->mode_config.min_height = 16;
> + drm->mode_config.max_width = 4096;
> + drm->mode_config.max_height = 4096;
> + drm->mode_config.funcs = &zx_drm_mode_config_funcs;
> +
> + ret = component_bind_all(dev, drm);
> + if (ret) {
> + dev_err(dev, "failed to bind all components: %d\n", ret);
Consider using the new DRM_DEV_* messages instead of the plain old dev_*
> + goto out_unregister;
> + }
> +
> + ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
> + if (ret < 0) {
> + dev_err(dev, "failed to init vblank: %d\n", ret);
> + goto out_unbind;
> + }
> +
> + /*
> + * We will manage irq handler on our own. In this case, irq_enabled
> + * need to be true for using vblank core support.
> + */
> + drm->irq_enabled = true;
> +
> + drm_mode_config_reset(drm);
> + drm_kms_helper_poll_init(drm);
> +
> + priv->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
> + drm->mode_config.num_connector);
> + if (IS_ERR(priv->fbdev)) {
> + ret = PTR_ERR(priv->fbdev);
> + dev_err(dev, "failed to init cma fbdev: %d\n", ret);
> + priv->fbdev = NULL;
> + goto out_poll_fini;
> + }
> +
> + ret = drm_dev_register(drm, 0);
> + if (ret)
> + goto out_fbdev_fini;
> +
> + return 0;
> +
> +out_fbdev_fini:
> + if (priv->fbdev) {
> + drm_fbdev_cma_fini(priv->fbdev);
> + priv->fbdev = NULL;
> + }
> +out_poll_fini:
> + drm_kms_helper_poll_fini(drm);
> + drm_mode_config_cleanup(drm);
> + drm_vblank_cleanup(drm);
> +out_unbind:
> + component_unbind_all(dev, drm);
> +out_unregister:
> + dev_set_drvdata(dev, NULL);
> + drm->dev_private = NULL;
> + drm_dev_unref(drm);
> + return ret;
> +}
> +
> +static void zx_drm_unbind(struct device *dev)
> +{
> + struct drm_device *drm = dev_get_drvdata(dev);
> + struct zx_drm_private *priv = drm->dev_private;
> +
> + drm_dev_unregister(drm);
> + if (priv->fbdev) {
> + drm_fbdev_cma_fini(priv->fbdev);
> + priv->fbdev = NULL;
> + }
> + drm_kms_helper_poll_fini(drm);
> + drm_mode_config_cleanup(drm);
> + drm_vblank_cleanup(drm);
> + component_unbind_all(dev, drm);
> + dev_set_drvdata(dev, NULL);
> + drm->dev_private = NULL;
> + drm_dev_unref(drm);
> +}
> +
> +static const struct component_master_ops zx_drm_master_ops = {
> + .bind = zx_drm_bind,
> + .unbind = zx_drm_unbind,
> +};
> +
> +static int compare_of(struct device *dev, void *data)
> +{
> + return dev->of_node == data;
> +}
> +
> +static int zx_drm_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *parent = dev->of_node;
> + struct device_node *child;
> + struct component_match *match = NULL;
> + int ret;
> +
> + ret = of_platform_populate(parent, NULL, NULL, dev);
> + if (ret)
> + return ret;
> +
> + for_each_available_child_of_node(parent, child) {
> + component_match_add(dev, &match, compare_of, child);
> + of_node_put(child);
> + }
> +
> + return component_master_add_with_match(dev, &zx_drm_master_ops, match);
> +}
> +
> +static int zx_drm_remove(struct platform_device *pdev)
> +{
> + component_master_del(&pdev->dev, &zx_drm_master_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id zx_drm_of_match[] = {
> + { .compatible = "zte,zx296718-vou", },
> + { /* end */ },
> +};
> +MODULE_DEVICE_TABLE(of, zx_drm_of_match);
> +
> +static struct platform_driver zx_drm_platform_driver = {
> + .probe = zx_drm_probe,
> + .remove = zx_drm_remove,
> + .driver = {
> + .name = "zx-drm",
> + .of_match_table = zx_drm_of_match,
> + },
> +};
> +
> +static struct platform_driver *drivers[] = {
> + &zx_crtc_driver,
> + &zx_hdmi_driver,
> + &zx_drm_platform_driver,
> +};
> +
> +static int zx_drm_init(void)
> +{
> + return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
> +}
> +module_init(zx_drm_init);
> +
> +static void zx_drm_exit(void)
> +{
> + platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
> +}
> +module_exit(zx_drm_exit);
> +
> +MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
> +MODULE_DESCRIPTION("ZTE ZX VOU DRM driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/zte/zx_drm_drv.h b/drivers/gpu/drm/zte/zx_drm_drv.h
> new file mode 100644
> index 000000000000..e65cd18a6cba
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_drm_drv.h
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright 2016 Linaro Ltd.
> + * Copyright 2016 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __ZX_DRM_DRV_H__
> +#define __ZX_DRM_DRV_H__
> +
> +extern struct platform_driver zx_crtc_driver;
> +extern struct platform_driver zx_hdmi_driver;
> +
> +static inline u32 zx_readl(void __iomem *reg)
> +{
> + return readl_relaxed(reg);
> +}
> +
> +static inline void zx_writel(void __iomem *reg, u32 val)
> +{
> + writel_relaxed(val, reg);
> +}
> +
> +static inline void zx_writel_mask(void __iomem *reg, u32 mask, u32 val)
> +{
> + u32 tmp;
> +
> + tmp = zx_readl(reg);
> + tmp = (tmp & ~mask) | (val & mask);
> + zx_writel(reg, tmp);
> +}
> +
> +#endif /* __ZX_DRM_DRV_H__ */
> diff --git a/drivers/gpu/drm/zte/zx_hdmi.c b/drivers/gpu/drm/zte/zx_hdmi.c
> new file mode 100644
> index 000000000000..81e1c3716ed8
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_hdmi.c
> @@ -0,0 +1,678 @@
> +/*
> + * Copyright 2016 Linaro Ltd.
> + * Copyright 2016 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/hdmi.h>
> +#include <linux/irq.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of_device.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_edid.h>
> +#include <drm/drm_of.h>
> +#include <drm/drmP.h>
> +
> +#include "zx_vou.h"
> +
> +#define FUNC_SEL 0x000b
> +#define FUNC_HDMI_EN BIT(0)
> +#define CLKPWD 0x000d
> +#define CLKPWD_PDIDCK BIT(2)
> +#define PWD_SRST 0x0010
> +#define P2T_CTRL 0x0066
> +#define P2T_DC_PKT_EN BIT(7)
> +#define L1_INTR_STAT 0x007e
> +#define L1_INTR_STAT_INTR1 BIT(0)
> +#define INTR1_STAT 0x008f
> +#define INTR1_MASK 0x0095
> +#define INTR1_MONITOR_DETECT (BIT(5) | BIT(6))
> +#define ZX_DDC_ADDR 0x00ed
> +#define ZX_DDC_SEGM 0x00ee
> +#define ZX_DDC_OFFSET 0x00ef
> +#define ZX_DDC_DIN_CNT1 0x00f0
> +#define ZX_DDC_DIN_CNT2 0x00f1
> +#define ZX_DDC_CMD 0x00f3
> +#define DDC_CMD_MASK 0xf
> +#define DDC_CMD_CLEAR_FIFO 0x9
> +#define DDC_CMD_SEQUENTIAL_READ 0x2
> +#define ZX_DDC_DATA 0x00f4
> +#define ZX_DDC_DOUT_CNT 0x00f5
> +#define DDC_DOUT_CNT_MASK 0x1f
> +#define TEST_TXCTRL 0x00f7
> +#define TEST_TXCTRL_HDMI_MODE BIT(1)
> +#define HDMICTL4 0x0235
> +#define TPI_HPD_RSEN 0x063b
> +#define TPI_HPD_CONNECTION (BIT(1) | BIT(2))
> +#define TPI_INFO_FSEL 0x06bf
> +#define FSEL_AVI 0
> +#define FSEL_GBD 1
> +#define FSEL_AUDIO 2
> +#define FSEL_SPD 3
> +#define FSEL_MPEG 4
> +#define FSEL_VSIF 5
> +#define TPI_INFO_B0 0x06c0
> +#define TPI_INFO_EN 0x06df
> +#define TPI_INFO_TRANS_EN BIT(7)
> +#define TPI_INFO_TRANS_RPT BIT(6)
> +#define TPI_DDC_MASTER_EN 0x06f8
> +#define HW_DDC_MASTER BIT(7)
> +
> +#define ZX_HDMI_INFOFRAME_SIZE 31
> +
> +#define DDC_SEGMENT_ADDR 0x30
> +
> +struct zx_hdmi_i2c {
> + struct i2c_adapter adap;
> + struct mutex lock;
> +};
> +
> +struct zx_hdmi {
> + struct drm_connector connector;
> + struct drm_encoder encoder;
> + struct zx_hdmi_i2c *ddc;
> + struct device *dev;
> + struct drm_device *drm;
> + void __iomem *mmio;
> + struct clk *cec_clk;
> + struct clk *osc_clk;
> + struct clk *xclk;
> + bool sink_is_hdmi;
> + bool sink_has_audio;
> + const struct vou_inf *inf;
> +};
> +
> +#define to_zx_hdmi(x) container_of(x, struct zx_hdmi, x)
> +
> +static const struct vou_inf vou_inf_hdmi = {
> + .id = VOU_HDMI,
> + .data_sel = VOU_YUV444,
> + .clocks_en_bits = BIT(24) | BIT(18) | BIT(6),
> + .clocks_sel_bits = BIT(13) | BIT(2),
> +};
> +
> +static inline u8 hdmi_readb(struct zx_hdmi *hdmi, u16 offset)
> +{
> + return readl_relaxed(hdmi->mmio + offset * 4);
> +}
> +
> +static inline void hdmi_writeb(struct zx_hdmi *hdmi, u16 offset, u8 val)
> +{
> + writel_relaxed(val, hdmi->mmio + offset * 4);
> +}
> +
> +static inline void hdmi_writeb_mask(struct zx_hdmi *hdmi, u16 offset,
> + u8 mask, u8 val)
> +{
> + u8 tmp;
> +
> + tmp = hdmi_readb(hdmi, offset);
> + tmp = (tmp & ~mask) | (val & mask);
> + hdmi_writeb(hdmi, offset, tmp);
> +}
> +
> +static int zx_hdmi_infoframe_trans(struct zx_hdmi *hdmi,
> + union hdmi_infoframe *frame, u8 fsel)
> +{
> + u8 buffer[ZX_HDMI_INFOFRAME_SIZE];
> + int num;
> + int i;
> +
> + hdmi_writeb(hdmi, TPI_INFO_FSEL, fsel);
> +
> + num = hdmi_infoframe_pack(frame, buffer, ZX_HDMI_INFOFRAME_SIZE);
> + if (num < 0) {
> + dev_err(hdmi->dev, "failed to pack infoframe: %d\n", num);
> + return num;
> + }
> +
> + for (i = 0; i < num; i++)
> + hdmi_writeb(hdmi, TPI_INFO_B0 + i, buffer[i]);
> +
> + hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_RPT,
> + TPI_INFO_TRANS_RPT);
> + hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_EN,
> + TPI_INFO_TRANS_EN);
> +
> + return num;
> +}
> +
> +static int zx_hdmi_config_video_vsi(struct zx_hdmi *hdmi,
> + struct drm_display_mode *mode)
> +{
> + union hdmi_infoframe frame;
> + int ret;
> +
> + ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
> + mode);
> + if (ret) {
> + dev_err(hdmi->dev, "failed to get vendor infoframe: %d\n", ret);
> + return ret;
> + }
> +
> + return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_VSIF);
> +}
> +
> +static int zx_hdmi_config_video_avi(struct zx_hdmi *hdmi,
> + struct drm_display_mode *mode)
> +{
> + union hdmi_infoframe frame;
> + int ret;
> +
> + ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
> + if (ret) {
> + dev_err(hdmi->dev, "failed to get avi infoframe: %d\n", ret);
> + return ret;
> + }
> +
> + /* We always use YUV444 for HDMI output. */
> + frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
> +
> + return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_AVI);
> +}
> +
> +static void zx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
> + struct drm_display_mode *mode,
> + struct drm_display_mode *adj_mode)
> +{
> + struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
> +
> + if (hdmi->sink_is_hdmi) {
> + zx_hdmi_config_video_avi(hdmi, mode);
> + zx_hdmi_config_video_vsi(hdmi, mode);
> + }
> +}
> +
> +static void zx_hdmi_encoder_enable(struct drm_encoder *encoder)
> +{
> + struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
> +
> + vou_inf_enable(hdmi->inf, encoder->crtc);
> +}
> +
> +static void zx_hdmi_encoder_disable(struct drm_encoder *encoder)
> +{
> + struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
> +
> + vou_inf_disable(hdmi->inf, encoder->crtc);
> +}
> +
> +static const struct drm_encoder_helper_funcs zx_hdmi_encoder_helper_funcs = {
> + .enable = zx_hdmi_encoder_enable,
> + .disable = zx_hdmi_encoder_disable,
> + .mode_set = zx_hdmi_encoder_mode_set,
> +};
> +
> +static const struct drm_encoder_funcs zx_hdmi_encoder_funcs = {
> + .destroy = drm_encoder_cleanup,
> +};
> +
> +static int zx_hdmi_connector_get_modes(struct drm_connector *connector)
> +{
> + struct zx_hdmi *hdmi = to_zx_hdmi(connector);
> + struct edid *edid;
> + int ret;
> +
> + edid = drm_get_edid(connector, &hdmi->ddc->adap);
> + if (!edid)
> + return 0;
> +
> + hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
> + hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
> + drm_mode_connector_update_edid_property(connector, edid);
> + ret = drm_add_edid_modes(connector, edid);
> + kfree(edid);
> +
> + return ret;
> +}
> +
> +static enum drm_mode_status
> +zx_hdmi_connector_mode_valid(struct drm_connector *connector,
> + struct drm_display_mode *mode)
> +{
> + return MODE_OK;
> +}
> +
> +static struct drm_connector_helper_funcs zx_hdmi_connector_helper_funcs = {
> + .get_modes = zx_hdmi_connector_get_modes,
> + .mode_valid = zx_hdmi_connector_mode_valid,
> +};
> +
> +static enum drm_connector_status
> +zx_hdmi_connector_detect(struct drm_connector *connector, bool force)
> +{
> + struct zx_hdmi *hdmi = to_zx_hdmi(connector);
> +
> + return (hdmi_readb(hdmi, TPI_HPD_RSEN) & TPI_HPD_CONNECTION) ?
> + connector_status_connected : connector_status_disconnected;
> +}
> +
> +static void zx_hdmi_connector_destroy(struct drm_connector *connector)
> +{
> + drm_connector_unregister(connector);
> + drm_connector_cleanup(connector);
> +}
> +
> +static const struct drm_connector_funcs zx_hdmi_connector_funcs = {
> + .dpms = drm_atomic_helper_connector_dpms,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .detect = zx_hdmi_connector_detect,
> + .destroy = zx_hdmi_connector_destroy,
> + .reset = drm_atomic_helper_connector_reset,
> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +static int zx_hdmi_register(struct drm_device *drm, struct zx_hdmi *hdmi)
> +{
> + struct drm_encoder *encoder = &hdmi->encoder;
> +
> + encoder->possible_crtcs = VOU_CRTC_MASK;
> +
> + drm_encoder_init(drm, encoder, &zx_hdmi_encoder_funcs,
> + DRM_MODE_ENCODER_TMDS, NULL);
> + drm_encoder_helper_add(encoder, &zx_hdmi_encoder_helper_funcs);
> +
> + hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
> +
> + drm_connector_init(drm, &hdmi->connector, &zx_hdmi_connector_funcs,
> + DRM_MODE_CONNECTOR_HDMIA);
> + drm_connector_helper_add(&hdmi->connector,
> + &zx_hdmi_connector_helper_funcs);
> +
> + drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
> +
> + return 0;
> +}
> +
> +static irqreturn_t zx_hdmi_irq_thread(int irq, void *dev_id)
> +{
> + struct zx_hdmi *hdmi = dev_id;
> +
> + drm_helper_hpd_irq_event(hdmi->connector.dev);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t zx_hdmi_irq_handler(int irq, void *dev_id)
> +{
> + struct zx_hdmi *hdmi = dev_id;
> + u8 lstat;
> +
> + lstat = hdmi_readb(hdmi, L1_INTR_STAT);
> +
> + /* Monitor detect/HPD interrupt */
> + if (lstat & L1_INTR_STAT_INTR1) {
> + u8 stat;
> +
> + stat = hdmi_readb(hdmi, INTR1_STAT);
> + hdmi_writeb(hdmi, INTR1_STAT, stat);
> +
> + if (stat & INTR1_MONITOR_DETECT)
> + return IRQ_WAKE_THREAD;
> + }
> +
> + return IRQ_NONE;
> +}
> +
> +static int zx_hdmi_i2c_read(struct zx_hdmi *hdmi, struct i2c_msg *msg)
> +{
> + int len = msg->len;
> + u8 *buf = msg->buf;
> + int retry = 0;
> + int ret = 0;
> +
> + /* Bits [9:8] of bytes */
> + hdmi_writeb(hdmi, ZX_DDC_DIN_CNT2, (len >> 8) & 0xff);
> + /* Bits [7:0] of bytes */
> + hdmi_writeb(hdmi, ZX_DDC_DIN_CNT1, len & 0xff);
> +
> + /* Clear FIFO */
> + hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK, DDC_CMD_CLEAR_FIFO);
> +
> + /* Kick off the read */
> + hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK,
> + DDC_CMD_SEQUENTIAL_READ);
> +
> + while (len > 0) {
> + int cnt, i;
> +
> + /* FIFO needs some time to get ready */
> + usleep_range(500, 1000);
> +
> + cnt = hdmi_readb(hdmi, ZX_DDC_DOUT_CNT) & DDC_DOUT_CNT_MASK;
> + if (cnt == 0) {
> + if (++retry > 5) {
> + dev_err(hdmi->dev, "DDC FIFO read timed out!");
> + ret = -ETIMEDOUT;
> + break;
Why not just return -ETIMEDOUT here?
> + }
> + continue;
> + }
> +
> + for (i = 0; i < cnt; i++)
> + *buf++ = hdmi_readb(hdmi, ZX_DDC_DATA);
> + len -= cnt;
> + }
> +
> + return ret;
> +}
> +
> +static int zx_hdmi_i2c_write(struct zx_hdmi *hdmi, struct i2c_msg *msg)
> +{
> + /*
> + * The DDC I2C adapter is only for reading EDID data, so we assume
> + * that the write to this adapter must be the EDID data offset.
> + */
> + if ((msg->len != 1) ||
> + ((msg->addr != DDC_ADDR) && (msg->addr != DDC_SEGMENT_ADDR)))
> + return -EINVAL;
> +
> + if (msg->addr == DDC_SEGMENT_ADDR)
> + hdmi_writeb(hdmi, ZX_DDC_SEGM, msg->addr << 1);
> + else if (msg->addr == DDC_ADDR)
> + hdmi_writeb(hdmi, ZX_DDC_ADDR, msg->addr << 1);
> +
> + hdmi_writeb(hdmi, ZX_DDC_OFFSET, msg->buf[0]);
> +
> + return 0;
> +}
> +
> +static int zx_hdmi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
> + int num)
> +{
> + struct zx_hdmi *hdmi = i2c_get_adapdata(adap);
> + struct zx_hdmi_i2c *ddc = hdmi->ddc;
> + int i, ret = 0;
> +
> + mutex_lock(&ddc->lock);
> +
> + /* Enable DDC master access */
> + hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, HW_DDC_MASTER);
> +
> + for (i = 0; i < num; i++) {
> + dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
> + i + 1, num, msgs[i].len, msgs[i].flags);
> +
> + if (msgs[i].flags & I2C_M_RD)
> + ret = zx_hdmi_i2c_read(hdmi, &msgs[i]);
> + else
> + ret = zx_hdmi_i2c_write(hdmi, &msgs[i]);
> +
> + if (ret < 0)
> + break;
> + }
> +
> + if (!ret)
> + ret = num;
> +
> + /* Disable DDC master access */
> + hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, 0);
> +
> + mutex_unlock(&ddc->lock);
> +
> + return ret;
> +}
> +
> +static u32 zx_hdmi_i2c_func(struct i2c_adapter *adapter)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
> +
> +static const struct i2c_algorithm zx_hdmi_algorithm = {
> + .master_xfer = zx_hdmi_i2c_xfer,
> + .functionality = zx_hdmi_i2c_func,
> +};
> +
> +static int zx_hdmi_ddc_register(struct zx_hdmi *hdmi)
> +{
> + struct i2c_adapter *adap;
> + struct zx_hdmi_i2c *ddc;
> + int ret;
> +
> + ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
> + if (!ddc)
> + return -ENOMEM;
> +
> + hdmi->ddc = ddc;
> + mutex_init(&ddc->lock);
> +
> + adap = &ddc->adap;
> + adap->owner = THIS_MODULE;
> + adap->class = I2C_CLASS_DDC;
> + adap->dev.parent = hdmi->dev;
> + adap->algo = &zx_hdmi_algorithm;
> + snprintf(adap->name, sizeof(adap->name), "zx hdmi i2c");
> +
> + ret = i2c_add_adapter(adap);
> + if (ret) {
> + dev_err(hdmi->dev, "failed to add I2C adapter: %d\n", ret);
> + return ret;
> + }
> +
> + i2c_set_adapdata(adap, hdmi);
> +
> + return 0;
> +}
> +
> +static void zx_hdmi_phy_start(struct zx_hdmi *hdmi)
> +{
> + /* Copy from ZTE BSP code */
> + hdmi_writeb(hdmi, 0x222, 0x0);
> + hdmi_writeb(hdmi, 0x224, 0x4);
> + hdmi_writeb(hdmi, 0x909, 0x0);
> + hdmi_writeb(hdmi, 0x7b0, 0x90);
> + hdmi_writeb(hdmi, 0x7b1, 0x00);
> + hdmi_writeb(hdmi, 0x7b2, 0xa7);
> + hdmi_writeb(hdmi, 0x7b8, 0xaa);
> + hdmi_writeb(hdmi, 0x7b2, 0xa7);
> + hdmi_writeb(hdmi, 0x7b3, 0x0f);
> + hdmi_writeb(hdmi, 0x7b4, 0x0f);
> + hdmi_writeb(hdmi, 0x7b5, 0x55);
> + hdmi_writeb(hdmi, 0x7b7, 0x03);
> + hdmi_writeb(hdmi, 0x7b9, 0x12);
> + hdmi_writeb(hdmi, 0x7ba, 0x32);
> + hdmi_writeb(hdmi, 0x7bc, 0x68);
> + hdmi_writeb(hdmi, 0x7be, 0x40);
> + hdmi_writeb(hdmi, 0x7bf, 0x84);
> + hdmi_writeb(hdmi, 0x7c1, 0x0f);
> + hdmi_writeb(hdmi, 0x7c8, 0x02);
> + hdmi_writeb(hdmi, 0x7c9, 0x03);
> + hdmi_writeb(hdmi, 0x7ca, 0x40);
> + hdmi_writeb(hdmi, 0x7dc, 0x31);
> + hdmi_writeb(hdmi, 0x7e2, 0x04);
> + hdmi_writeb(hdmi, 0x7e0, 0x06);
> + hdmi_writeb(hdmi, 0x7cb, 0x68);
> + hdmi_writeb(hdmi, 0x7f9, 0x02);
> + hdmi_writeb(hdmi, 0x7b6, 0x02);
> + hdmi_writeb(hdmi, 0x7f3, 0x0);
> +}
> +
> +static void zx_hdmi_hw_init(struct zx_hdmi *hdmi)
> +{
> + /* Software reset */
> + hdmi_writeb(hdmi, PWD_SRST, 1);
> +
> + /* Enable pclk */
> + hdmi_writeb_mask(hdmi, CLKPWD, CLKPWD_PDIDCK, CLKPWD_PDIDCK);
> +
> + /* Enable HDMI for TX */
> + hdmi_writeb_mask(hdmi, FUNC_SEL, FUNC_HDMI_EN, FUNC_HDMI_EN);
> +
> + /* Enable deep color packet */
> + hdmi_writeb_mask(hdmi, P2T_CTRL, P2T_DC_PKT_EN, P2T_DC_PKT_EN);
> +
> + /* Enable HDMI/MHL mode for output */
> + hdmi_writeb_mask(hdmi, TEST_TXCTRL, TEST_TXCTRL_HDMI_MODE,
> + TEST_TXCTRL_HDMI_MODE);
> +
> + /* Configure reg_qc_sel */
> + hdmi_writeb(hdmi, HDMICTL4, 0x3);
> +
> + /* Enable interrupt */
> + hdmi_writeb_mask(hdmi, INTR1_MASK, INTR1_MONITOR_DETECT,
> + INTR1_MONITOR_DETECT);
> +
> + /* Clear reset for normal operation */
> + hdmi_writeb(hdmi, PWD_SRST, 0);
> +
> + /* Start up phy */
> + zx_hdmi_phy_start(hdmi);
> +}
> +
> +static int zx_hdmi_bind(struct device *dev, struct device *master, void *data)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct drm_device *drm = data;
> + struct resource *res;
> + struct zx_hdmi *hdmi;
> + int irq;
> + int ret;
> +
> + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
> + if (!hdmi)
> + return -ENOMEM;
> +
> + hdmi->dev = dev;
> + hdmi->drm = drm;
> + hdmi->inf = &vou_inf_hdmi;
> +
> + dev_set_drvdata(dev, hdmi);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + hdmi->mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(hdmi->mmio)) {
> + ret = PTR_ERR(hdmi->mmio);
> + dev_err(dev, "failed to remap hdmi region: %d\n", ret);
> + return ret;
> + }
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> +
> + hdmi->cec_clk = devm_clk_get(hdmi->dev, "osc_cec");
> + if (IS_ERR(hdmi->cec_clk)) {
> + ret = PTR_ERR(hdmi->cec_clk);
> + dev_err(dev, "failed to get cec_clk: %d\n", ret);
> + return ret;
> + }
> +
> + hdmi->osc_clk = devm_clk_get(hdmi->dev, "osc_clk");
> + if (IS_ERR(hdmi->osc_clk)) {
> + ret = PTR_ERR(hdmi->osc_clk);
> + dev_err(dev, "failed to get osc_clk: %d\n", ret);
> + return ret;
> + }
> +
> + hdmi->xclk = devm_clk_get(hdmi->dev, "xclk");
> + if (IS_ERR(hdmi->xclk)) {
> + ret = PTR_ERR(hdmi->xclk);
> + dev_err(dev, "failed to get xclk: %d\n", ret);
> + return ret;
> + }
> +
> + zx_hdmi_hw_init(hdmi);
> +
> + ret = clk_prepare_enable(hdmi->cec_clk);
> + if (ret) {
> + dev_err(dev, "failed to enable cec_clk: %d\n", ret);
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(hdmi->osc_clk);
> + if (ret) {
> + dev_err(dev, "failed to enable osc_clk: %d\n", ret);
> + goto disable_cec_clk;
> + }
> +
> + ret = clk_prepare_enable(hdmi->xclk);
> + if (ret) {
> + dev_err(dev, "failed to enable xclk: %d\n", ret);
> + goto disable_osc_clk;
> + }
Perhaps add a TODO above hdmi_hw_init() to move it and the clock
enables to .enable and conversely implement .disable?
> +
> +
> + ret = zx_hdmi_ddc_register(hdmi);
> + if (ret) {
> + dev_err(dev, "failed to register ddc: %d\n", ret);
> + goto disable_xclk;
> + }
> +
> + ret = zx_hdmi_register(drm, hdmi);
> + if (ret) {
> + dev_err(dev, "failed to register hdmi: %d\n", ret);
> + goto disable_xclk;
> + }
> +
> + ret = devm_request_threaded_irq(dev, irq, zx_hdmi_irq_handler,
> + zx_hdmi_irq_thread, IRQF_SHARED,
> + dev_name(dev), hdmi);
> + if (ret) {
> + dev_err(dev, "failed to request threaded irq: %d\n", ret);
> + goto disable_xclk;
> + }
> +
> + return 0;
> +
> +disable_xclk:
> + clk_disable_unprepare(hdmi->xclk);
> +disable_osc_clk:
> + clk_disable_unprepare(hdmi->osc_clk);
> +disable_cec_clk:
> + clk_disable_unprepare(hdmi->cec_clk);
> + return ret;
> +}
> +
> +static void zx_hdmi_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct zx_hdmi *hdmi = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(hdmi->xclk);
> + clk_disable_unprepare(hdmi->osc_clk);
> + clk_disable_unprepare(hdmi->cec_clk);
> +}
> +
> +static const struct component_ops zx_hdmi_component_ops = {
> + .bind = zx_hdmi_bind,
> + .unbind = zx_hdmi_unbind,
> +};
> +
> +static int zx_hdmi_probe(struct platform_device *pdev)
> +{
> + return component_add(&pdev->dev, &zx_hdmi_component_ops);
> +}
> +
> +static int zx_hdmi_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &zx_hdmi_component_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id zx_hdmi_of_match[] = {
> + { .compatible = "zte,zx296718-hdmi", },
> + { /* end */ },
> +};
> +MODULE_DEVICE_TABLE(of, zx_hdmi_of_match);
> +
> +struct platform_driver zx_hdmi_driver = {
> + .probe = zx_hdmi_probe,
> + .remove = zx_hdmi_remove,
> + .driver = {
> + .name = "zx-hdmi",
> + .of_match_table = zx_hdmi_of_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/zte/zx_plane.c b/drivers/gpu/drm/zte/zx_plane.c
> new file mode 100644
> index 000000000000..fdab1715bee5
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_plane.c
> @@ -0,0 +1,375 @@
> +/*
> + * Copyright 2016 Linaro Ltd.
> + * Copyright 2016 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_modeset_helper_vtables.h>
> +#include <drm/drm_plane_helper.h>
> +#include <drm/drmP.h>
> +
> +#include "zx_drm_drv.h"
> +#include "zx_plane.h"
> +#include "zx_vou.h"
> +
> +/* GL registers */
> +#define GL_CTRL0 0x00
> +#define GL_UPDATE BIT(5)
> +#define GL_CTRL1 0x04
> +#define GL_DATA_FMT_SHIFT 0
> +#define GL_DATA_FMT_MASK (0xf << GL_DATA_FMT_SHIFT)
> +#define GL_FMT_ARGB8888 0
> +#define GL_FMT_RGB888 1
> +#define GL_FMT_RGB565 2
> +#define GL_FMT_ARGB1555 3
> +#define GL_FMT_ARGB4444 4
> +#define GL_CTRL2 0x08
> +#define GL_GLOBAL_ALPHA_SHIFT 8
> +#define GL_GLOBAL_ALPHA_MASK (0xff << GL_GLOBAL_ALPHA_SHIFT)
> +#define GL_CTRL3 0x0c
> +#define GL_SCALER_BYPASS_MODE BIT(0)
> +#define GL_STRIDE 0x18
> +#define GL_ADDR 0x1c
> +#define GL_SRC_SIZE 0x38
> +#define GL_SRC_W_SHIFT 16
> +#define GL_SRC_W_MASK (0x3fff << GL_SRC_W_SHIFT)
> +#define GL_SRC_H_SHIFT 0
> +#define GL_SRC_H_MASK (0x3fff << GL_SRC_H_SHIFT)
> +#define GL_POS_START 0x9c
> +#define GL_POS_END 0xa0
> +#define GL_POS_X_SHIFT 16
> +#define GL_POS_X_MASK (0x1fff << GL_POS_X_SHIFT)
> +#define GL_POS_Y_SHIFT 0
> +#define GL_POS_Y_MASK (0x1fff << GL_POS_Y_SHIFT)
> +
> +#define GL_SRC_W(x) (((x) << GL_SRC_W_SHIFT) & GL_SRC_W_MASK)
> +#define GL_SRC_H(x) (((x) << GL_SRC_H_SHIFT) & GL_SRC_H_MASK)
> +#define GL_POS_X(x) (((x) << GL_POS_X_SHIFT) & GL_POS_X_MASK)
> +#define GL_POS_Y(x) (((x) << GL_POS_Y_SHIFT) & GL_POS_Y_MASK)
> +
> +/* CSC registers */
> +#define CSC_CTRL0 0x30
> +#define CSC_COV_MODE_SHIFT 16
> +#define CSC_COV_MODE_MASK (0xffff << CSC_COV_MODE_SHIFT)
> +#define CSC_BT601_IMAGE_RGB2YCBCR 0
> +#define CSC_BT601_IMAGE_YCBCR2RGB 1
> +#define CSC_BT601_VIDEO_RGB2YCBCR 2
> +#define CSC_BT601_VIDEO_YCBCR2RGB 3
> +#define CSC_BT709_IMAGE_RGB2YCBCR 4
> +#define CSC_BT709_IMAGE_YCBCR2RGB 5
> +#define CSC_BT709_VIDEO_RGB2YCBCR 6
> +#define CSC_BT709_VIDEO_YCBCR2RGB 7
> +#define CSC_BT2020_IMAGE_RGB2YCBCR 8
> +#define CSC_BT2020_IMAGE_YCBCR2RGB 9
> +#define CSC_BT2020_VIDEO_RGB2YCBCR 10
> +#define CSC_BT2020_VIDEO_YCBCR2RGB 11
> +#define CSC_WORK_ENABLE BIT(0)
> +
> +/* RSZ registers */
> +#define RSZ_SRC_CFG 0x00
> +#define RSZ_DEST_CFG 0x04
> +#define RSZ_ENABLE_CFG 0x14
> +
> +#define RSZ_VER_SHIFT 16
> +#define RSZ_VER_MASK (0xffff << RSZ_VER_SHIFT)
> +#define RSZ_HOR_SHIFT 0
> +#define RSZ_HOR_MASK (0xffff << RSZ_HOR_SHIFT)
> +
> +#define RSZ_VER(x) (((x) << RSZ_VER_SHIFT) & RSZ_VER_MASK)
> +#define RSZ_HOR(x) (((x) << RSZ_HOR_SHIFT) & RSZ_HOR_MASK)
> +
> +/* HBSC registers */
> +#define HBSC_SATURATION 0x00
> +#define HBSC_HUE 0x04
> +#define HBSC_BRIGHT 0x08
> +#define HBSC_CONTRAST 0x0c
> +#define HBSC_THRESHOLD_COL1 0x10
> +#define HBSC_THRESHOLD_COL2 0x14
> +#define HBSC_THRESHOLD_COL3 0x18
> +#define HBSC_CTRL0 0x28
> +#define HBSC_CTRL_EN BIT(2)
> +
> +struct zx_plane {
> + struct drm_plane plane;
> + void __iomem *layer;
> + void __iomem *csc;
> + void __iomem *hbsc;
> + void __iomem *rsz;
> +};
> +
> +#define to_zx_plane(plane) container_of(plane, struct zx_plane, plane)
> +
> +static const uint32_t gl_formats[] = {
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_RGB888,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_ARGB1555,
> + DRM_FORMAT_ARGB4444,
> +};
> +
> +static int zx_gl_plane_atomic_check(struct drm_plane *plane,
> + struct drm_plane_state *plane_state)
> +{
> + struct drm_framebuffer *fb = plane_state->fb;
> + struct drm_crtc *crtc = plane_state->crtc;
> + struct drm_crtc_state *crtc_state;
> + struct drm_rect clip;
> +
> + if (!crtc || !fb)
> + return 0;
> +
> + crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state,
> + crtc);
> + if (WARN_ON(!crtc_state))
> + return -EINVAL;
> +
> + /* plane must match crtc enable state */
> + if (crtc_state->enable != !!plane_state->crtc)
> + return -EINVAL;
> +
> + /* nothing to check when disabling or disabled */
> + if (!crtc_state->enable)
> + return 0;
I think you can shuffle things around here to read a bit clearer:
if (!crtc_state->enable)
return 0;
if (!plane_state->crtc)
return -EINVAL
> +
> + clip.x1 = 0;
> + clip.y1 = 0;
> + clip.x2 = crtc_state->adjusted_mode.hdisplay;
> + clip.y2 = crtc_state->adjusted_mode.vdisplay;
> +
> + return drm_plane_helper_check_state(plane_state, &clip,
> + DRM_PLANE_HELPER_NO_SCALING,
> + DRM_PLANE_HELPER_NO_SCALING,
> + false, true);
> +}
> +
> +static int zx_gl_get_fmt(uint32_t format)
> +{
> + switch (format) {
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XRGB8888:
> + return GL_FMT_ARGB8888;
> + case DRM_FORMAT_RGB888:
> + return GL_FMT_RGB888;
> + case DRM_FORMAT_RGB565:
> + return GL_FMT_RGB565;
> + case DRM_FORMAT_ARGB1555:
> + return GL_FMT_ARGB1555;
> + case DRM_FORMAT_ARGB4444:
> + return GL_FMT_ARGB4444;
> + default:
> + WARN_ONCE(1, "invalid pixel format %d\n", format);
> + return -EINVAL;
> + }
> +}
> +
> +static inline void zx_gl_set_update(struct zx_plane *zplane)
> +{
> + void __iomem *layer = zplane->layer;
> +
> + zx_writel_mask(layer + GL_CTRL0, GL_UPDATE, GL_UPDATE);
> +}
> +
> +static inline void zx_gl_rsz_set_update(struct zx_plane *zplane)
> +{
> + zx_writel(zplane->rsz + RSZ_ENABLE_CFG, 1);
> +}
> +
> +void zx_plane_set_update(struct drm_plane *plane)
> +{
> + struct zx_plane *zplane = to_zx_plane(plane);
> +
> + zx_gl_rsz_set_update(zplane);
> + zx_gl_set_update(zplane);
> +}
> +
> +static void zx_gl_rsz_setup(struct zx_plane *zplane, u32 src_w, u32 src_h,
> + u32 dst_w, u32 dst_h)
> +{
> + void __iomem *rsz = zplane->rsz;
> +
> + zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1));
> + zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1));
> +
> + zx_gl_rsz_set_update(zplane);
> +}
> +
> +static void zx_gl_plane_atomic_update(struct drm_plane *plane,
> + struct drm_plane_state *old_state)
> +{
> + struct zx_plane *zplane = to_zx_plane(plane);
> + struct drm_framebuffer *fb = plane->state->fb;
> + struct drm_gem_cma_object *cma_obj;
> + void __iomem *layer = zplane->layer;
> + void __iomem *csc = zplane->csc;
> + void __iomem *hbsc = zplane->hbsc;
> + u32 src_x, src_y, src_w, src_h;
> + u32 dst_x, dst_y, dst_w, dst_h;
> + unsigned int depth, bpp;
> + uint32_t format;
> + dma_addr_t paddr;
> + u32 stride;
> + int fmt;
> +
> + if (!fb)
> + return;
> +
> + format = fb->pixel_format;
> + stride = fb->pitches[0];
> +
> + src_x = plane->state->src_x >> 16;
> + src_y = plane->state->src_y >> 16;
> + src_w = plane->state->src_w >> 16;
> + src_h = plane->state->src_h >> 16;
> +
> + dst_x = plane->state->crtc_x;
> + dst_y = plane->state->crtc_y;
> + dst_w = plane->state->crtc_w;
> + dst_h = plane->state->crtc_h;
> +
> + drm_fb_get_bpp_depth(format, &depth, &bpp);
> +
> + cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
> + paddr = cma_obj->paddr + fb->offsets[0];
> + paddr += src_y * stride + src_x * bpp / 8;
> + zx_writel(layer + GL_ADDR, paddr);
> +
> + /* Set up source height/width register */
> + zx_writel(layer + GL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h));
> +
> + /* Set up start position register */
> + zx_writel(layer + GL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y));
> +
> + /* Set up end position register */
> + zx_writel(layer + GL_POS_END,
> + GL_POS_X(dst_x + dst_w) | GL_POS_Y(dst_y + dst_h));
> +
> + /* Set up stride register */
> + zx_writel(layer + GL_STRIDE, stride & 0xffff);
> +
> + /* Set up graphic layer data format */
> + fmt = zx_gl_get_fmt(format);
> + if (fmt >= 0)
> + zx_writel_mask(layer + GL_CTRL1, GL_DATA_FMT_MASK,
> + fmt << GL_DATA_FMT_SHIFT);
> +
> + /* Initialize global alpha with a sane value */
> + zx_writel_mask(layer + GL_CTRL2, GL_GLOBAL_ALPHA_MASK,
> + 0xff << GL_GLOBAL_ALPHA_SHIFT);
> +
> + /* Setup CSC for the GL */
> + if (dst_h > 720)
> + zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
> + CSC_BT709_IMAGE_RGB2YCBCR << CSC_COV_MODE_SHIFT);
> + else
> + zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
> + CSC_BT601_IMAGE_RGB2YCBCR << CSC_COV_MODE_SHIFT);
> + zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, CSC_WORK_ENABLE);
> +
> + /* Always use scaler since it exists (set for not bypass) */
> + zx_writel_mask(layer + GL_CTRL3, GL_SCALER_BYPASS_MODE,
> + GL_SCALER_BYPASS_MODE);
> +
> + zx_gl_rsz_setup(zplane, src_w, src_h, dst_w, dst_h);
> +
> + /* Enable HBSC block */
> + zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
> +
> + zx_gl_set_update(zplane);
> +}
> +
> +static const struct drm_plane_helper_funcs zx_gl_plane_helper_funcs = {
> + .atomic_check = zx_gl_plane_atomic_check,
> + .atomic_update = zx_gl_plane_atomic_update,
> +};
> +
> +static void zx_plane_destroy(struct drm_plane *plane)
> +{
> + drm_plane_helper_disable(plane);
> + drm_plane_cleanup(plane);
> +}
> +
> +static const struct drm_plane_funcs zx_plane_funcs = {
> + .update_plane = drm_atomic_helper_update_plane,
> + .disable_plane = drm_atomic_helper_disable_plane,
> + .destroy = zx_plane_destroy,
> + .reset = drm_atomic_helper_plane_reset,
> + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> +};
> +
> +static void zx_plane_hbsc_init(struct zx_plane *zplane)
> +{
> + void __iomem *hbsc = zplane->hbsc;
> +
> + /*
> + * Initialize HBSC block with a sane configuration per recommedation
> + * from ZTE BSP code.
> + */
> + zx_writel(hbsc + HBSC_SATURATION, 0x200);
> + zx_writel(hbsc + HBSC_HUE, 0x0);
> + zx_writel(hbsc + HBSC_BRIGHT, 0x0);
> + zx_writel(hbsc + HBSC_CONTRAST, 0x200);
> +
> + zx_writel(hbsc + HBSC_THRESHOLD_COL1, (0x3ac << 16) | 0x40);
> + zx_writel(hbsc + HBSC_THRESHOLD_COL2, (0x3c0 << 16) | 0x40);
> + zx_writel(hbsc + HBSC_THRESHOLD_COL3, (0x3c0 << 16) | 0x40);
> +}
> +
> +struct drm_plane *zx_plane_init(struct drm_device *drm, struct device *dev,
> + struct zx_layer_data *data,
> + enum drm_plane_type type)
> +{
> + const struct drm_plane_helper_funcs *helper;
> + struct zx_plane *zplane;
> + struct drm_plane *plane;
> + const uint32_t *formats;
> + unsigned int format_count;
> + int ret;
> +
> + zplane = devm_kzalloc(dev, sizeof(*zplane), GFP_KERNEL);
> + if (!zplane)
> + return ERR_PTR(-ENOMEM);
> +
> + plane = &zplane->plane;
> +
> + zplane->layer = data->layer;
> + zplane->hbsc = data->hbsc;
> + zplane->csc = data->csc;
> + zplane->rsz = data->rsz;
> +
> + zx_plane_hbsc_init(zplane);
> +
> + switch (type) {
> + case DRM_PLANE_TYPE_PRIMARY:
> + helper = &zx_gl_plane_helper_funcs;
> + formats = gl_formats;
> + format_count = ARRAY_SIZE(gl_formats);
> + break;
> + case DRM_PLANE_TYPE_OVERLAY:
> + /* TODO: add video layer (vl) support */
> + break;
> + default:
> + return ERR_PTR(-ENODEV);
> + }
> +
> + ret = drm_universal_plane_init(drm, plane, VOU_CRTC_MASK,
> + &zx_plane_funcs, formats, format_count,
> + type, NULL);
> + if (ret) {
> + dev_err(dev, "failed to init universal plane: %d\n", ret);
> + return ERR_PTR(ret);
> + }
> +
> + drm_plane_helper_add(plane, helper);
> +
> + return plane;
> +}
> diff --git a/drivers/gpu/drm/zte/zx_plane.h b/drivers/gpu/drm/zte/zx_plane.h
> new file mode 100644
> index 000000000000..2b82cd558d9d
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_plane.h
> @@ -0,0 +1,26 @@
> +/*
> + * Copyright 2016 Linaro Ltd.
> + * Copyright 2016 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __ZX_PLANE_H__
> +#define __ZX_PLANE_H__
> +
> +struct zx_layer_data {
> + void __iomem *layer;
> + void __iomem *csc;
> + void __iomem *hbsc;
> + void __iomem *rsz;
> +};
> +
> +struct drm_plane *zx_plane_init(struct drm_device *drm, struct device *dev,
> + struct zx_layer_data *data,
> + enum drm_plane_type type);
> +void zx_plane_set_update(struct drm_plane *plane);
> +
> +#endif /* __ZX_PLANE_H__ */
> diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c
> new file mode 100644
> index 000000000000..676c750d6009
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_vou.c
> @@ -0,0 +1,799 @@
> +/*
> + * Copyright 2016 Linaro Ltd.
> + * Copyright 2016 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_address.h>
> +#include <video/videomode.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_fb_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_plane_helper.h>
> +#include <drm/drmP.h>
> +
> +#include "zx_drm_drv.h"
> +#include "zx_plane.h"
> +#include "zx_vou.h"
> +
> +/* Sub-module offset */
> +#define MAIN_GL_OFFSET 0x130
> +#define MAIN_CSC_OFFSET 0x580
> +#define MAIN_HBSC_OFFSET 0x820
> +#define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */
> +
> +#define AUX_GL_OFFSET 0x200
> +#define AUX_CSC_OFFSET 0x5d0
> +#define AUX_HBSC_OFFSET 0x860
> +#define AUX_RSZ_OFFSET 0x800
> +
> +/* OSD (GPC_GLOBAL) registers */
> +#define OSD_INT_STA 0x04
> +#define OSD_INT_CLRSTA 0x08
> +#define OSD_INT_MSK 0x0c
> +#define OSD_INT_AUX_UPT BIT(14)
> +#define OSD_INT_MAIN_UPT BIT(13)
> +#define OSD_INT_GL1_LBW BIT(10)
> +#define OSD_INT_GL0_LBW BIT(9)
> +#define OSD_INT_VL2_LBW BIT(8)
> +#define OSD_INT_VL1_LBW BIT(7)
> +#define OSD_INT_VL0_LBW BIT(6)
> +#define OSD_INT_BUS_ERR BIT(3)
> +#define OSD_INT_CFG_ERR BIT(2)
> +#define OSD_INT_ERROR (\
> + OSD_INT_GL1_LBW | OSD_INT_GL0_LBW | \
> + OSD_INT_VL2_LBW | OSD_INT_VL1_LBW | OSD_INT_VL0_LBW | \
> + OSD_INT_BUS_ERR | OSD_INT_CFG_ERR \
> +)
> +#define OSD_INT_ENABLE (OSD_INT_ERROR | OSD_INT_AUX_UPT | OSD_INT_MAIN_UPT)
> +#define OSD_CTRL0 0x10
> +#define OSD_CTRL0_GL0_EN BIT(7)
> +#define OSD_CTRL0_GL0_SEL BIT(6)
> +#define OSD_CTRL0_GL1_EN BIT(5)
> +#define OSD_CTRL0_GL1_SEL BIT(4)
> +#define OSD_RST_CLR 0x1c
> +#define RST_PER_FRAME BIT(19)
> +
> +/* Main/Aux channel registers */
> +#define OSD_MAIN_CHN 0x470
> +#define OSD_AUX_CHN 0x4d0
> +#define CHN_CTRL0 0x00
> +#define CHN_ENABLE BIT(0)
> +#define CHN_CTRL1 0x04
> +#define CHN_SCREEN_W_SHIFT 18
> +#define CHN_SCREEN_W_MASK (0x1fff << CHN_SCREEN_W_SHIFT)
> +#define CHN_SCREEN_H_SHIFT 5
> +#define CHN_SCREEN_H_MASK (0x1fff << CHN_SCREEN_H_SHIFT)
> +#define CHN_UPDATE 0x08
> +
> +/* TIMING_CTRL registers */
> +#define TIMING_TC_ENABLE 0x04
> +#define AUX_TC_EN BIT(1)
> +#define MAIN_TC_EN BIT(0)
> +#define FIR_MAIN_ACTIVE 0x08
> +#define FIR_AUX_ACTIVE 0x0c
> +#define V_ACTIVE_SHIFT 16
> +#define V_ACTIVE_MASK (0xffff << V_ACTIVE_SHIFT)
> +#define H_ACTIVE_SHIFT 0
> +#define H_ACTIVE_MASK (0xffff << H_ACTIVE_SHIFT)
> +#define FIR_MAIN_H_TIMING 0x10
> +#define FIR_MAIN_V_TIMING 0x14
> +#define FIR_AUX_H_TIMING 0x18
> +#define FIR_AUX_V_TIMING 0x1c
> +#define SYNC_WIDE_SHIFT 22
> +#define SYNC_WIDE_MASK (0x3ff << SYNC_WIDE_SHIFT)
> +#define BACK_PORCH_SHIFT 11
> +#define BACK_PORCH_MASK (0x7ff << BACK_PORCH_SHIFT)
> +#define FRONT_PORCH_SHIFT 0
> +#define FRONT_PORCH_MASK (0x7ff << FRONT_PORCH_SHIFT)
> +#define TIMING_CTRL 0x20
> +#define AUX_POL_SHIFT 3
> +#define AUX_POL_MASK (0x7 << AUX_POL_SHIFT)
> +#define MAIN_POL_SHIFT 0
> +#define MAIN_POL_MASK (0x7 << MAIN_POL_SHIFT)
> +#define POL_DE_SHIFT 2
> +#define POL_VSYNC_SHIFT 1
> +#define POL_HSYNC_SHIFT 0
> +#define TIMING_INT_CTRL 0x24
> +#define TIMING_INT_STATE 0x28
> +#define TIMING_INT_AUX_FRAME BIT(3)
> +#define TIMING_INT_MAIN_FRAME BIT(1)
> +#define TIMING_INT_AUX_FRAME_SEL_VSW (0x2 << 10)
> +#define TIMING_INT_MAIN_FRAME_SEL_VSW (0x2 << 6)
> +#define TIMING_INT_ENABLE (\
> + TIMING_INT_MAIN_FRAME_SEL_VSW | TIMING_INT_AUX_FRAME_SEL_VSW | \
> + TIMING_INT_MAIN_FRAME | TIMING_INT_AUX_FRAME \
> +)
> +#define TIMING_MAIN_SHIFT 0x2c
> +#define TIMING_AUX_SHIFT 0x30
> +#define H_SHIFT_VAL 0x0048
> +#define TIMING_MAIN_PI_SHIFT 0x68
> +#define TIMING_AUX_PI_SHIFT 0x6c
> +#define H_PI_SHIFT_VAL 0x000f
> +
> +#define V_ACTIVE(x) (((x) << V_ACTIVE_SHIFT) & V_ACTIVE_MASK)
> +#define H_ACTIVE(x) (((x) << H_ACTIVE_SHIFT) & H_ACTIVE_MASK)
> +
> +#define SYNC_WIDE(x) (((x) << SYNC_WIDE_SHIFT) & SYNC_WIDE_MASK)
> +#define BACK_PORCH(x) (((x) << BACK_PORCH_SHIFT) & BACK_PORCH_MASK)
> +#define FRONT_PORCH(x) (((x) << FRONT_PORCH_SHIFT) & FRONT_PORCH_MASK)
> +
> +/* DTRC registers */
> +#define DTRC_F0_CTRL 0x2c
> +#define DTRC_F1_CTRL 0x5c
> +#define DTRC_DECOMPRESS_BYPASS BIT(17)
> +#define DTRC_DETILE_CTRL 0x68
> +#define TILE2RASTESCAN_BYPASS_MODE BIT(30)
> +#define DETILE_ARIDR_MODE_MASK (0x3 << 0)
> +#define DETILE_ARID_ALL 0
> +#define DETILE_ARID_IN_ARIDR 1
> +#define DETILE_ARID_BYP_BUT_ARIDR 2
> +#define DETILE_ARID_IN_ARIDR2 3
> +#define DTRC_ARID 0x6c
> +#define DTRC_ARID3_SHIFT 24
> +#define DTRC_ARID3_MASK (0xff << DTRC_ARID3_SHIFT)
> +#define DTRC_ARID2_SHIFT 16
> +#define DTRC_ARID2_MASK (0xff << DTRC_ARID2_SHIFT)
> +#define DTRC_ARID1_SHIFT 8
> +#define DTRC_ARID1_MASK (0xff << DTRC_ARID1_SHIFT)
> +#define DTRC_ARID0_SHIFT 0
> +#define DTRC_ARID0_MASK (0xff << DTRC_ARID0_SHIFT)
> +#define DTRC_DEC2DDR_ARID 0x70
> +
> +#define DTRC_ARID3(x) (((x) << DTRC_ARID3_SHIFT) & DTRC_ARID3_MASK)
> +#define DTRC_ARID2(x) (((x) << DTRC_ARID2_SHIFT) & DTRC_ARID2_MASK)
> +#define DTRC_ARID1(x) (((x) << DTRC_ARID1_SHIFT) & DTRC_ARID1_MASK)
> +#define DTRC_ARID0(x) (((x) << DTRC_ARID0_SHIFT) & DTRC_ARID0_MASK)
> +
> +/* VOU_CTRL registers */
> +#define VOU_INF_EN 0x00
> +#define VOU_INF_CH_SEL 0x04
> +#define VOU_INF_DATA_SEL 0x08
> +#define VOU_SOFT_RST 0x14
> +#define VOU_CLK_SEL 0x18
> +#define VOU_CLK_GL1_SEL BIT(5)
> +#define VOU_CLK_GL0_SEL BIT(4)
> +#define VOU_CLK_REQEN 0x20
> +#define VOU_CLK_EN 0x24
> +
> +/* OTFPPU_CTRL registers */
> +#define OTFPPU_RSZ_DATA_SOURCE 0x04
> +
I find the register definitions pretty distracting here (and elsewhere
in the driver), I suppose my personal preference would be to hide them
in the headers.
> +#define GL_NUM 2
> +#define VL_NUM 3
> +
> +enum vou_chn_type {
> + VOU_CHN_MAIN,
> + VOU_CHN_AUX,
> +};
> +
> +struct zx_crtc_regs {
> + u32 fir_active;
> + u32 fir_htiming;
> + u32 fir_vtiming;
> + u32 timing_shift;
> + u32 timing_pi_shift;
> +};
> +
> +static const struct zx_crtc_regs main_crtc_regs = {
> + .fir_active = FIR_MAIN_ACTIVE,
> + .fir_htiming = FIR_MAIN_H_TIMING,
> + .fir_vtiming = FIR_MAIN_V_TIMING,
> + .timing_shift = TIMING_MAIN_SHIFT,
> + .timing_pi_shift = TIMING_MAIN_PI_SHIFT,
> +};
> +
> +static const struct zx_crtc_regs aux_crtc_regs = {
> + .fir_active = FIR_AUX_ACTIVE,
> + .fir_htiming = FIR_AUX_H_TIMING,
> + .fir_vtiming = FIR_AUX_V_TIMING,
> + .timing_shift = TIMING_AUX_SHIFT,
> + .timing_pi_shift = TIMING_AUX_PI_SHIFT,
> +};
> +
> +struct zx_crtc_bits {
> + u32 polarity_mask;
> + u32 polarity_shift;
> + u32 tc_enable;
> + u32 gl_enable;
> +};
> +
> +static const struct zx_crtc_bits main_crtc_bits = {
> + .polarity_mask = MAIN_POL_MASK,
> + .polarity_shift = MAIN_POL_SHIFT,
> + .tc_enable = MAIN_TC_EN,
> + .gl_enable = OSD_CTRL0_GL0_EN,
> +};
> +
> +static const struct zx_crtc_bits aux_crtc_bits = {
> + .polarity_mask = AUX_POL_MASK,
> + .polarity_shift = AUX_POL_SHIFT,
> + .tc_enable = AUX_TC_EN,
> + .gl_enable = OSD_CTRL0_GL1_EN,
> +};
> +
> +struct zx_crtc {
> + struct drm_crtc crtc;
> + struct drm_plane *primary;
> + struct zx_vou_hw *vou;
> + void __iomem *chnreg;
> + const struct zx_crtc_regs *regs;
> + const struct zx_crtc_bits *bits;
> + enum vou_chn_type chn_type;
> + struct clk *pixclk;
> +};
> +
> +#define to_zx_crtc(x) container_of(x, struct zx_crtc, crtc)
> +
> +struct zx_vou_hw {
> + struct device *dev;
> + void __iomem *osd;
> + void __iomem *timing;
> + void __iomem *vouctl;
> + void __iomem *otfppu;
> + void __iomem *dtrc;
> + struct clk *axi_clk;
> + struct clk *ppu_clk;
> + struct clk *main_clk;
> + struct clk *aux_clk;
> + struct zx_crtc *main_crtc;
> + struct zx_crtc *aux_crtc;
> +};
> +
> +static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
> +{
> + struct zx_crtc *zcrtc = to_zx_crtc(crtc);
> +
> + return zcrtc->vou;
> +}
> +
> +void vou_inf_enable(const struct vou_inf *inf, struct drm_crtc *crtc)
> +{
> + struct zx_crtc *zcrtc = to_zx_crtc(crtc);
> + struct zx_vou_hw *vou = zcrtc->vou;
> + bool is_main = zcrtc->chn_type == VOU_CHN_MAIN;
> + u32 data_sel_shift = inf->id << 1;
> +
> + /* Select data format */
> + zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
> + inf->data_sel << data_sel_shift);
> +
> + /* Select channel */
> + zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << inf->id,
> + zcrtc->chn_type << inf->id);
> +
> + /* Select interface clocks */
> + zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits,
> + is_main ? 0 : inf->clocks_sel_bits);
> +
> + /* Enable interface clocks */
> + zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits,
> + inf->clocks_en_bits);
> +
> + /* Enable the device */
> + zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << inf->id, 1 << inf->id);
> +}
> +
> +void vou_inf_disable(const struct vou_inf *inf, struct drm_crtc *crtc)
> +{
> + struct zx_vou_hw *vou = crtc_to_vou(crtc);
> +
> + /* Disable the device */
> + zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << inf->id, 0);
> +
> + /* Disable interface clocks */
> + zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);
> +}
> +
> +static inline void vou_chn_set_update(struct zx_crtc *zcrtc)
> +{
> + zx_writel(zcrtc->chnreg + CHN_UPDATE, 1);
> +}
> +
> +static void zx_crtc_enable(struct drm_crtc *crtc)
> +{
> + struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> + struct zx_crtc *zcrtc = to_zx_crtc(crtc);
> + struct zx_vou_hw *vou = zcrtc->vou;
> + const struct zx_crtc_regs *regs = zcrtc->regs;
> + const struct zx_crtc_bits *bits = zcrtc->bits;
> + struct videomode vm;
> + u32 pol = 0;
> + u32 val;
> + int ret;
> +
> + drm_display_mode_to_videomode(mode, &vm);
> +
> + /* Set up timing parameters */
> + val = V_ACTIVE(vm.vactive - 1);
> + val |= H_ACTIVE(vm.hactive - 1);
> + zx_writel(vou->timing + regs->fir_active, val);
> +
> + val = SYNC_WIDE(vm.hsync_len - 1);
> + val |= BACK_PORCH(vm.hback_porch - 1);
> + val |= FRONT_PORCH(vm.hfront_porch - 1);
> + zx_writel(vou->timing + regs->fir_htiming, val);
Yeah, this is much easier on the eyes (IMO)!
> +
> + val = SYNC_WIDE(vm.vsync_len - 1);
> + val |= BACK_PORCH(vm.vback_porch - 1);
> + val |= FRONT_PORCH(vm.vfront_porch - 1);
> + zx_writel(vou->timing + regs->fir_vtiming, val);
> +
> + /* Set up polarities */
> + if (vm.flags & DISPLAY_FLAGS_VSYNC_LOW)
> + pol |= 1 << POL_VSYNC_SHIFT;
> + if (vm.flags & DISPLAY_FLAGS_HSYNC_LOW)
> + pol |= 1 << POL_HSYNC_SHIFT;
> +
> + zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask,
> + pol << bits->polarity_shift);
> +
> + /* Setup SHIFT register by following what ZTE BSP does */
> + zx_writel(vou->timing + regs->timing_shift, H_SHIFT_VAL);
> + zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL);
> +
> + /* Enable TIMING_CTRL */
> + zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable,
> + bits->tc_enable);
> +
> + /* Configure channel screen size */
> + zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_W_MASK,
> + vm.hactive << CHN_SCREEN_W_SHIFT);
> + zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_H_MASK,
> + vm.vactive << CHN_SCREEN_H_SHIFT);
> +
> + /* Update channel */
> + vou_chn_set_update(zcrtc);
> +
> + /* Enable channel */
> + zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, CHN_ENABLE);
> +
> + /* Enable Graphic Layer */
> + zx_writel_mask(vou->osd + OSD_CTRL0, bits->gl_enable,
> + bits->gl_enable);
> +
> + drm_crtc_vblank_on(crtc);
> +
> + ret = clk_set_rate(zcrtc->pixclk, mode->clock * 1000);
> + if (ret) {
> + dev_warn(vou->dev, "failed to set pixclk rate: %d\n", ret);
> + return;
> + }
> +
> + ret = clk_prepare_enable(zcrtc->pixclk);
> + if (ret)
> + dev_warn(vou->dev, "failed to enable pixclk: %d\n", ret);
> +}
> +
> +static void zx_crtc_disable(struct drm_crtc *crtc)
> +{
> + struct zx_crtc *zcrtc = to_zx_crtc(crtc);
> + const struct zx_crtc_bits *bits = zcrtc->bits;
> + struct zx_vou_hw *vou = zcrtc->vou;
> +
> + clk_disable_unprepare(zcrtc->pixclk);
> +
> + drm_crtc_vblank_off(crtc);
> +
> + /* Disable Graphic Layer */
> + zx_writel_mask(vou->osd + OSD_CTRL0, bits->gl_enable, 0);
> +
> + /* Disable channel */
> + zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, 0);
> +
> + /* Disable TIMING_CTRL */
> + zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0);
> +}
> +
> +static void zx_crtc_atomic_begin(struct drm_crtc *crtc,
> + struct drm_crtc_state *state)
> +{
> + struct drm_pending_vblank_event *event = crtc->state->event;
> +
> + if (!event)
> + return;
> +
> + crtc->state->event = NULL;
> +
> + spin_lock_irq(&crtc->dev->event_lock);
> + if (drm_crtc_vblank_get(crtc) == 0)
> + drm_crtc_arm_vblank_event(crtc, event);
> + else
> + drm_crtc_send_vblank_event(crtc, event);
> + spin_unlock_irq(&crtc->dev->event_lock);
> +}
> +
> +static const struct drm_crtc_helper_funcs zx_crtc_helper_funcs = {
> + .enable = zx_crtc_enable,
> + .disable = zx_crtc_disable,
> + .atomic_begin = zx_crtc_atomic_begin,
> +};
> +
> +static const struct drm_crtc_funcs zx_crtc_funcs = {
> + .destroy = drm_crtc_cleanup,
> + .set_config = drm_atomic_helper_set_config,
> + .page_flip = drm_atomic_helper_page_flip,
> + .reset = drm_atomic_helper_crtc_reset,
> + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> +};
> +
> +static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou,
> + enum vou_chn_type chn_type)
> +{
> + struct device *dev = vou->dev;
> + struct zx_layer_data data;
> + struct zx_crtc *zcrtc;
> + int ret;
> +
> + zcrtc = devm_kzalloc(dev, sizeof(*zcrtc), GFP_KERNEL);
> + if (!zcrtc)
> + return -ENOMEM;
> +
> + zcrtc->vou = vou;
> + zcrtc->chn_type = chn_type;
> +
> + if (chn_type == VOU_CHN_MAIN) {
> + data.layer = vou->osd + MAIN_GL_OFFSET;
> + data.csc = vou->osd + MAIN_CSC_OFFSET;
> + data.hbsc = vou->osd + MAIN_HBSC_OFFSET;
> + data.rsz = vou->otfppu + MAIN_RSZ_OFFSET;
> + zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;
> + zcrtc->regs = &main_crtc_regs;
> + zcrtc->bits = &main_crtc_bits;
> + } else {
> + data.layer = vou->osd + AUX_GL_OFFSET;
> + data.csc = vou->osd + AUX_CSC_OFFSET;
> + data.hbsc = vou->osd + AUX_HBSC_OFFSET;
> + data.rsz = vou->otfppu + AUX_RSZ_OFFSET;
> + zcrtc->chnreg = vou->osd + OSD_AUX_CHN;
> + zcrtc->regs = &aux_crtc_regs;
> + zcrtc->bits = &aux_crtc_bits;
> + }
> +
> + zcrtc->pixclk = devm_clk_get(dev, (chn_type == VOU_CHN_MAIN) ?
> + "main_wclk" : "aux_wclk");
> + if (IS_ERR(zcrtc->pixclk)) {
> + ret = PTR_ERR(zcrtc->pixclk);
> + dev_err(dev, "failed to get pix clk: %d\n", ret);
> + return ret;
> + }
> +
> + zcrtc->primary = zx_plane_init(drm, dev, &data, DRM_PLANE_TYPE_PRIMARY);
> + if (IS_ERR(zcrtc->primary)) {
> + ret = PTR_ERR(zcrtc->primary);
> + dev_err(dev, "failed to init primary plane: %d\n", ret);
> + return ret;
> + }
> +
> + ret = drm_crtc_init_with_planes(drm, &zcrtc->crtc, zcrtc->primary, NULL,
> + &zx_crtc_funcs, NULL);
> + if (ret) {
> + dev_err(dev, "failed to init drm crtc: %d\n", ret);
> + return ret;
> + }
> +
> + drm_crtc_helper_add(&zcrtc->crtc, &zx_crtc_helper_funcs);
> +
> + if (chn_type == VOU_CHN_MAIN)
> + vou->main_crtc = zcrtc;
> + else
> + vou->aux_crtc = zcrtc;
> +
> + return 0;
> +}
> +
> +static inline struct drm_crtc *zx_find_crtc(struct drm_device *drm, int pipe)
> +{
> + struct drm_crtc *crtc;
> + int i = 0;
> +
> + list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
> + if (i++ == pipe)
> + return crtc;
> +
> + return NULL;
> +}
We have drm_plane_from_index, it seems like at least 2 drivers would
benefit from drm_crtc_from_index. Either way, you should probably
change this code to compare pipe to crtc->index instead of rolling
your own index counter.
> +
> +int zx_vou_enable_vblank(struct drm_device *drm, unsigned int pipe)
> +{
> + struct drm_crtc *crtc;
> + struct zx_vou_hw *vou;
> +
> + crtc = zx_find_crtc(drm, pipe);
> + if (!crtc)
> + return 0;
> +
> + vou = crtc_to_vou(crtc);
> +
> + if (pipe == 0)
> + zx_writel_mask(vou->timing + TIMING_INT_CTRL,
> + TIMING_INT_MAIN_FRAME, TIMING_INT_MAIN_FRAME);
> + else
> + zx_writel_mask(vou->timing + TIMING_INT_CTRL,
> + TIMING_INT_AUX_FRAME, TIMING_INT_AUX_FRAME);
> +
It seems like this could also benefit from crtc_bits/crtc_regs
> + return 0;
> +}
> +
> +void zx_vou_disable_vblank(struct drm_device *drm, unsigned int pipe)
> +{
> + struct drm_crtc *crtc;
> + struct zx_vou_hw *vou;
> +
> + crtc = zx_find_crtc(drm, pipe);
> + if (!crtc)
> + return;
> +
> + vou = crtc_to_vou(crtc);
> +
> + if (pipe == 0)
> + zx_writel_mask(vou->timing + TIMING_INT_CTRL,
> + TIMING_INT_MAIN_FRAME, 0);
> + else
> + zx_writel_mask(vou->timing + TIMING_INT_CTRL,
> + TIMING_INT_AUX_FRAME, 0);
> +}
> +
> +static irqreturn_t vou_irq_handler(int irq, void *dev_id)
> +{
> + struct zx_vou_hw *vou = dev_id;
> + u32 state;
> +
> + /* Handle TIMING_CTRL frame interrupts */
> + state = zx_readl(vou->timing + TIMING_INT_STATE);
> + zx_writel(vou->timing + TIMING_INT_STATE, state);
> +
> + if (state & TIMING_INT_MAIN_FRAME)
> + drm_crtc_handle_vblank(&vou->main_crtc->crtc);
> +
> + if (state & TIMING_INT_AUX_FRAME)
> + drm_crtc_handle_vblank(&vou->aux_crtc->crtc);
> +
> + /* Handle OSD interrupts */
> + state = zx_readl(vou->osd + OSD_INT_STA);
> + zx_writel(vou->osd + OSD_INT_CLRSTA, state);
> +
> + if (state & OSD_INT_MAIN_UPT) {
> + vou_chn_set_update(vou->main_crtc);
> + zx_plane_set_update(vou->main_crtc->primary);
> + }
> +
> + if (state & OSD_INT_AUX_UPT) {
> + vou_chn_set_update(vou->aux_crtc);
> + zx_plane_set_update(vou->aux_crtc->primary);
> + }
> +
> + if (state & OSD_INT_ERROR)
> + dev_err(vou->dev, "OSD ERROR: 0x%08x!\n", state);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void vou_dtrc_init(struct zx_vou_hw *vou)
> +{
> + /* Clear bit for bypass by ID */
> + zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL,
> + TILE2RASTESCAN_BYPASS_MODE, 0);
> +
> + /* Select ARIDR mode */
> + zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL, DETILE_ARIDR_MODE_MASK,
> + DETILE_ARID_IN_ARIDR);
> +
> + /* Bypass decompression for both frames */
> + zx_writel_mask(vou->dtrc + DTRC_F0_CTRL, DTRC_DECOMPRESS_BYPASS,
> + DTRC_DECOMPRESS_BYPASS);
> + zx_writel_mask(vou->dtrc + DTRC_F1_CTRL, DTRC_DECOMPRESS_BYPASS,
> + DTRC_DECOMPRESS_BYPASS);
> +
> + /* Set up ARID register */
> + zx_writel(vou->dtrc + DTRC_ARID, DTRC_ARID3(0xf) | DTRC_ARID2(0xe) |
> + DTRC_ARID1(0xf) | DTRC_ARID0(0xe));
> +}
> +
> +static void vou_hw_init(struct zx_vou_hw *vou)
> +{
> + /* Set GL0 to main channel and GL1 to aux channel */
> + zx_writel_mask(vou->osd + OSD_CTRL0, OSD_CTRL0_GL0_SEL, 0);
> + zx_writel_mask(vou->osd + OSD_CTRL0, OSD_CTRL0_GL1_SEL,
> + OSD_CTRL0_GL1_SEL);
> +
> + /* Release reset for all VOU modules */
> + zx_writel(vou->vouctl + VOU_SOFT_RST, ~0);
> +
> + /* Select main clock for GL0 and aux clock for GL1 module */
> + zx_writel_mask(vou->vouctl + VOU_CLK_SEL, VOU_CLK_GL0_SEL, 0);
> + zx_writel_mask(vou->vouctl + VOU_CLK_SEL, VOU_CLK_GL1_SEL,
> + VOU_CLK_GL1_SEL);
> +
> + /* Enable clock auto-gating for all VOU modules */
> + zx_writel(vou->vouctl + VOU_CLK_REQEN, ~0);
> +
> + /* Enable all VOU module clocks */
> + zx_writel(vou->vouctl + VOU_CLK_EN, ~0);
> +
> + /* Clear both OSD and TIMING_CTRL interrupt state */
> + zx_writel(vou->osd + OSD_INT_CLRSTA, ~0);
> + zx_writel(vou->timing + TIMING_INT_STATE, ~0);
> +
> + /* Enable OSD and TIMING_CTRL interrrupts */
> + zx_writel(vou->osd + OSD_INT_MSK, OSD_INT_ENABLE);
> + zx_writel(vou->timing + TIMING_INT_CTRL, TIMING_INT_ENABLE);
> +
> + /* Select GPC as input to gl/vl scaler as a sane default setting */
> + zx_writel(vou->otfppu + OTFPPU_RSZ_DATA_SOURCE, 0x2a);
> +
> + /*
> + * Needs to reset channel and layer logic per frame when frame starts
> + * to get VOU work properly.
> + */
> + zx_writel_mask(vou->osd + OSD_RST_CLR, RST_PER_FRAME, RST_PER_FRAME);
> +
> + vou_dtrc_init(vou);
> +}
> +
> +static int zx_crtc_bind(struct device *dev, struct device *master, void *data)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct drm_device *drm = data;
> + struct zx_vou_hw *vou;
> + struct resource *res;
> + int irq;
> + int ret;
> +
> + vou = devm_kzalloc(dev, sizeof(*vou), GFP_KERNEL);
> + if (!vou)
> + return -ENOMEM;
> +
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "osd");
> + vou->osd = devm_ioremap_resource(dev, res);
> + if (IS_ERR(vou->osd)) {
> + ret = PTR_ERR(vou->osd);
> + dev_err(dev, "failed to remap osd region: %d\n", ret);
> + return ret;
> + }
> +
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "timing_ctrl");
> + vou->timing = devm_ioremap_resource(dev, res);
> + if (IS_ERR(vou->timing)) {
> + ret = PTR_ERR(vou->timing);
> + dev_err(dev, "failed to remap timing_ctrl region: %d\n", ret);
> + return ret;
> + }
> +
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dtrc");
> + vou->dtrc = devm_ioremap_resource(dev, res);
> + if (IS_ERR(vou->dtrc)) {
> + ret = PTR_ERR(vou->dtrc);
> + dev_err(dev, "failed to remap dtrc region: %d\n", ret);
> + return ret;
> + }
> +
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vou_ctrl");
> + vou->vouctl = devm_ioremap_resource(dev, res);
> + if (IS_ERR(vou->vouctl)) {
> + ret = PTR_ERR(vou->vouctl);
> + dev_err(dev, "failed to remap vou_ctrl region: %d\n", ret);
> + return ret;
> + }
> +
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otfppu");
> + vou->otfppu = devm_ioremap_resource(dev, res);
> + if (IS_ERR(vou->otfppu)) {
> + ret = PTR_ERR(vou->otfppu);
> + dev_err(dev, "failed to remap otfppu region: %d\n", ret);
> + return ret;
> + }
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> +
> + vou->axi_clk = devm_clk_get(dev, "aclk");
> + if (IS_ERR(vou->axi_clk)) {
> + ret = PTR_ERR(vou->axi_clk);
> + dev_err(dev, "failed to get axi_clk: %d\n", ret);
> + return ret;
> + }
> +
> + vou->ppu_clk = devm_clk_get(dev, "ppu_wclk");
> + if (IS_ERR(vou->ppu_clk)) {
> + ret = PTR_ERR(vou->ppu_clk);
> + dev_err(dev, "failed to get ppu_clk: %d\n", ret);
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(vou->axi_clk);
> + if (ret) {
> + dev_err(dev, "failed to enable axi_clk: %d\n", ret);
> + return ret;
> + }
> +
> + clk_prepare_enable(vou->ppu_clk);
> + if (ret) {
> + dev_err(dev, "failed to enable ppu_clk: %d\n", ret);
> + goto disable_axi_clk;
> + }
> +
> + vou->dev = dev;
> + dev_set_drvdata(dev, vou);
> +
> + vou_hw_init(vou);
> +
> + ret = devm_request_irq(dev, irq, vou_irq_handler, 0, "zx_vou", vou);
> + if (ret < 0) {
> + dev_err(dev, "failed to request vou irq: %d\n", ret);
> + goto disable_ppu_clk;
> + }
> +
> + ret = zx_crtc_init(drm, vou, VOU_CHN_MAIN);
> + if (ret) {
> + dev_err(dev, "failed to init main channel crtc: %d\n", ret);
> + goto disable_ppu_clk;
> + }
> +
> + ret = zx_crtc_init(drm, vou, VOU_CHN_AUX);
> + if (ret) {
> + dev_err(dev, "failed to init aux channel crtc: %d\n", ret);
> + goto disable_ppu_clk;
> + }
> +
> + return 0;
> +
> +disable_ppu_clk:
> + clk_disable_unprepare(vou->ppu_clk);
> +disable_axi_clk:
> + clk_disable_unprepare(vou->axi_clk);
> + return ret;
> +}
> +
> +static void zx_crtc_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct zx_vou_hw *vou = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(vou->axi_clk);
> + clk_disable_unprepare(vou->ppu_clk);
> +}
> +
> +static const struct component_ops zx_crtc_component_ops = {
> + .bind = zx_crtc_bind,
> + .unbind = zx_crtc_unbind,
> +};
> +
> +static int zx_crtc_probe(struct platform_device *pdev)
> +{
> + return component_add(&pdev->dev, &zx_crtc_component_ops);
> +}
> +
> +static int zx_crtc_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &zx_crtc_component_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id zx_crtc_of_match[] = {
> + { .compatible = "zte,zx296718-dpc", },
> + { /* end */ },
> +};
> +MODULE_DEVICE_TABLE(of, zx_crtc_of_match);
> +
> +struct platform_driver zx_crtc_driver = {
> + .probe = zx_crtc_probe,
> + .remove = zx_crtc_remove,
> + .driver = {
> + .name = "zx-crtc",
> + .of_match_table = zx_crtc_of_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/zte/zx_vou.h b/drivers/gpu/drm/zte/zx_vou.h
> new file mode 100644
> index 000000000000..349e06cd86f4
> --- /dev/null
> +++ b/drivers/gpu/drm/zte/zx_vou.h
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright 2016 Linaro Ltd.
> + * Copyright 2016 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __ZX_VOU_H__
> +#define __ZX_VOU_H__
> +
> +#define VOU_CRTC_MASK 0x3
> +
> +/* VOU output interfaces */
> +enum vou_inf_id {
> + VOU_HDMI = 0,
> + VOU_RGB_LCD = 1,
> + VOU_TV_ENC = 2,
> + VOU_MIPI_DSI = 3,
> + VOU_LVDS = 4,
> + VOU_VGA = 5,
> +};
> +
> +enum vou_inf_data_sel {
> + VOU_YUV444 = 0,
> + VOU_RGB_101010 = 1,
> + VOU_RGB_888 = 2,
> + VOU_RGB_666 = 3,
> +};
> +
> +struct vou_inf {
> + enum vou_inf_id id;
> + enum vou_inf_data_sel data_sel;
> + u32 clocks_en_bits;
> + u32 clocks_sel_bits;
> +};
> +
> +void vou_inf_enable(const struct vou_inf *inf, struct drm_crtc *crtc);
> +void vou_inf_disable(const struct vou_inf *inf, struct drm_crtc *crtc);
> +
> +int zx_vou_enable_vblank(struct drm_device *drm, unsigned int pipe);
> +void zx_vou_disable_vblank(struct drm_device *drm, unsigned int pipe);
> +
> +#endif /* __ZX_VOU_H__ */
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH V6 00/10] dmaengine: qcom_hidma: add MSI interrupt support
From: Sinan Kaya @ 2016-10-20 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020094838.GY2467@localhost>
Hi Vinod,
On 10/20/2016 2:48 AM, Vinod Koul wrote:
>> 6:
>> > * rebase 4.9 kernel
> Why???
>
This is more for me. There is nothing special about 4.9 that impacts hidma.
It just means that I retested the code against 4.9-rc1 kernel.
>
> I already told you that I have applied 6 in the last version, please dont
> send me stuff which is already applied :(
I couldn't find your applied branch on git yesterday. That's why, I sent you
the whole thing so that you can pick the last 4 ones. You don't need to reapply
the first 6. Better to have everything than missing code.
slave-dma git://git.infradead.org/users/vkoul/slave-dma.git (fetch)
slave-dma git://git.infradead.org/users/vkoul/slave-dma.git (push)
If you prefer a reduced list, please make your current changelist available on
one of the branches on git, I can reapply, test and send only the remaining ones.
Sinan
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH 3/8] ARM: gr8: Add the UART3
From: Chen-Yu Tsai @ 2016-10-20 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b62c8661eb3c2d72e61511794a3ab1b43f005805.1476951078.git-series.maxime.ripard@free-electrons.com>
On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The GR8 has access to the UART3 controller, which was missing in the
> DTSI. Add it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply
* [PATCH 4/8] ARM: gr8: Fix typo in the i2s mclk pin group
From: Chen-Yu Tsai @ 2016-10-20 14:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f1c79380c34fcc2a1c1ff75ca91177de3b7380a9.1476951078.git-series.maxime.ripard@free-electrons.com>
On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> There was a dumb copy and paste mistake here, fix it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply
* [PATCH 5/8] ARM: gr8: Add missing pwm channel 1 pin
From: Chen-Yu Tsai @ 2016-10-20 14:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0df42247c3348e7f6aed945e5669cec87f96f7ac.1476951078.git-series.maxime.ripard@free-electrons.com>
On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The PWM controller has two different channels, but only the first pin was
> exposed in the DTSI. Add the other one.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
> ---
> arch/arm/boot/dts/ntc-gr8.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/ntc-gr8.dtsi b/arch/arm/boot/dts/ntc-gr8.dtsi
> index 74aff795e723..fad7381630f3 100644
> --- a/arch/arm/boot/dts/ntc-gr8.dtsi
> +++ b/arch/arm/boot/dts/ntc-gr8.dtsi
> @@ -854,6 +854,13 @@
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
>
> + pwm1_pins_a: pwm1 at 0 {
Nit: really don't need "_a" and "@0" here.
> + allwinner,pins = "PG13";
> + allwinner,function = "pwm1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> spdif_tx_pins_a: spdif at 0 {
> allwinner,pins = "PB10";
> allwinner,function = "spdif";
> --
> git-series 0.8.10
^ permalink raw reply
* [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit
From: Dinh Nguyen @ 2016-10-20 14:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020071913.rlka3or4c7fzjpyv@pengutronix.de>
On 10/20/2016 02:19 AM, Steffen Trumtrar wrote:
>> + cdns,tslch-ns = <4>;
>> +
>> + partition at qspi-boot {
>> + /* 8MB for raw data. */
>> + label = "Flash 0 Raw Data";
>> + reg = <0x0 0x800000>;
>> + };
>> +
>> + partition at qspi-rootfs {
>> + /* 120MB for jffs2 data. */
>> + label = "Flash 0 jffs2 Filesystem";
>> + reg = <0x800000 0x7800000>;
>> + };
>> + };
>> +};
>> +
>
> What is the current preferred way of handling the partitions?
> This doesn't fit my Sockit configuration for example. So I would always
> have to patch the devicetree.
I'm not 100% sure on this. Graham, do you have any insight?
>
> On the Socrates I didn't specify the partitions, because I did not
> want to force a specific configuration.
>
I know that on Arria10, we needed a specific configuration.
Dinh
^ permalink raw reply
* [PATCH 6/8] ARM: gr8: Add UART2 pins
From: Chen-Yu Tsai @ 2016-10-20 14:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0c1f98755c7dd1764dcd89a599f182a0face286f.1476951078.git-series.maxime.ripard@free-electrons.com>
On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The UART2 pins were missing from the DTSI. Add them.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply
* [PATCH 7/8] ARM: gr8: Add UART3 pins
From: Chen-Yu Tsai @ 2016-10-20 14:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cc81030de43c26dfc15ad9a9e525188ad8fb8ec9.1476951078.git-series.maxime.ripard@free-electrons.com>
On Thu, Oct 20, 2016 at 4:12 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The UART3 pins were missing from the DTSI. Add them.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply
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