* [PATCH 2/3] arm64: arch_timer: Work around QorIQ Erratum Hisilicon-161x01
From: Ding Tianhong @ 2016-10-23 3:21 UTC (permalink / raw)
To: linux-arm-kernel
Erratum Hisilicon-161x01 says that the ARM generic timer counter "has the
potential to contain an erroneous value when the timer value changes".
Accesses to TVAL (both read and write) are also affected due to the implicit counter
read. Accesses to CVAL are not affected.
The workaround is to reread TVAL and count registers until successive
reads return the limited range value (32) by back-to-back reads. Writes to TVAL are
replaced with an equivalent write to CVAL.
The workaround is enabled if the hisilicon,erratum-161x01 property is found in
the timer node in the device tree. This can be overridden with the
clocksource.arm_arch_timer.hisilicon-161x01 boot parameter, which allows KVM
users to enable the workaround until a mechanism is implemented to
automatically communicate this information.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
Documentation/arm64/silicon-errata.txt | 1 +
Documentation/kernel-parameters.txt | 9 ++
arch/arm64/include/asm/arch_timer.h | 41 +++++++--
drivers/clocksource/Kconfig | 14 ++-
drivers/clocksource/arm_arch_timer.c | 153 +++++++++++++++++++++++++++------
5 files changed, 182 insertions(+), 36 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 405da11..3a79803 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -63,3 +63,4 @@ stable kernels.
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
+| Hisilicon | Hip05/Hip06/Hip07 | #161x01 | HISILICON_ERRATUM_161x01|
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 6fa1d8a..175f349 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -707,6 +707,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
erratum. If unspecified, the workaround is
enabled based on the device tree.
+ clocksource.arm_arch_timer.hisilicon-161x01=
+ [ARM64]
+ Format: <bool>
+ Enable/disable the workaround of Hisilicon
+ erratum 161x01. This can be useful for KVM
+ guests, if the guest device tree doesn't show the
+ erratum. If unspecified, the workaround is
+ enabled based on the device tree.
+
clearcpuid=BITNUM [X86]
Disable CPUID feature X for the kernel. See
arch/x86/include/asm/cpufeatures.h for the valid bit
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index eaa5bbe..6b510db 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -29,17 +29,24 @@
#include <clocksource/arm_arch_timer.h>
-#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161X01)
extern struct static_key_false arch_timer_read_ool_enabled;
-#define needs_fsl_a008585_workaround() \
+extern struct arch_timer_erratum_workaround *erratum_workaround;
+#define needs_timer_erratum_workaround() \
static_branch_unlikely(&arch_timer_read_ool_enabled)
#else
-#define needs_fsl_a008585_workaround() false
+#define needs_timer_erratum_workaround() false
#endif
-u32 __fsl_a008585_read_cntp_tval_el0(void);
-u32 __fsl_a008585_read_cntv_tval_el0(void);
-u64 __fsl_a008585_read_cntvct_el0(void);
+struct clock_event_device;
+
+struct arch_timer_erratum_workaround {
+ int erratum;
+ u32 (*read_cntp_tval_el0)(void);
+ u32 (*read_cntv_tval_el0)(void);
+ u64 (*read_cntvct_el0)(void);
+};
+extern struct arch_timer_erratum_workaround *erratum_workaround;
/*
* The number of retries is an arbitrary value well beyond the highest number
@@ -59,16 +66,34 @@ u64 __fsl_a008585_read_cntvct_el0(void);
_new; \
})
+#define __hisi_161x01_read_reg(reg) ({ \
+ u64 _old, _new; \
+ int _retries = 200; \
+ \
+ do { \
+ _old = read_sysreg(reg); \
+ _new = read_sysreg(reg); \
+ _retries--; \
+ } while (unlikely((_new - _old) >> 5) && _retries); \
+ \
+ WARN_ON_ONCE(!_retries); \
+ _new; \
+})
+
+
+
#define arch_timer_reg_read_stable(reg) \
({ \
u64 _val; \
- if (needs_fsl_a008585_workaround()) \
- _val = __fsl_a008585_read_##reg(); \
+ if (needs_timer_erratum_workaround()) \
+ _val = erratum_workaround->read_##reg(); \
else \
_val = read_sysreg(reg); \
_val; \
})
+
+
/*
* These register accessors are marked inline so the compiler can
* nicely work out which register we want, and chuck away the rest of
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8a753fd..fcfcdc7 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -312,8 +312,20 @@ config FSL_ERRATUM_A008585
help
This option enables a workaround for Freescale/NXP Erratum
A-008585 ("ARM generic timer may contain an erroneous
- value"). The workaround will only be active if the
+ value"). The workaround will be active if the
fsl,erratum-a008585 property is found in the timer node.
+ This can be overridden with the clocksource.arm_arch_timer.fsl-a008585
+ boot parameter.
+
+config HISILICON_ERRATUM_161X01
+ bool "Workaround for Hisilicon Erratum 161201"
+ default y
+ depends on ARM_ARCH_TIMER && ARM64
+ help
+ This option enables a workaround for Hisilicon Erratum
+ 161201. The workaround will be active if the hisi,erratum-161201
+ property is found in the timer node. This can be overridden with
+ the clocksource.arm_arch_timer.hisi-161201 boot parameter.
config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 73c487d..e1cf0ad 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -90,16 +90,23 @@ static int __init early_evtstrm_cfg(char *buf)
}
early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
-/*
- * Architected system timer support.
- */
+#define FSL_A008585 1
+#define HISILICON_161X01 2
+
+struct arch_timer_erratum_workaround *erratum_workaround;
+
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161X01)
+static int arch_timer_uses_erratum = 0;
-#ifdef CONFIG_FSL_ERRATUM_A008585
DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
+#endif
-static int fsl_a008585_enable = -1;
+/*
+ * Architected system timer support.
+ */
+#ifdef CONFIG_FSL_ERRATUM_A008585
static int __init early_fsl_a008585_cfg(char *buf)
{
int ret;
@@ -109,28 +116,96 @@ static int __init early_fsl_a008585_cfg(char *buf)
if (ret)
return ret;
- fsl_a008585_enable = val;
+ if (val)
+ arch_timer_uses_erratum = FSL_A008585;
+
return 0;
}
early_param("clocksource.arm_arch_timer.fsl-a008585", early_fsl_a008585_cfg);
-u32 __fsl_a008585_read_cntp_tval_el0(void)
+u32 fsl_a008585_read_cntp_tval_el0(void)
{
return __fsl_a008585_read_reg(cntp_tval_el0);
}
-u32 __fsl_a008585_read_cntv_tval_el0(void)
+u32 fsl_a008585_read_cntv_tval_el0(void)
{
return __fsl_a008585_read_reg(cntv_tval_el0);
}
-u64 __fsl_a008585_read_cntvct_el0(void)
+u64 fsl_a008585_read_cntvct_el0(void)
{
return __fsl_a008585_read_reg(cntvct_el0);
}
-EXPORT_SYMBOL(__fsl_a008585_read_cntvct_el0);
+EXPORT_SYMBOL(fsl_a008585_read_cntvct_el0);
+#else
+u32 fsl_a008585_read_cntp_tval_el0(void)
+{
+ return 0;
+}
+
+u32 fsl_a008585_read_cntv_tval_el0(void)
+{
+ return 0;
+}
+
+u64 fsl_a008585_read_cntvct_el0(void)
+{
+ return 0;
+}
+EXPORT_SYMBOL(fsl_a008585_read_cntvct_el0);
#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#ifdef CONFIG_HISILICON_ERRATUM_161X01
+static int __init early_hisi_161x01_cfg(char *buf)
+{
+ int ret;
+ bool val;
+
+ ret = strtobool(buf, &val);
+ if (ret)
+ return ret;
+
+ if (val)
+ arch_timer_uses_erratum = HISILICON_161X01;
+
+ return 0;
+}
+early_param("clocksource.arm_arch_timer.hisilicon-161x01", early_hisi_161x01_cfg);
+
+u32 hisi_161x01_read_cntp_tval_el0(void)
+{
+ return __hisi_161x01_read_reg(cntp_tval_el0);
+}
+
+u32 hisi_161x01_read_cntv_tval_el0(void)
+{
+ return __hisi_161x01_read_reg(cntv_tval_el0);
+}
+
+u64 hisi_161x01_read_cntvct_el0(void)
+{
+ return __hisi_161x01_read_reg(cntvct_el0);
+}
+EXPORT_SYMBOL(hisi_161x01_read_cntvct_el0);
+#else
+u32 hisi_161x01_read_cntp_tval_el0(void)
+{
+ return 0;
+}
+
+u32 hisi_161x01_read_cntv_tval_el0(void)
+{
+ return 0;
+}
+
+u64 hisi_161x01_read_cntvct_el0(void)
+{
+ return 0;
+}
+EXPORT_SYMBOL(hisi_161x01_read_cntvct_el0);
+#endif
+
static __always_inline
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
struct clock_event_device *clk)
@@ -280,8 +355,8 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-#ifdef CONFIG_FSL_ERRATUM_A008585
-static __always_inline void fsl_a008585_set_next_event(const int access,
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161X01)
+static __always_inline void erratum_set_next_event(const int access,
unsigned long evt, struct clock_event_device *clk)
{
unsigned long ctrl;
@@ -299,20 +374,35 @@ static __always_inline void fsl_a008585_set_next_event(const int access,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-static int fsl_a008585_set_next_event_virt(unsigned long evt,
+static int erratum_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
+ erratum_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
return 0;
}
-static int fsl_a008585_set_next_event_phys(unsigned long evt,
+static int erratum_set_next_event_phys(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
+ erratum_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
return 0;
}
-#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#endif /* CONFIG_FSL_ERRATUM_A008585 || CONFIG_HISILICON_ERRATUM_161X01 */
+
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161X01)
+static struct arch_timer_erratum_workaround arch_timer_erratum[] = {
+{
+ .erratum = FSL_A008585,
+ .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
+ .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
+},{
+ .erratum = HISILICON_161X01,
+ .read_cntp_tval_el0 = hisi_161x01_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = hisi_161x01_read_cntv_tval_el0,
+ .read_cntvct_el0 = hisi_161x01_read_cntvct_el0,
+} };
+#endif
static int arch_timer_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
@@ -342,16 +432,16 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
return 0;
}
-static void fsl_a008585_set_sne(struct clock_event_device *clk)
+static void erratum_set_sne(struct clock_event_device *clk)
{
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161X01)
if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
return;
if (arch_timer_uses_ppi == VIRT_PPI)
- clk->set_next_event = fsl_a008585_set_next_event_virt;
+ clk->set_next_event = erratum_set_next_event_virt;
else
- clk->set_next_event = fsl_a008585_set_next_event_phys;
+ clk->set_next_event = erratum_set_next_event_phys;
#endif
}
@@ -384,7 +474,7 @@ static void __arch_timer_setup(unsigned type,
BUG();
}
- fsl_a008585_set_sne(clk);
+ erratum_set_sne(clk);
} else {
clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
clk->name = "arch_mem_timer";
@@ -890,12 +980,21 @@ static int __init arch_timer_of_init(struct device_node *np)
arch_timer_c3stop = !of_property_read_bool(np, "always-on");
-#ifdef CONFIG_FSL_ERRATUM_A008585
- if (fsl_a008585_enable < 0)
- fsl_a008585_enable = of_property_read_bool(np, "fsl,erratum-a008585");
- if (fsl_a008585_enable) {
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161X01)
+ if (!arch_timer_uses_erratum) {
+ if (IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) &&
+ of_property_read_bool(np, "fsl,erratum-a008585"))
+ arch_timer_uses_erratum = FSL_A008585;
+ else if (IS_ENABLED(CONFIG_HISI_ERRATUM_161X01) &&
+ of_property_read_bool(np, "hisilicon,erratum-161x01"))
+ arch_timer_uses_erratum = HISILICON_161X01;
+ }
+
+ if (arch_timer_uses_erratum) {
+ erratum_workaround = &arch_timer_erratum[arch_timer_uses_erratum - 1];
+ pr_info("Enabling workaround for %s\n", arch_timer_uses_erratum == FSL_A008585 ?
+ "FSL erratum A-008585" : "HISILICON ERRATUM 161x01");
static_branch_enable(&arch_timer_read_ool_enabled);
- pr_info("Enabling workaround for FSL erratum A-008585\n");
}
#endif
--
1.9.0
^ permalink raw reply related
* [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum
From: Ding Tianhong @ 2016-10-23 3:21 UTC (permalink / raw)
To: linux-arm-kernel
This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward. So, describe it
in the device tree.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ef5fbe9..26bc837 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,12 @@ to deliver its interrupts via SPIs.
This also affects writes to the tval register, due to the implicit
counter read.
+- hisilicon,erratum-161x01 : A boolean property. Indicates the presence of
+ QorIQ erratum 161201, which says that reading the counter is
+ unreliable unless the small range of value is returned by back-to-back reads.
+ This also affects writes to the tval register, due to the implicit
+ counter read.
+
** Optional properties:
- arm,cpu-registers-not-fw-configured : Firmware does not initialize
--
1.9.0
^ permalink raw reply related
* [linux-sunxi] [PATCH v5 0/7] ARM: ASoC: drm: sun8i: Add DE2 HDMI audio and video
From: Chen-Yu Tsai @ 2016-10-23 1:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1477142934.git.moinejf@free.fr>
On Sat, Oct 22, 2016 at 9:28 PM, Jean-Francois Moine <moinejf@free.fr> wrote:
> This patchset series adds HDMI audio and video support to the Allwinner
> sun8i SoCs which include the display engine 2 (DE2).
>
> A first submission in January for video on the H3 could not enter into
> the mainline kernel due to the lack of license headers in Allwinner's
> sources.
>
> Recently, an announce about Tina OS for the R series
> https://www.youtube.com/watch?v=h7KD-6HblAU
> was followed by the upload of a new linux-3.4 source tree
> https://github.com/tinalinux/linux-3.4
> with files containing GPL headers.
>
> Well, I don't know if these sources are really from Allwinner, but
> anyway, this is the opportunity to propose a new version of my DRM
> HDMI driver.
Could you clarify about this bit? Did you just clean up Allwinner's
existing drivers? Or just use them as reference? Either way I think
this deserves some mention in all your copyright headers.
Otherwise what difference does the new release make?
Regards
ChenYu
>
> v5:
> - add overlay plane
> - add audio support
> - add support for the A83T
> - add back the HDMI driver
> - many bug fixes
> v4:
> - drivers/clk/sunxi/Makefile was missing (Emil Velikov)
> v3:
> - add the hardware cursor
> - simplify and fix the DE2 init sequences
> - generation for all SUNXI SoCs (Andre Przywara)
> v2:
> - remove the HDMI driver
> - remarks from Chen-Yu Tsai and Russell King
> - DT documentation added
>
> Jean-Francois Moine (7):
> drm: sunxi: Add a basic DRM driver for Allwinner DE2
> ASoC: sunxi: Add a simple HDMI CODEC
> drm: sunxi: add DE2 HDMI support
> ASoC: sunxi: Add sun8i I2S driver
> ARM: dts: sun8i-h3: add HDMI audio and video nodes
> ARM: dts: sun8i-h3: Add HDMI audio and video to the Banana Pi M2+
> ARM: dts: sun8i-h3: Add HDMI audio and video to the Orange PI 2
>
> .../devicetree/bindings/display/sunxi/hdmi.txt | 52 ++
> .../bindings/display/sunxi/sunxi-de2.txt | 83 ++
> .../devicetree/bindings/sound/sun4i-i2s.txt | 38 +-
> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 17 +
> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 17 +
> arch/arm/boot/dts/sun8i-h3.dtsi | 67 ++
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/sunxi/Kconfig | 29 +
> drivers/gpu/drm/sunxi/Makefile | 9 +
> drivers/gpu/drm/sunxi/de2_crtc.c | 475 +++++++++++
> drivers/gpu/drm/sunxi/de2_crtc.h | 63 ++
> drivers/gpu/drm/sunxi/de2_de.c | 591 +++++++++++++
> drivers/gpu/drm/sunxi/de2_drm.h | 47 ++
> drivers/gpu/drm/sunxi/de2_drv.c | 378 +++++++++
> drivers/gpu/drm/sunxi/de2_hdmi.c | 396 +++++++++
> drivers/gpu/drm/sunxi/de2_hdmi.h | 40 +
> drivers/gpu/drm/sunxi/de2_hdmi_io.c | 927 +++++++++++++++++++++
> drivers/gpu/drm/sunxi/de2_hdmi_io.h | 25 +
> drivers/gpu/drm/sunxi/de2_plane.c | 119 +++
> include/sound/sunxi_hdmi.h | 23 +
> sound/soc/codecs/Kconfig | 9 +
> sound/soc/codecs/Makefile | 2 +
> sound/soc/codecs/sunxi-hdmi.c | 106 +++
> sound/soc/sunxi/Kconfig | 8 +
> sound/soc/sunxi/Makefile | 3 +
> sound/soc/sunxi/sun8i-i2s.c | 700 ++++++++++++++++
> 27 files changed, 4222 insertions(+), 5 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/sunxi/hdmi.txt
> create mode 100644 Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
> create mode 100644 drivers/gpu/drm/sunxi/Kconfig
> create mode 100644 drivers/gpu/drm/sunxi/Makefile
> create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.h
> create mode 100644 drivers/gpu/drm/sunxi/de2_de.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_drm.h
> create mode 100644 drivers/gpu/drm/sunxi/de2_drv.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi.h
> create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi_io.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_hdmi_io.h
> create mode 100644 drivers/gpu/drm/sunxi/de2_plane.c
> create mode 100644 include/sound/sunxi_hdmi.h
> create mode 100644 sound/soc/codecs/sunxi-hdmi.c
> create mode 100644 sound/soc/sunxi/sun8i-i2s.c
>
> --
> 2.10.1
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe at googlegroups.com.
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^ permalink raw reply
* [linux-sunxi] [PATCH v5 4/7] ASoC: sunxi: Add sun8i I2S driver
From: Chen-Yu Tsai @ 2016-10-23 1:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <bee315efb909c1ee8b5fe7d3aeb9a33d713cb562.1477142934.git.moinejf@free.fr>
Hi,
On Fri, Oct 21, 2016 at 4:36 PM, Jean-Francois Moine <moinejf@free.fr> wrote:
> This patch adds I2S support to sun8i SoCs as the A83T and H3.
>
> Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> ---
> Note: This driver is closed to the sun4i-i2s except that:
> - it handles the H3
If it's close to sun4i-i2s, you should probably rework that one to support
the newer SoCs.
> - it creates the sound card (with sun4i-i2s, the sound card is created
> by the CODECs)
I think this is wrong. I2S is only the DAI. You typically have a separate
platform driver for the whole card, or just use simple-card.
> ---
> .../devicetree/bindings/sound/sun4i-i2s.txt | 38 +-
> sound/soc/sunxi/Kconfig | 8 +
> sound/soc/sunxi/Makefile | 3 +
> sound/soc/sunxi/sun8i-i2s.c | 700 +++++++++++++++++++++
> 4 files changed, 744 insertions(+), 5 deletions(-)
> create mode 100644 sound/soc/sunxi/sun8i-i2s.c
>
> diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
> index 7b526ec..2fb0a7a 100644
> --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
> @@ -1,4 +1,4 @@
> -* Allwinner A10 I2S controller
> +* Allwinner A10/A38T/H3 I2S controller
>
> The I2S bus (Inter-IC sound bus) is a serial link for digital
> audio data transfer between devices in the system.
> @@ -6,20 +6,30 @@ audio data transfer between devices in the system.
> Required properties:
>
> - compatible: should be one of the followings
> - - "allwinner,sun4i-a10-i2s"
> + - "allwinner,sun4i-a10-i2s"
> + "allwinner,sun8i-a83t-i2s"
> + "allwinner,sun8i-h3-i2s"
> - reg: physical base address of the controller and length of memory mapped
> region.
> -- interrupts: should contain the I2S interrupt.
> - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
> Documentation/devicetree/bindings/dma/dma.txt
> -- dma-names: should include "tx" and "rx".
> +- dma-names: must include "tx" and/or "rx".
> - clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
> - clock-names: should contain followings:
> - "apb" : clock for the I2S bus interface
> - "mod" : module clock for the I2S controller
> - #sound-dai-cells : Must be equal to 0
>
> -Example:
> +Optional properties:
> +
> +- interrupts: I2S interrupt
> +- resets: phandle to the reset of the device
> +
> +Required nodes:
> +
> + - port: link to the associated CODEC (DAC, HDMI...)
Note here you are changing an existing binding, adding a required node.
If it were truely different, you probably should've started a new binding.
Regards
ChenYu
> +
> +Example 1:
>
> i2s0: i2s at 01c22400 {
> #sound-dai-cells = <0>;
> @@ -32,3 +42,21 @@ i2s0: i2s at 01c22400 {
> <&dma SUN4I_DMA_NORMAL 3>;
> dma-names = "rx", "tx";
> };
> +
> +Example 2:
> +
> +i2s2: i2s at 1c22800 {
> + compatible = "allwinner,sun8i-a83t-i2s";
> + reg = <0x01c22800 0x60>;
> + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_I2S2>;
> + dmas = <&dma 27>;
> + dma-names = "tx";
> + status = "disabled";
> + port {
> + i2s2_hdmi: endpoint {
> + remote-endpoint = <&hdmi_i2s2>;
> + };
> + };
> +};
^ permalink raw reply
* [PATCH V4 3/3] Revert "ACPI, PCI, IRQ: separate ISA penalty calculation"
From: Bjorn Helgaas @ 2016-10-22 23:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8dcd59ac-815b-da71-a3f2-ba533c4182c9@codeaurora.org>
On Thu, Oct 20, 2016 at 07:58:57PM -0700, Sinan Kaya wrote:
> On 10/20/2016 7:31 PM, Bjorn Helgaas wrote:
> ...
> > And I don't think it fixes a user-visible problem, so it doesn't need
> > to be applied immediately. I'm not sure this is worth doing by
> > itself; maybe it should wait until we can do more cleanup and think
> > about all these issues together?
>
> It does fix the PCI_USING penalty assignment.
>
> if (link->irq.active && link->irq.active == irq)
> penalty += PIRQ_PENALTY_PCI_USING;
>
>
> If we drop this patch, then we need
> [PATCH V3 1/3] ACPI, PCI IRQ: add PCI_USING penalty for ISA interrupts
>
> http://www.gossamer-threads.com/lists/linux/kernel/2547605
>
> as somebody needs to increment the penalty with PCI_USING when IRQ is assigned
> for a given ISA IRQ.
>
> We might as well take [PATCH V4 1/3], [PATCH V4 2/3] and [PATCH V3 1/3]
> for this regression.
It sounds like either V3 1/3 or V4 3/3 will fix the regression. The
V3 1/3 patch is much smaller and essentially makes this piece look
like it did in v4.6.
The V4 3/3 patch removes acpi_irq_penalty_init() and compensates by
using acpi_irq_pci_sharing_penalty() for ISA IRQs again. But
acpi_irq_penalty_init() added PIRQ_PENALTY_PCI_POSSIBLE for _CRS, and
only if there was no _PRS, while acpi_irq_pci_sharing_penalty() always
adds PIRQ_PENALTY_PCI_USING for _CRS, regardless of whether _PRS
exists.
Since V4 3/3 is so much bigger and makes this quite subtle change in
how _CRS is handled, I like V3 1/3 better.
Are we all set to go now? I think I've acked the patches you
mentioned.
Bjorn
^ permalink raw reply
* [PATCH V3 1/3] ACPI, PCI IRQ: add PCI_USING penalty for ISA interrupts
From: Bjorn Helgaas @ 2016-10-22 23:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476505867-24599-2-git-send-email-okaya@codeaurora.org>
On Sat, Oct 15, 2016 at 12:31:05AM -0400, Sinan Kaya wrote:
> The change introduced in commit 103544d86976 ("ACPI,PCI,IRQ: reduce
> resource requirements") removed PCI_USING penalty from
> acpi_pci_link_allocate function as there is no longer a fixed size penalty
> array for both PCI interrupts greater than 16.
>
> The array size has been reduced to 16 and array name got prefixed as ISA
> since it only is accountable for the ISA interrupts.
>
> The original change in commit 103544d86976 ("ACPI,PCI,IRQ: reduce
> resource requirements") removed penalty assignment in the code for PCI
> thinking that we will add the penalty later in acpi_irq_pci_sharing_penalty
> function.
>
> However, this function only gets called if the IRQ number is greater than
> 16 and acpi_irq_get_penalty function gets called before ACPI start in
> acpi_isa_irq_available and acpi_penalize_isa_irq functions. We can't rely
> on iterating the link list.
>
> We need to add the PCI_USING penalty for ISA interrupts too if the link is
> in use and matches our ISA IRQ number.
I think the history about the array size is more than is necessary for this
changelog. I think the useful part is something like this:
ACPI: pci_link: Include PIRQ_PENALTY_PCI_USING for ISA IRQs
103544d86976 ("ACPI,PCI,IRQ: reduce resource requirements") replaced
the addition of PIRQ_PENALTY_PCI_USING in acpi_pci_link_allocate()
with an addition in acpi_irq_pci_sharing_penalty(), but f7eca374f000
("ACPI,PCI,IRQ: separate ISA penalty calculation") removed the use
of acpi_irq_pci_sharing_penalty() for ISA IRQs.
Therefore, PIRQ_PENALTY_PCI_USING is missing from ISA IRQs used by
interrupt links. Include that penalty by adding it in the
acpi_pci_link_allocate() path.
Fixes: f7eca374f000 ("ACPI,PCI,IRQ: separate ISA penalty calculation")
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/acpi/pci_link.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c
> index c983bf7..a212709 100644
> --- a/drivers/acpi/pci_link.c
> +++ b/drivers/acpi/pci_link.c
> @@ -619,6 +619,10 @@ static int acpi_pci_link_allocate(struct acpi_pci_link *link)
> acpi_device_bid(link->device));
> return -ENODEV;
> } else {
> + if (link->irq.active < ACPI_MAX_ISA_IRQS)
> + acpi_isa_irq_penalty[link->irq.active] +=
> + PIRQ_PENALTY_PCI_USING;
> +
> printk(KERN_WARNING PREFIX "%s [%s] enabled at IRQ %d\n",
> acpi_device_name(link->device),
> acpi_device_bid(link->device), link->irq.active);
> --
> 1.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH V4 2/3] Revert "ACPI,PCI,IRQ: remove SCI penalize function"
From: Bjorn Helgaas @ 2016-10-22 23:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161021015814.GC31044@localhost>
On Thu, Oct 20, 2016 at 08:58:14PM -0500, Bjorn Helgaas wrote:
> On Wed, Oct 19, 2016 at 06:21:03PM -0400, Sinan Kaya wrote:
> > The SCI penalize function was removed in two steps (first refactor
> > and then remove) and these changes are reverted here in one go.
> >
> > The commit 103544d86976 ("ACPI,PCI,IRQ: reduce resource requirements")
> > refactored the original code so that SCI penalty is calculated dynamically
> > by the time get_penalty function is called. That change is partially
> > reverted here, specifically for the SCI IRQ alone.
> >
> > The SCI penalize function was finally dropped by commit 9e5ed6d1fb87
> > ("ACPI,PCI,IRQ: remove SCI penalize function") that replaced the old SCI
> > penalty API with penalty calculation carried out dynamically and based
> > on the acpi_gbl_FADT.sci_interrupt value.
> >
> > However, that new algorithm relies on the accurate setting of IRQ
> > types and that doesn't happen early enough on some platforms which
> > leads to incorrect penalty assignments for PCI IRQs. In those cases,
> > irq_get_trigger_type() returns incorrect values for the IRQs in
> > question, because they have not been registered yet by the time the
> > penalties are calculated.
> >
> > To fix this problem, we only need to fix the penalty for the SCI interrupt.
> > It seems better to add a single "sci_penalty" variable, set it to
> > PIRQ_PENALTY_PCI_USING if it's level/low or PIRQ_PENALTY_ISA_ALWAYS
> > otherwise, and add "sci_penalty" in when appropriate. That should fix it
> > for *any* SCI IRQ, not just those less than 256, and we don't have to add
> > these extra penalty table entries that are all unused (except possibly for
> > one entry if we have an SCI in the 16-255 range).
> >
> > For this reason, revert commit 9e5ed6d1fb87 ("ACPI,PCI,IRQ: remove SCI
> > penalize function") completely to restore the correct behavior.
>
> I like this patch fine, except for the changelog. I don't think it's
> useful to describe this as a revert and give all the historical
> details. I think the important part is something like this:
>
> We previously used irq_get_trigger_type(irq) to help compute the
> penalty for the SCI, but that depends on the SCI having been
> registered already. Add acpi_penalize_sci_irq() so platforms can
> tell us the SCI IRQ, trigger, and polarity so we can compute the
> penalty even before the SCI has been registered.
I think this is actually the critical patch that fixes the regression
reported by Ondrej, so the changelog really should include details
about the regression, e.g., something like this:
ACPI: pci_link: Penalize SCI correctly
Ondrej reported that IRQs stopped working in v4.7 on several
platforms. A typical scenario, from Ondrej's VT82C694X/694X, is:
ACPI: Using PIC for interrupt routing
ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 5 6 7 10 *11 12 14 15)
ACPI: No IRQ available for PCI Interrupt Link [LNKA]
8139too 0000:00:0f.0: PCI INT A: no GSI
We're using PIC routing, so acpi_irq_balance == 0, and LNKA is already
active at IRQ 11. In that case, acpi_pci_link_allocate() only tries
to use the active IRQ (IRQ 11) which also happens to be the SCI.
We should penalize the SCI by PIRQ_PENALTY_PCI_USING, but
irq_get_trigger_type(11) returns something other than
IRQ_TYPE_LEVEL_LOW, so we penalize it by PIRQ_PENALTY_ISA_ALWAYS
instead, which makes acpi_pci_link_allocate() assume the IRQ isn't
available and give up.
Add acpi_penalize_sci_irq() so platforms can tell us the SCI IRQ,
trigger, and polarity directly and we don't have to depend on
irq_get_trigger_type().
Link: http://lkml.kernel.org/r/201609251512.05657.linux at rainbow-software.org
Reported-by: Ondrej Zary <linux@rainbow-software.org>
I don't understand what's broken about using irq_get_trigger_type().
The SCI is registered in the following path, which is certainly before
we try to enable LNKA for the 8139too device:
acpi_init # subsys_initcall
acpi_bus_init
acpi_enable_subsystem
acpi_ev_install_xrupt_handlers
acpi_ev_install_sci_handler
acpi_os_install_interrupt_handler(sci_interrupt, ...)
acpi_gsi_to_irq
acpi_register_gsi
irq_create_fwspec_mapping
irqd_set_trigger_type
In any event, I think this patch to add acpi_penalize_sci_irq() is
fine.
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>
> > Link: https://lkml.org/lkml/2016/10/4/283
> > Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> > Fixes: commit 103544d86976 ("ACPI,PCI,IRQ: reduce resource requirements")
> > Fixes: commit 9e5ed6d1fb87 ("ACPI,PCI,IRQ: remove SCI penalize function")
>
> "commit" is redundant; it's sufficient to say:
>
> Fixes: 103544d86976 ("ACPI,PCI,IRQ: reduce resource requirements")
>
> In fact, I don't think you really need to include "commit" in the
> reference to 9e5ed6d1fb87 above either.
>
> > ---
> > arch/x86/kernel/acpi/boot.c | 1 +
> > drivers/acpi/pci_link.c | 30 +++++++++++++++---------------
> > include/linux/acpi.h | 1 +
> > 3 files changed, 17 insertions(+), 15 deletions(-)
> >
> > diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
> > index 90d84c3..0ffd26e 100644
> > --- a/arch/x86/kernel/acpi/boot.c
> > +++ b/arch/x86/kernel/acpi/boot.c
> > @@ -453,6 +453,7 @@ static void __init acpi_sci_ioapic_setup(u8 bus_irq, u16 polarity, u16 trigger,
> > polarity = acpi_sci_flags & ACPI_MADT_POLARITY_MASK;
> >
> > mp_override_legacy_irq(bus_irq, polarity, trigger, gsi);
> > + acpi_penalize_sci_irq(bus_irq, trigger, polarity);
> >
> > /*
> > * stash over-ride to indicate we've been here
> > diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c
> > index 4f37938..294b190 100644
> > --- a/drivers/acpi/pci_link.c
> > +++ b/drivers/acpi/pci_link.c
> > @@ -87,6 +87,7 @@ struct acpi_pci_link {
> >
> > static LIST_HEAD(acpi_link_list);
> > static DEFINE_MUTEX(acpi_link_lock);
> > +static int sci_irq = -1, sci_penalty;
> >
> > /* --------------------------------------------------------------------------
> > PCI Link Device Management
> > @@ -496,25 +497,13 @@ static int acpi_irq_get_penalty(int irq)
> > {
> > int penalty = 0;
> >
> > - /*
> > - * Penalize IRQ used by ACPI SCI. If ACPI SCI pin attributes conflict
> > - * with PCI IRQ attributes, mark ACPI SCI as ISA_ALWAYS so it won't be
> > - * use for PCI IRQs.
> > - */
> > - if (irq == acpi_gbl_FADT.sci_interrupt) {
> > - u32 type = irq_get_trigger_type(irq) & IRQ_TYPE_SENSE_MASK;
> > -
> > - if (type != IRQ_TYPE_LEVEL_LOW)
> > - penalty += PIRQ_PENALTY_ISA_ALWAYS;
> > - else
> > - penalty += PIRQ_PENALTY_PCI_USING;
> > - }
> > + if (irq == sci_irq)
> > + penalty += sci_penalty;
> >
> > if (irq < ACPI_MAX_ISA_IRQS)
> > return penalty + acpi_isa_irq_penalty[irq];
> >
> > - penalty += acpi_irq_pci_sharing_penalty(irq);
> > - return penalty;
> > + return penalty + acpi_irq_pci_sharing_penalty(irq);
> > }
> >
> > int __init acpi_irq_penalty_init(void)
> > @@ -881,6 +870,17 @@ bool acpi_isa_irq_available(int irq)
> > acpi_irq_get_penalty(irq) < PIRQ_PENALTY_ISA_ALWAYS);
> > }
> >
> > +void acpi_penalize_sci_irq(int irq, int trigger, int polarity)
> > +{
> > + sci_irq = irq;
> > +
> > + if (trigger == ACPI_MADT_TRIGGER_LEVEL &&
> > + polarity == ACPI_MADT_POLARITY_ACTIVE_LOW)
> > + sci_penalty = PIRQ_PENALTY_PCI_USING;
> > + else
> > + sci_penalty = PIRQ_PENALTY_ISA_ALWAYS;
> > +}
> > +
> > /*
> > * Over-ride default table to reserve additional IRQs for use by ISA
> > * e.g. acpi_irq_isa=5
> > diff --git a/include/linux/acpi.h b/include/linux/acpi.h
> > index c5eaf2f..67d1d3e 100644
> > --- a/include/linux/acpi.h
> > +++ b/include/linux/acpi.h
> > @@ -318,6 +318,7 @@ struct pci_dev;
> > int acpi_pci_irq_enable (struct pci_dev *dev);
> > void acpi_penalize_isa_irq(int irq, int active);
> > bool acpi_isa_irq_available(int irq);
> > +void acpi_penalize_sci_irq(int irq, int trigger, int polarity);
> > void acpi_pci_irq_disable (struct pci_dev *dev);
> >
> > extern int ec_read(u8 addr, u8 *val);
> > --
> > 1.9.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> --
> To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Disabling an interrupt in the handler locks the system up
From: Mason @ 2016-10-22 23:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161022123713.6dc788b3@arm.com>
On 22/10/2016 13:37, Marc Zyngier wrote:
> Mason wrote:
>
>> In my mental picture of interrupts (which is obviously so
>> incomplete as to be wrong) interrupts are a way for hardware
>> to tell the CPU that they urgently need the CPU's attention.
>
> That's how the CPU interprets it, but this is even more basic than
> that, see below.
>
>> Obviously, the hardware being idle (line high) is not an urgent
>> matter which interests the CPU. Likewise, I'm not sure the CPU
>> cares that the hardware is busy (line low). It seems to me the
>> interesting event from the CPU's perspective is when the
>> hardware completes a "task" (transition from low to high).
>
> There is no such thing as "busy" when it comes to interrupts. An
> interrupt signals the CPU that some device-specific condition has been
> satisfied. It could be "I've received a packet" or "Battery is about to
> explode", depending if the device is a network controller or a
> temperature sensor. The interrupt doesn't describe the process that
> leads to that condition (packet being received or temperature rising),
> but the condition itself.
>
> In your cases, as the device seems to do some form of processing
> (you're talking about task completion), then the interrupt seems to
> describe exactly this ("I'm done").
The device is a graphics engine, which can be programmed to perform
some operation on one or several frame buffers stored in memory.
It outputs its state (idle vs busy) on interrupt line 23.
>> So I had originally configured the interrupt as IRQ_TYPE_EDGE_RISING.
>> (There is an edge detection block in the irqchip, but the HW designer
>> warned me that at low frequencies, it is possible to "miss" some edges,
>> and we should prefer level triggers if possible.)
>
> Level and edge are not interchangeable. They do describe very different
> thing:
>
> - Level indicates a persistent state, which implies that the device
> needs to be serviced so that this condition can be cleared (the UART
> has received a character, and won't be able to received another until
> it has been read by the CPU). Once the device has been serviced and
> that condition cleared, it will lower its interrupt line.
With this graphics engine, there is nothing the CPU can do to
change what the engine outputs on the interrupt line:
When the graphics engine is idle, the line remains high, forever.
When the graphics engine is busy, the line remains low, until
all operations have been performed (engine idle).
All the CPU can do is mask the interrupt line at the interrupt
controller, as far as I understand.
> - Edge is indicative of an event having occurred ("I'm done") that
> doesn't require any action from the CPU. Because the device can
> continue its life without being poked by the CPU, it can continue
> delivering interrupts even if the first one hasn't been serviced.
> Being edge triggered, the signals get coalesced into a single
> interrupt. For example, the temperature sensor will say "Temperature
> rising" multiple times before the battery explodes, and it is the
> CPU's job to go and read the sensor to find out by how much it has
> risen.
>
> If your device only sends a pulse, then it is edge triggered, and it
> should be treated as such, no matter what your HW guy is saying. This
> usually involves looking at the device to find out how many times the
> interrupt has been generated (assuming the device is some kind of
> processing element). Of course, this is racy (interrupts can still be
> generated whilst you're processing them), and you should design your
> interrupt handler to take care of the possible race.
It is clear that the block does not send a pulse on the
interrupt line.
For reasons I don't understand, Linux didn't hang when I set
the IRQ type to IRQ_TYPE_EDGE_RISING, so it seemed better
than locking up the system.
I'm also fuzzy on what purpose the edge detector is supposed
to serve... I had the impression is what supposed to "capture"
an edge, to turn it into a level?
> So, to make it short: find out how your device works, and configure
> your interrupt controller in a similar way. Write your device driver
> with the interrupt policy in mind (state vs event). Keep it simple.
Thomas said "We describe the level which is raising the interrupt".
But I'm not sure I want the state "engine is busy" to raise an
interrupt. "engine is idle" makes more sense. But you said it's
stupid to set IRQ_TYPE_LEVEL_HIGH... /me confused
Maybe the fact that disable_irq locks the system up is an orthogonal
issue that needs to be fixed anyway.
Regards.
^ permalink raw reply
* [PATCH v2 4/4] cpufreq: pxa: convert to clock API
From: Robert Jarzmik @ 2016-10-22 21:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161018114025.GD11471@vireshk-i7>
Viresh Kumar <viresh.kumar@linaro.org> writes:
> On 15-10-16, 21:57, Robert Jarzmik wrote:
>> As the clock settings have been introduced into the clock pxa drivers,
>> which are now available to change the CPU clock by themselves, remove
>> the clock handling from this driver, and rely on pxa clock drivers.
>>
>> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
>> ---
>> Since v1: added !OF Kconfig dependency
>> ---
>> drivers/cpufreq/Kconfig.arm | 2 +-
>> drivers/cpufreq/pxa2xx-cpufreq.c | 191 ++++++++-------------------------------
>> 2 files changed, 40 insertions(+), 153 deletions(-)
>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Okay, after some more testing, I'd like to remove the !OF for next iteration.
The reason is that I have a usecase where I have a single kernel image with
devictree support (ie CONFIG_OF=y), but with support for both devicetree and
legacy platforms. In this case, a platform such as lubbock can boot :
- with devicetree
- with legacy arch/arm/mach-pxa/lubbock.c
In this kernel, the !OF Kconfig prevents the legacy version from working, as
pxa2xx-cpufreq is descarded even if it is needed in the legacy version.
Therefore, I'd like to respin without this !OF.
Cheers.
--
Robert
^ permalink raw reply
* [PATCH 2/3] ARM: convert to generated system call tables
From: Robert Jarzmik @ 2016-10-22 20:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <24632117.YsmPs86ri6@wuerfel>
Arnd Bergmann <arnd@arndb.de> writes:
> On Friday, October 21, 2016 4:48:56 PM CEST Russell King - ARM Linux wrote:
>> What's the point of the x32 mode?
>
> On x86, the motivation is faster code for most use cases that
> don't need a lot of memory, as the 64-bit opcodes have 16 registers
> rather than 8 in 32-bit mode but 32-bit pointers have lower
> cache footprint than 64-bit pointers.
For completness, the second point of x32 AFAIU is the IP-relative addressing
which is not available in standard 32 bit mode, which improves PIC code. For
simple not algorithmic code (think Android HAL for example) with many shared
libraries, it's better in the Hardware Abstraction Layer Libraries, instead of
the push-to-stack and pop register.
Cheers.
--
Robert
^ permalink raw reply
* [PATCH 7/7] ARM: dts: add support for Duckbill 2 series devices
From: Michael Heimpold @ 2016-10-22 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477164150-13553-1-git-send-email-mhei@heimpold.de>
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
---
arch/arm/boot/dts/Makefile | 4 +
arch/arm/boot/dts/imx28-duckbill-2-485.dts | 70 +++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-2-enocean.dts | 100 +++++++++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-2-spi.dts | 63 ++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-2.dts | 46 ++++++++++++
5 files changed, 283 insertions(+)
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2-485.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2-spi.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5a366c4..510e6f3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -459,6 +459,10 @@ dtb-$(CONFIG_ARCH_MXS) += \
imx28-cfa10056.dtb \
imx28-cfa10057.dtb \
imx28-cfa10058.dtb \
+ imx28-duckbill-2-485.dtb \
+ imx28-duckbill-2.dtb \
+ imx28-duckbill-2-enocean.dtb \
+ imx28-duckbill-2-spi.dtb \
imx28-duckbill-485.dtb \
imx28-duckbill.dtb \
imx28-duckbill-enocean.dtb \
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
new file mode 100644
index 0000000..6c7429d
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015-2016 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28-duckbill-2-common.dtsi"
+
+/ {
+ model = "I2SE Duckbill 2 485";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ ssp2: ssp at 80014000 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_4bit_pins_b
+ &mmc2_cd_cfg &mmc2_sck_cfg_b>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+ };
+
+ pinctrl at 80018000 {
+ rs485_led_pins: rs485_led_pins at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_I2C0_SCL__GPIO_3_24
+ MX28_PAD_I2C0_SDA__GPIO_3_25
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+ };
+
+ apbx at 80040000 {
+ auart0: serial at 8006a000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+ };
+ };
+ };
+
+ rs485_leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rs485_led_pins>;
+
+ rs485_red {
+ label = "duckbill:red:rs485";
+ gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ };
+
+ rs485_green {
+ label = "duckbill:green:rs485";
+ gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
new file mode 100644
index 0000000..f71944d3
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2015-2016 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "imx28-duckbill-2-common.dtsi"
+
+/ {
+ model = "I2SE Duckbill 2 EnOcean";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ ssp2: ssp at 80014000 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_4bit_pins_b
+ &mmc2_cd_cfg &mmc2_sck_cfg_b>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+ };
+
+ pinctrl at 80018000 {
+ enocean_led_pins: enocean_led_pins at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_CTS__GPIO_3_2
+ MX28_PAD_I2C0_SCL__GPIO_3_24
+ MX28_PAD_I2C0_SDA__GPIO_3_25
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ enocean_button: enocean_button at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_RTS__GPIO_3_3
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+ };
+
+ apbx at 80040000 {
+ auart0: serial at 8006a000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+ };
+ };
+ };
+
+ enocean_leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&enocean_led_pins>;
+
+ enocean_blue {
+ label = "duckbill:blue:enocean";
+ gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ };
+
+ enocean_red {
+ label = "duckbill:red:enocean";
+ gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ };
+
+ enocean_green {
+ label = "duckbill:green:enocean";
+ gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&enocean_button>;
+
+ enocean {
+ label = "EnOcean";
+ linux,code = <KEY_NEW>;
+ gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
new file mode 100644
index 0000000..e5c7d00
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2015 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx28-duckbill-2-common.dtsi"
+
+/ {
+ model = "I2SE Duckbill 2 SPI";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ aliases {
+ ethernet1 = &qca7000;
+ };
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ ssp2: ssp at 80014000 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+
+ qca7000: ethernet at 0 {
+ compatible = "qca,qca7000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qca7000_pins>;
+ reg = <0>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ spi-cpha;
+ spi-cpol;
+ spi-max-frequency = <8000000>;
+ };
+ };
+
+ pinctrl at 80018000 {
+ qca7000_pins: qca7000-pins at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */
+ MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */
+ MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */
+ MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */
+ MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */
+ MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts
new file mode 100644
index 0000000..207e263
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-2.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2015-2016 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx28-duckbill-2-common.dtsi"
+
+/ {
+ model = "I2SE Duckbill 2";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ ssp2: ssp at 80014000 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_4bit_pins_b
+ &mmc2_cd_cfg &mmc2_sck_cfg_b>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+ };
+ };
+
+ apbx at 80040000 {
+ i2c0: i2c at 80058000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+ };
+
+ auart0: serial at 8006a000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+ };
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 6/7] ARM: dts: add support for remaining members of Duckbill series
From: Michael Heimpold @ 2016-10-22 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477164150-13553-1-git-send-email-mhei@heimpold.de>
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx28-duckbill-485.dts | 60 +++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-enocean.dts | 90 ++++++++++++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-spi.dts | 64 ++++++++++++++++++++
4 files changed, 217 insertions(+)
create mode 100644 arch/arm/boot/dts/imx28-duckbill-485.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-enocean.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-spi.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd26..5a366c4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -459,7 +459,10 @@ dtb-$(CONFIG_ARCH_MXS) += \
imx28-cfa10056.dtb \
imx28-cfa10057.dtb \
imx28-cfa10058.dtb \
+ imx28-duckbill-485.dtb \
imx28-duckbill.dtb \
+ imx28-duckbill-enocean.dtb \
+ imx28-duckbill-spi.dtb \
imx28-eukrea-mbmx283lc.dtb \
imx28-eukrea-mbmx287lc.dtb \
imx28-evk.dtb \
diff --git a/arch/arm/boot/dts/imx28-duckbill-485.dts b/arch/arm/boot/dts/imx28-duckbill-485.dts
new file mode 100644
index 0000000..a60d78a
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-485.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2015 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28-duckbill-common.dtsi"
+
+/ {
+ model = "I2SE Duckbill 485";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ pinctrl at 80018000 {
+ rs485_led_pins: rs485_led_pins at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__GPIO_2_16
+ MX28_PAD_SSP2_MISO__GPIO_2_18
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+ };
+
+ apbx at 80040000 {
+ auart0: serial at 8006a000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+ };
+ };
+ };
+
+ rs485_leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rs485_led_pins>;
+
+ rs485_red {
+ label = "duckbill:red:rs485";
+ gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
+ };
+
+ rs485_green {
+ label = "duckbill:green:rs485";
+ gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-enocean.dts
new file mode 100644
index 0000000..4602d13
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-enocean.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2015 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "imx28-duckbill-common.dtsi"
+
+/ {
+ model = "I2SE Duckbill EnOcean";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ pinctrl at 80018000 {
+ enocean_led_pins: enocean_led_pins at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__GPIO_2_16
+ MX28_PAD_SSP2_MISO__GPIO_2_18
+ MX28_PAD_SSP2_SS0__GPIO_2_19
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ enocean_button: enocean_button at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SS2__GPIO_2_21
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+ };
+
+ apbx at 80040000 {
+ auart0: serial at 8006a000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+ };
+ };
+ };
+
+ enocean_leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&enocean_led_pins>;
+
+ enocean_blue {
+ label = "duckbill:blue:enocean";
+ gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
+ };
+
+ enocean_red {
+ label = "duckbill:red:enocean";
+ gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
+ };
+
+ enocean_green {
+ label = "duckbill:green:enocean";
+ gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&enocean_button>;
+
+ enocean {
+ label = "EnOcean";
+ linux,code = <KEY_NEW>;
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-spi.dts b/arch/arm/boot/dts/imx28-duckbill-spi.dts
new file mode 100644
index 0000000..5248d84
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-spi.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013-2014 Michael Heimpold <mhei@heimpold.de>
+ * Copyright (C) 2015 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx28-duckbill-common.dtsi"
+
+/ {
+ model = "I2SE Duckbill SPI";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ aliases {
+ ethernet1 = &qca7000;
+ };
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ ssp2: ssp at 80014000 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+
+ qca7000: ethernet at 0 {
+ compatible = "qca,qca7000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qca7000_pins>;
+ reg = <0>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ spi-cpha;
+ spi-cpol;
+ spi-max-frequency = <8000000>;
+ };
+ };
+
+ pinctrl at 80018000 {
+ qca7000_pins: qca7000-pins at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */
+ MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */
+ MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */
+ MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */
+ MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */
+ MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 5/7] ARM: dts: duckbill: simplify DT and use common definitions
From: Michael Heimpold @ 2016-10-22 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477164150-13553-1-git-send-email-mhei@heimpold.de>
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
---
arch/arm/boot/dts/imx28-duckbill.dts | 99 ++++--------------------------------
1 file changed, 11 insertions(+), 88 deletions(-)
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index ce1a7ef..c3d1ce1 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2013 Michael Heimpold <mhei@heimpold.de>
+ * Copyright (C) 2013-2014,2016 Michael Heimpold <mhei@heimpold.de>
+ * Copyright (C) 2015 I2SE GmbH <info@i2se.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@@ -10,112 +11,34 @@
*/
/dts-v1/;
-#include "imx28.dtsi"
+#include "imx28-duckbill-common.dtsi"
/ {
model = "I2SE Duckbill";
compatible = "i2se,duckbill", "fsl,imx28";
- memory {
- reg = <0x40000000 0x08000000>;
- };
-
apb at 80000000 {
apbh at 80000000 {
- ssp0: ssp at 80010000 {
- compatible = "fsl,imx28-mmc";
+ ssp2: ssp at 80014000 {
+ compatible = "fsl,imx28-spi";
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_4bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- bus-width = <4>;
- vmmc-supply = <®_3p3v>;
+ pinctrl-0 = <&spi2_pins_a>;
status = "okay";
};
-
- pinctrl at 80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog at 0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- led_pins_a: led_gpio at 0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_AUART1_RX__GPIO_3_4
- MX28_PAD_AUART1_TX__GPIO_3_5
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
};
apbx at 80040000 {
- duart: serial at 80074000 {
+ i2c0: i2c at 80058000 {
pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
+ pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
- usbphy0: usbphy at 8007c000 {
+ auart0: serial at 8006a000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
status = "okay";
};
};
};
-
- ahb at 80080000 {
- usb0: usb at 80080000 {
- status = "okay";
- };
-
- mac0: ethernet at 800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- phy-supply = <®_3p3v>;
- phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <100>;
- status = "okay";
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_3p3v: regulator at 0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_a>;
-
- status {
- label = "duckbill:green:status";
- gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
- };
-
- failure {
- label = "duckbill:red:status";
- gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
- };
- };
};
--
2.7.4
^ permalink raw reply related
* [PATCH 4/7] ARM: dts: add I2SE Duckbill common definitions
From: Michael Heimpold @ 2016-10-22 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477164150-13553-1-git-send-email-mhei@heimpold.de>
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
---
arch/arm/boot/dts/imx28-duckbill-2-common.dtsi | 110 +++++++++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-base.dtsi | 88 ++++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-common.dtsi | 80 ++++++++++++++++++
3 files changed, 278 insertions(+)
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2-common.dtsi
create mode 100644 arch/arm/boot/dts/imx28-duckbill-base.dtsi
create mode 100644 arch/arm/boot/dts/imx28-duckbill-common.dtsi
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-common.dtsi b/arch/arm/boot/dts/imx28-duckbill-2-common.dtsi
new file mode 100644
index 0000000..3354f8f
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-2-common.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2013-2014 Michael Heimpold <mhei@heimpold.de>
+ * Copyright (C) 2015 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28-duckbill-base.dtsi"
+
+/ {
+ model = "I2SE Duckbill 2";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ ssp0: ssp at 80010000 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_8bit_pins_a
+ &mmc0_cd_cfg &mmc0_sck_cfg>;
+ bus-width = <8>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+ non-removable;
+ };
+
+ pinctrl at 80018000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ mac0_phy_reset_pin: mac0_phy_reset_pin at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mac0_phy_int_pin: mac0_phy_int_pin at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ status_led_pins: status_led_pins at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF0_MCLK__GPIO_3_20
+ MX28_PAD_SAIF0_LRCLK__GPIO_3_21
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+ };
+ };
+
+ ahb at 80080000 {
+ mac0: ethernet at 800f0000 {
+ phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_phy_int_pin>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ max-speed = <100>;
+ };
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&status_led_pins>;
+
+ status_red {
+ label = "duckbill:red:status";
+ gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ status_green {
+ label = "duckbill:green:status";
+ gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-base.dtsi b/arch/arm/boot/dts/imx28-duckbill-base.dtsi
new file mode 100644
index 0000000..b64efd5
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-base.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2013-2014 Michael Heimpold <mhei@heimpold.de>
+ * Copyright (C) 2015 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx28.dtsi"
+
+/ {
+ model = "I2SE Duckbill";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ memory {
+ reg = <0x40000000 0x08000000>;
+ };
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ pinctrl at 80018000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog_pins at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+ };
+
+ apbx at 80040000 {
+ lradc at 80050000 {
+ status = "okay";
+ };
+
+ duart: serial at 80074000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+ };
+
+ usbphy0: usbphy at 8007c000 {
+ status = "okay";
+ };
+ };
+ };
+
+ ahb at 80080000 {
+ usb0: usb at 80080000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ mac0: ethernet at 800f0000 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
+ phy-supply = <®_3p3v>;
+ phy-reset-duration = <25>;
+ status = "okay";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3p3v: regulator at 0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-common.dtsi b/arch/arm/boot/dts/imx28-duckbill-common.dtsi
new file mode 100644
index 0000000..167b53f
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-common.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2013-2014 Michael Heimpold <mhei@heimpold.de>
+ * Copyright (C) 2015 I2SE GmbH <info@i2se.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28-duckbill-base.dtsi"
+
+/ {
+ model = "I2SE Duckbill";
+ compatible = "i2se,duckbill", "fsl,imx28";
+
+ apb at 80000000 {
+ apbh at 80000000 {
+ ssp0: ssp at 80010000 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a
+ &mmc0_cd_cfg &mmc0_sck_cfg>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+ };
+
+ pinctrl at 80018000 {
+ mac0_phy_reset_pin: mac0_phy_reset_pin at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ status_led_pins: status_led_pins at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART1_RX__GPIO_3_4
+ MX28_PAD_AUART1_TX__GPIO_3_5
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+ };
+ };
+
+ ahb at 80080000 {
+ mac0: ethernet at 800f0000 {
+ phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&status_led_pins>;
+
+ status_red {
+ label = "duckbill:red:status";
+ gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ status_green {
+ label = "duckbill:green:status";
+ gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 3/7] ARM: dts: imx28: add alternative muxing for mmc2_sck_cfg
From: Michael Heimpold @ 2016-10-22 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477164150-13553-1-git-send-email-mhei@heimpold.de>
From: Michael Heimpold <michael.heimpold@i2se.com>
Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
---
arch/arm/boot/dts/imx28.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index e29d797..f7707b4 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -611,6 +611,15 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
+ mmc2_sck_cfg_b: mmc2-sck-cfg at 1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__SSP2_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
i2c0_pins_a: i2c0 at 0 {
reg = <0>;
fsl,pinmux-ids = <
--
2.7.4
^ permalink raw reply related
* [PATCH 2/7] ARM: dts: imx28: rename mmc2_sck_cfg to prepare for an alternative muxing setup
From: Michael Heimpold @ 2016-10-22 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477164150-13553-1-git-send-email-mhei@heimpold.de>
From: Michael Heimpold <michael.heimpold@i2se.com>
Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
---
arch/arm/boot/dts/imx28-m28cu3.dts | 2 +-
arch/arm/boot/dts/imx28.dtsi | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 2df63be..bb53294 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -57,7 +57,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_4bit_pins_a
&mmc2_cd_cfg
- &mmc2_sck_cfg>;
+ &mmc2_sck_cfg_a>;
bus-width = <4>;
vmmc-supply = <®_vddio_sd1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index ef6e10d..e29d797 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -602,7 +602,8 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc2_sck_cfg: mmc2-sck-cfg {
+ mmc2_sck_cfg_a: mmc2-sck-cfg at 0 {
+ reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA7__SSP2_SCK
>;
--
2.7.4
^ permalink raw reply related
* [PATCH 1/7] ARM: dts: imx28: add alternative pinmuxing for mmc2
From: Michael Heimpold @ 2016-10-22 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477164150-13553-1-git-send-email-mhei@heimpold.de>
From: Michael Heimpold <michael.heimpold@i2se.com>
Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
---
arch/arm/boot/dts/imx28.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 0ad893b..ef6e10d 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -579,6 +579,22 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
+ mmc2_4bit_pins_b: mmc2-4bit at 1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__SSP2_SCK
+ MX28_PAD_SSP2_MOSI__SSP2_CMD
+ MX28_PAD_SSP2_MISO__SSP2_D0
+ MX28_PAD_SSP2_SS0__SSP2_D3
+ MX28_PAD_SSP2_SS1__SSP2_D1
+ MX28_PAD_SSP2_SS2__SSP2_D2
+ MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
mmc2_cd_cfg: mmc2-cd-cfg {
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
--
2.7.4
^ permalink raw reply related
* [PATCH 0/7] ARM: dts: support I2SE Duckbill device
From: Michael Heimpold @ 2016-10-22 19:22 UTC (permalink / raw)
To: linux-arm-kernel
This series updates/adds Device Tree support for I2SE's Duckbill
device family.
The Duckbill devices are small, pen-drive sized boards based on
NXP's i.MX28 SoC. While the initial variants (Duckbill series) were
equipped with a micro SD card slot only, the latest generation
(Duckbill 2 series) have an additional internal eMMC onboard.
Both device generations consists of four "family members":
- Duckbill/Duckbill 2: generic board, intented to be used as
baseboard for custom designs and/or as development board
- Duckbill EnOcean/Duckbill 2 EnOcean: come with an EnOcean
daugther board equipped with the popular TCM310 module
- Duckbill 485/Duckbill 2 485: as the name implies, these
devices are intended to be used as Ethernet - RS485 converters
- Duckbill SPI/Duckbill 2 SPI: not sold separately, but used
in I2SE's development kits for Green PHY HomePlug Powerline
communication
Since all devices are very similar and only differ in few
aspects, the following patch series introduces first common
device tree snippets which are then included by the real
devices. For better understanding, I tried to illustrate the
hierarchy:
+--------------------+ +----------------------+
| imx28-duckbill.dts | | imx28-duckbill-2.dts |
+--------------------+ +----------------------+
^ ^
| +----------------------------+ | +------------------------------+
| | imx28-duckbill-enocean.dts | | | imx28-duckbill-2-enocean.dts |
| +----------------------------+ | +------------------------------+
| ^ | ^
| | +------------------------+ | | +--------------------------+
| | | imx28-duckbill-485.dts | | | | imx28-duckbill-2-485.dts |
| | +------------------------+ | | +--------------------------+
| | ^ | | ^
| | | +------------------------+ | | | +--------------------------+
| | | | imx28-duckbill-spi.dts | | | | | imx28-duckbill-2-spi.dts |
| | | +------------------------+ | | | +--------------------------+
| | | ^ | | | ^
| | | | | | | |
| | | | | | | |
+---------------------------------------+ +-----------------------------------------+
| imx28-duckbill-common.dtsi | | imx28-duckbill-2-common.dtsi |
+---------------------------------------+ +-----------------------------------------+
^ ^
| |
+----------------------------+
| imx28-duckbill-base.dtsi |
+----------------------------+
^
|
+------------+
| imx28.dtsi |
+------------+
Michael Heimpold (7):
ARM: dts: imx28: add alternative pinmuxing for mmc2
ARM: dts: imx28: rename mmc2_sck_cfg to prepare for an alternative
muxing setup
ARM: dts: imx28: add alternative muxing for mmc2_sck_cfg
ARM: dts: add I2SE Duckbill common definitions
ARM: dts: duckbill: simplify DT and use common definitions
ARM: dts: add support for remaining members of Duckbill series
ARM: dts: add support for Duckbill 2 series devices
arch/arm/boot/dts/Makefile | 7 ++
arch/arm/boot/dts/imx28-duckbill-2-485.dts | 70 ++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-2-common.dtsi | 110 +++++++++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-2-enocean.dts | 100 ++++++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-2-spi.dts | 63 ++++++++++++++
arch/arm/boot/dts/imx28-duckbill-2.dts | 46 +++++++++++
arch/arm/boot/dts/imx28-duckbill-485.dts | 60 ++++++++++++++
arch/arm/boot/dts/imx28-duckbill-base.dtsi | 88 ++++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-common.dtsi | 80 ++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-enocean.dts | 90 ++++++++++++++++++++
arch/arm/boot/dts/imx28-duckbill-spi.dts | 64 ++++++++++++++
arch/arm/boot/dts/imx28-duckbill.dts | 99 +++-------------------
arch/arm/boot/dts/imx28-m28cu3.dts | 2 +-
arch/arm/boot/dts/imx28.dtsi | 28 ++++++-
14 files changed, 817 insertions(+), 90 deletions(-)
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2-485.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2-common.dtsi
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2-spi.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-2.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-485.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-base.dtsi
create mode 100644 arch/arm/boot/dts/imx28-duckbill-common.dtsi
create mode 100644 arch/arm/boot/dts/imx28-duckbill-enocean.dts
create mode 100644 arch/arm/boot/dts/imx28-duckbill-spi.dts
--
2.7.4
^ permalink raw reply
* [PATCH] drm/rockchip: analogix_dp: add supports for regulators in edp IP
From: Randy Li @ 2016-10-22 19:18 UTC (permalink / raw)
To: linux-arm-kernel
I found if eDP_AVDD_1V0 and eDP_AVDD_1V8 are not been power at
RK3288, once trying to enable the pclk clock, the kernel would dead.
This patch would try to enable them first. The eDP_AVDD_1V8 more
likely to be applied to eDP phy, but I have no time to confirmed
it yet.
Signed-off-by: Randy Li <ayaka@soulik.info>
---
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 8548e82..6bf0441 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -17,6 +17,7 @@
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/clk.h>
@@ -70,6 +71,7 @@ struct rockchip_dp_device {
struct clk *grfclk;
struct regmap *grf;
struct reset_control *rst;
+ struct regulator_bulk_data supplies[2];
struct work_struct psr_work;
spinlock_t psr_lock;
@@ -146,6 +148,13 @@ static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
cancel_work_sync(&dp->psr_work);
+ ret = regulator_bulk_enable(ARRAY_SIZE(dp->supplies),
+ dp->supplies);
+ if (ret) {
+ dev_err(dp->dev, "failed to enable vdd supply %d\n", ret);
+ return ret;
+ }
+
ret = clk_prepare_enable(dp->pclk);
if (ret < 0) {
dev_err(dp->dev, "failed to enable pclk %d\n", ret);
@@ -168,6 +177,9 @@ static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
clk_disable_unprepare(dp->pclk);
+ regulator_bulk_disable(ARRAY_SIZE(dp->supplies),
+ dp->supplies);
+
return 0;
}
@@ -323,6 +335,19 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)
return PTR_ERR(dp->rst);
}
+ dp->supplies[0].supply = "vcc";
+ dp->supplies[1].supply = "vccio";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dp->supplies),
+ dp->supplies);
+ if (ret < 0) {
+ dev_err(dev, "failed to get regulators: %d\n", ret);
+ }
+ ret = regulator_bulk_enable(ARRAY_SIZE(dp->supplies),
+ dp->supplies);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable regulators: %d\n", ret);
+ }
+
ret = clk_prepare_enable(dp->pclk);
if (ret < 0) {
dev_err(dp->dev, "failed to enable pclk %d\n", ret);
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/4] drivers: iio: ti_am335x_adc: add dma support
From: Jonathan Cameron @ 2016-10-22 17:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d7dd9a21-51d9-e8f5-a6fe-34653afc9240@ti.com>
On 19/10/16 09:52, Mugunthan V N wrote:
> On Sunday 09 October 2016 02:00 PM, Jonathan Cameron wrote:
>> On 05/10/16 10:04, Mugunthan V N wrote:
>>> This patch adds the required pieces to ti_am335x_adc driver for
>>> DMA support
>>>
>>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> Hi,
>>
>> Just the one question inline. I'll also need an Ack from Lee as
>> this touches code in mfd (as does the previous patch).
>> We have obviously missed this merge window, so no particular rush.
Question answered below. So just need that Ack from Lee.
>>
>> Otherwise, looking very nice indeed. Got to get my BBB out and play
>> with this now ;)
>>
>> Jonathan
>>> ---
>>> drivers/iio/adc/ti_am335x_adc.c | 148 ++++++++++++++++++++++++++++++++++-
>>> include/linux/mfd/ti_am335x_tscadc.h | 7 ++
>>> 2 files changed, 152 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c
>>> index c3cfacca..ad9dec3 100644
>>> --- a/drivers/iio/adc/ti_am335x_adc.c
>>> +++ b/drivers/iio/adc/ti_am335x_adc.c
>>> @@ -30,10 +30,28 @@
>>> #include <linux/iio/buffer.h>
>>> #include <linux/iio/kfifo_buf.h>
>>>
>>> +#include <linux/dmaengine.h>
>>> +#include <linux/dma-mapping.h>
>>> +
>>> +#define DMA_BUFFER_SIZE SZ_2K
>>> +
>>> +struct tiadc_dma {
>>> + struct dma_slave_config conf;
>>> + struct dma_chan *chan;
>>> + dma_addr_t addr;
>>> + dma_cookie_t cookie;
>>> + u8 *buf;
>>> + int current_period;
>>> + int period_size;
>>> + u8 fifo_thresh;
>>> +};
>>> +
>>> struct tiadc_device {
>>> struct ti_tscadc_dev *mfd_tscadc;
>>> + struct tiadc_dma dma;
>>> struct mutex fifo1_lock; /* to protect fifo access */
>>> int channels;
>>> + int total_ch_enabled;
>>> u8 channel_line[8];
>>> u8 channel_step[8];
>>> int buffer_en_ch_steps;
>>> @@ -198,6 +216,67 @@ static irqreturn_t tiadc_worker_h(int irq, void *private)
>>> return IRQ_HANDLED;
>>> }
>>>
>>> +static void tiadc_dma_rx_complete(void *param)
>>> +{
>>> + struct iio_dev *indio_dev = param;
>>> + struct tiadc_device *adc_dev = iio_priv(indio_dev);
>>> + struct tiadc_dma *dma = &adc_dev->dma;
>>> + u8 *data;
>>> + int i;
>>> +
>>> + data = dma->buf + dma->current_period * dma->period_size;
>>> + dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
>>> +
>>> + for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
>>> + iio_push_to_buffers(indio_dev, data);
>>> + data += indio_dev->scan_bytes;
>>> + }
>> Hmm. Another case for the mooted iio_push_to_buffers_multi. Guess
>> we should move on with that one ;)
>>> +}
>>> +
>>> +static int tiadc_start_dma(struct iio_dev *indio_dev)
>>> +{
>>> + struct tiadc_device *adc_dev = iio_priv(indio_dev);
>>> + struct tiadc_dma *dma = &adc_dev->dma;
>>> + struct dma_async_tx_descriptor *desc;
>>> +
>>> + dma->current_period = 0; /* We start to fill period 0 */
>>> + /*
>>> + * Make the fifo thresh as the multiple of total number of
>>> + * channels enabled, so make sure that cyclic DMA period
>>> + * length is also a multiple of total number of channels
>>> + * enabled. This ensures that no invalid data is reported
>>> + * to the stack via iio_push_to_buffers().
>>> + */
>>> + dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
>>> + adc_dev->total_ch_enabled) - 1;
>>> + /* Make sure that period length is multiple of fifo thresh level */
>>> + dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
>>> + (dma->fifo_thresh + 1) * sizeof(u16));
>>> +
>>> + dma->conf.src_maxburst = dma->fifo_thresh + 1;
>>> + dmaengine_slave_config(dma->chan, &dma->conf);
>>> +
>>> + desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
>>> + dma->period_size * 2,
>>> + dma->period_size, DMA_DEV_TO_MEM,
>>> + DMA_PREP_INTERRUPT);
>>> + if (!desc)
>>> + return -EBUSY;
>>> +
>>> + desc->callback = tiadc_dma_rx_complete;
>>> + desc->callback_param = indio_dev;
>>> +
>>> + dma->cookie = dmaengine_submit(desc);
>>> +
>>> + dma_async_issue_pending(dma->chan);
>>> +
>>> + tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
>>> + tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
>>> + tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
>>> {
>>> struct tiadc_device *adc_dev = iio_priv(indio_dev);
>>> @@ -218,20 +297,30 @@ static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
>>> static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
>>> {
>>> struct tiadc_device *adc_dev = iio_priv(indio_dev);
>>> + struct tiadc_dma *dma = &adc_dev->dma;
>>> + unsigned int irq_enable;
>>> unsigned int enb = 0;
>>> u8 bit;
>>>
>>> tiadc_step_config(indio_dev);
>>> - for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels)
>>> + for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) {
>>> enb |= (get_adc_step_bit(adc_dev, bit) << 1);
>>> + adc_dev->total_ch_enabled++;
>>> + }
>>> adc_dev->buffer_en_ch_steps = enb;
>>>
>>> + if (dma->chan)
>>> + tiadc_start_dma(indio_dev);
>>> +
>>> am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb);
>>>
>>> tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES
>>> | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW);
>>> - tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES
>>> - | IRQENB_FIFO1OVRRUN);
>>> +
>>> + irq_enable = IRQENB_FIFO1OVRRUN;
>>> + if (!dma->chan)
>>> + irq_enable |= IRQENB_FIFO1THRES;
>> This changes the non dma behaviour as we no longer set IRQENB_FIFO1THRES.
>> Why? Was it wrong before?
>
> In non DMA case, dms->chan will be NULL and IRQENB_FIFO1THRES interrupt
> will be enabled to pop the ADC samples.
>
oops. Thanks for pointing out how I'd misread this!
So just after the ack from Lee now.
Jonathan
> Regards
> Mugunthan V N
>
>>> + tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable);
>>>
>>> return 0;
>>> }
>>> @@ -239,12 +328,18 @@ static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
>>> static int tiadc_buffer_predisable(struct iio_dev *indio_dev)
>>> {
>>> struct tiadc_device *adc_dev = iio_priv(indio_dev);
>>> + struct tiadc_dma *dma = &adc_dev->dma;
>>> int fifo1count, i, read;
>>>
>>> tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
>>> IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW));
>>> am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps);
>>> adc_dev->buffer_en_ch_steps = 0;
>>> + adc_dev->total_ch_enabled = 0;
>>> + if (dma->chan) {
>>> + tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2);
>>> + dmaengine_terminate_async(dma->chan);
>>> + }
>>>
>>> /* Flush FIFO of leftover data in the time it takes to disable adc */
>>> fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
>>> @@ -430,6 +525,41 @@ static const struct iio_info tiadc_info = {
>>> .driver_module = THIS_MODULE,
>>> };
>>>
>>> +static int tiadc_request_dma(struct platform_device *pdev,
>>> + struct tiadc_device *adc_dev)
>>> +{
>>> + struct tiadc_dma *dma = &adc_dev->dma;
>>> + dma_cap_mask_t mask;
>>> +
>>> + /* Default slave configuration parameters */
>>> + dma->conf.direction = DMA_DEV_TO_MEM;
>>> + dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
>>> + dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
>>> +
>>> + dma_cap_zero(mask);
>>> + dma_cap_set(DMA_CYCLIC, mask);
>>> +
>>> + /* Get a channel for RX */
>>> + dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
>>> + if (IS_ERR(dma->chan)) {
>>> + int ret = PTR_ERR(dma->chan);
>>> +
>>> + dma->chan = NULL;
>>> + return ret;
>>> + }
>>> +
>>> + /* RX buffer */
>>> + dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
>>> + &dma->addr, GFP_KERNEL);
>>> + if (!dma->buf)
>>> + goto err;
>>> +
>>> + return 0;
>>> +err:
>>> + dma_release_channel(dma->chan);
>>> + return -ENOMEM;
>>> +}
>>> +
>>> static int tiadc_parse_dt(struct platform_device *pdev,
>>> struct tiadc_device *adc_dev)
>>> {
>>> @@ -512,8 +642,14 @@ static int tiadc_probe(struct platform_device *pdev)
>>>
>>> platform_set_drvdata(pdev, indio_dev);
>>>
>>> + err = tiadc_request_dma(pdev, adc_dev);
>>> + if (err && err == -EPROBE_DEFER)
>>> + goto err_dma;
>>> +
>>> return 0;
>>>
>>> +err_dma:
>>> + iio_device_unregister(indio_dev);
>>> err_buffer_unregister:
>>> tiadc_iio_buffered_hardware_remove(indio_dev);
>>> err_free_channels:
>>> @@ -525,8 +661,14 @@ static int tiadc_remove(struct platform_device *pdev)
>>> {
>>> struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>>> struct tiadc_device *adc_dev = iio_priv(indio_dev);
>>> + struct tiadc_dma *dma = &adc_dev->dma;
>>> u32 step_en;
>>>
>>> + if (dma->chan) {
>>> + dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
>>> + dma->buf, dma->addr);
>>> + dma_release_channel(dma->chan);
>>> + }
>>> iio_device_unregister(indio_dev);
>>> tiadc_iio_buffered_hardware_remove(indio_dev);
>>> tiadc_channels_remove(indio_dev);
>>> diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
>>> index e45a208..b9a53e0 100644
>>> --- a/include/linux/mfd/ti_am335x_tscadc.h
>>> +++ b/include/linux/mfd/ti_am335x_tscadc.h
>>> @@ -23,6 +23,8 @@
>>> #define REG_IRQENABLE 0x02C
>>> #define REG_IRQCLR 0x030
>>> #define REG_IRQWAKEUP 0x034
>>> +#define REG_DMAENABLE_SET 0x038
>>> +#define REG_DMAENABLE_CLEAR 0x03c
>>> #define REG_CTRL 0x040
>>> #define REG_ADCFSM 0x044
>>> #define REG_CLKDIV 0x04C
>>> @@ -36,6 +38,7 @@
>>> #define REG_FIFO0THR 0xE8
>>> #define REG_FIFO1CNT 0xF0
>>> #define REG_FIFO1THR 0xF4
>>> +#define REG_DMA1REQ 0xF8
>>> #define REG_FIFO0 0x100
>>> #define REG_FIFO1 0x200
>>>
>>> @@ -126,6 +129,10 @@
>>> #define FIFOREAD_DATA_MASK (0xfff << 0)
>>> #define FIFOREAD_CHNLID_MASK (0xf << 16)
>>>
>>> +/* DMA ENABLE/CLEAR Register */
>>> +#define DMA_FIFO0 BIT(0)
>>> +#define DMA_FIFO1 BIT(1)
>>> +
>>> /* Sequencer Status */
>>> #define SEQ_STATUS BIT(5)
>>> #define CHARGE_STEP 0x11
>>>
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH 1/1] arm: dts: imx6ul: 14x14-evk: add the optee node
From: Fabio Estevam @ 2016-10-22 17:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477148229-6940-1-git-send-email-jason.hui.liu@nxp.com>
Hi Jason,
On Sat, Oct 22, 2016 at 12:57 PM, Jason Liu <jason.hui.liu@nxp.com> wrote:
> This patch adds the optee node for the i.MX6UL 14x14 evk board
>
> Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
> ---
> arch/arm/boot/dts/imx6ul-14x14-evk.dts | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
> index e281d50..e68dc19 100644
> --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
> +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
> @@ -30,6 +30,13 @@
> status = "okay";
> };
>
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
It seems we need to wait until the property lands in mainline.
^ permalink raw reply
* [RFC PATCH 0/8] Support GICv3 ITS and vITS in 32-bit mode
From: Marc Zyngier @ 2016-10-22 15:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477042601-15227-1-git-send-email-vladimir.murzin@arm.com>
On Fri, 21 Oct 2016 10:36:33 +0100
Vladimir Murzin <vladimir.murzin@arm.com> wrote:
Hi Vladimir,
> Hi,
>
> This series introduces GICv3 ITS and vITS to 32-bit world. The first
> six patches make it possible to use ITS in a 32-bit guest with vITS on
> 64-bit host. The last two patches extend vITS to 32-bit host.
I quite like this series, mostly because it deletes a bit of code and
fixes a number of shortcomings. My only gripes are than it doesn't
apply to my current tree (see my comment on patch 4), and that this
should effectively be split in two series: one enabling the ITS on
32bit, and the other switching on ITS emulation for 32bit KVM.
Effectively, these series are completely independent.
It also makes it easier for me to merge things as I don't have to
coordinate the merging strategy with... myself. ;-)
Please repost this once the GIC fixes have reached mainline, and this
should be in good shape for a quick merge.
> I used Andrea's its/v8 branch at [1] for testing with the following
> diff on top
>
> diff --git a/arm/aarch32/arm-cpu.c b/arm/aarch32/arm-cpu.c
> index 27a8e17..16bba55 100644
> --- a/arm/aarch32/arm-cpu.c
> +++ b/arm/aarch32/arm-cpu.c
> @@ -12,7 +12,7 @@ static void generate_fdt_nodes(void *fdt, struct kvm *kvm)
> {
> int timer_interrupts[4] = {13, 14, 11, 10};
>
> - gic__generate_fdt_nodes(fdt, IRQCHIP_GICV2);
> + gic__generate_fdt_nodes(fdt, kvm->cfg.arch.irqchip);
> timer__generate_fdt_nodes(fdt, kvm, timer_interrupts);
> }
>
> diff --git a/arm/aarch32/include/kvm/kvm-arch.h b/arm/aarch32/include/kvm/kvm-arch.h
> index 1632e3c..99231f6 100644
> --- a/arm/aarch32/include/kvm/kvm-arch.h
> +++ b/arm/aarch32/include/kvm/kvm-arch.h
> @@ -1,8 +1,8 @@
> #ifndef KVM__KVM_ARCH_H
> #define KVM__KVM_ARCH_H
>
> -#define ARM_GIC_DIST_SIZE 0x1000
> -#define ARM_GIC_CPUI_SIZE 0x2000
> +#define ARM_GIC_DIST_SIZE 0x100000
> +#define ARM_GIC_CPUI_SIZE 0x200000
>
> #define ARM_KERN_OFFSET(...) 0x8000
>
>
> After passing --irqchip=gicv3-its --force-pci to kvmtool I can see
> that MSI is used:
>
> # cat /proc/interrupts
> CPU0
> 18: 1251 GICv3 27 Level arch_timer
> 28: 0 ITS-MSI 49152 Edge virtio3-config
> 29: 0 ITS-MSI 49153 Edge virtio3-input
> 30: 0 ITS-MSI 49154 Edge virtio3-output
> 31: 0 ITS-MSI 32768 Edge virtio2-config
> 32: 2 ITS-MSI 32769 Edge virtio2-input.0
> 33: 1 ITS-MSI 32770 Edge virtio2-output.0
> 34: 0 ITS-MSI 0 Edge virtio0-config
> 35: 303 ITS-MSI 1 Edge virtio0-requests
> 36: 0 ITS-MSI 16384 Edge virtio1-config
> 37: 218 ITS-MSI 16385 Edge virtio1-requests
> IPI0: 0 CPU wakeup interrupts
> IPI1: 0 Timer broadcast interrupts
> IPI2: 0 Rescheduling interrupts
> IPI3: 0 Function call interrupts
> IPI4: 0 CPU stop interrupts
> IPI5: 0 IRQ work interrupts
> IPI6: 0 completion interrupts
> Err: 0
Please also post these patches (I may try it in a model if I feel brave
enough...)!
Thanks,
M.
--
Jazz is not dead. It just smells funny.
^ permalink raw reply
* [RFC PATCH 4/8] irqchip/gicv3-its: specialise readq and writeq accesses
From: Marc Zyngier @ 2016-10-22 15:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477042601-15227-5-git-send-email-vladimir.murzin@arm.com>
On Fri, 21 Oct 2016 10:36:37 +0100
Vladimir Murzin <vladimir.murzin@arm.com> wrote:
Hi Vladimir,
> readq and writeq type of assessors are not supported in AArch32, so we
> need to specialise them and glue later with series of 32-bit accesses
> on AArch32 side.
>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
> arch/arm64/include/asm/arch_gicv3.h | 16 ++++++++++++++++
> drivers/irqchip/irq-gic-v3-its.c | 30 +++++++++++++++---------------
> 2 files changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
> index 4f0402a..e0ada98 100644
> --- a/arch/arm64/include/asm/arch_gicv3.h
> +++ b/arch/arm64/include/asm/arch_gicv3.h
> @@ -190,5 +190,21 @@ static inline void gic_write_bpr1(u32 val)
>
> #define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
>
> +#define gits_read_typer(c) readq_relaxed(c)
> +
> +#define gits_read_baser(c) readq_relaxed(c)
> +#define gits_write_baser(v, c) writeq_relaxed(v, c)
> +
> +#define gits_read_cbaser(c) readq_relaxed(c)
> +#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
> +
> +#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
> +
> +#define gicr_read_propbaser(c) readq_relaxed(c)
> +#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
> +
> +#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
> +#define gicr_read_pendbaser(c) readq_relaxed(c)
> +
> #endif /* __ASSEMBLY__ */
> #endif /* __ASM_ARCH_GICV3_H */
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 86efa6e..9f74abc 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -835,7 +835,7 @@ static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
> {
> u32 idx = baser - its->tables;
>
> - return readq_relaxed(its->base + GITS_BASER + (idx << 3));
> + return gits_read_baser(its->base + GITS_BASER + (idx << 3));
> }
>
> static void its_write_baser(struct its_node *its, struct its_baser *baser,
> @@ -843,7 +843,7 @@ static void its_write_baser(struct its_node *its, struct its_baser *baser,
> {
> u32 idx = baser - its->tables;
>
> - writeq_relaxed(val, its->base + GITS_BASER + (idx << 3));
> + gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
> baser->val = its_read_baser(its, baser);
> }
>
> @@ -1022,7 +1022,7 @@ static void its_free_tables(struct its_node *its)
>
> static int its_alloc_tables(struct its_node *its)
> {
> - u64 typer = readq_relaxed(its->base + GITS_TYPER);
> + u64 typer = gits_read_typer(its->base + GITS_TYPER);
This is going to conflict with the irq/irq-fixes-4.9 branch, which is
already on its way to mainline (and will hopefully hit -rc2) Could you
please rebase it once these patches are in mainline?
You'll notice that I didn't bother distinguishing between the various
GI*_TYPER registers, as they all have the same behaviour.
Otherwise looks good to me.
Thanks,
M.
--
Jazz is not dead. It just smells funny.
^ permalink raw reply
* [PATCH v3 1/3] mtd: s3c2410: make ecc mode configurable via platform data
From: Krzysztof Kozlowski @ 2016-10-22 15:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161022142907.08a3eedf@bbrezillon>
On Sat, Oct 22, 2016 at 02:29:07PM +0200, Boris Brezillon wrote:
> Hi Krzysztof,
>
> On Fri, 21 Oct 2016 21:27:10 +0300
> Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> > On Thu, Oct 20, 2016 at 07:42:44PM -0200, Sergio Prado wrote:
> > > Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode
> > > field in the drivers's platform data structure so it can be selectable
> > > via platform data.
> > >
> > > Also setting this field to NAND_ECC_SOFT in all boards using this
> > > driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.
> > >
> > > Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
> > > ---
> > > arch/arm/mach-s3c24xx/common-smdk.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-anubis.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-at2440evb.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-bast.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-gta02.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-jive.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-mini2440.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-osiris.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-qt2410.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-rx1950.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-rx3715.c | 1 +
> > > arch/arm/mach-s3c24xx/mach-vstms.c | 1 +
> > > arch/arm/mach-s3c64xx/mach-hmt.c | 1 +
> > > arch/arm/mach-s3c64xx/mach-mini6410.c | 1 +
> > > arch/arm/mach-s3c64xx/mach-real6410.c | 1 +
> > > drivers/mtd/nand/Kconfig | 9 --
> > > drivers/mtd/nand/s3c2410.c | 119 +++++++++++++------------
> > > include/linux/platform_data/mtd-nand-s3c2410.h | 6 +-
> > > 18 files changed, 79 insertions(+), 70 deletions(-)
> > >
> >
> > I acked this twice (v1 and v2)... and still you are ignoring them. I am
> > sorry, I am not gonna to ack this third time!
> >
> > For v2 I acked also other patches but it it is not there as well...
>
> I'll collect your acks (and Rob ones) when applying the patches. BTW,
> how should I proceed with patch 1? Do you want an topic branch
> containing this patch?
I don't expect much work around these files so the risk of conflicts is
rather small. You could put it on a topic branch just in case (so I
could pull in if needed) but I am fine with applying these to your tree
as is.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH V4 2/3] Revert "ACPI,PCI,IRQ: remove SCI penalize function"
From: Bjorn Helgaas @ 2016-10-22 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2a824792-486a-6251-4931-c5cc6fd67978@codeaurora.org>
On Fri, Oct 21, 2016 at 09:13:06AM -0700, Sinan Kaya wrote:
> On 10/21/2016 7:45 AM, Bjorn Helgaas wrote:
> > [1] http://marc.info/?l=linux-acpi&m=145580159209240&w=2)
> >
> >> > Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> > Wait a minute, I still have a question here: what about other ACPI
> > arches (ia64, arm64)? Don't they need to call acpi_penalize_sci_irq()
> > somewhere?
> >
>
> ACPI ARM64 architecture implements reduced ACPI profile which doesn't
> have GED object. Instead, ARM64 architecture uses onchip peripherals
> for similar functionality. If there is a need to signal interrupts,
> this is done by ACPI Notify in ASL or if absolutely needed using
> ACPI Generic Event Device (GED).
OK. I guess ia64 never did call acpi_penalize_sci_irq(), so while it
could be added someday to unify things, we don't need to add it now.
Same for arm64.
So I'd like it if you updated the changelog, but I'm OK with the
patch:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
^ permalink raw reply
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