* [PATCH/RFT v2 12/17] USB: ochi-da8xx: Use a regulator for vbus/overcurrent
From: Axel Haslam @ 2016-10-25 10:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d7e2b356-4874-fdc1-c505-70e57e3908de@ti.com>
On Tue, Oct 25, 2016 at 12:43 PM, Sekhar Nori <nsekhar@ti.com> wrote:
> On Monday 24 October 2016 10:16 PM, ahaslam at baylibre.com wrote:
>> From: Axel Haslam <ahaslam@baylibre.com>
>>
>> Currently, the da8xx ohci driver uses a set of gpios and callbacks in
>> board files to handle vbus and overcurrent irqs form the power supply.
>> However, this does not play nice when moving to a DT based boot were
>> we wont have board files.
>>
>> Instead of requesting and handling the gpio, use the regulator framework
>> to take care of enabling and disabling vbus power. This has the benefit
>> that we dont need to pass any more platform data to the driver:
>>
>> These will be handled by the regulator framework:
>> set_power -> regulator_enable/regulator_disable
>> get_power -> regulator_is_enabled
>> get_oci -> regulator_get_mode
>> ocic_notify -> regulator notification
>>
>> We can keep the default potpgt and use the regulator start delay instead:
>> potpgt -> regulator startup delay time
>>
>> The hawk board does not have a GPIO/OVERCURRENT gpio to control vbus,
>> (they should not have been decleared/reserved) so, just remove those
>> definitions from the hwk board file.
>>
>> Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
>> ---
>> arch/arm/mach-davinci/board-da830-evm.c | 97 ++++++++----------------
>> arch/arm/mach-davinci/board-omapl138-hawk.c | 96 +-----------------------
>> arch/arm/mach-davinci/include/mach/da8xx.h | 2 +-
>> arch/arm/mach-davinci/usb-da8xx.c | 3 +-
>> drivers/usb/host/ohci-da8xx.c | 111 ++++++++++++++++++----------
>> include/linux/platform_data/usb-davinci.h | 19 -----
>> 6 files changed, 105 insertions(+), 223 deletions(-)
>
> Can you separate out the driver enhancement from the platform
> (mach-davinci) changes? They need to go through different trees.
>
Ok, i will do that, (it might require intermediate code to have
the driver working on each patch)
> Thanks,
> Sekhar
>
>
^ permalink raw reply
* [RFC] shutdown machine when li-ion battery goes below 3V
From: Pali Rohár @ 2016-10-25 10:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161025102435.GA6916@amd>
On Tuesday 25 October 2016 12:24:35 Pavel Machek wrote:
> On Mon 2016-10-24 23:48:47, Pali Roh?r wrote:
> > On Monday 24 October 2016 23:41:52 Pavel Machek wrote:
> > > On Mon 2016-10-24 14:29:33, Tony Lindgren wrote:
> > > > Also, the shutdown voltage can depend on external devices
> > > > connected. It could be for example 3.3V depending on eMMC on some
> > > > devices while devices with no eMMC could have it at 3.0V.
> > >
> > > Actually, I'd like to shutdown at 3.3V or more (like 3.5V), because
> > > going below that is pretty mean to the battery. But if I set
> > > threshold too high, GSM activity will push it below that for a very
> > > short while, and I'll shutdown too soon.
> > >
> > > Ideas welcome...
> >
> > bq27x00 has EDVF flag which means that battery is empty. Maemo with
> > bq27x00 driver is configured to issue system shutdown when EDVF is set.
> >
> > Maybe kernel should issue emergency shutdown e.g. after minute or two
> > after EDVF flag is set?
>
> Thanks for pointer.
>
> EDVF seems to be exposed as health. ... but only if battery is
> calibrated, AFAICT.
No, EDVF is available also for uncalibrated battery. There are EDV1 and
EDVF flags. Both are set based on battery voltage and some other
parameters from bq EEPROM.
> if (has_ci_flag && (cache.flags & BQ27000_FLAG_CI)) {
> dev_info_once(di->dev, "battery is not calibrated! ignoring capacity values\n");
Yes, it ignores only capacity values (which needs calibration), not
those raw flags which works also without calibration.
> ...
> cache.health = -ENODATA;
>
> Plus, it prioritizes battery cold over battery dead. IMO we don't need
> to shutdown on battery cold (we just may not charge the battery), but
> we need to shutdown on battery dead.
>
> So something like this?
>
> Pavel
>
> Signed-off-by: Pavel Machek <pavel@ucw.cz>
>
> diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c
> index 8eb2f8f..5ddf6d7 100644
> --- a/drivers/power/supply/bq27xxx_battery.c
> +++ b/drivers/power/supply/bq27xxx_battery.c
> @@ -680,10 +680,10 @@ static int bq27xxx_battery_read_health(struct bq27xxx_device_info *di)
> /* Unlikely but important to return first */
> if (unlikely(bq27xxx_battery_overtemp(di, flags)))
> return POWER_SUPPLY_HEALTH_OVERHEAT;
> - if (unlikely(bq27xxx_battery_undertemp(di, flags)))
> - return POWER_SUPPLY_HEALTH_COLD;
> if (unlikely(bq27xxx_battery_dead(di, flags)))
> return POWER_SUPPLY_HEALTH_DEAD;
> + if (unlikely(bq27xxx_battery_undertemp(di, flags)))
> + return POWER_SUPPLY_HEALTH_COLD;
>
> return POWER_SUPPLY_HEALTH_GOOD;
> }
>
>
Looks like this is OK.
--
Pali Roh?r
pali.rohar at gmail.com
^ permalink raw reply
* [PATCH/RFT v2 00/17] Add DT support for ohci-da8xx
From: Sekhar Nori @ 2016-10-25 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161024164634.4330-1-ahaslam@baylibre.com>
Hi Axel,
On Monday 24 October 2016 10:16 PM, ahaslam at baylibre.com wrote:
> From: Axel Haslam <ahaslam@baylibre.com>
>
> The purpose of this patch series is to add DT support and modernize
> the ohci-da8xx glue driver without breaking the non-DT boot,
> which is still used in unconverted davinci devices.
>From a mach-davinci perspective, there are some patches which seem to be
safe to apply and some which depend on corresponding driver changes to
get in.
In order to speed up the process of applying this series, can you split
the mach-davinci updates which are safe to apply into a separate series.
For DT patches, the bindings should be accepted. For other patches, they
should not be causing any regressions.
Thanks,
Sekhar
^ permalink raw reply
* [RFC] shutdown machine when li-ion battery goes below 3V
From: Pavel Machek @ 2016-10-25 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161025105320.GK12154@pali>
On Tue 2016-10-25 12:53:20, Pali Roh?r wrote:
> On Tuesday 25 October 2016 12:24:35 Pavel Machek wrote:
> > On Mon 2016-10-24 23:48:47, Pali Roh?r wrote:
> > > On Monday 24 October 2016 23:41:52 Pavel Machek wrote:
> > > > On Mon 2016-10-24 14:29:33, Tony Lindgren wrote:
> > > > > Also, the shutdown voltage can depend on external devices
> > > > > connected. It could be for example 3.3V depending on eMMC on some
> > > > > devices while devices with no eMMC could have it at 3.0V.
> > > >
> > > > Actually, I'd like to shutdown at 3.3V or more (like 3.5V), because
> > > > going below that is pretty mean to the battery. But if I set
> > > > threshold too high, GSM activity will push it below that for a very
> > > > short while, and I'll shutdown too soon.
> > > >
> > > > Ideas welcome...
> > >
> > > bq27x00 has EDVF flag which means that battery is empty. Maemo with
> > > bq27x00 driver is configured to issue system shutdown when EDVF is set.
> > >
> > > Maybe kernel should issue emergency shutdown e.g. after minute or two
> > > after EDVF flag is set?
> >
> > Thanks for pointer.
> >
> > EDVF seems to be exposed as health. ... but only if battery is
> > calibrated, AFAICT.
>
> No, EDVF is available also for uncalibrated battery. There are EDV1 and
> EDVF flags. Both are set based on battery voltage and some other
> parameters from bq EEPROM.
>
> > if (has_ci_flag && (cache.flags & BQ27000_FLAG_CI)) {
> > dev_info_once(di->dev, "battery is not calibrated! ignoring capacity values\n");
>
> Yes, it ignores only capacity values (which needs calibration), not
> those raw flags which works also without calibration.
>
> > ...
> > cache.health = -ENODATA;
Take a look at code. Health is not read from hardware unless battery
is calibrated.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* [RFC] shutdown machine when li-ion battery goes below 3V
From: Pali Rohár @ 2016-10-25 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161025105604.GA25855@amd>
On Tuesday 25 October 2016 12:56:04 Pavel Machek wrote:
> Take a look at code. Health is not read from hardware unless battery
> is calibrated.
Then it is bug. EDVF should be accepted also when battery is not
calibrated.
--
Pali Roh?r
pali.rohar at gmail.com
^ permalink raw reply
* [PATCH 5/5] ARM: dts: Add LEGO MINDSTORTMS EV3 dts
From: Sekhar Nori @ 2016-10-25 10:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <84648cb0-f1fa-d88b-bac2-79208af01ca6@lechnology.com>
On Tuesday 25 October 2016 02:50 AM, David Lechner wrote:
> On 10/24/2016 02:50 PM, David Lechner wrote:
>> On 10/24/2016 10:50 AM, David Lechner wrote:
>>> On 10/24/2016 06:58 AM, Sekhar Nori wrote:
>>>> On Saturday 22 October 2016 12:06 AM, David Lechner wrote:
>>>>
>>>>> +&ehrpwm1 {
>>>>> + status = "disabled";
>>>>
>>>> Hmm, disabled? Can you add this node when you actually use it?
>>>
>>> Not sure why I have this disabled. Like the gpios, the pwms can be used
>>> via sysfs, so I would like to leave them.
>>>
>>
>> Now I remember why these are disabled. The clock matching is broken.
>> Only the first ehrpwm and the first ecap get clocks. The others fail.
>>
>> I can change these to "okay". It will just result in a kernel error
>> message until the clocks are fixed.
>>
>
> correction: it is not the clocks that are broken. it is the device names.
>
> In arch/arm/mach-davinci/da8xx-dt.c, we have...
>
>
> OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm", NULL),
> OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm", NULL),
> OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap", NULL),
> OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL),
> OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL),
>
>
> Which causes each device to have the same device node name. This causes
> sysfs errors because it is trying to register a second device at the
> same sysfs path.
>
> If you change the names here, then the device do not work because the
> clock lookup fails.
Yeah, this is incorrect (I should have caught it in review). The device
id should have been present in the lookup. Can you fix auxdata and clock
lookup too and send a separate patch? Its probably a v4.9-rc candidate.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] convert orion5x ls-chl to device tree
From: Andrew Lunn @ 2016-10-25 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <14522899-679b-2f8b-73ca-493788299790@gmail.com>
On Tue, Oct 25, 2016 at 12:04:49AM +0100, Ash Hughes wrote:
> Hi all,
>
> This patch converts my orion5x ls-chl Linkstation device to device tree.
>
> Signed-off-by: Ashley Hughes <ashley.hughes@blueyonder.co.uk>
Hi Ash
Nicely done.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [RFC] shutdown machine when li-ion battery goes below 3V
From: Pavel Machek @ 2016-10-25 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161024212932.uhjz752z2cy5hohl@atomide.com>
On Mon 2016-10-24 14:29:33, Tony Lindgren wrote:
> * Pavel Machek <pavel@ucw.cz> [161024 14:24]:
> > Hi!
> >
> > What about something like this? N900 will drain the battery down to
> > system crash, which is quite uncool.
>
> Can't we make that generic and configurable for the voltage somehow?
>
> Also, the shutdown voltage can depend on external devices connected.
> It could be for example 3.3V depending on eMMC on some devices while
> devices with no eMMC could have it at 3.0V.
Actually, do we need to make it configurable? It looks like we should
respect hardware telling us battery is dead, and only use (low)
hardcoded voltages as a fallback.
Currently patch looks like this. generic_protect() should work for
other batteries drivers, too.
Pavel
diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c
index 0fe278b..04094ad 100644
--- a/drivers/power/supply/bq27xxx_battery.c
+++ b/drivers/power/supply/bq27xxx_battery.c
@@ -46,6 +46,7 @@
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/power_supply.h>
+#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/of.h>
@@ -679,10 +680,10 @@ static int bq27xxx_battery_read_health(struct bq27xxx_device_info *di)
/* Unlikely but important to return first */
if (unlikely(bq27xxx_battery_overtemp(di, flags)))
return POWER_SUPPLY_HEALTH_OVERHEAT;
- if (unlikely(bq27xxx_battery_undertemp(di, flags)))
- return POWER_SUPPLY_HEALTH_COLD;
if (unlikely(bq27xxx_battery_dead(di, flags)))
return POWER_SUPPLY_HEALTH_DEAD;
+ if (unlikely(bq27xxx_battery_undertemp(di, flags)))
+ return POWER_SUPPLY_HEALTH_COLD;
return POWER_SUPPLY_HEALTH_GOOD;
}
@@ -740,6 +741,49 @@ void bq27xxx_battery_update(struct bq27xxx_device_info *di)
}
EXPORT_SYMBOL_GPL(bq27xxx_battery_update);
+static void shutdown(char *reason)
+{
+ pr_alert("%s Forcing shutdown\n", reason);
+ orderly_poweroff(true);
+}
+
+static int generic_protect(struct power_supply *psy)
+{
+ union power_supply_propval val;
+ int res;
+ int mV, mA, mOhm = 430, mVadj = 0;
+
+ res = psy->desc->get_property(psy, POWER_SUPPLY_PROP_HEALTH, &val);
+ if (res)
+ return res;
+
+ if (val.intval == POWER_SUPPLY_HEALTH_OVERHEAT)
+ shutdown("Battery overheat.");
+ if (val.intval == POWER_SUPPLY_HEALTH_DEAD)
+ shutdown("Battery dead.");
+
+ res = psy->desc->get_property(psy, POWER_SUPPLY_PROP_VOLTAGE_NOW, &val);
+ if (res)
+ return res;
+ mV = val.intval / 1000;
+
+ if (mV < 2950)
+ shutdown("Battery below 2.95V.");
+
+ res = psy->desc->get_property(psy, POWER_SUPPLY_PROP_CURRENT_NOW, &val);
+ if (res)
+ return res;
+ mA = val.intval / 1000;
+ mVadj = mV + (mA * mOhm) / 1000;
+
+ if (mVadj < 3150)
+ shutdown("Battery internal voltage below 3.15.");
+
+ printk(KERN_INFO "Main battery %d mV, internal voltage %d mV\n",
+ mV, mVadj);
+ return 0;
+}
+
static void bq27xxx_battery_poll(struct work_struct *work)
{
struct bq27xxx_device_info *di =
@@ -747,6 +791,7 @@ static void bq27xxx_battery_poll(struct work_struct *work)
work.work);
bq27xxx_battery_update(di);
+ generic_protect(di->bat);
if (poll_interval > 0)
schedule_delayed_work(&di->work, poll_interval * HZ);
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply related
* [RFC] shutdown machine when li-ion battery goes below 3V
From: Pali Rohár @ 2016-10-25 11:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161025112757.GC25855@amd>
On Tuesday 25 October 2016 13:27:57 Pavel Machek wrote:
> On Mon 2016-10-24 14:29:33, Tony Lindgren wrote:
> > * Pavel Machek <pavel@ucw.cz> [161024 14:24]:
> > > Hi!
> > >
> > > What about something like this? N900 will drain the battery down to
> > > system crash, which is quite uncool.
> >
> > Can't we make that generic and configurable for the voltage somehow?
> >
> > Also, the shutdown voltage can depend on external devices connected.
> > It could be for example 3.3V depending on eMMC on some devices while
> > devices with no eMMC could have it at 3.0V.
>
> Actually, do we need to make it configurable? It looks like we should
> respect hardware telling us battery is dead, and only use (low)
> hardcoded voltages as a fallback.
>
> Currently patch looks like this. generic_protect() should work for
> other batteries drivers, too.
Now I checked Maemo's BME replacement code and it shutdown device 10
seconds after it read that capacity level is LOW or CRITICAL. bq27xxx
driver reports LOW when EDV1 is set and CRITICAL when EDVF is set. And
bq27xxx reports those LOW/CRITICAL based on EDV1/EDVF flags even if
battery is not calibrated.
So I would be happy if kernel does not issue emergency shutdown before
Maemo's BME replacement issue own "correct" system shutdown. As Maemo is
doing it on EDV1 flag (not EDVF as I thought!) with 10 seconds delay and
check is done every 30 seconds it means that Maemo shutdown process in
worst case is started 40 seconds after EDV1 is set. Shutdown process is
about 60 seconds (probably max.), can we ensure that kernel does not do
its own emergency shutdown earlier then 2 minutes before first see EDV1
flag? Or can test that EDVF flag is set in most cases 2 minutes after
EDV1?
It is really bad idea to start emergency kernel shutdown before even
userspace do it!
> Pavel
>
> diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c
> index 0fe278b..04094ad 100644
> --- a/drivers/power/supply/bq27xxx_battery.c
> +++ b/drivers/power/supply/bq27xxx_battery.c
> @@ -46,6 +46,7 @@
> #include <linux/delay.h>
> #include <linux/platform_device.h>
> #include <linux/power_supply.h>
> +#include <linux/reboot.h>
> #include <linux/slab.h>
> #include <linux/of.h>
>
> @@ -679,10 +680,10 @@ static int bq27xxx_battery_read_health(struct bq27xxx_device_info *di)
> /* Unlikely but important to return first */
> if (unlikely(bq27xxx_battery_overtemp(di, flags)))
> return POWER_SUPPLY_HEALTH_OVERHEAT;
> - if (unlikely(bq27xxx_battery_undertemp(di, flags)))
> - return POWER_SUPPLY_HEALTH_COLD;
> if (unlikely(bq27xxx_battery_dead(di, flags)))
> return POWER_SUPPLY_HEALTH_DEAD;
> + if (unlikely(bq27xxx_battery_undertemp(di, flags)))
> + return POWER_SUPPLY_HEALTH_COLD;
>
> return POWER_SUPPLY_HEALTH_GOOD;
> }
> @@ -740,6 +741,49 @@ void bq27xxx_battery_update(struct bq27xxx_device_info *di)
> }
> EXPORT_SYMBOL_GPL(bq27xxx_battery_update);
>
> +static void shutdown(char *reason)
> +{
> + pr_alert("%s Forcing shutdown\n", reason);
> + orderly_poweroff(true);
> +}
> +
> +static int generic_protect(struct power_supply *psy)
> +{
> + union power_supply_propval val;
> + int res;
> + int mV, mA, mOhm = 430, mVadj = 0;
> +
> + res = psy->desc->get_property(psy, POWER_SUPPLY_PROP_HEALTH, &val);
> + if (res)
> + return res;
> +
> + if (val.intval == POWER_SUPPLY_HEALTH_OVERHEAT)
> + shutdown("Battery overheat.");
> + if (val.intval == POWER_SUPPLY_HEALTH_DEAD)
> + shutdown("Battery dead.");
Generally this is not a good idea. On some boards with bq27xxx devices
you can have another battery device or connected power device. You could
have "dead" battery but device supplied e.g. from wallcharger.
N900 cannot be powered from wallcharger by default, but in specific
conditions (turned everything except display) you can do battery
hotswap (when wallcharger is connected; it can power system).
So this patch basically break lot of other self powered devices.
I would propose check for am_i_power_supplied() (function with such name
in power_supply interface exist) and do that only for negative response.
> + res = psy->desc->get_property(psy, POWER_SUPPLY_PROP_VOLTAGE_NOW, &val);
> + if (res)
> + return res;
> + mV = val.intval / 1000;
> +
> + if (mV < 2950)
> + shutdown("Battery below 2.95V.");
> +
> + res = psy->desc->get_property(psy, POWER_SUPPLY_PROP_CURRENT_NOW, &val);
> + if (res)
> + return res;
> + mA = val.intval / 1000;
> + mVadj = mV + (mA * mOhm) / 1000;
> +
> + if (mVadj < 3150)
> + shutdown("Battery internal voltage below 3.15.");
> +
> + printk(KERN_INFO "Main battery %d mV, internal voltage %d mV\n",
> + mV, mVadj);
Please no printk. There is dev_info or how is that function called. And
spamming dmesg for every poll is not good idea. It should be probably
DEBUG not INFO.
> + return 0;
> +}
> +
> static void bq27xxx_battery_poll(struct work_struct *work)
> {
> struct bq27xxx_device_info *di =
> @@ -747,6 +791,7 @@ static void bq27xxx_battery_poll(struct work_struct *work)
> work.work);
>
> bq27xxx_battery_update(di);
> + generic_protect(di->bat);
>
> if (poll_interval > 0)
> schedule_delayed_work(&di->work, poll_interval * HZ);
>
--
Pali Roh?r
pali.rohar at gmail.com
^ permalink raw reply
* [PATCH v3 3/6] dt-bindings: pinctrl: Deprecate sunxi pinctrl bindings
From: Linus Walleij @ 2016-10-25 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161024194917.g5oezqc4uacsyt24@lukather>
On Mon, Oct 24, 2016 at 9:49 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> However, it looks like the first patch from this serie is missing from
> your tree, is there a reason for that?
No can you point it out?
> Also, in order to preserve bisectability, could you create an
> immutable branch for those sunxi patches so that I can merge the DT
> bits?
It's too late because they are already in the devel branch
and mixed up with merged of *other* immutable stuff.
However I think it is plain wrong to try to keep any bisectability
between the kernel at large and arch/*/boot/dts/*, because
the DTS stuff is supposed to at some point be maintained outside
of the kernel and for all OSes, they simply shouldn't be sync:ed.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2] Fix some potential warnings
From: Alexandre Bailon @ 2016-10-25 12:11 UTC (permalink / raw)
To: linux-arm-kernel
Some changes I'm working on causes some warning because two included
headers defines the same macros.
Change in V2:
Update the d830 evm board file to use the da8xx-cfgchip.h
These changes are required as I'm sending this patch apart from
the series "[PATCH/RFT v2 00/17] Add DT support for ohci-da8xx"
Alexandre Bailon (1):
ARM: davinci: da8xx: Fix some redefined symbol warnings
arch/arm/mach-davinci/board-da830-evm.c | 3 ++-
include/linux/platform_data/usb-davinci.h | 23 -----------------------
2 files changed, 2 insertions(+), 24 deletions(-)
--
2.7.3
^ permalink raw reply
* [PATCH v2] ARM: davinci: da8xx: Fix some redefined symbol warnings
From: Alexandre Bailon @ 2016-10-25 12:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477397492-7925-1-git-send-email-abailon@baylibre.com>
Some macro for DA8xx CFGCHIP are defined in usb-davinci.h,
but da8xx-cfgchip.h intend to replace them.
The usb-da8xx.c is using both headers, causing redefined symbol warnings.
Remove the macro and update the da830-evm board file to use da8xx-cfgchip.h
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
---
arch/arm/mach-davinci/board-da830-evm.c | 3 ++-
include/linux/platform_data/usb-davinci.h | 23 -----------------------
2 files changed, 2 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 3d8cf8c..9817316 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -27,6 +27,7 @@
#include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/spi-davinci.h>
#include <linux/platform_data/usb-davinci.h>
+#include <linux/mfd/da8xx-cfgchip.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -133,7 +134,7 @@ static __init void da830_evm_usb_init(void)
* controller won't be able to drive VBUS thinking that it's a B-device.
* Otherwise, we want to use the OTG mode and enable VBUS comparators.
*/
- cfgchip2 &= ~CFGCHIP2_OTGMODE;
+ cfgchip2 &= ~CFGCHIP2_OTGMODE_MASK;
#ifdef CONFIG_USB_MUSB_HOST
cfgchip2 |= CFGCHIP2_FORCE_HOST;
#else
diff --git a/include/linux/platform_data/usb-davinci.h b/include/linux/platform_data/usb-davinci.h
index e0bc4ab..0926e99 100644
--- a/include/linux/platform_data/usb-davinci.h
+++ b/include/linux/platform_data/usb-davinci.h
@@ -11,29 +11,6 @@
#ifndef __ASM_ARCH_USB_H
#define __ASM_ARCH_USB_H
-/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
-#define CFGCHIP2_PHYCLKGD (1 << 17)
-#define CFGCHIP2_VBUSSENSE (1 << 16)
-#define CFGCHIP2_RESET (1 << 15)
-#define CFGCHIP2_OTGMODE (3 << 13)
-#define CFGCHIP2_NO_OVERRIDE (0 << 13)
-#define CFGCHIP2_FORCE_HOST (1 << 13)
-#define CFGCHIP2_FORCE_DEVICE (2 << 13)
-#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
-#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
-#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
-#define CFGCHIP2_PHYPWRDN (1 << 10)
-#define CFGCHIP2_OTGPWRDN (1 << 9)
-#define CFGCHIP2_DATPOL (1 << 8)
-#define CFGCHIP2_USB1SUSPENDM (1 << 7)
-#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
-#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
-#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
-#define CFGCHIP2_REFFREQ (0xf << 0)
-#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
-#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
-#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
-
struct da8xx_ohci_root_hub;
typedef void (*da8xx_ocic_handler_t)(struct da8xx_ohci_root_hub *hub,
--
2.7.3
^ permalink raw reply related
* [PATCH/RFT v2 06/17] ARM: davinci: da8xx: Fix some redefined symbol warnings
From: Alexandre Bailon @ 2016-10-25 12:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9fa01842-cf8e-87e9-75ce-5d4b2841fdfe@ti.com>
On 10/25/2016 12:03 PM, Sekhar Nori wrote:
> On Monday 24 October 2016 10:16 PM, ahaslam at baylibre.com wrote:
>> From: Alexandre Bailon <abailon@baylibre.com>
>>
>> Some macro for DA8xx CFGCHIP are defined in usb-davinci.h,
>> but da8xx-cfgchip.h intend to replace them.
>> The usb-da8xx.c is using both headers, causing redefined symbol warnings.
>> Remove the old macros.
>>
>> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
>
> This is a v4.9-rc bug fix. Can you please post it as a separate patch
> for Greg to pick up?
>
Done
> You can add:
>
> Acked-by: Sekhar Nori <nsekhar@ti.com>
Actually, I didn't add it because I had to make few changes to
submit as a separate patch. I hope I did it in right way.
>
> Thanks,
> Sekhar
>
Thanks,
Alexandre
^ permalink raw reply
* [v17 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
From: Matthias Brugger @ 2016-10-25 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFqH_50_OwsbMWHkT_eukF52BVZYyMbGiamXO=pV4PpJq6BADA@mail.gmail.com>
On 10/18/2016 04:37 PM, Enric Balletbo Serra wrote:
[...]
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
[...]
>> +
>> +/* Firmware */
>> +#define PS_FW_NAME "ps864x_fw.bin"
>> +
>
> From where I can download this firmware image?
>
I suppose this FW bits have to be added to linux-firmware repository
first, before this patch can be accepted.
Regards,
Matthias
^ permalink raw reply
* [PATCH 1/6] dt/bindings: adjust bindings for Layerscape SCFG MSI
From: Minghuan Lian @ 2016-10-25 12:35 UTC (permalink / raw)
To: linux-arm-kernel
1. The different version of a SoC may have different MSI
implementation. But compatible "fsl,<soc-name>-msi" can not describe
the SoC version. The MSI driver will use SoC match interface to get
SoC type and version instead of compatible string. So all MSI node
can use the common compatible "fsl,ls-scfg-msi" and the original
compatible is unnecessary.
2. Layerscape SoCs may have one or several MSI controllers.
In order to increase MSI interrupt number of a PCIe, the patch
moves all MSI node into the parent node "msi-controller". So a
PCIe can request MSI from all the MSI controllers.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
.../interrupt-controller/fsl,ls-scfg-msi.txt | 57 +++++++++++++++++++---
1 file changed, 49 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index 9e38949..29f95fd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -1,18 +1,28 @@
* Freescale Layerscape SCFG PCIe MSI controller
+Layerscape SoCs may have one or multiple MSI controllers.
+Each MSI controller must be showed as a child node.
+
Required properties:
-- compatible: should be "fsl,<soc-name>-msi" to identify
- Layerscape PCIe MSI controller block such as:
- "fsl,1s1021a-msi"
- "fsl,1s1043a-msi"
+- compatible: should be "fsl,ls-scfg-msi"
+- #address-cells: must be 2
+- #size-cells: must be 2
+- ranges: allows valid 1:1 translation between child's address space and
+ parent's address space
- msi-controller: indicates that this is a PCIe MSI controller node
+
+Required child node:
+A child node must exist to represent the MSI controller.
+The following are properties specific to those nodes:
+
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
Optional properties:
- interrupt-parent: the phandle to the parent interrupt controller.
+Notes:
This interrupt controller hardware is a second level interrupt controller that
is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
platforms. If interrupt-parent is not provided, the default parent interrupt
@@ -22,9 +32,40 @@ MSI controller node
Examples:
- msi1: msi-controller at 1571000 {
- compatible = "fsl,1s1043a-msi";
- reg = <0x0 0x1571000 0x0 0x8>,
+ msi: msi-controller {
+ compatible = "fsl,ls-scfg-msi";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
msi-controller;
- interrupts = <0 116 0x4>;
+
+ msi0 at 1580000 {
+ reg = <0x0 0x1580000 0x0 0x10000>;
+ interrupts = <0 116 0x4>,
+ <0 111 0x4>,
+ <0 112 0x4>,
+ <0 113 0x4>;
+ };
+
+ msi1 at 1590000 {
+ reg = <0x0 0x1590000 0x0 0x10000>;
+ interrupts = <0 126 0x4>,
+ <0 121 0x4>,
+ <0 122 0x4>,
+ <0 123 0x4>;
+ };
+
+ msi2 at 15a0000 {
+ reg = <0x0 0x15a0000 0x0 0x10000>;
+ interrupts = <0 160 0x4>,
+ <0 155 0x4>,
+ <0 156 0x4>,
+ <0 157 0x4>;
+ };
+ };
+
+ pcie at 3400000 {
+ ...
+ msi-parent = <&msi>;
+ ...
};
--
1.9.1
^ permalink raw reply related
* [PATCH 2/6] arm: dts: ls1021a: update MSI node
From: Minghuan Lian @ 2016-10-25 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477398945-22774-1-git-send-email-Minghuan.Lian@nxp.com>
1. Change compatible to "fsl,ls-scfg-msi"
2. Move two MSI dts node into the parent node "msi-controller".
So a PCIe device can request the MSI from the two MSI controllers.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 28 ++++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..7a3b510 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -119,18 +119,22 @@
};
- msi1: msi-controller at 1570e00 {
- compatible = "fsl,1s1021a-msi";
- reg = <0x0 0x1570e00 0x0 0x8>;
+ msi: msi-controller {
+ compatible = "fsl,ls-scfg-msi";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
msi-controller;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- };
- msi2: msi-controller at 1570e08 {
- compatible = "fsl,1s1021a-msi";
- reg = <0x0 0x1570e08 0x0 0x8>;
- msi-controller;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ msi0 at 1570e00 {
+ reg = <0x0 0x1570e00 0x0 0x8>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ msi1 at 1570e08 {
+ reg = <0x0 0x1570e08 0x0 0x8>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
ifc: ifc at 1530000 {
@@ -643,7 +647,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi1>;
+ msi-parent = <&msi>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -666,7 +670,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi2>;
+ msi-parent = <&msi>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
--
1.9.1
^ permalink raw reply related
* [PATCH 3/6] arm64: dts: ls1043a: update MSI and PCIe node
From: Minghuan Lian @ 2016-10-25 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477398945-22774-1-git-send-email-Minghuan.Lian@nxp.com>
1. Change compatible to "fsl,ls-scfg-msi"
2. Move three MSI dts node into the parent node "msi-controller".
So a PCIe device can request the MSI from the three MSI controllers.
3. The rev1.1 of LS1043a moves PCIe INTB/C/D interrupts to MSI controller.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 64 +++++++++++++-------------
1 file changed, 33 insertions(+), 31 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 41e5dc1..5295bb9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -587,25 +587,36 @@
dma-coherent;
};
- msi1: msi-controller1 at 1571000 {
- compatible = "fsl,1s1043a-msi";
- reg = <0x0 0x1571000 0x0 0x8>;
+ msi: msi-controller {
+ compatible = "fsl,ls-scfg-msi";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
msi-controller;
- interrupts = <0 116 0x4>;
- };
- msi2: msi-controller2 at 1572000 {
- compatible = "fsl,1s1043a-msi";
- reg = <0x0 0x1572000 0x0 0x8>;
- msi-controller;
- interrupts = <0 126 0x4>;
- };
+ msi0 at 1571000 {
+ reg = <0x0 0x1571000 0x0 0x1000>;
+ interrupts = <0 116 0x4>,
+ <0 111 0x4>,
+ <0 112 0x4>,
+ <0 113 0x4>;
+ };
- msi3: msi-controller3 at 1573000 {
- compatible = "fsl,1s1043a-msi";
- reg = <0x0 0x1573000 0x0 0x8>;
- msi-controller;
- interrupts = <0 160 0x4>;
+ msi1 at 1572000 {
+ reg = <0x0 0x1572000 0x0 0x1000>;
+ interrupts = <0 126 0x4>,
+ <0 121 0x4>,
+ <0 122 0x4>,
+ <0 123 0x4>;
+ };
+
+ msi2 at 1573000 {
+ reg = <0x0 0x1573000 0x0 0x1000>;
+ interrupts = <0 160 0x4>,
+ <0 155 0x4>,
+ <0 156 0x4>,
+ <0 157 0x4>;
+ };
};
pcie at 3400000 {
@@ -624,13 +635,10 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi1>;
+ msi-parent = <&msi>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
- <0000 0 0 2 &gic 0 111 0x4>,
- <0000 0 0 3 &gic 0 112 0x4>,
- <0000 0 0 4 &gic 0 113 0x4>;
+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>;
};
pcie at 3500000 {
@@ -649,13 +657,10 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi2>;
+ msi-parent = <&msi>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
- <0000 0 0 2 &gic 0 121 0x4>,
- <0000 0 0 3 &gic 0 122 0x4>,
- <0000 0 0 4 &gic 0 123 0x4>;
+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>;
};
pcie at 3600000 {
@@ -674,13 +679,10 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&msi3>;
+ msi-parent = <&msi>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
- <0000 0 0 2 &gic 0 155 0x4>,
- <0000 0 0 3 &gic 0 156 0x4>,
- <0000 0 0 4 &gic 0 157 0x4>;
+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>;
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH 4/6] arm64: dts: ls1046a: add MSI dts node
From: Minghuan Lian @ 2016-10-25 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477398945-22774-1-git-send-email-Minghuan.Lian@nxp.com>
LS1046a has three MSI controllers. each controller is assigned
four SPI interrupts.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 32 ++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..5509dca 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -511,5 +511,37 @@
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
+
+ msi: msi-controller {
+ compatible = "fsl,ls-scfg-msi";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ msi-controller;
+
+ msi0 at 1580000 {
+ reg = <0x0 0x1580000 0x0 0x10000>;
+ interrupts = <0 116 0x4>,
+ <0 111 0x4>,
+ <0 112 0x4>,
+ <0 113 0x4>;
+ };
+
+ msi1 at 1590000 {
+ reg = <0x0 0x1590000 0x0 0x10000>;
+ interrupts = <0 126 0x4>,
+ <0 121 0x4>,
+ <0 122 0x4>,
+ <0 123 0x4>;
+ };
+
+ msi2 at 15a0000 {
+ reg = <0x0 0x15a0000 0x0 0x10000>;
+ interrupts = <0 160 0x4>,
+ <0 155 0x4>,
+ <0 156 0x4>,
+ <0 157 0x4>;
+ };
+ };
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH 5/6] arm64: dts: ls1043a: update gic dts node
From: Minghuan Lian @ 2016-10-25 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477398945-22774-1-git-send-email-Minghuan.Lian@nxp.com>
From: Gong Qianyu <Qianyu.Gong@nxp.com>
In order to support kvm, rev1.1 LS1043a GIC register has been
changed to align as 64K. The patch updates GIC node according to
the rev1.1 hardware.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 5295bb9..da1809d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -144,10 +144,10 @@
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x0 0x1401000 0 0x1000>, /* GICD */
- <0x0 0x1402000 0 0x2000>, /* GICC */
- <0x0 0x1404000 0 0x2000>, /* GICH */
- <0x0 0x1406000 0 0x2000>; /* GICV */
+ reg = <0x0 0x1410000 0 0x10000>, /* GICD */
+ <0x0 0x1420000 0 0x20000>, /* GICC */
+ <0x0 0x1440000 0 0x20000>, /* GICH */
+ <0x0 0x1460000 0 0x20000>; /* GICV */
interrupts = <1 9 0xf08>;
};
--
1.9.1
^ permalink raw reply related
* [PATCH 6/6] arm64: dts: ls1046a: add PCIe dts node
From: Minghuan Lian @ 2016-10-25 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477398945-22774-1-git-send-email-Minghuan.Lian@nxp.com>
LS1046a has three PCIe controllers.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 66 ++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 5509dca..427cba4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -543,5 +543,71 @@
<0 157 0x4>;
};
};
+
+ pcie at 3400000 {
+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 118 0x4>, /* controller interrupt */
+ <0 117 0x4>; /* PME interrupt */
+ interrupt-names = "aer", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>;
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 128 0x4>,
+ <0 127 0x4>;
+ interrupt-names = "aer", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>;
+ };
+
+ pcie at 3600000 {
+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 162 0x4>,
+ <0 161 0x4>;
+ interrupt-names = "aer", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>;
+ };
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH] pci: layerscape: add LS1046a support
From: Minghuan Lian @ 2016-10-25 12:36 UTC (permalink / raw)
To: linux-arm-kernel
From: "mingkai.hu@nxp.com" <mingkai.hu@nxp.com>
1. LS1046a PCIe controller has a different LUT_DBG offset.
Available "lut_dbg" is added to ls_pcie_drvdata to describe
this difference.
2. Match LS1046 PCIe compatible
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
drivers/pci/host/pci-layerscape.c | 13 ++++++++++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..ee1c72d5 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -15,6 +15,7 @@ Required properties:
- compatible: should contain the platform identifier such as:
"fsl,ls1021a-pcie", "snps,dw-pcie"
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
+ "fsl,ls1046a-pcie"
- reg: base addresses and lengths of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
index 958187f..8cebf9a 100644
--- a/drivers/pci/host/pci-layerscape.c
+++ b/drivers/pci/host/pci-layerscape.c
@@ -41,6 +41,7 @@
struct ls_pcie_drvdata {
u32 lut_offset;
u32 ltssm_shift;
+ u32 lut_dbg;
struct pcie_host_ops *ops;
};
@@ -134,7 +135,7 @@ static int ls_pcie_link_up(struct pcie_port *pp)
struct ls_pcie *pcie = to_ls_pcie(pp);
u32 state;
- state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
+ state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
pcie->drvdata->ltssm_shift) &
LTSSM_STATE_MASK;
@@ -196,18 +197,28 @@ static int ls_pcie_msi_host_init(struct pcie_port *pp,
static struct ls_pcie_drvdata ls1043_drvdata = {
.lut_offset = 0x10000,
.ltssm_shift = 24,
+ .lut_dbg = 0x7fc,
+ .ops = &ls_pcie_host_ops,
+};
+
+static struct ls_pcie_drvdata ls1046_drvdata = {
+ .lut_offset = 0x80000,
+ .ltssm_shift = 24,
+ .lut_dbg = 0x407fc,
.ops = &ls_pcie_host_ops,
};
static struct ls_pcie_drvdata ls2080_drvdata = {
.lut_offset = 0x80000,
.ltssm_shift = 0,
+ .lut_dbg = 0x7fc,
.ops = &ls_pcie_host_ops,
};
static const struct of_device_id ls_pcie_of_match[] = {
{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
+ { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
{ },
--
1.9.1
^ permalink raw reply related
* [PATCH] irqchip/ls-scfg-msi: update Layerscape SCFG MSI driver
From: Minghuan Lian @ 2016-10-25 12:39 UTC (permalink / raw)
To: linux-arm-kernel
1. The patch uses soc_device_match() to match the SoC family
and revision instead of DTS compatible, because compatible cannot
describe the SoC revision information.
2. The patch provides a new method to support Layerscape
SCFG MSI. It tries to assign a dedicated MSIR to every core.
When changing a MSI interrupt affinity, the MSI message
data will be changed to refer to a new MSIR that has
been associated with the core.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
The patch depends on https://patchwork.kernel.org/patch/9342915/
drivers/irqchip/irq-ls-scfg-msi.c | 444 +++++++++++++++++++++++++++++++-------
1 file changed, 367 insertions(+), 77 deletions(-)
diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
index 02cca74c..0245d8a 100644
--- a/drivers/irqchip/irq-ls-scfg-msi.c
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
@@ -10,6 +10,7 @@
* published by the Free Software Foundation.
*/
+#include <linux/bitmap.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/msi.h>
@@ -17,23 +18,91 @@
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/spinlock.h>
+#include <linux/sys_soc.h>
-#define MSI_MAX_IRQS 32
-#define MSI_IBS_SHIFT 3
-#define MSIR 4
+#define LS_MSIR_NUM_MAX 4 /* MSIIR can index 4 MSI registers */
+#define IRQS_32_PER_MSIR 32
+#define IRQS_8_PER_MSIR 8
+
+#define MSIR_OFFSET(idx) ((idx) * 0x4)
+
+enum msi_affinity_flag {
+ MSI_GROUP_AFFINITY_FLAG,
+ MSI_AFFINITY_FLAG
+};
+
+struct ls_scfg_msi;
+struct ls_scfg_msi_ctrl;
+
+struct ls_scfg_msi_cfg {
+ u32 ibs_shift; /* Shift of interrupt bit select */
+ u32 msir_irqs; /* The irq number per MSIR */
+ u32 msir_base; /* The base address of MSIR */
+};
+
+struct ls_scfg_msir {
+ struct ls_scfg_msi_ctrl *ctrl;
+ void __iomem *addr;
+ int index;
+ int virq;
+};
+
+struct ls_scfg_msi_ctrl {
+ struct list_head list;
+ struct ls_scfg_msi *msi_data;
+ void __iomem *regs;
+ phys_addr_t msiir_addr;
+ enum msi_affinity_flag flag;
+ int irq_base;
+ spinlock_t lock;
+ struct ls_scfg_msir *msir;
+ unsigned long *bm;
+};
struct ls_scfg_msi {
- spinlock_t lock;
- struct platform_device *pdev;
- struct irq_domain *parent;
- struct irq_domain *msi_domain;
- void __iomem *regs;
- phys_addr_t msiir_addr;
- int irq;
- DECLARE_BITMAP(used, MSI_MAX_IRQS);
+ struct platform_device *pdev;
+ struct irq_domain *parent;
+ struct irq_domain *msi_domain;
+ struct list_head ctrl_list;
+ const struct ls_scfg_msi_cfg *cfg;
+ u32 cpu_num;
+};
+
+static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
+ .ibs_shift = 3,
+ .msir_irqs = IRQS_32_PER_MSIR,
+ .msir_base = 0x4,
+};
+
+static struct ls_scfg_msi_cfg ls1043_rev11_msi_cfg = {
+ .ibs_shift = 2,
+ .msir_irqs = IRQS_8_PER_MSIR,
+ .msir_base = 0x10,
+};
+
+static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
+ .ibs_shift = 2,
+ .msir_irqs = IRQS_32_PER_MSIR,
+ .msir_base = 0x4,
+};
+
+static struct soc_device_attribute soc_msi_matches[] = {
+ { .family = "QorIQ LS1021A",
+ .data = &ls1021_msi_cfg },
+ { .family = "QorIQ LS1012A",
+ .data = &ls1021_msi_cfg },
+ { .family = "QorIQ LS1043A", .revision = "1.0",
+ .data = &ls1021_msi_cfg },
+ { .family = "QorIQ LS1043A", .revision = "1.1",
+ .data = &ls1043_rev11_msi_cfg },
+ { .family = "QorIQ LS1046A",
+ .data = &ls1046_msi_cfg },
+ { },
};
static struct irq_chip ls_scfg_msi_irq_chip = {
@@ -49,19 +118,53 @@ struct ls_scfg_msi {
.chip = &ls_scfg_msi_irq_chip,
};
+static int ctrl_num;
+
+static irqreturn_t (*ls_scfg_msi_irq_handler)(int irq, void *arg);
+
static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
- struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
+ struct ls_scfg_msi_ctrl *ctrl = irq_data_get_irq_chip_data(data);
+ u32 ibs, srs;
- msg->address_hi = upper_32_bits(msi_data->msiir_addr);
- msg->address_lo = lower_32_bits(msi_data->msiir_addr);
- msg->data = data->hwirq << MSI_IBS_SHIFT;
+ msg->address_hi = upper_32_bits(ctrl->msiir_addr);
+ msg->address_lo = lower_32_bits(ctrl->msiir_addr);
+
+ ibs = data->hwirq - ctrl->irq_base;
+
+ srs = cpumask_first(irq_data_get_affinity_mask(data));
+ if (srs >= ctrl->msi_data->cpu_num)
+ srs = 0;
+
+ msg->data = ibs << ctrl->msi_data->cfg->ibs_shift | srs;
+
+ pr_debug("%s: ibs %d srs %d address0x%x-0x%x data 0x%x\n",
+ __func__, ibs, srs, msg->address_hi,
+ msg->address_lo, msg->data);
}
-static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
- const struct cpumask *mask, bool force)
+static int ls_scfg_msi_set_affinity(struct irq_data *data,
+ const struct cpumask *mask, bool force)
{
- return -EINVAL;
+ struct ls_scfg_msi_ctrl *ctrl = irq_data_get_irq_chip_data(data);
+ u32 cpu;
+
+ if (!force)
+ cpu = cpumask_any_and(mask, cpu_online_mask);
+ else
+ cpu = cpumask_first(mask);
+
+ if (cpu >= ctrl->msi_data->cpu_num)
+ return -EINVAL;
+
+ if (ctrl->msir[cpu].virq <= 0) {
+ pr_warn("cannot bind the irq to cpu%d\n", cpu);
+ return -EINVAL;
+ }
+
+ cpumask_copy(irq_data_get_affinity_mask(data), mask);
+
+ return IRQ_SET_MASK_OK_NOCOPY;
}
static struct irq_chip ls_scfg_msi_parent_chip = {
@@ -76,44 +179,57 @@ static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
void *args)
{
struct ls_scfg_msi *msi_data = domain->host_data;
- int pos, err = 0;
+ static struct list_head *current_entry;
+ struct ls_scfg_msi_ctrl *ctrl;
+ int i, hwirq = -ENOMEM;
+
+ if (!current_entry || current_entry->next == &msi_data->ctrl_list)
+ current_entry = &msi_data->ctrl_list;
+
+ list_for_each_entry(ctrl, current_entry, list) {
+ spin_lock(&ctrl->lock);
+ hwirq = bitmap_find_free_region(ctrl->bm,
+ msi_data->cfg->msir_irqs,
+ order_base_2(nr_irqs));
+ spin_unlock(&ctrl->lock);
+
+ if (hwirq >= 0)
+ break;
+ }
- WARN_ON(nr_irqs != 1);
+ if (hwirq < 0)
+ return hwirq;
- spin_lock(&msi_data->lock);
- pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS);
- if (pos < MSI_MAX_IRQS)
- __set_bit(pos, msi_data->used);
- else
- err = -ENOSPC;
- spin_unlock(&msi_data->lock);
+ hwirq = hwirq + ctrl->irq_base;
- if (err)
- return err;
+ for (i = 0; i < nr_irqs; i++)
+ irq_domain_set_info(domain, virq + i, hwirq + i,
+ &ls_scfg_msi_parent_chip, ctrl,
+ handle_simple_irq, NULL, NULL);
- irq_domain_set_info(domain, virq, pos,
- &ls_scfg_msi_parent_chip, msi_data,
- handle_simple_irq, NULL, NULL);
+ current_entry = &ctrl->list;
return 0;
}
static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
- unsigned int virq, unsigned int nr_irqs)
+ unsigned int virq,
+ unsigned int nr_irqs)
{
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
- struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(d);
+ struct ls_scfg_msi_ctrl *ctrl = irq_data_get_irq_chip_data(d);
int pos;
- pos = d->hwirq;
- if (pos < 0 || pos >= MSI_MAX_IRQS) {
- pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
+ pos = d->hwirq - ctrl->irq_base;
+
+ if (pos < 0 || pos >= ctrl->msi_data->cfg->msir_irqs) {
+ pr_err("Failed to teardown msi. Invalid hwirq %d\n", pos);
return;
}
- spin_lock(&msi_data->lock);
- __clear_bit(pos, msi_data->used);
- spin_unlock(&msi_data->lock);
+ spin_lock(&ctrl->lock);
+ bitmap_release_region(ctrl->bm, pos, order_base_2(nr_irqs));
+ spin_unlock(&ctrl->lock);
}
static const struct irq_domain_ops ls_scfg_msi_domain_ops = {
@@ -121,29 +237,198 @@ static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
.free = ls_scfg_msi_domain_irq_free,
};
-static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
+static irqreturn_t ls_scfg_msi_irqs32_handler(int irq, void *arg)
{
- struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc);
+ struct ls_scfg_msir *msir = arg;
+ struct ls_scfg_msi_ctrl *ctrl = msir->ctrl;
+ struct ls_scfg_msi *msi_data = ctrl->msi_data;
unsigned long val;
- int pos, virq;
+ int pos = 0, hwirq, virq;
+ irqreturn_t ret = IRQ_NONE;
- chained_irq_enter(irq_desc_get_chip(desc), desc);
+ val = ioread32be(msir->addr);
- val = ioread32be(msi_data->regs + MSIR);
- for_each_set_bit(pos, &val, MSI_MAX_IRQS) {
- virq = irq_find_mapping(msi_data->parent, (31 - pos));
- if (virq)
+ for_each_set_bit(pos, &val, IRQS_32_PER_MSIR) {
+ hwirq = (IRQS_32_PER_MSIR - 1 - pos) + ctrl->irq_base;
+ virq = irq_find_mapping(msi_data->parent, hwirq);
+ if (virq) {
generic_handle_irq(virq);
+ ret = IRQ_HANDLED;
+ }
+ }
+
+ return ret;
+}
+
+static irqreturn_t ls_scfg_msi_irqs8_handler(int irq, void *arg)
+{
+ struct ls_scfg_msir *msir = arg;
+ struct ls_scfg_msi_ctrl *ctrl = msir->ctrl;
+ struct ls_scfg_msi *msi_data = ctrl->msi_data;
+ unsigned long val;
+ int pos = 0, hwirq, virq;
+ irqreturn_t ret = IRQ_NONE;
+
+ val = ioread32be(msir->addr);
+ val = (val << (msir->index * 8)) & 0xff000000;
+
+ for_each_set_bit(pos, &val, IRQS_32_PER_MSIR) {
+ hwirq = (IRQS_32_PER_MSIR - 1 - pos) + ctrl->irq_base;
+ virq = irq_find_mapping(msi_data->parent, hwirq);
+ if (virq) {
+ generic_handle_irq(virq);
+ ret = IRQ_HANDLED;
+ }
+ }
+
+ return ret;
+}
+
+static void ls_scfg_msi_cascade(struct irq_desc *desc)
+{
+ struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ chained_irq_enter(chip, desc);
+ ls_scfg_msi_irq_handler(desc->irq_data.irq, msir);
+ chained_irq_exit(chip, desc);
+}
+
+static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi_ctrl *ctrl,
+ struct device_node *node,
+ int index)
+{
+ struct ls_scfg_msir *msir = &ctrl->msir[index];
+ int ret;
+
+ msir->virq = of_irq_get(node, index);
+ if (msir->virq <= 0)
+ return -ENODEV;
+
+ msir->index = index;
+ msir->ctrl = ctrl;
+ msir->addr = ctrl->regs + ctrl->msi_data->cfg->msir_base +
+ MSIR_OFFSET(msir->index);
+
+ if (ctrl->flag == MSI_GROUP_AFFINITY_FLAG) {
+ ret = request_irq(msir->virq, ls_scfg_msi_irq_handler,
+ IRQF_NO_THREAD, "MSI-GROUP", msir);
+ if (ret) {
+ pr_err("failed to request irq %d\n", msir->virq);
+ msir->virq = 0;
+ return -ENODEV;
+ }
+ } else {
+ irq_set_chained_handler(msir->virq, ls_scfg_msi_cascade);
+ irq_set_handler_data(msir->virq, msir);
+ irq_set_affinity(msir->virq, get_cpu_mask(index));
+ }
+
+ return 0;
+}
+
+static void ls_scfg_msi_ctrl_remove(struct ls_scfg_msi_ctrl *ctrl)
+{
+ struct ls_scfg_msir *msir;
+ int i;
+
+ if (!ctrl)
+ return;
+
+ if (ctrl->msir) {
+ for (i = 0; i < ctrl->msi_data->cpu_num; i++) {
+ msir = &ctrl->msir[i];
+
+ if (msir->virq <= 0)
+ continue;
+
+ if (ctrl->flag == MSI_GROUP_AFFINITY_FLAG)
+ free_irq(msir->virq, msir);
+ else
+ irq_set_chained_handler_and_data(msir->virq,
+ NULL, NULL);
+ }
+
+ kfree(ctrl->msir);
}
- chained_irq_exit(irq_desc_get_chip(desc), desc);
+ if (ctrl->regs)
+ iounmap(ctrl->regs);
+
+ kfree(ctrl->bm);
+ kfree(ctrl);
+}
+
+static int ls_scfg_msi_ctrl_probe(struct device_node *node,
+ struct ls_scfg_msi *msi_data)
+{
+ struct ls_scfg_msi_ctrl *ctrl;
+ struct resource res;
+ int err, irqs, i;
+
+ err = of_address_to_resource(node, 0, &res);
+ if (err) {
+ pr_warn("%s: no regs\n", node->full_name);
+ return -ENXIO;
+ }
+
+ ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
+ if (!ctrl)
+ return -ENOMEM;
+
+ ctrl->msi_data = msi_data;
+ ctrl->msiir_addr = res.start;
+ spin_lock_init(&ctrl->lock);
+
+ ctrl->regs = ioremap(res.start, resource_size(&res));
+ if (!ctrl->regs) {
+ pr_err("%s: unable to map registers\n", node->full_name);
+ err = -ENOMEM;
+ goto _err;
+ }
+
+ ctrl->msir = kcalloc(msi_data->cpu_num, sizeof(struct ls_scfg_msir),
+ GFP_KERNEL);
+ if (!ctrl->msir) {
+ err = -ENOMEM;
+ goto _err;
+ }
+
+ ctrl->bm = kcalloc(BITS_TO_LONGS(msi_data->cfg->msir_irqs),
+ sizeof(long), GFP_KERNEL);
+ if (!ctrl->bm) {
+ err = -ENOMEM;
+ goto _err;
+ }
+
+ ctrl->irq_base = msi_data->cfg->msir_irqs * ctrl_num;
+ ctrl_num++;
+
+ irqs = of_irq_count(node);
+ if (irqs >= msi_data->cpu_num)
+ ctrl->flag = MSI_AFFINITY_FLAG;
+ else
+ ctrl->flag = MSI_GROUP_AFFINITY_FLAG;
+
+ for (i = 0; i < msi_data->cpu_num; i++)
+ ls_scfg_msi_setup_hwirq(ctrl, node, i);
+
+ list_add_tail(&ctrl->list, &msi_data->ctrl_list);
+
+ return 0;
+
+_err:
+ ls_scfg_msi_ctrl_remove(ctrl);
+ pr_err("MSI: failed probing %s (%d)\n", node->full_name, err);
+ return err;
}
static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
{
/* Initialize MSI domain parent */
msi_data->parent = irq_domain_add_linear(NULL,
- MSI_MAX_IRQS,
+ msi_data->cfg->msir_irqs *
+ ctrl_num,
&ls_scfg_msi_domain_ops,
msi_data);
if (!msi_data->parent) {
@@ -167,51 +452,57 @@ static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
static int ls_scfg_msi_probe(struct platform_device *pdev)
{
struct ls_scfg_msi *msi_data;
- struct resource *res;
- int ret;
+ const struct soc_device_attribute *match;
+ struct device_node *child;
msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
if (!msi_data)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(msi_data->regs)) {
- dev_err(&pdev->dev, "failed to initialize 'regs'\n");
- return PTR_ERR(msi_data->regs);
- }
- msi_data->msiir_addr = res->start;
-
- msi_data->irq = platform_get_irq(pdev, 0);
- if (msi_data->irq <= 0) {
- dev_err(&pdev->dev, "failed to get MSI irq\n");
- return -ENODEV;
- }
+ INIT_LIST_HEAD(&msi_data->ctrl_list);
msi_data->pdev = pdev;
- spin_lock_init(&msi_data->lock);
+ msi_data->cpu_num = num_possible_cpus();
+
+ match = soc_device_match(soc_msi_matches);
+ if (match)
+ msi_data->cfg = match->data;
+ else
+ msi_data->cfg = &ls1046_msi_cfg;
+
+ if (msi_data->cfg->msir_irqs == IRQS_8_PER_MSIR)
+ ls_scfg_msi_irq_handler = ls_scfg_msi_irqs8_handler;
+ else
+ ls_scfg_msi_irq_handler = ls_scfg_msi_irqs32_handler;
- ret = ls_scfg_msi_domains_init(msi_data);
- if (ret)
- return ret;
+ for_each_child_of_node(msi_data->pdev->dev.of_node, child)
+ ls_scfg_msi_ctrl_probe(child, msi_data);
- irq_set_chained_handler_and_data(msi_data->irq,
- ls_scfg_msi_irq_handler,
- msi_data);
+ ls_scfg_msi_domains_init(msi_data);
platform_set_drvdata(pdev, msi_data);
+ dev_info(&pdev->dev, "irqs:%dx%d ibs_shift:%d msir_base:0x%x\n",
+ msi_data->cfg->msir_irqs, ctrl_num,
+ msi_data->cfg->ibs_shift, msi_data->cfg->msir_base);
+
return 0;
}
static int ls_scfg_msi_remove(struct platform_device *pdev)
{
struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
+ struct ls_scfg_msi_ctrl *ctrl, *temp;
- irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL);
+ list_for_each_entry_safe(ctrl, temp, &msi_data->ctrl_list, list) {
+ list_move_tail(&ctrl->list, &msi_data->ctrl_list);
+ ls_scfg_msi_ctrl_remove(ctrl);
+ }
- irq_domain_remove(msi_data->msi_domain);
- irq_domain_remove(msi_data->parent);
+ if (msi_data->msi_domain)
+ irq_domain_remove(msi_data->msi_domain);
+ if (msi_data->parent)
+ irq_domain_remove(msi_data->parent);
platform_set_drvdata(pdev, NULL);
@@ -219,8 +510,7 @@ static int ls_scfg_msi_remove(struct platform_device *pdev)
}
static const struct of_device_id ls_scfg_msi_id[] = {
- { .compatible = "fsl,1s1021a-msi", },
- { .compatible = "fsl,1s1043a-msi", },
+ { .compatible = "fsl,ls-scfg-msi" },
{},
};
--
1.9.1
^ permalink raw reply related
* [PATCH] asm-generic: Drop getrlimit and setrlimit syscalls from default list
From: Stafford Horne @ 2016-10-25 12:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFiDJ59PdOiqiF8wFVFrkB4k0B6S5cTGVQPUpdjZ=83iv7GQag@mail.gmail.com>
On Tue, 25 Oct 2016, Ley Foon Tan wrote:
> On Mon, Oct 24, 2016 at 5:09 PM, James Hogan <james.hogan@imgtec.com> wrote:
>> On Sat, Oct 22, 2016 at 03:14:04PM +0300, Yury Norov wrote:
>>> The newer prlimit64 syscall provides all the functionality provided by
>>> the getrlimit and setrlimit syscalls and adds the pid of target process,
>>> so future architectures won't need to include getrlimit and setrlimit.
>>>
>>> Therefore drop getrlimit and setrlimit syscalls from the generic syscall
>>> list unless __ARCH_WANT_SET_GET_RLIMIT is defined by the architecture's
>>> unistd.h prior to including asm-generic/unistd.h, and adjust all
>>> architectures using the generic syscall list to define it so that no
>>> in-tree architectures are affected.
>>>
>>> Cc: Vineet Gupta <vgupta@synopsys.com>
>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>> Cc: Will Deacon <will.deacon@arm.com>
>>> Cc: Mark Salter <msalter@redhat.com>
>>> Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
>>> Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
>>> Cc: Richard Kuo <rkuo@codeaurora.org>
>>> Cc: James Hogan <james.hogan@imgtec.com>
>>> Cc: Ley Foon Tan <lftan@altera.com>
>>> Cc: Jonas Bonn <jonas@southpole.se>
>>> Cc: Chen Liqin <liqin.linux@gmail.com>
>>> Cc: Lennox Wu <lennox.wu@gmail.com>
>>> Cc: Chris Metcalf <cmetcalf@mellanox.com>
>>> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Cc: Andrew Pinski <Andrew.Pinski@cavium.com>
>>> Cc: linux-snps-arc at lists.infradead.org
>>> Cc: linux-kernel at vger.kernel.org
>>> Cc: linux-arm-kernel at lists.infradead.org
>>> Cc: linux-c6x-dev at linux-c6x.org
>>> Cc: uclinux-h8-devel at lists.sourceforge.jp
>>> Cc: linux-hexagon at vger.kernel.org
>>> Cc: linux-metag at vger.kernel.org
>>> Cc: nios2-dev at lists.rocketboards.org
>>> Cc: linux-arch at vger.kernel.or
>>> Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
>>>
>>> ---
>>> arch/arc/include/uapi/asm/unistd.h | 1 +
>>> arch/arm64/include/uapi/asm/unistd.h | 1 +
>>> arch/c6x/include/uapi/asm/unistd.h | 1 +
>>> arch/h8300/include/uapi/asm/unistd.h | 1 +
>>> arch/hexagon/include/uapi/asm/unistd.h | 1 +
>>> arch/metag/include/uapi/asm/unistd.h | 1 +
>>
>> Acked-by: James Hogan <james.hogan@imgtec.com> [metag]
>>
>> Cheers
>> James
>>
>>> arch/nios2/include/uapi/asm/unistd.h | 1 +
> Acked-by: Ley Foon Tan <lftan@altera.com> [nios2]
>
>
>>> arch/openrisc/include/uapi/asm/unistd.h | 1 +
Acked-by: Stafford Horne <shorne@gmail.com> [openrisc]
>>> arch/score/include/uapi/asm/unistd.h | 1 +
>>> arch/tile/include/uapi/asm/unistd.h | 1 +
>>> arch/unicore32/include/uapi/asm/unistd.h | 1 +
>>> include/uapi/asm-generic/unistd.h | 5 +++++
>>> 12 files changed, 16 insertions(+)
>>>
>>> diff --git a/arch/arc/include/uapi/asm/unistd.h b/arch/arc/include/uapi/asm/unistd.h
>>> index 41fa2ec..928546d 100644
>>> --- a/arch/arc/include/uapi/asm/unistd.h
>>> +++ b/arch/arc/include/uapi/asm/unistd.h
>>> @@ -16,6 +16,7 @@
>>> #define _UAPI_ASM_ARC_UNISTD_H
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>> #define __ARCH_WANT_SYS_EXECVE
>>> #define __ARCH_WANT_SYS_CLONE
>>> #define __ARCH_WANT_SYS_VFORK
>>> diff --git a/arch/arm64/include/uapi/asm/unistd.h b/arch/arm64/include/uapi/asm/unistd.h
>>> index 043d17a..48355a6 100644
>>> --- a/arch/arm64/include/uapi/asm/unistd.h
>>> +++ b/arch/arm64/include/uapi/asm/unistd.h
>>> @@ -15,5 +15,6 @@
>>> */
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>>
>>> #include <asm-generic/unistd.h>
>>> diff --git a/arch/c6x/include/uapi/asm/unistd.h b/arch/c6x/include/uapi/asm/unistd.h
>>> index 12d73d9..f676231 100644
>>> --- a/arch/c6x/include/uapi/asm/unistd.h
>>> +++ b/arch/c6x/include/uapi/asm/unistd.h
>>> @@ -15,6 +15,7 @@
>>> */
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>> #define __ARCH_WANT_SYS_CLONE
>>>
>>> /* Use the standard ABI for syscalls. */
>>> diff --git a/arch/h8300/include/uapi/asm/unistd.h b/arch/h8300/include/uapi/asm/unistd.h
>>> index 7dd20ef..2f98394 100644
>>> --- a/arch/h8300/include/uapi/asm/unistd.h
>>> +++ b/arch/h8300/include/uapi/asm/unistd.h
>>> @@ -1,5 +1,6 @@
>>> #define __ARCH_NOMMU
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>>
>>> #include <asm-generic/unistd.h>
>>> diff --git a/arch/hexagon/include/uapi/asm/unistd.h b/arch/hexagon/include/uapi/asm/unistd.h
>>> index 2151760..52d585c 100644
>>> --- a/arch/hexagon/include/uapi/asm/unistd.h
>>> +++ b/arch/hexagon/include/uapi/asm/unistd.h
>>> @@ -28,6 +28,7 @@
>>>
>>> #define sys_mmap2 sys_mmap_pgoff
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>> #define __ARCH_WANT_SYS_EXECVE
>>> #define __ARCH_WANT_SYS_CLONE
>>> #define __ARCH_WANT_SYS_VFORK
>>> diff --git a/arch/metag/include/uapi/asm/unistd.h b/arch/metag/include/uapi/asm/unistd.h
>>> index 459b6ec..16b5cb3 100644
>>> --- a/arch/metag/include/uapi/asm/unistd.h
>>> +++ b/arch/metag/include/uapi/asm/unistd.h
>>> @@ -8,6 +8,7 @@
>>> */
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>>
>>> /* Use the standard ABI for syscalls. */
>>> #include <asm-generic/unistd.h>
>>> diff --git a/arch/nios2/include/uapi/asm/unistd.h b/arch/nios2/include/uapi/asm/unistd.h
>>> index 51a32c7..b0dda4d 100644
>>> --- a/arch/nios2/include/uapi/asm/unistd.h
>>> +++ b/arch/nios2/include/uapi/asm/unistd.h
>>> @@ -18,6 +18,7 @@
>>> #define sys_mmap2 sys_mmap_pgoff
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>>
>>> /* Use the standard ABI for syscalls */
>>> #include <asm-generic/unistd.h>
>>> diff --git a/arch/openrisc/include/uapi/asm/unistd.h b/arch/openrisc/include/uapi/asm/unistd.h
>>> index 471905b..6812d81 100644
>>> --- a/arch/openrisc/include/uapi/asm/unistd.h
>>> +++ b/arch/openrisc/include/uapi/asm/unistd.h
>>> @@ -21,6 +21,7 @@
>>> #define sys_mmap2 sys_mmap_pgoff
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>> #define __ARCH_WANT_SYS_FORK
>>> #define __ARCH_WANT_SYS_CLONE
>>>
>>> diff --git a/arch/score/include/uapi/asm/unistd.h b/arch/score/include/uapi/asm/unistd.h
>>> index d4008c3..7ad1bdc 100644
>>> --- a/arch/score/include/uapi/asm/unistd.h
>>> +++ b/arch/score/include/uapi/asm/unistd.h
>>> @@ -1,6 +1,7 @@
>>> #define __ARCH_HAVE_MMU
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>> #define __ARCH_WANT_SYSCALL_NO_AT
>>> #define __ARCH_WANT_SYSCALL_NO_FLAGS
>>> #define __ARCH_WANT_SYSCALL_OFF_T
>>> diff --git a/arch/tile/include/uapi/asm/unistd.h b/arch/tile/include/uapi/asm/unistd.h
>>> index 24e9187..cf0505f 100644
>>> --- a/arch/tile/include/uapi/asm/unistd.h
>>> +++ b/arch/tile/include/uapi/asm/unistd.h
>>> @@ -13,6 +13,7 @@
>>> */
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>> #if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
>>> /* Use the flavor of this syscall that matches the 32-bit API better. */
>>> #define __ARCH_WANT_SYNC_FILE_RANGE2
>>> diff --git a/arch/unicore32/include/uapi/asm/unistd.h b/arch/unicore32/include/uapi/asm/unistd.h
>>> index 1f63c47..ef25aec 100644
>>> --- a/arch/unicore32/include/uapi/asm/unistd.h
>>> +++ b/arch/unicore32/include/uapi/asm/unistd.h
>>> @@ -11,6 +11,7 @@
>>> */
>>>
>>> #define __ARCH_WANT_RENAMEAT
>>> +#define __ARCH_WANT_SET_GET_RLIMIT
>>>
>>> /* Use the standard ABI for syscalls. */
>>> #include <asm-generic/unistd.h>
>>> diff --git a/include/uapi/asm-generic/unistd.h b/include/uapi/asm-generic/unistd.h
>>> index 9b1462e..bbaeac0 100644
>>> --- a/include/uapi/asm-generic/unistd.h
>>> +++ b/include/uapi/asm-generic/unistd.h
>>> @@ -465,10 +465,15 @@ __SYSCALL(__NR_uname, sys_newuname)
>>> __SYSCALL(__NR_sethostname, sys_sethostname)
>>> #define __NR_setdomainname 162
>>> __SYSCALL(__NR_setdomainname, sys_setdomainname)
>>> +
>>> +#ifdef __ARCH_WANT_SET_GET_RLIMIT
>>> +/* getrlimit and setrlimit are superseded with prlimit64 */
>>> #define __NR_getrlimit 163
>>> __SC_COMP(__NR_getrlimit, sys_getrlimit, compat_sys_getrlimit)
>>> #define __NR_setrlimit 164
>>> __SC_COMP(__NR_setrlimit, sys_setrlimit, compat_sys_setrlimit)
>>> +#endif
>>> +
>>> #define __NR_getrusage 165
>>> __SC_COMP(__NR_getrusage, sys_getrusage, compat_sys_getrusage)
>>> #define __NR_umask 166
>>> --
>>> 2.7.4
>>>
>
^ permalink raw reply
* [PATCH/RFT v2 09/17] regulator: fixed: Add over current event
From: Axel Haslam @ 2016-10-25 12:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161024181937.GP17252@sirena.org.uk>
Hi Mark,
On Mon, Oct 24, 2016 at 8:19 PM, Mark Brown <broonie@kernel.org> wrote:
> On Mon, Oct 24, 2016 at 08:11:40PM +0200, Axel Haslam wrote:
>> On Mon, Oct 24, 2016 at 7:53 PM, Mark Brown <broonie@kernel.org> wrote:
>
>> > does it make sense to report this as a mode, we don't report other error
>> > conditions as modes but instead use REGULATOR_STATUS_ with the
>> > get_status() operation?
>
>> I used mode, because when the regulator toggles the overcurrent
>> line, it means that it has entered a current limited mode, at least the
>> regulator im looking at. ill change to STATUS
>
> That's not what regulator modes are - please look at the documentation
> for the defines here. They're about the quality of regulation.
To be able to use regulator to handle the overcurrent pin, i need to be able
to somehow retrieve the over current pin state from the regulator driver.
As i was trying your suggestion, i remembered why i thought i should use
mode instead of status: Status seems to be for internal regulator driver use,
there is no regulator_get_status, function and REGULATOR_STATUS_* are defined
in driver.h and not in consumer.h as REGULATOR_MODE_*
it seems that status is only used to print sysfs info.
Would you be ok if i allow consumers to get the status via a new
"regulator_get_status" call?
Regards
Axel.
^ permalink raw reply
* [PATCH 1/6] dt/bindings: adjust bindings for Layerscape SCFG MSI
From: Robin Murphy @ 2016-10-25 13:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477398945-22774-1-git-send-email-Minghuan.Lian@nxp.com>
On 25/10/16 13:35, Minghuan Lian wrote:
> 1. The different version of a SoC may have different MSI
> implementation. But compatible "fsl,<soc-name>-msi" can not describe
> the SoC version.
Can't it?
compatible = "fsl-ls1043a-rev11-msi";
Oh, I guess it can!
Joking aside, if there are multiple versions of a piece of hardware
which require *different* treatment by drivers, then it is obviously
wrong to use the same compatible string because *they are not compatible*.
> The MSI driver will use SoC match interface to get
> SoC type and version instead of compatible string. So all MSI node
> can use the common compatible "fsl,ls-scfg-msi" and the original
> compatible is unnecessary.
If there is some common level of functionality that *all* variants
support without the driver having to know which one is which, then there
might be some sense in having an additional common compatible to
represent that level of functionality, e.g.
compatible = "fsl-ls1043a-rev11-msi", "fsl,ls-scfg-msi";
But if, say, new variants turn out to have less functionality, rather
than more, then there's probably not much point, and we should stick to
specific, accurate, compatible strings.
DT is not specific to a kernel version, nor even to Linux. A string
which triggers some board-specific magic in a specific version of a
Linux driver does not describe the hardware.
Robin.
> 2. Layerscape SoCs may have one or several MSI controllers.
> In order to increase MSI interrupt number of a PCIe, the patch
> moves all MSI node into the parent node "msi-controller". So a
> PCIe can request MSI from all the MSI controllers.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> .../interrupt-controller/fsl,ls-scfg-msi.txt | 57 +++++++++++++++++++---
> 1 file changed, 49 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
> index 9e38949..29f95fd 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
> @@ -1,18 +1,28 @@
> * Freescale Layerscape SCFG PCIe MSI controller
>
> +Layerscape SoCs may have one or multiple MSI controllers.
> +Each MSI controller must be showed as a child node.
> +
> Required properties:
>
> -- compatible: should be "fsl,<soc-name>-msi" to identify
> - Layerscape PCIe MSI controller block such as:
> - "fsl,1s1021a-msi"
> - "fsl,1s1043a-msi"
> +- compatible: should be "fsl,ls-scfg-msi"
> +- #address-cells: must be 2
> +- #size-cells: must be 2
> +- ranges: allows valid 1:1 translation between child's address space and
> + parent's address space
> - msi-controller: indicates that this is a PCIe MSI controller node
> +
> +Required child node:
> +A child node must exist to represent the MSI controller.
> +The following are properties specific to those nodes:
> +
> - reg: physical base address of the controller and length of memory mapped.
> - interrupts: an interrupt to the parent interrupt controller.
>
> Optional properties:
> - interrupt-parent: the phandle to the parent interrupt controller.
>
> +Notes:
> This interrupt controller hardware is a second level interrupt controller that
> is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
> platforms. If interrupt-parent is not provided, the default parent interrupt
> @@ -22,9 +32,40 @@ MSI controller node
>
> Examples:
>
> - msi1: msi-controller at 1571000 {
> - compatible = "fsl,1s1043a-msi";
> - reg = <0x0 0x1571000 0x0 0x8>,
> + msi: msi-controller {
> + compatible = "fsl,ls-scfg-msi";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> msi-controller;
> - interrupts = <0 116 0x4>;
> +
> + msi0 at 1580000 {
> + reg = <0x0 0x1580000 0x0 0x10000>;
> + interrupts = <0 116 0x4>,
> + <0 111 0x4>,
> + <0 112 0x4>,
> + <0 113 0x4>;
> + };
> +
> + msi1 at 1590000 {
> + reg = <0x0 0x1590000 0x0 0x10000>;
> + interrupts = <0 126 0x4>,
> + <0 121 0x4>,
> + <0 122 0x4>,
> + <0 123 0x4>;
> + };
> +
> + msi2 at 15a0000 {
> + reg = <0x0 0x15a0000 0x0 0x10000>;
> + interrupts = <0 160 0x4>,
> + <0 155 0x4>,
> + <0 156 0x4>,
> + <0 157 0x4>;
> + };
> + };
> +
> + pcie at 3400000 {
> + ...
> + msi-parent = <&msi>;
> + ...
> };
>
^ permalink raw reply
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