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* [PATCH v2] irqchip/bcm2836: Prevent spurious interrupts
From: Thomas Gleixner @ 2016-10-31 18:16 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <8737jcs8mc.fsf@eliezer.anholt.net>

On Mon, 31 Oct 2016, Eric Anholt wrote:
> Thomas Gleixner <tglx@linutronix.de> writes:
> 
> > On Fri, 28 Oct 2016, Eric Anholt wrote:
> >
> >> Thomas Gleixner <tglx@linutronix.de> writes:
> >> > This is missing a fixes tag. I have no idea when that problem was
> >> > introduced, so I have no way to decide whether this needs to be tagged
> >> > stable or not.
> >> 
> >> This code has been there since introduction of the driver, so:
> >> 
> >> Fixes: 1a15aaa998dc ("irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2")
> >
> > So it want's a stable tag, right?
> 
> I'm not the author here, and I was just trying to provide an assist with
> upstreaming, so I'm not going to get too involved.  I'd say this is an
> edge case for being a stable tree candidate (it's produces a scary dmesg
> warning but no other functional problems that I know of), and I didn't
> add a fixes tag myself because of that.

A fixes tag is not the same as a stable tag, I really want to see Fixes
tags on patches which are bug fixes as it makes it simple to see the
context in which a bug was introduced.

vs. the stable tag: scary warnings tend to confuse users and cause people
to send bug reports. So in this case I'd add one.

Thanks,

	tglx

^ permalink raw reply

* [RESEND PATCH] arm: assabet_defconfig: disable IDE subsystem
From: Bartlomiej Zolnierkiewicz @ 2016-10-31 18:14 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161031154622.GB1041@n2100.armlinux.org.uk>


Hi,

On Monday, October 31, 2016 03:46:22 PM Russell King - ARM Linux wrote:
> On Wed, Oct 26, 2016 at 07:01:12PM +0200, Bartlomiej Zolnierkiewicz wrote:
> > 
> > Hi,
> > 
> > On Wednesday, July 13, 2016 04:37:31 PM Arnd Bergmann wrote:
> > > On Wednesday, July 13, 2016 12:59:23 PM CEST Bartlomiej Zolnierkiewicz wrote:
> > > > 
> > > > On Friday, July 08, 2016 10:23:48 PM Arnd Bergmann wrote:
> > > > > On Friday, July 8, 2016 5:24:41 PM CEST Bartlomiej Zolnierkiewicz wrote:
> > > > > > This patch disables deprecated IDE subsystem in assabet_defconfig
> > > > > > (no IDE host drivers are selected in this config so there is no
> > > > > > valid reason to enable IDE subsystem itself).
> > > > > > 
> > > > > > Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
> > > > > > Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> > > > > 
> > > > > I think the series makes a lot of sense. I have checked your assertions
> > > > > in the changelogs and found no flaws in your logic, so I think we should
> > > > > take them all through arm-soc unless there are other concerns.
> > > > 
> > > > Thank you.
> > > > 
> > > > Should I resend everything or just patches that were not reposted yet
> > > > (the ones that were marked as RFT initially and got no feedback)?
> > > 
> > > I'd be fine with just getting a pull request with all the patches that
> > > had no negative feedback and that were not already applied (if any).
> > 
> > Here it is (sorry for taking so long).
> 
> I've just been digging in the dmesg logs from when I was using the
> Assabet+Neponset as my firewall, and it was having to use the IDE
> ide-cs driver rather than the pata pcmcia driver.
> 
> I don't recall whether the pata pcmcia driver was a problem or not,
> as the PCMCIA interface can't cope with _any_ 32-bit accesses.  I
> think PATA tries to use the "highest" possible access size by
> default...

It doesn't actually - it defaults to 16-bits for PIO data access and
you must explicitly enable 32-bits using ATA_PFLAG_PIO32 port flag
(pata_pcmcia doesn't set it so it should be okay).  Also taskfile
registers are accessed using 8-bits access by default transport
functions (which are used by pata_pcmcia).

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

^ permalink raw reply

* [PATCH] ARM: BCM5301X: Add back handler ignoring external imprecise aborts
From: Scott Branden @ 2016-10-31 18:08 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161029111229.26875-1-zajec5@gmail.com>

Hi Rafal,


On 16-10-29 04:12 AM, Rafa? Mi?ecki wrote:
> From: Rafa? Mi?ecki <rafal@milecki.pl>
>
> Since early BCM5301X days we got abort handler that was removed by
> commit 937b12306ea79 ("ARM: BCM5301X: remove workaround imprecise abort
> fault handler"). It assumed we need to deal only with pending aborts
> left by the bootloader. Unfortunately this isn't true for BCM5301X.
>
> When probing PCI config space (device enumeration) it is expected to
> have master aborts on the PCI bus. Most bridges don't forward (or they
> allow disabling it) these errors onto the AXI/AMBA bus but not the
> Northstar (BCM5301X) one.
Should we only add this workaround code if CONFIG_PCI is on then?

>
> iProc PCIe controller on Northstar seems to be some older one, without
> a control register for errors forwarding. It means we need to workaround
> this at platform level. All newer platforms are not affected by this
> issue.
>
> Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
> ---
>  arch/arm/mach-bcm/bcm_5301x.c | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c
> index c8830a2..fe067f6 100644
> --- a/arch/arm/mach-bcm/bcm_5301x.c
> +++ b/arch/arm/mach-bcm/bcm_5301x.c
> @@ -9,14 +9,42 @@
>  #include <asm/hardware/cache-l2x0.h>
>
>  #include <asm/mach/arch.h>
> +#include <asm/siginfo.h>
> +#include <asm/signal.h>
> +
> +#define FSR_EXTERNAL		(1 << 12)
> +#define FSR_READ		(0 << 10)
> +#define FSR_IMPRECISE		0x0406
>
>  static const char *const bcm5301x_dt_compat[] __initconst = {
>  	"brcm,bcm4708",
>  	NULL,
>  };
>
> +static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
> +				  struct pt_regs *regs)
> +{
> +	/*
> +	 * We want to ignore aborts forwarded from the PCIe bus that are
> +	 * expected and shouldn't really be passed by the PCIe controller.
> +	 * The biggest disadvantage is the same FSR code may be reported when
> +	 * reading non-existing APB register and we shouldn't ignore that.
> +	 */
> +	if (fsr == (FSR_EXTERNAL | FSR_READ | FSR_IMPRECISE))
> +		return 0;
> +
> +	return 1;
> +}
> +
> +static void __init bcm5301x_init_early(void)
> +{
> +	hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
> +			"imprecise external abort");
> +}
> +
>  DT_MACHINE_START(BCM5301X, "BCM5301X")
>  	.l2c_aux_val	= 0,
>  	.l2c_aux_mask	= ~0,
>  	.dt_compat	= bcm5301x_dt_compat,
> +	.init_early	= bcm5301x_init_early,
>  MACHINE_END
>

Regards,
Scott

^ permalink raw reply

* [PATCH v14 1/4] clk: mediatek: Add MT2701 clock support
From: Stephen Boyd @ 2016-10-31 18:06 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477896558.5376.13.camel@mtksdaap41>

On 10/31, James Liao wrote:
> On Thu, 2016-10-27 at 18:17 -0700, Stephen Boyd wrote:
> > On 10/21, Erin Lo wrote:
> > > @@ -244,3 +256,31 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs,
> > >  			clk_data->clks[mc->id] = clk;
> > >  	}
> > >  }
> > > +
> > > +void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
> > > +			int num, void __iomem *base, spinlock_t *lock,
> > > +				struct clk_onecell_data *clk_data)
> > > +{
> > > +	struct clk *clk;
> > > +	int i;
> > > +
> > > +	for (i = 0; i <  num; i++) {
> > > +		const struct mtk_clk_divider *mcd = &mcds[i];
> > > +
> > > +		if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
> > 
> > NULL is a valid clk. IS_ERR_OR_NULL is usually wrong.
> 
> Why NULL is a valid clk?

Perhaps at some point we'll want to return a NULL pointer to
clk_get() callers so that they can handle things like optional
clocks easily without having any storage requirements. I don't
know if we'll ever do that, but that's just a possibility.

> 
> clk_data is designed for multiple initialization from different clock
> types, such as infra_clk_data in clk-mt2701.c. So it will ignore valid
> clocks to avoid duplicated clock registration. Here I assume a clock
> pointer with error code or NULL to be an invalid (not initialized)
> clock.
> 

Ok. Would it be possible to initialize the array with all error
pointers? That would make things less error prone, but it
probably doesn't matter at all anyway because this is done during
registration time. IS_ERR_OR_NULL makes me take a second look
each time, because it's usually wrong.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply

* [PATCH V2 2/2] ARM: dts: bcm283x: fix typo in mailbox address
From: Eric Anholt @ 2016-10-31 18:06 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477848139-32267-1-git-send-email-stefan.wahren@i2se.com>

Stefan Wahren <stefan.wahren@i2se.com> writes:

> The address of the mailbox node in the bcm283x.dtsi also has a typo.
> So fix it accordingly.
>
> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
> Reviewed-by: Andreas F?rber <afaerber@suse.de>
> Fixes: 05b682b7a3b2 ("ARM: bcm2835: dt: Add the mailbox to the device tree")

Pulled to bcm2835-dt-next.  Thanks!
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* [PATCH v3] ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
From: Stefan Wahren @ 2016-10-31 18:00 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <877f8os8vo.fsf@eliezer.anholt.net>


> Eric Anholt <eric@anholt.net> hat am 31. Oktober 2016 um 18:53 geschrieben:
> 
> 
> Stefan Wahren <stefan.wahren@i2se.com> writes:
> 
> > Hi Eric,
> >
> >> Eric Anholt <eric@anholt.net> hat am 27. Oktober 2016 um 18:52 geschrieben:
> >> 
> >> 
> >> From: Linus Walleij <linus.walleij@linaro.org>
> >> 
> >> The idea is to give useful names to GPIO lines that an implementer
> >> will be using from userspace, e.g. for maker type projects.  These are
> >> user-visible using tools/gpio/lsgpio.c
> >
> > sorry for the late feedback, but did you check your patch against the
> > Firmware
> > DTS [1]?
> >
> > As an example the GPIO38 is connected and named as USB_LIMIT_1A2 since
> > Raspberry
> > Pi 1 B Plus.
> >
> > [1] -
> > https://github.com/raspberrypi/documentation/blob/master/configuration/images/dt-blob.dts
> 
> I did use the dt-blob sometimes for cross-checking, but these are
> written against the schematics, not the dt-blob.  If you've got things
> you'd like changed, could you send a patch?

A patch against your v3 or my own v4 based on your patch?

^ permalink raw reply

* [PATCH v2] irqchip/bcm2836: Prevent spurious interrupts
From: Eric Anholt @ 2016-10-31 17:58 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.20.1610282141030.5053@nanos>

Thomas Gleixner <tglx@linutronix.de> writes:

> On Fri, 28 Oct 2016, Eric Anholt wrote:
>
>> Thomas Gleixner <tglx@linutronix.de> writes:
>> > This is missing a fixes tag. I have no idea when that problem was
>> > introduced, so I have no way to decide whether this needs to be tagged
>> > stable or not.
>> 
>> This code has been there since introduction of the driver, so:
>> 
>> Fixes: 1a15aaa998dc ("irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2")
>
> So it want's a stable tag, right?

I'm not the author here, and I was just trying to provide an assist with
upstreaming, so I'm not going to get too involved.  I'd say this is an
edge case for being a stable tree candidate (it's produces a scary dmesg
warning but no other functional problems that I know of), and I didn't
add a fixes tag myself because of that.
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* [PATCH v3] ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
From: Eric Anholt @ 2016-10-31 17:53 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <2009597620.98560.11cdcb7c-b46d-43f0-a853-b742fde3546a.open-xchange@email.1und1.de>

Stefan Wahren <stefan.wahren@i2se.com> writes:

> Hi Eric,
>
>> Eric Anholt <eric@anholt.net> hat am 27. Oktober 2016 um 18:52 geschrieben:
>> 
>> 
>> From: Linus Walleij <linus.walleij@linaro.org>
>> 
>> The idea is to give useful names to GPIO lines that an implementer
>> will be using from userspace, e.g. for maker type projects.  These are
>> user-visible using tools/gpio/lsgpio.c
>
> sorry for the late feedback, but did you check your patch against the Firmware
> DTS [1]?
>
> As an example the GPIO38 is connected and named as USB_LIMIT_1A2 since Raspberry
> Pi 1 B Plus.
>
> [1] -
> https://github.com/raspberrypi/documentation/blob/master/configuration/images/dt-blob.dts

I did use the dt-blob sometimes for cross-checking, but these are
written against the schematics, not the dt-blob.  If you've got things
you'd like changed, could you send a patch?
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* [PATCH v2] KVM: arm/arm64: vgic: Prevent access to invalid SPIs
From: Andre Przywara @ 2016-10-31 17:21 UTC (permalink / raw)
  To: linux-arm-kernel

In our VGIC implementation we limit the number of SPIs to a number
that the userland application told us. Accordingly we limit the
allocation of memory for virtual IRQs to that number.
However in our MMIO dispatcher we didn't check if we ever access an
IRQ beyond that limit, leading to out-of-bound accesses.
Add a test against the number of allocated SPIs in check_region().
Adjust the VGIC_ADDR_TO_INTID macro to avoid an actual division, which
is not implemented on ARM(32).

[maz: cleaned-up original patch]

Cc: stable at vger.kernel.org
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
Hi Marc,

does the last hunk fix the GCC issue that your recent fix addresses
as well? ilog2 seems to be pretty cheap on ARM and ARM64, so I wonder
if this version of the fix is better, since smaller?

Cheers,
Andre.

Changes v1 .. v2:
- fix compilation for 32-bit ARM

 virt/kvm/arm/vgic/vgic-mmio.c | 41 +++++++++++++++++++++++++++--------------
 virt/kvm/arm/vgic/vgic-mmio.h |  2 +-
 2 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
index e18b30d..ebe1b9f 100644
--- a/virt/kvm/arm/vgic/vgic-mmio.c
+++ b/virt/kvm/arm/vgic/vgic-mmio.c
@@ -453,17 +453,33 @@ struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
 	return container_of(dev, struct vgic_io_device, dev);
 }
 
-static bool check_region(const struct vgic_register_region *region,
+static bool check_region(const struct kvm *kvm,
+			 const struct vgic_register_region *region,
 			 gpa_t addr, int len)
 {
-	if ((region->access_flags & VGIC_ACCESS_8bit) && len == 1)
-		return true;
-	if ((region->access_flags & VGIC_ACCESS_32bit) &&
-	    len == sizeof(u32) && !(addr & 3))
-		return true;
-	if ((region->access_flags & VGIC_ACCESS_64bit) &&
-	    len == sizeof(u64) && !(addr & 7))
-		return true;
+	int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
+
+	switch (len) {
+	case sizeof(u8):
+		flags = VGIC_ACCESS_8bit;
+		break;
+	case sizeof(u32):
+		flags = VGIC_ACCESS_32bit;
+		break;
+	case sizeof(u64):
+		flags = VGIC_ACCESS_64bit;
+		break;
+	default:
+		return false;
+	}
+
+	if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
+		if (!region->bits_per_irq)
+			return true;
+
+		/* Do we access a non-allocated IRQ? */
+		return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
+	}
 
 	return false;
 }
@@ -477,7 +493,7 @@ static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 
 	region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
 				       addr - iodev->base_addr);
-	if (!region || !check_region(region, addr, len)) {
+	if (!region || !check_region(vcpu->kvm, region, addr, len)) {
 		memset(val, 0, len);
 		return 0;
 	}
@@ -510,10 +526,7 @@ static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 
 	region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
 				       addr - iodev->base_addr);
-	if (!region)
-		return 0;
-
-	if (!check_region(region, addr, len))
+	if (!region || !check_region(vcpu->kvm, region, addr, len))
 		return 0;
 
 	switch (iodev->iodev_type) {
diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h
index 4c34d39..dacd1155 100644
--- a/virt/kvm/arm/vgic/vgic-mmio.h
+++ b/virt/kvm/arm/vgic/vgic-mmio.h
@@ -58,7 +58,7 @@ extern struct kvm_io_device_ops kvm_io_gic_ops;
  * numerator and denominator with 8 to support at most 64 bits per IRQ:
  */
 #define VGIC_ADDR_TO_INTID(addr, bits)  (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \
-					64 / (bits) / 8)
+					64 >> (ilog2(bits) + 3))
 
 /*
  * Some VGIC registers store per-IRQ information, with a different number
-- 
2.9.0

^ permalink raw reply related

* [RFC PATCH v2 5/5] ARM64: dts: meson-gxl-s905x: Enable internal ethernet PHY
From: Neil Armstrong @ 2016-10-31 16:56 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932987-27871-1-git-send-email-narmstrong@baylibre.com>

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
index 07f0e0b..08237ee 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
@@ -46,3 +46,9 @@
 / {
 	compatible = "amlogic,s905x", "amlogic,meson-gxl";
 };
+
+/* S905X Only has access to its internal PHY */
+&ethmac {
+	phy-mode = "rmii";
+	phy-handle = <&internal_phy>;
+};
-- 
1.9.1

^ permalink raw reply related

* [RFC PATCH v2 4/5] ARM64: dts: meson-gxl-p23x: Enable ethernet
From: Neil Armstrong @ 2016-10-31 16:56 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932987-27871-1-git-send-email-narmstrong@baylibre.com>

Enable Ethernet on the p23x board, pinctrl attribute is only added for
the p230 board since the p231 only uses the Internal PHY.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts  | 16 ++++++++++++++++
 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts  |  6 ++++++
 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi |  4 ++++
 3 files changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index 3dfaa37..a569286 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -49,3 +49,19 @@
 	compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
 	model = "Amlogic Meson GXL (S905D) P230 Development Board";
 };
+
+/* P230 has exclusive choice between internal or external PHY */
+&ethmac {
+	pinctrl-0 = <&eth_pins>;
+	pinctrl-names = "default";
+
+	phy-handle = <&external_phy>;
+};
+
+&external_mdio {
+	external_phy: ethernet-phy at 0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		max-speed = <1000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
index ade8d29..1cc8d49 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
@@ -49,3 +49,9 @@
 	compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl";
 	model = "Amlogic Meson GXL (S905D) P231 Development Board";
 };
+
+/* P231 has only internal PHY port */
+&ethmac {
+	phy-mode = "rmii";
+	phy-handle = <&internal_phy>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
index bbe46a2..622ffbe 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
@@ -182,3 +182,7 @@
 	clocks = <&clkc CLKID_FCLK_DIV4>;
 	clock-names = "clkin0";
 };
+
+&ethmac {
+	status = "okay";
+};
-- 
1.9.1

^ permalink raw reply related

* [RFC PATCH v2 3/5] ARM64: dts: meson-gxl: Add ethernet nodes with internal PHY
From: Neil Armstrong @ 2016-10-31 16:56 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932987-27871-1-git-send-email-narmstrong@baylibre.com>

Add Ethernet node with Internal PHY selection for the Amlogic GXL SoCs

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 45 ++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index d1bf381..71670c3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -47,6 +47,24 @@
 
 / {
 	compatible = "amlogic,meson-gxl";
+
+
+};
+
+&ethmac {
+	reg = <0x0 0xc9410000 0x0 0x10000
+	       0x0 0xc8834540 0x0 0x4>;
+
+	clocks = <&clkc CLKID_ETH>,
+		 <&clkc CLKID_FCLK_DIV2>,
+		 <&clkc CLKID_MPLL2>;
+	clock-names = "stmmaceth", "clkin0", "clkin1";
+
+	mdio0: mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+	};
 };
 
 &aobus {
@@ -214,6 +232,33 @@
 			};
 		};
 	};
+
+	eth-phy-mux {
+		compatible = "mdio-mux-mmioreg", "mdio-mux";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x55c 0x0 0x4>;
+		mux-mask = <0xffffffff>;
+		mdio-parent-bus = <&mdio0>;
+
+		internal_mdio: mdio at e40908ff {
+			reg = <0xe40908ff>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			internal_phy: ethernet-phy at 8 {
+				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
+				reg = <8>;
+				max-speed = <100>;
+			};
+		};
+
+		external_mdio: mdio at 2009087f {
+			reg = <0x2009087f>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
 };
 
 &hiubus {
-- 
1.9.1

^ permalink raw reply related

* [RFC PATCH v2 2/5] net: phy: Add Meson GXL Internal PHY driver
From: Neil Armstrong @ 2016-10-31 16:56 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932987-27871-1-git-send-email-narmstrong@baylibre.com>

Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs.

This PHY seems to only implement some standard registers and need some
workarounds to provide autoneg values from vendor registers.

Some magic values are currently used to configure the PHY, and this a
temporary setup until clarification about these registers names and
registers fields are provided by Amlogic.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/net/phy/Kconfig     |  5 +++
 drivers/net/phy/Makefile    |  1 +
 drivers/net/phy/meson-gxl.c | 81 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 87 insertions(+)
 create mode 100644 drivers/net/phy/meson-gxl.c

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 2651c8d..09342b6 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -226,6 +226,11 @@ config DP83867_PHY
 	---help---
 	  Currently supports the DP83867 PHY.
 
+config MESON_GXL_PHY
+	tristate "Amlogic Meson GXL Internal PHY"
+	---help---
+	  Currently has a driver for the Amlogic Meson GXL Internal PHY
+
 config FIXED_PHY
 	tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
 	depends on PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index e58667d..1511b3e 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
 obj-$(CONFIG_MICREL_KS8995MA)	+= spi_ks8995.o
 obj-$(CONFIG_MICREL_PHY)	+= micrel.o
 obj-$(CONFIG_MICROCHIP_PHY)	+= microchip.o
+obj-$(CONFIG_MESON_GXL_PHY)	+= meson-gxl.o
 obj-$(CONFIG_MICROSEMI_PHY)	+= mscc.o
 obj-$(CONFIG_NATIONAL_PHY)	+= national.o
 obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
new file mode 100644
index 0000000..1ea69b7
--- /dev/null
+++ b/drivers/net/phy/meson-gxl.c
@@ -0,0 +1,81 @@
+/*
+ * Amlogic Meson GXL Internal PHY Driver
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ * Copyright (C) 2016 BayLibre, SAS. All rights reserved.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+
+static int meson_gxl_config_init(struct phy_device *phydev)
+{
+	/* Enable Analog and DSP register Bank access by */
+	phy_write(phydev, 0x14, 0x0000);
+	phy_write(phydev, 0x14, 0x0400);
+	phy_write(phydev, 0x14, 0x0000);
+	phy_write(phydev, 0x14, 0x0400);
+
+	/* Write Analog register 23 */
+	phy_write(phydev, 0x17, 0x8E0D);
+	phy_write(phydev, 0x14, 0x4417);
+
+	/* Enable fractional PLL */
+	phy_write(phydev, 0x17, 0x0005);
+	phy_write(phydev, 0x14, 0x5C1B);
+
+	/* Program fraction FR_PLL_DIV1 */
+	phy_write(phydev, 0x17, 0x029A);
+	phy_write(phydev, 0x14, 0x5C1D);
+
+	/* Program fraction FR_PLL_DIV1 */
+	phy_write(phydev, 0x17, 0xAAAA);
+	phy_write(phydev, 0x14, 0x5C1C);
+
+	return 0;
+}
+
+static struct phy_driver meson_gxl_phy[] = {
+	{
+		.phy_id		= 0x01814400,
+		.phy_id_mask	= 0xfffffff0,
+		.name		= "Meson GXL Internal PHY",
+		.features	= PHY_BASIC_FEATURES,
+		.flags		= PHY_IS_INTERNAL,
+		.config_init	= meson_gxl_config_init,
+		.config_aneg	= genphy_config_aneg,
+		.aneg_done      = genphy_aneg_done,
+		.read_status	= genphy_read_status,
+		.suspend        = genphy_suspend,
+		.resume         = genphy_resume,
+	},
+};
+
+static struct mdio_device_id __maybe_unused meson_gxl_tbl[] = {
+	{ 0x01814400, 0xfffffff0 },
+	{ }
+};
+
+module_phy_driver(meson_gxl_phy);
+
+MODULE_DEVICE_TABLE(mdio, meson_gxl_tbl);
+
+MODULE_DESCRIPTION("Amlogic Meson GXL Internal PHY driver");
+MODULE_AUTHOR("Baoqi wang");
+MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
+MODULE_LICENSE("GPL");
-- 
1.9.1

^ permalink raw reply related

* [RFC PATCH v2 1/5] net: mdio-mux-mmioreg: Add support for 16bit and 32bit register sizes
From: Neil Armstrong @ 2016-10-31 16:56 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932987-27871-1-git-send-email-narmstrong@baylibre.com>

In order to support PHY switching on Amlogic GXL SoCs, add support for
16bit and 32bit registers sizes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 .../devicetree/bindings/net/mdio-mux-mmioreg.txt   |  4 +-
 drivers/net/phy/mdio-mux-mmioreg.c                 | 60 +++++++++++++++++-----
 2 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt
index 8516929..065e8bd 100644
--- a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt
+++ b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt
@@ -3,7 +3,7 @@ Properties for an MDIO bus multiplexer controlled by a memory-mapped device
 This is a special case of a MDIO bus multiplexer.  A memory-mapped device,
 like an FPGA, is used to control which child bus is connected.  The mdio-mux
 node must be a child of the memory-mapped device.  The driver currently only
-supports devices with eight-bit registers.
+supports devices with 8, 16 or 32-bit registers.
 
 Required properties in addition to the generic multiplexer properties:
 
@@ -11,7 +11,7 @@ Required properties in addition to the generic multiplexer properties:
 
 - reg : integer, contains the offset of the register that controls the bus
 	multiplexer.  The size field in the 'reg' property is the size of
-	register, and must therefore be 1.
+	register, and must therefore be 1, 2, or 4.
 
 - mux-mask : integer, contains an eight-bit mask that specifies which
 	bits in the register control the actual bus multiplexer.  The
diff --git a/drivers/net/phy/mdio-mux-mmioreg.c b/drivers/net/phy/mdio-mux-mmioreg.c
index d0bed52..6a33646 100644
--- a/drivers/net/phy/mdio-mux-mmioreg.c
+++ b/drivers/net/phy/mdio-mux-mmioreg.c
@@ -21,7 +21,8 @@
 struct mdio_mux_mmioreg_state {
 	void *mux_handle;
 	phys_addr_t phys;
-	uint8_t mask;
+	unsigned int iosize;
+	unsigned int mask;
 };
 
 /*
@@ -47,17 +48,47 @@ static int mdio_mux_mmioreg_switch_fn(int current_child, int desired_child,
 	struct mdio_mux_mmioreg_state *s = data;
 
 	if (current_child ^ desired_child) {
-		void __iomem *p = ioremap(s->phys, 1);
-		uint8_t x, y;
-
+		void __iomem *p = ioremap(s->phys, s->iosize);
 		if (!p)
 			return -ENOMEM;
 
-		x = ioread8(p);
-		y = (x & ~s->mask) | desired_child;
-		if (x != y) {
-			iowrite8((x & ~s->mask) | desired_child, p);
-			pr_debug("%s: %02x -> %02x\n", __func__, x, y);
+		switch (s->iosize) {
+		case sizeof(uint8_t): {
+			uint8_t x, y;
+
+			x = ioread8(p);
+			y = (x & ~s->mask) | desired_child;
+			if (x != y) {
+				iowrite8((x & ~s->mask) | desired_child, p);
+				pr_debug("%s: %02x -> %02x\n", __func__, x, y);
+			}
+
+			break;
+		}
+		case sizeof(uint16_t): {
+			uint16_t x, y;
+
+			x = ioread16(p);
+			y = (x & ~s->mask) | desired_child;
+			if (x != y) {
+				iowrite16((x & ~s->mask) | desired_child, p);
+				pr_debug("%s: %04x -> %04x\n", __func__, x, y);
+			}
+
+			break;
+		}
+		case sizeof(uint32_t): {
+			uint32_t x, y;
+
+			x = ioread32(p);
+			y = (x & ~s->mask) | desired_child;
+			if (x != y) {
+				iowrite32((x & ~s->mask) | desired_child, p);
+				pr_debug("%s: %08x -> %08x\n", __func__, x, y);
+			}
+
+			break;
+		}
 		}
 
 		iounmap(p);
@@ -88,8 +119,11 @@ static int mdio_mux_mmioreg_probe(struct platform_device *pdev)
 	}
 	s->phys = res.start;
 
-	if (resource_size(&res) != sizeof(uint8_t)) {
-		dev_err(&pdev->dev, "only 8-bit registers are supported\n");
+	s->iosize = resource_size(&res);
+	if (s->iosize != sizeof(uint8_t) &&
+	    s->iosize != sizeof(uint16_t) &&
+	    s->iosize != sizeof(uint32_t)) {
+		dev_err(&pdev->dev, "only 8/16/32-bit registers are supported\n");
 		return -EINVAL;
 	}
 
@@ -98,8 +132,8 @@ static int mdio_mux_mmioreg_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "missing or invalid mux-mask property\n");
 		return -ENODEV;
 	}
-	if (be32_to_cpup(iprop) > 255) {
-		dev_err(&pdev->dev, "only 8-bit registers are supported\n");
+	if (be32_to_cpup(iprop) >= BIT(s->iosize * 8)) {
+		dev_err(&pdev->dev, "only 8/16/32-bit registers are supported\n");
 		return -EINVAL;
 	}
 	s->mask = be32_to_cpup(iprop);
-- 
1.9.1

^ permalink raw reply related

* [RFC PATCH v2 0/5] ARM64: Add Internal PHY support for Meson GXL
From: Neil Armstrong @ 2016-10-31 16:56 UTC (permalink / raw)
  To: linux-arm-kernel

The Amlogic Meson GXL SoCs have an internal RMII PHY that is muxed with the
external RGMII pins.

In order to support switching between the two PHYs links, extended registers
size for mdio-mux-mmioreg must be added.

Finally, the internal PHY is added in the GXL dtsi and support for each
board is added in intermediate board family dtsi or final dts.

This patchset depends on ARM64 dts patch at [1]

Changes since original RFC patchset at : [2]
 - Remove meson8b experimental phy switching
 - Switch to mdio-mux-mmioreg with extennded size support
 - Add internal phy support for S905x and p231
 - Add external PHY support for p230

[1] http://lkml.kernel.org/r/1477932286-27482-1-git-send-email-narmstrong at baylibre.com
[2] http://lkml.kernel.org/r/1477060838-14164-1-git-send-email-narmstrong at baylibre.com

Neil Armstrong (5):
  net: mdio-mux-mmioreg: Add support for 16bit and 32bit register sizes
  net: phy: Add Meson GXL Internal PHY driver
  ARM64: dts: meson-gxl: Add ethernet nodes with internal PHY
  ARM64: dts: meson-gxl-p23x: Enable ethernet
  ARM64: dts: meson-gxl-s905x: Enable internal ethernet PHY

 .../devicetree/bindings/net/mdio-mux-mmioreg.txt   |  4 +-
 .../boot/dts/amlogic/meson-gxl-s905d-p230.dts      | 16 +++++
 .../boot/dts/amlogic/meson-gxl-s905d-p231.dts      |  6 ++
 .../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi     |  4 ++
 arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi   |  6 ++
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi         | 45 ++++++++++++
 drivers/net/phy/Kconfig                            |  5 ++
 drivers/net/phy/Makefile                           |  1 +
 drivers/net/phy/mdio-mux-mmioreg.c                 | 60 ++++++++++++----
 drivers/net/phy/meson-gxl.c                        | 81 ++++++++++++++++++++++
 10 files changed, 213 insertions(+), 15 deletions(-)
 create mode 100644 drivers/net/phy/meson-gxl.c

-- 
1.9.1

^ permalink raw reply

* [PATCH 8/8] ARM64: dts: meson-gxl-p23x: Enable IR receiver
From: Neil Armstrong @ 2016-10-31 16:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932286-27482-1-git-send-email-narmstrong@baylibre.com>

Enable the Infraread Receiver on the p23x board.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
index 7830809..bbe46a2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
@@ -105,6 +105,12 @@
 	pinctrl-names = "default";
 };
 
+&ir {
+	status = "okay";
+	pinctrl-0 = <&remote_input_ao_pins>;
+	pinctrl-names = "default";
+};
+
 /* Wireless SDIO Module */
 &sd_emmc_a {
 	status = "okay";
-- 
1.9.1

^ permalink raw reply related

* [PATCH 7/8] ARM64: dts: meson-gxl-p23x: Add SD/SDIO/MMC and PWM nodes
From: Neil Armstrong @ 2016-10-31 16:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932286-27482-1-git-send-email-narmstrong@baylibre.com>

Add SD/SDIO/MMC nodes and PWM 32768Hz clock configuration to provide
storage and WiFi functionality on the p23x boards.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 .../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi     | 112 +++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
index 666fe2b..7830809 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
@@ -56,6 +56,46 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
+
+	vddio_boot: regulator-vddio_boot {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_BOOT";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vddao_3v3: regulator-vddao_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc_3v3: regulator-vcc_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+	};
+
+	wifi32k: wifi32k {
+		compatible = "pwm-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+		clocks = <&wifi32k>;
+		clock-names = "ext_clock";
+	};
 };
 
 /* This UART is brought out to the DB9 connector */
@@ -64,3 +104,75 @@
 	pinctrl-0 = <&uart_ao_a_pins>;
 	pinctrl-names = "default";
 };
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+	status = "okay";
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <100000000>;
+
+	non-removable;
+	disable-wp;
+
+	mmc-pwrseq = <&sdio_pwrseq>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+
+	brcmf: bcrmf at 1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+/* SD card */
+&sd_emmc_b {
+	status = "okay";
+	pinctrl-0 = <&sdcard_pins>;
+	pinctrl-names = "default";
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <100000000>;
+	disable-wp;
+
+	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_pins>;
+	pinctrl-names = "default";
+
+	bus-width = <8>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	max-frequency = <200000000>;
+	non-removable;
+	disable-wp;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+
+	mmc-pwrseq = <&emmc_pwrseq>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+};
+
+&pwm_ef {
+	status = "okay";
+	pinctrl-0 = <&pwm_e_pins>;
+	pinctrl-names = "default";
+	clocks = <&clkc CLKID_FCLK_DIV4>;
+	clock-names = "clkin0";
+};
-- 
1.9.1

^ permalink raw reply related

* [PATCH 6/8] ARM64: dts: meson-gxl-p23x: Add uart pinctrl
From: Neil Armstrong @ 2016-10-31 16:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932286-27482-1-git-send-email-narmstrong@baylibre.com>

Add pinctrl attribute to p23x uart node.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
index bf08e87..666fe2b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
@@ -58,6 +58,9 @@
 	};
 };
 
+/* This UART is brought out to the DB9 connector */
 &uart_AO {
 	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
 };
-- 
1.9.1

^ permalink raw reply related

* [PATCH 5/8] ARM64: dts: meson-gxl: Add MMC/SD/SDIO nodes
From: Neil Armstrong @ 2016-10-31 16:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932286-27482-1-git-send-email-narmstrong@baylibre.com>

Add MMC/SD/SDIO nodes clock attributes for Amlogic Meson GXL.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index b45df2a..d1bf381 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -235,3 +235,24 @@
 &i2c_C {
 	clocks = <&clkc CLKID_I2C>;
 };
+
+&sd_emmc_a {
+	clocks = <&clkc CLKID_SD_EMMC_A>,
+		 <&xtal>,
+		 <&clkc CLKID_FCLK_DIV2>;
+	clock-names = "core", "clkin0", "clkin1";
+};
+
+&sd_emmc_b {
+	clocks = <&clkc CLKID_SD_EMMC_B>,
+		 <&xtal>,
+		 <&clkc CLKID_FCLK_DIV2>;
+       clock-names = "core", "clkin0", "clkin1";
+};
+
+&sd_emmc_c {
+	clocks = <&clkc CLKID_SD_EMMC_C>,
+		 <&xtal>,
+		 <&clkc CLKID_FCLK_DIV2>;
+	clock-names = "core", "clkin0", "clkin1";
+};
-- 
1.9.1

^ permalink raw reply related

* [PATCH 4/8] ARM64: dts: meson-gxl: Add i2c nodes
From: Neil Armstrong @ 2016-10-31 16:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932286-27482-1-git-send-email-narmstrong@baylibre.com>

Add i2c nodes clock attributes for Amlogic Meson GXL.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 33d0506..b45df2a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -223,3 +223,15 @@
 		reg = <0x0 0x0 0x0 0x3db>;
 	};
 };
+
+&i2c_A {
+	clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_B {
+	clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_C {
+	clocks = <&clkc CLKID_I2C>;
+};
-- 
1.9.1

^ permalink raw reply related

* [PATCH 3/8] ARM64: dts: meson-gxl: Add clock nodes
From: Neil Armstrong @ 2016-10-31 16:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932286-27482-1-git-send-email-narmstrong@baylibre.com>

Add clock node for Amlogic Meson GXL.
The GXBB compatible is retained since the GXBB clock tree is used for now.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index ce7f550..33d0506 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -42,6 +42,7 @@
  */
 
 #include "meson-gx.dtsi"
+#include <dt-bindings/clock/gxbb-clkc.h>
 #include <dt-bindings/gpio/meson-gxl-gpio.h>
 
 / {
@@ -214,3 +215,11 @@
 		};
 	};
 };
+
+&hiubus {
+	clkc: clock-controller at 0 {
+		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
+		#clock-cells = <1>;
+		reg = <0x0 0x0 0x0 0x3db>;
+	};
+};
-- 
1.9.1

^ permalink raw reply related

* [PATCH 2/8] ARM64: dts: meson-gxl: Add pinctrl nodes
From: Neil Armstrong @ 2016-10-31 16:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932286-27482-1-git-send-email-narmstrong@baylibre.com>

Add pinctrl nodes and pin definitions for Amlogic Meson GXL.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 168 +++++++++++++++++++++++++++++
 1 file changed, 168 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 13b10ee..ce7f550 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -42,7 +42,175 @@
  */
 
 #include "meson-gx.dtsi"
+#include <dt-bindings/gpio/meson-gxl-gpio.h>
 
 / {
 	compatible = "amlogic,meson-gxl";
 };
+
+&aobus {
+	pinctrl_aobus: pinctrl at 14 {
+		compatible = "amlogic,meson-gxl-aobus-pinctrl";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gpio_ao: bank at 14 {
+			reg = <0x0 0x00014 0x0 0x8>,
+			      <0x0 0x0002c 0x0 0x4>,
+			      <0x0 0x00024 0x0 0x8>;
+			reg-names = "mux", "pull", "gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		uart_ao_a_pins: uart_ao_a {
+			mux {
+				groups = "uart_tx_ao_a", "uart_rx_ao_a";
+				function = "uart_ao";
+			};
+		};
+
+		remote_input_ao_pins: remote_input_ao {
+			mux {
+				groups = "remote_input_ao";
+				function = "remote_input_ao";
+			};
+		};
+	};
+};
+
+&periphs {
+	pinctrl_periphs: pinctrl at 4b0 {
+		compatible = "amlogic,meson-gxl-periphs-pinctrl";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gpio: bank at 4b0 {
+			reg = <0x0 0x004b0 0x0 0x28>,
+			      <0x0 0x004e8 0x0 0x14>,
+			      <0x0 0x00120 0x0 0x14>,
+			      <0x0 0x00430 0x0 0x40>;
+			reg-names = "mux", "pull", "pull-enable", "gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		emmc_pins: emmc {
+			mux {
+				groups = "emmc_nand_d07",
+				       "emmc_cmd",
+				       "emmc_clk",
+				       "emmc_ds";
+				function = "emmc";
+			};
+		};
+
+		sdcard_pins: sdcard {
+			mux {
+				groups = "sdcard_d0",
+				       "sdcard_d1",
+				       "sdcard_d2",
+				       "sdcard_d3",
+				       "sdcard_cmd",
+				       "sdcard_clk";
+				function = "sdcard";
+			};
+		};
+
+		sdio_pins: sdio {
+			mux {
+				groups = "sdio_d0",
+				       "sdio_d1",
+				       "sdio_d2",
+				       "sdio_d3",
+				       "sdio_cmd",
+				       "sdio_clk";
+				function = "sdio";
+			};
+		};
+
+		sdio_irq_pins: sdio_irq {
+			mux {
+				groups = "sdio_irq";
+				function = "sdio";
+			};
+		};
+
+		uart_a_pins: uart_a {
+			mux {
+				groups = "uart_tx_a",
+				       "uart_rx_a";
+				function = "uart_a";
+			};
+		};
+
+		uart_b_pins: uart_b {
+			mux {
+				groups = "uart_tx_b",
+				       "uart_rx_b";
+				function = "uart_b";
+			};
+		};
+
+		uart_c_pins: uart_c {
+			mux {
+				groups = "uart_tx_c",
+				       "uart_rx_c";
+				function = "uart_c";
+			};
+		};
+
+		i2c_a_pins: i2c_a {
+			mux {
+				groups = "i2c_sck_a",
+				     "i2c_sda_a";
+				function = "i2c_a";
+			};
+		};
+
+		i2c_b_pins: i2c_b {
+			mux {
+				groups = "i2c_sck_b",
+				      "i2c_sda_b";
+				function = "i2c_b";
+			};
+		};
+
+		i2c_c_pins: i2c_c {
+			mux {
+				groups = "i2c_sck_c",
+				      "i2c_sda_c";
+				function = "i2c_c";
+			};
+		};
+
+		eth_pins: eth_c {
+			mux {
+				groups = "eth_mdio",
+				       "eth_mdc",
+				       "eth_clk_rx_clk",
+				       "eth_rx_dv",
+				       "eth_rxd0",
+				       "eth_rxd1",
+				       "eth_rxd2",
+				       "eth_rxd3",
+				       "eth_rgmii_tx_clk",
+				       "eth_tx_en",
+				       "eth_txd0",
+				       "eth_txd1",
+				       "eth_txd2",
+				       "eth_txd3";
+				function = "eth";
+			};
+		};
+
+		pwm_e_pins: pwm_e {
+			mux {
+				groups = "pwm_e";
+				function = "pwm_e";
+			};
+		};
+	};
+};
-- 
1.9.1

^ permalink raw reply related

* [PATCH 1/8] ARM64: dts: meson-gxbb: Move common nodes to meson-gx
From: Neil Armstrong @ 2016-10-31 16:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1477932286-27482-1-git-send-email-narmstrong@baylibre.com>

Move common nodes between GXBB and GXL in to the common GX dtsi.
Leave the clock attributes in the GXBB dtsi for now.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi   | 131 ++++++++++++++++++++++++
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 153 ++++------------------------
 2 files changed, 148 insertions(+), 136 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index fd1d0de..91be4f2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -129,6 +129,30 @@
 		#clock-cells = <0>;
 	};
 
+	firmware {
+		sm: secure-monitor {
+			compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
+		};
+	};
+
+	efuse: efuse {
+		compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		sn: sn at 14 {
+			reg = <0x14 0x10>;
+		};
+
+		eth_mac: eth_mac at 34 {
+			reg = <0x34 0x10>;
+		};
+
+		bid: bid at 46 {
+			reg = <0x46 0x30>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -142,6 +166,12 @@
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
 
+			reset: reset-controller at 4404 {
+				compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
+				reg = <0x0 0x04404 0x0 0x20>;
+				#reset-cells = <1>;
+			};
+
 			uart_A: serial at 84c0 {
 				compatible = "amlogic,meson-uart";
 				reg = <0x0 0x84c0 0x0 0x14>;
@@ -149,6 +179,76 @@
 				clocks = <&xtal>;
 				status = "disabled";
 			};
+
+			uart_B: serial at 84dc {
+				compatible = "amlogic,meson-uart";
+				reg = <0x0 0x84dc 0x0 0x14>;
+				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>;
+				status = "disabled";
+			};
+
+			i2c_A: i2c at 8500 {
+				compatible = "amlogic,meson-gxbb-i2c";
+				reg = <0x0 0x08500 0x0 0x20>;
+				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			pwm_ab: pwm at 8550 {
+				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+				reg = <0x0 0x08550 0x0 0x10>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_cd: pwm at 8650 {
+				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+				reg = <0x0 0x08650 0x0 0x10>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_ef: pwm at 86c0 {
+				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+				reg = <0x0 0x086c0 0x0 0x10>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			uart_C: serial at 8700 {
+				compatible = "amlogic,meson-uart";
+				reg = <0x0 0x8700 0x0 0x14>;
+				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>;
+				status = "disabled";
+			};
+
+			i2c_B: i2c at 87c0 {
+				compatible = "amlogic,meson-gxbb-i2c";
+				reg = <0x0 0x087c0 0x0 0x20>;
+				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c_C: i2c at 87e0 {
+				compatible = "amlogic,meson-gxbb-i2c";
+				reg = <0x0 0x087e0 0x0 0x20>;
+				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			watchdog at 98d0 {
+				compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
+				reg = <0x0 0x098d0 0x0 0x10>;
+				clocks = <&xtal>;
+			};
 		};
 
 		gic: interrupt-controller at c4301000 {
@@ -178,6 +278,13 @@
 				clocks = <&xtal>;
 				status = "disabled";
 			};
+
+			ir: ir at 580 {
+				compatible = "amlogic,meson-gxbb-ir";
+				reg = <0x0 0x00580 0x0 0x40>;
+				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+			};
 		};
 
 		periphs: periphs at c8834000 {
@@ -186,6 +293,11 @@
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
+
+			rng {
+				compatible = "amlogic,meson-rng";
+				reg = <0x0 0x0 0x0 0x4>;
+			};
 		};
 
 
@@ -195,6 +307,25 @@
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
+
+			mailbox: mailbox at 404 {
+				compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+				reg = <0 0x404 0 0x4c>;
+				interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
+					     <0 209 IRQ_TYPE_EDGE_RISING>,
+					     <0 210 IRQ_TYPE_EDGE_RISING>;
+				#mbox-cells = <1>;
+			};
+		};
+
+		ethmac: ethernet at c9410000 {
+			compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+			reg = <0x0 0xc9410000 0x0 0x10000
+			       0x0 0xc8834540 0x0 0x4>;
+			interrupts = <0 8 1>;
+			interrupt-names = "macirq";
+			phy-mode = "rgmii";
+			status = "disabled";
 		};
 
 		apb: apb at d0000000 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 2d69a3b..160664f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -50,30 +50,6 @@
 / {
 	compatible = "amlogic,meson-gxbb";
 
-	firmware {
-		sm: secure-monitor {
-			compatible = "amlogic,meson-gxbb-sm";
-		};
-	};
-
-	efuse: efuse {
-		compatible = "amlogic,meson-gxbb-efuse";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		sn: sn at 14 {
-			reg = <0x14 0x10>;
-		};
-
-		eth_mac: eth_mac at 34 {
-			reg = <0x34 0x10>;
-		};
-
-		bid: bid at 46 {
-			reg = <0x46 0x30>;
-		};
-	};
-
 	scpi {
 		compatible = "amlogic,meson-gxbb-scpi";
 		mboxes = <&mailbox 1 &mailbox 2>;
@@ -158,20 +134,6 @@
 			dr_mode = "host";
 			status = "disabled";
 		};
-
-		ethmac: ethernet at c9410000 {
-			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
-			reg = <0x0 0xc9410000 0x0 0x10000
-			       0x0 0xc8834540 0x0 0x4>;
-			interrupts = <0 8 1>;
-			interrupt-names = "macirq";
-			clocks = <&clkc CLKID_ETH>,
-				 <&clkc CLKID_FCLK_DIV2>,
-				 <&clkc CLKID_MPLL2>;
-			clock-names = "stmmaceth", "clkin0", "clkin1";
-			phy-mode = "rgmii";
-			status = "disabled";
-		};
 	};
 };
 
@@ -192,55 +154,6 @@
 };
 
 &cbus {
-	reset: reset-controller at 4404 {
-		compatible = "amlogic,meson-gxbb-reset";
-		reg = <0x0 0x04404 0x0 0x20>;
-		#reset-cells = <1>;
-	};
-
-	uart_B: serial at 84dc {
-		compatible = "amlogic,meson-uart";
-		reg = <0x0 0x84dc 0x0 0x14>;
-		interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
-		clocks = <&xtal>;
-		status = "disabled";
-	};
-
-	pwm_ab: pwm at 8550 {
-		compatible = "amlogic,meson-gxbb-pwm";
-		reg = <0x0 0x08550 0x0 0x10>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pwm_cd: pwm at 8650 {
-		compatible = "amlogic,meson-gxbb-pwm";
-		reg = <0x0 0x08650 0x0 0x10>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pwm_ef: pwm at 86c0 {
-		compatible = "amlogic,meson-gxbb-pwm";
-		reg = <0x0 0x086c0 0x0 0x10>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	uart_C: serial at 8700 {
-		compatible = "amlogic,meson-uart";
-		reg = <0x0 0x8700 0x0 0x14>;
-		interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
-		clocks = <&xtal>;
-		status = "disabled";
-	};
-
-	watchdog at 98d0 {
-		compatible = "amlogic,meson-gxbb-wdt";
-		reg = <0x0 0x098d0 0x0 0x10>;
-		clocks = <&xtal>;
-	};
-
 	spifc: spi at 8c80 {
 		compatible = "amlogic,meson-gxbb-spifc";
 		reg = <0x0 0x08c80 0x0 0x80>;
@@ -249,36 +162,13 @@
 		clocks = <&clkc CLKID_SPI>;
 		status = "disabled";
 	};
+};
 
-	i2c_A: i2c at 8500 {
-		compatible = "amlogic,meson-gxbb-i2c";
-		reg = <0x0 0x08500 0x0 0x20>;
-		interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
-		clocks = <&clkc CLKID_I2C>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c_B: i2c at 87c0 {
-		compatible = "amlogic,meson-gxbb-i2c";
-		reg = <0x0 0x087c0 0x0 0x20>;
-		interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
-		clocks = <&clkc CLKID_I2C>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c_C: i2c at 87e0 {
-		compatible = "amlogic,meson-gxbb-i2c";
-		reg = <0x0 0x087e0 0x0 0x20>;
-		interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
-		clocks = <&clkc CLKID_I2C>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
+&ethmac {
+	clocks = <&clkc CLKID_ETH>,
+		 <&clkc CLKID_FCLK_DIV2>,
+		 <&clkc CLKID_MPLL2>;
+	clock-names = "stmmaceth", "clkin0", "clkin1";
 };
 
 &aobus {
@@ -355,13 +245,6 @@
 		#reset-cells = <1>;
 	};
 
-	ir: ir at 580 {
-		compatible = "amlogic,meson-gxbb-ir";
-		reg = <0x0 0x00580 0x0 0x40>;
-		interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
-		status = "disabled";
-	};
-
 	pwm_ab_AO: pwm at 550 {
 		compatible = "amlogic,meson-gxbb-pwm";
 		reg = <0x0 0x0550 0x0 0x10>;
@@ -381,11 +264,6 @@
 };
 
 &periphs {
-	rng {
-		compatible = "amlogic,meson-rng";
-		reg = <0x0 0x0 0x0 0x4>;
-	};
-
 	pinctrl_periphs: pinctrl at 4b0 {
 		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
 		#address-cells = <2>;
@@ -593,15 +471,18 @@
 		#clock-cells = <1>;
 		reg = <0x0 0x0 0x0 0x3db>;
 	};
+};
 
-	mailbox: mailbox at 404 {
-		compatible = "amlogic,meson-gxbb-mhu";
-		reg = <0 0x404 0 0x4c>;
-		interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
-			     <0 209 IRQ_TYPE_EDGE_RISING>,
-			     <0 210 IRQ_TYPE_EDGE_RISING>;
-		#mbox-cells = <1>;
-	};
+&i2c_A {
+	clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_B {
+	clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_C {
+	clocks = <&clkc CLKID_I2C>;
 };
 
 &sd_emmc_a {
-- 
1.9.1

^ permalink raw reply related

* [PATCH 0/8] ARM64: dts: meson-gxl: Add extended support
From: Neil Armstrong @ 2016-10-31 16:44 UTC (permalink / raw)
  To: linux-arm-kernel

This patchset provides extended peripheral support for the Amlogix GXL SoCs.

In order to support more functionalities, this patchset :
 - Moves peripheral nodes to the common Meson arm64 dtsi
 - Add i2c, mmc, sd, sdio, pinctrl and clock nodes for GXL
 - Adds correct GXL P23X boards uart pinctrl
 - Add SD/MMC and SDIO WiFi support support for P23X boards

This patchset depends on pinctrl patch at [1] and the dt-include file :
include/dt-bindings/gpio/meson-gxl-gpio.h

Changes since original RFC patchset at : [2]
 - Rebased on v4.10/dt64 at [3] commit b2ac270c3836 ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")

[1] http://lkml.kernel.org/r/1477931531-27120-1-git-send-email-narmstrong at baylibre.com
[2] http://lkml.kernel.org/r/1477060838-14164-1-git-send-email-narmstrong at baylibre.com
[3] git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git

Neil Armstrong (8):
  ARM64: dts: meson-gxbb: Move common nodes to meson-gx
  ARM64: dts: meson-gxl: Add pinctrl nodes
  ARM64: dts: meson-gxl: Add clock nodes
  ARM64: dts: meson-gxl: Add i2c nodes
  ARM64: dts: meson-gxl: Add MMC/SD/SDIO nodes
  ARM64: dts: meson-gxl-p23x: Add uart pinctrl
  ARM64: dts: meson-gxl-p23x: Add SD/SDIO/MMC and PWM nodes
  ARM64: dts: meson-gxl-p23x: Enable IR receiver

 arch/arm64/boot/dts/amlogic/meson-gx.dtsi          | 131 +++++++++++++
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi        | 153 ++-------------
 .../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi     | 121 ++++++++++++
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi         | 210 +++++++++++++++++++++
 4 files changed, 479 insertions(+), 136 deletions(-)

-- 
1.9.1

^ permalink raw reply

* [PATCH] ARM: DT: stm32: move dma translation to board files
From: Bruno Herrera @ 2016-10-31 16:41 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <CAFvLkMQ6YMg4sf2Ug8x4-YshwnjbLz3aVzm+JpKP6zG9r-WU4Q@mail.gmail.com>

On Mon, Oct 31, 2016 at 12:14 PM, Rados?aw Pietrzyk
<radoslaw.pietrzyk@gmail.com> wrote:
> This is weird because dma ddresses are recalculated using parent's
> dma-ranges property and soc already has it so there should be absolutely no
> problem.

These are my DTS and DTSI file.
>
> 2016-10-31 11:27 GMT+01:00 Bruno Herrera <bruherrera@gmail.com>:
>>
>> On Fri, Oct 28, 2016 at 5:09 AM, Rados?aw Pietrzyk
>> <radoslaw.pietrzyk@gmail.com> wrote:
>> > Have you defined your sdio node within soc node ?
>>
>> It is in the SOC node of the DSTI file.
>>
>> >
>> > 2016-10-27 14:57 GMT+02:00 Bruno Herrera <bruherrera@gmail.com>:
>> >>
>> >> Hi Alex,
>> >>
>> >> On Thu, Oct 27, 2016 at 10:21 AM, Alexandre Torgue
>> >> <alexandre.torgue@st.com> wrote:
>> >> > Hi Bruno,
>> >> >
>> >> >
>> >> > On 10/27/2016 12:43 PM, Bruno Herrera wrote:
>> >> >>
>> >> >> Hi Alex,
>> >> >>
>> >> >> On Wed, Oct 26, 2016 at 7:09 AM, Alexandre Torgue
>> >> >> <alexandre.torgue@st.com> wrote:
>> >> >>>
>> >> >>> Hi Bruno,
>> >> >>>
>> >> >>> On 10/25/2016 11:06 PM, Bruno Herrera wrote:
>> >> >>>>
>> >> >>>>
>> >> >>>> Hi Alexandre,
>> >> >>>>
>> >> >>>>>
>> >> >>>>> stm32f469-disco and stm32f429-eval boards use SDRAM start address
>> >> >>>>> remapping
>> >> >>>>> (to @0) to boost performances. A DMA translation through
>> >> >>>>> "dma-ranges"
>> >> >>>>> property was needed for other masters than the M4 CPU.
>> >> >>>>> stm32f429-disco doesn't use remapping so doesn't need this DMA
>> >> >>>>> translation.
>> >> >>>>> This patches moves this DMA translation definition from stm32f429
>> >> >>>>> soc
>> >> >>>>> file
>> >> >>>>> to board files.
>> >> >>>>>
>> >> >>>>> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>> >> >>>>>
>> >> >>>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >>>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >>>>> index 13c7cd2..a763c15 100644
>> >> >>>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >>>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >>>>> @@ -82,6 +82,10 @@
>> >> >>>>>                 };
>> >> >>>>>         };
>> >> >>>>>
>> >> >>>>> +       soc {
>> >> >>>>> +               dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >>>>> +       };
>> >> >>>>> +
>> >> >>>>>         usbotg_hs_phy: usbphy {
>> >> >>>>>                 #phy-cells = <0>;
>> >> >>>>>                 compatible = "usb-nop-xceiv";
>> >> >>>>
>> >> >>>>
>> >> >>>>
>> >> >>>> Shouldn't also the peripheral dma-ranges property move to board
>> >> >>>> specific
>> >> >>>> too?
>> >> >>>> I  had this patch for while but I didn't had the time to submit:
>> >> >>>
>> >> >>>
>> >> >>>
>> >> >>> Well spot I forgot it. Actually, discussing with Arnd ysterday on
>> >> >>> IIRC,
>> >> >>> empty dma-ranges is not needed. Can you test on your side by
>> >> >>> removing
>> >> >>> dma-ranges in usb node please ?
>> >> >>
>> >> >> Unfortunately will take a time for me to set up this environment on
>> >> >> the STM32F4-EVAL board.
>> >> >> And on the discovery boards we dont have this scenario. That was the
>> >> >> main reason I did not submit the patch right away.
>> >> >> My conclusion and I might be wrong but is based on the my tests with
>> >> >> SDIO device at STM32F469I-DISCO board.
>> >> >>
>> >> >> I started this issue as discussion at ST Forum but Maxime gave me
>> >> >> the
>> >> >> hint.
>> >> >>
>> >> >>
>> >> >>
>> >> >>
>> >> >> https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=44
>> >> >>
>> >> >>> I will push a v2 by removing empty dma-ranges if tests are ok in
>> >> >>> your
>> >> >>> side.
>> >> >>
>> >> >>
>> >> >> From my understating/conclusion is: when empty property(dma-ranges)
>> >> >> is
>> >> >> the device node, the mapping will be taken in consideration when
>> >> >> using
>> >> >> DMA otherwise the mapping is ignored.
>> >> >> And in the SDIO case it is needed for DEV->MEM(SDRAM) and
>> >> >> MEM(SDRAM)->DEV. If it is not the case for the devices in question
>> >> >> so
>> >> >> I suppose it can work without the property.
>> >> >
>> >> >
>> >> > For sure translation has to be done but I'm not sure that an empty
>> >> > "dma-ranges" is needed in device node to activate it. For Ethernet
>> >> > empty
>> >> > "dma-ranges" is not needed. I will try with usb.
>> >>
>> >> In the case of SDIO it is needed. As example this is my working SDIO
>> >> node:
>> >>
>> >> sdio: sdio at 40012c00 {
>> >> compatible = "arm,pl18x", "arm,primecell";
>> >> arm,primecell-periphid = <0x00480181>;
>> >> reg = <0x40012c00 0x400>;
>> >> dmas =  <&dma2 6 4 0x10400 0x3>, /* Logical - DevToMem */
>> >> <&dma2 3 4 0x10400 0x3>; /* Logical - MemToDev */
>> >> dma-names = "rx", "tx";
>> >> clocks = <&rcc 0 171>;
>> >> clock-names = "apb_pclk";
>> >> interrupts = <49>;
>> >> status = "disabled";
>> >> };
>> >>
>> >> &sdio {
>> >> status = "okay";
>> >> vmmc-supply = <&wlan_en>;
>> >> bus-width = <4>;
>> >> max-frequency = <24000000>;
>> >> pinctrl-names = "default";
>> >> pinctrl-0 = <&sdio_pins>;
>> >> ti,non-removable;
>> >> ti,needs-special-hs-handling;
>> >> dma-ranges;
>> >> cap-power-off-card;
>> >> keep-power-in-suspend;
>> >>
>> >> #address-cells = <1>;
>> >> #size-cells = <0>;
>> >> wlcore: wlcore at 0 {
>> >> compatible = "ti,wl1835";
>> >> reg = <2>;
>> >> interrupt-parent = <&gpioa>;
>> >> interrupts = <8 IRQ_TYPE_EDGE_RISING>;
>> >> };
>> >> };
>> >>
>> >> >
>> >> > alex
>> >> >
>> >> >
>> >> >>
>> >> >>>
>> >> >>> Thanks in advance
>> >> >>> Alex
>> >> >>>
>> >> >>>
>> >> >>>>
>> >> >>>> Author: Bruno Herrera <bruherrera@gmail.com>
>> >> >>>> Date:   Sun Oct 16 14:50:00 2016 -0200
>> >> >>>>
>> >> >>>>     ARM: DT: STM32: Use dma-ranges property per board not at dtsi
>> >> >>>> file
>> >> >>>>
>> >> >>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >>>> index 6bfc595..2a22a82 100644
>> >> >>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >>>> @@ -52,6 +52,10 @@
>> >> >>>>         model = "STMicroelectronics STM32429i-EVAL board";
>> >> >>>>         compatible = "st,stm32429i-eval", "st,stm32f429";
>> >> >>>>
>> >> >>>> +       soc {
>> >> >>>> +               dma-ranges = <0xC0000000 0x0 0x10000000>;
>> >> >>>> +       };
>> >> >>>> +
>> >> >>>>         chosen {
>> >> >>>>                 bootargs = "root=/dev/ram rdinit=/linuxrc";
>> >> >>>>                 stdout-path = "serial0:115200n8";
>> >> >>>> @@ -96,6 +100,7 @@
>> >> >>>>
>> >> >>>>  &ethernet0 {
>> >> >>>>         status = "okay";
>> >> >>>> +       dma-ranges;
>> >> >>>>         pinctrl-0       = <&ethernet0_mii>;
>> >> >>>>         pinctrl-names   = "default";
>> >> >>>>         phy-mode        = "mii-id";
>> >> >>>> @@ -116,6 +121,7 @@
>> >> >>>>  };
>> >> >>>>
>> >> >>>>  &usbotg_hs {
>> >> >>>> +       dma-ranges;
>> >> >>>>         dr_mode = "host";
>> >> >>>>         phys = <&usbotg_hs_phy>;
>> >> >>>>         phy-names = "usb2-phy";
>> >> >>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >>>> b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >>>> index 7d624a2..697a133 100644
>> >> >>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >>>> @@ -59,7 +59,6 @@
>> >> >>>>         };
>> >> >>>>
>> >> >>>>         soc {
>> >> >>>> -               dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >>>>
>> >> >>>>                 timer2: timer at 40000000 {
>> >> >>>>                         compatible = "st,stm32-timer";
>> >> >>>> @@ -472,13 +471,11 @@
>> >> >>>>                         st,syscon = <&syscfg 0x4>;
>> >> >>>>                         snps,pbl = <8>;
>> >> >>>>                         snps,mixed-burst;
>> >> >>>> -                       dma-ranges;
>> >> >>>>                         status = "disabled";
>> >> >>>>                 };
>> >> >>>>
>> >> >>>>                 usbotg_hs: usb at 40040000 {
>> >> >>>>                         compatible = "snps,dwc2";
>> >> >>>> -                       dma-ranges;
>> >> >>>>                         reg = <0x40040000 0x40000>;
>> >> >>>>                         interrupts = <77>;
>> >> >>>>                         clocks = <&rcc 0 29>;
>> >> >>>>
>> >> >>>>
>> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >>>>> b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >>>>> index 0596d60..3a1cfdd 100644
>> >> >>>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >>>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >>>>> @@ -59,8 +59,6 @@
>> >> >>>>>         };
>> >> >>>>>
>> >> >>>>>         soc {
>> >> >>>>> -               dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >>>>> -
>> >> >>>>>                 timer2: timer at 40000000 {
>> >> >>>>>                         compatible = "st,stm32-timer";
>> >> >>>>>                         reg = <0x40000000 0x400>;
>> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >>>>> b/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >>>>> index 9e73656..c2213c0 100644
>> >> >>>>> --- a/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >>>>> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >>>>> @@ -64,6 +64,10 @@
>> >> >>>>>         aliases {
>> >> >>>>>                 serial0 = &usart3;
>> >> >>>>>         };
>> >> >>>>> +
>> >> >>>>> +       soc {
>> >> >>>>> +               dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >>>>> +       };
>> >> >>>>>  };
>> >> >>>>>
>> >> >>>>>  &clk_hse {
>> >> >>>>> --
>> >> >>>>
>> >> >>>>
>> >> >>>>
>> >> >>>>
>> >> >>>> Br.,
>> >> >>>> Bruno
>> >> >>>>
>> >> >>>
>> >> >
>> >>
>> >> _______________________________________________
>> >> linux-arm-kernel mailing list
>> >> linux-arm-kernel at lists.infradead.org
>> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> >
>> >
>
>
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