* [PATCH 11/12] ARM: dts: sk-rzg1e: add Ether support
From: Geert Uytterhoeven @ 2016-11-02 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1653044.nY120UqMZW@wasted.cogentembedded.com>
On Sat, Oct 29, 2016 at 12:31 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the SK-RZG1E board dependent part of the Ether device node.
> Enable DHCP and NFS root for the kernel booting.
>
> Based on the original (and large) patch by Dmitry Shifrin
> <dmitry.shifrin@cogentembedded.com>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject is off-by-one (the series has only 11 patches)
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [RFC PATCH v2 2/5] net: phy: Add Meson GXL Internal PHY driver
From: Neil Armstrong @ 2016-11-02 10:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161031190558.GK9441@lunn.ch>
On 10/31/2016 08:05 PM, Andrew Lunn wrote:
> On Mon, Oct 31, 2016 at 05:56:24PM +0100, Neil Armstrong wrote:
>> Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs.
>>
>> This PHY seems to only implement some standard registers and need some
>> workarounds to provide autoneg values from vendor registers.
>>
>> Some magic values are currently used to configure the PHY, and this a
>> temporary setup until clarification about these registers names and
>> registers fields are provided by Amlogic.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> drivers/net/phy/Kconfig | 5 +++
>> drivers/net/phy/Makefile | 1 +
>> drivers/net/phy/meson-gxl.c | 81 +++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 87 insertions(+)
>> create mode 100644 drivers/net/phy/meson-gxl.c
>>
>> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
>> index 2651c8d..09342b6 100644
>> --- a/drivers/net/phy/Kconfig
>> +++ b/drivers/net/phy/Kconfig
>> @@ -226,6 +226,11 @@ config DP83867_PHY
>> ---help---
>> Currently supports the DP83867 PHY.
>>
>> +config MESON_GXL_PHY
>> + tristate "Amlogic Meson GXL Internal PHY"
>> + ---help---
>> + Currently has a driver for the Amlogic Meson GXL Internal PHY
>> +
>
> Hi Neil
>
> Please keep them in alphabetic order. This goes after Marvell.
>
>> config FIXED_PHY
>> tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
>> depends on PHYLIB
>> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
>> index e58667d..1511b3e 100644
>> --- a/drivers/net/phy/Makefile
>> +++ b/drivers/net/phy/Makefile
>> @@ -44,6 +44,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
>> obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
>> obj-$(CONFIG_MICREL_PHY) += micrel.o
>> obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
>> +obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
>> obj-$(CONFIG_MICROSEMI_PHY) += mscc.o
>
> Again, alphabetic order.
>
> Andrew
>
Sorry, rebase issue.
Neil
^ permalink raw reply
* [PATCH v4 1/1] clk: mvebu: migrate CP110 system controller to clk_hw API and registration
From: Marcin Wojtas @ 2016-11-02 10:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102003750.GL16026@codeaurora.org>
Thanks!
2016-11-02 1:37 GMT+01:00 Stephen Boyd <sboyd@codeaurora.org>:
> On 09/25, Marcin Wojtas wrote:
>> Now that we have clk_hw based provider APIs to register clks, we
>> can get rid of struct clk pointers while registering clks in Armada
>> CP110 system controller driver. This commit introduces new
>> API and registration for all clocks in CP110 HW blocks.
>>
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> ---
>
> Applied to clk-next
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] iommu: arm-smmu: Set SMTNMB_TLBEN in ACR to enable caching of bypass entries
From: Robin Murphy @ 2016-11-02 11:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478093714-17219-1-git-send-email-nipun.gupta@nxp.com>
Hi Nipun,
On 02/11/16 13:35, Nipun Gupta wrote:
> The SMTNMB_TLBEN in the Auxiliary Configuration Register (ACR) provides an
> option to enable the updation of TLB in case of bypass transactions due to
> no stream match in the stream match table. This reduces the latencies of
> the subsequent transactions with the same stream-id which bypasses the SMMU.
> This provides a significant performance benefit for certain networking
> workloads.
...at the cost of increased TLB contention against other workloads.
However, in the general case we'd expect the system to be fully
described, so if there aren't any unmatched Stream IDs there hopefully
shouldn't be an impact to leaving this switched on. I'd be interested to
see some actual performance numbers, though - you already know my
opinion about unsubstantiated quotes from the MMU-500 TRM.
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> ---
> drivers/iommu/arm-smmu.c | 21 +++++++++++++++------
> 1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index ce2a9d4..7010a5c 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -246,6 +246,7 @@ enum arm_smmu_s2cr_privcfg {
>
> #define ARM_MMU500_ACTLR_CPRE (1 << 1)
>
> +#define ACR_SMTNMB_TLBEN (1 << 8)
ACR is entirely implementation-defined, so there are no generic field
names. Please follow the naming convention handily demonstrated in the
subsequent context line.
> #define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
Actually, can we also please keep these in descending order of bit
position like everything else?
> #define CB_PAR_F (1 << 0)
> @@ -1569,18 +1570,26 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
> for (i = 0; i < smmu->num_mapping_groups; ++i)
> arm_smmu_write_sme(smmu, i);
>
> + /* Get the major rev required for configuring ACR */
That comment is nonsense.
> + reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
> + major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
> +
> /*
> * Before clearing ARM_MMU500_ACTLR_CPRE, need to
> * clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
> * bit is only present in MMU-500r2 onwards.
> */
> - reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
> - major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
> - if ((smmu->model == ARM_MMU500) && (major >= 2)) {
> - reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
> + reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
> + if ((smmu->model == ARM_MMU500) && (major >= 2))
> reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
> - writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
> - }
> +
> + /*
> + * Set the SMTNMB_TLBEN in ACR so that the transactions which
> + * bypass with SMMU due to no stream match found in the SMR table
> + * are updated in the TLB's.
Or simply, e.g. "Allow unmatched Stream IDs to allocate bypass TLB
entries for reduced latency". It's already clear from the code what
bit's being set where, we only need to remember *why*.
> + */
> + reg |= ACR_SMTNMB_TLBEN;
> + writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
Are you sure it's perfectly fine to set that implementation-defined bit
on any SMMU implementation other than the two-and-a-half ARM Ltd. ones
which happen to share the same meaning? I'm certainly not.
The correct flow would be something like this:
if (smmu->model == ARM_MMU500) {
reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
if (major >= 2)
reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
reg |= ACR_SMTNMB_TLBEN;
writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
}
The shape of the current code avoids an extra level of indentation, but
once you have to have the nested conditional anyway, it might as well
all be predicated appropriately.
Robin.
> /* Make sure all context banks are disabled and clear CB_FSR */
> for (i = 0; i < smmu->num_context_banks; ++i) {
>
^ permalink raw reply
* [PATCH v1 0/6] Support GICv3 ITS in 32-bit mode
From: Vladimir Murzin @ 2016-11-02 11:54 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series introduces GICv3 ITS to 32-bit world. Since I'm limited
with real world 32-bit platforms which uses ITS it was tested with
help of vITS on 64-bit host running 32-bit guest.
I used Andrea's its/v8 branch at [1] with following option passed to
kvmtool: --aarch32 --irqchip=gicv3-its --force-pci
[1] git://www.linux-arm.org/kvmtool.git
Changelog:
RFC -> v1
- rebased on 4.9-rc2, gits_read_typer() has been dropped
- spilt ITS and vITS in separate patch sets
Vladimir Murzin (6):
irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility
irqchip/gic-v3-its: Narrow down Entry Size when used as a divider
irqchip/gicv3-its: Specialise flush_dcache operation
irqchip/gicv3-its: Specialise readq and writeq accesses
ARM: gic-v3-its: Add 32bit support to GICv3 ITS
ARM: virt: Select ARM_GIC_V3_ITS
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arch_gicv3.h | 54 +++++++++++++++++++++----
arch/arm64/include/asm/arch_gicv3.h | 17 ++++++++
drivers/irqchip/irq-gic-v3-its.c | 75 +++++++++++++++++------------------
include/linux/irqchip/arm-gic-v3.h | 4 +-
5 files changed, 104 insertions(+), 47 deletions(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH v1 1/6] irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility
From: Vladimir Murzin @ 2016-11-02 11:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478087648-5346-1-git-send-email-vladimir.murzin@arm.com>
Make sure that constants which are supposed to be applied on 64-bit
data is actually unsigned long long, so they won't be truncated when
used in 32-bit mode.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 28 ++++++++++++++--------------
include/linux/irqchip/arm-gic-v3.h | 4 ++--
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index c5dee30..bca125e 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -196,7 +196,7 @@ struct its_cmd_block {
static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
{
- cmd->raw_cmd[0] &= ~0xffUL;
+ cmd->raw_cmd[0] &= ~0xffULL;
cmd->raw_cmd[0] |= cmd_nr;
}
@@ -208,43 +208,43 @@ static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
{
- cmd->raw_cmd[1] &= ~0xffffffffUL;
+ cmd->raw_cmd[1] &= ~0xffffffffULL;
cmd->raw_cmd[1] |= id;
}
static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
{
- cmd->raw_cmd[1] &= 0xffffffffUL;
+ cmd->raw_cmd[1] &= 0xffffffffULL;
cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
}
static void its_encode_size(struct its_cmd_block *cmd, u8 size)
{
- cmd->raw_cmd[1] &= ~0x1fUL;
+ cmd->raw_cmd[1] &= ~0x1fULL;
cmd->raw_cmd[1] |= size & 0x1f;
}
static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
{
- cmd->raw_cmd[2] &= ~0xffffffffffffUL;
- cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
+ cmd->raw_cmd[2] &= ~0xffffffffffffULL;
+ cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00ULL;
}
static void its_encode_valid(struct its_cmd_block *cmd, int valid)
{
- cmd->raw_cmd[2] &= ~(1UL << 63);
+ cmd->raw_cmd[2] &= ~(1ULL << 63);
cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
}
static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
{
- cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
- cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
+ cmd->raw_cmd[2] &= ~(0xffffffffULL << 16);
+ cmd->raw_cmd[2] |= (target_addr & (0xffffffffULL << 16));
}
static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
{
- cmd->raw_cmd[2] &= ~0xffffUL;
+ cmd->raw_cmd[2] &= ~0xffffULL;
cmd->raw_cmd[2] |= col;
}
@@ -657,8 +657,8 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
its = its_dev->its;
addr = its->phys_base + GITS_TRANSLATER;
- msg->address_lo = addr & ((1UL << 32) - 1);
- msg->address_hi = addr >> 32;
+ msg->address_lo = lower_32_bits(addr);
+ msg->address_hi = upper_32_bits(addr);
msg->data = its_get_event_id(d);
iommu_dma_map_msi_msg(d->irq, msg);
@@ -935,9 +935,9 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
}
if (val != tmp) {
- pr_err("ITS@%pa: %s doesn't stick: %lx %lx\n",
+ pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
&its->phys_base, its_base_type_string[type],
- (unsigned long) val, (unsigned long) tmp);
+ val, tmp);
free_pages((unsigned long)base, order);
return -ENXIO;
}
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index b7e3431..5118d3a 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -239,7 +239,7 @@
#define GITS_TYPER_PTA (1UL << 19)
#define GITS_TYPER_HWCOLLCNT_SHIFT 24
-#define GITS_CBASER_VALID (1UL << 63)
+#define GITS_CBASER_VALID (1ULL << 63)
#define GITS_CBASER_SHAREABILITY_SHIFT (10)
#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
@@ -265,7 +265,7 @@
#define GITS_BASER_NR_REGS 8
-#define GITS_BASER_VALID (1UL << 63)
+#define GITS_BASER_VALID (1ULL << 63)
#define GITS_BASER_INDIRECT (1ULL << 62)
#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
--
1.7.9.5
^ permalink raw reply related
* [PATCH v1 2/6] irqchip/gic-v3-its: Narrow down Entry Size when used as a divider
From: Vladimir Murzin @ 2016-11-02 11:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478087648-5346-1-git-send-email-vladimir.murzin@arm.com>
GITS_BASER<n>'s Entry Size is much smaller than 64-bit, but when it
used as a divider it forces compiler to generate __aeabi_uldivmod if
build in 32-bit mode. So, casting it to int (like it is done in other
places) where used as a divider would give a hint to compiler that
32-bit division can be used.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index bca125e..312dd55 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -948,7 +948,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
- &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / tmp),
+ &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
its_base_type_string[type],
(unsigned long)virt_to_phys(base),
indirect ? "indirect" : "flat", (int)esz,
@@ -983,7 +983,7 @@ static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser
* which is reported by ITS hardware times lvl1 table
* entry size.
*/
- ids -= ilog2(psz / esz);
+ ids -= ilog2(psz / (int)esz);
esz = GITS_LVL1_ENTRY_SIZE;
}
}
@@ -998,7 +998,7 @@ static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser
new_order = max_t(u32, get_order(esz << ids), new_order);
if (new_order >= MAX_ORDER) {
new_order = MAX_ORDER - 1;
- ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / esz);
+ ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n",
&its->phys_base, its->device_ids, ids);
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH v1 3/6] irqchip/gicv3-its: Specialise flush_dcache operation
From: Vladimir Murzin @ 2016-11-02 11:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478087648-5346-1-git-send-email-vladimir.murzin@arm.com>
It'd be better to switch to CMA... but before that done redirect
flush_dcache operation, so 32-bit implementation could be wired
latter.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm64/include/asm/arch_gicv3.h | 3 +++
drivers/irqchip/irq-gic-v3-its.c | 17 ++++++++---------
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index f8ae6d6..4f0402a 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -79,6 +79,7 @@
#include <linux/stringify.h>
#include <asm/barrier.h>
+#include <asm/cacheflush.h>
#define read_gicreg(r) \
({ \
@@ -187,5 +188,7 @@ static inline void gic_write_bpr1(u32 val)
#define gic_read_typer(c) readq_relaxed(c)
#define gic_write_irouter(v, c) writeq_relaxed(v, c)
+#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_GICV3_H */
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 312dd55..b2a6e7b 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -37,7 +37,6 @@
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic-v3.h>
-#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/exception.h>
@@ -433,7 +432,7 @@ static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
* the ITS.
*/
if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
- __flush_dcache_area(cmd, sizeof(*cmd));
+ gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
else
dsb(ishst);
}
@@ -602,7 +601,7 @@ static void lpi_set_config(struct irq_data *d, bool enable)
* Humpf...
*/
if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
- __flush_dcache_area(cfg, sizeof(*cfg));
+ gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
else
dsb(ishst);
its_send_inv(its_dev, id);
@@ -817,7 +816,7 @@ static int __init its_alloc_lpi_tables(void)
LPI_PROPBASE_SZ);
/* Make sure the GIC will observe the written configuration */
- __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
+ gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
return 0;
}
@@ -910,7 +909,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
shr = tmp & GITS_BASER_SHAREABILITY_MASK;
if (!shr) {
cache = GITS_BASER_nC;
- __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order));
+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
}
goto retry_baser;
}
@@ -1102,7 +1101,7 @@ static void its_cpu_init_lpis(void)
}
/* Make sure the GIC will observe the zero-ed page */
- __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
+ gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
paddr = page_to_phys(pend_page);
pr_info("CPU%d: using LPI pending table @%pa\n",
@@ -1287,13 +1286,13 @@ static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
/* Flush Lvl2 table to PoC if hw doesn't support coherency */
if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
- __flush_dcache_area(page_address(page), baser->psz);
+ gic_flush_dcache_to_poc(page_address(page), baser->psz);
table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
/* Flush Lvl1 entry to PoC if hw doesn't support coherency */
if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
- __flush_dcache_area(table + idx, GITS_LVL1_ENTRY_SIZE);
+ gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
/* Ensure updated table contents are visible to ITS hardware */
dsb(sy);
@@ -1340,7 +1339,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
return NULL;
}
- __flush_dcache_area(itt, sz);
+ gic_flush_dcache_to_poc(itt, sz);
dev->its = its;
dev->itt = itt;
--
1.7.9.5
^ permalink raw reply related
* [PATCH v1 4/6] irqchip/gicv3-its: Specialise readq and writeq accesses
From: Vladimir Murzin @ 2016-11-02 11:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478087648-5346-1-git-send-email-vladimir.murzin@arm.com>
readq and writeq type of assessors are not supported in AArch32, so we
need to specialise them and glue later with series of 32-bit accesses
on AArch32 side.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm64/include/asm/arch_gicv3.h | 14 ++++++++++++++
drivers/irqchip/irq-gic-v3-its.c | 24 ++++++++++++------------
2 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 4f0402a..022523b 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -190,5 +190,19 @@ static inline void gic_write_bpr1(u32 val)
#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
+#define gits_read_baser(c) readq_relaxed(c)
+#define gits_write_baser(v, c) writeq_relaxed(v, c)
+
+#define gits_read_cbaser(c) readq_relaxed(c)
+#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
+
+#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
+
+#define gicr_read_propbaser(c) readq_relaxed(c)
+#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
+
+#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
+#define gicr_read_pendbaser(c) readq_relaxed(c)
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_GICV3_H */
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index b2a6e7b..69b040f 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -835,7 +835,7 @@ static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
{
u32 idx = baser - its->tables;
- return readq_relaxed(its->base + GITS_BASER + (idx << 3));
+ return gits_read_baser(its->base + GITS_BASER + (idx << 3));
}
static void its_write_baser(struct its_node *its, struct its_baser *baser,
@@ -843,7 +843,7 @@ static void its_write_baser(struct its_node *its, struct its_baser *baser,
{
u32 idx = baser - its->tables;
- writeq_relaxed(val, its->base + GITS_BASER + (idx << 3));
+ gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
baser->val = its_read_baser(its, baser);
}
@@ -1125,8 +1125,8 @@ static void its_cpu_init_lpis(void)
GICR_PROPBASER_WaWb |
((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
- writeq_relaxed(val, rbase + GICR_PROPBASER);
- tmp = readq_relaxed(rbase + GICR_PROPBASER);
+ gicr_write_propbaser(val, rbase + GICR_PROPBASER);
+ tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
@@ -1138,7 +1138,7 @@ static void its_cpu_init_lpis(void)
val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
GICR_PROPBASER_CACHEABILITY_MASK);
val |= GICR_PROPBASER_nC;
- writeq_relaxed(val, rbase + GICR_PROPBASER);
+ gicr_write_propbaser(val, rbase + GICR_PROPBASER);
}
pr_info_once("GIC: using cache flushing for LPI property table\n");
gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
@@ -1149,8 +1149,8 @@ static void its_cpu_init_lpis(void)
GICR_PENDBASER_InnerShareable |
GICR_PENDBASER_WaWb);
- writeq_relaxed(val, rbase + GICR_PENDBASER);
- tmp = readq_relaxed(rbase + GICR_PENDBASER);
+ gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
+ tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
/*
@@ -1160,7 +1160,7 @@ static void its_cpu_init_lpis(void)
val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
GICR_PENDBASER_CACHEABILITY_MASK);
val |= GICR_PENDBASER_nC;
- writeq_relaxed(val, rbase + GICR_PENDBASER);
+ gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
}
/* Enable LPIs */
@@ -1716,8 +1716,8 @@ static int __init its_probe_one(struct resource *res,
(ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
GITS_CBASER_VALID);
- writeq_relaxed(baser, its->base + GITS_CBASER);
- tmp = readq_relaxed(its->base + GITS_CBASER);
+ gits_write_cbaser(baser, its->base + GITS_CBASER);
+ tmp = gits_read_cbaser(its->base + GITS_CBASER);
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
@@ -1729,13 +1729,13 @@ static int __init its_probe_one(struct resource *res,
baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
GITS_CBASER_CACHEABILITY_MASK);
baser |= GITS_CBASER_nC;
- writeq_relaxed(baser, its->base + GITS_CBASER);
+ gits_write_cbaser(baser, its->base + GITS_CBASER);
}
pr_info("ITS: using cache flushing for cmd queue\n");
its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
}
- writeq_relaxed(0, its->base + GITS_CWRITER);
+ gits_write_cwriter(0, its->base + GITS_CWRITER);
writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
err = its_init_domain(handle, its);
--
1.7.9.5
^ permalink raw reply related
* [PATCH v1 5/6] ARM: gic-v3-its: Add 32bit support to GICv3 ITS
From: Vladimir Murzin @ 2016-11-02 11:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478087648-5346-1-git-send-email-vladimir.murzin@arm.com>
Wire-up flush_dcache, readq- and writeq-like gic-v3-its assessors, so
GICv3 ITS gets all it needs to be built and run.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm/include/asm/arch_gicv3.h | 54 ++++++++++++++++++++++++++++++++-----
1 file changed, 47 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index a808829..2747590 100644
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <asm/barrier.h>
+#include <asm/cacheflush.h>
#include <asm/cp15.h>
#define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
@@ -230,19 +231,14 @@ static inline void gic_write_bpr1(u32 val)
* AArch32, since the syndrome register doesn't provide any information for
* them.
* Consequently, the following IO helpers use 32bit accesses.
- *
- * There are only two registers that need 64bit accesses in this driver:
- * - GICD_IROUTERn, contain the affinity values associated to each interrupt.
- * The upper-word (aff3) will always be 0, so there is no need for a lock.
- * - GICR_TYPER is an ID register and doesn't need atomicity.
*/
-static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)
+static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
{
writel_relaxed((u32)val, addr);
writel_relaxed((u32)(val >> 32), addr + 4);
}
-static inline u64 gic_read_typer(const volatile void __iomem *addr)
+static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
{
u64 val;
@@ -251,5 +247,49 @@ static inline u64 gic_read_typer(const volatile void __iomem *addr)
return val;
}
+#define gic_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
+
+/*
+ * GICD_IROUTERn, contain the affinity values associated to each interrupt.
+ * The upper-word (aff3) will always be 0, so there is no need for a lock.
+ */
+#define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c)
+
+/*
+ * GICR_TYPER is an ID register and doesn't need atomicity.
+ */
+#define gic_read_typer(c) __gic_readq_nonatomic(c)
+
+/*
+ * GITS_BASER - hi and lo bits may be accessed independently.
+ */
+#define gits_read_baser(c) __gic_readq_nonatomic(c)
+#define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c)
+
+/*
+ * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
+ * won't be being used during any updates and can be changed non-atomically
+ */
+#define gicr_read_propbaser(c) __gic_readq_nonatomic(c)
+#define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c)
+#define gicr_read_pendbaser(c) __gic_readq_nonatomic(c)
+#define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c)
+
+/*
+ * GITS_TYPER is an ID register and doesn't need atomicity.
+ */
+#define gits_read_typer(c) __gic_readq_nonatomic(c)
+
+/*
+ * GITS_CBASER - hi and lo bits may be accessed independently.
+ */
+#define gits_read_cbaser(c) __gic_readq_nonatomic(c)
+#define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c)
+
+/*
+ * GITS_CWRITER - hi and lo bits may be accessed independently.
+ */
+#define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c)
+
#endif /* !__ASSEMBLY__ */
#endif /* !__ASM_ARCH_GICV3_H */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v1 6/6] ARM: virt: Select ARM_GIC_V3_ITS
From: Vladimir Murzin @ 2016-11-02 11:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478087648-5346-1-git-send-email-vladimir.murzin@arm.com>
This patch allows ARM guests to use GICv3 ITS on an arm64 host
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b5d529f..caef684 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -703,6 +703,7 @@ config ARCH_VIRT
select ARM_GIC
select ARM_GIC_V2M if PCI
select ARM_GIC_V3
+ select ARM_GIC_V3_ITS if PCI
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/3] fix ohci phy name
From: Axel Haslam @ 2016-11-02 12:44 UTC (permalink / raw)
To: linux-arm-kernel
The usb ohci clock match is not working because the usb clock
is registered as "ohci" instead of "ohci.0"
But since there is only a single ohci instance, lets pass -1 to
the platform data id parameter and avoid the extra ".0" matching.
while we are fixing this, rename the driver to "ohci-da8xx" to be
consistent with davinci musb and other usb drivers.
Axel Haslam (3):
ARM: davinci: da8xx: Fix ohci driver name
phy: da8xx-usb: rename the ohci device to ohci-da8xx
usb: ohci-da8xx: rename driver to ohci-da8xx
arch/arm/mach-davinci/da830.c | 2 +-
arch/arm/mach-davinci/da850.c | 2 +-
arch/arm/mach-davinci/da8xx-dt.c | 2 +-
arch/arm/mach-davinci/usb-da8xx.c | 4 ++--
drivers/phy/phy-da8xx-usb.c | 5 +++--
drivers/usb/host/ohci-da8xx.c | 2 +-
6 files changed, 9 insertions(+), 8 deletions(-)
--
2.10.1
^ permalink raw reply
* [PATCH 1/3] ARM: davinci: da8xx: Fix ohci driver name
From: Axel Haslam @ 2016-11-02 12:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102124435.31777-1-ahaslam@baylibre.com>
There is a single instance of the ohci driver,
while the clk lookup table is making reference to "ohci"
other subsystems (such as phy) are looking for "ohci.0"
Since there is a single ohci instance, change the dev id
to -1, and add the "-da8xx" for consitancy with the musb
driver name.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
---
arch/arm/mach-davinci/da830.c | 2 +-
arch/arm/mach-davinci/da850.c | 2 +-
arch/arm/mach-davinci/da8xx-dt.c | 2 +-
arch/arm/mach-davinci/usb-da8xx.c | 4 ++--
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 41459bd..073c458 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -420,7 +420,7 @@ static struct clk_lookup da830_clks[] = {
CLK("davinci_mdio.0", "fck", &emac_clk),
CLK(NULL, "gpio", &gpio_clk),
CLK("i2c_davinci.2", NULL, &i2c1_clk),
- CLK("ohci", "usb11", &usb11_clk),
+ CLK("ohci-da8xx", "usb11", &usb11_clk),
CLK(NULL, "emif3", &emif3_clk),
CLK(NULL, "arm", &arm_clk),
CLK(NULL, "rmii", &rmii_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 196e262..3961556 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -503,7 +503,7 @@ static struct clk_lookup da850_clks[] = {
CLK("da830-mmc.1", NULL, &mmcsd1_clk),
CLK("ti-aemif", NULL, &aemif_clk),
CLK(NULL, "aemif", &aemif_clk),
- CLK("ohci", "usb11", &usb11_clk),
+ CLK("ohci-da8xx", "usb11", &usb11_clk),
CLK("musb-da8xx", "usb20", &usb20_clk),
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 92ae093..2afb067 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -39,7 +39,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL),
OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", NULL),
OF_DEV_AUXDATA("ti,da850-tilcdc", 0x01e13000, "da8xx_lcdc.0", NULL),
- OF_DEV_AUXDATA("ti,da830-ohci", 0x01e25000, "ohci", NULL),
+ OF_DEV_AUXDATA("ti,da830-ohci", 0x01e25000, "ohci-da8xx", NULL),
OF_DEV_AUXDATA("ti,da830-musb", 0x01e00000, "musb-da8xx", NULL),
OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL),
{}
diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
index b010e5f..c6feecf 100644
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ b/arch/arm/mach-davinci/usb-da8xx.c
@@ -109,8 +109,8 @@ static struct resource da8xx_usb11_resources[] = {
static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32);
static struct platform_device da8xx_usb11_device = {
- .name = "ohci",
- .id = 0,
+ .name = "ohci-da8xx",
+ .id = -1,
.dev = {
.dma_mask = &da8xx_usb11_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
--
2.10.1
^ permalink raw reply related
* [PATCH 2/3] phy: da8xx-usb: rename the ohci device to ohci-da8xx
From: Axel Haslam @ 2016-11-02 12:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102124435.31777-1-ahaslam@baylibre.com>
There is only one ohci on the da8xx series of chips,
so remove the ".0" when creating the phy. Also add
the "-da8xx" postfix to be consistent across davinci
usb drivers.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
---
drivers/phy/phy-da8xx-usb.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c
index 32ae78c..c85fb0b 100644
--- a/drivers/phy/phy-da8xx-usb.c
+++ b/drivers/phy/phy-da8xx-usb.c
@@ -198,7 +198,8 @@ static int da8xx_usb_phy_probe(struct platform_device *pdev)
} else {
int ret;
- ret = phy_create_lookup(d_phy->usb11_phy, "usb-phy", "ohci.0");
+ ret = phy_create_lookup(d_phy->usb11_phy, "usb-phy",
+ "ohci-da8xx");
if (ret)
dev_warn(dev, "Failed to create usb11 phy lookup\n");
ret = phy_create_lookup(d_phy->usb20_phy, "usb-phy",
@@ -216,7 +217,7 @@ static int da8xx_usb_phy_remove(struct platform_device *pdev)
if (!pdev->dev.of_node) {
phy_remove_lookup(d_phy->usb20_phy, "usb-phy", "musb-da8xx");
- phy_remove_lookup(d_phy->usb11_phy, "usb-phy", "ohci.0");
+ phy_remove_lookup(d_phy->usb11_phy, "usb-phy", "ohci-da8xx");
}
return 0;
--
2.10.1
^ permalink raw reply related
* [PATCH 3/3] usb: ohci-da8xx: rename driver to ohci-da8xx
From: Axel Haslam @ 2016-11-02 12:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102124435.31777-1-ahaslam@baylibre.com>
To be consistent on the usb driver for the davinci
platform follow the example of musb, and add the
"-da8xx" postfix to the driver name.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
---
drivers/usb/host/ohci-da8xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
index bd6cf3c..b3de8bc 100644
--- a/drivers/usb/host/ohci-da8xx.c
+++ b/drivers/usb/host/ohci-da8xx.c
@@ -27,7 +27,7 @@
#include "ohci.h"
#define DRIVER_DESC "DA8XX"
-#define DRV_NAME "ohci"
+#define DRV_NAME "ohci-da8xx"
static struct hc_driver __read_mostly ohci_da8xx_hc_driver;
--
2.10.1
^ permalink raw reply related
* [PATCH 0/5] ARM: OMAP: dead code removal
From: Joshua Clayton @ 2016-11-02 12:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478000206-10855-1-git-send-email-Nicolae_Rosia@mentor.com>
On Tuesday, November 01, 2016 01:36:41 PM Nicolae Rosia wrote:
> Hi,
>
> I have identified some dead code which can be removed.
>
> Nicolae Rosia (5):
> ARM: OMAP4: kill omap4_pmic_init and omap4_pmic_get_config
> ARM: OMAP3: kill omap3_pmic_get_config and twl_{get,set}_voltage
> ARM: OMAP3: kill omap3_pmic_init
> ARM: OMAP2: kill omap2_pmic_init
> ARM: OMAP: kill omap_pmic_init
>
> arch/arm/mach-omap2/twl-common.c | 483 ---------------------------------------
> arch/arm/mach-omap2/twl-common.h | 24 --
> 2 files changed, 507 deletions(-)
>
>
I think the commit logs for these patches
need a little detail on why the code is
no longer needed. For posterity.
^ permalink raw reply
* [PATCH -next] [media] c8sectpfe: fix error return code in c8sectpfe_probe()
From: Patrice Chotard @ 2016-11-02 13:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477792390-24533-1-git-send-email-weiyj.lk@gmail.com>
On 10/30/2016 02:53 AM, Wei Yongjun wrote:
> From: Wei Yongjun <weiyongjun1@huawei.com>
>
> Fix to return error code -ENODEV from the error handling
> case instead of 0, as done elsewhere in this function.
>
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
> ---
> drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c b/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c
> index 42b123f..69d9a16 100644
> --- a/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c
> +++ b/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c
> @@ -813,6 +813,7 @@ static int c8sectpfe_probe(struct platform_device *pdev)
> i2c_bus = of_parse_phandle(child, "i2c-bus", 0);
> if (!i2c_bus) {
> dev_err(&pdev->dev, "No i2c-bus found\n");
> + ret = -ENODEV;
> goto err_clk_disable;
> }
> tsin->i2c_adapter =
> @@ -820,6 +821,7 @@ static int c8sectpfe_probe(struct platform_device *pdev)
> if (!tsin->i2c_adapter) {
> dev_err(&pdev->dev, "No i2c adapter found\n");
> of_node_put(i2c_bus);
> + ret = -ENODEV;
> goto err_clk_disable;
> }
> of_node_put(i2c_bus);
>
Hi Wei
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Thanks
^ permalink raw reply
* [PATCH 1/3] ipmi/bt-bmc: change compatible node to 'aspeed, ast2400-ibt-bmc'
From: Arnd Bergmann @ 2016-11-02 13:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478073426-3714-2-git-send-email-clg@kaod.org>
On Wednesday 02 November 2016, C?dric Le Goater wrote:
> The Aspeed SoCs have two BT interfaces : one is IPMI compliant and the
> other is H8S/2168 compliant.
>
> The current ipmi/bt-bmc driver implements the IPMI version and we
> should reflect its nature in the compatible node name using
> 'aspeed,ast2400-ibt-bmc' instead of 'aspeed,ast2400-bt-bmc'. The
> latter should be used for a H8S interface driver if it is implemented
> one day.
>
> Signed-off-by: C?dric Le Goater <clg@kaod.org>
We generally try to avoid changing the compatible strings after the
fact, but it's probably ok in this case.
I don't understand who decides which of the two interfaces is used:
is it the same register set that can be driven by either one or the
other driver, or do you expect to have two drivers that can both
be active in the same system and talk to different hardware once
you get there?
If the first one of these is true, it seems a little awkward to
use the DT compatible string to decide which driver to use rather
than making the decision in the OS.
Arnd
^ permalink raw reply
* [PATCH 3/5] ARM: multi_v7_defconfig: Remove CONFIG_ST_THERMAL_MEMMAP Kconfig symbol
From: Patrice Chotard @ 2016-11-02 13:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161024101408.GA10440@griffinp-ThinkPad-X1-Carbon-2nd>
On 10/24/2016 12:14 PM, Peter Griffin wrote:
> Hi Patrice,
>
> On Fri, 21 Oct 2016, patrice.chotard at st.com wrote:
>
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> Driver code has been already removed, see
>> http://www.spinics.net/lists/devicetree/msg143322.html
>> Remove the multi_v7_defconfig part
>>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> Cc: <rui.zhang@intel.com>
>> Cc: <edubezval@gmail.com>
>> ---
>> arch/arm/configs/multi_v7_defconfig | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
>> index 15b2f99..45e252b 100644
>> --- a/arch/arm/configs/multi_v7_defconfig
>> +++ b/arch/arm/configs/multi_v7_defconfig
>> @@ -450,7 +450,6 @@ CONFIG_RCAR_THERMAL=y
>> CONFIG_ARMADA_THERMAL=y
>> CONFIG_DAVINCI_WATCHDOG=m
>> CONFIG_EXYNOS_THERMAL=m
>> -CONFIG_ST_THERMAL_MEMMAP=y
>
Hi Peter
> Are you sure you want to remove this?
Well spotted, you are right. It must be kept.
Thanks
>
> This Kconfig symbol is still used for the stih407 family
> thermal parts in drivers/thermal/st/st_thermal_memmap.c?
>
> My patch only removed the stih415/6 parts from the driver.
>
> regards,
>
> Peter.
>
^ permalink raw reply
* flush_dcache_page() in ARM vs ARM64
From: Rabin Vincent @ 2016-11-02 13:27 UTC (permalink / raw)
To: linux-arm-kernel
ARMv7-A and ARMv8-A are, as far as I can see, identical in which cache
behaviours they support. The data cache has to behave as PIPT while for
the instruction cache, PIPT, VIPT, and ASIC-tagged VIVT behaviours are
supported. See section B3.11 of the ARMv7-A ARM and section D4.9 of the
ARMv8-A ARM.
Both ARMv7-A with Multiprocessing Extensions and ARMv8-A broadcast cache
maintenance operations to other cores. See B2.2.5 of the ARMv7-A ARM
and D7.2.57 of the ARMv8-A ARM.
Both arch/arm/ (for ARMv6+) and arch/arm64/ define PG_arch_1 to be
PG_dcache_clean and use it to postpone flushing from flush_dcache_page()
to set_pte_at(). See arch/{arm,arm64}/mm/flush.c.
However, arch/arm64/'s flush_dcache_page() is implemented like this:
void flush_dcache_page(struct page *page)
{
if (test_bit(PG_dcache_clean, &page->flags))
clear_bit(PG_dcache_clean, &page->flags);
}
while arch/arm/ has this:
void flush_dcache_page(struct page *page)
{
struct address_space *mapping;
/*
* The zero page is never written to, so never has any dirty
* cache lines, and therefore never needs to be flushed.
*/
if (page == ZERO_PAGE(0))
return;
mapping = page_mapping(page);
if (!cache_ops_need_broadcast() &&
mapping && !page_mapcount(page))
clear_bit(PG_dcache_clean, &page->flags);
else {
__flush_dcache_page(mapping, page);
if (mapping && cache_is_vivt())
__flush_dcache_aliases(mapping, page);
else if (mapping)
__flush_icache_all();
set_bit(PG_dcache_clean, &page->flags);
}
}
Why does arch/arm/ flush the data cache area in flush_dcache_page() for
the (!mapping || page_mapcount(page)) case even on ARMv7+ME, while
arch/arm64/ doesn't for ARMv8?
Why does arch/arm/ invalidate the instruction cache in
flush_dcache_page() for the (mapping && page_count(page)) case even for
ARMv7+ME, while arch/arm64/ doesn't for ARMv8?
What would break with the following patch?
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 3cced84..f1e6190 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -327,6 +327,12 @@ void flush_dcache_page(struct page *page)
if (page == ZERO_PAGE(0))
return;
+ if (!cache_ops_need_broadcast() && cache_is_vipt_nonaliasing()) {
+ if (test_bit(PG_dcache_clean, &page->flags))
+ clear_bit(PG_dcache_clean, &page->flags);
+ return;
+ }
+
mapping = page_mapping(page);
if (!cache_ops_need_broadcast() &&
^ permalink raw reply related
* [PATCH 0/3] ARM: dts: sun9i: Enable SDIO-based WiFi
From: Maxime Ripard @ 2016-11-02 13:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161028101154.7350-1-wens@csie.org>
On Fri, Oct 28, 2016 at 06:11:51PM +0800, Chen-Yu Tsai wrote:
> Hi Maxime,
>
> Now that we have support for both PMICs, we can turn on the
> regulators needed for the onboard WiFi chips.
>
> This is a fairly simple series. The WiFi chips themselves are
> supported by the brcmfmac driver, but the user needs to get an
> nvram.txt file and put it in their firmware directory, in
> addition to the firmware file in linux-firmware. Otherwise we
> just need to enable the mmc controller and supply the vmmc and
> vqmmc regulators.
Applied all three, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 0/3] ARM: dts: sun8i: Support NanoPi SBCs
From: Maxime Ripard @ 2016-11-02 13:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161028065903.23298-1-woogyom.kim@gmail.com>
On Fri, Oct 28, 2016 at 03:59:00PM +0900, Milo Kim wrote:
> NanoPi M1 and NEO have common features, so duplicate properties can be
> moved into new dtsi file.
Applied all three, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH] iommu: arm-smmu: Set SMTNMB_TLBEN in ACR to enable caching of bypass entries
From: Nipun Gupta @ 2016-11-02 13:35 UTC (permalink / raw)
To: linux-arm-kernel
The SMTNMB_TLBEN in the Auxiliary Configuration Register (ACR) provides an
option to enable the updation of TLB in case of bypass transactions due to
no stream match in the stream match table. This reduces the latencies of
the subsequent transactions with the same stream-id which bypasses the SMMU.
This provides a significant performance benefit for certain networking
workloads.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
drivers/iommu/arm-smmu.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index ce2a9d4..7010a5c 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -246,6 +246,7 @@ enum arm_smmu_s2cr_privcfg {
#define ARM_MMU500_ACTLR_CPRE (1 << 1)
+#define ACR_SMTNMB_TLBEN (1 << 8)
#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
#define CB_PAR_F (1 << 0)
@@ -1569,18 +1570,26 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
for (i = 0; i < smmu->num_mapping_groups; ++i)
arm_smmu_write_sme(smmu, i);
+ /* Get the major rev required for configuring ACR */
+ reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
+ major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
+
/*
* Before clearing ARM_MMU500_ACTLR_CPRE, need to
* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
* bit is only present in MMU-500r2 onwards.
*/
- reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
- major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
- if ((smmu->model == ARM_MMU500) && (major >= 2)) {
- reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
+ reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
+ if ((smmu->model == ARM_MMU500) && (major >= 2))
reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
- writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
- }
+
+ /*
+ * Set the SMTNMB_TLBEN in ACR so that the transactions which
+ * bypass with SMMU due to no stream match found in the SMR table
+ * are updated in the TLB's.
+ */
+ reg |= ACR_SMTNMB_TLBEN;
+ writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
/* Make sure all context banks are disabled and clear CB_FSR */
for (i = 0; i < smmu->num_context_banks; ++i) {
--
1.9.1
^ permalink raw reply related
* Tegra baseline test results for v4.9-rc1
From: Jon Hunter @ 2016-11-02 13:39 UTC (permalink / raw)
To: linux-arm-kernel
Here are some basic Tegra test results for Linux v4.9-rc1.
Logs and other details at:
https://nvtb.github.io//linux/test_v4.9-rc1/20161102045959/
Test summary
------------
Build: zImage:
FAIL: ( 1/ 2): multi_v7_defconfig
Pass: ( 1/ 2): tegra_defconfig
Build: Image:
Pass: ( 1/ 1): defconfig
Boot to userspace: defconfig:
Pass: ( 4/ 4): qemu-vexpress64, tegra132-norrin,
tegra210-p2371-0000, tegra210-smaug
Boot to userspace: tegra_defconfig:
Pass: ( 5/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra124-nyan-big, tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig:
FAIL: ( 5/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra124-nyan-big, tegra20-trimslice, tegra30-beaver
vmlinux object size
(delta in bytes from test_v4.8 (c8d2bc9bc39ebea8437fd974fdbc21847bb897a3)):
text data bss total kernel
-3007747 +3664344 +7816 +664413 defconfig
+69649 +14344 +3952 +87945 tegra_defconfig
Boot-time memory difference
(delta in bytes from test_v4.8 (c8d2bc9bc39ebea8437fd974fdbc21847bb897a3))
avail rsrvd high freed board kconfig dtb
-640k 640k . 64k qemu-vexpress64 defconfig __internal
-4k 4k . . tegra114-dalmore-a04 tegra_defconfig tegra114-dalmore
-4k 4k . . tegra124-jetson-tk1 tegra_defconfig tegra124-jetson-tk1
-96k 96k . . tegra132-norrin defconfig tegra132-norrin
-4k 4k . . tegra20-trimslice tegra_defconfig tegra20-trimslice
-660k 660k . 64k tegra210-p2371-0000 defconfig tegra210-p2371-0000
-664k 664k . 64k tegra210-smaug defconfig tegra210-smaug
-4k 4k . . tegra30-beaver tegra_defconfig tegra30-beaver
--
nvpublic
^ permalink raw reply
* [PATCH v2 4/4] spi: sun6i: Support Allwinner H3 SPI controller
From: Maxime Ripard @ 2016-11-02 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161028065412.23008-5-woogyom.kim@gmail.com>
On Fri, Oct 28, 2016 at 03:54:12PM +0900, Milo Kim wrote:
> H3 has two SPI controllers. The size of the buffer is 64 * 8.
> (8 bit transfer by 64 entry FIFO)
> A31 has four controllers. The size of the buffer is 128 * 8.
> (8 bit transfer by 128 entry FIFO)
>
> Register maps are sharable, so sun6i SPI driver is reusable with
> device configuration.
>
> Use the variable, 'fifo_depth' instead of fixed value to support both SPI
> controllers.
>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
> Cc: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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