* [PATCH v1 07/11] perf: hisi: Add support for Hisilicon SoC event counters
From: Anurup M @ 2016-11-02 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478101374-18778-1-git-send-email-anurup.m@huawei.com>
1. Hip05/06/07 uncore PMU to support different hardware
event counters.
2. Hisilicon PMU shall use the DJTAG hardware interface
to access hardware event counters and configuration
register.
3. Routines to initialize and setup PMU.
4. Routines to enable/disable/add/del/start/stop hardware
event counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M <anurup.m@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/perf/Makefile | 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/hisi_uncore_l3c.c | 571 +++++++++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_l3c.h | 67 ++++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 331 ++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 108 ++++++
6 files changed, 1079 insertions(+)
create mode 100644 drivers/perf/hisilicon/Makefile
create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c.h
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile
index b116e98..061f229 100644
--- a/drivers/perf/Makefile
+++ b/drivers/perf/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_ARM_PMU) += arm_pmu.o
obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
+obj-$(CONFIG_HISI_PMU) += hisilicon/
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
new file mode 100644
index 0000000..e1766cf
--- /dev/null
+++ b/drivers/perf/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c.c b/drivers/perf/hisilicon/hisi_uncore_l3c.c
new file mode 100644
index 0000000..f78f7b2
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c.c
@@ -0,0 +1,571 @@
+/*
+ * HiSilicon SoC L3C Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/bitmap.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/perf_event.h>
+#include "hisi_uncore_l3c.h"
+
+static inline int hisi_l3c_counter_valid(int idx)
+{
+ return (idx >= HISI_IDX_L3C_COUNTER0 &&
+ idx <= HISI_IDX_L3C_COUNTER_MAX);
+}
+
+static u32 hisi_read_l3c_counter(struct hisi_l3c_data *l3c_hwmod_data,
+ int cntr_idx, int bank_idx)
+{
+ struct hisi_djtag_client *client = l3c_hwmod_data->client;
+ u32 module_id = l3c_hwmod_data->l3c_hwcfg.module_id[bank_idx];
+ u32 cfg_en = l3c_hwmod_data->l3c_hwcfg.bank_cfgen[bank_idx];
+ u32 reg_offset, value;
+
+ reg_offset = l3c_hwmod_data->l3c_hwcfg.counter_reg0_off +
+ (cntr_idx * 4);
+
+ hisi_djtag_readreg(module_id, cfg_en, reg_offset, client, &value);
+
+ return value;
+}
+
+static u64 hisi_l3c_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc, int idx)
+{
+ struct hisi_pmu *pl3c_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
+ u64 delta, prev_raw_count, total_raw_count = 0, avg_raw_count = 0;
+ u32 num_banks = l3c_hwmod_data->l3c_hwcfg.num_banks;
+ int i;
+
+ if (!hisi_l3c_counter_valid(idx)) {
+ dev_err(pl3c_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ /* Check if the L3C data is initialized for this SCCL */
+ if (!l3c_hwmod_data->client) {
+ dev_err(pl3c_pmu->dev, "SCL=%d not initialized!\n",
+ pl3c_pmu->scl_id);
+ return 0;
+ }
+
+ do {
+ /* Get count from individual L3C banks and sum them up */
+ for (i = 0; i < num_banks; i++) {
+ total_raw_count += hisi_read_l3c_counter(l3c_hwmod_data,
+ idx, i);
+ }
+ prev_raw_count = local64_read(&hwc->prev_count);
+
+ /*
+ * As prev_raw_count is updated with average value of
+ * L3 cache banks, we multiply it by no of banks and
+ * compute the delta
+ */
+ delta = (total_raw_count - (prev_raw_count * num_banks)) &
+ HISI_MAX_PERIOD;
+
+ local64_add(delta, &event->count);
+
+ /*
+ * Divide by num of banks to get average count and
+ * update prev_count with this value
+ */
+ avg_raw_count = total_raw_count / num_banks;
+ } while (local64_cmpxchg(
+ &hwc->prev_count, prev_raw_count, avg_raw_count) !=
+ prev_raw_count);
+
+ return total_raw_count;
+}
+
+static void hisi_set_l3c_evtype(struct hisi_pmu *pl3c_pmu, int idx, u32 val)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
+ u32 reg_offset = l3c_hwmod_data->l3c_hwcfg.evtype_reg0_off;
+ u32 event_value, value = 0;
+ u32 cfg_en, module_id;
+ int i;
+
+ event_value = (val -
+ HISI_HWEVENT_L3C_READ_ALLOCATE);
+
+ /* Select the appropriate Event select register */
+ if (idx > 3)
+ reg_offset += 4;
+
+ /* Value to write to event type register */
+ val = event_value << (8 * idx);
+
+ /* Find the djtag Identifier of the Unit */
+ client = l3c_hwmod_data->client;
+
+ /*
+ * Set the event in L3C_EVENT_TYPEx Register
+ * for all L3C banks
+ */
+ for (i = 0; i < l3c_hwmod_data->l3c_hwcfg.num_banks; i++) {
+ module_id = l3c_hwmod_data->l3c_hwcfg.module_id[i];
+ cfg_en = l3c_hwmod_data->l3c_hwcfg.bank_cfgen[i];
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client, &value);
+
+ value &= ~(0xff << (8 * idx));
+ value |= val;
+
+ hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+ }
+}
+
+static u32 hisi_write_l3c_counter(struct hisi_pmu *pl3c_pmu,
+ struct hw_perf_event *hwc, u32 value)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
+ u32 reg_offset, cfg_en, module_id;
+ int i, ret = 0;
+ int idx = GET_CNTR_IDX(hwc);
+
+ if (!hisi_l3c_counter_valid(idx)) {
+ dev_err(pl3c_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return -EINVAL;
+ }
+
+ reg_offset = l3c_hwmod_data->l3c_hwcfg.counter_reg0_off +
+ (idx * 4);
+
+ client = l3c_hwmod_data->client;
+
+ for (i = 0; i < l3c_hwmod_data->l3c_hwcfg.num_banks; i++) {
+ module_id = l3c_hwmod_data->l3c_hwcfg.module_id[i];
+ cfg_en = l3c_hwmod_data->l3c_hwcfg.bank_cfgen[i];
+ ret = hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+ if (!ret)
+ ret = value;
+ }
+
+ return ret;
+}
+
+static void hisi_enable_l3c_counter(struct hisi_pmu *pl3c_pmu, int idx)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
+ u32 reg_offset = l3c_hwmod_data->l3c_hwcfg.event_ctrl_reg_off;
+ u32 eventen = l3c_hwmod_data->l3c_hwcfg.event_enable;
+ u32 value, cfg_en, module_id;
+ int i;
+
+ if (!hisi_l3c_counter_valid(idx)) {
+ dev_err(pl3c_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ client = l3c_hwmod_data->client;
+
+ /*
+ * Set the event_bus_en bit in L3C AUCNTRL to enable counting
+ * for all L3C banks
+ */
+ for (i = 0; i < l3c_hwmod_data->l3c_hwcfg.num_banks; i++) {
+ module_id = l3c_hwmod_data->l3c_hwcfg.module_id[i];
+ cfg_en = l3c_hwmod_data->l3c_hwcfg.bank_cfgen[i];
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client, &value);
+
+ value |= eventen;
+ hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+ }
+}
+
+static void hisi_disable_l3c_counter(struct hisi_pmu *pl3c_pmu, int idx)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
+ u32 reg_offset = l3c_hwmod_data->l3c_hwcfg.event_ctrl_reg_off;
+ u32 eventen = l3c_hwmod_data->l3c_hwcfg.event_enable;
+ u32 value, cfg_en, module_id;
+ int i;
+
+ if (!hisi_l3c_counter_valid(idx)) {
+ dev_err(pl3c_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ /* Find the djtag Identifier of the Unit */
+ client = l3c_hwmod_data->client;
+
+ /*
+ * Clear the event_bus_en bit in L3C AUCNTRL if no other
+ * event counting for all L3C banks
+ */
+ for (i = 0; i < l3c_hwmod_data->l3c_hwcfg.num_banks; i++) {
+ module_id = l3c_hwmod_data->l3c_hwcfg.module_id[i];
+ cfg_en = l3c_hwmod_data->l3c_hwcfg.bank_cfgen[i];
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client, &value);
+
+ value &= ~(eventen);
+ hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+ }
+}
+
+static void hisi_clear_l3c_event_idx(struct hisi_pmu *pl3c_pmu,
+ int idx)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
+ u32 reg_offset = l3c_hwmod_data->l3c_hwcfg.evtype_reg0_off;
+ void *bitmap_addr;
+ u32 cfg_en, value, module_id;
+ int i;
+
+ if (!hisi_l3c_counter_valid(idx)) {
+ dev_err(pl3c_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ bitmap_addr = l3c_hwmod_data->hisi_l3c_event_used_mask;
+
+ __clear_bit(idx, bitmap_addr);
+
+ /* Clear Counting in L3C event config register */
+ if (idx > 3)
+ reg_offset += 4;
+
+ client = l3c_hwmod_data->client;
+
+ /*
+ * Clear the event in L3C_EVENT_TYPEx Register
+ * for all L3C banks
+ */
+ for (i = 0; i < l3c_hwmod_data->l3c_hwcfg.num_banks; i++) {
+ module_id = l3c_hwmod_data->l3c_hwcfg.module_id[i];
+ cfg_en = l3c_hwmod_data->l3c_hwcfg.bank_cfgen[i];
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client, &value);
+
+ value &= ~(0xff << (8 * idx));
+ value |= (0xff << (8 * idx));
+ hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+ }
+}
+
+static int hisi_l3c_get_event_idx(struct hisi_pmu *pl3c_pmu)
+{
+ struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
+ int event_idx;
+
+ event_idx =
+ find_first_zero_bit(
+ l3c_hwmod_data->hisi_l3c_event_used_mask,
+ pl3c_pmu->num_counters);
+
+ if (event_idx == HISI_MAX_CFG_L3C_CNTR)
+ return -EAGAIN;
+
+ __set_bit(event_idx,
+ l3c_hwmod_data->hisi_l3c_event_used_mask);
+
+ return event_idx;
+}
+
+static void hisi_free_l3c_data(struct hisi_pmu *pl3c_pmu)
+{
+ kfree(pl3c_pmu->hwmod_data);
+ pl3c_pmu->hwmod_data = NULL;
+}
+
+static int init_hisi_l3c_hwcfg(struct device *dev,
+ struct hisi_l3c_data *pl3c_data)
+{
+ struct hisi_l3c_hwcfg *pl3c_hwcfg = &pl3c_data->l3c_hwcfg;
+ struct device_node *node = dev->of_node;
+ u32 prop_len;
+ int ret;
+
+ if (of_property_read_u32(node, "counter-reg",
+ &pl3c_hwcfg->counter_reg0_off)) {
+ dev_err(dev, "DT:Couldnot read counter-reg!\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "evctrl-reg",
+ &pl3c_hwcfg->event_ctrl_reg_off)) {
+ dev_err(dev, "DT:Couldnot read evctrl-reg!\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "event-en",
+ &pl3c_hwcfg->event_enable)) {
+ dev_err(dev, "DT:Couldnot read event-en!\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "evtype-reg",
+ &pl3c_hwcfg->evtype_reg0_off)) {
+ dev_err(dev, "DT:Couldnot read evtype-reg!\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "num-banks",
+ &pl3c_hwcfg->num_banks)) {
+ dev_err(dev, "DT:Couldnot read num-banks!\n");
+ return -EINVAL;
+ }
+
+ prop_len = of_property_count_u32_elems(node, "module-id");
+ if (prop_len != pl3c_hwcfg->num_banks) {
+ dev_err(dev, "DT:module-id entry not valid!\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32_array(node, "module-id",
+ &pl3c_hwcfg->module_id[0],
+ pl3c_hwcfg->num_banks);
+ if (ret < 0) {
+ dev_err(dev, "DT:Couldnot read module-id!\n");
+ return -EINVAL;
+ }
+
+ prop_len = of_property_count_u32_elems(node, "cfgen-map");
+ if (prop_len != pl3c_hwcfg->num_banks) {
+ dev_err(dev, "DT:cfgen-map entrynot valid!\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32_array(node, "cfgen-map",
+ &pl3c_hwcfg->bank_cfgen[0],
+ pl3c_hwcfg->num_banks);
+ if (ret < 0) {
+ dev_err(dev, "DT:Couldnot read cfgen-map!\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int init_hisi_l3c_data(struct device *dev,
+ struct hisi_pmu *pl3c_pmu,
+ struct hisi_djtag_client *client)
+{
+ struct hisi_l3c_data *l3c_hwmod_data = NULL;
+ int ret;
+
+ l3c_hwmod_data = kzalloc(sizeof(struct hisi_l3c_data),
+ GFP_KERNEL);
+ if (!l3c_hwmod_data)
+ return -ENOMEM;
+
+ /* Set the djtag Identifier */
+ l3c_hwmod_data->client = client;
+
+ pl3c_pmu->hw_events.events = devm_kcalloc(dev,
+ pl3c_pmu->num_counters,
+ sizeof(*pl3c_pmu->hw_events.events),
+ GFP_KERNEL);
+ if (!pl3c_pmu->hw_events.events) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ raw_spin_lock_init(&pl3c_pmu->hw_events.pmu_lock);
+
+ pl3c_pmu->hwmod_data = l3c_hwmod_data;
+
+ ret = init_hisi_l3c_hwcfg(dev, l3c_hwmod_data);
+ if (ret)
+ goto fail;
+
+ return 0;
+
+fail:
+ hisi_free_l3c_data(pl3c_pmu);
+ return ret;
+}
+
+static struct hisi_uncore_ops hisi_uncore_l3c_ops = {
+ .set_evtype = hisi_set_l3c_evtype,
+ .set_event_period = hisi_pmu_set_event_period,
+ .get_event_idx = hisi_l3c_get_event_idx,
+ .clear_event_idx = hisi_clear_l3c_event_idx,
+ .event_update = hisi_l3c_event_update,
+ .enable_counter = hisi_enable_l3c_counter,
+ .disable_counter = hisi_disable_l3c_counter,
+ .write_counter = hisi_write_l3c_counter,
+};
+
+static int hisi_l3c_pmu_init(struct device *dev,
+ struct hisi_pmu *pl3c_pmu)
+{
+ int ret;
+
+ /* Read common PMU properties */
+ ret = hisi_uncore_common_fwprop_read(dev, pl3c_pmu);
+ if (ret)
+ return ret;
+
+ pl3c_pmu->name = kasprintf(GFP_KERNEL, "hisi_l3c%d",
+ pl3c_pmu->scl_id);
+ pl3c_pmu->ops = &hisi_uncore_l3c_ops;
+ pl3c_pmu->dev = dev;
+
+ /* Pick one core to use for cpumask attributes */
+ cpumask_set_cpu(smp_processor_id(), &pl3c_pmu->cpu);
+
+ return 0;
+}
+
+static int hisi_pmu_l3c_dev_probe(struct hisi_djtag_client *client)
+{
+ struct hisi_pmu *pl3c_pmu = NULL;
+ struct device *dev = &client->dev;
+ int ret;
+
+ pl3c_pmu = hisi_pmu_alloc(dev);
+ if (IS_ERR(pl3c_pmu))
+ return PTR_ERR(pl3c_pmu);
+
+ ret = hisi_l3c_pmu_init(dev, pl3c_pmu);
+ if (ret)
+ return ret;
+
+ ret = init_hisi_l3c_data(dev, pl3c_pmu, client);
+ if (ret)
+ goto fail_init;
+
+ /* Register with perf PMU */
+ pl3c_pmu->pmu = (struct pmu) {
+ .name = pl3c_pmu->name,
+ .task_ctx_nr = perf_invalid_context,
+ .event_init = hisi_uncore_pmu_event_init,
+ .add = hisi_uncore_pmu_add,
+ .del = hisi_uncore_pmu_del,
+ .start = hisi_uncore_pmu_start,
+ .stop = hisi_uncore_pmu_stop,
+ .read = hisi_uncore_pmu_read,
+ };
+
+ ret = hisi_uncore_pmu_setup(pl3c_pmu, pl3c_pmu->name);
+ if (ret) {
+ dev_err(dev, "hisi_uncore_pmu_init FAILED!!\n");
+ goto fail;
+ }
+
+ /* Set the drv data to l3c_pmu */
+ dev_set_drvdata(dev, pl3c_pmu);
+
+ return 0;
+
+fail:
+ hisi_free_l3c_data(pl3c_pmu);
+
+fail_init:
+ dev_err(dev, "%s failed\n", __func__);
+ return ret;
+}
+
+static int hisi_pmu_l3c_dev_remove(struct hisi_djtag_client *client)
+{
+ struct hisi_pmu *pl3c_pmu = NULL;
+ struct device *dev = &client->dev;
+
+ pl3c_pmu = dev_get_drvdata(dev);
+
+ perf_pmu_unregister(&pl3c_pmu->pmu);
+ hisi_free_l3c_data(pl3c_pmu);
+
+ return 0;
+}
+
+static const struct of_device_id l3c_of_match[] = {
+ { .compatible = "hisilicon,hisi-pmu-l3c-v1", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, l3c_of_match);
+
+static struct hisi_djtag_driver hisi_pmu_l3c_driver = {
+ .driver = {
+ .name = "hisi-pmu-l3c",
+ .of_match_table = l3c_of_match,
+ },
+ .probe = hisi_pmu_l3c_dev_probe,
+ .remove = hisi_pmu_l3c_dev_remove,
+};
+
+static int __init hisi_pmu_l3c_init(void)
+{
+ int rc;
+
+ rc = hisi_djtag_register_driver(THIS_MODULE, &hisi_pmu_l3c_driver);
+ if (rc < 0) {
+ pr_err("hisi pmu l3c init failed, rc=%d\n", rc);
+ return rc;
+ }
+
+ return 0;
+}
+module_init(hisi_pmu_l3c_init);
+
+static void __exit hisi_pmu_l3c_exit(void)
+{
+ hisi_djtag_unregister_driver(&hisi_pmu_l3c_driver);
+
+}
+module_exit(hisi_pmu_l3c_exit);
+
+MODULE_DESCRIPTION("HiSilicon SoC HIP0x L3C PMU driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Anurup M");
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c.h b/drivers/perf/hisilicon/hisi_uncore_l3c.h
new file mode 100644
index 0000000..a4a1777
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c.h
@@ -0,0 +1,67 @@
+/*
+ * HiSilicon SoC L3C Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __HISI_UNCORE_L3C_H__
+#define __HISI_UNCORE_L3C_H__
+
+#include "hisi_uncore_pmu.h"
+
+/*
+ * ARMv8 HiSilicon L3C RAW event types.
+ */
+enum armv8_hisi_l3c_event_types {
+ HISI_HWEVENT_L3C_READ_ALLOCATE = 0x0,
+ HISI_HWEVENT_L3C_WRITE_ALLOCATE = 0x01,
+ HISI_HWEVENT_L3C_READ_NOALLOCATE = 0x02,
+ HISI_HWEVENT_L3C_WRITE_NOALLOCATE = 0x03,
+ HISI_HWEVENT_L3C_READ_HIT = 0x04,
+ HISI_HWEVENT_L3C_WRITE_HIT = 0x05,
+ HISI_HWEVENT_L3C_EVENT_MAX = 0x15,
+};
+
+/*
+ * ARMv8 HiSilicon Hardware counter Index.
+ */
+enum armv8_hisi_l3c_counters {
+ HISI_IDX_L3C_COUNTER0 = 0x0,
+ HISI_IDX_L3C_COUNTER_MAX = 0x7,
+};
+
+#define HISI_MAX_CFG_L3C_CNTR 0x08
+
+struct hisi_l3c_hwcfg {
+ u32 evtype_reg0_off;
+ u32 counter_reg0_off;
+ u32 event_ctrl_reg_off;
+ u32 event_enable;
+ u32 module_id[MAX_BANKS];
+ u32 num_banks;
+ u32 bank_cfgen[MAX_BANKS];
+};
+
+struct hisi_l3c_data {
+ struct hisi_djtag_client *client;
+ DECLARE_BITMAP(hisi_l3c_event_used_mask,
+ HISI_MAX_CFG_L3C_CNTR);
+ struct hisi_l3c_hwcfg l3c_hwcfg;
+};
+
+#endif /* __HISI_UNCORE_L3C_H__ */
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c
new file mode 100644
index 0000000..8d29fcc
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -0,0 +1,331 @@
+/*
+ * HiSilicon SoC Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/bitmap.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/perf_event.h>
+#include "hisi_uncore_pmu.h"
+
+/* djtag read interface - Call djtag driver to access SoC registers */
+int hisi_djtag_readreg(int module_id, int bank, u32 offset,
+ struct hisi_djtag_client *client, u32 *pvalue)
+{
+ int ret;
+ u32 chain_id = 0;
+
+ while (bank != 1) {
+ bank = (bank >> 0x1);
+ chain_id++;
+ }
+
+ ret = hisi_djtag_readl(client, offset, module_id,
+ chain_id, pvalue);
+ if (ret)
+ dev_err(&client->dev, "read failed, ret=%d!\n", ret);
+
+ return ret;
+}
+
+/* djtag write interface - Call djtag driver to access SoC registers */
+int hisi_djtag_writereg(int module_id, int bank,
+ u32 offset, u32 value,
+ struct hisi_djtag_client *client)
+{
+ int ret;
+
+ ret = hisi_djtag_writel(client, offset, module_id,
+ HISI_DJTAG_MOD_MASK, value);
+ if (ret)
+ dev_err(&client->dev, "write failed, ret=%d!\n", ret);
+
+ return ret;
+}
+
+static int pmu_map_event(struct perf_event *event)
+{
+ return (int)(event->attr.config & HISI_EVTYPE_EVENT);
+}
+
+static int
+__hw_perf_event_init(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
+ struct device *dev = phisi_pmu->dev;
+ int mapping;
+
+ mapping = pmu_map_event(event);
+ if (mapping < 0) {
+ dev_err(dev, "event %x:%llx not supported\n", event->attr.type,
+ event->attr.config);
+ return mapping;
+ }
+
+ /*
+ * We don't assign an index until we actually place the event onto
+ * hardware. Use -1 to signify that we haven't decided where to put it
+ * yet.
+ */
+ hwc->idx = -1;
+ hwc->config = 0;
+ hwc->event_base = 0;
+
+ /* For HiSilicon SoC L3C update config_base based on event encoding */
+ hwc->config_base = event->attr.config;
+
+ return 0;
+}
+
+int hisi_uncore_pmu_event_init(struct perf_event *event)
+{
+ int err;
+ struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
+
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ /* we do not support sampling as the counters are all
+ * shared by all CPU cores in a CPU die(SCCL). Also we
+ * donot support attach to a task(per-process mode)
+ */
+ if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+ return -EOPNOTSUPP;
+
+ /* counters do not have these bits */
+ if (event->attr.exclude_user ||
+ event->attr.exclude_kernel ||
+ event->attr.exclude_host ||
+ event->attr.exclude_guest ||
+ event->attr.exclude_hv ||
+ event->attr.exclude_idle)
+ return -EINVAL;
+
+ if (event->cpu < 0)
+ return -EINVAL;
+
+ event->cpu = cpumask_first(&phisi_pmu->cpu);
+
+ err = __hw_perf_event_init(event);
+
+ return err;
+}
+
+/*
+ * Enable counter and set the counter to count
+ * the event that we're interested in.
+ */
+void hisi_uncore_pmu_enable_event(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
+
+ /* Disable the hardware event counting */
+ if (phisi_pmu->ops->disable_counter)
+ phisi_pmu->ops->disable_counter(phisi_pmu, GET_CNTR_IDX(hwc));
+
+ /*
+ * Set event (if destined for Hisilicon SoC counters).
+ */
+ if (phisi_pmu->ops->set_evtype)
+ phisi_pmu->ops->set_evtype(phisi_pmu, GET_CNTR_IDX(hwc),
+ hwc->config_base);
+
+ /* Enable the hardware event counting */
+ if (phisi_pmu->ops->enable_counter)
+ phisi_pmu->ops->enable_counter(phisi_pmu, GET_CNTR_IDX(hwc));
+}
+
+void hisi_pmu_set_event_period(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
+
+ /*
+ * The Hisilicon PMU counters have a period of 2^32. To account for the
+ * possiblity of extreme interrupt latency we program for a period of
+ * half that. Hopefully we can handle the interrupt before another 2^31
+ * events occur and the counter overtakes its previous value.
+ */
+ u64 val = 1ULL << 31;
+
+ local64_set(&hwc->prev_count, val);
+
+ /* Write to the hardware event counter */
+ phisi_pmu->ops->write_counter(phisi_pmu, hwc, val);
+}
+
+void hisi_uncore_pmu_start(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_pmu_hw_events *hw_events;
+
+ hw_events = &phisi_pmu->hw_events;
+
+ if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+ return;
+
+ WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+ hwc->state = 0;
+
+ if (phisi_pmu->ops->set_event_period)
+ phisi_pmu->ops->set_event_period(event);
+
+ if (flags & PERF_EF_RELOAD) {
+ u64 prev_raw_count = local64_read(&hwc->prev_count);
+
+ phisi_pmu->ops->write_counter(phisi_pmu, hwc,
+ (u32)prev_raw_count);
+ }
+
+ hisi_uncore_pmu_enable_event(event);
+ perf_event_update_userpage(event);
+}
+
+void hisi_uncore_pmu_stop(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ /*
+ * We always reprogram the counter, so ignore PERF_EF_UPDATE.
+ * See hisi_uncore_pmu_start()
+ */
+ if (phisi_pmu->ops->disable_counter)
+ phisi_pmu->ops->disable_counter(phisi_pmu,
+ GET_CNTR_IDX(hwc));
+
+ WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+ hwc->state |= PERF_HES_STOPPED;
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ /* Read hardware counter and update the Perf counter statistics */
+ phisi_pmu->ops->event_update(event, hwc, GET_CNTR_IDX(hwc));
+ hwc->state |= PERF_HES_UPTODATE;
+}
+
+int hisi_uncore_pmu_add(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_pmu_hw_events *hw_events;
+ int idx;
+
+ hw_events = &phisi_pmu->hw_events;
+
+ hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+
+ /* If we don't have a free counter then return early. */
+ idx = phisi_pmu->ops->get_event_idx(phisi_pmu);
+ if (idx < 0)
+ return -EAGAIN;
+
+ event->hw.idx = idx;
+ hw_events->events[idx] = event;
+
+ if (flags & PERF_EF_START)
+ hisi_uncore_pmu_start(event, PERF_EF_RELOAD);
+
+ /* Propagate our changes to the userspace mapping. */
+ perf_event_update_userpage(event);
+
+ return 0;
+}
+
+void hisi_uncore_pmu_del(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_pmu_hw_events *hw_events;
+
+ hw_events = &phisi_pmu->hw_events;
+
+ hisi_uncore_pmu_stop(event, PERF_EF_UPDATE);
+
+ phisi_pmu->ops->clear_event_idx(phisi_pmu, GET_CNTR_IDX(hwc));
+ perf_event_update_userpage(event);
+ hw_events->events[GET_CNTR_IDX(hwc)] = NULL;
+}
+
+struct hisi_pmu *hisi_pmu_alloc(struct device *dev)
+{
+ struct hisi_pmu *phisi_pmu;
+
+ phisi_pmu = devm_kzalloc(dev, sizeof(*phisi_pmu), GFP_KERNEL);
+ if (!phisi_pmu)
+ return ERR_PTR(-ENOMEM);
+
+ return phisi_pmu;
+}
+
+void hisi_uncore_pmu_read(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
+
+ /* Read hardware counter and update the Perf counter statistics */
+ phisi_pmu->ops->event_update(event, hwc, GET_CNTR_IDX(hwc));
+}
+
+int hisi_uncore_common_fwprop_read(struct device *dev,
+ struct hisi_pmu *phisi_pmu)
+{
+ if (device_property_read_u32(dev, "num-events",
+ &phisi_pmu->num_events)) {
+ dev_err(dev, "Cant read num-events from DT!\n");
+ return -EINVAL;
+ }
+
+ if (device_property_read_u32(dev, "num-counters",
+ &phisi_pmu->num_counters)) {
+ dev_err(dev, "Cant read num-counters from DT!\n");
+ return -EINVAL;
+ }
+
+ /* Find the SCL ID */
+ if (device_property_read_u32(dev, "scl-id",
+ &phisi_pmu->scl_id)) {
+ dev_err(dev, "Cant read scl-id!\n");
+ return -EINVAL;
+ }
+
+ if (phisi_pmu->scl_id == 0 ||
+ phisi_pmu->scl_id >= MAX_UNITS) {
+ dev_err(dev, "Invalid SCL=%d!\n",
+ phisi_pmu->scl_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int hisi_uncore_pmu_setup(struct hisi_pmu *phisi_pmu,
+ const char *pmu_name)
+{
+ /* Register the events with perf */
+ return perf_pmu_register(&phisi_pmu->pmu, pmu_name, -1);
+}
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.h b/drivers/perf/hisilicon/hisi_uncore_pmu.h
new file mode 100644
index 0000000..b6b16df
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.h
@@ -0,0 +1,108 @@
+/*
+ * HiSilicon SoC Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __HISI_UNCORE_PMU_H__
+#define __HISI_UNCORE_PMU_H__
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/soc/hisilicon/djtag.h>
+#include <linux/types.h>
+#include <asm/local64.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "hisi_pmu: " fmt
+
+#define HISI_DJTAG_MOD_MASK (0xFFFF)
+#define HISI_CNTR_SCCL_MASK (0xF00)
+
+#define HISI_EVTYPE_EVENT 0xfff
+#define HISI_MAX_PERIOD ((1LLU << 32) - 1)
+
+#define MAX_BANKS 8
+#define MAX_COUNTERS 30
+#define MAX_UNITS 8
+
+#define GET_CNTR_IDX(hwc) (hwc->idx)
+#define to_hisi_pmu(c) (container_of(c, struct hisi_pmu, pmu))
+
+#define GET_UNIT_IDX(event_code) \
+ (((event_code & HISI_SCCL_MASK) >> \
+ HISI_SCCL_SHIFT) - 1)
+
+struct hisi_pmu;
+
+struct hisi_uncore_ops {
+ void (*set_evtype)(struct hisi_pmu *, int, u32);
+ void (*set_event_period)(struct perf_event *);
+ int (*get_event_idx)(struct hisi_pmu *);
+ void (*clear_event_idx)(struct hisi_pmu *, int);
+ u64 (*event_update)(struct perf_event *,
+ struct hw_perf_event *, int);
+ u32 (*read_counter)(struct hisi_pmu *, int, int);
+ u32 (*write_counter)(struct hisi_pmu *,
+ struct hw_perf_event *, u32);
+ void (*enable_counter)(struct hisi_pmu *, int);
+ void (*disable_counter)(struct hisi_pmu *, int);
+};
+
+struct hisi_pmu_hw_events {
+ struct perf_event **events;
+ raw_spinlock_t pmu_lock;
+};
+
+/* Generic pmu struct for different pmu types */
+struct hisi_pmu {
+ const char *name;
+ struct hisi_pmu_hw_events hw_events;
+ struct hisi_uncore_ops *ops;
+ struct device *dev;
+ void *hwmod_data; /* Hardware module specific data */
+ cpumask_t cpu;
+ struct pmu pmu;
+ u32 scl_id;
+ int num_counters;
+ int num_events;
+ int num_units;
+};
+
+void hisi_uncore_pmu_read(struct perf_event *event);
+void hisi_uncore_pmu_del(struct perf_event *event, int flags);
+int hisi_uncore_pmu_add(struct perf_event *event, int flags);
+void hisi_uncore_pmu_start(struct perf_event *event, int flags);
+void hisi_uncore_pmu_stop(struct perf_event *event, int flags);
+void hisi_pmu_set_event_period(struct perf_event *event);
+void hisi_uncore_pmu_enable_event(struct perf_event *event);
+int hisi_uncore_pmu_setup(struct hisi_pmu *phisi_pmu, const char *pmu_name);
+int hisi_uncore_pmu_event_init(struct perf_event *event);
+int hisi_djtag_readreg(int module_id, int bank, u32 offset,
+ struct hisi_djtag_client *client,
+ u32 *pvalue);
+int hisi_djtag_writereg(int module_id, int bank,
+ u32 offset, u32 value,
+ struct hisi_djtag_client *client);
+struct hisi_pmu *hisi_pmu_alloc(struct device *dev);
+int hisi_uncore_common_fwprop_read(struct device *dev,
+ struct hisi_pmu *phisi_pmu);
+#endif /* __HISI_UNCORE_PMU_H__ */
--
2.1.4
^ permalink raw reply related
* [PATCH v1 08/11] perf: hisi: Add sysfs attributes for L3 cache(L3C) PMU
From: Anurup M @ 2016-11-02 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478101374-18778-1-git-send-email-anurup.m@huawei.com>
1. Add L3 caches events to /sys/devices/hisi_l3c2/events/
The events can be selected as shown in perf list
e.g.: For L3C_READ_ALLOCATE event for Super CPU cluster 2 the
event format is
-e "hisi_l3c2/read_allocate/"
2. Add cpu_mask attribute group for showing the available CPU
for counting.
Signed-off-by: Anurup M <anurup.m@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57 ++++++++++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 22 ++++++++++++
3 files changed, 119 insertions(+)
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c.c b/drivers/perf/hisilicon/hisi_uncore_l3c.c
index f78f7b2..428fba0 100644
--- a/drivers/perf/hisilicon/hisi_uncore_l3c.c
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c.c
@@ -436,6 +436,62 @@ static int init_hisi_l3c_data(struct device *dev,
return ret;
}
+static struct attribute *hisi_l3c_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-11"),
+ NULL,
+};
+
+static struct attribute_group hisi_l3c_format_group = {
+ .name = "format",
+ .attrs = hisi_l3c_format_attr,
+};
+
+static struct attribute *hisi_l3c_events_attr[] = {
+ HISI_PMU_EVENT_ATTR_STR(read_allocate,
+ "event=0x0"),
+ HISI_PMU_EVENT_ATTR_STR(write_allocate,
+ "event=0x01"),
+ HISI_PMU_EVENT_ATTR_STR(read_noallocate,
+ "event=0x02"),
+ HISI_PMU_EVENT_ATTR_STR(write_noallocate,
+ "event=0x03"),
+ HISI_PMU_EVENT_ATTR_STR(read_hit, "event=0x04"),
+ HISI_PMU_EVENT_ATTR_STR(write_hit, "event=0x05"),
+ NULL,
+};
+
+static struct attribute_group hisi_l3c_events_group = {
+ .name = "events",
+ .attrs = hisi_l3c_events_attr,
+};
+
+static struct attribute *hisi_l3c_attrs[] = {
+ NULL,
+};
+
+struct attribute_group hisi_l3c_attr_group = {
+ .attrs = hisi_l3c_attrs,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_l3c_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_l3c_cpumask_attr_group = {
+ .attrs = hisi_l3c_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_l3c_pmu_attr_groups[] = {
+ &hisi_l3c_attr_group,
+ &hisi_l3c_format_group,
+ &hisi_l3c_events_group,
+ &hisi_l3c_cpumask_attr_group,
+ NULL,
+};
+
static struct hisi_uncore_ops hisi_uncore_l3c_ops = {
.set_evtype = hisi_set_l3c_evtype,
.set_event_period = hisi_pmu_set_event_period,
@@ -496,6 +552,7 @@ static int hisi_pmu_l3c_dev_probe(struct hisi_djtag_client *client)
.start = hisi_uncore_pmu_start,
.stop = hisi_uncore_pmu_stop,
.read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_l3c_pmu_attr_groups,
};
ret = hisi_uncore_pmu_setup(pl3c_pmu, pl3c_pmu->name);
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c
index 8d29fcc..d0a911a 100644
--- a/drivers/perf/hisilicon/hisi_uncore_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -26,6 +26,46 @@
#include <linux/perf_event.h>
#include "hisi_uncore_pmu.h"
+/*
+ * PMU format attributes
+ */
+ssize_t hisi_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute,
+ attr);
+ return sprintf(buf, "%s\n", (char *) eattr->var);
+}
+
+/*
+ * PMU event attributes
+ */
+ssize_t hisi_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(attr, struct perf_pmu_events_attr, attr);
+
+ if (pmu_attr->event_str)
+ return sprintf(buf, "%s", pmu_attr->event_str);
+
+ return 0;
+}
+
+/*
+ * sysfs cpumask attributes
+ */
+ssize_t hisi_cpumask_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct pmu *pmu = dev_get_drvdata(dev);
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
+
+ return cpumap_print_to_pagebuf(true, buf, &hisi_pmu->cpu);
+}
+
/* djtag read interface - Call djtag driver to access SoC registers */
int hisi_djtag_readreg(int module_id, int bank, u32 offset,
struct hisi_djtag_client *client, u32 *pvalue)
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.h b/drivers/perf/hisilicon/hisi_uncore_pmu.h
index b6b16df..a948752 100644
--- a/drivers/perf/hisilicon/hisi_uncore_pmu.h
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.h
@@ -51,6 +51,22 @@
(((event_code & HISI_SCCL_MASK) >> \
HISI_SCCL_SHIFT) - 1)
+#define HISI_PMU_FORMAT_ATTR(_name, _config) \
+ (&((struct dev_ext_attribute[]) { \
+ { .attr = __ATTR(_name, 0444, \
+ hisi_format_sysfs_show, NULL), \
+ .var = (void *) _config, \
+ } \
+ })[0].attr.attr)
+
+#define HISI_PMU_EVENT_ATTR_STR(_name, _str) \
+ (&((struct perf_pmu_events_attr[]) { \
+ { .attr = __ATTR(_name, 0444, \
+ hisi_event_sysfs_show, NULL), \
+ .event_str = _str, \
+ } \
+ })[0].attr.attr)
+
struct hisi_pmu;
struct hisi_uncore_ops {
@@ -105,4 +121,10 @@ int hisi_djtag_writereg(int module_id, int bank,
struct hisi_pmu *hisi_pmu_alloc(struct device *dev);
int hisi_uncore_common_fwprop_read(struct device *dev,
struct hisi_pmu *phisi_pmu);
+ssize_t hisi_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t hisi_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t hisi_cpumask_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf);
#endif /* __HISI_UNCORE_PMU_H__ */
--
2.1.4
^ permalink raw reply related
* [PATCH v1 09/11] perf: hisi: Miscellanous node(MN) event counting in perf
From: Anurup M @ 2016-11-02 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478101374-18778-1-git-send-email-anurup.m@huawei.com>
From: Shaokun Zhang <zhangshaokun@hisilicon.com>
1. Add support to count MN hardware events.
2. Mn events are listed in sysfs at /sys/devices/hisi_mn2/events/
The events can be selected as shown in perf list
e.g.: For MN_READ_REQUEST event for Super CPU cluster 2 the
event format is
-e "hisi_mn2/read_req/"
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 571 ++++++++++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_mn.h | 68 ++++
3 files changed, 640 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn.h
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index e1766cf..8975104 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o hisi_uncore_mn.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_mn.c b/drivers/perf/hisilicon/hisi_uncore_mn.c
new file mode 100644
index 0000000..920e346
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_mn.c
@@ -0,0 +1,571 @@
+/*
+ * HiSilicon SoC MN Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/bitmap.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/perf_event.h>
+#include "hisi_uncore_mn.h"
+
+static inline int hisi_mn_counter_valid(int idx)
+{
+ return (idx >= HISI_IDX_MN_COUNTER0 &&
+ idx <= HISI_IDX_MN_COUNTER_MAX);
+}
+
+static u32 hisi_read_mn_counter(struct hisi_mn_data *mn_hwmod_data,
+ int idx)
+{
+ u32 module_id = mn_hwmod_data->mn_hwcfg.module_id;
+ struct hisi_djtag_client *client = mn_hwmod_data->client;
+ u32 cfg_en, reg_offset, value;
+
+ cfg_en = mn_hwmod_data->mn_hwcfg.bank_cfgen;
+ reg_offset = mn_hwmod_data->mn_hwcfg.counter_reg0_off + (idx * 4);
+
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client, &value);
+
+ return value;
+}
+
+static u64 hisi_mn_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc, int idx)
+{
+ struct hisi_pmu *pmn_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_mn_data *mn_hwmod_data;
+ u64 delta, prev_raw_count, new_raw_count = 0;
+ u32 cfg_en;
+
+ if (!hisi_mn_counter_valid(idx)) {
+ dev_err(pmn_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ mn_hwmod_data = pmn_pmu->hwmod_data;
+
+ /* Check if the MN data is initialized for this SCCL */
+ if (!mn_hwmod_data->client) {
+ dev_err(pmn_pmu->dev,
+ "SCL=%d not initialized!\n", pmn_pmu->scl_id);
+ return 0;
+ }
+
+ cfg_en = mn_hwmod_data->mn_hwcfg.bank_cfgen;
+
+ do {
+ prev_raw_count = local64_read(&hwc->prev_count);
+ new_raw_count =
+ hisi_read_mn_counter(mn_hwmod_data, idx);
+ delta = (new_raw_count - prev_raw_count) &
+ HISI_MAX_PERIOD;
+
+ local64_add(delta, &event->count);
+ } while (local64_cmpxchg(
+ &hwc->prev_count, prev_raw_count, new_raw_count) !=
+ prev_raw_count);
+
+ return new_raw_count;
+}
+
+static void hisi_set_mn_evtype(struct hisi_pmu *pmn_pmu, int idx, u32 val)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_mn_data *mn_hwmod_data = pmn_pmu->hwmod_data;
+ u32 reg_offset = mn_hwmod_data->mn_hwcfg.evtype_reg0_off;
+ u32 module_id = mn_hwmod_data->mn_hwcfg.module_id;
+ u32 cfg_en, event_value, value = 0;
+
+ event_value = (val -
+ HISI_HWEVENT_MN_EO_BARR_REQ);
+
+ /* Value to write to event type register */
+ val = event_value << (8 * idx);
+
+ /* Find the djtag Identifier of the Unit */
+ client = mn_hwmod_data->client;
+ cfg_en = mn_hwmod_data->mn_hwcfg.bank_cfgen;
+
+ /*
+ * Set the event in MN_EVENT_TYPE Register
+ */
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client, &value);
+
+ value &= ~(0xff << (8 * idx));
+ value |= val;
+
+ hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+}
+
+static u32 hisi_write_mn_counter(struct hisi_pmu *pmn_pmu,
+ struct hw_perf_event *hwc, u32 value)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_mn_data *mn_hwmod_data = pmn_pmu->hwmod_data;
+ u32 module_id = mn_hwmod_data->mn_hwcfg.module_id;
+ u32 cfg_en, reg_offset;
+ int ret;
+ int idx = GET_CNTR_IDX(hwc);
+
+ if (!hisi_mn_counter_valid(idx)) {
+ dev_err(pmn_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return -EINVAL;
+ }
+
+ reg_offset = mn_hwmod_data->mn_hwcfg.counter_reg0_off +
+ (idx * 4);
+ /* Find the djtag Identifier of the Unit */
+ client = mn_hwmod_data->client;
+ cfg_en = mn_hwmod_data->mn_hwcfg.bank_cfgen;
+
+ ret = hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+
+ return ret;
+}
+
+static void hisi_enable_mn_counter(struct hisi_pmu *pmn_pmu, int idx)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_mn_data *mn_hwmod_data = pmn_pmu->hwmod_data;
+ u32 reg_offset = mn_hwmod_data->mn_hwcfg.event_ctrl_reg_off;
+ u32 module_id = mn_hwmod_data->mn_hwcfg.module_id;
+ u32 event_en = mn_hwmod_data->mn_hwcfg.event_enable;
+ u32 cfg_en, value;
+
+ if (!hisi_mn_counter_valid(idx)) {
+ dev_err(pmn_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ /* Find the djtag Identifier of the Unit */
+ client = mn_hwmod_data->client;
+ cfg_en = mn_hwmod_data->mn_hwcfg.bank_cfgen;
+
+ /*
+ * Set the event_bus_en bit in MN_EVENT_CTRL to enable counting
+ */
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client,
+ &value);
+
+ value |= event_en;
+ hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+}
+
+static void hisi_disable_mn_counter(struct hisi_pmu *pmn_pmu, int idx)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_mn_data *mn_hwmod_data = pmn_pmu->hwmod_data;
+ u32 reg_offset = mn_hwmod_data->mn_hwcfg.event_ctrl_reg_off;
+ u32 module_id = mn_hwmod_data->mn_hwcfg.module_id;
+ u32 event_en = mn_hwmod_data->mn_hwcfg.event_enable;
+ u32 cfg_en, value;
+
+ if (!hisi_mn_counter_valid(idx)) {
+ dev_err(pmn_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ /* Find the djtag Identifier of the Unit */
+ client = mn_hwmod_data->client;
+ cfg_en = mn_hwmod_data->mn_hwcfg.bank_cfgen;
+
+ /*
+ * Clear the event_bus_en bit in MN event control
+ */
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client, &value);
+
+ value &= ~(event_en);
+ hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+}
+
+static void hisi_clear_mn_event_idx(struct hisi_pmu *pmn_pmu, int idx)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_mn_data *mn_hwmod_data = pmn_pmu->hwmod_data;
+ u32 reg_offset = mn_hwmod_data->mn_hwcfg.evtype_reg0_off;
+ u32 module_id = mn_hwmod_data->mn_hwcfg.module_id;
+ void *bitmap_addr;
+ u32 cfg_en, value;
+
+ if (!hisi_mn_counter_valid(idx)) {
+ dev_err(pmn_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return;
+ }
+
+ bitmap_addr = mn_hwmod_data->hisi_mn_event_used_mask;
+
+ __clear_bit(idx, bitmap_addr);
+
+ /* Find the djtag Identifier of the Unit */
+ client = mn_hwmod_data->client;
+ cfg_en = mn_hwmod_data->mn_hwcfg.bank_cfgen;
+
+ /*
+ * Clear the event in MN_EVENT_TYPE Register
+ */
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client, &value);
+
+ value &= ~(0xff << (8 * idx));
+ value |= (0xff << (8 * idx));
+ hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+}
+
+static int hisi_mn_get_event_idx(struct hisi_pmu *pmn_pmu)
+{
+ struct hisi_mn_data *mn_hwmod_data = pmn_pmu->hwmod_data;
+ int event_idx;
+
+ event_idx =
+ find_first_zero_bit(
+ mn_hwmod_data->hisi_mn_event_used_mask,
+ HISI_MAX_CFG_MN_CNTR);
+
+ if (event_idx == HISI_MAX_CFG_MN_CNTR)
+ return -EAGAIN;
+
+ __set_bit(event_idx,
+ mn_hwmod_data->hisi_mn_event_used_mask);
+
+ return event_idx;
+}
+
+static void hisi_free_mn_data(struct hisi_pmu *pmn_pmu)
+{
+ kfree(pmn_pmu->hwmod_data);
+ pmn_pmu->hwmod_data = NULL;
+}
+
+static int init_hisi_mn_hwcfg(struct device *dev,
+ struct hisi_mn_data *pmn_data)
+{
+ struct hisi_mn_hwcfg *pmn_hwcfg = &pmn_data->mn_hwcfg;
+ struct device_node *node = dev->of_node;
+
+ if (of_property_read_u32(node, "counter-reg",
+ &pmn_hwcfg->counter_reg0_off)) {
+ dev_err(dev, "DT:Couldnot read counter-reg!\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "evctrl-reg",
+ &pmn_hwcfg->event_ctrl_reg_off)) {
+ dev_err(dev, "DT:Couldnot read evctrl-reg!\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "event-en",
+ &pmn_hwcfg->event_enable)) {
+ dev_err(dev, "DT:Couldnot read event-en property!\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "evtype-reg",
+ &pmn_hwcfg->evtype_reg0_off)) {
+ dev_err(dev, "DT:Couldnot read evtype-reg!\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "module-id",
+ &pmn_hwcfg->module_id)) {
+ dev_err(dev, "DT:Couldnot read module-id property!\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32(node, "cfgen-map",
+ &pmn_hwcfg->bank_cfgen)) {
+ dev_err(dev, "DT:Couldnot read cfgen-map property!\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int init_hisi_mn_data(struct device *dev,
+ struct hisi_pmu *pmn_pmu,
+ struct hisi_djtag_client *client)
+{
+ struct hisi_mn_data *mn_hwmod_data;
+ int ret;
+
+ mn_hwmod_data = kzalloc(sizeof(struct hisi_mn_data),
+ GFP_KERNEL);
+ if (!mn_hwmod_data)
+ return -ENOMEM;
+
+ /* Set the djtag Identifier */
+ mn_hwmod_data->client = client;
+
+ pmn_pmu->hw_events.events = devm_kcalloc(dev,
+ pmn_pmu->num_counters,
+ sizeof(*pmn_pmu->hw_events.events),
+ GFP_KERNEL);
+ if (!pmn_pmu->hw_events.events) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ raw_spin_lock_init(&pmn_pmu->hw_events.pmu_lock);
+
+ pmn_pmu->hwmod_data = mn_hwmod_data;
+
+ ret = init_hisi_mn_hwcfg(dev, mn_hwmod_data);
+ if (ret)
+ goto fail;
+
+ return 0;
+
+fail:
+ hisi_free_mn_data(pmn_pmu);
+ return ret;
+}
+
+static struct attribute *hisi_mn_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-11"),
+ NULL,
+};
+
+static struct attribute_group hisi_mn_format_group = {
+ .name = "format",
+ .attrs = hisi_mn_format_attr,
+};
+
+static struct attribute *hisi_mn_events_attr[] = {
+ HISI_PMU_EVENT_ATTR_STR(eo_barrier_req,
+ "event=0x0"),
+ HISI_PMU_EVENT_ATTR_STR(ec_barrier_req,
+ "event=0x01"),
+ HISI_PMU_EVENT_ATTR_STR(dvm_op_req,
+ "event=0x02"),
+ HISI_PMU_EVENT_ATTR_STR(dvm_sync_req,
+ "event=0x03"),
+ HISI_PMU_EVENT_ATTR_STR(read_req,
+ "event=0x04"),
+ HISI_PMU_EVENT_ATTR_STR(write_req,
+ "event=0x05"),
+ NULL,
+};
+
+static struct attribute_group hisi_mn_events_group = {
+ .name = "events",
+ .attrs = hisi_mn_events_attr,
+};
+
+static struct attribute *hisi_mn_attrs[] = {
+ NULL,
+};
+
+struct attribute_group hisi_mn_attr_group = {
+ .attrs = hisi_mn_attrs,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_mn_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_mn_cpumask_attr_group = {
+ .attrs = hisi_mn_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_mn_pmu_attr_groups[] = {
+ &hisi_mn_attr_group,
+ &hisi_mn_format_group,
+ &hisi_mn_events_group,
+ &hisi_mn_cpumask_attr_group,
+ NULL,
+};
+
+static struct hisi_uncore_ops hisi_uncore_mn_ops = {
+ .set_evtype = hisi_set_mn_evtype,
+ .set_event_period = hisi_pmu_set_event_period,
+ .get_event_idx = hisi_mn_get_event_idx,
+ .clear_event_idx = hisi_clear_mn_event_idx,
+ .event_update = hisi_mn_event_update,
+ .enable_counter = hisi_enable_mn_counter,
+ .disable_counter = hisi_disable_mn_counter,
+ .write_counter = hisi_write_mn_counter,
+};
+
+static int hisi_mn_pmu_init(struct device *dev,
+ struct hisi_pmu *pmn_pmu)
+{
+ int ret;
+ /* Read common PMU properties */
+ ret = hisi_uncore_common_fwprop_read(dev, pmn_pmu);
+ if (ret)
+ return ret;
+
+ pmn_pmu->name = kasprintf(GFP_KERNEL, "hisi_mn%d",
+ pmn_pmu->scl_id);
+ pmn_pmu->ops = &hisi_uncore_mn_ops;
+
+ pmn_pmu->dev = dev;
+ /* Pick one core to use for cpumask attributes */
+ cpumask_set_cpu(smp_processor_id(), &pmn_pmu->cpu);
+
+ return 0;
+}
+
+static int hisi_pmu_mn_dev_probe(struct hisi_djtag_client *client)
+{
+ struct hisi_pmu *pmn_pmu = NULL;
+ struct device *dev = &client->dev;
+ int ret;
+
+ pmn_pmu = hisi_pmu_alloc(dev);
+ if (IS_ERR(pmn_pmu))
+ return PTR_ERR(pmn_pmu);
+
+ ret = hisi_mn_pmu_init(dev, pmn_pmu);
+ if (ret)
+ return ret;
+
+ ret = init_hisi_mn_data(dev, pmn_pmu, client);
+ if (ret)
+ goto fail_init;
+
+ /* Register with perf PMU */
+ pmn_pmu->pmu = (struct pmu) {
+ .name = pmn_pmu->name,
+ .task_ctx_nr = perf_invalid_context,
+ .event_init = hisi_uncore_pmu_event_init,
+ .add = hisi_uncore_pmu_add,
+ .del = hisi_uncore_pmu_del,
+ .start = hisi_uncore_pmu_start,
+ .stop = hisi_uncore_pmu_stop,
+ .read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_mn_pmu_attr_groups,
+ };
+
+ ret = hisi_uncore_pmu_setup(pmn_pmu, pmn_pmu->name);
+ if (ret) {
+ dev_err(pmn_pmu->dev, "hisi_uncore_pmu_init FAILED!!\n");
+ goto fail;
+ }
+
+ /* Set the drv data to mn_pmu */
+ dev_set_drvdata(dev, pmn_pmu);
+
+ return 0;
+
+fail:
+ hisi_free_mn_data(pmn_pmu);
+
+fail_init:
+ if (pmn_pmu)
+ devm_kfree(dev, pmn_pmu);
+ dev_err(pmn_pmu->dev, "%s failed\n", __func__);
+
+ return ret;
+}
+
+static int hisi_pmu_mn_dev_remove(struct hisi_djtag_client *client)
+{
+ struct hisi_pmu *pmn_pmu = NULL;
+ struct device *dev = &client->dev;
+
+ pmn_pmu = dev_get_drvdata(dev);
+
+ perf_pmu_unregister(&pmn_pmu->pmu);
+ hisi_free_mn_data(pmn_pmu);
+
+ return 0;
+}
+
+static const struct of_device_id mn_of_match[] = {
+ { .compatible = "hisilicon,hisi-pmu-mn-v1", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mn_of_match);
+
+static struct hisi_djtag_driver hisi_pmu_mn_driver = {
+ .driver = {
+ .name = "hisi-pmu-mn",
+ .of_match_table = mn_of_match,
+ },
+ .probe = hisi_pmu_mn_dev_probe,
+ .remove = hisi_pmu_mn_dev_remove,
+};
+
+static int __init hisi_pmu_mn_init(void)
+{
+ int rc;
+
+ rc = hisi_djtag_register_driver(THIS_MODULE, &hisi_pmu_mn_driver);
+ if (rc < 0) {
+ pr_err("hisi pmu mn init failed, rc=%d\n", rc);
+ return rc;
+ }
+
+ return 0;
+}
+module_init(hisi_pmu_mn_init);
+
+static void __exit hisi_pmu_mn_exit(void)
+{
+ hisi_djtag_unregister_driver(&hisi_pmu_mn_driver);
+}
+module_exit(hisi_pmu_mn_exit);
+
+MODULE_DESCRIPTION("HiSilicon SoC HIP0x MN PMU driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Shaokun Zhang");
diff --git a/drivers/perf/hisilicon/hisi_uncore_mn.h b/drivers/perf/hisilicon/hisi_uncore_mn.h
new file mode 100644
index 0000000..4cac2f3
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_mn.h
@@ -0,0 +1,68 @@
+/*
+ * HiSilicon SoC MN Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __HISI_UNCORE_MN_H__
+#define __HISI_UNCORE_MN_H__
+
+#include "hisi_uncore_pmu.h"
+
+/*
+ * ARMv8 HiSilicon MN RAW event types.
+ */
+enum armv8_hisi_mn_event_types {
+ HISI_HWEVENT_MN_EO_BARR_REQ = 0x0,
+ HISI_HWEVENT_MN_EC_BARR_REQ = 0x01,
+ HISI_HWEVENT_MN_DVM_OP_REQ = 0x02,
+ HISI_HWEVENT_MN_DVM_SYNC_REQ = 0x03,
+ HISI_HWEVENT_MN_READ_REQ = 0x04,
+ HISI_HWEVENT_MN_WRITE_REQ = 0x05,
+ HISI_HWEVENT_MN_COPYBK_REQ = 0x06,
+ HISI_HWEVENT_MN_OTHER_REQ = 0x07,
+ HISI_HWEVENT_MN_EVENT_MAX = 0x08,
+};
+
+/*
+ * ARMv8 HiSilicon Hardware counter Index.
+ */
+enum armv8_hisi_mn_counters {
+ HISI_IDX_MN_COUNTER0 = 0x0,
+ HISI_IDX_MN_COUNTER_MAX = 0x4,
+};
+
+#define HISI_MAX_CFG_MN_CNTR 0x04
+
+struct hisi_mn_hwcfg {
+ u32 evtype_reg0_off;
+ u32 counter_reg0_off;
+ u32 event_ctrl_reg_off;
+ u32 event_enable;
+ u32 module_id;
+ u32 bank_cfgen;
+};
+
+struct hisi_mn_data {
+ struct hisi_djtag_client *client;
+ DECLARE_BITMAP(hisi_mn_event_used_mask,
+ HISI_MAX_CFG_MN_CNTR);
+ struct hisi_mn_hwcfg mn_hwcfg;
+};
+
+#endif /* __HISI_UNCORE_MN_H__ */
--
2.1.4
^ permalink raw reply related
* [PATCH v1 10/11] perf: hisi: Support for Hisilicon DDRC PMU.
From: Anurup M @ 2016-11-02 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478101374-18778-1-git-send-email-anurup.m@huawei.com>
1. Add support for counting Hisilicon DDRC
statistics events in perf.
2. Support a total of 13 statistics events.
3. Events listed in /sys/devices/<pmu_name>/
Signed-off-by: Anurup M <anurup.m@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_ddrc.c | 444 ++++++++++++++++++++++++++++++
drivers/perf/hisilicon/hisi_uncore_ddrc.h | 73 +++++
3 files changed, 518 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc.h
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index 8975104..8e9df2e 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o hisi_uncore_mn.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o hisi_uncore_mn.o hisi_uncore_ddrc.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc.c b/drivers/perf/hisilicon/hisi_uncore_ddrc.c
new file mode 100644
index 0000000..b89a72e
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_ddrc.c
@@ -0,0 +1,444 @@
+/*
+ * HiSilicon SoC DDRC Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/bitmap.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/perf_event.h>
+#include "hisi_uncore_ddrc.h"
+
+static inline int hisi_ddrc_counter_valid(int idx, struct hisi_pmu *ddrc_pmu)
+{
+ return (idx >= 0 && idx < ddrc_pmu->num_counters);
+}
+
+static u32 hisi_ddrc_read32_relaxed(void __iomem *regs_base, u32 off)
+{
+ void __iomem *reg_addr = regs_base + off;
+
+ return readl_relaxed(reg_addr);
+}
+
+static void hisi_ddrc_write32(void __iomem *regs_base, u32 off, u32 val)
+{
+ void __iomem *reg_addr = regs_base + off;
+
+ writel(val, reg_addr);
+}
+
+static u32 hisi_read_ddrc_counter(struct hisi_ddrc_data *ddrc_hwmod_data,
+ unsigned long event_code, int idx)
+{
+ u32 value;
+ u32 reg_off;
+
+ reg_off = HISI_DDRC_FLUX_WR_REG_OFF + (event_code * 4);
+
+ value = hisi_ddrc_read32_relaxed(ddrc_hwmod_data->regs_base,
+ reg_off);
+ return value;
+}
+
+static u64 hisi_ddrc_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc, int idx)
+{
+ struct hisi_pmu *ddrc_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_ddrc_data *ddrc_hwmod_data;
+ u64 delta, prev_raw_count, new_raw_count = 0;
+
+ if (!hisi_ddrc_counter_valid(idx, ddrc_pmu)) {
+ dev_err(ddrc_pmu->dev,
+ "%s: Unsupported event index:%d!\n", __func__, idx);
+ return 0;
+ }
+
+ ddrc_hwmod_data = ddrc_pmu->hwmod_data;
+
+ /* Check if the DDRC data is initialized for this SCCL */
+ if (!ddrc_hwmod_data->regs_base) {
+ dev_err(ddrc_pmu->dev, "DDRC registers not mapped!\n");
+ return 0;
+ }
+
+ do {
+ prev_raw_count = local64_read(&hwc->prev_count);
+ new_raw_count =
+ hisi_read_ddrc_counter(ddrc_hwmod_data,
+ hwc->config_base, idx);
+ delta = (new_raw_count - prev_raw_count) &
+ HISI_MAX_PERIOD;
+
+ local64_add(delta, &event->count);
+ } while (local64_cmpxchg(
+ &hwc->prev_count, prev_raw_count, new_raw_count) !=
+ prev_raw_count);
+
+ return new_raw_count;
+}
+
+static u32 hisi_write_ddrc_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc, u32 value)
+{
+ struct hisi_ddrc_data *ddrc_hwmod_data = ddrc_pmu->hwmod_data;
+ u32 reg_off;
+ u32 event_code = hwc->config_base;
+
+ if (!(event_code >= HISI_HWEVENT_DDRC_FLUX_WR &&
+ event_code < HISI_HWEVENT_DDRC_MAX_EVENT)) {
+ dev_err(ddrc_pmu->dev, "Unknown DDR evevnt!");
+ return 0;
+ }
+
+ if (!ddrc_hwmod_data->regs_base) {
+ dev_err(ddrc_pmu->dev,
+ "DDR reg address not mapped!\n");
+ return 0;
+ }
+
+ reg_off = HISI_DDRC_FLUX_WR_REG_OFF + (event_code * 4);
+
+ hisi_ddrc_write32(ddrc_hwmod_data->regs_base,
+ reg_off, value);
+
+ return value;
+}
+
+static void hisi_ddrc_set_event_period(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hisi_pmu *ddrc_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_ddrc_data *ddrc_hwmod_data = ddrc_pmu->hwmod_data;
+ u32 event_code = hwc->config_base;
+ u32 reg_off;
+ u32 value;
+
+ reg_off = HISI_DDRC_FLUX_WR_REG_OFF + (event_code * 4);
+ /*
+ * For Hisilicon DDRC PMU we save the current counter value
+ * to prev_count, as we have enabled continuous counting for
+ * DDRC.
+ */
+ value = hisi_ddrc_read32_relaxed(ddrc_hwmod_data->regs_base,
+ reg_off);
+ local64_set(&hwc->prev_count, value);
+}
+
+static void hisi_clear_ddrc_event_idx(struct hisi_pmu *ddrc_pmu, int idx)
+{
+ struct hisi_ddrc_data *ddrc_hwmod_data = ddrc_pmu->hwmod_data;
+ void *bitmap_addr;
+
+ if (!hisi_ddrc_counter_valid(idx, ddrc_pmu)) {
+ dev_err(ddrc_pmu->dev,
+ "%s:Unsupported event index:%d!\n", __func__, idx);
+ return;
+ }
+
+ bitmap_addr = ddrc_hwmod_data->hisi_ddrc_event_used_mask;
+
+ __clear_bit(idx, bitmap_addr);
+}
+
+static int hisi_ddrc_get_event_idx(struct hisi_pmu *ddrc_pmu)
+{
+ struct hisi_ddrc_data *ddrc_hwmod_data = ddrc_pmu->hwmod_data;
+ int event_idx;
+
+ event_idx =
+ find_first_zero_bit(
+ ddrc_hwmod_data->hisi_ddrc_event_used_mask,
+ ddrc_pmu->num_counters);
+
+ if (event_idx == ddrc_pmu->num_counters)
+ return -EAGAIN;
+
+ __set_bit(event_idx,
+ ddrc_hwmod_data->hisi_ddrc_event_used_mask);
+
+ return event_idx;
+}
+
+static void hisi_free_ddrc_data(struct hisi_pmu *ddrc_pmu)
+{
+ kfree(ddrc_pmu->hwmod_data);
+ ddrc_pmu->hwmod_data = NULL;
+}
+
+static void init_hisi_ddr(void __iomem *reg_base)
+{
+ u32 value;
+
+ hisi_ddrc_write32(reg_base, HISI_DDRC_CTRL_PERF_REG_OFF, 0);
+
+ value = hisi_ddrc_read32_relaxed(reg_base, HISI_DDRC_CFG_PERF_REG_OFF);
+ value &= 0x2fffffff;
+ hisi_ddrc_write32(reg_base, HISI_DDRC_CFG_PERF_REG_OFF, value);
+
+ /* Enable Continuous counting */
+ hisi_ddrc_write32(reg_base, HISI_DDRC_CTRL_PERF_REG_OFF, 1);
+}
+
+static int init_hisi_ddrc_dts_data(struct platform_device *pdev,
+ struct hisi_ddrc_data *ddrc_hwmod_data)
+{
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ /* Continue for zero entries */
+ if (!res) {
+ dev_err(&pdev->dev, "No DDR reg resorces!\n");
+ return -EINVAL;
+ }
+
+ if (!resource_size(res)) {
+ dev_err(&pdev->dev, "Zero DDR reg entry!\n");
+ return -EINVAL;
+ }
+
+ ddrc_hwmod_data->regs_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ddrc_hwmod_data->regs_base))
+ return PTR_ERR(ddrc_hwmod_data->regs_base);
+
+ init_hisi_ddr(ddrc_hwmod_data->regs_base);
+
+ return 0;
+}
+
+static int init_hisi_ddrc_data(struct platform_device *pdev,
+ struct hisi_pmu *ddrc_pmu)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ ddrc_pmu->hw_events.events = devm_kcalloc(dev,
+ ddrc_pmu->num_counters,
+ sizeof(*ddrc_pmu->hw_events.events),
+ GFP_KERNEL);
+ if (!ddrc_pmu->hw_events.events) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ raw_spin_lock_init(&ddrc_pmu->hw_events.pmu_lock);
+
+ init_hisi_ddrc_dts_data(pdev, ddrc_pmu->hwmod_data);
+
+ return 0;
+
+fail:
+ hisi_free_ddrc_data(ddrc_pmu);
+ return ret;
+}
+
+static struct attribute *hisi_ddrc_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-11"),
+ NULL,
+};
+
+static struct attribute_group hisi_ddrc_format_group = {
+ .name = "format",
+ .attrs = hisi_ddrc_format_attr,
+};
+
+static struct attribute *hisi_ddrc_events_attr[] = {
+ HISI_PMU_EVENT_ATTR_STR(flux_write, "event=0x00"),
+ HISI_PMU_EVENT_ATTR_STR(flux_read, "event=0x01"),
+ HISI_PMU_EVENT_ATTR_STR(flux_write_cmd, "event=0x02"),
+ HISI_PMU_EVENT_ATTR_STR(flux_read_cmd, "event=0x03"),
+ HISI_PMU_EVENT_ATTR_STR(fluxid_write, "event=0x04"),
+ HISI_PMU_EVENT_ATTR_STR(fluxid_read, "event=0x05"),
+ HISI_PMU_EVENT_ATTR_STR(fluxid_write_cmd, "event=0x06"),
+ HISI_PMU_EVENT_ATTR_STR(fluxid_read_cmd, "event=0x07"),
+ HISI_PMU_EVENT_ATTR_STR(write_latency_cnt0,
+ "event=0x08"),
+ HISI_PMU_EVENT_ATTR_STR(read_latency_cnt0,
+ "event=0x09"),
+ HISI_PMU_EVENT_ATTR_STR(write_latency_cnt1,
+ "event=0x0A"),
+ HISI_PMU_EVENT_ATTR_STR(read_latency_cnt1,
+ "event=0x0B"),
+ HISI_PMU_EVENT_ATTR_STR(read_latency_cnt_inher,
+ "event=0x0C"),
+ NULL,
+};
+
+static struct attribute_group hisi_ddrc_events_group = {
+ .name = "events",
+ .attrs = hisi_ddrc_events_attr,
+};
+
+static struct attribute *hisi_ddrc_attrs[] = {
+ NULL,
+};
+
+struct attribute_group hisi_ddrc_attr_group = {
+ .attrs = hisi_ddrc_attrs,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_ddrc_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_ddrc_cpumask_attr_group = {
+ .attrs = hisi_ddrc_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_ddrc_pmu_attr_groups[] = {
+ &hisi_ddrc_attr_group,
+ &hisi_ddrc_format_group,
+ &hisi_ddrc_events_group,
+ &hisi_ddrc_cpumask_attr_group,
+ NULL,
+};
+
+static struct hisi_uncore_ops hisi_uncore_ddrc_ops = {
+ .set_event_period = hisi_ddrc_set_event_period,
+ .get_event_idx = hisi_ddrc_get_event_idx,
+ .clear_event_idx = hisi_clear_ddrc_event_idx,
+ .event_update = hisi_ddrc_event_update,
+ .write_counter = hisi_write_ddrc_counter,
+};
+
+static int hisi_ddrc_pmu_init(struct device *dev,
+ struct hisi_pmu *ddrc_pmu)
+{
+ struct hisi_ddrc_data *ddrc_hwmod_data;
+ struct hisi_ddrc_hwcfg *ddrc_hwcfg;
+ int ret;
+
+ /* Read common PMU properties */
+ ret = hisi_uncore_common_fwprop_read(dev, ddrc_pmu);
+ if (ret)
+ return ret;
+
+ ddrc_hwmod_data = kzalloc(sizeof(struct hisi_ddrc_data),
+ GFP_KERNEL);
+ if (!ddrc_hwmod_data)
+ return -ENOMEM;
+
+ ddrc_hwcfg = &ddrc_hwmod_data->ddrc_hwcfg;
+ if (of_property_read_u32(dev->of_node, "ch-id",
+ &ddrc_hwcfg->channel_id)) {
+ kfree(ddrc_hwmod_data);
+ return -EINVAL;
+ }
+
+ ddrc_pmu->name = kasprintf(GFP_KERNEL, "hisi_ddrc%d_%d",
+ ddrc_pmu->scl_id, ddrc_hwcfg->channel_id);
+
+ ddrc_pmu->ops = &hisi_uncore_ddrc_ops;
+ ddrc_pmu->hwmod_data = ddrc_hwmod_data;
+ ddrc_pmu->dev = dev;
+
+ /* Pick one core to use for cpumask attributes */
+ cpumask_set_cpu(smp_processor_id(), &ddrc_pmu->cpu);
+
+ return 0;
+}
+
+static const struct of_device_id ddrc_of_match[] = {
+ { .compatible = "hisilicon,hisi-pmu-ddrc-v1", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ddrc_of_match);
+
+static int hisi_pmu_ddrc_dev_probe(struct platform_device *pdev)
+{
+ struct hisi_pmu *ddrc_pmu;
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *of_id;
+ int ret;
+
+ of_id = of_match_device(ddrc_of_match, dev);
+ if (!of_id)
+ return -EINVAL;
+
+ ddrc_pmu = hisi_pmu_alloc(dev);
+ if (IS_ERR(ddrc_pmu))
+ return PTR_ERR(ddrc_pmu);
+
+ ret = hisi_ddrc_pmu_init(dev, ddrc_pmu);
+ if (ret)
+ return ret;
+
+ ret = init_hisi_ddrc_data(pdev, ddrc_pmu);
+ if (ret)
+ goto fail_init;
+
+ /* Register with perf PMU */
+ ddrc_pmu->pmu = (struct pmu) {
+ .name = ddrc_pmu->name,
+ .task_ctx_nr = perf_invalid_context,
+ .event_init = hisi_uncore_pmu_event_init,
+ .add = hisi_uncore_pmu_add,
+ .del = hisi_uncore_pmu_del,
+ .start = hisi_uncore_pmu_start,
+ .stop = hisi_uncore_pmu_stop,
+ .read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_ddrc_pmu_attr_groups,
+ };
+
+ ret = hisi_uncore_pmu_setup(ddrc_pmu, ddrc_pmu->name);
+ if (ret) {
+ dev_err(ddrc_pmu->dev, "hisi_uncore_pmu_init FAILED!!\n");
+ goto fail;
+ }
+
+ platform_set_drvdata(pdev, ddrc_pmu);
+
+ return 0;
+fail:
+ hisi_free_ddrc_data(ddrc_pmu);
+
+fail_init:
+ dev_err(ddrc_pmu->dev, "%s failed\n", __func__);
+
+ return ret;
+}
+
+static int hisi_pmu_ddrc_dev_remove(struct platform_device *pdev)
+{
+ struct hisi_pmu *ddrc_pmu = platform_get_drvdata(pdev);
+
+ perf_pmu_unregister(&ddrc_pmu->pmu);
+ hisi_free_ddrc_data(ddrc_pmu);
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+}
+
+static struct platform_driver hisi_pmu_ddrc_driver = {
+ .driver = {
+ .name = "hisi-pmu-ddrc",
+ .of_match_table = ddrc_of_match,
+ },
+ .probe = hisi_pmu_ddrc_dev_probe,
+ .remove = hisi_pmu_ddrc_dev_remove,
+};
+module_platform_driver(hisi_pmu_ddrc_driver);
+
+MODULE_DESCRIPTION("HiSilicon SoC HIP0x DDRC PMU driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Anurup M");
diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc.h b/drivers/perf/hisilicon/hisi_uncore_ddrc.h
new file mode 100644
index 0000000..89eab6b
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_ddrc.h
@@ -0,0 +1,73 @@
+/*
+ * HiSilicon SoC DDRC Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Anurup M <anurup.m@huawei.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __HISI_UNCORE_DDRC_H__
+#define __HISI_UNCORE_DDRC_H__
+
+#include "hisi_uncore_pmu.h"
+
+/*
+ * ARMv8 HiSilicon DDRC event types.
+ */
+enum armv8_hisi_ddrc_event_types {
+ HISI_HWEVENT_DDRC_FLUX_WR = 0x0,
+ HISI_HWEVENT_DDRC_FLUX_RD = 0x01,
+ HISI_HWEVENT_DDRC_FLUX_WCMD = 0x02,
+ HISI_HWEVENT_DDRC_FLUX_RCMD = 0x03,
+ HISI_HWEVENT_DDRC_FLUXID_WD = 0x04,
+ HISI_HWEVENT_DDRC_FLUXID_RD = 0x05,
+ HISI_HWEVENT_DDRC_FLUXID_WCMD = 0x06,
+ HISI_HWEVENT_DDRC_FLUXID_RCMD = 0x07,
+ HISI_HWEVENT_DDRC_WLAT_CNT0 = 0x08,
+ HISI_HWEVENT_DDRC_RLAT_CNT0 = 0x09,
+ HISI_HWEVENT_DDRC_WLAT_CNT1 = 0x0A,
+ HISI_HWEVENT_DDRC_RLAT_CNT1 = 0x0B,
+ HISI_HWEVENT_DDRC_INHERE_RLAT_CNT = 0x0C,
+ HISI_HWEVENT_DDRC_MAX_EVENT,
+};
+
+#define HISI_DDRC_CTRL_PERF_REG_OFF 0x010
+#define HISI_DDRC_CFG_PERF_REG_OFF 0x270
+#define HISI_DDRC_FLUX_WR_REG_OFF 0x380
+#define HISI_DDRC_FLUX_RD_REG_OFF 0x384
+#define HISI_DDRC_FLUX_WCMD_REG_OFF 0x388
+#define HISI_DDRC_FLUX_RCMD_REG_OFF 0x38C
+#define HISI_DDRC_FLUXID_WR_REG_OFF 0x390
+#define HISI_DDRC_FLUXID_RD_REG_OFF 0x394
+#define HISI_DDRC_FLUXID_WCMD_REG_OFF 0x398
+#define HISI_DDRC_FLUXID_RCMD_REG_OFF 0x39C
+#define HISI_DDRC_FLUX_WLATCNT0_REG_OFF 0x3A0
+#define HISI_DDRC_FLUX_RLAT_CNT0_REG_OFF 0x3A4
+#define HISI_DDRC_FLUX_WLATCNT1_REG_OFF 0x3A8
+#define HISI_DDRC_FLUX_RLAT_CNT1_REG_OFF 0x3AC
+
+struct hisi_ddrc_hwcfg {
+ u32 channel_id;
+};
+
+struct hisi_ddrc_data {
+ void __iomem *regs_base;
+ DECLARE_BITMAP(hisi_ddrc_event_used_mask,
+ HISI_HWEVENT_DDRC_MAX_EVENT);
+ struct hisi_ddrc_hwcfg ddrc_hwcfg;
+};
+
+#endif /* __HISI_UNCORE_DDRC_H__ */
--
2.1.4
^ permalink raw reply related
* [PATCH v1 11/11] dts: arm64: hip06: Add Hisilicon SoC PMU support
From: Anurup M @ 2016-11-02 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478101374-18778-1-git-send-email-anurup.m@huawei.com>
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
3. Add nodes for hip06 DDRC to support uncore events.
Signed-off-by: Anurup M <anurup.m@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 116 +++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index cb9e018..9ff3afe 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -980,6 +980,122 @@
status = "disabled";
};
+ djtag0: djtag at 60010000 {
+ compatible = "hisilicon,hip06-cpu-djtag-v1";
+ reg = <0x0 0x60010000 0x0 0x10000>;
+
+ /* L3 cache for socket0 CPU die scl#2 */
+ pmul3c0 {
+ compatible = "hisilicon,hisi-pmu-l3c-v1";
+ scl-id = <0x02>;
+ num-events = <0x16>;
+ num-counters = <0x08>;
+ module-id = <0x04 0x04 0x04 0x04>;
+ num-banks = <0x04>;
+ cfgen-map = <0x02 0x04 0x01 0x08>;
+ counter-reg = <0x170>;
+ evctrl-reg = <0x04>;
+ event-en = <0x1000000>;
+ evtype-reg = <0x140>;
+ };
+
+ /* Miscellaneous node for socket0
+ * CPU die scl#2
+ */
+ pmumn0 {
+ compatible = "hisilicon,hisi-pmu-mn-v1";
+ scl-id = <0x02>;
+ num-events = <0x09>;
+ num-counters = <0x04>;
+ module-id = <0x0b>;
+ cfgen-map = <0x01>;
+ counter-reg = <0x30>;
+ evctrl-reg = <0x40>;
+ event-en = <0x01>;
+ evtype-reg = <0x48>;
+ };
+ };
+
+ djtag1: djtag at 40010000 {
+ compatible = "hisilicon,hip06-cpu-djtag-v1";
+ reg = <0x0 0x40010000 0x0 0x10000>;
+
+ /* L3 cache for socket0 CPU die scl#1 */
+ pmul3c1 {
+ compatible = "hisilicon,hisi-pmu-l3c-v1";
+ scl-id = <0x01>;
+ num-events = <0x16>;
+ num-counters = <0x08>;
+ module-id = <0x04 0x04 0x04 0x04>;
+ num-banks = <0x04>;
+ cfgen-map = <0x02 0x04 0x01 0x08>;
+ counter-reg = <0x170>;
+ evctrl-reg = <0x04>;
+ event-en = <0x1000000>;
+ evtype-reg = <0x140>;
+ };
+
+ /* Miscellaneous node for socket0
+ * CPU die scl#1
+ */
+ pmumn1 {
+ compatible = "hisilicon,hisi-pmu-mn-v1";
+ scl-id = <0x01>;
+ num-events = <0x09>;
+ num-counters = <0x04>;
+ module-id = <0x0b>;
+ cfgen-map = <0x01>;
+ counter-reg = <0x30>;
+ evctrl-reg = <0x40>;
+ event-en = <0x01>;
+ evtype-reg = <0x48>;
+ };
+ };
+
+ /* DDRC for CPU die scl #1 Channel #0 */
+ pmu_sccl0_ddrc0: pmu_ddrc0 at 40348000 {
+ compatible = "hisilicon,hisi-pmu-ddrc-v1";
+ scl-id = <0x01>;
+ ch-id = <0x0>;
+ num-events = <0x0d>;
+ num-counters = <0x04>;
+ reg = <0x0 0x40348000 0x0 0x10000>; /* TOTEMA DDRC0 */
+ status = "okay";
+ };
+
+ /* DDRC for CPU die scl #1 Channel #1 */
+ pmu_sccl0_ddrc1: pmu_ddrc1 at 40358000 {
+ compatible = "hisilicon,hisi-pmu-ddrc-v1";
+ scl-id = <0x01>;
+ ch-id = <0x01>;
+ num-events = <0x0d>;
+ num-counters = <0x04>;
+ reg = <0x0 0x40358000 0x0 0x10000>; /* TOTEMA DDRC1 */
+ status = "okay";
+ };
+
+ /* DDRC for CPU die scl #2 Channel #0 */
+ pmu_sccl1_ddrc0: pmu_ddrc0 at 60348000 {
+ compatible = "hisilicon,hisi-pmu-ddrc-v1";
+ scl-id = <0x02>;
+ ch-id = <0x0>;
+ num-events = <0x0d>;
+ num-counters = <0x04>;
+ reg = <0x0 0x60348000 0x0 0x10000>; /* TOTEMC DDRC0 */
+ status = "okay";
+ };
+
+ /* DDRC for CPU die scl #2 Channel #1 */
+ pmu_sccl1_ddrc1: pmu_ddrc1 at 60358000 {
+ compatible = "hisilicon,hisi-pmu-ddrc-v1";
+ scl-id = <0x02>;
+ ch-id = <0x01>;
+ num-events = <0x0d>;
+ num-counters = <0x04>;
+ reg = <0x0 0x60358000 0x0 0x10000>; /* TOTEMC DDRC1 */
+ status = "okay";
+ };
+
sas1: sas at a2000000 {
compatible = "hisilicon,hip06-sas-v2";
reg = <0 0xa2000000 0 0x10000>;
--
2.1.4
^ permalink raw reply related
* [PATCH v7 RESEND 1/2] ASoC: samsung: Add DT bindings documentation for TM2 sound subsystem
From: Sylwester Nawrocki @ 2016-11-02 16:02 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds DT binding documentation for Exnos5433 based TM2
and TM2E boards sound subsystem.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes since v5:
- none.
Changes since v4:
- indentation changes.
Changes since v2:
- none.
Changes since initial version:
- dropped clocks, clock-names properties, instead properties from
the CODEC node will be used,
- property renames: 'samsung,model' -> 'model', 'samsung,i2s-controller'
-> 'i2s-controller', 'samsung,speaker-amplifier' -> 'audio-amplifier',
- added 'audio-codec' property.
---
.../bindings/sound/samsung,tm2-audio.txt | 38 ++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt
diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt
new file mode 100644
index 0000000..94442e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt
@@ -0,0 +1,38 @@
+Samsung Exynos5433 TM2(E) audio complex with WM5110 codec
+
+Required properties:
+
+ - compatible : "samsung,tm2-audio"
+ - model : the user-visible name of this sound complex
+ - audio-codec : the phandle of the wm5110 audio codec node,
+ as described in ../mfd/arizona.txt
+ - i2s-controller : the phandle of the I2S controller
+ - audio-amplifier : the phandle of the MAX98504 amplifier
+ - samsung,audio-routing : a list of the connections between audio components;
+ each entry is a pair of strings, the first being the
+ connection's sink, the second being the connection's
+ source; valid names for sources and sinks are the
+ WM5110's and MAX98504's pins and the jacks on the
+ board: HP, SPK, Main Mic, Sub Mic, Third Mic,
+ Headset Mic
+ - mic-bias-gpios : GPIO pin that enables the Main Mic bias regulator
+
+
+Example:
+
+sound {
+ compatible = "samsung,tm2-audio";
+ audio-codec = <&wm5110>;
+ i2s-controller = <&i2s0>;
+ audio-amplifier = <&max98504>;
+ mic-bias-gpios = <&gpr3 2 0>;
+ model = "wm5110";
+ samsung,audio-routing =
+ "HP", "HPOUT1L",
+ "HP", "HPOUT1R",
+ "SPK", "SPKOUT",
+ "SPKOUT", "HPOUT2L",
+ "SPKOUT", "HPOUT2R",
+ "Main Mic", "MICBIAS2",
+ "IN1R", "Main Mic";
+};
--
1.9.1
^ permalink raw reply related
* [PATCH v3 2/3] Documentation: dt: add bindings for ti-cpufreq
From: Dave Gerlach @ 2016-11-02 16:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102035941.GA10786@vireshk-i7>
Hi,
On 11/01/2016 10:59 PM, Viresh Kumar wrote:
> On 27-10-16, 16:41, Dave Gerlach wrote:
>> Add the device tree bindings document for the TI CPUFreq/OPP driver
>> on AM33xx and AM43xx SoCs. The operating-points-v2 binding allows us
>> to provide an opp-supported-hw property for each OPP to define when
>> it is available. This driver is responsible for reading and parsing
>> registers to determine which OPPs can be selectively enabled based
>> on the specific SoC in use by matching against the opp-supported-hw
>> data.
>>
>> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
>> ---
>> v2->v3:
>> - Move ti,syscon-* properties under opp table instead of cpu node, as
>> that is a better location for them.
>> - For the opp table do not use platform specific compatible strings
>> but instead a operating-points-v2-ti-cpu
>>
>> .../devicetree/bindings/cpufreq/ti-cpufreq.txt | 132 +++++++++++++++++++++
>> 1 file changed, 132 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
>>
>> diff --git a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
>> new file mode 100644
>> index 000000000000..467ad29c75c9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
>> @@ -0,0 +1,132 @@
>> +TI CPUFreq and OPP bindings
>> +================================
>> +
>> +Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx
>> +families support different OPPs depending on the silicon variant in use.
>> +The ti_cpufreq driver can use revision and an efuse value from the SoC to
>> +provide the OPP framework with supported hardware information. This is
>> +used to determine which OPPs from the operating-points-v2 table get enabled
>> +when it is parsed by the OPP framework.
>> +
>> +Required properties:
>> +--------------------
>> +In 'cpus' nodes:
>> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
>> +
>> +In 'operating-points-v2' table:
>> +- compatible: Should be 'operating-points-v2-ti-cpu' for am335x, am43xx,
>> + and dra7xx/am57xx SoCs
>> +- ti,syscon-efuse: Syscon phandle, offset to efuse register, efuse register
>> + mask, and efuse register shift to get the relevant bits
>> + that describe OPP availability.
>> +- ti,syscon-rev: Syscon and offset used to look up revision value on SoC.
>> +
>> +Optional properties:
>> +--------------------
>> +For each opp entry in 'operating-points-v2' table:
>> +- opp-supported-hw: Two bitfields indicating:
>> + 1. Which revision of the SoC the OPP is supported by
>> + 2. Which eFuse bits indicate this OPP is available
>> +
>> + A bitwise AND is performed against these values and if any bit
>> + matches, the OPP gets enabled. Not providing the property for an
>> + entry indicates that an OPP is always supported.
>> +
>> +Example:
>> +--------
>> +
>> +/* From arch/arm/boot/dts/am33xx.dtsi */
>> +cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu at 0 {
>> + compatible = "arm,cortex-a8";
>> + device_type = "cpu";
>> + reg = <0>;
>> +
>> + operating-points-v2 = <&cpu0_opp_table>;
>> +
>> + clocks = <&dpll_mpu_ck>;
>> + clock-names = "cpu";
>> +
>> + clock-latency = <300000>; /* From omap-cpufreq driver */
>> + };
>> +};
>> +
>> +/*
>> + * cpu0 has different OPPs depending on SoC revision and some on revisions
>> + * 0x2 and 0x4 have eFuse bits that indicate if they are available or not
>> + */
>> +cpu0_opp_table: opp_table0 {
>> + compatible = "operating-points-v2-ti-am3352-cpu";
>> + ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
>> + ti,syscon-rev = <&scm_conf 0x600>;
>> +
>> + /*
>> + * The three following nodes are marked with opp-suspend
>> + * because they can not be enabled simultaneously on a
>> + * single SoC.
>> + */
>> + opp50 at 300000000 {
>> + opp-hz = /bits/ 64 <300000000>;
>> + opp-microvolt = <950000 931000 969000>;
>> + opp-supported-hw = <0x06 0x0010>;
>> + opp-suspend;
>> + };
>> +
>> + opp100 at 275000000 {
>> + opp-hz = /bits/ 64 <275000000>;
>> + opp-microvolt = <1100000 1078000 1122000>;
>> + opp-supported-hw = <0x01 0x00FF>;
>> + opp-suspend;
>> + };
>> +
>> + opp100 at 300000000 {
>> + opp-hz = /bits/ 64 <300000000>;
>> + opp-microvolt = <1100000 1078000 1122000>;
>> + opp-supported-hw = <0x06 0x0020>;
>> + opp-suspend;
>
> Only one OPP in the table can be marked as suspend OPP.
>
Does that still apply when opp-supported-hw is involved? Based on the
comment at the start of the table, those OPPs are all mutually exclusive
and will not ever be enabled on the same piece of silicon, they
represent the lowest OPP for each of three different supported-hw
configurations.
Regards,
Dave
^ permalink raw reply
* [PATCH v7 RESEND 2/2] ASoC: samsung: Add machine driver for Exynos5433 based TM2 board
From: Sylwester Nawrocki @ 2016-11-02 16:05 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the sound machine driver for the TM2 and TM2E boards.
Speaker and headphone playback, Main Mic capture, Bluetooth, Voice
call and external accessory are supported.
Signed-off-by: Inha Song <ideal.song@samsung.com>
[k.kozlowski: rebased on 4.1]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
[s.nawrocki: rebased to 4.7, adjustment to the ASoC core changes,
removed unused ops and direct calls to the max98504 function,
added parsing of "audio-amplifier" and "audio-codec"
properties, added TDM API calls, switched to gpiod API]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
---
Changes since v6:
- removed unused variables.
Changes since v5:
- dropped requesting and managing of the CODEC's clocks,
- removed driver remove() handler,
- changed pm_ops to use prepare/complete rather than
late_suspend/early_resume.
Changes since v4 (addressing review comments from Charles):
- changed the order of WM5110_FLL{1,2}, WM5110_FLL{1,2}_REFCLK setting,
- ARIZONA_CLK_SYSCLK, ARIZONA_CLK_ASYNCCLK setting moved to late_probe,
- added tm2_aif2_hw_free callback for disabling FLL2,
- removed unneded card->dapm.bias_level assignment in tm2_mic_bias callback,
- suspend_late, resume_early dev_pm_ops used instead of suspend_post,
resume_pre struct snd_soc_card callbacks.
Changes since v3:
- removed SND_SOC_SAMSUNG_AUDSS from Kconfig.
Changes since v2:
- added missing Kconfig dependencies.
Changes since initial version:
- added PDM Tx channels setup through TDM API
- adaptation to renamed 'samsung,model', 'samsung,i2s-controller',
'samsung,speaker-amplifier' properties,
- removed some dev_dbg() calls,
- cleaned up mic-bias GPIO handling and switched to gpiod API,
- added parsing of 'audio-codec' property,
- initialized codec_of_node of dai_link instead of codec_name,
- switched to using clock, clock-names properties from the wm5110
codec node,
- fixed error paths in probe() (of_node reference counting).
sound/soc/samsung/Kconfig | 9 +
sound/soc/samsung/Makefile | 2 +
sound/soc/samsung/tm2_wm5110.c | 552 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 563 insertions(+)
create mode 100644 sound/soc/samsung/tm2_wm5110.c
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index f6023b4..6b5b048 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -229,4 +229,13 @@ config SND_SOC_ARNDALE_RT5631_ALC5631
select SND_SAMSUNG_I2S
select SND_SOC_RT5631
+config SND_SOC_SAMSUNG_TM2_WM5110
+ tristate "SoC I2S Audio support for WM5110 on TM2 board"
+ depends on SND_SOC_SAMSUNG && MFD_ARIZONA && I2C && SPI_MASTER
+ select SND_SOC_MAX98504
+ select SND_SOC_WM5110
+ select SND_SAMSUNG_I2S
+ help
+ Say Y if you want to add support for SoC audio on the TM2 board.
+
endif #SND_SOC_SAMSUNG
diff --git a/sound/soc/samsung/Makefile b/sound/soc/samsung/Makefile
index 5d03f5c..4444b9f 100644
--- a/sound/soc/samsung/Makefile
+++ b/sound/soc/samsung/Makefile
@@ -44,6 +44,7 @@ snd-soc-lowland-objs := lowland.o
snd-soc-littlemill-objs := littlemill.o
snd-soc-bells-objs := bells.o
snd-soc-arndale-rt5631-objs := arndale_rt5631.o
+snd-soc-tm2-wm5110-objs := tm2_wm5110.o
obj-$(CONFIG_SND_SOC_SAMSUNG_JIVE_WM8750) += snd-soc-jive-wm8750.o
obj-$(CONFIG_SND_SOC_SAMSUNG_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o
@@ -69,3 +70,4 @@ obj-$(CONFIG_SND_SOC_LOWLAND) += snd-soc-lowland.o
obj-$(CONFIG_SND_SOC_LITTLEMILL) += snd-soc-littlemill.o
obj-$(CONFIG_SND_SOC_BELLS) += snd-soc-bells.o
obj-$(CONFIG_SND_SOC_ARNDALE_RT5631_ALC5631) += snd-soc-arndale-rt5631.o
+obj-$(CONFIG_SND_SOC_SAMSUNG_TM2_WM5110) += snd-soc-tm2-wm5110.o
diff --git a/sound/soc/samsung/tm2_wm5110.c b/sound/soc/samsung/tm2_wm5110.c
new file mode 100644
index 0000000..5cdf7d1
--- /dev/null
+++ b/sound/soc/samsung/tm2_wm5110.c
@@ -0,0 +1,552 @@
+/*
+ * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
+ *
+ * Authors: Inha Song <ideal.song@samsung.com>
+ * Sylwester Nawrocki <s.nawrocki@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include "i2s.h"
+#include "../codecs/wm5110.h"
+
+/*
+ * The source clock is XCLKOUT with its mux set to the external fixed rate
+ * oscillator (XXTI).
+ */
+#define MCLK_RATE 24000000U
+
+#define TM2_DAI_AIF1 0
+#define TM2_DAI_AIF2 1
+
+struct tm2_machine_priv {
+ struct snd_soc_codec *codec;
+ unsigned int sysclk_rate;
+ struct gpio_desc *gpio_mic_bias;
+};
+
+static int tm2_start_sysclk(struct snd_soc_card *card)
+{
+ struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(card);
+ struct snd_soc_codec *codec = priv->codec;
+ int ret;
+
+ ret = snd_soc_codec_set_pll(codec, WM5110_FLL1_REFCLK,
+ ARIZONA_FLL_SRC_MCLK1,
+ MCLK_RATE,
+ priv->sysclk_rate);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to set FLL1 source: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_codec_set_pll(codec, WM5110_FLL1,
+ ARIZONA_FLL_SRC_MCLK1,
+ MCLK_RATE,
+ priv->sysclk_rate);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to start FLL1: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_codec_set_sysclk(codec, ARIZONA_CLK_SYSCLK,
+ ARIZONA_CLK_SRC_FLL1,
+ priv->sysclk_rate,
+ SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to set SYSCLK source: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tm2_stop_sysclk(struct snd_soc_card *card)
+{
+ struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(card);
+ struct snd_soc_codec *codec = priv->codec;
+ int ret;
+
+ ret = snd_soc_codec_set_pll(codec, WM5110_FLL1, 0, 0, 0);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to stop FLL1: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_codec_set_sysclk(codec, ARIZONA_CLK_SYSCLK,
+ ARIZONA_CLK_SRC_FLL1, 0, 0);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to stop SYSCLK: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tm2_aif1_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_codec *codec = rtd->codec;
+ struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(rtd->card);
+
+ switch (params_rate(params)) {
+ case 4000:
+ case 8000:
+ case 12000:
+ case 16000:
+ case 24000:
+ case 32000:
+ case 48000:
+ case 96000:
+ case 192000:
+ /* Highest possible SYSCLK frequency: 147.456MHz */
+ priv->sysclk_rate = 147456000U;
+ break;
+ case 11025:
+ case 22050:
+ case 44100:
+ case 88200:
+ case 176400:
+ /* Highest possible SYSCLK frequency: 135.4752 MHz */
+ priv->sysclk_rate = 135475200U;
+ break;
+ default:
+ dev_err(codec->dev, "Not supported sample rate: %d\n",
+ params_rate(params));
+ return -EINVAL;
+ }
+
+ return tm2_start_sysclk(rtd->card);
+}
+
+static struct snd_soc_ops tm2_aif1_ops = {
+ .hw_params = tm2_aif1_hw_params,
+};
+
+static int tm2_aif2_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_codec *codec = rtd->codec;
+ unsigned int asyncclk_rate;
+ int ret;
+
+ switch (params_rate(params)) {
+ case 8000:
+ case 12000:
+ case 16000:
+ /* Highest possible ASYNCCLK frequency: 49.152MHz */
+ asyncclk_rate = 49152000U;
+ break;
+ case 11025:
+ /* Highest possible ASYNCCLK frequency: 45.1584 MHz */
+ asyncclk_rate = 45158400U;
+ break;
+ default:
+ dev_err(codec->dev, "Not supported sample rate: %d\n",
+ params_rate(params));
+ return -EINVAL;
+ }
+
+ ret = snd_soc_codec_set_pll(codec, WM5110_FLL2_REFCLK,
+ ARIZONA_FLL_SRC_MCLK1,
+ MCLK_RATE,
+ asyncclk_rate);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to set FLL2 source: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_codec_set_pll(codec, WM5110_FLL2,
+ ARIZONA_FLL_SRC_MCLK1,
+ MCLK_RATE,
+ asyncclk_rate);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to start FLL2: %d\n", ret);
+ return ret;
+ }
+
+ ret = snd_soc_codec_set_sysclk(codec, ARIZONA_CLK_ASYNCCLK,
+ ARIZONA_CLK_SRC_FLL2,
+ asyncclk_rate,
+ SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ dev_err(codec->dev, "Failed to set ASYNCCLK source: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tm2_aif2_hw_free(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_codec *codec = rtd->codec;
+ int ret;
+
+ /* disable FLL2 */
+ ret = snd_soc_codec_set_pll(codec, WM5110_FLL2, ARIZONA_FLL_SRC_MCLK1,
+ 0, 0);
+ if (ret < 0)
+ dev_err(codec->dev, "Failed to stop FLL2: %d\n", ret);
+
+ return ret;
+}
+
+static struct snd_soc_ops tm2_aif2_ops = {
+ .hw_params = tm2_aif2_hw_params,
+ .hw_free = tm2_aif2_hw_free,
+};
+
+static int tm2_mic_bias(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_card *card = w->dapm->card;
+ struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(card);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ gpiod_set_value_cansleep(priv->gpio_mic_bias, 1);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ gpiod_set_value_cansleep(priv->gpio_mic_bias, 0);
+ break;
+ }
+
+ return 0;
+}
+
+static int tm2_set_bias_level(struct snd_soc_card *card,
+ struct snd_soc_dapm_context *dapm,
+ enum snd_soc_bias_level level)
+{
+ struct snd_soc_pcm_runtime *rtd;
+
+ rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
+
+ if (dapm->dev != rtd->codec_dai->dev)
+ return 0;
+
+ switch (level) {
+ case SND_SOC_BIAS_STANDBY:
+ if (card->dapm.bias_level == SND_SOC_BIAS_OFF)
+ tm2_start_sysclk(card);
+ break;
+ case SND_SOC_BIAS_OFF:
+ tm2_stop_sysclk(card);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static struct snd_soc_aux_dev tm2_speaker_amp_dev;
+
+static int tm2_late_probe(struct snd_soc_card *card)
+{
+ struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(card);
+ struct snd_soc_dai_link_component dlc = { 0 };
+ unsigned int ch_map[] = { 0, 1 };
+ struct snd_soc_dai *amp_pdm_dai;
+ struct snd_soc_pcm_runtime *rtd;
+ struct snd_soc_dai *aif1_dai;
+ struct snd_soc_dai *aif2_dai;
+ int ret;
+
+ rtd = snd_soc_get_pcm_runtime(card, card->dai_link[TM2_DAI_AIF1].name);
+ aif1_dai = rtd->codec_dai;
+ priv->codec = rtd->codec;
+
+ ret = snd_soc_dai_set_sysclk(aif1_dai, ARIZONA_CLK_SYSCLK, 0, 0);
+ if (ret < 0) {
+ dev_err(aif1_dai->dev, "Failed to set SYSCLK: %d\n", ret);
+ return ret;
+ }
+
+ rtd = snd_soc_get_pcm_runtime(card, card->dai_link[TM2_DAI_AIF2].name);
+ aif2_dai = rtd->codec_dai;
+
+ ret = snd_soc_dai_set_sysclk(aif2_dai, ARIZONA_CLK_ASYNCCLK, 0, 0);
+ if (ret < 0) {
+ dev_err(aif2_dai->dev, "Failed to set ASYNCCLK: %d\n", ret);
+ return ret;
+ }
+
+ dlc.of_node = tm2_speaker_amp_dev.codec_of_node;
+ amp_pdm_dai = snd_soc_find_dai(&dlc);
+ if (!amp_pdm_dai)
+ return -ENODEV;
+
+ /* Set the MAX98504 V/I sense PDM Tx DAI channel mapping */
+ ret = snd_soc_dai_set_channel_map(amp_pdm_dai, ARRAY_SIZE(ch_map),
+ ch_map, 0, NULL);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_tdm_slot(amp_pdm_dai, 0x3, 0x0, 2, 16);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static const struct snd_kcontrol_new tm2_controls[] = {
+ SOC_DAPM_PIN_SWITCH("HP"),
+ SOC_DAPM_PIN_SWITCH("SPK"),
+ SOC_DAPM_PIN_SWITCH("RCV"),
+ SOC_DAPM_PIN_SWITCH("VPS"),
+ SOC_DAPM_PIN_SWITCH("HDMI"),
+
+ SOC_DAPM_PIN_SWITCH("Main Mic"),
+ SOC_DAPM_PIN_SWITCH("Sub Mic"),
+ SOC_DAPM_PIN_SWITCH("Third Mic"),
+
+ SOC_DAPM_PIN_SWITCH("Headset Mic"),
+};
+
+const struct snd_soc_dapm_widget tm2_dapm_widgets[] = {
+ SND_SOC_DAPM_HP("HP", NULL),
+ SND_SOC_DAPM_SPK("SPK", NULL),
+ SND_SOC_DAPM_SPK("RCV", NULL),
+ SND_SOC_DAPM_LINE("VPS", NULL),
+ SND_SOC_DAPM_LINE("HDMI", NULL),
+
+ SND_SOC_DAPM_MIC("Main Mic", tm2_mic_bias),
+ SND_SOC_DAPM_MIC("Sub Mic", NULL),
+ SND_SOC_DAPM_MIC("Third Mic", NULL),
+
+ SND_SOC_DAPM_MIC("Headset Mic", NULL),
+};
+
+static const struct snd_soc_component_driver tm2_component = {
+ .name = "tm2-audio",
+};
+
+static struct snd_soc_dai_driver tm2_ext_dai[] = {
+ {
+ .name = "Voice call",
+ .playback = {
+ .channels_min = 1,
+ .channels_max = 4,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_48000),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ .capture = {
+ .channels_min = 1,
+ .channels_max = 4,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_48000),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ },
+ {
+ .name = "Bluetooth",
+ .playback = {
+ .channels_min = 1,
+ .channels_max = 4,
+ .rate_min = 8000,
+ .rate_max = 16000,
+ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ .capture = {
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 16000,
+ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ },
+};
+
+static struct snd_soc_dai_link tm2_dai_links[] = {
+ {
+ .name = "WM5110 AIF1",
+ .stream_name = "HiFi Primary",
+ .codec_dai_name = "wm5110-aif1",
+ .ops = &tm2_aif1_ops,
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM,
+ }, {
+ .name = "WM5110 Voice",
+ .stream_name = "Voice call",
+ .codec_dai_name = "wm5110-aif2",
+ .ops = &tm2_aif2_ops,
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM,
+ .ignore_suspend = 1,
+ }, {
+ .name = "WM5110 BT",
+ .stream_name = "Bluetooth",
+ .codec_dai_name = "wm5110-aif3",
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM,
+ .ignore_suspend = 1,
+ }
+};
+
+static struct snd_soc_card tm2_card = {
+ .owner = THIS_MODULE,
+
+ .dai_link = tm2_dai_links,
+ .num_links = ARRAY_SIZE(tm2_dai_links),
+ .controls = tm2_controls,
+ .num_controls = ARRAY_SIZE(tm2_controls),
+ .dapm_widgets = tm2_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(tm2_dapm_widgets),
+ .aux_dev = &tm2_speaker_amp_dev,
+ .num_aux_devs = 1,
+
+ .late_probe = tm2_late_probe,
+ .set_bias_level = tm2_set_bias_level,
+};
+
+static int tm2_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct snd_soc_card *card = &tm2_card;
+ struct tm2_machine_priv *priv;
+ struct device_node *cpu_dai_node, *codec_dai_node;
+ int ret, i;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ snd_soc_card_set_drvdata(card, priv);
+ card->dev = dev;
+
+ priv->gpio_mic_bias = devm_gpiod_get(dev, "mic-bias",
+ GPIOF_OUT_INIT_LOW);
+ if (IS_ERR(priv->gpio_mic_bias)) {
+ dev_err(dev, "Failed to get mic bias gpio\n");
+ return PTR_ERR(priv->gpio_mic_bias);
+ }
+
+ ret = snd_soc_of_parse_card_name(card, "model");
+ if (ret < 0) {
+ dev_err(dev, "Card name is not specified\n");
+ return ret;
+ }
+
+ ret = snd_soc_of_parse_audio_routing(card, "samsung,audio-routing");
+ if (ret < 0) {
+ dev_err(dev, "Audio routing is not specified or invalid\n");
+ return ret;
+ }
+
+ card->aux_dev[0].codec_of_node = of_parse_phandle(dev->of_node,
+ "audio-amplifier", 0);
+ if (!card->aux_dev[0].codec_of_node) {
+ dev_err(dev, "audio-amplifier property invalid or missing\n");
+ return -EINVAL;
+ }
+
+ cpu_dai_node = of_parse_phandle(dev->of_node, "i2s-controller", 0);
+ if (!cpu_dai_node) {
+ dev_err(dev, "i2s-controllers property invalid or missing\n");
+ ret = -EINVAL;
+ goto amp_node_put;
+ }
+
+ codec_dai_node = of_parse_phandle(dev->of_node, "audio-codec", 0);
+ if (!codec_dai_node) {
+ dev_err(dev, "audio-codec property invalid or missing\n");
+ ret = -EINVAL;
+ goto cpu_dai_node_put;
+ }
+
+ for (i = 0; i < card->num_links; i++) {
+ card->dai_link[i].cpu_dai_name = NULL;
+ card->dai_link[i].cpu_name = NULL;
+ card->dai_link[i].platform_name = NULL;
+ card->dai_link[i].codec_of_node = codec_dai_node;
+ card->dai_link[i].cpu_of_node = cpu_dai_node;
+ card->dai_link[i].platform_of_node = cpu_dai_node;
+ }
+
+ ret = devm_snd_soc_register_component(dev, &tm2_component,
+ tm2_ext_dai, ARRAY_SIZE(tm2_ext_dai));
+ if (ret < 0) {
+ dev_err(dev, "Failed to register component: %d\n", ret);
+ goto codec_dai_node_put;
+ }
+
+ ret = devm_snd_soc_register_card(dev, card);
+ if (ret < 0) {
+ dev_err(dev, "Failed to register card: %d\n", ret);
+ goto codec_dai_node_put;
+ }
+
+codec_dai_node_put:
+ of_node_put(codec_dai_node);
+cpu_dai_node_put:
+ of_node_put(cpu_dai_node);
+amp_node_put:
+ of_node_put(card->aux_dev[0].codec_of_node);
+ return ret;
+}
+
+static int tm2_pm_prepare(struct device *dev)
+{
+ struct snd_soc_card *card = dev_get_drvdata(dev);
+
+ return tm2_stop_sysclk(card);
+}
+
+static void tm2_pm_complete(struct device *dev)
+{
+ struct snd_soc_card *card = dev_get_drvdata(dev);
+
+ tm2_start_sysclk(card);
+}
+
+const struct dev_pm_ops tm2_pm_ops = {
+ .prepare = tm2_pm_prepare,
+ .suspend = snd_soc_suspend,
+ .resume = snd_soc_resume,
+ .complete = tm2_pm_complete,
+ .freeze = snd_soc_suspend,
+ .thaw = snd_soc_resume,
+ .poweroff = snd_soc_poweroff,
+ .restore = snd_soc_resume,
+};
+
+static const struct of_device_id tm2_of_match[] = {
+ { .compatible = "samsung,tm2-audio" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, tm2_of_match);
+
+static struct platform_driver tm2_driver = {
+ .driver = {
+ .name = "tm2-audio",
+ .pm = &tm2_pm_ops,
+ .of_match_table = tm2_of_match,
+ },
+ .probe = tm2_probe,
+};
+module_platform_driver(tm2_driver);
+
+MODULE_AUTHOR("Inha Song <ideal.song@samsung.com>");
+MODULE_DESCRIPTION("ALSA SoC Exynos TM2 Audio Support");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related
* [PATCH] ARM: DT: stm32: move dma translation to board files
From: Bruno Herrera @ 2016-11-02 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3e854414-f51d-3e59-6cee-142106cef40f@st.com>
Hi
On Wed, Nov 2, 2016 at 12:32 PM, Alexandre Torgue
<alexandre.torgue@st.com> wrote:
> Hi
>
> On 10/31/2016 07:58 PM, Rados?aw Pietrzyk wrote:
>>
>> I think wlcore driver searches dma-ranges in its parent that's why sdio
>> node needs it.
>
>
> Yes I agree. In this case it is needed as you have subnode in sdio node.
> So IMO empty dma-ranges could be removed from ethernet and usb node, but
> kept in future sdio subnode.
Now it is clear.
>
> Bruno,
> Do you plan to push sdio support ?
Yes I do, but I'm not sure how long it will take. The I had to
change(and hack) the mmci code because I could not get the ID from
STM32 SDIO IP.
My current WIP is at @
https://github.com/mcoquelin-stm32/afboot-stm32/pull/4#issuecomment-247571615
I know Andrea Merello is also working on that (and he probably has a
more complete patch).
>
>
>
>>
>> 2016-10-31 17:41 GMT+01:00 Bruno Herrera <bruherrera@gmail.com
>> <mailto:bruherrera@gmail.com>>:
>>
>> On Mon, Oct 31, 2016 at 12:14 PM, Rados?aw Pietrzyk
>> <radoslaw.pietrzyk at gmail.com <mailto:radoslaw.pietrzyk@gmail.com>>
>> wrote:
>> > This is weird because dma ddresses are recalculated using parent's
>> > dma-ranges property and soc already has it so there should be
>> absolutely no
>> > problem.
>>
>> These are my DTS and DTSI file.
>> >
>> > 2016-10-31 11:27 GMT+01:00 Bruno Herrera <bruherrera@gmail.com
>> <mailto:bruherrera@gmail.com>>:
>> >>
>> >> On Fri, Oct 28, 2016 at 5:09 AM, Rados?aw Pietrzyk
>> >> <radoslaw.pietrzyk@gmail.com
>> <mailto:radoslaw.pietrzyk@gmail.com>> wrote:
>> >> > Have you defined your sdio node within soc node ?
>> >>
>> >> It is in the SOC node of the DSTI file.
>> >>
>> >> >
>> >> > 2016-10-27 14:57 GMT+02:00 Bruno Herrera <bruherrera@gmail.com
>> <mailto:bruherrera@gmail.com>>:
>> >> >>
>> >> >> Hi Alex,
>> >> >>
>> >> >> On Thu, Oct 27, 2016 at 10:21 AM, Alexandre Torgue
>> >> >> <alexandre.torgue at st.com <mailto:alexandre.torgue@st.com>>
>> wrote:
>> >> >> > Hi Bruno,
>> >> >> >
>> >> >> >
>> >> >> > On 10/27/2016 12:43 PM, Bruno Herrera wrote:
>> >> >> >>
>> >> >> >> Hi Alex,
>> >> >> >>
>> >> >> >> On Wed, Oct 26, 2016 at 7:09 AM, Alexandre Torgue
>> >> >> >> <alexandre.torgue at st.com <mailto:alexandre.torgue@st.com>>
>> wrote:
>> >> >> >>>
>> >> >> >>> Hi Bruno,
>> >> >> >>>
>> >> >> >>> On 10/25/2016 11:06 PM, Bruno Herrera wrote:
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>> Hi Alexandre,
>> >> >> >>>>
>> >> >> >>>>>
>> >> >> >>>>> stm32f469-disco and stm32f429-eval boards use SDRAM
>> start address
>> >> >> >>>>> remapping
>> >> >> >>>>> (to @0) to boost performances. A DMA translation through
>> >> >> >>>>> "dma-ranges"
>> >> >> >>>>> property was needed for other masters than the M4 CPU.
>> >> >> >>>>> stm32f429-disco doesn't use remapping so doesn't need
>> this DMA
>> >> >> >>>>> translation.
>> >> >> >>>>> This patches moves this DMA translation definition from
>> stm32f429
>> >> >> >>>>> soc
>> >> >> >>>>> file
>> >> >> >>>>> to board files.
>> >> >> >>>>>
>> >> >> >>>>> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com
>> <mailto:alexandre.torgue@st.com>>
>>
>> >> >> >>>>>
>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>>> index 13c7cd2..a763c15 100644
>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>>> @@ -82,6 +82,10 @@
>> >> >> >>>>> };
>> >> >> >>>>> };
>> >> >> >>>>>
>> >> >> >>>>> + soc {
>> >> >> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >> >>>>> + };
>> >> >> >>>>> +
>> >> >> >>>>> usbotg_hs_phy: usbphy {
>> >> >> >>>>> #phy-cells = <0>;
>> >> >> >>>>> compatible = "usb-nop-xceiv";
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>> Shouldn't also the peripheral dma-ranges property move to
>> board
>> >> >> >>>> specific
>> >> >> >>>> too?
>> >> >> >>>> I had this patch for while but I didn't had the time to
>> submit:
>> >> >> >>>
>> >> >> >>>
>> >> >> >>>
>> >> >> >>> Well spot I forgot it. Actually, discussing with Arnd
>> ysterday on
>> >> >> >>> IIRC,
>> >> >> >>> empty dma-ranges is not needed. Can you test on your side by
>> >> >> >>> removing
>> >> >> >>> dma-ranges in usb node please ?
>> >> >> >>
>> >> >> >> Unfortunately will take a time for me to set up this
>> environment on
>> >> >> >> the STM32F4-EVAL board.
>> >> >> >> And on the discovery boards we dont have this scenario.
>> That was the
>> >> >> >> main reason I did not submit the patch right away.
>> >> >> >> My conclusion and I might be wrong but is based on the my
>> tests with
>> >> >> >> SDIO device at STM32F469I-DISCO board.
>> >> >> >>
>> >> >> >> I started this issue as discussion at ST Forum but Maxime
>> gave me
>> >> >> >> the
>> >> >> >> hint.
>> >> >> >>
>> >> >> >>
>> >> >> >>
>> >> >> >>
>> >> >> >>
>>
>> https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B¤tviews=44
>>
>> <https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B¤tviews=44>
>> >> >> >>
>> >> >> >>> I will push a v2 by removing empty dma-ranges if tests are
>> ok in
>> >> >> >>> your
>> >> >> >>> side.
>> >> >> >>
>> >> >> >>
>> >> >> >> From my understating/conclusion is: when empty
>> property(dma-ranges)
>> >> >> >> is
>> >> >> >> the device node, the mapping will be taken in consideration
>> when
>> >> >> >> using
>> >> >> >> DMA otherwise the mapping is ignored.
>> >> >> >> And in the SDIO case it is needed for DEV->MEM(SDRAM) and
>> >> >> >> MEM(SDRAM)->DEV. If it is not the case for the devices in
>> question
>> >> >> >> so
>> >> >> >> I suppose it can work without the property.
>> >> >> >
>> >> >> >
>> >> >> > For sure translation has to be done but I'm not sure that an
>> empty
>> >> >> > "dma-ranges" is needed in device node to activate it. For
>> Ethernet
>> >> >> > empty
>> >> >> > "dma-ranges" is not needed. I will try with usb.
>> >> >>
>> >> >> In the case of SDIO it is needed. As example this is my
>> working SDIO
>> >> >> node:
>> >> >>
>> >> >> sdio: sdio at 40012c00 {
>> >> >> compatible = "arm,pl18x", "arm,primecell";
>> >> >> arm,primecell-periphid = <0x00480181>;
>> >> >> reg = <0x40012c00 0x400>;
>> >> >> dmas = <&dma2 6 4 0x10400 0x3>, /* Logical - DevToMem */
>> >> >> <&dma2 3 4 0x10400 0x3>; /* Logical - MemToDev */
>> >> >> dma-names = "rx", "tx";
>> >> >> clocks = <&rcc 0 171>;
>> >> >> clock-names = "apb_pclk";
>> >> >> interrupts = <49>;
>> >> >> status = "disabled";
>> >> >> };
>> >> >>
>> >> >> &sdio {
>> >> >> status = "okay";
>> >> >> vmmc-supply = <&wlan_en>;
>> >> >> bus-width = <4>;
>> >> >> max-frequency = <24000000>;
>> >> >> pinctrl-names = "default";
>> >> >> pinctrl-0 = <&sdio_pins>;
>> >> >> ti,non-removable;
>> >> >> ti,needs-special-hs-handling;
>> >> >> dma-ranges;
>> >> >> cap-power-off-card;
>> >> >> keep-power-in-suspend;
>> >> >>
>> >> >> #address-cells = <1>;
>> >> >> #size-cells = <0>;
>> >> >> wlcore: wlcore at 0 {
>> >> >> compatible = "ti,wl1835";
>> >> >> reg = <2>;
>> >> >> interrupt-parent = <&gpioa>;
>> >> >> interrupts = <8 IRQ_TYPE_EDGE_RISING>;
>> >> >> };
>> >> >> };
>> >> >>
>> >> >> >
>> >> >> > alex
>> >> >> >
>> >> >> >
>> >> >> >>
>> >> >> >>>
>> >> >> >>> Thanks in advance
>> >> >> >>> Alex
>> >> >> >>>
>> >> >> >>>
>> >> >> >>>>
>> >> >> >>>> Author: Bruno Herrera <bruherrera@gmail.com
>> <mailto:bruherrera@gmail.com>>
>>
>> >> >> >>>> Date: Sun Oct 16 14:50:00 2016 -0200
>> >> >> >>>>
>> >> >> >>>> ARM: DT: STM32: Use dma-ranges property per board not
>> at dtsi
>> >> >> >>>> file
>> >> >> >>>>
>> >> >> >>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>> index 6bfc595..2a22a82 100644
>> >> >> >>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>> @@ -52,6 +52,10 @@
>> >> >> >>>> model = "STMicroelectronics STM32429i-EVAL board";
>> >> >> >>>> compatible = "st,stm32429i-eval", "st,stm32f429";
>> >> >> >>>>
>> >> >> >>>> + soc {
>> >> >> >>>> + dma-ranges = <0xC0000000 0x0 0x10000000>;
>> >> >> >>>> + };
>> >> >> >>>> +
>> >> >> >>>> chosen {
>> >> >> >>>> bootargs = "root=/dev/ram rdinit=/linuxrc";
>> >> >> >>>> stdout-path = "serial0:115200n8";
>> >> >> >>>> @@ -96,6 +100,7 @@
>> >> >> >>>>
>> >> >> >>>> ðernet0 {
>> >> >> >>>> status = "okay";
>> >> >> >>>> + dma-ranges;
>> >> >> >>>> pinctrl-0 = <ðernet0_mii>;
>> >> >> >>>> pinctrl-names = "default";
>> >> >> >>>> phy-mode = "mii-id";
>> >> >> >>>> @@ -116,6 +121,7 @@
>> >> >> >>>> };
>> >> >> >>>>
>> >> >> >>>> &usbotg_hs {
>> >> >> >>>> + dma-ranges;
>> >> >> >>>> dr_mode = "host";
>> >> >> >>>> phys = <&usbotg_hs_phy>;
>> >> >> >>>> phy-names = "usb2-phy";
>> >> >> >>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>> b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>> index 7d624a2..697a133 100644
>> >> >> >>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>> @@ -59,7 +59,6 @@
>> >> >> >>>> };
>> >> >> >>>>
>> >> >> >>>> soc {
>> >> >> >>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >> >>>>
>> >> >> >>>> timer2: timer at 40000000 {
>> >> >> >>>> compatible = "st,stm32-timer";
>> >> >> >>>> @@ -472,13 +471,11 @@
>> >> >> >>>> st,syscon = <&syscfg 0x4>;
>> >> >> >>>> snps,pbl = <8>;
>> >> >> >>>> snps,mixed-burst;
>> >> >> >>>> - dma-ranges;
>> >> >> >>>> status = "disabled";
>> >> >> >>>> };
>> >> >> >>>>
>> >> >> >>>> usbotg_hs: usb at 40040000 {
>> >> >> >>>> compatible = "snps,dwc2";
>> >> >> >>>> - dma-ranges;
>> >> >> >>>> reg = <0x40040000 0x40000>;
>> >> >> >>>> interrupts = <77>;
>> >> >> >>>> clocks = <&rcc 0 29>;
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>>> b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>>> index 0596d60..3a1cfdd 100644
>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>>> @@ -59,8 +59,6 @@
>> >> >> >>>>> };
>> >> >> >>>>>
>> >> >> >>>>> soc {
>> >> >> >>>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >> >>>>> -
>> >> >> >>>>> timer2: timer at 40000000 {
>> >> >> >>>>> compatible = "st,stm32-timer";
>> >> >> >>>>> reg = <0x40000000 0x400>;
>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >> >>>>> b/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >> >>>>> index 9e73656..c2213c0 100644
>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >> >>>>> @@ -64,6 +64,10 @@
>> >> >> >>>>> aliases {
>> >> >> >>>>> serial0 = &usart3;
>> >> >> >>>>> };
>> >> >> >>>>> +
>> >> >> >>>>> + soc {
>> >> >> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >> >>>>> + };
>> >> >> >>>>> };
>> >> >> >>>>>
>> >> >> >>>>> &clk_hse {
>> >> >> >>>>> --
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>> Br.,
>> >> >> >>>> Bruno
>> >> >> >>>>
>> >> >> >>>
>> >> >> >
>> >> >>
>> >> >> _______________________________________________
>> >> >> linux-arm-kernel mailing list
>> >> >> linux-arm-kernel at lists.infradead.org
>> <mailto:linux-arm-kernel@lists.infradead.org>
>> >> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>
>> >> >
>> >> >
>> >
>> >
>>
>>
>
^ permalink raw reply
* [PATCHv2] PCI: QDF2432 32 bit config space accessors
From: Bjorn Helgaas @ 2016-11-02 16:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <dbf40b73baa71155f39e13d6e51073aa@codeaurora.org>
On Tue, Nov 01, 2016 at 07:06:31AM -0600, cov at codeaurora.org wrote:
> Hi Bjorn,
>
> On 2016-10-31 15:48, Bjorn Helgaas wrote:
> >On Wed, Sep 21, 2016 at 06:38:05PM -0400, Christopher Covington wrote:
> >>The Qualcomm Technologies QDF2432 SoC does not support accesses
> >>smaller
> >>than 32 bits to the PCI configuration space. Register the appropriate
> >>quirk.
> >>
> >>Signed-off-by: Christopher Covington <cov@codeaurora.org>
> >
> >Hi Christopher,
> >
> >Can you rebase this against v4.9-rc1? It no longer applies to my tree.
>
> I apologize for not being clearer. This patch depends on:
>
> PCI/ACPI: Extend pci_mcfg_lookup() responsibilities
> PCI/ACPI: Check platform-specific ECAM quirks
>
> These patches from Tomasz Nowicki were previously in your pci/ecam-v6
> branch, but that seems to have come and gone. How would you like to
> proceed?
Oh yes, that's right, I forgot that connection. I'm afraid I kind of
dropped the ball on that thread, so I went back and read through it
again.
I *think* the current state is:
- I'm OK with the first two patches that add the quirk
infrastructure.
- My issue with the last three patches that add ThunderX quirks is
that there's no generic description of the ECAM address space.
So if I understand correctly, your Qualcomm patch depends only on the
first two patches.
Then the question is how the Qualcomm ECAM address space is described.
Your quirk overrides the default pci_generic_ecam_ops with the
&pci_32b_ops, but it doesn't touch the address space part, so I assume
the bus ranges and corresponding address space in your MCFG is
correct. So far, so good.
Is there also an ACPI device that contains that space in _CRS? I
think we concluded that the standard solution is to describe this with
a PNP0C02 device.
Would you mind opening a bugzilla at bugzilla.kernel.org and attaching
the dmesg log, /proc/iomem, and maybe a DSDT dump? I'd like to have
something to point at to say "if you need an MCFG quirk, you need the
MCFG bit and *also* these other related ACPI device bits, and here's
how it should be done."
Bjorn
^ permalink raw reply
* [PATCH] ARM: DT: stm32: move dma translation to board files
From: Alexandre Torgue @ 2016-11-02 16:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAF3+TqeiPjtG7Fs1-cpbcHGxxtSS1UOGD=S=sggpaZahFLJhEQ@mail.gmail.com>
On 11/02/2016 05:07 PM, Bruno Herrera wrote:
> Hi
>
> On Wed, Nov 2, 2016 at 12:32 PM, Alexandre Torgue
> <alexandre.torgue@st.com> wrote:
>> Hi
>>
>> On 10/31/2016 07:58 PM, Rados?aw Pietrzyk wrote:
>>>
>>> I think wlcore driver searches dma-ranges in its parent that's why sdio
>>> node needs it.
>>
>>
>> Yes I agree. In this case it is needed as you have subnode in sdio node.
>> So IMO empty dma-ranges could be removed from ethernet and usb node, but
>> kept in future sdio subnode.
>
> Now it is clear.
Nice. Can I add your tested-by ?
>
>>
>> Bruno,
>> Do you plan to push sdio support ?
>
> Yes I do, but I'm not sure how long it will take. The I had to
> change(and hack) the mmci code because I could not get the ID from
> STM32 SDIO IP.
> My current WIP is at @
> https://github.com/mcoquelin-stm32/afboot-stm32/pull/4#issuecomment-247571615
> I know Andrea Merello is also working on that (and he probably has a
> more complete patch).
>
>>
>>
>>
>>>
>>> 2016-10-31 17:41 GMT+01:00 Bruno Herrera <bruherrera@gmail.com
>>> <mailto:bruherrera@gmail.com>>:
>>>
>>> On Mon, Oct 31, 2016 at 12:14 PM, Rados?aw Pietrzyk
>>> <radoslaw.pietrzyk at gmail.com <mailto:radoslaw.pietrzyk@gmail.com>>
>>> wrote:
>>> > This is weird because dma ddresses are recalculated using parent's
>>> > dma-ranges property and soc already has it so there should be
>>> absolutely no
>>> > problem.
>>>
>>> These are my DTS and DTSI file.
>>> >
>>> > 2016-10-31 11:27 GMT+01:00 Bruno Herrera <bruherrera@gmail.com
>>> <mailto:bruherrera@gmail.com>>:
>>> >>
>>> >> On Fri, Oct 28, 2016 at 5:09 AM, Rados?aw Pietrzyk
>>> >> <radoslaw.pietrzyk@gmail.com
>>> <mailto:radoslaw.pietrzyk@gmail.com>> wrote:
>>> >> > Have you defined your sdio node within soc node ?
>>> >>
>>> >> It is in the SOC node of the DSTI file.
>>> >>
>>> >> >
>>> >> > 2016-10-27 14:57 GMT+02:00 Bruno Herrera <bruherrera@gmail.com
>>> <mailto:bruherrera@gmail.com>>:
>>> >> >>
>>> >> >> Hi Alex,
>>> >> >>
>>> >> >> On Thu, Oct 27, 2016 at 10:21 AM, Alexandre Torgue
>>> >> >> <alexandre.torgue at st.com <mailto:alexandre.torgue@st.com>>
>>> wrote:
>>> >> >> > Hi Bruno,
>>> >> >> >
>>> >> >> >
>>> >> >> > On 10/27/2016 12:43 PM, Bruno Herrera wrote:
>>> >> >> >>
>>> >> >> >> Hi Alex,
>>> >> >> >>
>>> >> >> >> On Wed, Oct 26, 2016 at 7:09 AM, Alexandre Torgue
>>> >> >> >> <alexandre.torgue at st.com <mailto:alexandre.torgue@st.com>>
>>> wrote:
>>> >> >> >>>
>>> >> >> >>> Hi Bruno,
>>> >> >> >>>
>>> >> >> >>> On 10/25/2016 11:06 PM, Bruno Herrera wrote:
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>> Hi Alexandre,
>>> >> >> >>>>
>>> >> >> >>>>>
>>> >> >> >>>>> stm32f469-disco and stm32f429-eval boards use SDRAM
>>> start address
>>> >> >> >>>>> remapping
>>> >> >> >>>>> (to @0) to boost performances. A DMA translation through
>>> >> >> >>>>> "dma-ranges"
>>> >> >> >>>>> property was needed for other masters than the M4 CPU.
>>> >> >> >>>>> stm32f429-disco doesn't use remapping so doesn't need
>>> this DMA
>>> >> >> >>>>> translation.
>>> >> >> >>>>> This patches moves this DMA translation definition from
>>> stm32f429
>>> >> >> >>>>> soc
>>> >> >> >>>>> file
>>> >> >> >>>>> to board files.
>>> >> >> >>>>>
>>> >> >> >>>>> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com
>>> <mailto:alexandre.torgue@st.com>>
>>>
>>> >> >> >>>>>
>>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>>> index 13c7cd2..a763c15 100644
>>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>>> @@ -82,6 +82,10 @@
>>> >> >> >>>>> };
>>> >> >> >>>>> };
>>> >> >> >>>>>
>>> >> >> >>>>> + soc {
>>> >> >> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
>>> >> >> >>>>> + };
>>> >> >> >>>>> +
>>> >> >> >>>>> usbotg_hs_phy: usbphy {
>>> >> >> >>>>> #phy-cells = <0>;
>>> >> >> >>>>> compatible = "usb-nop-xceiv";
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>> Shouldn't also the peripheral dma-ranges property move to
>>> board
>>> >> >> >>>> specific
>>> >> >> >>>> too?
>>> >> >> >>>> I had this patch for while but I didn't had the time to
>>> submit:
>>> >> >> >>>
>>> >> >> >>>
>>> >> >> >>>
>>> >> >> >>> Well spot I forgot it. Actually, discussing with Arnd
>>> ysterday on
>>> >> >> >>> IIRC,
>>> >> >> >>> empty dma-ranges is not needed. Can you test on your side by
>>> >> >> >>> removing
>>> >> >> >>> dma-ranges in usb node please ?
>>> >> >> >>
>>> >> >> >> Unfortunately will take a time for me to set up this
>>> environment on
>>> >> >> >> the STM32F4-EVAL board.
>>> >> >> >> And on the discovery boards we dont have this scenario.
>>> That was the
>>> >> >> >> main reason I did not submit the patch right away.
>>> >> >> >> My conclusion and I might be wrong but is based on the my
>>> tests with
>>> >> >> >> SDIO device at STM32F469I-DISCO board.
>>> >> >> >>
>>> >> >> >> I started this issue as discussion at ST Forum but Maxime
>>> gave me
>>> >> >> >> the
>>> >> >> >> hint.
>>> >> >> >>
>>> >> >> >>
>>> >> >> >>
>>> >> >> >>
>>> >> >> >>
>>>
>>> https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B¤tviews=44
>>>
>>> <https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B¤tviews=44>
>>> >> >> >>
>>> >> >> >>> I will push a v2 by removing empty dma-ranges if tests are
>>> ok in
>>> >> >> >>> your
>>> >> >> >>> side.
>>> >> >> >>
>>> >> >> >>
>>> >> >> >> From my understating/conclusion is: when empty
>>> property(dma-ranges)
>>> >> >> >> is
>>> >> >> >> the device node, the mapping will be taken in consideration
>>> when
>>> >> >> >> using
>>> >> >> >> DMA otherwise the mapping is ignored.
>>> >> >> >> And in the SDIO case it is needed for DEV->MEM(SDRAM) and
>>> >> >> >> MEM(SDRAM)->DEV. If it is not the case for the devices in
>>> question
>>> >> >> >> so
>>> >> >> >> I suppose it can work without the property.
>>> >> >> >
>>> >> >> >
>>> >> >> > For sure translation has to be done but I'm not sure that an
>>> empty
>>> >> >> > "dma-ranges" is needed in device node to activate it. For
>>> Ethernet
>>> >> >> > empty
>>> >> >> > "dma-ranges" is not needed. I will try with usb.
>>> >> >>
>>> >> >> In the case of SDIO it is needed. As example this is my
>>> working SDIO
>>> >> >> node:
>>> >> >>
>>> >> >> sdio: sdio at 40012c00 {
>>> >> >> compatible = "arm,pl18x", "arm,primecell";
>>> >> >> arm,primecell-periphid = <0x00480181>;
>>> >> >> reg = <0x40012c00 0x400>;
>>> >> >> dmas = <&dma2 6 4 0x10400 0x3>, /* Logical - DevToMem */
>>> >> >> <&dma2 3 4 0x10400 0x3>; /* Logical - MemToDev */
>>> >> >> dma-names = "rx", "tx";
>>> >> >> clocks = <&rcc 0 171>;
>>> >> >> clock-names = "apb_pclk";
>>> >> >> interrupts = <49>;
>>> >> >> status = "disabled";
>>> >> >> };
>>> >> >>
>>> >> >> &sdio {
>>> >> >> status = "okay";
>>> >> >> vmmc-supply = <&wlan_en>;
>>> >> >> bus-width = <4>;
>>> >> >> max-frequency = <24000000>;
>>> >> >> pinctrl-names = "default";
>>> >> >> pinctrl-0 = <&sdio_pins>;
>>> >> >> ti,non-removable;
>>> >> >> ti,needs-special-hs-handling;
>>> >> >> dma-ranges;
>>> >> >> cap-power-off-card;
>>> >> >> keep-power-in-suspend;
>>> >> >>
>>> >> >> #address-cells = <1>;
>>> >> >> #size-cells = <0>;
>>> >> >> wlcore: wlcore at 0 {
>>> >> >> compatible = "ti,wl1835";
>>> >> >> reg = <2>;
>>> >> >> interrupt-parent = <&gpioa>;
>>> >> >> interrupts = <8 IRQ_TYPE_EDGE_RISING>;
>>> >> >> };
>>> >> >> };
>>> >> >>
>>> >> >> >
>>> >> >> > alex
>>> >> >> >
>>> >> >> >
>>> >> >> >>
>>> >> >> >>>
>>> >> >> >>> Thanks in advance
>>> >> >> >>> Alex
>>> >> >> >>>
>>> >> >> >>>
>>> >> >> >>>>
>>> >> >> >>>> Author: Bruno Herrera <bruherrera@gmail.com
>>> <mailto:bruherrera@gmail.com>>
>>>
>>> >> >> >>>> Date: Sun Oct 16 14:50:00 2016 -0200
>>> >> >> >>>>
>>> >> >> >>>> ARM: DT: STM32: Use dma-ranges property per board not
>>> at dtsi
>>> >> >> >>>> file
>>> >> >> >>>>
>>> >> >> >>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>> index 6bfc595..2a22a82 100644
>>> >> >> >>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>> @@ -52,6 +52,10 @@
>>> >> >> >>>> model = "STMicroelectronics STM32429i-EVAL board";
>>> >> >> >>>> compatible = "st,stm32429i-eval", "st,stm32f429";
>>> >> >> >>>>
>>> >> >> >>>> + soc {
>>> >> >> >>>> + dma-ranges = <0xC0000000 0x0 0x10000000>;
>>> >> >> >>>> + };
>>> >> >> >>>> +
>>> >> >> >>>> chosen {
>>> >> >> >>>> bootargs = "root=/dev/ram rdinit=/linuxrc";
>>> >> >> >>>> stdout-path = "serial0:115200n8";
>>> >> >> >>>> @@ -96,6 +100,7 @@
>>> >> >> >>>>
>>> >> >> >>>> ðernet0 {
>>> >> >> >>>> status = "okay";
>>> >> >> >>>> + dma-ranges;
>>> >> >> >>>> pinctrl-0 = <ðernet0_mii>;
>>> >> >> >>>> pinctrl-names = "default";
>>> >> >> >>>> phy-mode = "mii-id";
>>> >> >> >>>> @@ -116,6 +121,7 @@
>>> >> >> >>>> };
>>> >> >> >>>>
>>> >> >> >>>> &usbotg_hs {
>>> >> >> >>>> + dma-ranges;
>>> >> >> >>>> dr_mode = "host";
>>> >> >> >>>> phys = <&usbotg_hs_phy>;
>>> >> >> >>>> phy-names = "usb2-phy";
>>> >> >> >>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>> b/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>> index 7d624a2..697a133 100644
>>> >> >> >>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>> @@ -59,7 +59,6 @@
>>> >> >> >>>> };
>>> >> >> >>>>
>>> >> >> >>>> soc {
>>> >> >> >>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
>>> >> >> >>>>
>>> >> >> >>>> timer2: timer at 40000000 {
>>> >> >> >>>> compatible = "st,stm32-timer";
>>> >> >> >>>> @@ -472,13 +471,11 @@
>>> >> >> >>>> st,syscon = <&syscfg 0x4>;
>>> >> >> >>>> snps,pbl = <8>;
>>> >> >> >>>> snps,mixed-burst;
>>> >> >> >>>> - dma-ranges;
>>> >> >> >>>> status = "disabled";
>>> >> >> >>>> };
>>> >> >> >>>>
>>> >> >> >>>> usbotg_hs: usb at 40040000 {
>>> >> >> >>>> compatible = "snps,dwc2";
>>> >> >> >>>> - dma-ranges;
>>> >> >> >>>> reg = <0x40040000 0x40000>;
>>> >> >> >>>> interrupts = <77>;
>>> >> >> >>>> clocks = <&rcc 0 29>;
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>>> b/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>>> index 0596d60..3a1cfdd 100644
>>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>>> @@ -59,8 +59,6 @@
>>> >> >> >>>>> };
>>> >> >> >>>>>
>>> >> >> >>>>> soc {
>>> >> >> >>>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
>>> >> >> >>>>> -
>>> >> >> >>>>> timer2: timer at 40000000 {
>>> >> >> >>>>> compatible = "st,stm32-timer";
>>> >> >> >>>>> reg = <0x40000000 0x400>;
>>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
>>> >> >> >>>>> b/arch/arm/boot/dts/stm32f469-disco.dts
>>> >> >> >>>>> index 9e73656..c2213c0 100644
>>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32f469-disco.dts
>>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
>>> >> >> >>>>> @@ -64,6 +64,10 @@
>>> >> >> >>>>> aliases {
>>> >> >> >>>>> serial0 = &usart3;
>>> >> >> >>>>> };
>>> >> >> >>>>> +
>>> >> >> >>>>> + soc {
>>> >> >> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
>>> >> >> >>>>> + };
>>> >> >> >>>>> };
>>> >> >> >>>>>
>>> >> >> >>>>> &clk_hse {
>>> >> >> >>>>> --
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>> Br.,
>>> >> >> >>>> Bruno
>>> >> >> >>>>
>>> >> >> >>>
>>> >> >> >
>>> >> >>
>>> >> >> _______________________________________________
>>> >> >> linux-arm-kernel mailing list
>>> >> >> linux-arm-kernel at lists.infradead.org
>>> <mailto:linux-arm-kernel@lists.infradead.org>
>>> >> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>> <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>
>>> >> >
>>> >> >
>>> >
>>> >
>>>
>>>
>>
^ permalink raw reply
* [PATCH v14 00/16] KVM PCIe/MSI passthrough on ARM/ARM64
From: Auger Eric @ 2016-11-02 16:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <452b773f-826b-61cd-55e3-018ecb34b503@arm.com>
Hi Robin,
On 24/10/2016 21:39, Robin Murphy wrote:
> On 21/10/16 10:26, Auger Eric wrote:
>> Hi Will,
>>
>> On 20/10/2016 19:32, Will Deacon wrote:
>>> Hi Eric,
>>>
>>> Thanks for posting this.
>>>
>>> On Wed, Oct 12, 2016 at 01:22:08PM +0000, Eric Auger wrote:
>>>> This is the second respin on top of Robin's series [1], addressing Alex' comments.
>>>>
>>>> Major changes are:
>>>> - MSI-doorbell API now is moved to DMA IOMMU API following Alex suggestion
>>>> to put all API pieces at the same place (so eventually in the IOMMU
>>>> subsystem)
>>>> - new iommu_domain_msi_resv struct and accessor through DOMAIN_ATTR_MSI_RESV
>>>> domain with mirror VFIO capability
>>>> - more robustness I think in the VFIO layer
>>>> - added "iommu/iova: fix __alloc_and_insert_iova_range" since with the current
>>>> code I failed allocating an IOVA page in a single page domain with upper part
>>>> reserved
>>>>
>>>> IOVA range exclusion will be handled in a separate series
>>>>
>>>> The priority really is to discuss and freeze the API and especially the MSI
>>>> doorbell's handling. Do we agree to put that in DMA IOMMU?
>>>>
>>>> Note: the size computation does not take into account possible page overlaps
>>>> between doorbells but it would add quite a lot of complexity i think.
>>>>
>>>> Tested on AMD Overdrive (single GICv2m frame) with I350 VF assignment.
>>>
>>> Marc, Robin and I sat down and had a look at the series and, whilst it's
>>> certainly addressing a problem that we desperately want to see fixed, we
>>> think that it's slightly over-engineering in places and could probably
>>> be simplified in the interest of getting something upstream that can be
>>> used as a base, on which the ABI can be extended as concrete use-cases
>>> become clear.
>>>
>>> Stepping back a minute, we're trying to reserve some of the VFIO virtual
>>> address space so that it can be used by devices to map their MSI doorbells
>>> using the SMMU. With your patches, this requires that (a) the kernel
>>> tells userspace about the size and alignment of the doorbell region
>>> (MSI_RESV) and (b) userspace tells the kernel the VA-range that can be
>>> used (RESERVED_MSI_IOVA).
>>>
>>> However, this is all special-cased for MSI doorbells and there are
>>> potentially other regions of the VFIO address space that are reserved
>>> and need to be communicated to userspace as well. We already know of
>>> hardware where the PCI RC intercepts p2p accesses before they make it
>>> to the SMMU, and other hardware where the MSI doorbell is at a fixed
>>> address. This means that we need a mechanism to communicate *fixed*
>>> regions of virtual address space that are reserved by VFIO. I don't
>>> even particularly care if VFIO_MAP_DMA enforces that, but we do need
>>> a way to tell userspace "hey, you don't want to put memory here because
>>> it won't work well with devices".
>>
>> I think we all agree on this. Exposing an API to the user space
>> reporting *fixed* reserved IOVA ranges is a requirement anyway. The
>> problem was quite clearly stated by Alex in
>> http://lkml.iu.edu/hypermail/linux/kernel/1610.0/03308.html
>> (VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE)
>>
>> I started working on this VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE
>> capability but to me and I think according to Alex, it was a different
>> API from MSI_RESV.
>>
>>>
>>> In that case, we end up with something like your MSI_RESV capability,
>>> but actually specifying a virtual address range that is simply not to
>>> be used by MAP_DMA -- we don't say anything about MSIs. Now, taking this
>>> to its logical conclusion, we no longer need to distinguish between
>>> remappable reserved regions and fixed reserved regions in the ABI.
>>> Instead, we can have the kernel allocate the virtual address space for
>>> the remappable reserved regions (probably somewhere in the bottom 4GB)
>>> and expose them via the capability.
>>
>>
>> If I understand correctly you want the host to arbitrarily choose where
>> it puts the iovas reserved for MSI and not ask the userspace.
>>
>> Well so we are back to the discussions we had in Dec 2015 (see Marc's
>> answer in http://thread.gmane.org/gmane.comp.emulators.kvm.arm.devel/3858).
>
> To an extent, yes, however the difference is that we now know we
> definitely have to deal with situations in which userspace *cannot* be
> in total control of the memory map, and that changes the game:
>
> _________
> / \
> / Fixed \
> / things (A) \
> ( _________ )
> \ / MSI \ /
> X doorbells X
> / \___(B)___/ \
> ( )
> \ Remappable /
> \ things (C)/
> \_________/
>
> In the absence of A, then B == C so it was very hard to not want to
> implement C. As soon as A *has* to be implemented for other reasons,
> then that is also sufficient to encompass B. C can still be implemented
> later as a nice-to-have, but is not necessary to get B off the ground.
>
>> - So I guess you will init an iova_domain seomewhere below the 4GB to
>> allocate the MSIs. what size are you going to choose. Don't you have the
>> same need to dimension the iova range.
>> - we still need to assess the MSI assignment safety. How will we compute
>> safety for VFIO?
>
> Absolutely. We're talking in general terms of the userspace ABI here,
> although that can't help but colour the underlying implementation
> decisions.
Sorry for the delay I was out of the office last week.
The userspace ABI to retrieve reserved regions is the *easy* part. It is
based on VFIO capability chain and I have an RFC ready.
Of course the VFIO internals still have to handle the
> specific case of MSIs, but that's basically no more than this:
>
> static bool msi_isolation = true; /* until proven otherwise */
> static unsigned long msi_remap_virt_base = 0x08000000; /* fits QEMU */
> static size_t msi_remap_size;
>
> vfio_msi_thing_callback(thing) {
> msi_remap_size += thing->info.size;
> msi_isolation &= thing->info.flags & PROVIDES_ISOLATION;
> }
>
> vfio_msi_init(...) {
> ...
> #ifdef CONFIG_X86
> msi_remap_virt_base = 0xfee00000;
> msi_remap_size = 0x100000;
> msi_isolation = irq_remapping_enabled;
> #else
> irq_for_each_msi_thing(vfio_msi_thing_callback);
> #endif
> ...
> }
>
> vfio_attach_group(...) {
> ...
> if (!msi_isolation && !allow_unsafe_interrupts)
> return -ENOWAY;
> ...
> get_msi_region_cookie(domain, msi_remap_base, msi_remap_size);
> ...
> }
I doubt Alex will accept to put that code in VFIO. He suggested in the
past to use the IOMMU API to retrieve the reserved region(s).
what about adding a reserved_regions list in iommu_domain and add a new
iommu_ops, something like
void add_reserved_regions(struct iommu_domain *, struct device *dev)
whose role would be to populate the list. This add_reserved_regions()
would be called on __iommu_attach_device. The list would be emptied on
iommu_domain_free().
arm-smmu cb implementation would be in charge of
- computing non ACS PCI host bridge windows from @dev,
- computing msi_rebase_map/size computation
on x86, cb would simply populate the MSI window.
vfio would lookup the iommu domain reserved_regions list on
VFIO_IOMMU_GET_INFO
Drawback of this approach is the security aspect is not handled by the
IOMMU API.
Note that combining v14 series and this one would implement everything I
think + giving the flexibility for the userspace to choose where it put
things. But well, LPC discussions will bring the last word obviously.
>
> And when a well-behaved userspace queries the reserved regions, that
> base address and size is just one of potentially several that it should
> get back. It's that "querying the reserved regions" bit that needs to be
> gotten right first time.
>
> Note that at this point I'm no longer even overly bothered about the
> details of irq_for_each_msi_thing(), as it's an internal kernel
> interface and thus malleable, although obviously the simpler the better.
> I have to say Punit's idea of iterating irq_domains does actually look
> really neat and tidy as a proof-of-concept, and also makes me think off
> on a tangent that it would be sweet to be able to retrieve base+size
> from dev->msi_domain to pre-allocate MSI pages in default domains, and
> obviate the compose 'failure' case.
As Punit mentionned, the natural place where the msi doorbell base,
size and irq_remapping can be retrieved looks to be the irqchip itself.
It works perfectly fine for v2m and its. Hence my first attempt to use a
cb at this level (irqchip msi_doorbell_info up to v11).
Adding a cb at irq_domain level looks quite impractical to me to
retrieve the info. Actually I don't see how to manage that without
adding new fields in irq_domain struct. If you have any suggestion,
please let me know.
Thanks
Eric
>
>> This simplifies things in the
>>> following ways:
>>>
>>> * You don't need to keep track of MSI vs DMA addresses in the VFIO rbtree
>> right: I guess you rely on iommu_map to return an error in case the iova
>> is already mapped somewhere else.
>>> * You don't need to try collapsing doorbells into a single region
>> why? at host level I guess you will init a single iova domain?
>
> Yeah, right now this one goes either way - as things stand, it does make
> life easier on the host side to make a single region to hang off the
> back of the current iova_cookie magic, and as illustrated above it's
> possibly the most trivial part of the whole thing, but the point is we
> still don't *need* to. Since a userspace ABI for generic reservations
> has to be able handle more than one region for the sake of non-MSI
> things, we'd be free to change the kernel-side implementation in future
> to just report multiple doorbells as individual regions - for starters,
> if and when we add dynamic reservations and userspace gets to pick its
> own IOVAs for those, it'll be a damn sight easier *not* to coalesce
> everything.
>
>>> * You don't need a special MAP flavour to map MSI doorbells
>> right
>>> * The ABI is reusable for PCI p2p and fixed doorbells
>> right
>>
>> Aren't we moving the issue at user-space? Currently QEMU mach-virt
>> address space is fully static. Adapting mach-virt to adjust to host
>> constraints is not straightforward. It is simple to reject the
>> assignment in case of collision but more difficult to react positively.
>
> The point is that we *have* to move at least some of the issue to
> userspace, and by then I'm struggling to see any real difference between
> these situations:
>
> a) QEMU asks VFIO to map some pages for DMA, gets an error back because
> VFIO detects it conflicts with a reserved region, and gives up.
> b) QEMU starts by asking VFIO what regions are reserved, realises they
> will overlap with its hard-coded RAM address, and gives up.
>
> where (a) requires a bunch of kernel machinery to second-guess
> userspace, while (b) simply relies on userspace not being broken. And if
> userspace fails at not being broken, then we simply retain the behaviour
> which actually happens right now:
>
> c) QEMU maps some pages for DMA at the same address as PCI config space
> on the underlying hardware. Hilarity ensues.
>
> Of course, userspace could be anything other than QEMU as well, so it's
> not necessarily second-guessable at all; maybe we make the arbitrary
> msi_remap_virt_base a VFIO module parameter to be more accommodating.
> Who knows, maybe it turns out that's enough to keep users happy and we
> never need to implement fully dynamic reservations.
>
> Robin.
>
>>> I really think it would make your patch series both generally useful and
>>> an awful lot smaller, whilst leaving the door open to ABI extension on
>>> a case-by-case basis when we determine that it's really needed.
>>
>> I would like to have a better understanding of how you assess the
>> security and dimension the iova domain. This is the purpose of msi
>> doorbell registration, which is not neat at all I acknowledge but well I
>> did not find any other solution and did not get any other suggestion.
>> Besides I think the per-cpu thing is over-engineered and this can
>> definitively be simplified.
>>
>> VFIO part was reviewed by Alex and I don't have the impression that this
>> is the blocking part. besides there is on iova.c fix,
>> IOMMU_CAP_INTR_REMAP removal; so is it really over-complicated?
>>
>> Thanks
>>
>> Eric
>>
>>>
>>> Thoughts?
>>>
>>> Will
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCH] coresight: Add support for ARM Coresight STM-500
From: Suzuki K Poulose @ 2016-11-02 16:19 UTC (permalink / raw)
To: linux-arm-kernel
Add the PIDs for STM-500 to the known STM devices list.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Chunyan Zhang <zhang.chunyan@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-stm.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
index 49e0f1b..3524452 100644
--- a/drivers/hwtracing/coresight/coresight-stm.c
+++ b/drivers/hwtracing/coresight/coresight-stm.c
@@ -920,6 +920,11 @@ static struct amba_id stm_ids[] = {
.mask = 0x0003ffff,
.data = "STM32",
},
+ {
+ .id = 0x0003b963,
+ .mask = 0x0003ffff,
+ .data = "STM500",
+ },
{ 0, 0},
};
--
2.7.4
^ permalink raw reply related
* [PATCH v7 0/7] arm/arm64: vgic: Implement API for vGICv3 live migration
From: Christoffer Dall @ 2016-11-02 16:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMJs5B8aLZCDeAVhJN7Cajt4PL4HBtXc3BiNzMyjK1tOSjMwmg@mail.gmail.com>
Hi Vijay,
On Thu, Oct 06, 2016 at 02:14:13PM +0200, Christoffer Dall wrote:
> Hi Vijay,
>
> On Wed, Oct 5, 2016 at 4:33 PM, Vijay Kilari <vijay.kilari@gmail.com> wrote:
> > Hi Marc, Christoffer,
> >
> > Do you have any review comments on this patch set?.
> >
> Since we missed the 4.9 merge window there is no urgency just yet, and
> I'm tied up with other things for a while, and Marc is away this week
> on holiday. I'm sure he'll have a look when he's back and I'll follow
> up later.
>
I think it would be useful for you to post a v7 of your patch set
rebased v4.9-rcX and addressing the issue you found yourself with a
wrong parameter.
Then I'll have another look.
Thanks,
-Christoffer
^ permalink raw reply
* [PATCHv2] PCI: QDF2432 32 bit config space accessors
From: Sinan Kaya @ 2016-11-02 16:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102160820.GA6568@bhelgaas-glaptop.roam.corp.google.com>
Hi Bjorn,
On 11/2/2016 12:08 PM, Bjorn Helgaas wrote:
> On Tue, Nov 01, 2016 at 07:06:31AM -0600, cov at codeaurora.org wrote:
>> Hi Bjorn,
>>
>> On 2016-10-31 15:48, Bjorn Helgaas wrote:
>>> On Wed, Sep 21, 2016 at 06:38:05PM -0400, Christopher Covington wrote:
>>>> The Qualcomm Technologies QDF2432 SoC does not support accesses
>>>> smaller
>>>> than 32 bits to the PCI configuration space. Register the appropriate
>>>> quirk.
>>>>
>>>> Signed-off-by: Christopher Covington <cov@codeaurora.org>
>>>
>>> Hi Christopher,
>>>
>>> Can you rebase this against v4.9-rc1? It no longer applies to my tree.
>>
>> I apologize for not being clearer. This patch depends on:
>>
>> PCI/ACPI: Extend pci_mcfg_lookup() responsibilities
>> PCI/ACPI: Check platform-specific ECAM quirks
>>
>> These patches from Tomasz Nowicki were previously in your pci/ecam-v6
>> branch, but that seems to have come and gone. How would you like to
>> proceed?
>
> Oh yes, that's right, I forgot that connection. I'm afraid I kind of
> dropped the ball on that thread, so I went back and read through it
> again.
>
> I *think* the current state is:
>
> - I'm OK with the first two patches that add the quirk
> infrastructure.
>
> - My issue with the last three patches that add ThunderX quirks is
> that there's no generic description of the ECAM address space.
>
> So if I understand correctly, your Qualcomm patch depends only on the
> first two patches.
>
> Then the question is how the Qualcomm ECAM address space is described.
> Your quirk overrides the default pci_generic_ecam_ops with the
> &pci_32b_ops, but it doesn't touch the address space part, so I assume
> the bus ranges and corresponding address space in your MCFG is
> correct. So far, so good.
Qualcomm ECAM space includes both the root port and the endpoint address
space with a single contiguous 256 MB address space described in MCFG table.
There is no need to describe additional resources like PNP0C02.
The only thing we missed was 8/16 bits access support on the root port.
That's why, we need Cov's patch.
>
> Is there also an ACPI device that contains that space in _CRS? I
> think we concluded that the standard solution is to describe this with
> a PNP0C02 device.
>
> Would you mind opening a bugzilla at bugzilla.kernel.org and attaching
> the dmesg log, /proc/iomem, and maybe a DSDT dump? I'd like to have
> something to point at to say "if you need an MCFG quirk, you need the
> MCFG bit and *also* these other related ACPI device bits, and here's
> how it should be done."
>
> Bjorn
>
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* flush_dcache_page() in ARM vs ARM64
From: Catalin Marinas @ 2016-11-02 16:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102132714.GA1326@lnxartpec.se.axis.com>
On Wed, Nov 02, 2016 at 02:27:14PM +0100, Rabin Vincent wrote:
> ARMv7-A and ARMv8-A are, as far as I can see, identical in which cache
> behaviours they support. The data cache has to behave as PIPT while for
> the instruction cache, PIPT, VIPT, and ASIC-tagged VIVT behaviours are
> supported. See section B3.11 of the ARMv7-A ARM and section D4.9 of the
> ARMv8-A ARM.
>
> Both ARMv7-A with Multiprocessing Extensions and ARMv8-A broadcast cache
> maintenance operations to other cores. See B2.2.5 of the ARMv7-A ARM
> and D7.2.57 of the ARMv8-A ARM.
>
> Both arch/arm/ (for ARMv6+) and arch/arm64/ define PG_arch_1 to be
> PG_dcache_clean and use it to postpone flushing from flush_dcache_page()
> to set_pte_at(). See arch/{arm,arm64}/mm/flush.c.
>
> However, arch/arm64/'s flush_dcache_page() is implemented like this:
>
> void flush_dcache_page(struct page *page)
> {
> if (test_bit(PG_dcache_clean, &page->flags))
> clear_bit(PG_dcache_clean, &page->flags);
> }
arm64 had a similar implementation to arm until commit b5b6c9e9149d
("arm64: Avoid cache flushing in flush_dcache_page()").
> Why does arch/arm/ flush the data cache area in flush_dcache_page() for
> the (!mapping || page_mapcount(page)) case even on ARMv7+ME, while
> arch/arm64/ doesn't for ARMv8?
IIRC, the reason was D-cache aliases which have disappeared from ARMv7.
> Why does arch/arm/ invalidate the instruction cache in
> flush_dcache_page() for the (mapping && page_count(page)) case even for
> ARMv7+ME, while arch/arm64/ doesn't for ARMv8?
I guess no-one updated it for non-aliasing caches.
> What would break with the following patch?
>
> diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
> index 3cced84..f1e6190 100644
> --- a/arch/arm/mm/flush.c
> +++ b/arch/arm/mm/flush.c
> @@ -327,6 +327,12 @@ void flush_dcache_page(struct page *page)
> if (page == ZERO_PAGE(0))
> return;
>
> + if (!cache_ops_need_broadcast() && cache_is_vipt_nonaliasing()) {
> + if (test_bit(PG_dcache_clean, &page->flags))
> + clear_bit(PG_dcache_clean, &page->flags);
> + return;
> + }
> +
> mapping = page_mapping(page);
>
> if (!cache_ops_need_broadcast() &&
This should work. Note that the test_bit() is just an optimisation I
borrowed from powerpc, not sure it has any noticeable impact (you could
as well just do the clear_bit()).
--
Catalin
^ permalink raw reply
* [PATCHv2] PCI: QDF2432 32 bit config space accessors
From: Bjorn Helgaas @ 2016-11-02 16:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102160820.GA6568@bhelgaas-glaptop.roam.corp.google.com>
On Wed, Nov 02, 2016 at 11:08:20AM -0500, Bjorn Helgaas wrote:
> On Tue, Nov 01, 2016 at 07:06:31AM -0600, cov at codeaurora.org wrote:
> > Hi Bjorn,
> >
> > On 2016-10-31 15:48, Bjorn Helgaas wrote:
> > >On Wed, Sep 21, 2016 at 06:38:05PM -0400, Christopher Covington wrote:
> > >>The Qualcomm Technologies QDF2432 SoC does not support accesses
> > >>smaller
> > >>than 32 bits to the PCI configuration space. Register the appropriate
> > >>quirk.
> > >>
> > >>Signed-off-by: Christopher Covington <cov@codeaurora.org>
> > >
> > >Hi Christopher,
> > >
> > >Can you rebase this against v4.9-rc1? It no longer applies to my tree.
> >
> > I apologize for not being clearer. This patch depends on:
> >
> > PCI/ACPI: Extend pci_mcfg_lookup() responsibilities
> > PCI/ACPI: Check platform-specific ECAM quirks
> >
> > These patches from Tomasz Nowicki were previously in your pci/ecam-v6
> > branch, but that seems to have come and gone. How would you like to
> > proceed?
>
> Oh yes, that's right, I forgot that connection. I'm afraid I kind of
> dropped the ball on that thread, so I went back and read through it
> again.
>
> I *think* the current state is:
>
> - I'm OK with the first two patches that add the quirk
> infrastructure.
>
> - My issue with the last three patches that add ThunderX quirks is
> that there's no generic description of the ECAM address space.
>
> So if I understand correctly, your Qualcomm patch depends only on the
> first two patches.
I put those first two patches and yours on pci/ecam-v6 and pushed it
again, so you can check it out.
Bjorn
^ permalink raw reply
* arm64 build failure with CONFIG_ARM64_LSE_ATOMICS=y
From: Artem Savkov @ 2016-11-02 16:44 UTC (permalink / raw)
To: linux-arm-kernel
Hello Catalin,
Looks like your patch "efd9e03 arm64: Use static keys for CPU features"
breaks arm64 build with "CONFIG_ARM64_LSE_ATOMICS=y" because it creates a
circular dependency for asm/lse.h through jump_label.h:
CC arch/arm64/kernel/asm-offsets.s
In file included from ./arch/arm64/include/asm/atomic.h:34:0,
from ./include/linux/atomic.h:4,
from ./include/linux/jump_label.h:169,
from ./arch/arm64/include/asm/cpufeature.h:12,
from ./arch/arm64/include/asm/alternative.h:4,
from ./arch/arm64/include/asm/lse.h:7,
from ./arch/arm64/include/asm/spinlock.h:19,
from ./include/linux/spinlock.h:87,
from ./include/linux/seqlock.h:35,
from ./include/linux/time.h:5,
from ./include/uapi/linux/timex.h:56,
from ./include/linux/timex.h:56,
from ./include/linux/sched.h:19,
from arch/arm64/kernel/asm-offsets.c:21:
./arch/arm64/include/asm/atomic_lse.h: In function ?atomic_andnot?:
./arch/arm64/include/asm/atomic_lse.h:35:15: error: expected string literal before ?ARM64_LSE_ATOMIC_INSN?
asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(op), \
...
./arch/arm64/include/asm/cmpxchg.h: In function ?__xchg_case_1?:
./arch/arm64/include/asm/cmpxchg.h:38:15: error: expected string literal before ?ARM64_LSE_ATOMIC_INSN?
asm volatile(ARM64_LSE_ATOMIC_INSN( \
--
Regards,
Artem
^ permalink raw reply
* Applied "ASoC: dapm: Introduce DAPM_DOUBLE_R dual channel dual register control type" to the asoc tree
From: Mark Brown @ 2016-11-02 16:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161003110804.28235-5-wens@csie.org>
The patch
ASoC: dapm: Introduce DAPM_DOUBLE_R dual channel dual register control type
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 02866eab0f0d88c4b6a68de72022c2b26f0359b5 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 2 Nov 2016 15:36:01 +0800
Subject: [PATCH] ASoC: dapm: Introduce DAPM_DOUBLE_R dual channel dual
register control type
A DAPM_DOUBLE_R control type can be used for dual channel mixer input
selectors / mute controls across 2 registers, possibly toggling both
channels together.
The control is meant to be shared by 2 widgets, 1 for each channel,
such that the mixer control exposed to userspace remains a combined
stereo control.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
include/sound/soc-dapm.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index f74ec19687f8..a466f4bdc835 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -277,6 +277,11 @@ struct device;
.info = snd_soc_info_volsw, \
.get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \
.private_value = SOC_DOUBLE_VALUE(reg, lshift, rshift, max, invert, 0) }
+#define SOC_DAPM_DOUBLE_R(xname, lreg, rreg, shift, max, invert) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = snd_soc_info_volsw, \
+ .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \
+ .private_value = SOC_DOUBLE_R_VALUE(lreg, rreg, shift, max, invert) }
#define SOC_DAPM_SINGLE(xname, reg, shift, max, invert) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = snd_soc_info_volsw, \
--
2.10.1
^ permalink raw reply related
* Applied "ASoC: dapm: Introduce DAPM_DOUBLE dual channel control type" to the asoc tree
From: Mark Brown @ 2016-11-02 16:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161003110804.28235-4-wens@csie.org>
The patch
ASoC: dapm: Introduce DAPM_DOUBLE dual channel control type
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 9ee7ef31b5a07cdca88cae023c613e045af935b9 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 2 Nov 2016 15:36:00 +0800
Subject: [PATCH] ASoC: dapm: Introduce DAPM_DOUBLE dual channel control type
A DAPM_DOUBLE control type can be used for dual channel mixer input
selectors / mute controls in one register, possibly toggling both
channels together.
The control is meant to be shared by 2 widgets, 1 for each channel,
such that the mixer control exposed to userspace remains a combined
stereo control.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
include/sound/soc-dapm.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index d5f4677776ce..f74ec19687f8 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -272,6 +272,11 @@ struct device;
/* dapm kcontrol types */
+#define SOC_DAPM_DOUBLE(xname, reg, lshift, rshift, max, invert) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = snd_soc_info_volsw, \
+ .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \
+ .private_value = SOC_DOUBLE_VALUE(reg, lshift, rshift, max, invert, 0) }
#define SOC_DAPM_SINGLE(xname, reg, shift, max, invert) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = snd_soc_info_volsw, \
--
2.10.1
^ permalink raw reply related
* Applied "ASoC: dapm: Implement stereo mixer control support" to the asoc tree
From: Mark Brown @ 2016-11-02 16:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102073601.8659-3-wens@csie.org>
The patch
ASoC: dapm: Implement stereo mixer control support
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From e7aa450fe17890e59db7d3c2d8eff5b6b41fc531 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 2 Nov 2016 15:35:59 +0800
Subject: [PATCH] ASoC: dapm: Implement stereo mixer control support
While DAPM is mono or single channel, its controls can be shared between
widgets, such as sharing one stereo mixer control between the left and
right channel widgets. An example such as the following routes
[Line In Left]----------<Line In Playback Switch>-------[Left Mixer]
^
^ ^ | ^
(inputs) (paths) <shared stereo mixer control> (outputs)
v v | v
v
[Line In Right]---------<Line In Playback Switch>-------[Right Mixer]
where we have separate widgets and paths for the left and right channels
from "Line In" to "Mixer", but a shared stereo mixer control for the
2 paths.
This patch introduces support for such shared mixer controls, allowing
more than 1 path to be attached to a single stereo control, and being
able to control left/right channels independently.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/soc-dapm.c | 141 ++++++++++++++++++++++++++++++++++++++++-----------
1 file changed, 112 insertions(+), 29 deletions(-)
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 32e7af9b93d5..27dd02e57b31 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -330,6 +330,11 @@ static int dapm_kcontrol_data_alloc(struct snd_soc_dapm_widget *widget,
case snd_soc_dapm_mixer_named_ctl:
mc = (struct soc_mixer_control *)kcontrol->private_value;
+ if (mc->autodisable && snd_soc_volsw_is_stereo(mc))
+ dev_warn(widget->dapm->dev,
+ "ASoC: Unsupported stereo autodisable control '%s'\n",
+ ctrl_name);
+
if (mc->autodisable) {
struct snd_soc_dapm_widget template;
@@ -723,7 +728,8 @@ static int dapm_connect_mux(struct snd_soc_dapm_context *dapm,
}
/* set up initial codec paths */
-static void dapm_set_mixer_path_status(struct snd_soc_dapm_path *p, int i)
+static void dapm_set_mixer_path_status(struct snd_soc_dapm_path *p, int i,
+ int nth_path)
{
struct soc_mixer_control *mc = (struct soc_mixer_control *)
p->sink->kcontrol_news[i].private_value;
@@ -736,7 +742,25 @@ static void dapm_set_mixer_path_status(struct snd_soc_dapm_path *p, int i)
if (reg != SND_SOC_NOPM) {
soc_dapm_read(p->sink->dapm, reg, &val);
- val = (val >> shift) & mask;
+ /*
+ * The nth_path argument allows this function to know
+ * which path of a kcontrol it is setting the initial
+ * status for. Ideally this would support any number
+ * of paths and channels. But since kcontrols only come
+ * in mono and stereo variants, we are limited to 2
+ * channels.
+ *
+ * The following code assumes for stereo controls the
+ * first path is the left channel, and all remaining
+ * paths are the right channel.
+ */
+ if (snd_soc_volsw_is_stereo(mc) && nth_path > 0) {
+ if (reg != mc->rreg)
+ soc_dapm_read(p->sink->dapm, mc->rreg, &val);
+ val = (val >> mc->rshift) & mask;
+ } else {
+ val = (val >> shift) & mask;
+ }
if (invert)
val = max - val;
p->connect = !!val;
@@ -749,13 +773,13 @@ static void dapm_set_mixer_path_status(struct snd_soc_dapm_path *p, int i)
static int dapm_connect_mixer(struct snd_soc_dapm_context *dapm,
struct snd_soc_dapm_path *path, const char *control_name)
{
- int i;
+ int i, nth_path = 0;
/* search for mixer kcontrol */
for (i = 0; i < path->sink->num_kcontrols; i++) {
if (!strcmp(control_name, path->sink->kcontrol_news[i].name)) {
path->name = path->sink->kcontrol_news[i].name;
- dapm_set_mixer_path_status(path, i);
+ dapm_set_mixer_path_status(path, i, nth_path++);
return 0;
}
}
@@ -2186,7 +2210,8 @@ EXPORT_SYMBOL_GPL(snd_soc_dapm_mux_update_power);
/* test and update the power status of a mixer or switch widget */
static int soc_dapm_mixer_update_power(struct snd_soc_card *card,
- struct snd_kcontrol *kcontrol, int connect)
+ struct snd_kcontrol *kcontrol,
+ int connect, int rconnect)
{
struct snd_soc_dapm_path *path;
int found = 0;
@@ -2195,8 +2220,33 @@ static int soc_dapm_mixer_update_power(struct snd_soc_card *card,
/* find dapm widget path assoc with kcontrol */
dapm_kcontrol_for_each_path(path, kcontrol) {
+ /*
+ * Ideally this function should support any number of
+ * paths and channels. But since kcontrols only come
+ * in mono and stereo variants, we are limited to 2
+ * channels.
+ *
+ * The following code assumes for stereo controls the
+ * first path (when 'found == 0') is the left channel,
+ * and all remaining paths (when 'found == 1') are the
+ * right channel.
+ *
+ * A stereo control is signified by a valid 'rconnect'
+ * value, either 0 for unconnected, or >= 0 for connected.
+ * This is chosen instead of using snd_soc_volsw_is_stereo,
+ * so that the behavior of snd_soc_dapm_mixer_update_power
+ * doesn't change even when the kcontrol passed in is
+ * stereo.
+ *
+ * It passes 'connect' as the path connect status for
+ * the left channel, and 'rconnect' for the right
+ * channel.
+ */
+ if (found && rconnect >= 0)
+ soc_dapm_connect_path(path, rconnect, "mixer update");
+ else
+ soc_dapm_connect_path(path, connect, "mixer update");
found = 1;
- soc_dapm_connect_path(path, connect, "mixer update");
}
if (found)
@@ -2214,7 +2264,7 @@ int snd_soc_dapm_mixer_update_power(struct snd_soc_dapm_context *dapm,
mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME);
card->update = update;
- ret = soc_dapm_mixer_update_power(card, kcontrol, connect);
+ ret = soc_dapm_mixer_update_power(card, kcontrol, connect, -1);
card->update = NULL;
mutex_unlock(&card->dapm_mutex);
if (ret > 0)
@@ -3039,22 +3089,28 @@ int snd_soc_dapm_get_volsw(struct snd_kcontrol *kcontrol,
int reg = mc->reg;
unsigned int shift = mc->shift;
int max = mc->max;
+ unsigned int width = fls(max);
unsigned int mask = (1 << fls(max)) - 1;
unsigned int invert = mc->invert;
- unsigned int val;
+ unsigned int reg_val, val, rval = 0;
int ret = 0;
- if (snd_soc_volsw_is_stereo(mc))
- dev_warn(dapm->dev,
- "ASoC: Control '%s' is stereo, which is not supported\n",
- kcontrol->id.name);
-
mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME);
if (dapm_kcontrol_is_powered(kcontrol) && reg != SND_SOC_NOPM) {
- ret = soc_dapm_read(dapm, reg, &val);
- val = (val >> shift) & mask;
+ ret = soc_dapm_read(dapm, reg, ®_val);
+ val = (reg_val >> shift) & mask;
+
+ if (ret == 0 && reg != mc->rreg)
+ ret = soc_dapm_read(dapm, mc->rreg, ®_val);
+
+ if (snd_soc_volsw_is_stereo(mc))
+ rval = (reg_val >> mc->rshift) & mask;
} else {
- val = dapm_kcontrol_get_value(kcontrol);
+ reg_val = dapm_kcontrol_get_value(kcontrol);
+ val = reg_val & mask;
+
+ if (snd_soc_volsw_is_stereo(mc))
+ rval = (reg_val >> width) & mask;
}
mutex_unlock(&card->dapm_mutex);
@@ -3066,6 +3122,13 @@ int snd_soc_dapm_get_volsw(struct snd_kcontrol *kcontrol,
else
ucontrol->value.integer.value[0] = val;
+ if (snd_soc_volsw_is_stereo(mc)) {
+ if (invert)
+ ucontrol->value.integer.value[1] = max - rval;
+ else
+ ucontrol->value.integer.value[1] = rval;
+ }
+
return ret;
}
EXPORT_SYMBOL_GPL(snd_soc_dapm_get_volsw);
@@ -3089,46 +3152,66 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol,
int reg = mc->reg;
unsigned int shift = mc->shift;
int max = mc->max;
- unsigned int mask = (1 << fls(max)) - 1;
+ unsigned int width = fls(max);
+ unsigned int mask = (1 << width) - 1;
unsigned int invert = mc->invert;
- unsigned int val;
- int connect, change, reg_change = 0;
+ unsigned int val, rval = 0;
+ int connect, rconnect = -1, change, reg_change = 0;
struct snd_soc_dapm_update update = { NULL };
int ret = 0;
- if (snd_soc_volsw_is_stereo(mc))
- dev_warn(dapm->dev,
- "ASoC: Control '%s' is stereo, which is not supported\n",
- kcontrol->id.name);
-
val = (ucontrol->value.integer.value[0] & mask);
connect = !!val;
if (invert)
val = max - val;
+ if (snd_soc_volsw_is_stereo(mc)) {
+ rval = (ucontrol->value.integer.value[1] & mask);
+ rconnect = !!rval;
+ if (invert)
+ rval = max - rval;
+ }
+
mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME);
- change = dapm_kcontrol_set_value(kcontrol, val);
+ /* This assumes field width < (bits in unsigned int / 2) */
+ if (width > sizeof(unsigned int) * 8 / 2)
+ dev_warn(dapm->dev,
+ "ASoC: control %s field width limit exceeded\n",
+ kcontrol->id.name);
+ change = dapm_kcontrol_set_value(kcontrol, val | (rval << width));
if (reg != SND_SOC_NOPM) {
- mask = mask << shift;
val = val << shift;
+ rval = rval << mc->rshift;
+
+ reg_change = soc_dapm_test_bits(dapm, reg, mask << shift, val);
- reg_change = soc_dapm_test_bits(dapm, reg, mask, val);
+ if (snd_soc_volsw_is_stereo(mc))
+ reg_change |= soc_dapm_test_bits(dapm, mc->rreg,
+ mask << mc->rshift,
+ rval);
}
if (change || reg_change) {
if (reg_change) {
+ if (snd_soc_volsw_is_stereo(mc)) {
+ update.has_second_set = true;
+ update.reg2 = mc->rreg;
+ update.mask2 = mask << mc->rshift;
+ update.val2 = rval;
+ }
update.kcontrol = kcontrol;
update.reg = reg;
- update.mask = mask;
+ update.mask = mask << shift;
update.val = val;
card->update = &update;
}
change |= reg_change;
- ret = soc_dapm_mixer_update_power(card, kcontrol, connect);
+ ret = soc_dapm_mixer_update_power(card, kcontrol, connect,
+ rconnect);
card->update = NULL;
}
--
2.10.1
^ permalink raw reply related
* Applied "ASoC: dapm: Support second register for DAPM control updates" to the asoc tree
From: Mark Brown @ 2016-11-02 16:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102073601.8659-2-wens@csie.org>
The patch
ASoC: dapm: Support second register for DAPM control updates
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From e411b0b5eb9b65257a050eac333d181d6e00e2c6 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 2 Nov 2016 15:35:58 +0800
Subject: [PATCH] ASoC: dapm: Support second register for DAPM control updates
To support double channel shared controls split across 2 registers, one
for each channel, we must be able to update both registers together.
Add a second set of register fields to struct snd_soc_dapm_update, and
update the DAPM control writeback (put) callbacks to support this.
For codecs that use custom events which call into DAPM to do updates,
also clear struct snd_soc_dapm_update before using it, so the second
set of fields remains clean.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
include/sound/soc-dapm.h | 4 ++++
sound/soc/codecs/adau17x1.c | 2 +-
sound/soc/codecs/tlv320aic3x.c | 2 +-
sound/soc/codecs/wm9712.c | 2 +-
sound/soc/codecs/wm9713.c | 2 +-
sound/soc/soc-dapm.c | 13 +++++++++++--
6 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index f60d755f7ac6..d5f4677776ce 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -615,6 +615,10 @@ struct snd_soc_dapm_update {
int reg;
int mask;
int val;
+ int reg2;
+ int mask2;
+ int val2;
+ bool has_second_set;
};
struct snd_soc_dapm_wcache {
diff --git a/sound/soc/codecs/adau17x1.c b/sound/soc/codecs/adau17x1.c
index 439aa3ff1f99..b36511d965c8 100644
--- a/sound/soc/codecs/adau17x1.c
+++ b/sound/soc/codecs/adau17x1.c
@@ -160,7 +160,7 @@ static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
struct adau *adau = snd_soc_codec_get_drvdata(codec);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
- struct snd_soc_dapm_update update;
+ struct snd_soc_dapm_update update = { 0 };
unsigned int stream = e->shift_l;
unsigned int val, change;
int reg;
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 5a8d96ec058c..8877b74b0510 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -157,7 +157,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
unsigned int mask = (1 << fls(max)) - 1;
unsigned int invert = mc->invert;
unsigned short val;
- struct snd_soc_dapm_update update;
+ struct snd_soc_dapm_update update = { 0 };
int connect, change;
val = (ucontrol->value.integer.value[0] & mask);
diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c
index 557709eac698..85f7c5bb8b82 100644
--- a/sound/soc/codecs/wm9712.c
+++ b/sound/soc/codecs/wm9712.c
@@ -187,7 +187,7 @@ static int wm9712_hp_mixer_put(struct snd_kcontrol *kcontrol,
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mixer, mask, shift, old;
- struct snd_soc_dapm_update update;
+ struct snd_soc_dapm_update update = { 0 };
bool change;
mixer = mc->shift >> 8;
diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c
index e4301ddb1b84..7e4822185feb 100644
--- a/sound/soc/codecs/wm9713.c
+++ b/sound/soc/codecs/wm9713.c
@@ -231,7 +231,7 @@ static int wm9713_hp_mixer_put(struct snd_kcontrol *kcontrol,
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mixer, mask, shift, old;
- struct snd_soc_dapm_update update;
+ struct snd_soc_dapm_update update = { 0 };
bool change;
mixer = mc->shift >> 8;
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 3bbe32ee4630..32e7af9b93d5 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -1626,6 +1626,15 @@ static void dapm_widget_update(struct snd_soc_card *card)
dev_err(w->dapm->dev, "ASoC: %s DAPM update failed: %d\n",
w->name, ret);
+ if (update->has_second_set) {
+ ret = soc_dapm_update_bits(w->dapm, update->reg2,
+ update->mask2, update->val2);
+ if (ret < 0)
+ dev_err(w->dapm->dev,
+ "ASoC: %s DAPM update failed: %d\n",
+ w->name, ret);
+ }
+
for (wi = 0; wi < wlist->num_widgets; wi++) {
w = wlist->widgets[wi];
@@ -3084,7 +3093,7 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol,
unsigned int invert = mc->invert;
unsigned int val;
int connect, change, reg_change = 0;
- struct snd_soc_dapm_update update;
+ struct snd_soc_dapm_update update = { NULL };
int ret = 0;
if (snd_soc_volsw_is_stereo(mc))
@@ -3192,7 +3201,7 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol,
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int val, change, reg_change = 0;
unsigned int mask;
- struct snd_soc_dapm_update update;
+ struct snd_soc_dapm_update update = { NULL };
int ret = 0;
if (item[0] >= e->items)
--
2.10.1
^ permalink raw reply related
* Applied "ASoC: sun4i-codec: Enable bus clock after getting GPIO" to the asoc tree
From: Mark Brown @ 2016-11-02 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161101063155.15826-1-wens@csie.org>
The patch
ASoC: sun4i-codec: Enable bus clock after getting GPIO
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 3716a891d65cc04217da1af5f2bccb7eaf6092c2 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 1 Nov 2016 14:31:55 +0800
Subject: [PATCH] ASoC: sun4i-codec: Enable bus clock after getting GPIO
In the current probe function the GPIO is acquired after the codec's
bus clock is enabled. However if it fails to acquire the GPIO due to
a deferred probe, it does not disable the bus clock before bailing out.
This would result in the clock being enabled multiple times.
Move the code that enables the bus clock after the part that gets the
GPIO, maintaining a separation between resource acquisition and device
enablement in the probe function.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/sunxi/sun4i-codec.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index a60707761abf..56ed9472e89f 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -829,12 +829,6 @@ static int sun4i_codec_probe(struct platform_device *pdev)
return PTR_ERR(scodec->clk_module);
}
- /* Enable the bus clock */
- if (clk_prepare_enable(scodec->clk_apb)) {
- dev_err(&pdev->dev, "Failed to enable the APB clock\n");
- return -EINVAL;
- }
-
scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa",
GPIOD_OUT_LOW);
if (IS_ERR(scodec->gpio_pa)) {
@@ -844,6 +838,12 @@ static int sun4i_codec_probe(struct platform_device *pdev)
return ret;
}
+ /* Enable the bus clock */
+ if (clk_prepare_enable(scodec->clk_apb)) {
+ dev_err(&pdev->dev, "Failed to enable the APB clock\n");
+ return -EINVAL;
+ }
+
/* DMA configuration for TX FIFO */
scodec->playback_dma_data.addr = res->start + SUN4I_CODEC_DAC_TXDATA;
scodec->playback_dma_data.maxburst = 4;
--
2.10.1
^ permalink raw reply related
* [PATCH v4 6/7] net: ethernet: bgmac: add NS2 support
From: Jon Mason @ 2016-11-02 16:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161101210512.GB27191@broadcom.com>
On Tue, Nov 01, 2016 at 05:05:13PM -0400, Jon Mason wrote:
> On Tue, Nov 01, 2016 at 01:34:30PM -0700, Scott Branden wrote:
> > One change in this patch
> >
> > On 16-11-01 01:04 PM, Jon Mason wrote:
> > >Add support for the variant of amac hardware present in the Broadcom
> > >Northstar2 based SoCs. Northstar2 requires an additional register to be
> > >configured with the port speed/duplexity (NICPM). This can be added to
> > >the link callback to hide it from the instances that do not use this.
> > >Also, clearing of the pending interrupts on init is required due to
> > >observed issues on some platforms.
> > >
> > >Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> > >---
> > > drivers/net/ethernet/broadcom/bgmac-platform.c | 56 +++++++++++++++++++++++++-
> > > drivers/net/ethernet/broadcom/bgmac.c | 3 ++
> > > drivers/net/ethernet/broadcom/bgmac.h | 1 +
> > > 3 files changed, 58 insertions(+), 2 deletions(-)
> > >
> > >diff --git a/drivers/net/ethernet/broadcom/bgmac-platform.c b/drivers/net/ethernet/broadcom/bgmac-platform.c
> > >index aed5dc5..f6d48c7 100644
> > >--- a/drivers/net/ethernet/broadcom/bgmac-platform.c
> > >+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c
> > >@@ -14,12 +14,21 @@
> > > #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> > >
> > > #include <linux/bcma/bcma.h>
> > >+#include <linux/brcmphy.h>
> > > #include <linux/etherdevice.h>
> > > #include <linux/of_address.h>
> > > #include <linux/of_mdio.h>
> > > #include <linux/of_net.h>
> > > #include "bgmac.h"
> > >
> > >+#define NICPM_IOMUX_CTRL 0x00000008
> > >+
> > >+#define NICPM_IOMUX_CTRL_INIT_VAL 0x3196e000
> > >+#define NICPM_IOMUX_CTRL_SPD_SHIFT 10
> > >+#define NICPM_IOMUX_CTRL_SPD_10M 0
> > >+#define NICPM_IOMUX_CTRL_SPD_100M 1
> > >+#define NICPM_IOMUX_CTRL_SPD_1000M 2
> > >+
> > > static u32 platform_bgmac_read(struct bgmac *bgmac, u16 offset)
> > > {
> > > return readl(bgmac->plat.base + offset);
> > >@@ -87,12 +96,46 @@ static void platform_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
> > > WARN_ON(1);
> > > }
> > >
> > >+static void bgmac_nicpm_speed_set(struct net_device *net_dev)
> > >+{
> > >+ struct bgmac *bgmac = netdev_priv(net_dev);
> > >+ u32 val;
> > >+
> > >+ if (!bgmac->plat.nicpm_base)
> > >+ return;
> > >+
> > >+ val = NICPM_IOMUX_CTRL_INIT_VAL;
> > >+ switch (bgmac->net_dev->phydev->speed) {
> > >+ default:
> > >+ pr_err("Unsupported speed. Defaulting to 1000Mb\n");
> > This should be dev_err
>
> It should probably be netdev_err (and there are a few instances below
> that should probably be changed to netdev_err as well).
Actually, the other instances I referenced above should not be
netdev_err, as they are enountered before the netdev is created. So,
dev_err is correct for them.
That being said, the original pr_err that Scott referenced should be
netdev_err (as it is encountered after the netdev is created). v5 will
make that change.
Thanks,
Jon
>
> Thanks,
> Jon
>
> > >+ case SPEED_1000:
> > >+ val |= NICPM_IOMUX_CTRL_SPD_1000M << NICPM_IOMUX_CTRL_SPD_SHIFT;
> > >+ break;
> > >+ case SPEED_100:
> > >+ val |= NICPM_IOMUX_CTRL_SPD_100M << NICPM_IOMUX_CTRL_SPD_SHIFT;
> > >+ break;
> > >+ case SPEED_10:
> > >+ val |= NICPM_IOMUX_CTRL_SPD_10M << NICPM_IOMUX_CTRL_SPD_SHIFT;
> > >+ break;
> > >+ }
> > >+
> > >+ writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL);
> > >+
> > >+ bgmac_adjust_link(bgmac->net_dev);
> > >+}
> > >+
> > > static int platform_phy_connect(struct bgmac *bgmac)
> > > {
> > > struct phy_device *phy_dev;
> > >
> > >- phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
> > >- bgmac_adjust_link);
> > >+ if (bgmac->plat.nicpm_base)
> > >+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
> > >+ bgmac->dev->of_node,
> > >+ bgmac_nicpm_speed_set);
> > >+ else
> > >+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
> > >+ bgmac->dev->of_node,
> > >+ bgmac_adjust_link);
> > > if (!phy_dev) {
> > > dev_err(bgmac->dev, "Phy connect failed\n");
> > > return -ENODEV;
> > >@@ -182,6 +225,14 @@ static int bgmac_probe(struct platform_device *pdev)
> > > if (IS_ERR(bgmac->plat.idm_base))
> > > return PTR_ERR(bgmac->plat.idm_base);
> > >
> > >+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nicpm_base");
> > >+ if (regs) {
> > >+ bgmac->plat.nicpm_base = devm_ioremap_resource(&pdev->dev,
> > >+ regs);
> > >+ if (IS_ERR(bgmac->plat.nicpm_base))
> > >+ return PTR_ERR(bgmac->plat.nicpm_base);
> > >+ }
> > >+
> > > bgmac->read = platform_bgmac_read;
> > > bgmac->write = platform_bgmac_write;
> > > bgmac->idm_read = platform_bgmac_idm_read;
> > >@@ -213,6 +264,7 @@ static int bgmac_remove(struct platform_device *pdev)
> > > static const struct of_device_id bgmac_of_enet_match[] = {
> > > {.compatible = "brcm,amac",},
> > > {.compatible = "brcm,nsp-amac",},
> > >+ {.compatible = "brcm,ns2-amac",},
> > > {},
> > > };
> > >
> > >diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
> > >index 4584958..a805cc8 100644
> > >--- a/drivers/net/ethernet/broadcom/bgmac.c
> > >+++ b/drivers/net/ethernet/broadcom/bgmac.c
> > >@@ -1082,6 +1082,9 @@ static void bgmac_enable(struct bgmac *bgmac)
> > > /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
> > > static void bgmac_chip_init(struct bgmac *bgmac)
> > > {
> > >+ /* Clear any erroneously pending interrupts */
> > >+ bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
> > >+
> > > /* 1 interrupt per received frame */
> > > bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
> > >
> > >diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h
> > >index ea52ac3..b1820ea 100644
> > >--- a/drivers/net/ethernet/broadcom/bgmac.h
> > >+++ b/drivers/net/ethernet/broadcom/bgmac.h
> > >@@ -463,6 +463,7 @@ struct bgmac {
> > > struct {
> > > void *base;
> > > void *idm_base;
> > >+ void *nicpm_base;
> > > } plat;
> > > struct {
> > > struct bcma_device *core;
> > >
^ permalink raw reply
* [RFC PATCH v2 1/1] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller
From: Bjorn Helgaas @ 2016-11-02 16:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ff2976e86b4990fba80544e9916a85361afcc237.1477443743.git.dhdang@apm.com>
Hi Duc,
On Tue, Oct 25, 2016 at 06:24:32PM -0700, Duc Dang wrote:
> PCIe controllers in X-Gene SoCs is not ECAM compliant: software
> needs to configure additional controller's register to address
> device at bus:dev:function.
>
> This patch depends on "ECAM quirks handling for ARM64 platforms"
> series (http://www.spinics.net/lists/arm-kernel/msg530692.html,
> the series was also modified by Bjorn) to address the limitation
> above for X-Gene PCIe controller.
>
> The quirk will only be applied for X-Gene PCIe MCFG table with
> OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
The quirks here contain some hard-coded address space consumed by
ECAM. The ECAM quirk itself is not a generic description of that
address space in the sense of a PCI BAR or an ACPI _CRS method, i.e.,
the quirk description is not enough to keep other parts of the kernel
from treating the address space as "available".
Can you add a note here in the changelog about how you are describing
this space generically? The standard solution is a PNP0C02 device
with _CRS that describes it.
It would be ideal if you could open a bugzilla at bugzilla.kernel.org
and attach there a dmesg log, /proc/iomem contents, and DSDT. This
would show both the generic PNP0C02 piece and the ECAM quirk piece.
BTW, I did refresh and re-push the pci/ecam-v6 branch where I'm
collecting this stuff, so if you want to rebase your patch on top of
that and test it, that would be great.
> Signed-off-by: Duc Dang <dhdang@apm.com>
> ---
> v2 changes:
> 1. Get rid of pci-xgene-ecam.c file and fold quirk code into pci-xgene.c
> 2. Redefine fixup array for X-Gene
> 3. Use devm_ioremap_resource to map csr_base
>
> drivers/acpi/pci_mcfg.c | 30 ++++++++
> drivers/pci/host/pci-xgene.c | 165 ++++++++++++++++++++++++++++++++++++++++++-
> include/linux/pci-ecam.h | 5 ++
> 3 files changed, 197 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index bb2c508..9dfc937 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -96,6 +96,36 @@ struct mcfg_fixup {
> THUNDER_ECAM_MCFG(2, 12),
> THUNDER_ECAM_MCFG(2, 13),
> #endif
> +#ifdef CONFIG_PCI_XGENE
> +#define XGENE_V1_ECAM_MCFG(rev, seg) \
> + {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
> + &xgene_v1_pcie_ecam_ops }
> +#define XGENE_V2_1_ECAM_MCFG(rev, seg) \
> + {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
> + &xgene_v2_1_pcie_ecam_ops }
> +#define XGENE_V2_2_ECAM_MCFG(rev, seg) \
> + {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
> + &xgene_v2_2_pcie_ecam_ops }
> +
> + /* X-Gene SoC with v1 PCIe controller */
> + XGENE_V1_ECAM_MCFG(1, 0),
> + XGENE_V1_ECAM_MCFG(1, 1),
> + XGENE_V1_ECAM_MCFG(1, 2),
> + XGENE_V1_ECAM_MCFG(1, 3),
> + XGENE_V1_ECAM_MCFG(1, 4),
> + XGENE_V1_ECAM_MCFG(2, 0),
> + XGENE_V1_ECAM_MCFG(2, 1),
> + XGENE_V1_ECAM_MCFG(2, 2),
> + XGENE_V1_ECAM_MCFG(2, 3),
> + XGENE_V1_ECAM_MCFG(2, 4),
> + /* X-Gene SoC with v2.1 PCIe controller */
> + XGENE_V2_1_ECAM_MCFG(3, 0),
> + XGENE_V2_1_ECAM_MCFG(3, 1),
> + /* X-Gene SoC with v2.2 PCIe controller */
> + XGENE_V2_2_ECAM_MCFG(4, 0),
> + XGENE_V2_2_ECAM_MCFG(4, 1),
> + XGENE_V2_2_ECAM_MCFG(4, 2),
> +#endif
> };
>
> static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
> diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
> index 1de23d7..d6aa642 100644
> --- a/drivers/pci/host/pci-xgene.c
> +++ b/drivers/pci/host/pci-xgene.c
> @@ -27,6 +27,8 @@
> #include <linux/of_irq.h>
> #include <linux/of_pci.h>
> #include <linux/pci.h>
> +#include <linux/pci-acpi.h>
> +#include <linux/pci-ecam.h>
> #include <linux/platform_device.h>
> #include <linux/slab.h>
>
> @@ -64,6 +66,7 @@
> /* PCIe IP version */
> #define XGENE_PCIE_IP_VER_UNKN 0
> #define XGENE_PCIE_IP_VER_1 1
> +#define XGENE_PCIE_IP_VER_2 2
>
> struct xgene_pcie_port {
> struct device_node *node;
> @@ -97,7 +100,15 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
> */
> static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
> {
> - struct xgene_pcie_port *port = bus->sysdata;
> + struct pci_config_window *cfg;
> + struct xgene_pcie_port *port;
> +
> + if (acpi_disabled)
> + port = bus->sysdata;
> + else {
> + cfg = bus->sysdata;
> + port = cfg->priv;
> + }
>
> if (bus->number >= (bus->primary + 1))
> return port->cfg_base + AXI_EP_CFG_ACCESS;
> @@ -111,10 +122,18 @@ static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
> */
> static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
> {
> - struct xgene_pcie_port *port = bus->sysdata;
> + struct pci_config_window *cfg;
> + struct xgene_pcie_port *port;
> unsigned int b, d, f;
> u32 rtdid_val = 0;
>
> + if (acpi_disabled)
> + port = bus->sysdata;
> + else {
> + cfg = bus->sysdata;
> + port = cfg->priv;
> + }
> +
> b = bus->number;
> d = PCI_SLOT(devfn);
> f = PCI_FUNC(devfn);
> @@ -158,7 +177,15 @@ static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
> static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
> int where, int size, u32 *val)
> {
> - struct xgene_pcie_port *port = bus->sysdata;
> + struct pci_config_window *cfg;
> + struct xgene_pcie_port *port;
> +
> + if (acpi_disabled)
> + port = bus->sysdata;
> + else {
> + cfg = bus->sysdata;
> + port = cfg->priv;
> + }
>
> if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
> PCIBIOS_SUCCESSFUL)
> @@ -189,6 +216,138 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
> .write = pci_generic_config_write32,
> };
>
> +#ifdef CONFIG_ACPI
> +static struct resource xgene_v1_csr_res[] = {
> + [0] = DEFINE_RES_MEM(0x1f2b0000UL, SZ_64K),
> + [1] = DEFINE_RES_MEM(0x1f2c0000UL, SZ_64K),
> + [2] = DEFINE_RES_MEM(0x1f2d0000UL, SZ_64K),
> + [3] = DEFINE_RES_MEM(0x1f500000UL, SZ_64K),
> + [4] = DEFINE_RES_MEM(0x1f510000UL, SZ_64K),
> +};
> +
> +static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
> +{
> + struct acpi_device *adev = to_acpi_device(cfg->parent);
> + struct acpi_pci_root *root = acpi_driver_data(adev);
> + struct device *dev = cfg->parent;
> + struct xgene_pcie_port *port;
> + struct resource *csr;
> +
> + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> + if (!port)
> + return -ENOMEM;
> +
> + csr = &xgene_v1_csr_res[root->segment];
> + port->csr_base = devm_ioremap_resource(dev, csr);
> + if (IS_ERR(port->csr_base)) {
> + kfree(port);
> + return -ENOMEM;
> + }
> +
> + port->cfg_base = cfg->win;
> + port->version = XGENE_PCIE_IP_VER_1;
> +
> + cfg->priv = port;
> +
> + return 0;
> +}
> +
> +struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
> + .bus_shift = 16,
> + .init = xgene_v1_pcie_ecam_init,
> + .pci_ops = {
> + .map_bus = xgene_pcie_map_bus,
> + .read = xgene_pcie_config_read32,
> + .write = pci_generic_config_write,
> + }
> +};
> +
> +static struct resource xgene_v2_1_csr_res[] = {
> + [0] = DEFINE_RES_MEM(0x1f2b0000UL, SZ_64K),
> + [1] = DEFINE_RES_MEM(0x1f2c0000UL, SZ_64K),
> +};
> +
> +static int xgene_v2_1_pcie_ecam_init(struct pci_config_window *cfg)
> +{
> + struct acpi_device *adev = to_acpi_device(cfg->parent);
> + struct acpi_pci_root *root = acpi_driver_data(adev);
> + struct device *dev = cfg->parent;
> + struct xgene_pcie_port *port;
> + struct resource *csr;
> +
> + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> + if (!port)
> + return -ENOMEM;
> +
> + csr = &xgene_v2_1_csr_res[root->segment];
> + port->csr_base = devm_ioremap_resource(dev, csr);
> + if (IS_ERR(port->csr_base)) {
> + kfree(port);
> + return -ENOMEM;
> + }
> +
> + port->cfg_base = cfg->win;
> + port->version = XGENE_PCIE_IP_VER_2;
> +
> + cfg->priv = port;
> +
> + return 0;
> +}
> +
> +struct pci_ecam_ops xgene_v2_1_pcie_ecam_ops = {
> + .bus_shift = 16,
> + .init = xgene_v2_1_pcie_ecam_init,
> + .pci_ops = {
> + .map_bus = xgene_pcie_map_bus,
> + .read = xgene_pcie_config_read32,
> + .write = pci_generic_config_write,
> + }
> +};
> +
> +static struct resource xgene_v2_2_csr_res[] = {
> + [0] = DEFINE_RES_MEM(0x1f2b0000UL, SZ_64K),
> + [1] = DEFINE_RES_MEM(0x1f500000UL, SZ_64K),
> + [2] = DEFINE_RES_MEM(0x1f2d0000UL, SZ_64K),
> +};
> +
> +static int xgene_v2_2_pcie_ecam_init(struct pci_config_window *cfg)
> +{
> + struct acpi_device *adev = to_acpi_device(cfg->parent);
> + struct acpi_pci_root *root = acpi_driver_data(adev);
> + struct device *dev = cfg->parent;
> + struct xgene_pcie_port *port;
> + struct resource *csr;
> +
> + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> + if (!port)
> + return -ENOMEM;
> +
> + csr = &xgene_v2_2_csr_res[root->segment];
> + port->csr_base = devm_ioremap_resource(dev, csr);
> + if (IS_ERR(port->csr_base)) {
> + kfree(port);
> + return -ENOMEM;
> + }
> +
> + port->cfg_base = cfg->win;
> + port->version = XGENE_PCIE_IP_VER_2;
> +
> + cfg->priv = port;
> +
> + return 0;
> +}
> +
> +struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops = {
> + .bus_shift = 16,
> + .init = xgene_v2_2_pcie_ecam_init,
> + .pci_ops = {
> + .map_bus = xgene_pcie_map_bus,
> + .read = xgene_pcie_config_read32,
> + .write = pci_generic_config_write,
> + }
> +};
> +#endif
> +
> static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
> u32 flags, u64 size)
> {
> diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
> index 35f0e81..40da3e7 100644
> --- a/include/linux/pci-ecam.h
> +++ b/include/linux/pci-ecam.h
> @@ -65,6 +65,11 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
> #ifdef CONFIG_PCI_HOST_THUNDER_ECAM
> extern struct pci_ecam_ops pci_thunder_ecam_ops;
> #endif
> +#ifdef CONFIG_PCI_XGENE
> +extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops;
> +extern struct pci_ecam_ops xgene_v2_1_pcie_ecam_ops;
> +extern struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops;
> +#endif
>
> #ifdef CONFIG_PCI_HOST_GENERIC
> /* for DT-based PCI controllers that support ECAM */
> --
> 1.9.1
>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox