* [PATCH 3/3] usb: ohci-da8xx: rename driver to ohci-da8xx
From: Sekhar Nori @ 2016-11-03 11:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161102124435.31777-4-ahaslam@baylibre.com>
On Wednesday 02 November 2016 06:14 PM, Axel Haslam wrote:
> To be consistent on the usb driver for the davinci
> platform follow the example of musb, and add the
> "-da8xx" postfix to the driver name.
>
> Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
> ---
> drivers/usb/host/ohci-da8xx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
> index bd6cf3c..b3de8bc 100644
> --- a/drivers/usb/host/ohci-da8xx.c
> +++ b/drivers/usb/host/ohci-da8xx.c
> @@ -27,7 +27,7 @@
> #include "ohci.h"
>
> #define DRIVER_DESC "DA8XX"
> -#define DRV_NAME "ohci"
> +#define DRV_NAME "ohci-da8xx"
To which baseline does this patch apply? I don't see this code in
linux-next.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH 0/3] fix ohci phy name
From: Sekhar Nori @ 2016-11-03 12:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKXjFTPiL6K8g2KuFrq9rKJpViVaGPuBDBFSKk9bjqjY3Zd5Rg@mail.gmail.com>
On Thursday 03 November 2016 01:54 PM, Axel Haslam wrote:
> Hi Sekhar, David,
>
> It might make sense to have this patch series,
> squashed into a single patch, would you agree,
> or do you prefer it as is: one-per-subsystem?
Patches in the current form are okay. Some coordination is required in
getting them merged though. I am happy to take the driver patches
through ARM-SoC with ack from respective maintainers.
I will need to carry the platform patch through my tree because it
conflicts with other changes I have already queued.
That said, I am unable to review 3/3 since I am unable to find its baseline.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH 3/3] usb: ohci-da8xx: rename driver to ohci-da8xx
From: Axel Haslam @ 2016-11-03 12:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a1b45345-ef63-ad6a-a755-57881355049d@ti.com>
Hi Sekhar,
The baseline used was the branch usb-next, in Greg's tree:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
Linux next is missing this patch[1] which was applied last week,
but not yet pulled into linux-next. it will be there soon.
Sorry, i did not mention it, i thought it would be already
on linux-next.
[1]
6c21caa USB: OHCI: make ohci-da8xx a separate driver
https://lkml.org/lkml/2016/10/27/120
Regards
Axel
On Thu, Nov 3, 2016 at 12:56 PM, Sekhar Nori <nsekhar@ti.com> wrote:
> On Wednesday 02 November 2016 06:14 PM, Axel Haslam wrote:
>> To be consistent on the usb driver for the davinci
>> platform follow the example of musb, and add the
>> "-da8xx" postfix to the driver name.
>>
>> Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
>> ---
>> drivers/usb/host/ohci-da8xx.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
>> index bd6cf3c..b3de8bc 100644
>> --- a/drivers/usb/host/ohci-da8xx.c
>> +++ b/drivers/usb/host/ohci-da8xx.c
>> @@ -27,7 +27,7 @@
>> #include "ohci.h"
>>
>> #define DRIVER_DESC "DA8XX"
>> -#define DRV_NAME "ohci"
>> +#define DRV_NAME "ohci-da8xx"
>
> To which baseline does this patch apply? I don't see this code in
> linux-next.
>
> Thanks,
> Sekhar
^ permalink raw reply
* [PATCH v3 3/5] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC
From: Andi Shyti @ 2016-11-03 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478155149-28527-4-git-send-email-cw00.choi@samsung.com>
Hi Chanwoo,
Tested-by: Andi Shyti <andi.shyti@samsung.com>
Andi
On Thu, Nov 03, 2016 at 03:39:07PM +0900, Chanwoo Choi wrote:
> This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
> Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
> PSCI (Power State Coordination Interface) v0.1.
>
> This patch includes following Device Tree node to support Exynos5433 SoC:
> 1. Octa cores for big.LITTLE architecture
> - Cortex-A53 LITTLE Quad-core
> - Cortex-A57 big Quad-core
> - Support PSCI v0.1
>
> 2. Clock controller node
> - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
> - CMU_CPIF : clocks for LLI (Low Latency Interface)
> - CMU_MIF : clocks for DRAM Memory Controller
> - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS
> - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC
> - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA
> - CMU_G2D : clocks for G2D/MDMA
> - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER
> - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO
> - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses
> - CMU_G3D : clocks for 3D Graphics Engine
> - CMU_GSCL : clocks for GSCALER
> - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor.
> - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor,
> CoreSight and L2 cache controller.
> - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs.
> - CMU_MFC : clocks for MFC (Multi-Format Codec) IP.
> - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP.
> - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
> - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.
> - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs.
>
> 3. pinctrl node for GPIO
> - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad
>
> 4. Timer
> - ARM architecture timer (armv8-timer)
> - MCT (Multi Core Timer) timer
>
> 5. Interrupt controller (GIC-400)
>
> 6. BUS devices
> - HS-I2C (High-Speed I2C) device
> - SPI (Serial Peripheral Interface) device
>
> 7. Sound devices
> - I2S bus
> - LPASS (Low Power Audio Subsystem)
>
> 8. Power management devices
> - CPUFREQ for for Cortex-A53/A57
> - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP
>
> 9. Display controller devices
> - DECON (Display and enhancement controller) for panel output
> - DSI (Display Serial Interface)
> - MIC (Mobile Image Compressor)
>
> 10. USB
> - USB 3.0 DRD (Dual Role Device) controller
> - USB 3.0 Host controller
>
> 11. Storage devices
> - MSHC (Mobile Storage Host Controller)
>
> 12. Misc devices
> - UART device
> - ADC (Analog Digital Converter)
> - PWM (Pulse Width Modulation)
> - ADMA (Advanced DMA) and PDMA (Peripheral DMA)
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Inki Dae <inki.dae@samsung.com>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> Signed-off-by: Inha Song <ideal.song@samsung.com>
> Signed-off-by: Ingi kim <ingi2.kim@samsung.com>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 794 ++++++++++++
> .../dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi | 23 +
> .../dts/exynos/exynos5433-tmu-sensor-conf.dtsi | 22 +
> arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 296 +++++
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1356 ++++++++++++++++++++
> 5 files changed, 2491 insertions(+)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
> new file mode 100644
> index 000000000000..796881310bf6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
> @@ -0,0 +1,794 @@
> +/*
> + * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + * Chanwoo Choi <cw00.choi@samsung.com>
> + *
> + * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
> + * tree nodes are listed in this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#define PIN_PULL_NONE 0
> +#define PIN_PULL_DOWN 1
> +#define PIN_PULL_UP 3
> +
> +#define PIN_DRV_LV1 0
> +#define PIN_DRV_LV2 2
> +#define PIN_DRV_LV3 1
> +#define PIN_DRV_LV4 3
> +
> +#define PIN_IN 0
> +#define PIN_OUT 1
> +#define PIN_FUNC1 2
> +
> +#define PIN(_func, _pin, _pull, _drv) \
> + _pin { \
> + samsung,pins = #_pin; \
> + samsung,pin-function = <PIN_ ##_func>; \
> + samsung,pin-pud = <PIN_PULL_ ##_pull>; \
> + samsung,pin-drv = <PIN_DRV_ ##_drv>; \
> + }
> +
> +&pinctrl_alive {
> + gpa0: gpa0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 0 0>, <GIC_SPI 1 0>, <GIC_SPI 2 0>,
> + <GIC_SPI 3 0>, <GIC_SPI 4 0>, <GIC_SPI 5 0>,
> + <GIC_SPI 6 0>, <GIC_SPI 7 0>;
> + #interrupt-cells = <2>;
> + };
> +
> + gpa1: gpa1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 8 0>, <GIC_SPI 9 0>, <GIC_SPI 10 0>,
> + <GIC_SPI 11 0>, <GIC_SPI 12 0>, <GIC_SPI 13 0>,
> + <GIC_SPI 14 0>, <GIC_SPI 15 0>;
> + #interrupt-cells = <2>;
> + };
> +
> + gpa2: gpa2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpa3: gpa3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf1: gpf1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf2: gpf2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf3: gpf3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf4: gpf4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf5: gpf5 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&pinctrl_aud {
> + gpz0: gpz0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpz1: gpz1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + i2s0_bus: i2s0-bus {
> + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
> + "gpz0-4", "gpz0-5", "gpz0-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pcm0_bus: pcm0-bus {
> + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + uart_aud_bus: uart-aud-bus {
> + samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +};
> +
> +&pinctrl_cpif {
> + gpv6: gpv6 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&pinctrl_ese {
> + gpj2: gpj2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&pinctrl_finger {
> + gpd5: gpd5 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + spi2_bus: spi2-bus {
> + samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c6_bus: hs-i2c6-bus {
> + samsung,pins = "gpd5-3", "gpd5-2";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +};
> +
> +&pinctrl_fsys {
> + gph1: gph1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr4: gpr4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr0: gpr0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr1: gpr1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr2: gpr2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr3: gpr3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + sd0_clk: sd0-clk {
> + samsung,pins = "gpr0-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_cmd: sd0-cmd {
> + samsung,pins = "gpr0-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_rdqs: sd0-rdqs {
> + samsung,pins = "gpr0-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_qrdy: sd0-qrdy {
> + samsung,pins = "gpr0-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus1: sd0-bus-width1 {
> + samsung,pins = "gpr1-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus4: sd0-bus-width4 {
> + samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus8: sd0-bus-width8 {
> + samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_clk: sd1-clk {
> + samsung,pins = "gpr2-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_cmd: sd1-cmd {
> + samsung,pins = "gpr2-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_bus1: sd1-bus-width1 {
> + samsung,pins = "gpr3-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_bus4: sd1-bus-width4 {
> + samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_bus8: sd1-bus-width8 {
> + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + pcie_bus: pcie_bus {
> + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + };
> +
> + sd2_clk: sd2-clk {
> + samsung,pins = "gpr4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_cmd: sd2-cmd {
> + samsung,pins = "gpr4-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_cd: sd2-cd {
> + samsung,pins = "gpr4-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_bus1: sd2-bus-width1 {
> + samsung,pins = "gpr4-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_bus4: sd2-bus-width4 {
> + samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_clk_output: sd2-clk-output {
> + samsung,pins = "gpr4-0";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd2_cmd_output: sd2-cmd-output {
> + samsung,pins = "gpr4-1";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <2>;
> + };
> +};
> +
> +&pinctrl_imem {
> + gpf0: gpf0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&pinctrl_nfc {
> + gpj0: gpj0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + hs_i2c4_bus: hs-i2c4-bus {
> + samsung,pins = "gpj0-1", "gpj0-0";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +};
> +
> +&pinctrl_peric {
> + gpv7: gpv7 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb0: gpb0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc0: gpc0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc1: gpc1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc2: gpc2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc3: gpc3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg0: gpg0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd0: gpd0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd1: gpd1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd2: gpd2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd4: gpd4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd8: gpd8 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd6: gpd6 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd7: gpd7 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg1: gpg1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg2: gpg2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg3: gpg3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + hs_i2c8_bus: hs-i2c8-bus {
> + samsung,pins = "gpb0-1", "gpb0-0";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c9_bus: hs-i2c9-bus {
> + samsung,pins = "gpb0-3", "gpb0-2";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + i2s1_bus: i2s1-bus {
> + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
> + "gpd4-3", "gpd4-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pcm1_bus: pcm1-bus {
> + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
> + "gpd4-3", "gpd4-4";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spdif_bus: spdif-bus {
> + samsung,pins = "gpd4-3", "gpd4-4";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_spi_pin0: fimc-is-spi-pin0 {
> + samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_spi_pin1: fimc-is-spi-pin1 {
> + samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + uart0_bus: uart0-bus {
> + samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + hs_i2c2_bus: hs-i2c2-bus {
> + samsung,pins = "gpd0-3", "gpd0-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + uart2_bus: uart2-bus {
> + samsung,pins = "gpd1-5", "gpd1-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + uart1_bus: uart1-bus {
> + samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + hs_i2c3_bus: hs-i2c3-bus {
> + samsung,pins = "gpd1-3", "gpd1-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c0_bus: hs-i2c0-bus {
> + samsung,pins = "gpd2-1", "gpd2-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c1_bus: hs-i2c1-bus {
> + samsung,pins = "gpd2-3", "gpd2-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pwm0_out: pwm0-out {
> + samsung,pins = "gpd2-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pwm1_out: pwm1-out {
> + samsung,pins = "gpd2-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pwm2_out: pwm2-out {
> + samsung,pins = "gpd2-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pwm3_out: pwm3-out {
> + samsung,pins = "gpd2-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi1_bus: spi1-bus {
> + samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c7_bus: hs-i2c7-bus {
> + samsung,pins = "gpd2-7", "gpd2-6";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi0_bus: spi0-bus {
> + samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c10_bus: hs-i2c10-bus {
> + samsung,pins = "gpg3-1", "gpg3-0";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c11_bus: hs-i2c11-bus {
> + samsung,pins = "gpg3-3", "gpg3-2";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi3_bus: spi3-bus {
> + samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi4_bus: spi4-bus {
> + samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_uart: fimc-is-uart {
> + samsung,pins = "gpc1-1", "gpc0-7";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch0_i2c: fimc-is-ch0_i2c {
> + samsung,pins = "gpc2-1", "gpc2-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch0_mclk: fimc-is-ch0_mclk {
> + samsung,pins = "gpd7-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch1_i2c: fimc-is-ch1-i2c {
> + samsung,pins = "gpc2-3", "gpc2-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch1_mclk: fimc-is-ch1-mclk {
> + samsung,pins = "gpd7-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch2_i2c: fimc-is-ch2-i2c {
> + samsung,pins = "gpc2-5", "gpc2-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch2_mclk: fimc-is-ch2-mclk {
> + samsung,pins = "gpd7-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +};
> +
> +&pinctrl_touch {
> + gpj1: gpj1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + hs_i2c5_bus: hs-i2c5-bus {
> + samsung,pins = "gpj1-1", "gpj1-0";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
> new file mode 100644
> index 000000000000..9be2978f1b9a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
> @@ -0,0 +1,23 @@
> +/*
> + * Device tree sources for Exynos5433 TMU sensor configuration
> + *
> + * Copyright (c) 2016 Jonghwa Lee <jonghwa3.lee@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/thermal/thermal_exynos.h>
> +
> +#thermal-sensor-cells = <0>;
> +samsung,tmu_gain = <8>;
> +samsung,tmu_reference_voltage = <23>;
> +samsung,tmu_noise_cancel_mode = <4>;
> +samsung,tmu_efuse_value = <75>;
> +samsung,tmu_min_efuse_value = <40>;
> +samsung,tmu_max_efuse_value = <150>;
> +samsung,tmu_first_point_trim = <25>;
> +samsung,tmu_second_point_trim = <85>;
> +samsung,tmu_default_temp_offset = <50>;
> +samsung,tmu_mux_addr = <6>;
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
> new file mode 100644
> index 000000000000..125fe58d77ce
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
> @@ -0,0 +1,22 @@
> +/*
> + * Device tree sources for Exynos5433 TMU sensor configuration
> + *
> + * Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/thermal/thermal_exynos.h>
> +
> +#thermal-sensor-cells = <0>;
> +samsung,tmu_gain = <8>;
> +samsung,tmu_reference_voltage = <16>;
> +samsung,tmu_noise_cancel_mode = <4>;
> +samsung,tmu_efuse_value = <75>;
> +samsung,tmu_min_efuse_value = <40>;
> +samsung,tmu_max_efuse_value = <150>;
> +samsung,tmu_first_point_trim = <25>;
> +samsung,tmu_second_point_trim = <85>;
> +samsung,tmu_default_temp_offset = <50>;
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
> new file mode 100644
> index 000000000000..ceaa05145b8a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
> @@ -0,0 +1,296 @@
> +/*
> + * Device tree sources for Exynos5433 thermal zone
> + *
> + * Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> +thermal-zones {
> + atlas0_thermal: atlas0-thermal {
> + thermal-sensors = <&tmu_atlas0>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + atlas0_alert_0: atlas0-alert-0 {
> + temperature = <65000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_1: atlas0-alert-1 {
> + temperature = <70000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_2: atlas0-alert-2 {
> + temperature = <75000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_3: atlas0-alert-3 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_4: atlas0-alert-4 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_5: atlas0-alert-5 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_6: atlas0-alert-6 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + /* Set maximum frequency as 1800MHz */
> + trip = <&atlas0_alert_0>;
> + cooling-device = <&cpu4 1 2>;
> + };
> + map1 {
> + /* Set maximum frequency as 1700MHz */
> + trip = <&atlas0_alert_1>;
> + cooling-device = <&cpu4 2 3>;
> + };
> + map2 {
> + /* Set maximum frequency as 1600MHz */
> + trip = <&atlas0_alert_2>;
> + cooling-device = <&cpu4 3 4>;
> + };
> + map3 {
> + /* Set maximum frequency as 1500MHz */
> + trip = <&atlas0_alert_3>;
> + cooling-device = <&cpu4 4 5>;
> + };
> + map4 {
> + /* Set maximum frequency as 1400MHz */
> + trip = <&atlas0_alert_4>;
> + cooling-device = <&cpu4 5 7>;
> + };
> + map5 {
> + /* Set maximum frequencyas 1200MHz */
> + trip = <&atlas0_alert_5>;
> + cooling-device = <&cpu4 7 9>;
> + };
> + map6 {
> + /* Set maximum frequency as 1000MHz */
> + trip = <&atlas0_alert_6>;
> + cooling-device = <&cpu4 9 14>;
> + };
> + };
> + };
> +
> + atlas1_thermal: atlas1-thermal {
> + thermal-sensors = <&tmu_atlas1>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + atlas1_alert_0: atlas1-alert-0 {
> + temperature = <65000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_1: atlas1-alert-1 {
> + temperature = <70000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_2: atlas1-alert-2 {
> + temperature = <75000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_3: atlas1-alert-3 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_4: atlas1-alert-4 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_5: atlas1-alert-5 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_6: atlas1-alert-6 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> + };
> +
> + g3d_thermal: g3d-thermal {
> + thermal-sensors = <&tmu_g3d>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + g3d_alert_0: g3d-alert-0 {
> + temperature = <70000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_1: g3d-alert-1 {
> + temperature = <75000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_2: g3d-alert-2 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_3: g3d-alert-3 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_4: g3d-alert-4 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_5: g3d-alert-5 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_6: g3d-alert-6 {
> + temperature = <100000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> + };
> +
> + apollo_thermal: apollo-thermal {
> + thermal-sensors = <&tmu_apollo>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + apollo_alert_0: apollo-alert-0 {
> + temperature = <65000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_1: apollo-alert-1 {
> + temperature = <70000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_2: apollo-alert-2 {
> + temperature = <75000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_3: apollo-alert-3 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_4: apollo-alert-4 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_5: apollo-alert-5 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_6: apollo-alert-6 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + /* Set maximum frequency as 1200MHz */
> + trip = <&apollo_alert_2>;
> + cooling-device = <&cpu0 1 2>;
> + };
> + map1 {
> + /* Set maximum frequency as 1100MHz */
> + trip = <&apollo_alert_3>;
> + cooling-device = <&cpu0 2 3>;
> + };
> + map2 {
> + /* Set maximum frequency as 1000MHz */
> + trip = <&apollo_alert_4>;
> + cooling-device = <&cpu0 3 4>;
> + };
> + map3 {
> + /* Set maximum frequency as 900MHz */
> + trip = <&apollo_alert_5>;
> + cooling-device = <&cpu0 4 5>;
> + };
> + map4 {
> + /* Set maximum frequency as 800MHz */
> + trip = <&apollo_alert_6>;
> + cooling-device = <&cpu0 5 9>;
> + };
> + };
> + };
> +
> + isp_thermal: isp-thermal {
> + thermal-sensors = <&tmu_isp>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + isp_alert_0: isp-alert-0 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_1: isp-alert-1 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_2: isp-alert-2 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_3: isp-alert-3 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_4: isp-alert-4 {
> + temperature = <100000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_5: isp-alert-5 {
> + temperature = <105000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_6: isp-alert-6 {
> + temperature = <110000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> + };
> +};
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> new file mode 100644
> index 000000000000..1188630823a7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -0,0 +1,1356 @@
> +/*
> + * Samsung's Exynos5433 SoC device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Samsung's Exynos5433 SoC device nodes are listed in this file.
> + * Exynos5433 based board files can include this file and provide
> + * values for board specific bindings.
> + *
> + * Note: This file does not include device nodes for all the controllers in
> + * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
> + * additional nodes can be added to this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/clock/exynos5433.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "samsung,exynos5433";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + interrupt-parent = <&gic>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x100>;
> + clock-frequency = <1300000000>;
> + clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
> + clock-names = "apolloclk";
> + operating-points-v2 = <&cluster_a53_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu1: cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x101>;
> + clock-frequency = <1300000000>;
> + operating-points-v2 = <&cluster_a53_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu2: cpu at 102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x102>;
> + clock-frequency = <1300000000>;
> + operating-points-v2 = <&cluster_a53_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu3: cpu at 103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x103>;
> + clock-frequency = <1300000000>;
> + operating-points-v2 = <&cluster_a53_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu4: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x0>;
> + clock-frequency = <1900000000>;
> + clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
> + clock-names = "atlasclk";
> + operating-points-v2 = <&cluster_a57_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu5: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x1>;
> + clock-frequency = <1900000000>;
> + operating-points-v2 = <&cluster_a57_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu6: cpu at 2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x2>;
> + clock-frequency = <1900000000>;
> + operating-points-v2 = <&cluster_a57_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu7: cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x3>;
> + clock-frequency = <1900000000>;
> + operating-points-v2 = <&cluster_a57_opp_table>;
> + #cooling-cells = <2>;
> + };
> + };
> +
> + cluster_a53_opp_table: opp_table0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp at 400000000 {
> + opp-hz = /bits/ 64 <400000000>;
> + opp-microvolt = <900000>;
> + };
> + opp at 500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-microvolt = <925000>;
> + };
> + opp at 600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <950000>;
> + };
> + opp at 700000000 {
> + opp-hz = /bits/ 64 <700000000>;
> + opp-microvolt = <975000>;
> + };
> + opp at 800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <1000000>;
> + };
> + opp at 900000000 {
> + opp-hz = /bits/ 64 <900000000>;
> + opp-microvolt = <1050000>;
> + };
> + opp at 1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <1075000>;
> + };
> + opp at 1100000000 {
> + opp-hz = /bits/ 64 <1100000000>;
> + opp-microvolt = <1112500>;
> + };
> + opp at 1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1112500>;
> + };
> + opp at 1300000000 {
> + opp-hz = /bits/ 64 <1300000000>;
> + opp-microvolt = <1150000>;
> + };
> + };
> +
> + cluster_a57_opp_table: opp_table1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp at 500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-microvolt = <900000>;
> + };
> + opp at 600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <900000>;
> + };
> + opp at 700000000 {
> + opp-hz = /bits/ 64 <700000000>;
> + opp-microvolt = <912500>;
> + };
> + opp at 800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <912500>;
> + };
> + opp at 900000000 {
> + opp-hz = /bits/ 64 <900000000>;
> + opp-microvolt = <937500>;
> + };
> + opp at 1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <975000>;
> + };
> + opp at 1100000000 {
> + opp-hz = /bits/ 64 <1100000000>;
> + opp-microvolt = <1012500>;
> + };
> + opp at 1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1037500>;
> + };
> + opp at 1300000000 {
> + opp-hz = /bits/ 64 <1300000000>;
> + opp-microvolt = <1062500>;
> + };
> + opp at 1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-microvolt = <1087500>;
> + };
> + opp at 1500000000 {
> + opp-hz = /bits/ 64 <1500000000>;
> + opp-microvolt = <1125000>;
> + };
> + opp at 1600000000 {
> + opp-hz = /bits/ 64 <1600000000>;
> + opp-microvolt = <1137500>;
> + };
> + opp at 1700000000 {
> + opp-hz = /bits/ 64 <1700000000>;
> + opp-microvolt = <1175000>;
> + };
> + opp at 1800000000 {
> + opp-hz = /bits/ 64 <1800000000>;
> + opp-microvolt = <1212500>;
> + };
> + opp at 1900000000 {
> + opp-hz = /bits/ 64 <1900000000>;
> + opp-microvolt = <1262500>;
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci";
> + method = "smc";
> + cpu_off = <0x84000002>;
> + cpu_on = <0xC4000003>;
> + };
> +
> + reboot: syscon-reboot {
> + compatible = "syscon-reboot";
> + regmap = <&pmu_system_controller>;
> + offset = <0x400>; /* SWRESET */
> + mask = <0x1>;
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x18000000>;
> +
> + chipid at 10000000 {
> + compatible = "samsung,exynos4210-chipid";
> + reg = <0x10000000 0x100>;
> + };
> +
> + xxti: xxti {
> + compatible = "fixed-clock";
> + clock-output-names = "oscclk";
> + #clock-cells = <0>;
> + };
> +
> + cmu_top: clock-controller at 10030000 {
> + compatible = "samsung,exynos5433-cmu-top";
> + reg = <0x10030000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_mphy_pll",
> + "sclk_mfc_pll",
> + "sclk_bus_pll";
> + clocks = <&xxti>,
> + <&cmu_cpif CLK_SCLK_MPHY_PLL>,
> + <&cmu_mif CLK_SCLK_MFC_PLL>,
> + <&cmu_mif CLK_SCLK_BUS_PLL>;
> + };
> +
> + cmu_cpif: clock-controller at 10fc0000 {
> + compatible = "samsung,exynos5433-cmu-cpif";
> + reg = <0x10fc0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk";
> + clocks = <&xxti>;
> + };
> +
> + cmu_mif: clock-controller at 105b0000 {
> + compatible = "samsung,exynos5433-cmu-mif";
> + reg = <0x105b0000 0x2000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_mphy_pll";
> + clocks = <&xxti>,
> + <&cmu_cpif CLK_SCLK_MPHY_PLL>;
> + };
> +
> + cmu_peric: clock-controller at 14c80000 {
> + compatible = "samsung,exynos5433-cmu-peric";
> + reg = <0x14c80000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + cmu_peris: clock-controller at 0x10040000 {
> + compatible = "samsung,exynos5433-cmu-peris";
> + reg = <0x10040000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + cmu_fsys: clock-controller at 156e0000 {
> + compatible = "samsung,exynos5433-cmu-fsys";
> + reg = <0x156e0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_ufs_mphy",
> + "div_aclk_fsys_200",
> + "sclk_pcie_100_fsys",
> + "sclk_ufsunipro_fsys",
> + "sclk_mmc2_fsys",
> + "sclk_mmc1_fsys",
> + "sclk_mmc0_fsys",
> + "sclk_usbhost30_fsys",
> + "sclk_usbdrd30_fsys";
> + clocks = <&xxti>,
> + <&cmu_cpif CLK_SCLK_UFS_MPHY>,
> + <&cmu_top CLK_DIV_ACLK_FSYS_200>,
> + <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
> + <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
> + <&cmu_top CLK_SCLK_MMC2_FSYS>,
> + <&cmu_top CLK_SCLK_MMC1_FSYS>,
> + <&cmu_top CLK_SCLK_MMC0_FSYS>,
> + <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> + <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
> + };
> +
> + cmu_g2d: clock-controller at 12460000 {
> + compatible = "samsung,exynos5433-cmu-g2d";
> + reg = <0x12460000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "aclk_g2d_266",
> + "aclk_g2d_400";
> + clocks = <&xxti>,
> + <&cmu_top CLK_ACLK_G2D_266>,
> + <&cmu_top CLK_ACLK_G2D_400>;
> + };
> +
> + cmu_disp: clock-controller at 13b90000 {
> + compatible = "samsung,exynos5433-cmu-disp";
> + reg = <0x13b90000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_dsim1_disp",
> + "sclk_dsim0_disp",
> + "sclk_dsd_disp",
> + "sclk_decon_tv_eclk_disp",
> + "sclk_decon_vclk_disp",
> + "sclk_decon_eclk_disp",
> + "sclk_decon_tv_vclk_disp",
> + "aclk_disp_333";
> + clocks = <&xxti>,
> + <&cmu_mif CLK_SCLK_DSIM1_DISP>,
> + <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> + <&cmu_mif CLK_SCLK_DSD_DISP>,
> + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> + <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
> + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> + <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
> + <&cmu_mif CLK_ACLK_DISP_333>;
> + };
> +
> + cmu_aud: clock-controller at 114c0000 {
> + compatible = "samsung,exynos5433-cmu-aud";
> + reg = <0x114c0000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + cmu_bus0: clock-controller at 13600000 {
> + compatible = "samsung,exynos5433-cmu-bus0";
> + reg = <0x13600000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "aclk_bus0_400";
> + clocks = <&cmu_top CLK_ACLK_BUS0_400>;
> + };
> +
> + cmu_bus1: clock-controller at 14800000 {
> + compatible = "samsung,exynos5433-cmu-bus1";
> + reg = <0x14800000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "aclk_bus1_400";
> + clocks = <&cmu_top CLK_ACLK_BUS1_400>;
> + };
> +
> + cmu_bus2: clock-controller at 13400000 {
> + compatible = "samsung,exynos5433-cmu-bus2";
> + reg = <0x13400000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "aclk_bus2_400";
> + clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
> + };
> +
> + cmu_g3d: clock-controller at 14aa0000 {
> + compatible = "samsung,exynos5433-cmu-g3d";
> + reg = <0x14aa0000 0x2000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "aclk_g3d_400";
> + clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
> + };
> +
> + cmu_gscl: clock-controller at 13cf0000 {
> + compatible = "samsung,exynos5433-cmu-gscl";
> + reg = <0x13cf0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "aclk_gscl_111",
> + "aclk_gscl_333";
> + clocks = <&xxti>,
> + <&cmu_top CLK_ACLK_GSCL_111>,
> + <&cmu_top CLK_ACLK_GSCL_333>;
> + };
> +
> + cmu_apollo: clock-controller at 11900000 {
> + compatible = "samsung,exynos5433-cmu-apollo";
> + reg = <0x11900000 0x2000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "sclk_bus_pll_apollo";
> + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
> + };
> +
> + cmu_atlas: clock-controller at 11800000 {
> + compatible = "samsung,exynos5433-cmu-atlas";
> + reg = <0x11800000 0x2000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "sclk_bus_pll_atlas";
> + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
> + };
> +
> + cmu_mscl: clock-controller at 105d0000 {
> + compatible = "samsung,exynos5433-cmu-mscl";
> + reg = <0x150d0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_jpeg_mscl",
> + "aclk_mscl_400";
> + clocks = <&xxti>,
> + <&cmu_top CLK_SCLK_JPEG_MSCL>,
> + <&cmu_top CLK_ACLK_MSCL_400>;
> + };
> +
> + cmu_mfc: clock-controller at 15280000 {
> + compatible = "samsung,exynos5433-cmu-mfc";
> + reg = <0x15280000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "aclk_mfc_400";
> + clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
> + };
> +
> + cmu_hevc: clock-controller at 14f80000 {
> + compatible = "samsung,exynos5433-cmu-hevc";
> + reg = <0x14f80000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "aclk_hevc_400";
> + clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
> + };
> +
> + cmu_isp: clock-controller at 146d0000 {
> + compatible = "samsung,exynos5433-cmu-isp";
> + reg = <0x146d0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "aclk_isp_dis_400",
> + "aclk_isp_400";
> + clocks = <&xxti>,
> + <&cmu_top CLK_ACLK_ISP_DIS_400>,
> + <&cmu_top CLK_ACLK_ISP_400>;
> + };
> +
> + cmu_cam0: clock-controller at 120d0000 {
> + compatible = "samsung,exynos5433-cmu-cam0";
> + reg = <0x120d0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "aclk_cam0_333",
> + "aclk_cam0_400",
> + "aclk_cam0_552";
> + clocks = <&xxti>,
> + <&cmu_top CLK_ACLK_CAM0_333>,
> + <&cmu_top CLK_ACLK_CAM0_400>,
> + <&cmu_top CLK_ACLK_CAM0_552>;
> + };
> +
> + cmu_cam1: clock-controller at 145d0000 {
> + compatible = "samsung,exynos5433-cmu-cam1";
> + reg = <0x145d0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_isp_uart_cam1",
> + "sclk_isp_spi1_cam1",
> + "sclk_isp_spi0_cam1",
> + "aclk_cam1_333",
> + "aclk_cam1_400",
> + "aclk_cam1_552";
> + clocks = <&xxti>,
> + <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
> + <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
> + <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
> + <&cmu_top CLK_ACLK_CAM1_333>,
> + <&cmu_top CLK_ACLK_CAM1_400>,
> + <&cmu_top CLK_ACLK_CAM1_552>;
> + };
> +
> + tmu_atlas0: tmu at 10060000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x10060000 0x200>;
> + interrupts = <GIC_SPI 95 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU0>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + tmu_atlas1: tmu at 10068000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x10068000 0x200>;
> + interrupts = <GIC_SPI 96 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU0>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + tmu_g3d: tmu at 10070000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x10070000 0x200>;
> + interrupts = <GIC_SPI 99 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU1>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + tmu_apollo: tmu at 10078000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x10078000 0x200>;
> + interrupts = <GIC_SPI 115 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU1>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + tmu_isp: tmu at 1007c000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x1007c000 0x200>;
> + interrupts = <GIC_SPI 94 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU1>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + mct at 101c0000 {
> + compatible = "samsung,exynos4210-mct";
> + reg = <0x101c0000 0x800>;
> + interrupts = <GIC_SPI 102 0>, <GIC_SPI 103 0>,
> + <GIC_SPI 104 0>, <GIC_SPI 105 0>,
> + <GIC_SPI 106 0>, <GIC_SPI 107 0>,
> + <GIC_SPI 108 0>, <GIC_SPI 109 0>,
> + <GIC_SPI 110 0>, <GIC_SPI 111 0>,
> + <GIC_SPI 112 0>, <GIC_SPI 113 0>;
> + clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
> + clock-names = "fin_pll", "mct";
> + };
> +
> + pinctrl_alive: pinctrl at 10580000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
> +
> + wakeup-interrupt-controller {
> + compatible = "samsung,exynos7-wakeup-eint";
> + interrupts = <GIC_SPI 16 0>;
> + };
> + };
> +
> + pinctrl_aud: pinctrl at 114b0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x114b0000 0x1000>;
> + interrupts = <GIC_SPI 68 0>;
> + };
> +
> + pinctrl_cpif: pinctrl at 10fe0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x10fe0000 0x1000>;
> + interrupts = <GIC_SPI 179 0>;
> + };
> +
> + pinctrl_ese: pinctrl at 14ca0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14ca0000 0x1000>;
> + interrupts = <GIC_SPI 413 0>;
> + };
> +
> + pinctrl_finger: pinctrl at 14cb0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14cb0000 0x1000>;
> + interrupts = <GIC_SPI 414 0>;
> + };
> +
> + pinctrl_fsys: pinctrl at 15690000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x15690000 0x1000>;
> + interrupts = <GIC_SPI 229 0>;
> + };
> +
> + pinctrl_imem: pinctrl at 11090000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x11090000 0x1000>;
> + interrupts = <GIC_SPI 325 0>;
> + };
> +
> + pinctrl_nfc: pinctrl at 14cd0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14cd0000 0x1000>;
> + interrupts = <GIC_SPI 441 0>;
> + };
> +
> + pinctrl_peric: pinctrl at 14cc0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14cc0000 0x1100>;
> + interrupts = <GIC_SPI 440 0>;
> + };
> +
> + pinctrl_touch: pinctrl at 14ce0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14ce0000 0x1100>;
> + interrupts = <GIC_SPI 442 0>;
> + };
> +
> + pmu_system_controller: system-controller at 105c0000 {
> + compatible = "samsung,exynos5433-pmu", "syscon";
> + reg = <0x105c0000 0x5008>;
> + #clock-cells = <1>;
> + clock-names = "clkout16";
> + clocks = <&xxti>;
> + };
> +
> + gic: interrupt-controller at 11001000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x11001000 0x1000>,
> + <0x11002000 0x2000>,
> + <0x11004000 0x2000>,
> + <0x11006000 0x2000>;
> + interrupts = <GIC_PPI 9 0xf04>;
> + };
> +
> + mipi_phy: video-phy at 105c0710 {
> + compatible = "samsung,exynos5433-mipi-video-phy";
> + #phy-cells = <1>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + samsung,cam0-sysreg = <&syscon_cam0>;
> + samsung,cam1-sysreg = <&syscon_cam1>;
> + samsung,disp-sysreg = <&syscon_disp>;
> + };
> +
> + decon: decon at 13800000 {
> + compatible = "samsung,exynos5433-decon";
> + reg = <0x13800000 0x2104>;
> + clocks = <&cmu_disp CLK_PCLK_DECON>,
> + <&cmu_disp CLK_ACLK_DECON>,
> + <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
> + <&cmu_disp CLK_ACLK_XIU_DECON0X>,
> + <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
> + <&cmu_disp CLK_SCLK_DECON_VCLK>,
> + <&cmu_disp CLK_SCLK_DECON_ECLK>;
> + clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
> + "aclk_xiu_decon0x", "pclk_smmu_decon0x",
> + "sclk_decon_vclk", "sclk_decon_eclk";
> + interrupt-names = "fifo", "vsync", "lcd_sys";
> + interrupts = <GIC_SPI 201 0>, <GIC_SPI 202 0>,
> + <GIC_SPI 203 0>;
> + samsung,disp-sysreg = <&syscon_disp>;
> + status = "disabled";
> + iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
> + iommu-names = "m0", "m1";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + decon_to_mic: endpoint {
> + remote-endpoint =
> + <&mic_to_decon>;
> + };
> + };
> + };
> + };
> +
> + dsi: dsi at 13900000 {
> + compatible = "samsung,exynos5433-mipi-dsi";
> + reg = <0x13900000 0xC0>;
> + interrupts = <GIC_SPI 205 0>;
> + phys = <&mipi_phy 1>;
> + phy-names = "dsim";
> + clocks = <&cmu_disp CLK_PCLK_DSIM0>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
> + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
> + <&cmu_disp CLK_SCLK_DSIM0>;
> + clock-names = "bus_clk",
> + "phyclk_mipidphy0_bitclkdiv8",
> + "phyclk_mipidphy0_rxclkesc0",
> + "sclk_rgb_vclk_to_dsim0",
> + "sclk_mipi";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + dsi_to_mic: endpoint {
> + remote-endpoint = <&mic_to_dsi>;
> + };
> + };
> + };
> + };
> +
> + mic: mic at 13930000 {
> + compatible = "samsung,exynos5433-mic";
> + reg = <0x13930000 0x48>;
> + clocks = <&cmu_disp CLK_PCLK_MIC0>,
> + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
> + clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
> + samsung,disp-syscon = <&syscon_disp>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + mic_to_decon: endpoint {
> + remote-endpoint =
> + <&decon_to_mic>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> + mic_to_dsi: endpoint {
> + remote-endpoint = <&dsi_to_mic>;
> + };
> + };
> + };
> + };
> +
> + syscon_disp: syscon at 13b80000 {
> + compatible = "syscon";
> + reg = <0x13b80000 0x1010>;
> + };
> +
> + syscon_cam0: syscon at 120f0000 {
> + compatible = "syscon";
> + reg = <0x120f0000 0x1020>;
> + };
> +
> + syscon_cam1: syscon at 145f0000 {
> + compatible = "syscon";
> + reg = <0x145f0000 0x1038>;
> + };
> +
> + sysmmu_decon0x: sysmmu at 0x13a00000 {
> + compatible = "samsung,exynos-sysmmu";
> + reg = <0x13a00000 0x1000>;
> + interrupts = <GIC_SPI 192 0>;
> + clock-names = "pclk", "aclk";
> + clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
> + <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
> + #iommu-cells = <0>;
> + };
> +
> + sysmmu_decon1x: sysmmu at 0x13a10000 {
> + compatible = "samsung,exynos-sysmmu";
> + reg = <0x13a10000 0x1000>;
> + interrupts = <GIC_SPI 194 0>;
> + clock-names = "pclk", "aclk";
> + clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
> + <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
> + #iommu-cells = <0>;
> + };
> +
> + serial_0: serial at 14c10000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x14c10000 0x100>;
> + interrupts = <GIC_SPI 421 0>;
> + clocks = <&cmu_peric CLK_PCLK_UART0>,
> + <&cmu_peric CLK_SCLK_UART0>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_bus>;
> + status = "disabled";
> + };
> +
> + serial_1: serial at 14c20000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x14c20000 0x100>;
> + interrupts = <GIC_SPI 422 0>;
> + clocks = <&cmu_peric CLK_PCLK_UART1>,
> + <&cmu_peric CLK_SCLK_UART1>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_bus>;
> + status = "disabled";
> + };
> +
> + serial_2: serial at 14c30000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x14c30000 0x100>;
> + interrupts = <GIC_SPI 423 0>;
> + clocks = <&cmu_peric CLK_PCLK_UART2>,
> + <&cmu_peric CLK_SCLK_UART2>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_bus>;
> + status = "disabled";
> + };
> +
> + spi_0: spi at 14d20000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d20000 0x100>;
> + interrupts = <GIC_SPI 432 0>;
> + dmas = <&pdma0 9>, <&pdma0 8>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI0>,
> + <&cmu_peric CLK_SCLK_SPI0>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + spi_1: spi at 14d30000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d30000 0x100>;
> + interrupts = <GIC_SPI 433 0>;
> + dmas = <&pdma0 11>, <&pdma0 10>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI1>,
> + <&cmu_peric CLK_SCLK_SPI1>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi1_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + spi_2: spi at 14d40000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d40000 0x100>;
> + interrupts = <GIC_SPI 434 0>;
> + dmas = <&pdma0 13>, <&pdma0 12>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI2>,
> + <&cmu_peric CLK_SCLK_SPI2>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi2_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + spi_3: spi at 14d50000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d50000 0x100>;
> + interrupts = <GIC_SPI 447 0>;
> + dmas = <&pdma0 23>, <&pdma0 22>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI3>,
> + <&cmu_peric CLK_SCLK_SPI3>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi3_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + spi_4: spi at 14d00000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d00000 0x100>;
> + interrupts = <GIC_SPI 412 0>;
> + dmas = <&pdma0 25>, <&pdma0 24>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI4>,
> + <&cmu_peric CLK_SCLK_SPI4>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi4_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + adc: adc at 14d10000 {
> + compatible = "samsung,exynos7-adc";
> + reg = <0x14d10000 0x100>;
> + interrupts = <GIC_SPI 438 0>;
> + clock-names = "adc";
> + clocks = <&cmu_peric CLK_PCLK_ADCIF>;
> + #io-channel-cells = <1>;
> + io-channel-ranges;
> + status = "disabled";
> + };
> +
> + pwm: pwm at 14dd0000 {
> + compatible = "samsung,exynos4210-pwm";
> + reg = <0x14dd0000 0x100>;
> + interrupts = <GIC_SPI 416 0>, <GIC_SPI 417 0>,
> + <GIC_SPI 418 0>, <GIC_SPI 419 0>,
> + <GIC_SPI 420 0>;
> + samsung,pwm-outputs = <0>, <1>, <2>, <3>;
> + clocks = <&cmu_peric CLK_PCLK_PWM>;
> + clock-names = "timers";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + hsi2c_0: hsi2c at 14e40000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14e40000 0x1000>;
> + interrupts = <GIC_SPI 428 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c0_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_1: hsi2c at 14e50000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14e50000 0x1000>;
> + interrupts = <GIC_SPI 429 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c1_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_2: hsi2c at 14e60000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14e60000 0x1000>;
> + interrupts = <GIC_SPI 430 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c2_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_3: hsi2c at 14e70000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14e70000 0x1000>;
> + interrupts = <GIC_SPI 431 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c3_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_4: hsi2c at 14ec0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14ec0000 0x1000>;
> + interrupts = <GIC_SPI 424 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c4_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_5: hsi2c at 14ed0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14ed0000 0x1000>;
> + interrupts = <GIC_SPI 425 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c5_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_6: hsi2c at 14ee0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14ee0000 0x1000>;
> + interrupts = <GIC_SPI 426 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c6_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_7: hsi2c at 14ef0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14ef0000 0x1000>;
> + interrupts = <GIC_SPI 427 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c7_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_8: hsi2c at 14d90000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14d90000 0x1000>;
> + interrupts = <GIC_SPI 443 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c8_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_9: hsi2c at 14da0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14da0000 0x1000>;
> + interrupts = <GIC_SPI 444 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c9_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_10: hsi2c at 14de0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14de0000 0x1000>;
> + interrupts = <GIC_SPI 445 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c10_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_11: hsi2c at 14df0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14df0000 0x1000>;
> + interrupts = <GIC_SPI 446 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c11_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + usbdrd30: usb at 15400000 {
> + compatible = "samsung,exynos5250-dwusb3";
> + clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
> + <&cmu_fsys CLK_SCLK_USBDRD30>;
> + clock-names = "usbdrd30", "usbdrd30_susp_clk";
> + assigned-clocks =
> + <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> + <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> + <&cmu_top CLK_DIV_SCLK_USBDRD30>;
> + assigned-clock-parents =
> + <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> + assigned-clock-rates = <0>, <0>, <66700000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + dwc3 at 15400000 {
> + compatible = "snps,dwc3";
> + reg = <0x15400000 0x10000>;
> + interrupts = <GIC_SPI 231 0>;
> + phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
> + phy-names = "usb2-phy", "usb3-phy";
> + };
> + };
> +
> + usbdrd30_phy: phy at 15500000 {
> + compatible = "samsung,exynos5433-usbdrd-phy";
> + reg = <0x15500000 0x100>;
> + clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
> + <&cmu_fsys CLK_SCLK_USBDRD30>;
> + clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
> + "itp";
> + assigned-clocks =
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
> + assigned-clock-parents =
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
> + #phy-cells = <1>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + status = "disabled";
> + };
> +
> + usbhost30_phy: phy at 15580000 {
> + compatible = "samsung,exynos5433-usbdrd-phy";
> + reg = <0x15580000 0x100>;
> + clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
> + <&cmu_fsys CLK_SCLK_USBHOST30>;
> + clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
> + "itp";
> + assigned-clocks =
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
> + assigned-clock-parents =
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
> + #phy-cells = <1>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + status = "disabled";
> + };
> +
> + usbhost30: usb at 15a00000 {
> + compatible = "samsung,exynos5250-dwusb3";
> + clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
> + <&cmu_fsys CLK_SCLK_USBHOST30>;
> + clock-names = "usbdrd30", "usbdrd30_susp_clk";
> + assigned-clocks =
> + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> + <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> + <&cmu_top CLK_DIV_SCLK_USBHOST30>;
> + assigned-clock-parents =
> + <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> + assigned-clock-rates = <0>, <0>, <66700000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + usbdrd_dwc3_0: dwc3 at 15a00000 {
> + compatible = "snps,dwc3";
> + reg = <0x15a00000 0x10000>;
> + interrupts = <GIC_SPI 244 0>;
> + phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
> + phy-names = "usb2-phy", "usb3-phy";
> + };
> + };
> +
> + mshc_0: mshc at 15540000 {
> + compatible = "samsung,exynos7-dw-mshc-smu";
> + interrupts = <GIC_SPI 225 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x15540000 0x2000>;
> + clocks = <&cmu_fsys CLK_ACLK_MMC0>,
> + <&cmu_fsys CLK_SCLK_MMC0>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x40>;
> + status = "disabled";
> + };
> +
> + mshc_1: mshc at 15550000 {
> + compatible = "samsung,exynos7-dw-mshc-smu";
> + interrupts = <GIC_SPI 226 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x15550000 0x2000>;
> + clocks = <&cmu_fsys CLK_ACLK_MMC1>,
> + <&cmu_fsys CLK_SCLK_MMC1>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x40>;
> + status = "disabled";
> + };
> +
> + mshc_2: mshc at 15560000 {
> + compatible = "samsung,exynos7-dw-mshc-smu";
> + interrupts = <GIC_SPI 227 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x15560000 0x2000>;
> + clocks = <&cmu_fsys CLK_ACLK_MMC2>,
> + <&cmu_fsys CLK_SCLK_MMC2>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x40>;
> + status = "disabled";
> + };
> +
> + amba {
> + compatible = "arm,amba-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + pdma0: pdma at 15610000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x15610000 0x1000>;
> + interrupts = <GIC_SPI 228 0>;
> + clocks = <&cmu_fsys CLK_PDMA0>;
> + clock-names = "apb_pclk";
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + };
> +
> + pdma1: pdma at 15600000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x15600000 0x1000>;
> + interrupts = <GIC_SPI 246 0>;
> + clocks = <&cmu_fsys CLK_PDMA1>;
> + clock-names = "apb_pclk";
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + };
> + };
> +
> + audio-subsystem at 11400000 {
> + compatible = "samsung,exynos5433-lpass";
> + reg = <0x11400000 0x100>, <0x11500000 0x08>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + adma: adma at 11420000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x11420000 0x1000>;
> + interrupts = <GIC_SPI 73 0>;
> + clocks = <&cmu_aud CLK_ACLK_DMAC>;
> + clock-names = "apb_pclk";
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + };
> +
> + i2s0: i2s0 at 11440000 {
> + compatible = "samsung,exynos7-i2s";
> + reg = <0x11440000 0x100>;
> + dmas = <&adma 0 &adma 2>;
> + dma-names = "tx", "rx";
> + interrupts = <GIC_SPI 70 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
> + <&cmu_aud CLK_SCLK_AUD_I2S>,
> + <&cmu_aud CLK_SCLK_I2S_BCLK>;
> + clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s0_bus>;
> + status = "disabled";
> + };
> +
> + serial_3: serial at 11460000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x11460000 0x100>;
> + interrupts = <GIC_SPI 67 0>;
> + clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
> + <&cmu_aud CLK_SCLK_AUD_UART>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart_aud_bus>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +};
> +
> +#include "exynos5433-pinctrl.dtsi"
> +#include "exynos5433-tmu.dtsi"
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH 0/6] Add basic support for support for Rockchip RK1108 SOC
From: Andy Yan @ 2016-11-03 12:26 UTC (permalink / raw)
To: linux-arm-kernel
RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core.
It is designed for varies application scenario such as car DVR, sports
DV, secure camera and UAV camera.
This patch series add basic support for it, which can boot a board with
initramfs into shell.
More new feathers will come soon.
Andy Yan (4):
pinctrl: rockchip: add support for rk1108
ARM: dts: add basic support for Rockchip RK1108 SOC
ARM: add low level debug uart for rk1108
ARM: dts: rockchip: add rockchip RK1108 Evaluation board
Shawn Lin (2):
dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description
clk: rockchip: add clock controller for rk1108
Documentation/devicetree/bindings/arm/rockchip.txt | 3 +
.../devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
arch/arm/Kconfig.debug | 30 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk1108-evb.dts | 69 +++
arch/arm/boot/dts/rk1108.dtsi | 420 +++++++++++++++++++
arch/arm/mach-rockchip/rockchip.c | 1 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk1108.c | 463 +++++++++++++++++++++
drivers/clk/rockchip/clk.h | 14 +
drivers/pinctrl/pinctrl-rockchip.c | 27 +-
include/dt-bindings/clock/rk1108-cru.h | 308 ++++++++++++++
12 files changed, 1337 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/rk1108-evb.dts
create mode 100644 arch/arm/boot/dts/rk1108.dtsi
create mode 100644 drivers/clk/rockchip/clk-rk1108.c
create mode 100644 include/dt-bindings/clock/rk1108-cru.h
--
2.7.4
^ permalink raw reply
* [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Mirza Krak @ 2016-11-03 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <df12a1f0-316d-64a4-54fe-f7559742eeca@nvidia.com>
2016-11-03 11:06 GMT+01:00 Jon Hunter <jonathanh@nvidia.com>:
> Hi Mirza,
>
> On 27/10/16 15:01, Mirza Krak wrote:
>>
>> From: Mirza Krak <mirza.krak@gmail.com>
>>
>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
>> is max rate.
>>
>> The maximum rate value of 92 MHz is pulled from the downstream L4T
>> kernel.
>
>
> Thanks for adding this. I assume that this is from an L4T r16 release with a
> v3.1 kernel. I had a quick poke through the kernel sources for v3.1 but was
> unable to see where this is set. Obviously v3.1 did not have CCF and so
> everything seems to be in the arch/arm/mach-tegra directory for setting up
> clocks. Can you point me to the appropriate sources so I can ACK this?
I use the kernel sources provided by Toradex, and these sources are
based on L4T r16 release.
http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
Best Regards
Mirza Krak
^ permalink raw reply
* [PATCH v3 4/5] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board
From: Andi Shyti @ 2016-11-03 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478155149-28527-5-git-send-email-cw00.choi@samsung.com>
Hi Chanwoo,
Tested-by: Andi Shyti <andi.shyti@samsung.com>
Andi
On Thu, Nov 03, 2016 at 03:39:08PM +0900, Chanwoo Choi wrote:
> This patch adds the Device Tree source for Exynos5433-based Samsung TM2 board.
> This board fully support the all things for mobile target.
>
> This patch supports the following devices:
> 1. basic SoC
> - Initial booting for Samsung Exynos5433 SoC
> - DRAM LPDDR3 (3GB)
> - eMMC (32GB)
> - ARM architecture timer
>
> 2. power management devices
> - Sasmung S2MPS13 PMIC for the power supply
> - CPUFREQ for big.LITTLE cores
> - TMU for big.LITTLE cores and GPU
> - ADC with thermistor to measure the temperature of AP/Battery/Charger
> - Maxim MAX77843 Interface PMIC (MUIC/Haptic/Regulator)
>
> 3. sound devices
> - I2S for sound bus
> - LPASS for sound power control
> - Wolfson WM5110 for sound codec
> - Maxim MAX98504 for speaker amplifier
> - TM2 ASoC Machine device driver node
>
> 3. display devices
> - DECON, DSI and MIC for the panel output
>
> 4. usb devices
> - USB 3.0 DRD (Dual Role Device)
> - USB 3.0 Host controller
>
> 5. storage devices
> - MSHC (Mobile Storage Host Controller) for eMMC device
>
> 6. misc devices
> - gpio-keys (power, volume up/down, home key)
> - PWM (Pulse Width Modulation Timer)
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Inki Dae <inki.dae@samsung.com>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> Signed-off-by: Inha Song <ideal.song@samsung.com>
> Signed-off-by: Ingi kim <ingi2.kim@samsung.com>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
> .../bindings/arm/samsung/samsung-boards.txt | 1 +
> arch/arm64/boot/dts/exynos/Makefile | 4 +-
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 974 +++++++++++++++++++++
> 3 files changed, 978 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> index 0ea7f14ef294..339af8b9cdc5 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> @@ -15,6 +15,7 @@ Required root node properties:
> - "samsung,xyref5260" - for Exynos5260-based Samsung board.
> - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
> - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
> + - "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
> - "samsung,sd5v1" - for Exynos5440-based Samsung board.
> - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
>
> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> index 50c9b9383cfa..947c750acba1 100644
> --- a/arch/arm64/boot/dts/exynos/Makefile
> +++ b/arch/arm64/boot/dts/exynos/Makefile
> @@ -1,4 +1,6 @@
> -dtb-$(CONFIG_ARCH_EXYNOS) += exynos7-espresso.dtb
> +dtb-$(CONFIG_ARCH_EXYNOS) += \
> + exynos5433-tm2.dtb \
> + exynos7-espresso.dtb
>
> always := $(dtb-y)
> subdir-y := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> new file mode 100644
> index 000000000000..9ea3f32bae9e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -0,0 +1,974 @@
> +/*
> + * SAMSUNG Exynos5433 TM2 board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Device tree source file for Samsung's TM2 board which is based on
> + * Samsung Exynos5433 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +#include "exynos5433.dtsi"
> +#include <dt-bindings/clock/samsung,s2mps11.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + model = "Samsung TM2 board";
> + compatible = "samsung,tm2", "samsung,exynos5433";
> +
> + aliases {
> + pinctrl0 = &pinctrl_alive;
> + pinctrl1 = &pinctrl_aud;
> + pinctrl2 = &pinctrl_cpif;
> + pinctrl3 = &pinctrl_ese;
> + pinctrl4 = &pinctrl_finger;
> + pinctrl5 = &pinctrl_fsys;
> + pinctrl6 = &pinctrl_imem;
> + pinctrl7 = &pinctrl_nfc;
> + pinctrl8 = &pinctrl_peric;
> + pinctrl9 = &pinctrl_touch;
> + serial0 = &serial_0;
> + serial1 = &serial_1;
> + serial2 = &serial_2;
> + serial3 = &serial_3;
> + spi0 = &spi_0;
> + spi1 = &spi_1;
> + spi2 = &spi_2;
> + spi3 = &spi_3;
> + spi4 = &spi_4;
> + };
> +
> + chosen {
> + stdout-path = &serial_1;
> + };
> +
> + memory at 20000000 {
> + device_type = "memory";
> + reg = <0x0 0x20000000 0x0 0xc0000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + power-key {
> + gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + label = "power key";
> + debounce-interval = <10>;
> + };
> +
> + volume-up-key {
> + gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEUP>;
> + label = "volume-up key";
> + debounce-interval = <10>;
> + };
> +
> + volume-down-key {
> + gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEDOWN>;
> + label = "volume-down key";
> + debounce-interval = <10>;
> + };
> +
> + homepage-key {
> + gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_MENU>;
> + label = "homepage key";
> + debounce-interval = <10>;
> + };
> + };
> +
> + i2c_max98504: i2c-gpio-0 {
> + compatible = "i2c-gpio";
> + gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
> + &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
> + i2c-gpio,delay-us = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + max98504: max98504 at 31 {
> + compatible = "maxim,max98504";
> + reg = <0x31>;
> + maxim,rx-path = <1>;
> + maxim,tx-path = <1>;
> + maxim,tx-channel-mask = <3>;
> + maxim,tx-channel-source = <2>;
> + };
> + };
> +
> + sound {
> + compatible = "samsung,tm2-audio";
> + audio-codec = <&wm5110>;
> + i2s-controller = <&i2s0>;
> + audio-amplifier = <&max98504>;
> + mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
> + model = "wm5110";
> + samsung,audio-routing =
> + /* Headphone */
> + "HP", "HPOUT1L",
> + "HP", "HPOUT1R",
> +
> + /* Speaker */
> + "SPK", "SPKOUT",
> + "SPKOUT", "HPOUT2L",
> + "SPKOUT", "HPOUT2R",
> +
> + /* Receiver */
> + "RCV", "HPOUT3L",
> + "RCV", "HPOUT3R";
> + status = "okay";
> + };
> +};
> +
> +&adc {
> + vdd-supply = <&ldo3_reg>;
> + status = "okay";
> +
> + thermistor-ap {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 0>;
> + };
> +
> + thermistor-battery {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 1>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + thermistor-charger {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 2>;
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&buck3_reg>;
> +};
> +
> +&cpu4 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&decon {
> + status = "okay";
> +
> + i80-if-timings {
> + };
> +};
> +
> +&dsi {
> + status = "okay";
> + vddcore-supply = <&ldo6_reg>;
> + vddio-supply = <&ldo7_reg>;
> + samsung,pll-clock-frequency = <24000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&te_irq>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + reg = <1>;
> +
> + dsi_out: endpoint {
> + samsung,burst-clock-frequency = <512000000>;
> + samsung,esc-clock-frequency = <16000000>;
> + };
> + };
> + };
> +};
> +
> +&hsi2c_0 {
> + status = "okay";
> + clock-frequency = <2500000>;
> +
> + s2mps13-pmic at 66 {
> + compatible = "samsung,s2mps13-pmic";
> + interrupt-parent = <&gpa0>;
> + interrupts = <7 IRQ_TYPE_NONE>;
> + reg = <0x66>;
> + samsung,s2mps11-wrstbi-ground;
> +
> + s2mps13_osc: clocks {
> + compatible = "samsung,s2mps13-clk";
> + #clock-cells = <1>;
> + clock-output-names = "s2mps13_ap", "s2mps13_cp",
> + "s2mps13_bt";
> + };
> +
> + regulators {
> + ldo1_reg: LDO1 {
> + regulator-name = "VDD_ALIVE_0.9V_AP";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-always-on;
> + };
> +
> + ldo2_reg: LDO2 {
> + regulator-name = "VDDQ_MMC2_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo3_reg: LDO3 {
> + regulator-name = "VDD1_E_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo4_reg: LDO4 {
> + regulator-name = "VDD10_MIF_PLL_1.0V_AP";
> + regulator-min-microvolt = <1300000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo5_reg: LDO5 {
> + regulator-name = "VDD10_DPLL_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo6_reg: LDO6 {
> + regulator-name = "VDD10_MIPI2L_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo7_reg: LDO7 {
> + regulator-name = "VDD18_MIPI2L_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo8_reg: LDO8 {
> + regulator-name = "VDD18_LLI_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo9_reg: LDO9 {
> + regulator-name = "VDD18_ABB_ETC_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo10_reg: LDO10 {
> + regulator-name = "VDD33_USB30_3.0V_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo11_reg: LDO11 {
> + regulator-name = "VDD_INT_M_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo12_reg: LDO12 {
> + regulator-name = "VDD_KFC_M_1.1V_AP";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + };
> +
> + ldo13_reg: LDO13 {
> + regulator-name = "VDD_G3D_M_0.95V_AP";
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <950000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo14_reg: LDO14 {
> + regulator-name = "VDDQ_M1_LDO_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo15_reg: LDO15 {
> + regulator-name = "VDDQ_M2_LDO_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo16_reg: LDO16 {
> + regulator-name = "VDDQ_EFUSE";
> + regulator-min-microvolt = <1400000>;
> + regulator-max-microvolt = <3400000>;
> + regulator-always-on;
> + };
> +
> + ldo17_reg: LDO17 {
> + regulator-name = "V_TFLASH_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo18_reg: LDO18 {
> + regulator-name = "V_CODEC_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo19_reg: LDO19 {
> + regulator-name = "VDDA_1.8V_COMP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo20_reg: LDO20 {
> + regulator-name = "VCC_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> +
> + ldo21_reg: LDO21 {
> + regulator-name = "VT_CAM_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo22_reg: LDO22 {
> + regulator-name = "CAM_IO_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo23_reg: LDO23 {
> + regulator-name = "CAM_SEN_CORE_1.2V_AP";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo24_reg: LDO24 {
> + regulator-name = "VT_CAM_1.2V";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo25_reg: LDO25 {
> + regulator-name = "CAM_SEN_A2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo26_reg: LDO26 {
> + regulator-name = "CAM_AF_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo27_reg: LDO27 {
> + regulator-name = "VCC_3.0V_LCD_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo28_reg: LDO28 {
> + regulator-name = "VCC_1.8V_LCD_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo29_reg: LDO29 {
> + regulator-name = "VT_CAM_2.8V";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo30_reg: LDO30 {
> + regulator-name = "TSP_AVDD_3.3V_AP";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + ldo31_reg: LDO31 {
> + regulator-name = "TSP_VDD_1.85V_AP";
> + regulator-min-microvolt = <1850000>;
> + regulator-max-microvolt = <1850000>;
> + };
> +
> + ldo32_reg: LDO32 {
> + regulator-name = "VTOUCH_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo33_reg: LDO33 {
> + regulator-name = "VTOUCH_LED_3.3V";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-ramp-delay = <12500>;
> + };
> +
> + ldo34_reg: LDO34 {
> + regulator-name = "VCC_1.8V_MHL_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <2100000>;
> + };
> +
> + ldo35_reg: LDO35 {
> + regulator-name = "OIS_VM_2.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo36_reg: LDO36 {
> + regulator-name = "VSIL_1.0V";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + };
> +
> + ldo37_reg: LDO37 {
> + regulator-name = "VF_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo38_reg: LDO38 {
> + regulator-name = "VCC_3.0V_MOTOR_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo39_reg: LDO39 {
> + regulator-name = "V_HRM_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo40_reg: LDO40 {
> + regulator-name = "V_HRM_3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + buck1_reg: BUCK1 {
> + regulator-name = "VDD_MIF_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck2_reg: BUCK2 {
> + regulator-name = "VDD_EGL_1.0V_AP";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck3_reg: BUCK3 {
> + regulator-name = "VDD_KFC_1.0V_AP";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck4_reg: BUCK4 {
> + regulator-name = "VDD_INT_0.95V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck5_reg: BUCK5 {
> + regulator-name = "VDD_DISP_CAM0_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck6_reg: BUCK6 {
> + regulator-name = "VDD_G3D_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck7_reg: BUCK7 {
> + regulator-name = "VDD_MEM1_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + buck8_reg: BUCK8 {
> + regulator-name = "VDD_LLDO_1.35V_AP";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + buck9_reg: BUCK9 {
> + regulator-name = "VDD_MLDO_2.0V_AP";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + buck10_reg: BUCK10 {
> + regulator-name = "vdd_mem2";
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&hsi2c_8 {
> + status = "okay";
> +
> + max77843 at 66 {
> + compatible = "maxim,max77843";
> + interrupt-parent = <&gpa1>;
> + interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> + reg = <0x66>;
> +
> + muic: max77843-muic {
> + compatible = "maxim,max77843-muic";
> + };
> +
> + regulators {
> + compatible = "maxim,max77843-regulator";
> + safeout1_reg: SAFEOUT1 {
> + regulator-name = "SAFEOUT1";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <4950000>;
> + };
> +
> + safeout2_reg: SAFEOUT2 {
> + regulator-name = "SAFEOUT2";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <4950000>;
> + };
> +
> + charger_reg: CHARGER {
> + regulator-name = "CHARGER";
> + regulator-min-microamp = <100000>;
> + regulator-max-microamp = <3150000>;
> + };
> + };
> +
> + haptic: max77843-haptic {
> + compatible = "maxim,max77843-haptic";
> + haptic-supply = <&ldo38_reg>;
> + pwms = <&pwm 0 33670 0>;
> + pwm-names = "haptic";
> + };
> + };
> +};
> +
> +&i2s0 {
> + status = "okay";
> +};
> +
> +&mshc_0 {
> + status = "okay";
> + num-slots = <1>;
> + non-removable;
> + card-detect-delay = <200>;
> + samsung,dw-mshc-ciu-div = <3>;
> + samsung,dw-mshc-sdr-timing = <0 4>;
> + samsung,dw-mshc-ddr-timing = <0 2>;
> + samsung,dw-mshc-hs400-timing = <0 3>;
> + samsung,read-strobe-delay = <90>;
> + fifo-depth = <0x80>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
> + &sd0_bus8 &sd0_rdqs>;
> + bus-width = <8>;
> + assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
> + assigned-clock-rates = <800000000>;
> +};
> +
> +&pinctrl_alive {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_alive>;
> +
> + initial_alive: initial-state {
> + PIN(IN, gpa0-0, DOWN, LV1);
> + PIN(IN, gpa0-1, NONE, LV1);
> + PIN(IN, gpa0-2, DOWN, LV1);
> + PIN(IN, gpa0-3, NONE, LV1);
> + PIN(IN, gpa0-4, NONE, LV1);
> + PIN(IN, gpa0-5, DOWN, LV1);
> + PIN(IN, gpa0-6, NONE, LV1);
> + PIN(IN, gpa0-7, NONE, LV1);
> +
> + PIN(IN, gpa1-0, UP, LV1);
> + PIN(IN, gpa1-1, NONE, LV1);
> + PIN(IN, gpa1-2, NONE, LV1);
> + PIN(IN, gpa1-3, DOWN, LV1);
> + PIN(IN, gpa1-4, DOWN, LV1);
> + PIN(IN, gpa1-5, NONE, LV1);
> + PIN(IN, gpa1-6, NONE, LV1);
> + PIN(IN, gpa1-7, NONE, LV1);
> +
> + PIN(IN, gpa2-0, NONE, LV1);
> + PIN(IN, gpa2-1, NONE, LV1);
> + PIN(IN, gpa2-2, NONE, LV1);
> + PIN(IN, gpa2-3, DOWN, LV1);
> + PIN(IN, gpa2-4, NONE, LV1);
> + PIN(IN, gpa2-5, DOWN, LV1);
> + PIN(IN, gpa2-6, DOWN, LV1);
> + PIN(IN, gpa2-7, NONE, LV1);
> +
> + PIN(IN, gpa3-0, DOWN, LV1);
> + PIN(IN, gpa3-1, DOWN, LV1);
> + PIN(IN, gpa3-2, NONE, LV1);
> + PIN(IN, gpa3-3, DOWN, LV1);
> + PIN(IN, gpa3-4, NONE, LV1);
> + PIN(IN, gpa3-5, DOWN, LV1);
> + PIN(IN, gpa3-6, DOWN, LV1);
> + PIN(IN, gpa3-7, DOWN, LV1);
> +
> + PIN(IN, gpf1-0, NONE, LV1);
> + PIN(IN, gpf1-1, NONE, LV1);
> + PIN(IN, gpf1-2, DOWN, LV1);
> + PIN(IN, gpf1-4, UP, LV1);
> + PIN(OUT, gpf1-5, NONE, LV1);
> + PIN(IN, gpf1-6, DOWN, LV1);
> + PIN(IN, gpf1-7, DOWN, LV1);
> +
> + PIN(IN, gpf2-0, DOWN, LV1);
> + PIN(IN, gpf2-1, DOWN, LV1);
> + PIN(IN, gpf2-2, DOWN, LV1);
> + PIN(IN, gpf2-3, DOWN, LV1);
> +
> + PIN(IN, gpf3-0, DOWN, LV1);
> + PIN(IN, gpf3-1, DOWN, LV1);
> + PIN(IN, gpf3-2, NONE, LV1);
> + PIN(IN, gpf3-3, DOWN, LV1);
> +
> + PIN(IN, gpf4-0, DOWN, LV1);
> + PIN(IN, gpf4-1, DOWN, LV1);
> + PIN(IN, gpf4-2, DOWN, LV1);
> + PIN(IN, gpf4-3, DOWN, LV1);
> + PIN(IN, gpf4-4, DOWN, LV1);
> + PIN(IN, gpf4-5, DOWN, LV1);
> + PIN(IN, gpf4-6, DOWN, LV1);
> + PIN(IN, gpf4-7, DOWN, LV1);
> +
> + PIN(IN, gpf5-0, DOWN, LV1);
> + PIN(IN, gpf5-1, DOWN, LV1);
> + PIN(IN, gpf5-2, DOWN, LV1);
> + PIN(IN, gpf5-3, DOWN, LV1);
> + PIN(OUT, gpf5-4, NONE, LV1);
> + PIN(IN, gpf5-5, DOWN, LV1);
> + PIN(IN, gpf5-6, DOWN, LV1);
> + PIN(IN, gpf5-7, DOWN, LV1);
> + };
> +
> + te_irq: te_irq {
> + samsung,pins = "gpf1-3";
> + samsung,pin-function = <0xf>;
> + };
> +};
> +
> +&pinctrl_cpif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_cpif>;
> +
> + initial_cpif: initial-state {
> + PIN(IN, gpv6-0, DOWN, LV1);
> + PIN(IN, gpv6-1, DOWN, LV1);
> + };
> +};
> +
> +&pinctrl_ese {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_ese>;
> +
> + initial_ese: initial-state {
> + PIN(IN, gpj2-0, DOWN, LV1);
> + PIN(IN, gpj2-1, DOWN, LV1);
> + PIN(IN, gpj2-2, DOWN, LV1);
> + };
> +};
> +
> +&pinctrl_fsys {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_fsys>;
> +
> + initial_fsys: initial-state {
> + PIN(IN, gpr3-0, NONE, LV1);
> + PIN(IN, gpr3-1, DOWN, LV1);
> + PIN(IN, gpr3-2, DOWN, LV1);
> + PIN(IN, gpr3-3, DOWN, LV1);
> + PIN(IN, gpr3-7, NONE, LV1);
> + };
> +};
> +
> +&pinctrl_imem {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_imem>;
> +
> + initial_imem: initial-state {
> + PIN(IN, gpf0-0, UP, LV1);
> + PIN(IN, gpf0-1, UP, LV1);
> + PIN(IN, gpf0-2, DOWN, LV1);
> + PIN(IN, gpf0-3, UP, LV1);
> + PIN(IN, gpf0-4, DOWN, LV1);
> + PIN(IN, gpf0-5, NONE, LV1);
> + PIN(IN, gpf0-6, DOWN, LV1);
> + PIN(IN, gpf0-7, UP, LV1);
> + };
> +};
> +
> +&pinctrl_nfc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_nfc>;
> +
> + initial_nfc: initial-state {
> + PIN(IN, gpj0-2, DOWN, LV1);
> + };
> +};
> +
> +&pinctrl_peric {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_peric>;
> +
> + initial_peric: initial-state {
> + PIN(IN, gpv7-0, DOWN, LV1);
> + PIN(IN, gpv7-1, DOWN, LV1);
> + PIN(IN, gpv7-2, NONE, LV1);
> + PIN(IN, gpv7-3, DOWN, LV1);
> + PIN(IN, gpv7-4, DOWN, LV1);
> + PIN(IN, gpv7-5, DOWN, LV1);
> +
> + PIN(IN, gpb0-4, DOWN, LV1);
> +
> + PIN(IN, gpc0-2, DOWN, LV1);
> + PIN(IN, gpc0-5, DOWN, LV1);
> + PIN(IN, gpc0-7, DOWN, LV1);
> +
> + PIN(IN, gpc1-1, DOWN, LV1);
> +
> + PIN(IN, gpc3-4, NONE, LV1);
> + PIN(IN, gpc3-5, NONE, LV1);
> + PIN(IN, gpc3-6, NONE, LV1);
> + PIN(IN, gpc3-7, NONE, LV1);
> +
> + PIN(OUT, gpg0-0, NONE, LV1);
> + PIN(FUNC1, gpg0-1, DOWN, LV1);
> +
> + PIN(IN, gpd2-5, DOWN, LV1);
> +
> + PIN(IN, gpd4-0, NONE, LV1);
> + PIN(IN, gpd4-1, DOWN, LV1);
> + PIN(IN, gpd4-2, DOWN, LV1);
> + PIN(IN, gpd4-3, DOWN, LV1);
> + PIN(IN, gpd4-4, DOWN, LV1);
> +
> + PIN(IN, gpd6-3, DOWN, LV1);
> +
> + PIN(IN, gpd8-1, UP, LV1);
> +
> + PIN(IN, gpg1-0, DOWN, LV1);
> + PIN(IN, gpg1-1, DOWN, LV1);
> + PIN(IN, gpg1-2, DOWN, LV1);
> + PIN(IN, gpg1-3, DOWN, LV1);
> + PIN(IN, gpg1-4, DOWN, LV1);
> +
> + PIN(IN, gpg2-0, DOWN, LV1);
> + PIN(IN, gpg2-1, DOWN, LV1);
> +
> + PIN(IN, gpg3-0, DOWN, LV1);
> + PIN(IN, gpg3-1, DOWN, LV1);
> + PIN(IN, gpg3-5, DOWN, LV1);
> + PIN(IN, gpg3-7, DOWN, LV1);
> + };
> +};
> +
> +&pinctrl_touch {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_touch>;
> +
> + initial_touch: initial-state {
> + PIN(IN, gpj1-2, DOWN, LV1);
> + };
> +};
> +
> +&pwm {
> + pinctrl-0 = <&pwm0_out>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mic {
> + status = "okay";
> +
> + i80-if-timings {
> + };
> +};
> +
> +&serial_1 {
> + status = "okay";
> +};
> +
> +&serial_3 {
> + assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
> + assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> + status = "okay";
> +};
> +
> +&spi_1 {
> + cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + wm5110: wm5110-codec at 0 {
> + compatible = "wlf,wm5110";
> + reg = <0x0>;
> + spi-max-frequency = <20000000>;
> + interrupt-parent = <&gpa0>;
> + interrupts = <4 IRQ_TYPE_NONE>;
> + clocks = <&pmu_system_controller 0>,
> + <&s2mps13_osc S2MPS11_CLK_BT>;
> + clock-names = "mclk1", "mclk2";
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + wlf,micd-detect-debounce = <300>;
> + wlf,micd-bias-start-time = <0x1>;
> + wlf,micd-rate = <0x7>;
> + wlf,micd-dbtime = <0x1>;
> + wlf,micd-force-micbias;
> + wlf,micd-configs = <0x0 1 0>;
> + wlf,hpdet-channel = <1>;
> + wlf,gpsw = <0x1>;
> + wlf,inmode = <2 0 2 0>;
> +
> + wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
> + wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
> +
> + /* core supplies */
> + AVDD-supply = <&ldo18_reg>;
> + DBVDD1-supply = <&ldo18_reg>;
> + CPVDD-supply = <&ldo18_reg>;
> + DBVDD2-supply = <&ldo18_reg>;
> + DBVDD3-supply = <&ldo18_reg>;
> +
> + controller-data {
> + samsung,spi-feedback-delay = <0>;
> + };
> + };
> +};
> +
> +&timer {
> + clock-frequency = <24000000>;
> +};
> +
> +&tmu_atlas0 {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&tmu_apollo {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&tmu_g3d {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&usbdrd30 {
> + vdd33-supply = <&ldo10_reg>;
> + vdd10-supply = <&ldo6_reg>;
> + status = "okay";
> +};
> +
> +&usbdrd_dwc3_0 {
> + dr_mode = "otg";
> +};
> +
> +&usbdrd30_phy {
> + vbus-supply = <&safeout1_reg>;
> + status = "okay";
> +};
> +
> +&xxti {
> + clock-frequency = <24000000>;
> +};
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v3 5/5] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board
From: Andi Shyti @ 2016-11-03 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478155149-28527-6-git-send-email-cw00.choi@samsung.com>
Hi Chanwoo,
Tested-by: Andi Shyti <andi.shyti@samsung.com>
Andi
On Thu, Nov 03, 2016 at 03:39:09PM +0900, Chanwoo Choi wrote:
> This patch adds the Device Tree source for Exynos5433-based Samsung TM2E
> board. TM2E board is the most similar with TM2 board. The exynos5433-tm2e.dts
> include the difference between TM2 and TM2E.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Inki Dae <inki.dae@samsung.com>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> Signed-off-by: Inha Song <ideal.song@samsung.com>
> Signed-off-by: Ingi kim <ingi2.kim@samsung.com>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
> .../bindings/arm/samsung/samsung-boards.txt | 1 +
> arch/arm64/boot/dts/exynos/Makefile | 1 +
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 41 ++++++++++++++++++++++
> 3 files changed, 43 insertions(+)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> index 339af8b9cdc5..c64c7b515777 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> @@ -16,6 +16,7 @@ Required root node properties:
> - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
> - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
> - "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
> + - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
> - "samsung,sd5v1" - for Exynos5440-based Samsung board.
> - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
>
> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> index 947c750acba1..7ddea53769a7 100644
> --- a/arch/arm64/boot/dts/exynos/Makefile
> +++ b/arch/arm64/boot/dts/exynos/Makefile
> @@ -1,5 +1,6 @@
> dtb-$(CONFIG_ARCH_EXYNOS) += \
> exynos5433-tm2.dtb \
> + exynos5433-tm2e.dtb \
> exynos7-espresso.dtb
>
> always := $(dtb-y)
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> new file mode 100644
> index 000000000000..1db4e7f363a9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> @@ -0,0 +1,41 @@
> +/*
> + * SAMSUNG Exynos5433 TM2E board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
> + * Samsung Exynos5433 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "exynos5433-tm2.dts"
> +
> +/ {
> + model = "Samsung TM2E board";
> + compatible = "samsung,tm2e", "samsung,exynos5433";
> +};
> +
> +&ldo23_reg {
> + regulator-name = "CAM_SEN_CORE_1.025V_AP";
> + regulator-max-microvolt = <1050000>;
> +};
> +
> +&ldo25_reg {
> + regulator-name = "UNUSED_LDO25";
> + regulator-always-off;
> +};
> +
> +&ldo31_reg {
> + regulator-name = "TSP_VDD_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +};
> +
> +&ldo38_reg {
> + regulator-name = "VCC_3.3V_MOTOR_AP";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Mirza Krak @ 2016-11-03 12:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALw8SCWyLAw=yZ-W_nAFuDAazpa4HJfZuzqLDKQKYLWjV5JzYw@mail.gmail.com>
2016-11-03 13:26 GMT+01:00 Mirza Krak <mirza.krak@gmail.com>:
> 2016-11-03 11:06 GMT+01:00 Jon Hunter <jonathanh@nvidia.com>:
>> Hi Mirza,
>>
>> On 27/10/16 15:01, Mirza Krak wrote:
>>>
>>> From: Mirza Krak <mirza.krak@gmail.com>
>>>
>>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
>>> is max rate.
>>>
>>> The maximum rate value of 92 MHz is pulled from the downstream L4T
>>> kernel.
>>
>>
>> Thanks for adding this. I assume that this is from an L4T r16 release with a
>> v3.1 kernel. I had a quick poke through the kernel sources for v3.1 but was
>> unable to see where this is set. Obviously v3.1 did not have CCF and so
>> everything seems to be in the arch/arm/mach-tegra directory for setting up
>> clocks. Can you point me to the appropriate sources so I can ACK this?
>
> I use the kernel sources provided by Toradex, and these sources are
> based on L4T r16 release.
>
> http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
Ops, pre-mature send.
I also added Marcel from Toradex on CC.
The link to the source are [1] for Tegra2 and [2] for Tegra3.
[1]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
[2]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra3_clocks.c?h=tegra#n4353
Best Regards
Mirza
^ permalink raw reply
* [PATCH 1/6] dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description
From: Andy Yan @ 2016-11-03 12:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com>
From: Shawn Lin <shawn.lin@rock-chips.com>
Add "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on rk1108 platform.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
index 07184e8..ea9c1c9 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
@@ -13,6 +13,7 @@ Required Properties:
- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
before RK3288
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
+ - "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
--
2.7.4
^ permalink raw reply related
* [PATCH 2/6] pinctrl: rockchip: add support for rk1108
From: Andy Yan @ 2016-11-03 12:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com>
Add basic support for rk1108 soc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 49bf7dc..9f324b1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -59,6 +59,7 @@
#define GPIO_LS_SYNC 0x60
enum rockchip_pinctrl_type {
+ RK1108,
RK2928,
RK3066B,
RK3188,
@@ -1123,6 +1124,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
return !(data & BIT(bit))
? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
: PIN_CONFIG_BIAS_DISABLE;
+ case RK1108:
case RK3188:
case RK3288:
case RK3368:
@@ -1169,6 +1171,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
spin_unlock_irqrestore(&bank->slock, flags);
break;
+ case RK1108:
case RK3188:
case RK3288:
case RK3368:
@@ -1358,6 +1361,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
pull == PIN_CONFIG_BIAS_DISABLE);
case RK3066B:
return pull ? false : true;
+ case RK1108:
case RK3188:
case RK3288:
case RK3368:
@@ -1385,7 +1389,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
-
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
rc = rockchip_set_pull(bank, pin - bank->pin_base,
@@ -2455,6 +2458,26 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
return 0;
}
+static struct rockchip_pin_bank rk1108_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU),
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
+};
+
+static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
+ .pin_banks = rk1108_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
+ .label = "RK1108-GPIO",
+ .type = RK1108,
+ .grf_mux_offset = 0x10,
+ .pmu_mux_offset = 0x0,
+ .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk2928_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@@ -2684,6 +2707,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
};
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
+ { .compatible = "rockchip,rk1108-pinctrl",
+ .data = (void *)&rk1108_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",
.data = (void *)&rk2928_pin_ctrl },
{ .compatible = "rockchip,rk3036-pinctrl",
--
2.7.4
^ permalink raw reply related
* [PATCH 3/6] clk: rockchip: add clock controller for rk1108
From: Andy Yan @ 2016-11-03 12:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com>
From: Shawn Lin <shawn.lin@rock-chips.com>
Add the clock tree definition and driver for rk1108 SoC.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk1108.c | 463 +++++++++++++++++++++++++++++++++
drivers/clk/rockchip/clk.h | 14 +
include/dt-bindings/clock/rk1108-cru.h | 308 ++++++++++++++++++++++
4 files changed, 786 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rk1108.c
create mode 100644 include/dt-bindings/clock/rk1108-cru.h
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b5f2c8e..16e098c 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -11,6 +11,7 @@ obj-y += clk-mmc-phase.o
obj-y += clk-ddr.o
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
+obj-y += clk-rk1108.o
obj-y += clk-rk3036.o
obj-y += clk-rk3188.o
obj-y += clk-rk3228.o
diff --git a/drivers/clk/rockchip/clk-rk1108.c b/drivers/clk/rockchip/clk-rk1108.c
new file mode 100644
index 0000000..eafc623
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk1108.c
@@ -0,0 +1,463 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Shawn Lin <shawn.lin@rock-chips.com>
+ * Andy Yan <andy.yan@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+#include <dt-bindings/clock/rk1108-cru.h>
+#include "clk.h"
+
+#define RK1108_GRF_SOC_STATUS0 0x480
+
+enum rk1108_plls {
+ apll, dpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rk1108_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
+ RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
+ RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
+ RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
+ { /* sentinel */ },
+};
+
+
+#define RK1108_DIV_CORE_MASK 0xf
+#define RK1108_DIV_CORE_SHIFT 4
+
+#define RK1108_CLKSEL0(_core_peri_div) \
+ { \
+ .reg = RK1108_CLKSEL_CON(1), \
+ .val = HIWORD_UPDATE(_core_peri_div, RK1108_DIV_CORE_MASK, \
+ RK1108_DIV_CORE_SHIFT) \
+ }
+
+#define RK1108_CPUCLK_RATE(_prate, _core_peri_div) \
+ { \
+ .prate = _prate, \
+ .divs = { \
+ RK1108_CLKSEL0(_core_peri_div), \
+ }, \
+ }
+
+static struct rockchip_cpuclk_rate_table rk1108_cpuclk_rates[] __initdata = {
+ RK1108_CPUCLK_RATE(816000000, 4),
+ RK1108_CPUCLK_RATE(600000000, 4),
+ RK1108_CPUCLK_RATE(312000000, 4),
+};
+
+static const struct rockchip_cpuclk_reg_data rk1108_cpuclk_data = {
+ .core_reg = RK1108_CLKSEL_CON(0),
+ .div_core_shift = 0,
+ .div_core_mask = 0x1f,
+ .mux_core_alt = 1,
+ .mux_core_main = 0,
+ .mux_core_shift = 8,
+ .mux_core_mask = 0x1,
+};
+
+PNAME(mux_pll_p) = { "xin24m", "xin24m"};
+
+PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
+PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
+PNAME(mux_pmu_1f) = { "xin24m", "pmu_24m"};
+PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
+PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
+PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "pclk_top_pre", "xin24m" };
+
+PNAME(mux_pll_src_4plls_p) = { "dpll", "hdmiphy", "gpll", "usb480m" };
+PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" };
+PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
+
+PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_dpll", "aclk_peri_src_gpll" };
+PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" };
+
+PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
+PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" };
+
+
+PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
+PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
+PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
+
+
+static struct rockchip_pll_clock rk1108_pll_clks[] __initdata = {
+ [apll] = PLL(pll_rk3399, RK1108_APLL_ID, "apll", mux_pll_p, 0, RK1108_PLL_CON(0),
+ RK1108_PLL_CON(3), 8, 31, 0, rk1108_pll_rates),
+ [dpll] = PLL(pll_rk3399, RK1108_DPLL_ID, "dpll", mux_pll_p, 0, RK1108_PLL_CON(8),
+ RK1108_PLL_CON(11), 8, 31, 0, NULL),
+ [gpll] = PLL(pll_rk3399, RK1108_GPLL_ID, "gpll", mux_pll_p, 0, RK1108_PLL_CON(16),
+ RK1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk1108_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+
+static struct rockchip_clk_branch rk1108_uart0_fracmux __initdata =
+ MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
+ RK1108_CLKSEL_CON(13), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk1108_uart1_fracmux __initdata =
+ MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
+ RK1108_CLKSEL_CON(14), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk1108_uart2_fracmux __initdata =
+ MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
+ RK1108_CLKSEL_CON(15), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk1108_clk_branches[] __initdata = {
+ /*
+ * Clock-Architecture Diagram 2
+ */
+
+ /* PD_CORE */
+ GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(0), 1, GFLAGS),
+ GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(0), 0, GFLAGS),
+ GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(0), 2, GFLAGS),
+ COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK1108_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK1108_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(11), 0, GFLAGS),
+ GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(11), 1, GFLAGS),
+
+ /* PD_RKVENC */
+
+ /* PD_RKVDEC */
+
+ /* PD_PMU_wrapper */
+ COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(38), 0, 5, DFLAGS,
+ RK1108_CLKGATE_CON(8), 12, GFLAGS),
+ GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(10), 0, GFLAGS),
+ GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(10), 1, GFLAGS),
+ GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(10), 2, GFLAGS),
+ GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(10), 3, GFLAGS),
+ GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(10), 4, GFLAGS),
+ GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(10), 5, GFLAGS),
+ GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(10), 6, GFLAGS),
+ COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK1108_CLKGATE_CON(8), 15, GFLAGS),
+ COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK1108_CLKGATE_CON(8), 14, GFLAGS),
+ GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(8), 13, GFLAGS),
+
+
+
+ /*
+ * Clock-Architecture Diagram 4
+ */
+ COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK1108_CLKGATE_CON(6), 0, GFLAGS),
+ GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(17), 0, GFLAGS),
+ COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
+ RK1108_CLKSEL_CON(29), 0, 5, DFLAGS,
+ RK1108_CLKGATE_CON(7), 2, GFLAGS),
+ COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
+ RK1108_CLKSEL_CON(29), 8, 5, DFLAGS,
+ RK1108_CLKGATE_CON(7), 3, GFLAGS),
+
+
+ /*
+ * Clock-Architecture Diagram 5
+ */
+
+ /* PD_BUS */
+ GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(1), 0, GFLAGS),
+ GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(1), 1, GFLAGS),
+ GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(1), 2, GFLAGS),
+ COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
+ RK1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
+ COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0,
+ RK1108_CLKSEL_CON(3), 0, 5, DFLAGS,
+ RK1108_CLKGATE_CON(1), 4, GFLAGS),
+ COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0,
+ RK1108_CLKSEL_CON(3), 8, 5, DFLAGS,
+ RK1108_CLKGATE_CON(1), 5, GFLAGS),
+ GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(1), 6, GFLAGS),
+ GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(1), 7, GFLAGS),
+ GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(1), 8, GFLAGS),
+ GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(1), 9, GFLAGS),
+ GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(1), 10, GFLAGS),
+ GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 4, GFLAGS),
+
+ COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
+ RK1108_CLKGATE_CON(3), 1, GFLAGS),
+ COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
+ RK1108_CLKGATE_CON(3), 3, GFLAGS),
+ COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS,
+ RK1108_CLKGATE_CON(3), 5, GFLAGS),
+
+ COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+ RK1108_CLKSEL_CON(16), 0,
+ RK1108_CLKGATE_CON(3), 2, GFLAGS,
+ &rk1108_uart0_fracmux),
+ COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+ RK1108_CLKSEL_CON(17), 0,
+ RK1108_CLKGATE_CON(3), 4, GFLAGS,
+ &rk1108_uart1_fracmux),
+ COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
+ RK1108_CLKSEL_CON(18), 0,
+ RK1108_CLKGATE_CON(3), 6, GFLAGS,
+ &rk1108_uart2_fracmux),
+ GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 10, GFLAGS),
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 11, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 12, GFLAGS),
+
+
+ COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS,
+ RK1108_CLKGATE_CON(3), 7, GFLAGS),
+ COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS,
+ RK1108_CLKGATE_CON(3), 8, GFLAGS),
+ COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS,
+ RK1108_CLKGATE_CON(3), 9, GFLAGS),
+ GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 0, GFLAGS),
+ GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 1, GFLAGS),
+ GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 2, GFLAGS),
+ COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS,
+ RK1108_CLKGATE_CON(3), 10, GFLAGS),
+ GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 6, GFLAGS),
+ GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 3, GFLAGS),
+ GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 7, GFLAGS),
+ GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 8, GFLAGS),
+ GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(13), 9, GFLAGS),
+
+ GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(14), 0, GFLAGS),
+
+ GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
+ RK1108_CLKGATE_CON(12), 2, GFLAGS),
+ GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(12), 3, GFLAGS),
+ GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(12), 1, GFLAGS),
+
+ /* PD_DDR */
+ GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(0), 8, GFLAGS),
+ GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(0), 9, GFLAGS),
+ GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(0), 10, GFLAGS),
+ COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+ RK1108_CLKGATE_CON(10), 9, GFLAGS),
+ GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(12), 4, GFLAGS),
+ GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(12), 5, GFLAGS),
+ GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(12), 6, GFLAGS),
+ GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(0), 11, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 6
+ */
+
+ /* PD_PERI */
+ COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
+ RK1108_CLKSEL_CON(23), 10, 5, DFLAGS,
+ RK1108_CLKGATE_CON(4), 5, GFLAGS),
+ GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(15), 13, GFLAGS),
+ COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
+ RK1108_CLKSEL_CON(23), 5, 5, DFLAGS,
+ RK1108_CLKGATE_CON(4), 4, GFLAGS),
+ GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(15), 12, GFLAGS),
+
+ GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(4), 1, GFLAGS),
+ GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
+ RK1108_CLKGATE_CON(4), 2, GFLAGS),
+ COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED,
+ RK1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS,
+ RK1108_CLKGATE_CON(15), 11, GFLAGS),
+
+ COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
+ RK1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK1108_CLKGATE_CON(5), 0, GFLAGS),
+
+ COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
+ RK1108_CLKSEL_CON(25), 10, 2, MFLAGS,
+ RK1108_CLKGATE_CON(5), 2, GFLAGS),
+ DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
+ RK1108_CLKSEL_CON(26), 0, 8, DFLAGS),
+
+ COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
+ RK1108_CLKSEL_CON(25), 12, 2, MFLAGS,
+ RK1108_CLKGATE_CON(5), 1, GFLAGS),
+ DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
+ RK2928_CLKSEL_CON(26), 8, 8, DFLAGS),
+ GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 0, GFLAGS),
+ GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 1, GFLAGS),
+ GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 2, GFLAGS),
+
+ COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
+ RK1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK1108_CLKGATE_CON(5), 3, GFLAGS),
+ GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 3, GFLAGS),
+
+ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
+ RK1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS,
+ RK1108_CLKGATE_CON(5), 4, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 10, GFLAGS),
+ MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK1108_SDMMC_CON0, 1),
+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK1108_SDMMC_CON1, 1),
+
+ MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK1108_SDIO_CON0, 1),
+ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK1108_SDIO_CON1, 1),
+
+ MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK1108_EMMC_CON0, 1),
+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK1108_EMMC_CON1, 1),
+};
+
+static const char *const rk1108_critical_clocks[] __initconst = {
+ "aclk_core",
+ "aclk_bus_src_gpll",
+ "aclk_periph",
+ "hclk_periph",
+ "pclk_periph",
+};
+
+static void __init rk1108_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rk1108_pll_clks,
+ ARRAY_SIZE(rk1108_pll_clks),
+ RK1108_GRF_SOC_STATUS0);
+ rockchip_clk_register_branches(ctx, rk1108_clk_branches,
+ ARRAY_SIZE(rk1108_clk_branches));
+ rockchip_clk_protect_critical(rk1108_critical_clocks,
+ ARRAY_SIZE(rk1108_critical_clocks));
+
+ rockchip_clk_register_armclk(ctx, RK1108_ARMCLK, "armclk",
+ mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+ &rk1108_cpuclk_data, rk1108_cpuclk_rates,
+ ARRAY_SIZE(rk1108_cpuclk_rates));
+
+ rockchip_register_softrst(np, 13, reg_base + RK1108_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+ rockchip_register_restart_notifier(ctx, RK1108_GLB_SRST_FST, NULL);
+
+ rockchip_clk_of_add_provider(np, ctx);
+}
+CLK_OF_DECLARE(rk1108_cru, "rockchip,rk1108-cru", rk1108_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 1653edd..90c580a 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -34,6 +34,20 @@ struct clk;
#define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
+/* register positions shared by RK1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
+#define RK1108_PLL_CON(x) ((x) * 0x4)
+#define RK1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
+#define RK1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
+#define RK1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
+#define RK1108_GLB_SRST_FST 0x1c0
+#define RK1108_GLB_SRST_SND 0x1c4
+#define RK1108_SDMMC_CON0 0x1d8
+#define RK1108_SDMMC_CON1 0x1dc
+#define RK1108_SDIO_CON0 0x1e0
+#define RK1108_SDIO_CON1 0x1e4
+#define RK1108_EMMC_CON0 0x1e8
+#define RK1108_EMMC_CON1 0x1ec
+
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
diff --git a/include/dt-bindings/clock/rk1108-cru.h b/include/dt-bindings/clock/rk1108-cru.h
new file mode 100644
index 0000000..e731cc8
--- /dev/null
+++ b/include/dt-bindings/clock/rk1108-cru.h
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
+
+/* pll id */
+#define RK1108_APLL_ID 0
+#define RK1108_DPLL_ID 1
+#define RK1108_GPLL_ID 2
+#define RK1108_ARMCLK 3
+#define RK1108_END_PLL_ID 4
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0 65
+#define SCLK_NANDC 67
+#define SCLK_SDMMC 68
+#define SCLK_SDIO 69
+#define SCLK_EMMC 71
+#define SCLK_UART0 72
+#define SCLK_UART1 73
+#define SCLK_UART2 74
+#define SCLK_I2S0 75
+#define SCLK_I2S1 76
+#define SCLK_I2S2 77
+#define SCLK_TIMER0 78
+#define SCLK_TIMER1 79
+#define SCLK_SFC 80
+#define SCLK_SDMMC_DRV 81
+#define SCLK_SDIO_DRV 82
+#define SCLK_EMMC_DRV 83
+#define SCLK_SDMMC_SAMPLE 84
+#define SCLK_SDIO_SAMPLE 85
+#define SCLK_EMMC_SAMPLE 86
+
+/* aclk gates */
+#define ACLK_DMAC 251
+#define ACLK_PRE 252
+#define ACLK_CORE 253
+#define ACLK_ENMCORE 254
+
+/* pclk gates */
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GPIO3 323
+#define PCLK_GRF 329
+#define PCLK_I2C1 333
+#define PCLK_I2C2 334
+#define PCLK_I2C3 335
+#define PCLK_SPI 338
+#define PCLK_SFC 339
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_TSADC 344
+#define PCLK_PWM 350
+#define PCLK_TIMER 353
+#define PCLK_PERI 363
+
+/* hclk gates */
+#define HCLK_I2S0_8CH 442
+#define HCLK_I2S1_8CH 443
+#define HCLK_I2S2_2CH 444
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO 457
+#define HCLK_EMMC 459
+#define HCLK_PERI 478
+#define HCLK_SFC 479
+
+#define CLK_NR_CLKS (HCLK_SFC + 1)
+
+/* reset id */
+#define SRST_CORE_PO_AD 0
+#define SRST_CORE_AD 1
+#define SRST_L2_AD 2
+#define SRST_CPU_NIU_AD 3
+#define SRST_CORE_PO 4
+#define SRST_CORE 5
+#define SRST_L2 6
+#define RST_0RES7 7
+#define SRST_CORE_DBG 8
+#define PRST_DBG 9
+#define RST_DAP 10
+#define PRST_DBG_NIU 11
+#define RST_0RES12 12
+#define RST_0RES13 13
+#define RST_0RES14 14
+#define ARST_STRC_SYS_AD 15
+
+#define SRST_DDRPHY_CLKDIV 16
+#define SRST_DDRPHY 17
+#define PRST_DDRPHY 18
+#define PRST_HDMIPHY 19
+#define PRST_VDACPHY 20
+#define PRST_VADCPHY 21
+#define PRST_MIPI_CSI_PHY 22
+#define PRST_MIPI_DSI_PHY 23
+#define PRST_ACODEC 24
+#define ARST_BUS_NIU 25
+#define PRST_TOP_NIU 26
+#define ARST_INTMEM 27
+#define HRST_ROM 28
+#define ARST_DMAC 29
+#define SRST_MSCH_NIU 30
+#define PRST_MSCH_NIU 31
+
+#define PRST_DDRUPCTL 32
+#define NRST_DDRUPCTL 33
+#define PRST_DDRMON 34
+#define HRST_I2S0_8CH 35
+#define MRST_I2S0_8CH 36
+#define HRST_I2S1_2CH 37
+#define MRST_IS21_2CH 38
+#define HRST_I2S2_2CH 39
+#define MRST_I2S2_2CH 40
+#define HRST_CRYPTO 41
+#define SRST_CRYPTO 42
+#define PRST_SPI 43
+#define SRST_SPI 44
+#define PRST_UART0 45
+#define PRST_UART1 46
+#define PRST_UART2 47
+
+#define SRST_UART0 48
+#define SRST_UART1 49
+#define SRST_UART2 50
+#define PRST_I2C1 51
+#define PRST_I2C2 52
+#define PRST_I2C3 53
+#define SRST_I2C1 54
+#define SRST_I2C2 55
+#define SRST_I2C3 56
+#define RST_3RES9 57
+#define PRST_PWM1 58
+#define RST_3RES11 59
+#define SRST_PWM1 60
+#define PRST_WDT 61
+#define PRST_GPIO1 62
+#define PRST_GPIO2 63
+
+#define PRST_GPIO3 64
+#define PRST_GRF 65
+#define PRST_EFUSE 66
+#define PRST_EFUSE512 67
+#define PRST_TIMER0 68
+#define SRST_TIMER0 69
+#define SRST_TIMER1 70
+#define PRST_TSADC 71
+#define SRST_TSADC 72
+#define PRST_SARADC 73
+#define SRST_SARADC 74
+#define HRST_SYSBUS 75
+#define PRST_USBGRF 76
+#define RST_4RES13 77
+#define RST_4RES14 78
+#define RST_4RES15 79
+
+#define ARST_PERIPH_NIU 80
+#define HRST_PERIPH_NIU 81
+#define PRST_PERIPH_NIU 82
+#define HRST_PERIPH 83
+#define HRST_SDMMC 84
+#define HRST_SDIO 85
+#define HRST_EMMC 86
+#define HRST_NANDC 87
+#define NRST_NANDC 88
+#define HRST_SFC 89
+#define SRST_SFC 90
+#define ARST_GMAC 91
+#define HRST_OTG 92
+#define SRST_OTG 93
+#define SRST_OTG_ADP 94
+#define HRST_HOST0 95
+
+#define HRST_HOST0_AUX 96
+#define HRST_HOST0_ARB 97
+#define SRST_HOST0_EHCIPHY 98
+#define SRST_HOST0_UTMI 99
+#define SRST_USBPOR 100
+#define SRST_UTMI0 101
+#define SRST_UTMI1 102
+#define RST_6RES7 103
+#define RST_6RES8 104
+#define RST_6RES9 105
+#define RST_6RES10 106
+#define RST_6RES11 107
+#define RST_6RES12 108
+#define RST_6RES13 109
+#define RST_6RES14 110
+#define RST_6RES15 101
+
+#define ARST_VIO0_NIU 102
+#define ARST_VIO1_NIU 103
+#define HRST_VIO_NIU 104
+#define PRST_VIO_NIU 105
+#define ARST_VOP 106
+#define HRST_VOP 107
+#define DRST_VOP 108
+#define ARST_IEP 109
+#define HRST_IEP 110
+#define ARST_RGA 111
+#define HRST_RGA 112
+#define SRST_RGA 113
+#define PRST_CVBS 114
+#define PRST_HDMI 115
+#define SRST_HDMI 116
+#define PRST_MIPI_DSI 117
+
+#define ARST_ISP_NIU 118
+#define HRST_ISP_NIU 119
+#define HRST_ISP 120
+#define SRST_ISP 121
+#define ARST_VIP0 122
+#define HRST_VIP0 123
+#define PRST_VIP0 124
+#define ARST_VIP1 125
+#define HRST_VIP1 126
+#define PRST_VIP1 127
+#define ARST_VIP2 128
+#define HRST_VIP2 129
+#define PRST_VIP2 120
+#define ARST_VIP3 121
+#define HRST_VIP3 122
+#define PRST_VIP4 123
+
+#define PRST_CIF1TO4 124
+#define SRST_CVBS_CLK 125
+#define HRST_CVBS 126
+#define RST_9RES3 127
+#define RST_9RES4 128
+#define RST_9RES5 129
+#define RST_9RES6 130
+#define RST_9RES7 131
+#define RST_9RES8 132
+#define RST_9RES9 133
+#define RST_9RES10 134
+#define RST_9RES11 134
+#define RST_9RES12 136
+#define RST_9RES13 137
+#define RST_9RES14 138
+#define RST_9RES15 139
+
+#define ARST_VPU_NIU 140
+#define HRST_VPU_NIU 141
+#define ARST_VPU 142
+#define HRST_VPU 143
+#define ARST_RKVDEC_NIU 144
+#define HRST_RKVDEC_NIU 145
+#define ARST_RKVDEC 146
+#define HRST_RKVDEC 147
+#define SRST_RKVDEC_CABAC 148
+#define SRST_RKVDEC_CORE 149
+#define ARST_RKVENC_NIU 150
+#define HRST_RKVENC_NIU 151
+#define ARST_RKVENC 152
+#define HRST_RKVENC 153
+#define SRST_RKVENC_CORE 154
+#define RST_10RES15 155
+
+#define SRST_DSP_CORE 156
+#define SRST_DSP_SYS 157
+#define SRST_DSP_GLOBAL 158
+#define SRST_DSP_OECM 159
+#define PRST_DSP_IOP_NIU 160
+#define ARST_DSP_EPP_NIU 161
+#define ARST_DSP_EDP_NIU 162
+#define PRST_DSP_DBG_NIU 163
+#define PRST_DSP_CFG_NIU 164
+#define PRST_DSP_GRF 165
+#define PRST_DSP_MAILBOX 166
+#define PRST_DSP_INTC 167
+#define RST_11RES12 168
+#define PRST_DSP_PFM_MON 169
+#define SRST_DSP_PFM_MON 170
+#define ARST_DSP_EDAP_NIU 171
+
+#define SRST_PMU 172
+#define SRST_PMU_I2C0 173
+#define PRST_PMU_I2C0 174
+#define PRST_PMU_GPIO0 175
+#define PRST_PMU_INTMEM 176
+#define PRST_PMU_PWM0 177
+#define SRST_PMU_PWM0 178
+#define PRST_PMU_GRF 179
+#define SRST_PMU_NIU 180
+#define SRST_PMU_PVTM 181
+#define RST_12RES10 182
+#define RST_12RES11 183
+#define ARST_DSP_EDP_PERF 184
+#define ARST_DSP_EPP_PERF 185
+#define RST_12RES114 186
+#define RST_12RES15 187
+
+#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H */
+
--
2.7.4
^ permalink raw reply related
* [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC
From: Andy Yan @ 2016-11-03 12:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com>
RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core.
It is designed for varies application scenario such as car DVR, sports
DV, secure camera and UAV camera.
This patch add basic support for it with DMAC / UART / CRU / pinctrl
enabled.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/boot/dts/rk1108.dtsi | 420 ++++++++++++++++++++++++++++++++++++++
arch/arm/mach-rockchip/rockchip.c | 1 +
2 files changed, 421 insertions(+)
create mode 100644 arch/arm/boot/dts/rk1108.dtsi
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
new file mode 100644
index 0000000..9dccfea
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -0,0 +1,420 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/rk1108-cru.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rk1108";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ };
+
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma at 102a0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x102a0000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ bus_intmem at 10080000 {
+ compatible = "mmio-sram";
+ reg = <0x10080000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x2000>;
+ };
+
+ grf: syscon at 10300000 {
+ compatible = "rockchip,rk1108-grf", "syscon";
+ reg = <0x10300000 0x1000>;
+ };
+
+ emmc: dwmmc at 30110000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30110000 0x4000>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc at 30120000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30120000 0x4000>;
+ status = "disabled";
+ };
+
+ sdmmc: dwmmc at 30130000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 100000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30130000 0x4000>;
+ status = "disabled";
+ };
+
+ uart2: serial at 10210000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10210000 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "disabled";
+ };
+
+ uart1: serial at 10220000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10220000 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ status = "disabled";
+ };
+
+ uart0: serial at 10230000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10230000 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "disabled";
+ };
+
+ cru: clock-controller at 20200000 {
+ compatible = "rockchip,rk1108-cru";
+ reg = <0x20200000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller at 32010000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x32011000 0x1000>,
+ <0x32012000 0x1000>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk1108-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0 at 20030000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20030000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1 at 10310000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10310000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2 at 10320000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10320000 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3 at 10330000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10330000 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_input_high: pcfg-input-high {
+ bias-pull-up;
+ input-enable;
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ i2c2m1 {
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ i2c2m1_gpio: i2c2m1-gpio {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c2m05v {
+ i2c2m05v_xfer: i2c2m05v-xfer {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ i2c2m05v_gpio: i2c2m05v-gpio {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
+ <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts_gpio: uart0-rts-gpio {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m0 {
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m1 {
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
+ <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2_5v {
+ uart2_5v_cts: uart2_5v-cts {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart2_5v_rts: uart2_5v-rts {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index a7ab9ec..e7fdf06 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -76,6 +76,7 @@ static void __init rockchip_dt_init(void)
}
static const char * const rockchip_board_dt_compat[] = {
+ "rockchip,rk1108",
"rockchip,rk2928",
"rockchip,rk3066a",
"rockchip,rk3066b",
--
2.7.4
^ permalink raw reply related
* [PATCH] ARM: gr8: evb: Enable SPDIF
From: Maxime Ripard @ 2016-11-03 12:41 UTC (permalink / raw)
To: linux-arm-kernel
The GR8-EVB has a SPDIF out connector. Enable it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/ntc-gr8-evb.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/ntc-gr8-evb.dts b/arch/arm/boot/dts/ntc-gr8-evb.dts
index 4b622f3b5220..e3b7a6273c61 100644
--- a/arch/arm/boot/dts/ntc-gr8-evb.dts
+++ b/arch/arm/boot/dts/ntc-gr8-evb.dts
@@ -75,6 +75,24 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
};
+
+ spdif {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
};
&be0 {
--
2.10.1
^ permalink raw reply related
* [PATCH 5/6] ARM: add low level debug uart for rk1108
From: Andy Yan @ 2016-11-03 12:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com>
RK1108 UARTs are Synopsis DesignWare 8250 compatible.
Only with different register addresses.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/Kconfig.debug | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index d83f7c3..408540f 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -776,6 +776,30 @@ choice
their output to the standard serial port on the RealView
PB1176 platform.
+ config DEBUG_RK1108_UART0
+ bool "Kernel low-level debugging messages via Rockchip RK1108 UART0"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK1108 based platforms.
+
+ config DEBUG_RK1108_UART1
+ bool "Kernel low-level debugging messages via Rockchip RK1108 UART1"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK1108 based platforms.
+
+ config DEBUG_RK1108_UART2
+ bool "Kernel low-level debugging messages via Rockchip RK1108 UART2"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK1108 based platforms.
+
config DEBUG_RK29_UART0
bool "Kernel low-level debugging messages via Rockchip RK29 UART0"
depends on ARCH_ROCKCHIP
@@ -1465,6 +1489,9 @@ config DEBUG_UART_PHYS
default 0x10126000 if DEBUG_RK3X_UART1
default 0x101f1000 if DEBUG_VERSATILE
default 0x101fb000 if DEBUG_NOMADIK_UART
+ default 0x10210000 if DEBUG_RK1108_UART2
+ default 0x10220000 if DEBUG_RK1108_UART1
+ default 0x10230000 if DEBUG_RK1108_UART0
default 0x11002000 if DEBUG_MT8127_UART0
default 0x11006000 if DEBUG_MT6589_UART0
default 0x11009000 if DEBUG_MT8135_UART3
@@ -1563,6 +1590,9 @@ config DEBUG_UART_PHYS
config DEBUG_UART_VIRT
hex "Virtual base address of debug UART"
+ default 0xc881f000 if DEBUG_RK1108_UART2
+ default 0xc8821000 if DEBUG_RK1108_UART1
+ default 0xc8912000 if DEBUG_RK1108_UART0
default 0xe0000a00 if DEBUG_NETX_UART
default 0xe0010fe0 if ARCH_RPC
default 0xf0000be0 if ARCH_EBSA110
--
2.7.4
^ permalink raw reply related
* [PATCH 6/6] ARM: dts: rockchip: add rockchip RK1108 Evaluation board
From: Andy Yan @ 2016-11-03 12:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com>
RK1108EVB is designed by Rockchip for CVR field.
This patch add basic support for it, which can boot with
initramfs into shell.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
Documentation/devicetree/bindings/arm/rockchip.txt | 3 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk1108-evb.dts | 69 ++++++++++++++++++++++
3 files changed, 73 insertions(+)
create mode 100644 arch/arm/boot/dts/rk1108-evb.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 10b92b5..8670181 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -1,5 +1,8 @@
Rockchip platforms device tree bindings
---------------------------------------
+- Rockchip RK1108 Evaluation board
+ Required root node properties:
+ - compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
- Kylin RK3036 board:
Required root node properties:
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e49476a..249dca9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -635,6 +635,7 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pba8.dtb \
arm-realview-pbx-a9.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk1108-evb.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts
new file mode 100644
index 0000000..3956cff
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108-evb.dts
@@ -0,0 +1,69 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk1108.dtsi"
+
+/ {
+ model = "Rockchip RK1108 Evaluation board";
+ compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
+
+ memory at 60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x08000000>;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH next 1/2] media: mtk-mdp: fix video_device_release argument
From: Hans Verkuil @ 2016-11-03 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161028075253.gdy2bbugih6oqncw@romuald.bergerie>
Hi Vincent,
On 28/10/16 09:52, Vincent Stehl? wrote:
> On Thu, Oct 27, 2016 at 10:23:24PM +0200, Vincent Stehl? wrote:
>> video_device_release() takes a pointer to struct video_device as argument.
>> Fix two call sites where the address of the pointer is passed instead.
>
> Sorry, I messed up: please ignore that "fix". The 0day robot made me
> realize this is indeed not a proper fix.
>
> The issue remains, though: we cannot call video_device_release() on the
> vdev structure member, as this will in turn call kfree(). Most probably,
> vdev needs to be dynamically allocated, or the call to
> video_device_release() dropped completely.
I prefer that vdev is dynamically allocated. There are known problems with
embedded video_device structs, so allocating it is preferred.
Minghsiu, can you do that?
Regards,
Hans
>
> Sorry for the bad patch.
>
> Best regards,
>
> Vincent.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-media" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH V3 6/6] bus: Add support for Tegra Generic Memory Interface
From: Mirza Krak @ 2016-11-03 13:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3cdf7281-840f-1aa0-5a57-fe58501165f4@nvidia.com>
2016-11-03 11:51 GMT+01:00 Jon Hunter <jonathanh@nvidia.com>:
>
> On 27/10/16 15:01, Mirza Krak wrote:
>>
>> From: Mirza Krak <mirza.krak@gmail.com>
>>
>> The Generic Memory Interface bus can be used to connect high-speed
>> devices such as NOR flash, FPGAs, DSPs...
>>
>> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
>> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
>> ---
>>
>> Changes in v2:
>> - Fixed some checkpatch errors
>> - Re-ordered probe to get rid of local variables
>> - Moved of_platform_default_populate call to the end of probe
>> - Use the timing and configuration properties from the child device
>> - Added warning if more then 1 child device exist
>>
>> Changes in v3:
>> - added helper function to disable the controller which is used in remove
>> and
>> on error.
>> - Added logic to parse CS# from "ranges" property with fallback to "reg"
>> property
>>
>> drivers/bus/Kconfig | 8 ++
>> drivers/bus/Makefile | 1 +
>> drivers/bus/tegra-gmi.c | 267
>> ++++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 276 insertions(+)
>> create mode 100644 drivers/bus/tegra-gmi.c
>>
>> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
>> index 4ed7d26..2e75a7f 100644
>> --- a/drivers/bus/Kconfig
>> +++ b/drivers/bus/Kconfig
>> @@ -141,6 +141,14 @@ config TEGRA_ACONNECT
>> Driver for the Tegra ACONNECT bus which is used to interface
>> with
>> the devices inside the Audio Processing Engine (APE) for
>> Tegra210.
>>
>> +config TEGRA_GMI
>> + tristate "Tegra Generic Memory Interface bus driver"
>> + depends on ARCH_TEGRA
>> + help
>> + Driver for the Tegra Generic Memory Interface bus which can be
>> used
>> + to attach devices such as NOR, UART, FPGA and more.
>> +
>> +
>
>
> Nit-pick ... only one additional line above is needed to be consistent with
> the rest of the file.
Will fix that.
>
>
>> config UNIPHIER_SYSTEM_BUS
>> tristate "UniPhier System Bus driver"
>> depends on ARCH_UNIPHIER && OF
>> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
>> index ac84cc4..34e2bab 100644
>> --- a/drivers/bus/Makefile
>> +++ b/drivers/bus/Makefile
>> @@ -18,5 +18,6 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
>> obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
>> obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
>> obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o
>> +obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o
>> obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
>> obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
>> diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c
>> new file mode 100644
>> index 0000000..dd9623e
>> --- /dev/null
>> +++ b/drivers/bus/tegra-gmi.c
>> @@ -0,0 +1,267 @@
>> +/*
>> + * Driver for NVIDIA Generic Memory Interface
>> + *
>> + * Copyright (C) 2016 Host Mobility AB. All rights reserved.
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/reset.h>
>> +
>> +#define TEGRA_GMI_CONFIG 0x00
>> +#define TEGRA_GMI_CONFIG_GO BIT(31)
>> +#define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30)
>> +#define TEGRA_GMI_MUX_MODE BIT(28)
>> +#define TEGRA_GMI_RDY_BEFORE_DATA BIT(24)
>> +#define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23)
>> +#define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22)
>> +#define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21)
>> +#define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20)
>> +#define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4)
>> +
>> +#define TEGRA_GMI_TIMING0 0x10
>> +#define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12)
>> +#define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8)
>> +#define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4)
>> +#define TEGRA_GMI_CE_WIDTH(x) (x & 0xf)
>> +
>> +#define TEGRA_GMI_TIMING1 0x14
>> +#define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16)
>> +#define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8)
>> +#define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff)
>> +
>> +struct tegra_gmi_priv {
>> + void __iomem *base;
>> + struct reset_control *rst;
>> + struct clk *clk;
>> +
>> + u32 snor_config;
>> + u32 snor_timing0;
>> + u32 snor_timing1;
>> +};
>> +
>> +static void tegra_gmi_disable(struct tegra_gmi_priv *priv)
>> +{
>> + u32 config;
>> +
>> + /* stop GMI operation */
>> + config = readl(priv->base + TEGRA_GMI_CONFIG);
>> + config &= ~TEGRA_GMI_CONFIG_GO;
>> + writel(config, priv->base + TEGRA_GMI_CONFIG);
>> +
>> + reset_control_assert(priv->rst);
>> + clk_disable_unprepare(priv->clk);
>> +}
>> +
>> +static void tegra_gmi_init(struct device *dev, struct tegra_gmi_priv
>> *priv)
>> +{
>> + writel(priv->snor_timing0, priv->base + TEGRA_GMI_TIMING0);
>> + writel(priv->snor_timing1, priv->base + TEGRA_GMI_TIMING1);
>> +
>> + priv->snor_config |= TEGRA_GMI_CONFIG_GO;
>> + writel(priv->snor_config, priv->base + TEGRA_GMI_CONFIG);
>> +}
>> +
>> +static int tegra_gmi_parse_dt(struct device *dev, struct tegra_gmi_priv
>> *priv)
>> +{
>> + struct device_node *child =
>> of_get_next_available_child(dev->of_node,
>> + NULL);
>> + u32 property, ranges[4];
>> + int ret;
>> +
>> + if (!child) {
>> + dev_warn(dev, "no child nodes found\n");
>> + return 0;
>
>
> Don't we want to return an error here? Otherwise, we will call
> tegra_gmi_init() with an invalid configuration.
True, we probably want that. My thought was that we might accept a
tegra-gmi node without any child nodes and just print a warning. But
since it is the child node that holds the bus configuration it makes
sense to fail probe due to no child nodes.
>
>
>> + }
>> +
>> + /*
>> + * We currently only support one child device due to lack of
>> + * chip-select address decoding. Which means that we only have one
>> + * chip-select line from the GMI controller.
>> + */
>> + if (of_get_child_count(dev->of_node) > 1)
>> + dev_warn(dev, "only one child device is supported.");
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
>> + priv->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
>> + priv->snor_config |= TEGRA_GMI_MUX_MODE;
>> +
>> + if (of_property_read_bool(child,
>> "nvidia,snor-rdy-active-before-data"))
>> + priv->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-rdy-inv"))
>> + priv->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-adv-inv"))
>> + priv->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-oe-inv"))
>> + priv->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-cs-inv"))
>> + priv->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
>> +
>> + /* Decode the CS# */
>> + ret = of_property_read_u32_array(child, "ranges", ranges, 4);
>> + if (ret < 0) {
>> + /* Invalid binding */
>> + if (ret == -EOVERFLOW) {
>> + dev_err(dev, "invalid ranges length\n");
>> + goto error_cs_decode;
>> + }
>> +
>> + /*
>> + * If we reach here it means that the child node has an
>> empty
>> + * ranges or it does not exist at all. Attempt to decode
>> the
>> + * CS# from the reg property instead.
>> + */
>> + ret = of_property_read_u32(child, "reg", &property);
>> + if (ret < 0) {
>> + dev_err(dev, "no reg property found\n");
>> + goto error_cs_decode;
>> + }
>> + } else {
>> + property = ranges[1];
>> + }
>> +
>> + priv->snor_config |= TEGRA_GMI_CS_SELECT(property);
>
>
> Should we make sure the CS is a valid value before setting?
The TEGRA_GMI_CS_SELECT(x) macro will truncate any erroneous CS value.
But yeah we could do a sanity check instead and return an error if it
is invalid.
>
>
>> +
>> + /* The default values that are provided below are reset values */
>> + if (!of_property_read_u32(child, "nvidia,snor-muxed-width",
>> &property))
>> + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
>> + else
>> + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-hold-width",
>> &property))
>> + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
>> + else
>> + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-adv-width",
>> &property))
>> + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
>> + else
>> + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-ce-width",
>> &property))
>> + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
>> + else
>> + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-we-width",
>> &property))
>> + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
>> + else
>> + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-oe-width",
>> &property))
>> + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
>> + else
>> + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-wait-width",
>> &property))
>> + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
>> + else
>> + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
>> +
>> +error_cs_decode:
>> + if (ret < 0)
>> + dev_err(dev, "failed to decode chip-select number\n");
>
>
> Nit do we need another error message here? Can we add the "failed to decode
> CS" part the earlier message?
Does it make sense to drop the two earlier messages instead and keep this one?
Best Regards
Mirza
^ permalink raw reply
* [PATCH] dmaengine: st_fdma: Update st_fdma to 'depends on REMOTEPROC'.
From: Koul, Vinod @ 2016-11-03 13:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477039465-31121-1-git-send-email-peter.griffin@linaro.org>
On Fri, 2016-10-21 at 09:44 +0100, Peter Griffin wrote:
> During randconfig builds you can get the following warning
> "warning: (ST_FDMA) selects ST_SLIM_REMOTEPROC which has unmet direct
> ?dependencies (REMOTEPROC)"
>
> randconfig builds should always build without any warnings so
> update fdma to depend on REMOTEPROC so this can not happen.
Applied, thanks
--
~Vinod
^ permalink raw reply
* [PATCH V7 0/4] dmaengine: qcom_hidma: add MSI interrupt support
From: Koul, Vinod @ 2016-11-03 13:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477067879-23750-1-git-send-email-okaya@codeaurora.org>
On Fri, 2016-10-21 at 12:37 -0400, Sinan Kaya wrote:
> The new version of the HW supports MSI interrupts instead of wired
> interrupts. The MSI interrupts are especially useful for the guest
> machine
> execution. The wired interrupts usually trap to the hypervisor and
> then are
> relayed to the actual interrupt.
>
> The MSI interrupts can be directly fed into the interrupt controller.
>
> Adding a new OF compat string (qcom,hidma-1.1) and ACPI string
> (QCOM8062)
> to distinguish newer HW from the older ones.
Applied, thanks
--
~Vinod
^ permalink raw reply
* [PATCH] ARM: DTS: r8a7794: alt: Fix PCF names for DU
From: Jacopo Mondi @ 2016-11-03 13:42 UTC (permalink / raw)
To: linux-arm-kernel
Update the PCF pin groups and function names of DU interface for
r8a7794 ALT board.
The currently specified pin groups and function names prevented PCF and
DU interfaces from being correctly configured:
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
rcar-du: probe of feb00000.display failed with error -22
Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
---
Patch applied against Simon Horman's renesas/master branch.
The PCF pin groups and function renaming was introduced by commit 56ed4bb9 and
DTS for ALT board has never been update accordingly.
Tested displaying frames on VGA interface: the rcar-du driver loads correctly.
arch/arm/boot/dts/r8a7794-alt.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 8d1b35a..9d65fb3 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -165,8 +165,8 @@
pinctrl-names = "default";
du_pins: du {
- groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
- function = "du";
+ groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
+ function = "du1";
};
scif2_pins: scif2 {
--
2.7.4
^ permalink raw reply related
* [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Jon Hunter @ 2016-11-03 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALw8SCWC7RmNLVv4vxO9xw3jHVkgCaevbL61sJcpcva9CiaAVQ@mail.gmail.com>
On 03/11/16 12:30, Mirza Krak wrote:
> 2016-11-03 13:26 GMT+01:00 Mirza Krak <mirza.krak@gmail.com>:
>> 2016-11-03 11:06 GMT+01:00 Jon Hunter <jonathanh@nvidia.com>:
>>> Hi Mirza,
>>>
>>> On 27/10/16 15:01, Mirza Krak wrote:
>>>>
>>>> From: Mirza Krak <mirza.krak@gmail.com>
>>>>
>>>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
>>>> is max rate.
>>>>
>>>> The maximum rate value of 92 MHz is pulled from the downstream L4T
>>>> kernel.
>>>
>>>
>>> Thanks for adding this. I assume that this is from an L4T r16 release with a
>>> v3.1 kernel. I had a quick poke through the kernel sources for v3.1 but was
>>> unable to see where this is set. Obviously v3.1 did not have CCF and so
>>> everything seems to be in the arch/arm/mach-tegra directory for setting up
>>> clocks. Can you point me to the appropriate sources so I can ACK this?
>>
>> I use the kernel sources provided by Toradex, and these sources are
>> based on L4T r16 release.
>>
>> http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
>
> Ops, pre-mature send.
>
> I also added Marcel from Toradex on CC.
>
> The link to the source are [1] for Tegra2 and [2] for Tegra3.
>
> [1]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
> [2]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra3_clocks.c?h=tegra#n4353
Great. Yes I see the same. Thanks!
Jon
--
nvpublic
^ permalink raw reply
* [PATCH v14 14/16] vfio/type1: Check doorbell safety
From: Diana Madalina Craciun @ 2016-11-03 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1476278544-3397-15-git-send-email-eric.auger@redhat.com>
Hi Eric,
On 10/12/2016 04:23 PM, Eric Auger wrote:
> On x86 IRQ remapping is abstracted by the IOMMU. On ARM this is abstracted
> by the msi controller.
>
> Since we currently have no way to detect whether the MSI controller is
> upstream or downstream to the IOMMU we rely on the MSI doorbell information
> registered by the interrupt controllers. In case at least one doorbell
> does not implement proper isolation, we state the assignment is unsafe
> with regard to interrupts. This is a coarse assessment but should allow to
> wait for a better system description.
>
> At this point ARM sMMU still advertises IOMMU_CAP_INTR_REMAP. This is
> removed in next patch.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> ---
> v13 -> v15:
> - check vfio_msi_resv before checking whether msi doorbell is safe
>
> v9 -> v10:
> - coarse safety assessment based on MSI doorbell info
>
> v3 -> v4:
> - rename vfio_msi_parent_irq_remapping_capable into vfio_safe_irq_domain
> and irq_remapping into safe_irq_domains
>
> v2 -> v3:
> - protect vfio_msi_parent_irq_remapping_capable with
> CONFIG_GENERIC_MSI_IRQ_DOMAIN
> ---
> drivers/vfio/vfio_iommu_type1.c | 30 +++++++++++++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
> index e0c97ef..c18ba9d 100644
> --- a/drivers/vfio/vfio_iommu_type1.c
> +++ b/drivers/vfio/vfio_iommu_type1.c
> @@ -442,6 +442,29 @@ static void vfio_unmap_unpin(struct vfio_iommu *iommu, struct vfio_dma *dma)
> }
>
> /**
> + * vfio_msi_resv - Return whether any VFIO iommu domain requires
> + * MSI mapping
> + *
> + * @iommu: vfio iommu handle
> + *
> + * Return: true of MSI mapping is needed, false otherwise
> + */
> +static bool vfio_msi_resv(struct vfio_iommu *iommu)
> +{
> + struct iommu_domain_msi_resv msi_resv;
> + struct vfio_domain *d;
> + int ret;
> +
> + list_for_each_entry(d, &iommu->domain_list, next) {
> + ret = iommu_domain_get_attr(d->domain, DOMAIN_ATTR_MSI_RESV,
> + &msi_resv);
> + if (!ret)
> + return true;
> + }
> + return false;
> +}
> +
> +/**
> * vfio_set_msi_aperture - Sets the msi aperture on all domains
> * requesting MSI mapping
> *
> @@ -945,8 +968,13 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
> INIT_LIST_HEAD(&domain->group_list);
> list_add(&group->next, &domain->group_list);
>
> + /*
> + * to advertise safe interrupts either the IOMMU or the MSI controllers
> + * must support IRQ remapping (aka. interrupt translation)
> + */
> if (!allow_unsafe_interrupts &&
> - !iommu_capable(bus, IOMMU_CAP_INTR_REMAP)) {
> + (!iommu_capable(bus, IOMMU_CAP_INTR_REMAP) &&
> + !(vfio_msi_resv(iommu) && iommu_msi_doorbell_safe()))) {
> pr_warn("%s: No interrupt remapping support. Use the module param \"allow_unsafe_interrupts\" to enable VFIO IOMMU support on this platform\n",
> __func__);
> ret = -EPERM;
I understand from the other discussions that you will respin these
series, but anyway I have tested this version with GICV3 + ITS and it
stops here. As I have a GICv3 I am not supposed to enable allow unsafe
interrupts. What I see is that vfio_msi_resv returns false just because
the iommu->domain_list list is empty. The newly created domain is
actually added to the domain_list at the end of this function, so it
seems normal for the list to be empty at this point.
Thanks,
Diana
^ permalink raw reply
* [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Jon Hunter @ 2016-11-03 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477576872-2665-2-git-send-email-mirza.krak@gmail.com>
On 27/10/16 15:01, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
>
> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
> is max rate.
>
> The maximum rate value of 92 MHz is pulled from the downstream L4T
> kernel.
>
> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
^ permalink raw reply
* [PATCH V3 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table
From: Jon Hunter @ 2016-11-03 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477576872-2665-3-git-send-email-mirza.krak@gmail.com>
On 27/10/16 15:01, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
>
> Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which
> is max rate.
>
> The maximum rate value of 127 MHz is pulled from the downstream L4T
> kernel.
>
> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
^ permalink raw reply
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