* [PATCH 2/3] ARM: cache-uniphier: refactor jump label to follow coding style guideline
From: Masahiro Yamada @ 2016-11-04 11:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478259816-24965-1-git-send-email-yamada.masahiro@socionext.com>
Documentation/CodingStyle recommends to use label names which say
what the goto does or why the goto exists.
Just in case, split it up into three labels because the CodingStyle
says "one err bugs" is a common type of bug (although, I do not
believe the current code includes such a bug).
During the refactoring, iounmap(data->op_base) turned out to have no
corresponding bail-out point, so remove it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mm/cache-uniphier.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index 58f2ddb..c71ab7c 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -387,21 +387,21 @@ static int __init __uniphier_cache_init(struct device_node *np,
if (!data->ctrl_base) {
pr_err("L%d: failed to map control register\n", *cache_level);
ret = -ENOMEM;
- goto err;
+ goto free_mem;
}
data->rev_base = of_iomap(np, 1);
if (!data->rev_base) {
pr_err("L%d: failed to map revision register\n", *cache_level);
ret = -ENOMEM;
- goto err;
+ goto unmap_ctrl;
}
data->op_base = of_iomap(np, 2);
if (!data->op_base) {
pr_err("L%d: failed to map operation register\n", *cache_level);
ret = -ENOMEM;
- goto err;
+ goto unmap_rev;
}
data->way_ctrl_base = data->ctrl_base + 0xc00;
@@ -451,10 +451,12 @@ static int __init __uniphier_cache_init(struct device_node *np,
of_node_put(next_np);
return ret;
-err:
- iounmap(data->op_base);
+
+unmap_rev:
iounmap(data->rev_base);
+unmap_ctrl:
iounmap(data->ctrl_base);
+free_mem:
kfree(data);
return ret;
--
1.9.1
^ permalink raw reply related
* [PATCH 3/3] ARM: cache-uniphier: clean up active way setup code
From: Masahiro Yamada @ 2016-11-04 11:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478259816-24965-1-git-send-email-yamada.masahiro@socionext.com>
Now, the active way setup function is called with a fixed value zero
for the second argument only when enabling the outer-cache.
The code can be simpler.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mm/cache-uniphier.c | 20 +++++++-------------
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c
index c71ab7c..58ba2bd 100644
--- a/arch/arm/mm/cache-uniphier.c
+++ b/arch/arm/mm/cache-uniphier.c
@@ -71,8 +71,7 @@
* @ctrl_base: virtual base address of control registers
* @rev_base: virtual base address of revision registers
* @op_base: virtual base address of operation registers
- * @way_present_mask: each bit specifies if the way is present
- * @way_locked_mask: each bit specifies if the way is locked
+ * @way_mask: each bit specifies if the way is present
* @nsets: number of associativity sets
* @line_size: line size in bytes
* @range_op_max_size: max size that can be handled by a single range operation
@@ -83,8 +82,7 @@ struct uniphier_cache_data {
void __iomem *rev_base;
void __iomem *op_base;
void __iomem *way_ctrl_base;
- u32 way_present_mask;
- u32 way_locked_mask;
+ u32 way_mask;
u32 nsets;
u32 line_size;
u32 range_op_max_size;
@@ -234,17 +232,13 @@ static void __uniphier_cache_enable(struct uniphier_cache_data *data, bool on)
writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC);
}
-static void __init __uniphier_cache_set_locked_ways(
- struct uniphier_cache_data *data,
- u32 way_mask)
+static void __init __uniphier_cache_set_active_ways(
+ struct uniphier_cache_data *data)
{
unsigned int cpu;
- data->way_locked_mask = way_mask & data->way_present_mask;
-
for_each_possible_cpu(cpu)
- writel_relaxed(~data->way_locked_mask & data->way_present_mask,
- data->way_ctrl_base + 4 * cpu);
+ writel_relaxed(data->way_mask, data->way_ctrl_base + 4 * cpu);
}
static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
@@ -307,7 +301,7 @@ static void __init uniphier_cache_enable(void)
list_for_each_entry(data, &uniphier_cache_list, list) {
__uniphier_cache_enable(data, true);
- __uniphier_cache_set_locked_ways(data, 0);
+ __uniphier_cache_set_active_ways(data);
}
}
@@ -381,7 +375,7 @@ static int __init __uniphier_cache_init(struct device_node *np,
data->line_size = line_size;
data->nsets = nsets;
- data->way_present_mask = ((u32)1 << cache_size / nsets / line_size) - 1;
+ data->way_mask = GENMASK(cache_size / nsets / line_size - 1, 0);
data->ctrl_base = of_iomap(np, 0);
if (!data->ctrl_base) {
--
1.9.1
^ permalink raw reply related
* [PATCH] bus: vexpress-config: fix device reference leak
From: Russell King - ARM Linux @ 2016-11-04 12:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478259746.17152.126.camel@arm.com>
On Fri, Nov 04, 2016 at 11:42:26AM +0000, Pawel Moll wrote:
> On Tue, 2016-11-01 at 11:43 +0100, Johan Hovold wrote:
> > Make sure to drop the reference to the parent device taken by
> > class_find_device() after populating the bus.
> >
> > Fixes: 3b9334ac835b ("mfd: vexpress: Convert custom func API to
> > regmap")
> > Signed-off-by: Johan Hovold <johan@kernel.org>
>
> You're right. May I ask how did you figure it out? The get_device()
> happening in class_find_device() is a bit obscure,
It's not obscure at all - all the functions that find a device do so
under a lock to ensure that the device does not go away, and they
take a reference count on the device before returning the pointer for
exactly the same reason.
If they didn't do that, the find function could locate a struct device
while another thread is deleting the struct device, and it would then
return a stale pointer - and dereferencing that pointer would then be
a use-after-free bug.
So not obscure, but rather fundamentally necessary.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH 2/3] ARM: cache-uniphier: refactor jump label to follow coding style guideline
From: Russell King - ARM Linux @ 2016-11-04 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478259816-24965-3-git-send-email-yamada.masahiro@socionext.com>
On Fri, Nov 04, 2016 at 08:43:35PM +0900, Masahiro Yamada wrote:
> Documentation/CodingStyle recommends to use label names which say
> what the goto does or why the goto exists.
>
> Just in case, split it up into three labels because the CodingStyle
> says "one err bugs" is a common type of bug (although, I do not
> believe the current code includes such a bug).
However, this has the effect of making the code unnecessarily more
complicated, which is a bad thing. Avoiding unnecessary code
complexity wins over style rules.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH] ARM: dts: armada-370-rn102: drop specification of compatible for i2c0
From: Gregory CLEMENT @ 2016-11-04 12:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020191527.27679-1-u.kleine-koenig@pengutronix.de>
Hi Uwe,
On jeu., oct. 20 2016, Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de> wrote:
> The compatible string is already provided by armada-370.dtsi.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
Applied on mvebu/dt
Thanks,
Gregory
> ---
> Hello,
>
> this is the same as commit 43940ce3b089962f97de544d72b783bd146ef362 that
> currently is in next, just for rn102 instead of rn104.
>
> Best regards
> Uwe
>
> arch/arm/boot/dts/armada-370-netgear-rn102.dts | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> index 39181b3fa90d..3ca6330a1752 100644
> --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> @@ -120,7 +120,6 @@
> };
>
> i2c at 11000 {
> - compatible = "marvell,mv64xxx-i2c";
> clock-frequency = <100000>;
> status = "okay";
>
> --
> 2.9.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] ARM: dts: armada-370-rn102: add pinmuxing for i2c0
From: Gregory CLEMENT @ 2016-11-04 12:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161020191942.30616-1-u.kleine-koenig@pengutronix.de>
Hi Uwe,
On jeu., oct. 20 2016, Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de> wrote:
> Up to now a working i2c bus depended on the bootloader to configure the
> pinmuxing. Make it explicit.
>
> As a side effect this change makes i2c work in barebox.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
Applied on mvebu/dt
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-370-netgear-rn102.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> index 3ca6330a1752..a9e3810aea65 100644
> --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> @@ -121,6 +121,10 @@
>
> i2c at 11000 {
> clock-frequency = <100000>;
> +
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> status = "okay";
>
> isl12057: isl12057 at 68 {
> --
> 2.9.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] ARM: mvebu: Update comment for main PLL frequency
From: Gregory CLEMENT @ 2016-11-04 12:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161025235242.31764-1-chris.packham@alliedtelesis.co.nz>
Hi Chris,
On mer., oct. 26 2016, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> The actual frequency was updated in commit ae142bd99765 ("ARM: mvebu:
> Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the
> comment was not updated. Update it now.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Applied on mvebu/dt
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-375.dtsi | 2 +-
> arch/arm/boot/dts/armada-38x.dtsi | 2 +-
> arch/arm/boot/dts/armada-39x.dtsi | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
> index cc952cf8ec30..45fa92f9cf5c 100644
> --- a/arch/arm/boot/dts/armada-375.dtsi
> +++ b/arch/arm/boot/dts/armada-375.dtsi
> @@ -65,7 +65,7 @@
> };
>
> clocks {
> - /* 2 GHz fixed main PLL */
> + /* 1 GHz fixed main PLL */
> mainpll: mainpll {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index 2d7668848c5a..7450e9fea45d 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -661,7 +661,7 @@
> };
>
> clocks {
> - /* 2 GHz fixed main PLL */
> + /* 1 GHz fixed main PLL */
> mainpll: mainpll {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
> index 34cba87f9200..de171baffcf6 100644
> --- a/arch/arm/boot/dts/armada-39x.dtsi
> +++ b/arch/arm/boot/dts/armada-39x.dtsi
> @@ -573,7 +573,7 @@
> };
>
> clocks {
> - /* 2 GHz fixed main PLL */
> + /* 1 GHz fixed main PLL */
> mainpll: mainpll {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.10.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] convert orion5x ls-chl to device tree
From: Gregory CLEMENT @ 2016-11-04 12:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <14522899-679b-2f8b-73ca-493788299790@gmail.com>
Hi Ash,
On mar., oct. 25 2016, Ash Hughes <sehguh.hsa@gmail.com> wrote:
> Hi all,
>
> This patch converts my orion5x ls-chl Linkstation device to device
> tree.
I was about to apply your patch but it does not apply on mvebu/dt or
even on v4.9-rc1.
Could you rebase it?
Thanks,
Gregory
>
> Signed-off-by: Ashley Hughes <ashley.hughes@blueyonder.co.uk>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/orion5x-lschl.dts | 171 ++++++++++++++++++
> arch/arm/mach-orion5x/Kconfig | 4 +-
> arch/arm/mach-orion5x/Makefile | 1 -
> arch/arm/mach-orion5x/ls-chl-setup.c | 331 -----------------------------------
> 5 files changed, 174 insertions(+), 334 deletions(-)
> create mode 100644 arch/arm/boot/dts/orion5x-lschl.dts
> delete mode 100644 arch/arm/mach-orion5x/ls-chl-setup.c
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index befcd26..4853049 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -597,6 +597,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
> orion5x-lacie-ethernet-disk-mini-v2.dtb \
> orion5x-linkstation-lsgl.dtb \
> orion5x-linkstation-lswtgl.dtb \
> + orion5x-lschl.dtb \
> orion5x-lswsgl.dtb \
> orion5x-maxtor-shared-storage-2.dtb \
> orion5x-netgear-wnr854t.dtb \
> diff --git a/arch/arm/boot/dts/orion5x-lschl.dts b/arch/arm/boot/dts/orion5x-lschl.dts
> new file mode 100644
> index 0000000..9474092
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-lschl.dts
> @@ -0,0 +1,171 @@
> +/*
> + * Device Tree file for Buffalo Linkstation LS-CHLv3
> + *
> + * Copyright (C) 2016 Ash Hughes <ashley.hughes@blueyonder.co.uk>
> + * Copyright (C) 2015, 2016
> + * Roger Shimizu <rogershimizu@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include "orion5x-linkstation.dtsi"
> +#include "mvebu-linkstation-gpio-simple.dtsi"
> +#include "mvebu-linkstation-fan.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Buffalo Linkstation Live v3 (LS-CHL)";
> + compatible = "buffalo,lschl", "marvell,orion5x-88f5182", "marvell,orion5x";
> +
> + memory { /* 128 MB */
> + device_type = "memory";
> + reg = <0x00000000 0x8000000>;
> + };
> +
> + gpio_keys {
> + func {
> + label = "Function Button";
> + linux,code = <KEY_OPTION>;
> + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
> + };
> +
> + power-on-switch {
> + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
> + };
> +
> + power-auto-switch {
> + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + gpio_leds {
> + pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info &pmx_led_func>;
> + blue-power-led {
> + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
> + };
> +
> + red-alarm-led {
> + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
> + };
> +
> + amber-info-led {
> + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
> + };
> +
> + func {
> + label = "lschl:func:blue:top";
> + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + gpio_fan {
> + gpios = <&gpio0 14 GPIO_ACTIVE_LOW
> + &gpio0 16 GPIO_ACTIVE_LOW>;
> +
> + alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +&pinctrl {
> + pmx_led_power: pmx-leds {
> + marvell,pins = "mpp0";
> + marvell,function = "gpio";
> + };
> +
> + pmx_power_hdd: pmx-power-hdd {
> + marvell,pins = "mpp1";
> + marvell,function = "gpio";
> + };
> +
> + pmx_led_alarm: pmx-leds {
> + marvell,pins = "mpp2";
> + marvell,function = "gpio";
> + };
> +
> + pmx_led_info: pmx-leds {
> + marvell,pins = "mpp3";
> + marvell,function = "gpio";
> + };
> +
> + pmx_fan_lock: pmx-fan-lock {
> + marvell,pins = "mpp6";
> + marvell,function = "gpio";
> + };
> +
> + pmx_power_switch: pmx-power-switch {
> + marvell,pins = "mpp8", "mpp10", "mpp15";
> + marvell,function = "gpio";
> + };
> +
> + pmx_power_usb: pmx-power-usb {
> + marvell,pins = "mpp9";
> + marvell,function = "gpio";
> + };
> +
> + pmx_fan_high: pmx-fan-high {
> + marvell,pins = "mpp14";
> + marvell,function = "gpio";
> + };
> +
> + pmx_fan_low: pmx-fan-low {
> + marvell,pins = "mpp16";
> + marvell,function = "gpio";
> + };
> +
> + pmx_led_func: pmx-leds {
> + marvell,pins = "mpp17";
> + marvell,function = "gpio";
> + };
> +
> + pmx_sw_init: pmx-sw-init {
> + marvell,pins = "mpp7";
> + marvell,function = "gpio";
> + };
> +};
> +
> +&hdd_power {
> + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&usb_power {
> + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
> +};
> +
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index 89bb0fc..793efa9 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -85,8 +85,8 @@ config MACH_LINKSTATION_PRO
> v2 devices are supported.
>
> config MACH_LINKSTATION_LSCHL
> - bool "Buffalo Linkstation Live v3 (LS-CHL)"
> - select I2C_BOARDINFO if I2C
> + bool "Buffalo Linkstation Live v3 (LS-CHL) (Flattened Device Tree)"
> + select ARCH_ORION5X_DT
> help
> Say 'Y' here if you want your kernel to support the
> Buffalo Linkstation Live v3 (LS-CHL) platform.
> diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
> index 4b2502b..ae91872 100644
> --- a/arch/arm/mach-orion5x/Makefile
> +++ b/arch/arm/mach-orion5x/Makefile
> @@ -18,7 +18,6 @@ obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o
> obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o
> obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o
> obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o
> -obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o
>
> obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o
> obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o
> diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
> deleted file mode 100644
> index dfdaa8a..0000000
> --- a/arch/arm/mach-orion5x/ls-chl-setup.c
> +++ /dev/null
> @@ -1,331 +0,0 @@
> -/*
> - * arch/arm/mach-orion5x/ls-chl-setup.c
> - *
> - * Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk>
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/mv643xx_eth.h>
> -#include <linux/leds.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/gpio-fan.h>
> -#include <linux/input.h>
> -#include <linux/i2c.h>
> -#include <linux/ata_platform.h>
> -#include <linux/gpio.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include "common.h"
> -#include "mpp.h"
> -#include "orion5x.h"
> -
> -/*****************************************************************************
> - * Linkstation LS-CHL Info
> - ****************************************************************************/
> -
> -/*
> - * 256K NOR flash Device bus boot chip select
> - */
> -
> -#define LSCHL_NOR_BOOT_BASE 0xf4000000
> -#define LSCHL_NOR_BOOT_SIZE SZ_256K
> -
> -/*****************************************************************************
> - * 256KB NOR Flash on BOOT Device
> - ****************************************************************************/
> -
> -static struct physmap_flash_data lschl_nor_flash_data = {
> - .width = 1,
> -};
> -
> -static struct resource lschl_nor_flash_resource = {
> - .flags = IORESOURCE_MEM,
> - .start = LSCHL_NOR_BOOT_BASE,
> - .end = LSCHL_NOR_BOOT_BASE + LSCHL_NOR_BOOT_SIZE - 1,
> -};
> -
> -static struct platform_device lschl_nor_flash = {
> - .name = "physmap-flash",
> - .id = 0,
> - .dev = {
> - .platform_data = &lschl_nor_flash_data,
> - },
> - .num_resources = 1,
> - .resource = &lschl_nor_flash_resource,
> -};
> -
> -/*****************************************************************************
> - * Ethernet
> - ****************************************************************************/
> -
> -static struct mv643xx_eth_platform_data lschl_eth_data = {
> - .phy_addr = MV643XX_ETH_PHY_ADDR(8),
> -};
> -
> -/*****************************************************************************
> - * RTC 5C372a on I2C bus
> - ****************************************************************************/
> -
> -static struct i2c_board_info __initdata lschl_i2c_rtc = {
> - I2C_BOARD_INFO("rs5c372a", 0x32),
> -};
> -
> -/*****************************************************************************
> - * LEDs attached to GPIO
> - ****************************************************************************/
> -
> -#define LSCHL_GPIO_LED_ALARM 2
> -#define LSCHL_GPIO_LED_INFO 3
> -#define LSCHL_GPIO_LED_FUNC 17
> -#define LSCHL_GPIO_LED_PWR 0
> -
> -static struct gpio_led lschl_led_pins[] = {
> - {
> - .name = "alarm:red",
> - .gpio = LSCHL_GPIO_LED_ALARM,
> - .active_low = 1,
> - }, {
> - .name = "info:amber",
> - .gpio = LSCHL_GPIO_LED_INFO,
> - .active_low = 1,
> - }, {
> - .name = "func:blue:top",
> - .gpio = LSCHL_GPIO_LED_FUNC,
> - .active_low = 1,
> - }, {
> - .name = "power:blue:bottom",
> - .gpio = LSCHL_GPIO_LED_PWR,
> - },
> -};
> -
> -static struct gpio_led_platform_data lschl_led_data = {
> - .leds = lschl_led_pins,
> - .num_leds = ARRAY_SIZE(lschl_led_pins),
> -};
> -
> -static struct platform_device lschl_leds = {
> - .name = "leds-gpio",
> - .id = -1,
> - .dev = {
> - .platform_data = &lschl_led_data,
> - },
> -};
> -
> -/*****************************************************************************
> - * SATA
> - ****************************************************************************/
> -static struct mv_sata_platform_data lschl_sata_data = {
> - .n_ports = 2,
> -};
> -
> -/*****************************************************************************
> - * LS-CHL specific power off method: reboot
> - ****************************************************************************/
> -/*
> - * On the LS-CHL, the shutdown process is following:
> - * - Userland monitors key events until the power switch goes to off position
> - * - The board reboots
> - * - U-boot starts and goes into an idle mode waiting for the user
> - * to move the switch to ON position
> - *
> - */
> -
> -static void lschl_power_off(void)
> -{
> - orion5x_restart(REBOOT_HARD, NULL);
> -}
> -
> -/*****************************************************************************
> - * General Setup
> - ****************************************************************************/
> -#define LSCHL_GPIO_USB_POWER 9
> -#define LSCHL_GPIO_AUTO_POWER 17
> -#define LSCHL_GPIO_POWER 18
> -
> -/****************************************************************************
> - * GPIO Attached Keys
> - ****************************************************************************/
> -#define LSCHL_GPIO_KEY_FUNC 15
> -#define LSCHL_GPIO_KEY_POWER 8
> -#define LSCHL_GPIO_KEY_AUTOPOWER 10
> -#define LSCHL_SW_POWER 0x00
> -#define LSCHL_SW_AUTOPOWER 0x01
> -#define LSCHL_SW_FUNC 0x02
> -
> -static struct gpio_keys_button lschl_buttons[] = {
> - {
> - .type = EV_SW,
> - .code = LSCHL_SW_POWER,
> - .gpio = LSCHL_GPIO_KEY_POWER,
> - .desc = "Power-on Switch",
> - .active_low = 1,
> - }, {
> - .type = EV_SW,
> - .code = LSCHL_SW_AUTOPOWER,
> - .gpio = LSCHL_GPIO_KEY_AUTOPOWER,
> - .desc = "Power-auto Switch",
> - .active_low = 1,
> - }, {
> - .type = EV_SW,
> - .code = LSCHL_SW_FUNC,
> - .gpio = LSCHL_GPIO_KEY_FUNC,
> - .desc = "Function Switch",
> - .active_low = 1,
> - },
> -};
> -
> -static struct gpio_keys_platform_data lschl_button_data = {
> - .buttons = lschl_buttons,
> - .nbuttons = ARRAY_SIZE(lschl_buttons),
> -};
> -
> -static struct platform_device lschl_button_device = {
> - .name = "gpio-keys",
> - .id = -1,
> - .num_resources = 0,
> - .dev = {
> - .platform_data = &lschl_button_data,
> - },
> -};
> -
> -#define LSCHL_GPIO_HDD_POWER 1
> -
> -/****************************************************************************
> - * GPIO Fan
> - ****************************************************************************/
> -
> -#define LSCHL_GPIO_FAN_LOW 16
> -#define LSCHL_GPIO_FAN_HIGH 14
> -#define LSCHL_GPIO_FAN_LOCK 6
> -
> -static struct gpio_fan_alarm lschl_alarm = {
> - .gpio = LSCHL_GPIO_FAN_LOCK,
> -};
> -
> -static struct gpio_fan_speed lschl_speeds[] = {
> - {
> - .rpm = 0,
> - .ctrl_val = 3,
> - }, {
> - .rpm = 1500,
> - .ctrl_val = 2,
> - }, {
> - .rpm = 3250,
> - .ctrl_val = 1,
> - }, {
> - .rpm = 5000,
> - .ctrl_val = 0,
> - },
> -};
> -
> -static int lschl_gpio_list[] = {
> - LSCHL_GPIO_FAN_HIGH, LSCHL_GPIO_FAN_LOW,
> -};
> -
> -static struct gpio_fan_platform_data lschl_fan_data = {
> - .num_ctrl = ARRAY_SIZE(lschl_gpio_list),
> - .ctrl = lschl_gpio_list,
> - .alarm = &lschl_alarm,
> - .num_speed = ARRAY_SIZE(lschl_speeds),
> - .speed = lschl_speeds,
> -};
> -
> -static struct platform_device lschl_fan_device = {
> - .name = "gpio-fan",
> - .id = -1,
> - .num_resources = 0,
> - .dev = {
> - .platform_data = &lschl_fan_data,
> - },
> -};
> -
> -/****************************************************************************
> - * GPIO Data
> - ****************************************************************************/
> -
> -static unsigned int lschl_mpp_modes[] __initdata = {
> - MPP0_GPIO, /* LED POWER */
> - MPP1_GPIO, /* HDD POWER */
> - MPP2_GPIO, /* LED ALARM */
> - MPP3_GPIO, /* LED INFO */
> - MPP4_UNUSED,
> - MPP5_UNUSED,
> - MPP6_GPIO, /* FAN LOCK */
> - MPP7_GPIO, /* SW INIT */
> - MPP8_GPIO, /* SW POWER */
> - MPP9_GPIO, /* USB POWER */
> - MPP10_GPIO, /* SW AUTO POWER */
> - MPP11_UNUSED,
> - MPP12_UNUSED,
> - MPP13_UNUSED,
> - MPP14_GPIO, /* FAN HIGH */
> - MPP15_GPIO, /* SW FUNC */
> - MPP16_GPIO, /* FAN LOW */
> - MPP17_GPIO, /* LED FUNC */
> - MPP18_UNUSED,
> - MPP19_UNUSED,
> - 0,
> -};
> -
> -static void __init lschl_init(void)
> -{
> - /*
> - * Setup basic Orion functions. Needs to be called early.
> - */
> - orion5x_init();
> -
> - orion5x_mpp_conf(lschl_mpp_modes);
> -
> - /*
> - * Configure peripherals.
> - */
> - orion5x_ehci0_init();
> - orion5x_ehci1_init();
> - orion5x_eth_init(&lschl_eth_data);
> - orion5x_i2c_init();
> - orion5x_sata_init(&lschl_sata_data);
> - orion5x_uart0_init();
> - orion5x_xor_init();
> -
> - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
> - ORION_MBUS_DEVBUS_BOOT_ATTR,
> - LSCHL_NOR_BOOT_BASE,
> - LSCHL_NOR_BOOT_SIZE);
> - platform_device_register(&lschl_nor_flash);
> -
> - platform_device_register(&lschl_leds);
> -
> - platform_device_register(&lschl_button_device);
> -
> - platform_device_register(&lschl_fan_device);
> -
> - i2c_register_board_info(0, &lschl_i2c_rtc, 1);
> -
> - /* usb power on */
> - gpio_set_value(LSCHL_GPIO_USB_POWER, 1);
> -
> - /* register power-off method */
> - pm_power_off = lschl_power_off;
> -
> - pr_info("%s: finished\n", __func__);
> -}
> -
> -MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
> - /* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */
> - .atag_offset = 0x100,
> - .nr_irqs = ORION5X_NR_IRQS,
> - .init_machine = lschl_init,
> - .map_io = orion5x_map_io,
> - .init_early = orion5x_init_early,
> - .init_irq = orion5x_init_irq,
> - .init_time = orion5x_timer_init,
> - .fixup = tag_fixup_mem32,
> - .restart = orion5x_restart,
> -MACHINE_END
> -- 2.7.4
>
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 2/3] ARM: cache-uniphier: refactor jump label to follow coding style guideline
From: Masahiro Yamada @ 2016-11-04 12:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161104122322.GB1041@n2100.armlinux.org.uk>
Hi Russell,
2016-11-04 21:23 GMT+09:00 Russell King - ARM Linux <linux@armlinux.org.uk>:
> On Fri, Nov 04, 2016 at 08:43:35PM +0900, Masahiro Yamada wrote:
>> Documentation/CodingStyle recommends to use label names which say
>> what the goto does or why the goto exists.
>>
>> Just in case, split it up into three labels because the CodingStyle
>> says "one err bugs" is a common type of bug (although, I do not
>> believe the current code includes such a bug).
>
> However, this has the effect of making the code unnecessarily more
> complicated, which is a bad thing. Avoiding unnecessary code
> complexity wins over style rules.
I thought this patch is stupid, but makes the code more straight-forward;
the failure path only calls really needed iounmap/kfree()
without exploiting that NULL input makes them no-op.
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [1/4] ARM: EXYNOS: Remove smp_init_cpus hook from platsmp.c
From: Alim Akhtar @ 2016-11-04 12:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478230764-13748-2-git-send-email-pankaj.dubey@samsung.com>
Hi Pankaj,
On 11/04/2016 09:09 AM, Pankaj Dubey wrote:
> We can safely remove exynos_smp_init_cpus() hook from mach-exynos/platsmp.c,
> as all SMP platforms in mach-exynos can rely on DT for CPU core description
> instead of determining number of cores from the SCU.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
Looks good.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> arch/arm/mach-exynos/platsmp.c | 31 -------------------------------
> 1 file changed, 31 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index 98ffe1e..a5d6841 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -385,36 +385,6 @@ fail:
> return pen_release != -1 ? ret : 0;
> }
>
> -/*
> - * Initialise the CPU possible map early - this describes the CPUs
> - * which may be present or become present in the system.
> - */
> -
> -static void __init exynos_smp_init_cpus(void)
> -{
> - void __iomem *scu_base = scu_base_addr();
> - unsigned int i, ncores;
> -
> - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
> - ncores = scu_base ? scu_get_core_count(scu_base) : 1;
> - else
> - /*
> - * CPU Nodes are passed thru DT and set_cpu_possible
> - * is set by "arm_dt_init_cpu_maps".
> - */
> - return;
> -
> - /* sanity check */
> - if (ncores > nr_cpu_ids) {
> - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
> - ncores, nr_cpu_ids);
> - ncores = nr_cpu_ids;
> - }
> -
> - for (i = 0; i < ncores; i++)
> - set_cpu_possible(i, true);
> -}
> -
> static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
> {
> int i;
> @@ -479,7 +449,6 @@ static void exynos_cpu_die(unsigned int cpu)
> #endif /* CONFIG_HOTPLUG_CPU */
>
> const struct smp_operations exynos_smp_ops __initconst = {
> - .smp_init_cpus = exynos_smp_init_cpus,
> .smp_prepare_cpus = exynos_smp_prepare_cpus,
> .smp_secondary_init = exynos_secondary_init,
> .smp_boot_secondary = exynos_boot_secondary,
>
^ permalink raw reply
* [PATCH] bus: vexpress-config: fix device reference leak
From: Johan Hovold @ 2016-11-04 13:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478259746.17152.126.camel@arm.com>
On Fri, Nov 04, 2016 at 11:42:26AM +0000, Pawel Moll wrote:
> On Tue, 2016-11-01 at 11:43 +0100, Johan Hovold wrote:
> > Make sure to drop the reference to the parent device taken by
> > class_find_device() after populating the bus.
> >
> > Fixes: 3b9334ac835b ("mfd: vexpress: Convert custom func API to
> > regmap")
> > Signed-off-by: Johan Hovold <johan@kernel.org>
>
> You're right. May I ask how did you figure it out? The get_device()
> happening in class_find_device() is a bit obscure, so have you simply
> followed places where it's being used or used some static (?) analysis
> tool? If the latter, I'd be very curios to hear what was it :-)
I stumbled over one of these leaks and grepped and searched for more.
I've submitted a few patches this week fixing some of the more obvious
ones, but there are more lurking behind various subsystem wrappers.
Thanks,
Johan
^ permalink raw reply
* [PATCH v3 1/6] arm64: arch_timer: Add device tree binding for hisilicon-161601 erratum
From: Ding Tianhong @ 2016-11-04 13:06 UTC (permalink / raw)
To: linux-arm-kernel
This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward. So, describe it
in the device tree.
v2: Use the new erratum name and update the description.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ef5fbe9..c27b2c4 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,14 @@ to deliver its interrupts via SPIs.
This also affects writes to the tval register, due to the implicit
counter read.
+- hisilicon,erratum-161601 : A boolean property. Indicates the presence of
+ erratum 161601, which says that reading the counter is unreliable unless
+ reading twice on the register and the value of the second read is larger
+ than the first by less than 32. If the verification is unsuccessful, then
+ discard the value of this read and repeat this procedure until the verification
+ is successful. This also affects writes to the tval register, due to the
+ implicit counter read.
+
** Optional properties:
- arm,cpu-registers-not-fw-configured : Firmware does not initialize
--
1.9.0
^ permalink raw reply related
* [PATCH v3 2/6] arm64: arch_timer: Introduce a generic erratum handing mechanism for fsl-a008585
From: Ding Tianhong @ 2016-11-04 13:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478264794-14652-1-git-send-email-dingtianhong@huawei.com>
The workaround for hisilicon,161601 will check the return value of the system counter
by different way, in order to distinguish with the fsl-a008585 workaround, introduce
a new generic erratum handing mechanism for fsl-a008585 and rename some functions.
v2: Introducing a new generic erratum handling mechanism for fsl erratum a008585.
v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585
and make the #define __fsl_a008585_read_reg to be private to the .c file instead of
being globally visible. After discussion with Marc and Will, a consensus decision was
made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum,
and make some generic name more specific, export timer_unstable_counter_workaround
for module access.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
Documentation/kernel-parameters.txt | 9 -----
arch/arm64/include/asm/arch_timer.h | 36 ++++++-----------
drivers/clocksource/arm_arch_timer.c | 78 +++++++++++++++++++++---------------
3 files changed, 58 insertions(+), 65 deletions(-)
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 6fa1d8a..738de4e 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -698,15 +698,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
loops can be debugged more effectively on production
systems.
- clocksource.arm_arch_timer.fsl-a008585=
- [ARM64]
- Format: <bool>
- Enable/disable the workaround of Freescale/NXP
- erratum A-008585. This can be useful for KVM
- guests, if the guest device tree doesn't show the
- erratum. If unspecified, the workaround is
- enabled based on the device tree.
-
clearcpuid=BITNUM [X86]
Disable CPUID feature X for the kernel. See
arch/x86/include/asm/cpufeatures.h for the valid bit
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index eaa5bbe..f882c7c 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -31,39 +31,27 @@
#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
extern struct static_key_false arch_timer_read_ool_enabled;
-#define needs_fsl_a008585_workaround() \
+#define needs_unstable_timer_counter_workaround() \
static_branch_unlikely(&arch_timer_read_ool_enabled)
#else
-#define needs_fsl_a008585_workaround() false
+#define needs_unstable_timer_counter_workaround() false
#endif
-u32 __fsl_a008585_read_cntp_tval_el0(void);
-u32 __fsl_a008585_read_cntv_tval_el0(void);
-u64 __fsl_a008585_read_cntvct_el0(void);
-/*
- * The number of retries is an arbitrary value well beyond the highest number
- * of iterations the loop has been observed to take.
- */
-#define __fsl_a008585_read_reg(reg) ({ \
- u64 _old, _new; \
- int _retries = 200; \
- \
- do { \
- _old = read_sysreg(reg); \
- _new = read_sysreg(reg); \
- _retries--; \
- } while (unlikely(_old != _new) && _retries); \
- \
- WARN_ON_ONCE(!_retries); \
- _new; \
-})
+struct arch_timer_erratum_workaround {
+ int erratum; /* Indicate the Erratum ID */
+ u32 (*read_cntp_tval_el0)(void);
+ u32 (*read_cntv_tval_el0)(void);
+ u64 (*read_cntvct_el0)(void);
+};
+
+extern struct arch_timer_erratum_workaround *timer_unstable_counter_workaround;
#define arch_timer_reg_read_stable(reg) \
({ \
u64 _val; \
- if (needs_fsl_a008585_workaround()) \
- _val = __fsl_a008585_read_##reg(); \
+ if (needs_unstable_timer_counter_workaround()) \
+ _val = timer_unstable_counter_workaround->read_##reg();\
else \
_val = read_sysreg(reg); \
_val; \
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 73c487d..696386f 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -95,40 +95,53 @@ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
*/
#ifdef CONFIG_FSL_ERRATUM_A008585
-DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
-EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
-
-static int fsl_a008585_enable = -1;
+struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
+EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
-static int __init early_fsl_a008585_cfg(char *buf)
-{
- int ret;
- bool val;
+#define FSL_A008585 0x0001
- ret = strtobool(buf, &val);
- if (ret)
- return ret;
-
- fsl_a008585_enable = val;
- return 0;
-}
-early_param("clocksource.arm_arch_timer.fsl-a008585", early_fsl_a008585_cfg);
+DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
+EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
-u32 __fsl_a008585_read_cntp_tval_el0(void)
+/*
+ * The number of retries is an arbitrary value well beyond the highest number
+ * of iterations the loop has been observed to take.
+ */
+#define __fsl_a008585_read_reg(reg) ({ \
+ u64 _old, _new; \
+ int _retries = 200; \
+ \
+ do { \
+ _old = read_sysreg(reg); \
+ _new = read_sysreg(reg); \
+ _retries--; \
+ } while (unlikely(_old != _new) && _retries); \
+ \
+ WARN_ON_ONCE(!_retries); \
+ _new; \
+})
+
+static u32 fsl_a008585_read_cntp_tval_el0(void)
{
return __fsl_a008585_read_reg(cntp_tval_el0);
}
-u32 __fsl_a008585_read_cntv_tval_el0(void)
+static u32 fsl_a008585_read_cntv_tval_el0(void)
{
return __fsl_a008585_read_reg(cntv_tval_el0);
}
-u64 __fsl_a008585_read_cntvct_el0(void)
+static u64 fsl_a008585_read_cntvct_el0(void)
{
return __fsl_a008585_read_reg(cntvct_el0);
}
-EXPORT_SYMBOL(__fsl_a008585_read_cntvct_el0);
+
+static struct arch_timer_erratum_workaround arch_timer_fsl_a008585 = {
+ .erratum = FSL_A008585,
+ .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
+ .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
+};
#endif /* CONFIG_FSL_ERRATUM_A008585 */
static __always_inline
@@ -281,7 +294,7 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
}
#ifdef CONFIG_FSL_ERRATUM_A008585
-static __always_inline void fsl_a008585_set_next_event(const int access,
+static __always_inline void erratum_set_next_event_generic(const int access,
unsigned long evt, struct clock_event_device *clk)
{
unsigned long ctrl;
@@ -299,17 +312,17 @@ static __always_inline void fsl_a008585_set_next_event(const int access,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-static int fsl_a008585_set_next_event_virt(unsigned long evt,
+static int erratum_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
+ erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
return 0;
}
-static int fsl_a008585_set_next_event_phys(unsigned long evt,
+static int erratum_set_next_event_phys(unsigned long evt,
struct clock_event_device *clk)
{
- fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
+ erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
return 0;
}
#endif /* CONFIG_FSL_ERRATUM_A008585 */
@@ -342,16 +355,16 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
return 0;
}
-static void fsl_a008585_set_sne(struct clock_event_device *clk)
+static void erratum_workaround_set_sne(struct clock_event_device *clk)
{
#ifdef CONFIG_FSL_ERRATUM_A008585
if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
return;
if (arch_timer_uses_ppi == VIRT_PPI)
- clk->set_next_event = fsl_a008585_set_next_event_virt;
+ clk->set_next_event = erratum_set_next_event_virt;
else
- clk->set_next_event = fsl_a008585_set_next_event_phys;
+ clk->set_next_event = erratum_set_next_event_phys;
#endif
}
@@ -384,7 +397,7 @@ static void __arch_timer_setup(unsigned type,
BUG();
}
- fsl_a008585_set_sne(clk);
+ erratum_workaround_set_sne(clk);
} else {
clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
clk->name = "arch_mem_timer";
@@ -891,9 +904,10 @@ static int __init arch_timer_of_init(struct device_node *np)
arch_timer_c3stop = !of_property_read_bool(np, "always-on");
#ifdef CONFIG_FSL_ERRATUM_A008585
- if (fsl_a008585_enable < 0)
- fsl_a008585_enable = of_property_read_bool(np, "fsl,erratum-a008585");
- if (fsl_a008585_enable) {
+ if (!timer_unstable_counter_workaround && of_property_read_bool(np, "fsl,erratum-a008585"))
+ timer_unstable_counter_workaround = &arch_timer_fsl_a008585;
+
+ if (timer_unstable_counter_workaround) {
static_branch_enable(&arch_timer_read_ool_enabled);
pr_info("Enabling workaround for FSL erratum A-008585\n");
}
--
1.9.0
^ permalink raw reply related
* [PATCH v3 3/6] arm64: arch_timer: Work around Erratum Hisilicon-161601
From: Ding Tianhong @ 2016-11-04 13:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478264794-14652-1-git-send-email-dingtianhong@huawei.com>
Erratum Hisilicon-161601 says that the ARM generic timer counter "has the
potential to contain an erroneous value when the timer value changes".
Accesses to TVAL (both read and write) are also affected due to the implicit counter
read. Accesses to CVAL are not affected.
The workaround is to reread the system count registers until the value of the second
read is larger than the first one by less than 32, the system counter can be guaranteed
not to return wrong value twice by back-to-back read and the error value is always larger
than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
The workaround is enabled if the hisilicon,erratum-161601 property is found in
the timer node in the device tree. This can be overridden with the
clocksource.arm_arch_timer.hisilicon-161601 boot parameter, which allows KVM
users to enable the workaround until a mechanism is implemented to
automatically communicate this information.
Fix some description for fsl erratum a008585.
v2: Significant rework based on feedback, including seperate the fsl erratum a008585
to another patch, update the erratum name and remove unwanted code.
v3: Significant rework based on feedback, including fix some alignment problem, make the
#define __hisi_161601_read_reg to be private to the .c file instead of being globally
visible, add more accurate annotation and modify a bit of logical format to enable
arch_timer_read_ool_enabled, remove the kernel commandline parameter
clocksource.arm_arch_timer.hisilicon-161601.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/include/asm/arch_timer.h | 2 +-
drivers/clocksource/Kconfig | 9 +++++
drivers/clocksource/arm_arch_timer.c | 67 +++++++++++++++++++++++++++++++---
4 files changed, 73 insertions(+), 6 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 405da11..1c1a95f 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -63,3 +63,4 @@ stable kernels.
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
+| Hisilicon | Hip0{5,6,7} | #161601 | HISILICON_ERRATUM_161601|
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index f882c7c..ebf4cde 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -29,7 +29,7 @@
#include <clocksource/arm_arch_timer.h>
-#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
extern struct static_key_false arch_timer_read_ool_enabled;
#define needs_unstable_timer_counter_workaround() \
static_branch_unlikely(&arch_timer_read_ool_enabled)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8a753fd..6c03ed0 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -315,6 +315,15 @@ config FSL_ERRATUM_A008585
value"). The workaround will only be active if the
fsl,erratum-a008585 property is found in the timer node.
+config HISILICON_ERRATUM_161601
+ bool "Workaround for Hisilicon Erratum 161601"
+ default y
+ depends on ARM_ARCH_TIMER && ARM64
+ help
+ This option enables a workaround for Hisilicon Erratum
+ 161601. The workaround will be active if the hisilicon,erratum-161601
+ property is found in the timer node.
+
config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST
select CLKSRC_OF if OF
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 696386f..3d59af1 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -94,15 +94,18 @@ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
* Architected system timer support.
*/
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if CONFIG_FSL_ERRATUM_A008585 || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
#define FSL_A008585 0x0001
+#define HISILICON_161601 0x0002
DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
+#endif
+#ifdef CONFIG_FSL_ERRATUM_A008585
/*
* The number of retries is an arbitrary value well beyond the highest number
* of iterations the loop has been observed to take.
@@ -144,6 +147,51 @@ static struct arch_timer_erratum_workaround arch_timer_fsl_a008585 = {
};
#endif /* CONFIG_FSL_ERRATUM_A008585 */
+#ifdef CONFIG_HISILICON_ERRATUM_161601
+/*
+ * Theoretically the erratum should not occur more than twice in succession,
+ * so set the retry count to 2 is sufficient here.
+ * Verify whether the value of the second read is larger than the first by
+ * less than 32 is the only way to confirm the value is correct, so clear the
+ * lower 5 bits to check whether the difference is greater than 32 or not.
+ */
+#define __hisi_161601_read_reg(reg) ({ \
+ u64 _old, _new; \
+ int _retries = 2; \
+ \
+ do { \
+ _old = read_sysreg(reg); \
+ _new = read_sysreg(reg); \
+ _retries--; \
+ } while (unlikely((_new - _old) >> 5) && _retries); \
+ \
+ WARN_ON_ONCE(!_retries); \
+ _new; \
+})
+
+static u32 hisi_161601_read_cntp_tval_el0(void)
+{
+ return __hisi_161601_read_reg(cntp_tval_el0);
+}
+
+static u32 hisi_161601_read_cntv_tval_el0(void)
+{
+ return __hisi_161601_read_reg(cntv_tval_el0);
+}
+
+static u64 hisi_161601_read_cntvct_el0(void)
+{
+ return __hisi_161601_read_reg(cntvct_el0);
+}
+
+static struct arch_timer_erratum_workaround arch_timer_hisi_161601 = {
+ .erratum = HISILICON_161601,
+ .read_cntp_tval_el0 = hisi_161601_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = hisi_161601_read_cntv_tval_el0,
+ .read_cntvct_el0 = hisi_161601_read_cntvct_el0,
+};
+#endif /* CONFIG_HISILICON_ERRATUM_161601 */
+
static __always_inline
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
struct clock_event_device *clk)
@@ -293,7 +341,7 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
static __always_inline void erratum_set_next_event_generic(const int access,
unsigned long evt, struct clock_event_device *clk)
{
@@ -357,7 +405,7 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
static void erratum_workaround_set_sne(struct clock_event_device *clk)
{
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
return;
@@ -617,7 +665,7 @@ static void __init arch_counter_register(unsigned type)
clocksource_counter.archdata.vdso_direct = true;
-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
/*
* Don't use the vdso fastpath if errata require using
* the out-of-line counter accessor.
@@ -906,10 +954,19 @@ static int __init arch_timer_of_init(struct device_node *np)
#ifdef CONFIG_FSL_ERRATUM_A008585
if (!timer_unstable_counter_workaround && of_property_read_bool(np, "fsl,erratum-a008585"))
timer_unstable_counter_workaround = &arch_timer_fsl_a008585;
+#endif
+
+#ifdef CONFIG_HISILICON_ERRATUM_161601
+ if (!timer_unstable_counter_workaround && of_property_read_bool(np, "hisilicon,erratum-161601"))
+ timer_unstable_counter_workaround = &arch_timer_hisi_161601;
+#endif
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
if (timer_unstable_counter_workaround) {
static_branch_enable(&arch_timer_read_ool_enabled);
- pr_info("Enabling workaround for FSL erratum A-008585\n");
+ pr_info("Enabling workaround for %s\n",
+ timer_unstable_counter_workaround->erratum == FSL_A008585 ?
+ "FSL ERRATUM A-008585" : "HISILICON ERRATUM 161601");
}
#endif
--
1.9.0
^ permalink raw reply related
* [PATCH v3 4/6] arm64: arch timer: Add timer erratum property for Hip05-d02 and Hip06-d03
From: Ding Tianhong @ 2016-11-04 13:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478264794-14652-1-git-send-email-dingtianhong@huawei.com>
Enable workaround for hisilicon erratum 161601 on Hip05-d02 and Hip06-d03 board.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 1 +
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index bf322ed..f815d94 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -281,6 +281,7 @@
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ hisilicon,erratum-161601;
};
pmu {
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 5927bc4..d63990b 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -260,6 +260,7 @@
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ hisilicon,erratum-161601;
};
pmu {
--
1.9.0
^ permalink raw reply related
* [PATCH v3 5/6] arm64: arch_timer: apci: Introduce a generic aquirk framework for erratum
From: Ding Tianhong @ 2016-11-04 13:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478264794-14652-1-git-send-email-dingtianhong@huawei.com>
From: Hanjun Guo <hanjun.guo@linaro.org>
Introduce a general quirk framework for each timer erratum in ACPI,
which use the oem information in GTDT table for platform specific erratums.
The struct gtdt_arch_timer_fixup is introduced to record the oem
information to match the quirk and handle the erratum.
v3: Introduce a generic aquick framework for erratum in ACPI mode.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
drivers/clocksource/arm_arch_timer.c | 37 ++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 3d59af1..9bc93e5 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -1068,6 +1068,40 @@ CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
arch_timer_mem_init);
#ifdef CONFIG_ACPI
+struct gtdt_arch_timer_fixup {
+ char oem_id[ACPI_OEM_ID_SIZE];
+ char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
+ u32 oem_revision;
+
+ /* quirk handler for arch timer erratum */
+ void (*handler)(u32 erratum);
+ u32 erratum;
+};
+
+/* note: this needs to be updated according to the doc of OEM ID
+ * and TABLE ID for different board.
+ */
+struct gtdt_arch_timer_fixup arch_timer_quirks[] __initdata = {
+};
+
+void __init arch_timer_acpi_quirks_handler(char *oem_id,
+ char *oem_table_id,
+ u32 oem_revision)
+{
+ struct gtdt_arch_timer_fixup *quirks = arch_timer_quirks;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(arch_timer_quirks); i++, quirks++) {
+ if (!memcmp(quirks->oem_id, oem_id, ACPI_OEM_ID_SIZE) &&
+ !memcmp(quirks->oem_table_id, oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
+ quirks->oem_revision == oem_revision) {
+ if (quirks->handler && quirks->erratum)
+ quirks->handler(quirks->erratum);
+ break;
+ }
+ }
+}
+
static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
{
int trigger, polarity;
@@ -1094,6 +1128,9 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
return -EINVAL;
}
+ arch_timer_acpi_quirks_handler(table->oem_id, table->oem_table_id,
+ table->oem_revision);
+
gtdt = container_of(table, struct acpi_table_gtdt, header);
arch_timers_present |= ARCH_CP15_TIMER;
--
1.9.0
^ permalink raw reply related
* [PATCH v3 6/6] arm64: arch_timer: acpi: add hisi timer errata data
From: Ding Tianhong @ 2016-11-04 13:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478264794-14652-1-git-send-email-dingtianhong@huawei.com>
From: Hanjun Guo <hanjun.guo@linaro.org>
Add hisi timer specific erratum fixes.
v3: add hisilicon erratum 161601 for ACPI mode.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
drivers/clocksource/arm_arch_timer.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 9bc93e5..270d179 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -1078,10 +1078,26 @@ struct gtdt_arch_timer_fixup {
u32 erratum;
};
+#ifdef CONFIG_HISILICON_ERRATUM_161601
+static void __init erratum_workaround_enable(u32 erratum)
+{
+ if (erratum & HISILICON_161601) {
+ timer_unstable_counter_workaround = &arch_timer_hisi_161601;
+ static_branch_enable(&arch_timer_read_ool_enabled);
+ pr_info("Enabling workaround for HISILICON ERRATUM 161601\n");
+ }
+}
+#endif
+
/* note: this needs to be updated according to the doc of OEM ID
* and TABLE ID for different board.
*/
struct gtdt_arch_timer_fixup arch_timer_quirks[] __initdata = {
+#ifdef CONFIG_HISILICON_ERRATUM_161601
+ {"HISI", "hip05", 0, &erratum_workaround_enable, HISILICON_161601},
+ {"HISI", "hip06", 0, &erratum_workaround_enable, HISILICON_161601},
+ {"HISI", "hip07", 0, &erratum_workaround_enable, HISILICON_161601},
+#endif
};
void __init arch_timer_acpi_quirks_handler(char *oem_id,
--
1.9.0
^ permalink raw reply related
* [2/4] ARM: dts: exynos: Add SCU device node to exynos4.dtsi
From: Alim Akhtar @ 2016-11-04 13:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478230764-13748-3-git-send-email-pankaj.dubey@samsung.com>
Hi Pankaj,
On 11/04/2016 09:09 AM, Pankaj Dubey wrote:
> Exynos4 like other Cortex-A9 SoC's has a Snoop Control Unit(SCU)
> and its SFR are used during SMP boot and S2R. Add SCU node to the device tree.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> arch/arm/boot/dts/exynos4.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> index 5f034eb..6865ca9 100644
> --- a/arch/arm/boot/dts/exynos4.dtsi
> +++ b/arch/arm/boot/dts/exynos4.dtsi
> @@ -78,6 +78,11 @@
> reg = <0x10000000 0x100>;
> };
>
> + scu: snoop-control-unit at 10500000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0x10500000 0x2000>;
> + };
> +
> memory-controller at 12570000 {
> compatible = "samsung,exynos4210-srom";
> reg = <0x12570000 0x14>;
>
^ permalink raw reply
* [3/4] ARM: EXYNOS: Remove static mapping of SCU SFR
From: Alim Akhtar @ 2016-11-04 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478230764-13748-4-git-send-email-pankaj.dubey@samsung.com>
Hi Pankaj,
On 11/04/2016 09:09 AM, Pankaj Dubey wrote:
> Lets remove static mapping of SCU SFR mainly used in CORTEX-A9 SoC based boards.
> Instead use mapping from device tree node of SCU.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
> arch/arm/mach-exynos/exynos.c | 22 ----------------------
> arch/arm/mach-exynos/include/mach/map.h | 2 --
> arch/arm/mach-exynos/platsmp.c | 18 +++++++++++-------
> arch/arm/mach-exynos/pm.c | 14 +++++++++++---
> arch/arm/mach-exynos/suspend.c | 15 +++++++++++----
> arch/arm/plat-samsung/include/plat/map-s5p.h | 4 ----
> 6 files changed, 33 insertions(+), 42 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index 757fc11..fa08ef9 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -28,15 +28,6 @@
>
> #include "common.h"
>
> -static struct map_desc exynos4_iodesc[] __initdata = {
> - {
> - .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
> - .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
> - .length = SZ_8K,
> - .type = MT_DEVICE,
> - },
> -};
> -
> static struct platform_device exynos_cpuidle = {
> .name = "exynos_cpuidle",
> #ifdef CONFIG_ARM_EXYNOS_CPUIDLE
> @@ -99,17 +90,6 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
> return 1;
> }
>
> -/*
> - * exynos_map_io
> - *
> - * register the standard cpu IO areas
> - */
> -static void __init exynos_map_io(void)
> -{
> - if (soc_is_exynos4())
> - iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
> -}
> -
> static void __init exynos_init_io(void)
> {
> debug_ll_io_init();
> @@ -118,8 +98,6 @@ static void __init exynos_init_io(void)
>
> /* detect cpu id and rev. */
> s5p_init_cpu(S5P_VA_CHIPID);
> -
> - exynos_map_io();
> }
>
> /*
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 5fb0040..0eef407 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -18,6 +18,4 @@
>
> #define EXYNOS_PA_CHIPID 0x10000000
>
> -#define EXYNOS4_PA_COREPERI 0x10500000
> -
> #endif /* __ASM_ARCH_MAP_H */
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index a5d6841..553d0d9 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -224,11 +224,6 @@ static void write_pen_release(int val)
> sync_cache_w(&pen_release);
> }
>
> -static void __iomem *scu_base_addr(void)
> -{
> - return (void __iomem *)(S5P_VA_SCU);
> -}
> -
> static DEFINE_SPINLOCK(boot_lock);
>
> static void exynos_secondary_init(unsigned int cpu)
> @@ -387,14 +382,23 @@ fail:
>
> static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
> {
> + struct device_node *np;
> + void __iomem *scu_base;
> int i;
>
> exynos_sysram_init();
>
> exynos_set_delayed_reset_assertion(true);
>
> - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
> - scu_enable(scu_base_addr());
> + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
> + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
what if of_find_compatible_node() fails? May be add a error check for
the same?
> + scu_base = of_iomap(np, 0);
> + if (scu_base) {
> + scu_enable(scu_base);
> + iounmap(scu_base);
> + }
> + of_node_put(np);
> + }
>
> /*
> * Write the address of secondary startup into the
> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
> index 487295f..60e6827 100644
> --- a/arch/arm/mach-exynos/pm.c
> +++ b/arch/arm/mach-exynos/pm.c
> @@ -18,6 +18,7 @@
> #include <linux/cpu_pm.h>
> #include <linux/io.h>
> #include <linux/of.h>
> +#include <linux/of_address.h>
> #include <linux/soc/samsung/exynos-regs-pmu.h>
> #include <linux/soc/samsung/exynos-pmu.h>
>
> @@ -26,8 +27,6 @@
> #include <asm/suspend.h>
> #include <asm/cacheflush.h>
>
> -#include <mach/map.h>
> -
> #include "common.h"
>
> static inline void __iomem *exynos_boot_vector_addr(void)
> @@ -158,6 +157,8 @@ static int exynos_aftr_finisher(unsigned long flags)
>
> void exynos_enter_aftr(void)
> {
> + struct device_node *np;
> + void __iomem *scu_base;
> unsigned int cpuid = smp_processor_id();
>
> cpu_pm_enter();
> @@ -177,7 +178,14 @@ void exynos_enter_aftr(void)
> cpu_suspend(0, exynos_aftr_finisher);
>
> if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
> - scu_enable(S5P_VA_SCU);
> + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
same as above
> + scu_base = of_iomap(np, 0);
> + if (scu_base) {
> + scu_enable(scu_base);
> + iounmap(scu_base);
> + }
> + of_node_put(np);
> +
> if (call_firmware_op(resume) == -ENOSYS)
> exynos_cpu_restore_register();
> }
> diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
> index 06332f6..7ab7e67 100644
> --- a/arch/arm/mach-exynos/suspend.c
> +++ b/arch/arm/mach-exynos/suspend.c
> @@ -34,8 +34,6 @@
> #include <asm/smp_scu.h>
> #include <asm/suspend.h>
>
> -#include <mach/map.h>
> -
> #include <plat/pm-common.h>
>
> #include "common.h"
> @@ -453,6 +451,8 @@ static void exynos_pm_release_retention(void)
>
> static void exynos_pm_resume(void)
> {
> + struct device_node *np;
> + void __iomem *scu_base;
> u32 cpuid = read_cpuid_part();
>
> if (exynos_pm_central_resume())
> @@ -461,8 +461,15 @@ static void exynos_pm_resume(void)
> /* For release retention */
> exynos_pm_release_retention();
>
> - if (cpuid == ARM_CPU_PART_CORTEX_A9)
> - scu_enable(S5P_VA_SCU);
> + if (cpuid == ARM_CPU_PART_CORTEX_A9) {
> + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
and here otherwise patch looks good.
> + scu_base = of_iomap(np, 0);
> + if (scu_base) {
> + scu_enable(scu_base);
> + iounmap(scu_base);
> + }
> + of_node_put(np);
> + }
>
> if (call_firmware_op(resume) == -ENOSYS
> && cpuid == ARM_CPU_PART_CORTEX_A9)
> diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
> index 0fe2828..512ed1f 100644
> --- a/arch/arm/plat-samsung/include/plat/map-s5p.h
> +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
> @@ -15,10 +15,6 @@
>
> #define S5P_VA_CHIPID S3C_ADDR(0x02000000)
>
> -#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
> -#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
> -#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
> -
> #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
> #define VA_VIC0 VA_VIC(0)
> #define VA_VIC1 VA_VIC(1)
>
^ permalink raw reply
* [4/4] ARM: EXYNOS: Remove unused soc_is_exynos{4,5}
From: Alim Akhtar @ 2016-11-04 13:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478230764-13748-5-git-send-email-pankaj.dubey@samsung.com>
Hi Pankaj,
On 11/04/2016 09:09 AM, Pankaj Dubey wrote:
> As no more user of soc_is_exynos{4,5} we can safely remove them.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Also I have complied tested this series, looks good.
> arch/arm/mach-exynos/common.h | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index 9424a8a..d19064b 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -105,11 +105,6 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
> # define soc_is_exynos5800() 0
> #endif
>
> -#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
> - soc_is_exynos4412())
> -#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
> - soc_is_exynos5420() || soc_is_exynos5800())
> -
> extern u32 cp15_save_diag;
> extern u32 cp15_save_power;
>
>
^ permalink raw reply
* [PATCH v6 7/7] arm64: dts: NS2: add AMAC ethernet support
From: Sergei Shtylyov @ 2016-11-04 13:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478236262-3351-8-git-send-email-jon.mason@broadcom.com>
Hello.
On 11/4/2016 8:11 AM, Jon Mason wrote:
> Add support for the AMAC ethernet to the Broadcom Northstar2 SoC device
> tree
>
> Signed-off-by: Jon Mason <jon.mason@broadcom.com>
> ---
> arch/arm64/boot/dts/broadcom/ns2-svk.dts | 5 +++++
> arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 ++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
> index b09f3bc..c4d5442 100644
> --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
> +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
> @@ -56,6 +56,10 @@
> };
> };
>
> +&enet {
> + status = "ok";
The spec dictates it should be "okay" (although "ok" is also recognized).
> +};
> +
> &pci_phy0 {
> status = "ok";
> };
> @@ -174,6 +178,7 @@
> &mdio_mux_iproc {
> mdio at 10 {
> gphy0: eth-phy at 10 {
> + enet-phy-lane-swap;
> reg = <0x10>;
> };
> };
[...]
MBR, Sergei
^ permalink raw reply
* [PATCH 2/3] ARM: cache-uniphier: refactor jump label to follow coding style guideline
From: Russell King - ARM Linux @ 2016-11-04 13:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK7LNAQKCW2tDXEia7qZ+d9Xy1_ccHSGCat4=w+nfyHiuTHy6w@mail.gmail.com>
On Fri, Nov 04, 2016 at 09:50:56PM +0900, Masahiro Yamada wrote:
> Hi Russell,
>
> 2016-11-04 21:23 GMT+09:00 Russell King - ARM Linux <linux@armlinux.org.uk>:
> > On Fri, Nov 04, 2016 at 08:43:35PM +0900, Masahiro Yamada wrote:
> >> Documentation/CodingStyle recommends to use label names which say
> >> what the goto does or why the goto exists.
> >>
> >> Just in case, split it up into three labels because the CodingStyle
> >> says "one err bugs" is a common type of bug (although, I do not
> >> believe the current code includes such a bug).
> >
> > However, this has the effect of making the code unnecessarily more
> > complicated, which is a bad thing. Avoiding unnecessary code
> > complexity wins over style rules.
>
>
> I thought this patch is stupid, but makes the code more straight-forward;
> the failure path only calls really needed iounmap/kfree()
> without exploiting that NULL input makes them no-op.
... while making it more fragile, because we're going back to a
situation where the right places need to jump to the right label
in the cleanup, so that the right functions are called.
This is a backwards step.
The reason that iounmap() and kfree() check for NULL pointers is to
allow the cleanup paths to be simple, and that's very important as
many cleanup paths are simply _not_ tested.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH] ARM: gr8: evb: Enable SPDIF
From: Maxime Ripard @ 2016-11-04 13:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v67D4mxEP87acuTKgQe8Md1NZyvmQD6+XnL72xqtztFWLg@mail.gmail.com>
On Fri, Nov 04, 2016 at 06:41:05PM +0800, Chen-Yu Tsai wrote:
> On Thu, Nov 3, 2016 at 8:41 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The GR8-EVB has a SPDIF out connector. Enable it.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [RFC v2 4/8] iommu: Add a list of iommu_reserved_region in iommu_domain
From: Robin Murphy @ 2016-11-04 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478258646-3117-5-git-send-email-eric.auger@redhat.com>
Hi Eric,
Thanks for posting this new series - the bottom-up approach is a lot
easier to reason about :)
On 04/11/16 11:24, Eric Auger wrote:
> Introduce a new iommu_reserved_region struct. This embodies
> an IOVA reserved region that cannot be used along with the IOMMU
> API. The list is protected by a dedicated mutex.
In the light of these patches, I think I'm settling into agreement that
the iommu_domain is the sweet spot for accessing this information - the
underlying magic address ranges might be properties of various bits of
hardware many of which aren't the IOMMU itself, but they only start to
matter at the point you start wanting to use an IOMMU domain at the
higher level. Therefore, having a callback in the domain ops to pull
everything together fits rather neatly.
>
> An iommu domain now owns a list of those.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> ---
> ---
> drivers/iommu/iommu.c | 2 ++
> include/linux/iommu.h | 17 +++++++++++++++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
> index 9a2f196..0af07492 100644
> --- a/drivers/iommu/iommu.c
> +++ b/drivers/iommu/iommu.c
> @@ -1061,6 +1061,8 @@ static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus,
>
> domain->ops = bus->iommu_ops;
> domain->type = type;
> + INIT_LIST_HEAD(&domain->reserved_regions);
> + mutex_init(&domain->resv_mutex);
> /* Assume all sizes by default; the driver may override this later */
> domain->pgsize_bitmap = bus->iommu_ops->pgsize_bitmap;
>
> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> index 436dc21..0f2eb64 100644
> --- a/include/linux/iommu.h
> +++ b/include/linux/iommu.h
> @@ -84,6 +84,8 @@ struct iommu_domain {
> void *handler_token;
> struct iommu_domain_geometry geometry;
> void *iova_cookie;
> + struct list_head reserved_regions;
> + struct mutex resv_mutex; /* protects the reserved region list */
> };
>
> enum iommu_cap {
> @@ -131,6 +133,21 @@ struct iommu_dm_region {
> int prot;
> };
>
> +/**
> + * struct iommu_reserved_region - descriptor for a reserved iova region
> + * @list: Linked list pointers
> + * @start: IOVA base address of the region
> + * @length: Length of the region in bytes
> + */
> +struct iommu_reserved_region {
> + struct list_head list;
> + dma_addr_t start;
> + size_t length;
> +};
Looking at this in context with the dm_region above, though, I come to
the surprising realisation that these *are* dm_regions, even at the
fundamental level - on the one hand you've got physical addresses which
can't be remapped (because something is already using them), while on
the other you've got physical addresses which can't be remapped (because
the IOMMU is incapable). In fact for reserved regions *other* than our
faked-up MSI region there's no harm if the IOMMU were to actually
identity-map them.
Let's just add this to the existing infrastructure, either with some
kind of IOMMU_NOMAP flag or simply prot = 0. That way it automatically
gets shared between the VFIO and DMA cases for free!
Robin.
> +
> +#define iommu_reserved_region_for_each(resv, d) \
> + list_for_each_entry(resv, &(d)->reserved_regions, list)
> +
> #ifdef CONFIG_IOMMU_API
>
> /**
>
^ permalink raw reply
* [PATCH v2 0/5] ARM: OMAP: dead code removal
From: Nicolae Rosia @ 2016-11-04 14:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478000206-10855-1-git-send-email-Nicolae_Rosia@mentor.com>
Hi,
I have identified some dead code which can be removed.
v2:
- Added details on each commit on how the code ended up unused.
Nicolae Rosia (5):
ARM: OMAP4: kill omap4_pmic_init and omap4_pmic_get_config
ARM: OMAP3: kill omap3_pmic_get_config and twl_{get,set}_voltage
ARM: OMAP3: kill omap3_pmic_init
ARM: OMAP2: kill omap2_pmic_init
ARM: OMAP: kill omap_pmic_init
arch/arm/mach-omap2/twl-common.c | 483 ---------------------------------------
arch/arm/mach-omap2/twl-common.h | 24 --
2 files changed, 507 deletions(-)
--
2.5.5
^ permalink raw reply
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