* [RESEND PATCH v1 2/6] irqchip/gic-v3-its: Narrow down Entry Size when used as a divider
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478510482-15471-1-git-send-email-vladimir.murzin@arm.com>
GITS_BASER<n>'s Entry Size is much smaller than 64-bit, but when it
used as a divider it forces compiler to generate __aeabi_uldivmod if
build in 32-bit mode. So, casting it to int (like it is done in other
places) where used as a divider would give a hint to compiler that
32-bit division can be used.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index bca125e..312dd55 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -948,7 +948,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
- &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / tmp),
+ &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
its_base_type_string[type],
(unsigned long)virt_to_phys(base),
indirect ? "indirect" : "flat", (int)esz,
@@ -983,7 +983,7 @@ static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser
* which is reported by ITS hardware times lvl1 table
* entry size.
*/
- ids -= ilog2(psz / esz);
+ ids -= ilog2(psz / (int)esz);
esz = GITS_LVL1_ENTRY_SIZE;
}
}
@@ -998,7 +998,7 @@ static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser
new_order = max_t(u32, get_order(esz << ids), new_order);
if (new_order >= MAX_ORDER) {
new_order = MAX_ORDER - 1;
- ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / esz);
+ ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n",
&its->phys_base, its->device_ids, ids);
}
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v1 1/6] irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478510482-15471-1-git-send-email-vladimir.murzin@arm.com>
Make sure that constants which are supposed to be applied on 64-bit
data is actually unsigned long long, so they won't be truncated when
used in 32-bit mode.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 28 ++++++++++++++--------------
include/linux/irqchip/arm-gic-v3.h | 4 ++--
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index c5dee30..bca125e 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -196,7 +196,7 @@ struct its_cmd_block {
static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
{
- cmd->raw_cmd[0] &= ~0xffUL;
+ cmd->raw_cmd[0] &= ~0xffULL;
cmd->raw_cmd[0] |= cmd_nr;
}
@@ -208,43 +208,43 @@ static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
{
- cmd->raw_cmd[1] &= ~0xffffffffUL;
+ cmd->raw_cmd[1] &= ~0xffffffffULL;
cmd->raw_cmd[1] |= id;
}
static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
{
- cmd->raw_cmd[1] &= 0xffffffffUL;
+ cmd->raw_cmd[1] &= 0xffffffffULL;
cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
}
static void its_encode_size(struct its_cmd_block *cmd, u8 size)
{
- cmd->raw_cmd[1] &= ~0x1fUL;
+ cmd->raw_cmd[1] &= ~0x1fULL;
cmd->raw_cmd[1] |= size & 0x1f;
}
static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
{
- cmd->raw_cmd[2] &= ~0xffffffffffffUL;
- cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
+ cmd->raw_cmd[2] &= ~0xffffffffffffULL;
+ cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00ULL;
}
static void its_encode_valid(struct its_cmd_block *cmd, int valid)
{
- cmd->raw_cmd[2] &= ~(1UL << 63);
+ cmd->raw_cmd[2] &= ~(1ULL << 63);
cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
}
static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
{
- cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
- cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
+ cmd->raw_cmd[2] &= ~(0xffffffffULL << 16);
+ cmd->raw_cmd[2] |= (target_addr & (0xffffffffULL << 16));
}
static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
{
- cmd->raw_cmd[2] &= ~0xffffUL;
+ cmd->raw_cmd[2] &= ~0xffffULL;
cmd->raw_cmd[2] |= col;
}
@@ -657,8 +657,8 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
its = its_dev->its;
addr = its->phys_base + GITS_TRANSLATER;
- msg->address_lo = addr & ((1UL << 32) - 1);
- msg->address_hi = addr >> 32;
+ msg->address_lo = lower_32_bits(addr);
+ msg->address_hi = upper_32_bits(addr);
msg->data = its_get_event_id(d);
iommu_dma_map_msi_msg(d->irq, msg);
@@ -935,9 +935,9 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
}
if (val != tmp) {
- pr_err("ITS@%pa: %s doesn't stick: %lx %lx\n",
+ pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
&its->phys_base, its_base_type_string[type],
- (unsigned long) val, (unsigned long) tmp);
+ val, tmp);
free_pages((unsigned long)base, order);
return -ENXIO;
}
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index b7e3431..5118d3a 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -239,7 +239,7 @@
#define GITS_TYPER_PTA (1UL << 19)
#define GITS_TYPER_HWCOLLCNT_SHIFT 24
-#define GITS_CBASER_VALID (1UL << 63)
+#define GITS_CBASER_VALID (1ULL << 63)
#define GITS_CBASER_SHAREABILITY_SHIFT (10)
#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
@@ -265,7 +265,7 @@
#define GITS_BASER_NR_REGS 8
-#define GITS_BASER_VALID (1UL << 63)
+#define GITS_BASER_VALID (1ULL << 63)
#define GITS_BASER_INDIRECT (1ULL << 62)
#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v1 0/6] Support GICv3 ITS in 32-bit mode
From: Vladimir Murzin @ 2016-11-07 9:21 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series introduces GICv3 ITS to 32-bit world. Since I'm limited
with real world 32-bit platforms which uses ITS it was tested with
help of vITS on 64-bit host running 32-bit guest.
I used Andrea's its/v8 branch at [1] with following option passed to
kvmtool: --aarch32 --irqchip=gicv3-its --force-pci
[1] git://www.linux-arm.org/kvmtool.git
Changelog:
RFC -> v1
- rebased on 4.9-rc2, gits_read_typer() has been dropped
- spilt ITS and vITS in separate patch sets
Vladimir Murzin (6):
irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility
irqchip/gic-v3-its: Narrow down Entry Size when used as a divider
irqchip/gicv3-its: Specialise flush_dcache operation
irqchip/gicv3-its: Specialise readq and writeq accesses
ARM: gic-v3-its: Add 32bit support to GICv3 ITS
ARM: virt: Select ARM_GIC_V3_ITS
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arch_gicv3.h | 54 +++++++++++++++++++++----
arch/arm64/include/asm/arch_gicv3.h | 17 ++++++++
drivers/irqchip/irq-gic-v3-its.c | 75 +++++++++++++++++------------------
include/linux/irqchip/arm-gic-v3.h | 4 +-
5 files changed, 104 insertions(+), 47 deletions(-)
--
1.7.9.5
^ permalink raw reply
* [PATCH 1/1] pinctrl: st: st_pctl_dt_parse_groups simplify expression
From: Patrice Chotard @ 2016-11-07 9:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161105143515.4668-1-xypron.glpk@gmx.de>
On 11/05/2016 03:35 PM, Heinrich Schuchardt wrote:
> for_each_property_of_node(pins, pp) checks that pp is not NULL.
> So there is no need to check it inside the loop.
>
> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
> ---
> drivers/pinctrl/pinctrl-st.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index 8308f15..676efcc 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -1181,7 +1181,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
> if (!strcmp(pp->name, "name"))
> continue;
>
> - if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) {
> + if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
> npins++;
> } else {
> pr_warn("Invalid st,pins in %s node\n", np->name);
>
Hi Heinrich
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Thanks
^ permalink raw reply
* [PATCH 1/1] pinctrl: st: st_pinconf_dbg_show wrong format string
From: Patrice Chotard @ 2016-11-07 9:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161105142515.4377-1-xypron.glpk@gmx.de>
On 11/05/2016 03:25 PM, Heinrich Schuchardt wrote:
> function is defined as unsigned int.
> So we need %u to print it.
>
> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
> ---
> drivers/pinctrl/pinctrl-st.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index b7bb371..8308f15 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -1006,7 +1006,7 @@ static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
>
> function = st_pctl_get_pin_function(pc, offset);
> if (function)
> - snprintf(f, 10, "Alt Fn %d", function);
> + snprintf(f, 10, "Alt Fn %u", function);
> else
> snprintf(f, 5, "GPIO");
>
>
Hi Heinrich
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Thanks
^ permalink raw reply
* [PATCH v7 2/2] ARM: EXYNOS: refactoring of mach-exynos to enable chipid driver
From: Arnd Bergmann @ 2016-11-07 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478347427-28409-3-git-send-email-pankaj.dubey@samsung.com>
On Saturday, November 5, 2016 5:33:47 PM CET Pankaj Dubey wrote:
> This patch enables chipid driver for ARCH_EXYNOS and refactors
> machine code for using chipid driver for identification of
> SoC ID and SoC rev.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
> arch/arm/mach-exynos/Kconfig | 1 +
> arch/arm/mach-exynos/common.h | 92 ----------------------------
> arch/arm/mach-exynos/exynos.c | 31 ----------
> arch/arm/mach-exynos/firmware.c | 10 +--
> arch/arm/mach-exynos/include/mach/map.h | 21 -------
> arch/arm/mach-exynos/platsmp.c | 22 ++++---
> arch/arm/mach-exynos/pm.c | 41 ++++++++-----
> arch/arm/plat-samsung/cpu.c | 14 -----
> arch/arm/plat-samsung/include/plat/cpu.h | 2 -
> arch/arm/plat-samsung/include/plat/map-s5p.h | 2 -
> 10 files changed, 47 insertions(+), 189 deletions(-)
> delete mode 100644 arch/arm/mach-exynos/include/mach/map.h
Nice code removal!
> -
> static void __init exynos_init_io(void)
> {
> debug_ll_io_init();
> -
> - of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
> -
> - /* detect cpu id and rev. */
> - s5p_init_cpu(S5P_VA_CHIPID);
> }
This is now the default for .map_io, so you can remove the rest of the
function as well and do
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 757fc11de30d..808872981f45 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -234,7 +234,6 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
.l2c_aux_val = 0x3c400001,
.l2c_aux_mask = 0xc20fffff,
.smp = smp_ops(exynos_smp_ops),
- .map_io = exynos_init_io,
.init_early = exynos_firmware_init,
.init_irq = exynos_init_irq,
.init_machine = exynos_dt_machine_init,
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index fd6da54..a9f8504e 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -44,7 +44,7 @@ static int exynos_do_idle(unsigned long mode)
> writel_relaxed(virt_to_phys(exynos_cpu_resume_ns),
> sysram_ns_base_addr + 0x24);
> writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
> - if (soc_is_exynos3250()) {
> + if (of_machine_is_compatible("samsung,exynos3250")) {
> flush_cache_all();
> exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
> SMC_POWERSTATE_IDLE, 0);
I'd rather not see a proliferation of many such checks. Please try
to rework it to have fewer checks, e.g. by having a separate instance
of "struct firmware_ops" for each incompatible variant and making the
decision once.
>
> +static struct soc_device_attribute exynos4210_rev11[] = {
> + { .soc_id = "EXYNOS4210", .revision = "11", },
> + { },
> +};
> +
> static void __iomem *cpu_boot_reg_base(void)
> {
> - if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
> + if (soc_device_match(exynos4210_rev11))
> return pmu_base_addr + S5P_INFORM5;
> return sysram_base_addr;
> }
> @@ -182,9 +187,10 @@ static inline void __iomem *cpu_boot_reg(int cpu)
> boot_reg = cpu_boot_reg_base();
> if (!boot_reg)
> return IOMEM_ERR_PTR(-ENODEV);
> - if (soc_is_exynos4412())
> + if (of_machine_is_compatible("samsung,exynos4412"))
> boot_reg += 4*cpu;
> - else if (soc_is_exynos5420() || soc_is_exynos5800())
> + else if (of_machine_is_compatible("samsung,exynos5420") ||
> + of_machine_is_compatible("samsung,exynos5800"))
> boot_reg += 4;
> return boot_reg;
> }
Same here, it would be nicer to rework the code to compute the address
once while called from a place where you already know this information
and then store the register address.
>
> +static struct soc_device_attribute exynos4210_rev11[] = {
> + { .soc_id = "EXYNOS4210", .revision = "11", },
> + { },
> +};
> +
> +static struct soc_device_attribute exynos4210_rev10[] = {
> + { .soc_id = "EXYNOS4210", .revision = "10", },
> + { },
> +};
Please use a single 'soc_device_attribute' table and make use
of the .data field to encode the difference.
Arnd
^ permalink raw reply related
* [crypto] [marvell-cesa] Possible regression after Linux 4.7
From: radioconfusion at gmail.com @ 2016-11-07 8:53 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
Thu, 3 Nov 2016 14:57:06 +0100, Romain Perier wrote:
>
> > Do you have any improvement for the issue?
> > Please let me know if you need any help to resolve it.
> >
> > Best Regards,
> > Jussi
> >
>
> Sorry for the delay.
> Could you try to revert locally commit
> 2786cee8e50bb4b4303dc22665f391b72318fa84 (crypto: marvell - Move SRAM
> I/O operations to step functions) ?
>
> It seems to fix most of the issues I had with curl.
> I will continue to investigate, that's just to confirm if it fixes the
> issues for you.
>
Thanks for this suggestion.
Unfortunately, I didn't get improvements using curl with this revertion.
Thanks for your investigation. Waiting for your input.
Best Regards,
Jussi
^ permalink raw reply
* [PATCH 3/3 v4] ARM: dts: Add gyro and accel to APQ8060 Dragonboard
From: Linus Walleij @ 2016-11-07 8:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478508284-10847-1-git-send-email-linus.walleij@linaro.org>
This adds the MPU-3050 gyroscope and the KXSD9 accelerometer to
the Qualcomm APQ8060 Dragonboard. The KXSD9 is mounted beyond the
MPU-3050 and appear as a subdevice beyond it. We set up the
required GPIO and interrupt lines to make the devices work.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v3->v4:
- Use interrupts-extended
- Add Bjorn's ACK.
ChangeLog v2->v3:
- Move the interrupt to the pm8058 alias to reflect the two patches
properly specifying the PMIC as interrupt parent.
ChangeLog v1->v2:
- Use the new I2C mux gate bindings from Peter Rosin (merged to
the I2C subsystem)
---
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 52 ++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index ea660ffa03ea..39d9e6ddefed 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -220,6 +220,14 @@
function = "ebi2";
};
};
+
+ /* Interrupt line for the KXSD9 accelerometer */
+ dragon_kxsd9_gpios: kxsd9 {
+ irq {
+ pins = "gpio57"; /* IRQ line */
+ bias-pull-up;
+ };
+ };
};
qcom,ssbi at 500000 {
@@ -272,6 +280,15 @@
power-source = <PM8058_GPIO_S3>;
};
};
+ dragon_mpu3050_gpios: mpu3050-gpios {
+ pinconf {
+ pins = "gpio17";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
dragon_sdcc3_gpios: sdcc3-gpios {
pinconf {
pins = "gpio22";
@@ -389,6 +406,41 @@
vddd-supply = <&pm8058_lvs0>; // 1.8V
vdda-supply = <&pm8058_l14>; // 2.85V
};
+ mpu3050 at 68 {
+ compatible = "invensense,mpu3050";
+ reg = <0x68>;
+ /*
+ * GPIO17 has interrupt 208 on the
+ * PM8058, it is pulled high by a 10k
+ * resistor to VLOGIC so needs to be
+ * active low/falling edge.
+ */
+ interrupts-extended = <&pm8058 208 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_mpu3050_gpios>;
+ vlogic-supply = <&pm8058_lvs0>; // 1.8V
+ vdd-supply = <&pm8058_l14>; // 2.85V
+
+ /*
+ * The MPU-3050 acts as a hub for the
+ * accelerometer.
+ */
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ kxsd9 at 18 {
+ compatible = "kionix,kxsd9";
+ reg = <0x18>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <57 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_kxsd9_gpios>;
+ iovdd-supply = <&pm8058_lvs0>; // 1.8V
+ vdd-supply = <&pm8058_l14>; // 2.85V
+ };
+ };
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/3 v4] ARM: dts: reference PM8058 as IRQ parent
From: Linus Walleij @ 2016-11-07 8:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478508284-10847-1-git-send-email-linus.walleij@linaro.org>
Some nodes are referencing the pm8058_gpio as IRQ parent, but
the HW IRQ offset they are supplying is actually that for the
parent to that controller: the PM8058 itself. Since that is the
proper parent, reference it directly.
We can switch this to the pm8058_gpio and the proper offset
once we have fixed the SSBI GPIO driver to properly deal with
the hierarchical IRQ domain and get proper local offset
translation.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Add Bjorn's ACK.
- Follow version numbering of the primary patch.
---
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 4a532ddab53a..ea660ffa03ea 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -369,8 +369,8 @@
ak8975 at 0c {
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
- /* GPIO33 has interrupt 224 on the PM8058 */
- interrupt-parent = <&pm8058_gpio>;
+ /* FIXME: GPIO33 has interrupt 224 on the PM8058 */
+ interrupt-parent = <&pm8058>;
interrupts = <224 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&dragon_ak8975_gpios>;
@@ -380,8 +380,8 @@
bmp085 at 77 {
compatible = "bosch,bmp085";
reg = <0x77>;
- /* GPIO16 has interrupt 207 on the PM8058 */
- interrupt-parent = <&pm8058_gpio>;
+ /* FIXME: GPIO16 has interrupt 207 on the PM8058 */
+ interrupt-parent = <&pm8058>;
interrupts = <207 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
--
2.7.4
^ permalink raw reply related
* [PATCH 1/3 v4] ARM: dts: rename MSM8660/APQ8060 pmicintc to pm8058
From: Linus Walleij @ 2016-11-07 8:44 UTC (permalink / raw)
To: linux-arm-kernel
The name "pmicintc" is ambiguous: there is a second power
management IC named PM8901 on these systems, and it is also
an interrupt controller. To make things clear, just name the
node alias "pm8058", this in unambigous and has all information
we need.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v4:
- Add Bjorn's ACK.
- Follow version numbering of the primary patch.
---
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 2 +-
arch/arm/boot/dts/qcom-msm8660-surf.dts | 2 +-
arch/arm/boot/dts/qcom-msm8660.dtsi | 12 ++++++------
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 4b8872cc8bf9..4a532ddab53a 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -412,7 +412,7 @@
* The second interrupt is the PME interrupt
* for network wakeup, connected to the TLMM.
*/
- interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>,
+ interrupts-extended = <&pm8058 198 IRQ_TYPE_EDGE_FALLING>,
<&tlmm 29 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
vdd33a-supply = <&dragon_veth>;
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 23de764558ab..1adc04978a47 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -48,7 +48,7 @@
};
};
-&pmicintc {
+&pm8058 {
keypad at 148 {
linux,keymap = <
MATRIX_KEY(0, 0, KEY_FN_F1)
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 4d828f810746..91c9a62ae725 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -163,7 +163,7 @@
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
- pmicintc: pmic at 0 {
+ pm8058: pmic at 0 {
compatible = "qcom,pm8058";
interrupt-parent = <&tlmm>;
interrupts = <88 8>;
@@ -176,7 +176,7 @@
compatible = "qcom,pm8058-gpio",
"qcom,ssbi-gpio";
reg = <0x150>;
- interrupt-parent = <&pmicintc>;
+ interrupt-parent = <&pm8058>;
interrupts = <192 IRQ_TYPE_NONE>,
<193 IRQ_TYPE_NONE>,
<194 IRQ_TYPE_NONE>,
@@ -232,7 +232,7 @@
reg = <0x50>;
gpio-controller;
#gpio-cells = <2>;
- interrupt-parent = <&pmicintc>;
+ interrupt-parent = <&pm8058>;
interrupts =
<128 IRQ_TYPE_NONE>,
<129 IRQ_TYPE_NONE>,
@@ -251,7 +251,7 @@
pwrkey at 1c {
compatible = "qcom,pm8058-pwrkey";
reg = <0x1c>;
- interrupt-parent = <&pmicintc>;
+ interrupt-parent = <&pm8058>;
interrupts = <50 1>, <51 1>;
debounce = <15625>;
pull-up;
@@ -260,7 +260,7 @@
keypad at 148 {
compatible = "qcom,pm8058-keypad";
reg = <0x148>;
- interrupt-parent = <&pmicintc>;
+ interrupt-parent = <&pm8058>;
interrupts = <74 1>, <75 1>;
debounce = <15>;
scan-delay = <32>;
@@ -270,7 +270,7 @@
rtc at 1e8 {
compatible = "qcom,pm8058-rtc";
reg = <0x1e8>;
- interrupt-parent = <&pmicintc>;
+ interrupt-parent = <&pm8058>;
interrupts = <39 1>;
allow-set-time;
};
--
2.7.4
^ permalink raw reply related
* [PATCH v7 1/2] soc: samsung: add exynos chipid driver support
From: Arnd Bergmann @ 2016-11-07 8:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478347427-28409-2-git-send-email-pankaj.dubey@samsung.com>
On Saturday, November 5, 2016 5:33:46 PM CET Pankaj Dubey wrote:
> Exynos SoCs have Chipid, for identification of product IDs
> and SoC revisions. This patch intends to provide initialization
> code for all these functionalities, at the same time it provides some
> sysfs entries for accessing these information to user-space.
>
> This driver uses existing binding for exynos-chipid.
>
> CC: Grant Likely <grant.likely@linaro.org>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
> drivers/soc/samsung/Kconfig | 5 ++
> drivers/soc/samsung/Makefile | 1 +
> drivers/soc/samsung/exynos-chipid.c | 148 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 154 insertions(+)
> create mode 100644 drivers/soc/samsung/exynos-chipid.c
>
> diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
> index 2455339..f9ab858 100644
> --- a/drivers/soc/samsung/Kconfig
> +++ b/drivers/soc/samsung/Kconfig
> @@ -14,4 +14,9 @@ config EXYNOS_PM_DOMAINS
> bool "Exynos PM domains" if COMPILE_TEST
> depends on PM_GENERIC_DOMAINS || COMPILE_TEST
>
> +config EXYNOS_CHIPID
> + bool "Exynos Chipid controller driver" if COMPILE_TEST
> + depends on (ARM && ARCH_EXYNOS) || ((ARM || ARM64) && COMPILE_TEST)
> + select SOC_BUS
> +
Please add a help text.
Why is this not enabled for ARM64 EXYNOS?
> + exynos_chipid_base = of_iomap(np, 0);
> +
> + if (!exynos_chipid_base)
> + return PTR_ERR(exynos_chipid_base);
> +
> + product_id = __raw_readl(exynos_chipid_base);
> + revision = product_id & EXYNOS_REV_MASK;
> + iounmap(exynos_chipid_base);
Never use __raw_readl/__raw_writel in device drivers, they are not endian
safe, and we just removed all instances for Exynos a while back.
> + return 0;
> +}
> +early_initcall(exynos_chipid_early_init);
>
Why is this early? Please add a code comment if it's really needed to be
an early_initcall, otherwise make it a device_initcall.
Arnd
^ permalink raw reply
* [PATCH v7 1/2] soc: samsung: add exynos chipid driver support
From: Arnd Bergmann @ 2016-11-07 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cafc255a-3bdb-7eb2-1092-545866752858@samsung.com>
On Monday, November 7, 2016 8:35:47 AM CET Marek Szyprowski wrote:
> This approach is a bit error prone. You have already missed Exynos5410
> and early Exynos 4210 are not detected because of the incorrect SOC MASK.
> IMHO you should replace above code and defines with a simple array,
> where each ID is present only once, so it will be much easier to add
> future SoCs:
>
> static const struct exynos_soc_id {
> const char *name;
> unsigned int id;
> unsigned int mask;
> } soc_ids[] = {
> { "EXYNOS3250", 0xE3472000, 0xFFFFF000 },
> { "EXYNOS4210", 0x43200000, 0xFFFE0000 },
> { "EXYNOS4212", 0x43220000, 0xFFFE0000 },
> { "EXYNOS4412", 0xE4412000, 0xFFFE0000 },
> { "EXYNOS4415", 0xE4415000, 0xFFFE0000 },
> { "EXYNOS5250", 0x43520000, 0xFFFFF000 },
> { "EXYNOS5260", 0xE5260000, 0xFFFFF000 },
> { "EXYNOS5410", 0xE5410000, 0xFFFFF000 },
> { "EXYNOS5420", 0xE5420000, 0xFFFFF000 },
> { "EXYNOS5440", 0xE5440000, 0xFFFFF000 },
> { "EXYNOS5800", 0xE5422000, 0xFFFFF000 },
> };
Good idea
>
> I'm also not sure about Exynos 4415, which has been scheduled for removal.
I'd vote for leaving it in the driver, and possibly adding other
models even if we don't support them in the other drivers, if
only for documentation purposes.
Arnd
^ permalink raw reply
* [PATCH V4 6/6] bus: Add support for Tegra Generic Memory Interface
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
The Generic Memory Interface bus can be used to connect high-speed
devices such as NOR flash, FPGAs, DSPs...
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
---
Changes in v2:
- Fixed some checkpatch errors
- Re-ordered probe to get rid of local variables
- Moved of_platform_default_populate call to the end of probe
- Use the timing and configuration properties from the child device
- Added warning if more then 1 child device exist
Changes in v3:
- added helper function to disable the controller which is used in remove and
on error.
- Added logic to parse CS# from "ranges" property with fallback to "reg"
property
Changes in v4:
- added sanity check of chip-select property (fail if invalid)
- adjusted for device tree binding property name changes
- fail probe if there are no child nodes
- removed superfluous error message
- removed superfluous newline in Kconfig
drivers/bus/Kconfig | 7 ++
drivers/bus/Makefile | 1 +
drivers/bus/tegra-gmi.c | 275 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 283 insertions(+)
create mode 100644 drivers/bus/tegra-gmi.c
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 4ed7d26..a9ebc4c 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -141,6 +141,13 @@ config TEGRA_ACONNECT
Driver for the Tegra ACONNECT bus which is used to interface with
the devices inside the Audio Processing Engine (APE) for Tegra210.
+config TEGRA_GMI
+ tristate "Tegra Generic Memory Interface bus driver"
+ depends on ARCH_TEGRA
+ help
+ Driver for the Tegra Generic Memory Interface bus which can be used
+ to attach devices such as NOR, UART, FPGA and more.
+
config UNIPHIER_SYSTEM_BUS
tristate "UniPhier System Bus driver"
depends on ARCH_UNIPHIER && OF
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index ac84cc4..34e2bab 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o
+obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o
obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c
new file mode 100644
index 0000000..687e212
--- /dev/null
+++ b/drivers/bus/tegra-gmi.c
@@ -0,0 +1,275 @@
+/*
+ * Driver for NVIDIA Generic Memory Interface
+ *
+ * Copyright (C) 2016 Host Mobility AB. All rights reserved.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/reset.h>
+
+#define TEGRA_GMI_CONFIG 0x00
+#define TEGRA_GMI_CONFIG_GO BIT(31)
+#define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30)
+#define TEGRA_GMI_MUX_MODE BIT(28)
+#define TEGRA_GMI_RDY_BEFORE_DATA BIT(24)
+#define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23)
+#define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22)
+#define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21)
+#define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20)
+#define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4)
+
+#define TEGRA_GMI_TIMING0 0x10
+#define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12)
+#define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8)
+#define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4)
+#define TEGRA_GMI_CE_WIDTH(x) (x & 0xf)
+
+#define TEGRA_GMI_TIMING1 0x14
+#define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16)
+#define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8)
+#define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff)
+
+#define TEGRA_GMI_MAX_CHIP_SELECT 8
+
+struct tegra_gmi_priv {
+ void __iomem *base;
+ struct reset_control *rst;
+ struct clk *clk;
+
+ u32 snor_config;
+ u32 snor_timing0;
+ u32 snor_timing1;
+};
+
+static void tegra_gmi_disable(struct tegra_gmi_priv *priv)
+{
+ u32 config;
+
+ /* stop GMI operation */
+ config = readl(priv->base + TEGRA_GMI_CONFIG);
+ config &= ~TEGRA_GMI_CONFIG_GO;
+ writel(config, priv->base + TEGRA_GMI_CONFIG);
+
+ reset_control_assert(priv->rst);
+ clk_disable_unprepare(priv->clk);
+}
+
+static void tegra_gmi_init(struct device *dev, struct tegra_gmi_priv *priv)
+{
+ writel(priv->snor_timing0, priv->base + TEGRA_GMI_TIMING0);
+ writel(priv->snor_timing1, priv->base + TEGRA_GMI_TIMING1);
+
+ priv->snor_config |= TEGRA_GMI_CONFIG_GO;
+ writel(priv->snor_config, priv->base + TEGRA_GMI_CONFIG);
+}
+
+static int tegra_gmi_parse_dt(struct device *dev, struct tegra_gmi_priv *priv)
+{
+ struct device_node *child = of_get_next_available_child(dev->of_node,
+ NULL);
+ u32 property, ranges[4];
+ int ret;
+
+ if (!child) {
+ dev_err(dev, "no child nodes found\n");
+ return -ENODEV;
+ }
+
+ /*
+ * We currently only support one child device due to lack of
+ * chip-select address decoding. Which means that we only have one
+ * chip-select line from the GMI controller.
+ */
+ if (of_get_child_count(dev->of_node) > 1)
+ dev_warn(dev, "only one child device is supported.");
+
+ if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
+ priv->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
+
+ if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
+ priv->snor_config |= TEGRA_GMI_MUX_MODE;
+
+ if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data"))
+ priv->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
+
+ if (of_property_read_bool(child, "nvidia,snor-rdy-active-high"))
+ priv->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
+
+ if (of_property_read_bool(child, "nvidia,snor-adv-active-high"))
+ priv->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
+
+ if (of_property_read_bool(child, "nvidia,snor-oe-active-high"))
+ priv->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
+
+ if (of_property_read_bool(child, "nvidia,snor-cs-active-high"))
+ priv->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
+
+ /* Decode the CS# */
+ ret = of_property_read_u32_array(child, "ranges", ranges, 4);
+ if (ret < 0) {
+ /* Invalid binding */
+ if (ret == -EOVERFLOW) {
+ dev_err(dev,
+ "failed to decode CS: invalid ranges length\n");
+ goto error_cs;
+ }
+
+ /*
+ * If we reach here it means that the child node has an empty
+ * ranges or it does not exist@all. Attempt to decode the
+ * CS# from the reg property instead.
+ */
+ ret = of_property_read_u32(child, "reg", &property);
+ if (ret < 0) {
+ dev_err(dev,
+ "failed to decode CS: no reg property found\n");
+ goto error_cs;
+ }
+ } else {
+ property = ranges[1];
+ }
+
+ /* Valid chip selects are CS0-CS7 */
+ if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {
+ dev_err(dev, "invalid chip select: %d", property);
+ ret = -EINVAL;
+ goto error_cs;
+ }
+
+ priv->snor_config |= TEGRA_GMI_CS_SELECT(property);
+
+ /* The default values that are provided below are reset values */
+ if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
+ priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
+ else
+ priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
+ priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
+ else
+ priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
+ priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
+ else
+ priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
+ priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
+ else
+ priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
+
+ if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
+ priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
+ else
+ priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
+ priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
+ else
+ priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
+
+ if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
+ priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
+ else
+ priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
+
+error_cs:
+ of_node_put(child);
+ return ret;
+}
+
+static int tegra_gmi_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct device *dev = &pdev->dev;
+ struct tegra_gmi_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->clk = devm_clk_get(dev, "gmi");
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "can not get clock\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->rst = devm_reset_control_get(dev, "gmi");
+ if (IS_ERR(priv->rst)) {
+ dev_err(dev, "can not get reset\n");
+ return PTR_ERR(priv->rst);
+ }
+
+ ret = tegra_gmi_parse_dt(dev, priv);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "fail to enable clock.\n");
+ return ret;
+ }
+
+ reset_control_assert(priv->rst);
+ udelay(2);
+ reset_control_deassert(priv->rst);
+
+ tegra_gmi_init(dev, priv);
+
+ ret = of_platform_default_populate(dev->of_node, NULL, dev);
+ if (ret < 0) {
+ dev_err(dev, "fail to create devices.\n");
+ tegra_gmi_disable(priv);
+ return ret;
+ }
+
+ dev_set_drvdata(dev, priv);
+
+ return 0;
+}
+
+static int tegra_gmi_remove(struct platform_device *pdev)
+{
+ struct tegra_gmi_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ of_platform_depopulate(&pdev->dev);
+
+ tegra_gmi_disable(priv);
+
+ return 0;
+}
+
+static const struct of_device_id tegra_gmi_id_table[] = {
+ { .compatible = "nvidia,tegra20-gmi", },
+ { .compatible = "nvidia,tegra30-gmi", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);
+
+static struct platform_driver tegra_gmi_driver = {
+ .probe = tegra_gmi_probe,
+ .remove = tegra_gmi_remove,
+ .driver = {
+ .name = "tegra-gmi",
+ .of_match_table = tegra_gmi_id_table,
+ },
+};
+module_platform_driver(tegra_gmi_driver);
+
+MODULE_AUTHOR("Mirza Krak <mirza.krak@gmail.com");
+MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver");
+MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related
* [PATCH V4 5/6] ARM: tegra: Add Tegra20 GMI support
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add a device node for the GMI controller found on Tegra20.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- added address-cells, size-cells and ranges properties
Changes in v3:
- fixed range address which is not the same as Tegra30.
Changes in v4:
- removed extra newline and a initial space in resets property.
arch/arm/boot/dts/tegra20.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 2207c08..e880750 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -376,6 +376,19 @@
status = "disabled";
};
+ gmi at 70009000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd0000000 0xfffffff>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ status = "disabled";
+ };
+
pwm: pwm at 7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
2.1.4
^ permalink raw reply related
* [PATCH V4 4/6] ARM: tegra: Add Tegra30 GMI support
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add a device node for the GMI controller found on Tegra30.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- added address-cells, size-cells and ranges properties
Changes in v3:
- no changes
Changes in v4:
- no changes
arch/arm/boot/dts/tegra30.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 5030065..bbb1c00 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -439,6 +439,19 @@
status = "disabled";
};
+ gmi at 70009000 {
+ compatible = "nvidia,tegra30-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x48000000 0x7ffffff>;
+ clocks = <&tegra_car TEGRA30_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ status = "disabled";
+ };
+
pwm: pwm at 7000a000 {
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
2.1.4
^ permalink raw reply related
* [PATCH V4 3/6] dt/bindings: Add bindings for Tegra GMI controller
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Document the devicetree bindings for the Generic Memory Interface (GMI)
bus driver found on Tegra SOCs.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v2:
- Updated examples and some information based on comments from Jon Hunter.
Changes in v3:
- Updates ranges description based on comments from Rob Herring
Changes in v4:
- renamed snor-*-inv to snor-*-active-high
.../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132 +++++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
new file mode 100644
index 0000000..83b0e54
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
@@ -0,0 +1,132 @@
+Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
+
+The Generic Memory Interface bus enables memory transfers between internal and
+external memory. Can be used to attach various high speed devices such as
+synchronous/asynchronous NOR, FPGA, UARTS and more.
+
+The actual devices are instantiated from the child nodes of a GMI node.
+
+Required properties:
+ - compatible : Should contain one of the following:
+ For Tegra20 must contain "nvidia,tegra20-gmi".
+ For Tegra30 must contain "nvidia,tegra30-gmi".
+ - reg: Should contain GMI controller registers location and length.
+ - clocks: Must contain an entry for each entry in clock-names.
+ - clock-names: Must include the following entries: "gmi"
+ - resets : Must contain an entry for each entry in reset-names.
+ - reset-names : Must include the following entries: "gmi"
+ - #address-cells: The number of cells used to represent physical base
+ addresses in the GMI address space. Should be 2.
+ - #size-cells: The number of cells used to represent the size of an address
+ range in the GMI address space. Should be 1.
+ - ranges: Must be set up to reflect the memory layout with three integer values
+ for each chip-select line in use (only one entry is supported, see below
+ comments):
+ <cs-number> <offset> <physical address of mapping> <size>
+
+Note that the GMI controller does not have any internal chip-select address
+decoding, because of that chip-selects either need to be managed via software
+or by employing external chip-select decoding logic.
+
+If external chip-select logic is used to support multiple devices it is assumed
+that the devices use the same timing and so are probably the same type. It also
+assumes that they can fit in the 256MB address range. In this case only one
+child device is supported which represents the active chip-select line, see
+examples for more insight.
+
+The chip-select number is decoded from the child nodes second address cell of
+'ranges' property, if 'ranges' property is not present or empty chip-select will
+then be decoded from the first cell of the 'reg' property.
+
+Optional child cs node properties:
+
+ - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
+ - nvidia,snor-mux-mode: Enable address/data MUX mode.
+ - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
+ If omitted it will be asserted with data.
+ - nvidia,snor-rdy-active-high: RDY signal is active high
+ - nvidia,snor-adv-active-high: ADV signal is active high
+ - nvidia,snor-oe-active-high: WE/OE signal is active high
+ - nvidia,snor-cs-active-high: CS signal is active high
+
+ Note that there is some special handling for the timing values.
+ From Tegra TRM:
+ Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
+
+ - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
+ bus. Valid values are 0-15, default is 1
+ - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
+ de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
+ (in case of MASTER Request). Valid values are 0-15, default is 1
+ - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
+ Valid values are 0-15, default is 1.
+ - nvidia,snor-ce-width: Number of cycles before CE is asserted.
+ Valid values are 0-15, default is 4
+ - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
+ Valid values are 0-15, default is 1
+ - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
+ Valid values are 0-255, default is 1
+ - nvidia,snor-wait-width: Number of cycles before READY is asserted.
+ Valid values are 0-255, default is 3
+
+Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
+controllers with a simple-bus node since they are all connected to the same
+chip-select (CS4), in this example external address decoding is provided:
+
+gmi at 70090000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ ranges = <4 0 0xd0000000 0xfffffff>;
+
+ status = "okay";
+
+ bus at 4,0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 4 0 0x40100>;
+
+ nvidia,snor-mux-mode;
+ nvidia,snor-adv-active-high;
+
+ can at 0 {
+ reg = <0 0x100>;
+ ...
+ };
+
+ can at 40000 {
+ reg = <0x40000 0x100>;
+ ...
+ };
+ };
+};
+
+Example with one SJA1000 CAN controller connected to the GMI bus
+on CS4:
+
+gmi at 70090000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ ranges = <4 0 0xd0000000 0xfffffff>;
+
+ status = "okay";
+
+ can at 4,0 {
+ reg = <4 0 0x100>;
+ nvidia,snor-mux-mode;
+ nvidia,snor-adv-active-high;
+ ...
+ };
+};
--
2.1.4
^ permalink raw reply related
* [PATCH V4 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which
is max rate.
The maximum rate value of 127 MHz is pulled from the downstream L4T
kernel.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- no changes
Changes in v3:
- Added comment in commit message where I got the maximum rates from.
Changes in V4:
- no changes
drivers/clk/tegra/clk-tegra30.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8e2db5e..67f1677 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1252,6 +1252,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
{ TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
{ TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
+ { TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 127000000, 0 },
{ TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
--
2.1.4
^ permalink raw reply related
* [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Mirza Krak @ 2016-11-07 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com>
From: Mirza Krak <mirza.krak@gmail.com>
Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
is max rate.
The maximum rate value of 92 MHz is pulled from the downstream L4T
kernel.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- no changes
Changes in v3:
- Added comment in commit message where I got the maximum rates from.
Changes in V4:
- no changes
drivers/clk/tegra/clk-tegra20.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 837e5cb..13d3b5a 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
{ TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
{ TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
+ { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 },
{ TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
--
2.1.4
^ permalink raw reply related
* [PATCH V4 0/6] Add support for Tegra GMI bus controller
From: Mirza Krak @ 2016-11-07 8:29 UTC (permalink / raw)
To: linux-arm-kernel
From: Mirza Krak <mirza.krak@hostmobility.com>
Hi.
This patch series adds support for the Tegra GMI bus controller.
I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom
carrier board which has multiple CAN controllers (SJA1000) connected to the
GMI bus.
I have re-based on top of latest tegra/for-next in V4. Also see individual
patches for changes in V4.
Hopefully this will be the last round.
See below links for previous discussions.
Comments on RFC:
https://marc.info/?l=linux-clk&m=146893557629903&w=2
https://marc.info/?l=linux-tegra&m=146893541829801&w=2
https://marc.info/?l=linux-tegra&m=146893542429814&w=2
Comments on V1:
https://marc.info/?l=linux-arm-kernel&m=147051551821122&w=2
https://marc.info/?l=linux-arm-kernel&m=147051553121150&w=2
https://marc.info/?l=linux-arm-kernel&m=147194856600627&w=2
https://marc.info/?l=linux-arm-kernel&m=147072742432211&w=2
Comments on V2:
https://marc.info/?l=devicetree&m=147522253920226&w=2
https://marc.info/?l=linux-tegra&m=147204588027687&w=2
https://marc.info/?l=linux-tegra&m=147204588027687&w=2
https://marc.info/?l=devicetree&m=147256931318922&w=2
Comments on V3:
https://marc.info/?l=linux-tegra&m=147789181607782&w=2
https://marc.info/?l=linux-tegra&m=147816818203104&w=2
https://marc.info/?l=linux-tegra&m=147816897003332&w=2
https://marc.info/?l=linux-tegra&m=147818119107204&w=2
Mirza Krak (6):
clk: tegra: add TEGRA20_CLK_NOR to init table
clk: tegra: add TEGRA30_CLK_NOR to init table
dt/bindings: Add bindings for Tegra GMI controller
ARM: tegra: Add Tegra30 GMI support
ARM: tegra: Add Tegra20 GMI support
bus: Add support for Tegra Generic Memory Interface
.../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132 ++++++++++
arch/arm/boot/dts/tegra20.dtsi | 13 +
arch/arm/boot/dts/tegra30.dtsi | 13 +
drivers/bus/Kconfig | 7 +
drivers/bus/Makefile | 1 +
drivers/bus/tegra-gmi.c | 275 +++++++++++++++++++++
drivers/clk/tegra/clk-tegra20.c | 1 +
drivers/clk/tegra/clk-tegra30.c | 1 +
8 files changed, 443 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
create mode 100644 drivers/bus/tegra-gmi.c
--
2.1.4
^ permalink raw reply
* ILP32 for ARM64: testing with glibc testsuite
From: Yury Norov @ 2016-11-07 8:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477081997-4770-1-git-send-email-ynorov@caviumnetworks.com>
Hi all,
[add libc-alpha mail list]
For libc-alpha: this is the part of LKML submission with latest
patches for aarch64/ilp32.
https://www.spinics.net/lists/arm-kernel/msg537846.html
Glibc that I use has also included consolidation patches from Adhemerval
Zanella and me that are still not in the glibc master. The full series is:
https://github.com/norov/glibc/tree/ilp32-2.24-dev2
Below is the results of glibc testsuite run for aarch64/lp64
in different configurations. Column names meaning:
kvgv: kernel is vanilla, glibc is vanilla;
kdgv: kernel has ilp32 patches applied, but ilp32 is disabled in config;
glibc is vanilla;
kegv: kernel has ilp32 patches applied and ilp32 is enabled, glibc is vanilla;
kege: kernel patches are applied and enabled, glibc patches are applied.
Only different lines are shown. Full results are in attached archive.
I didn't analyze regressions deep yet, so any ideas/suggestions are appreciated.
Yury.
Test kvgv kdgv kegv kege
conform/ISO/stdio.h/linknamespace PASS PASS PASS FAIL
conform/ISO11/stdio.h/linknamespace PASS PASS PASS FAIL
conform/ISO99/stdio.h/linknamespace PASS PASS PASS FAIL
conform/POSIX/stdio.h/linknamespace PASS PASS PASS FAIL
conform/POSIX/sys/stat.h/linknamespace PASS PASS PASS FAIL
conform/UNIX98/stdio.h/linknamespace PASS PASS PASS FAIL
conform/XOPEN2K/stdio.h/linknamespace PASS PASS PASS FAIL
conform/XPG3/stdio.h/linknamespace PASS PASS PASS FAIL
conform/XPG4/stdio.h/linknamespace PASS PASS PASS FAIL
csu/tst-atomic PASS PASS PASS FAIL
elf/check-localplt PASS PASS PASS FAIL
iconvdata/mtrace-tst-loading PASS FAIL PASS PASS
iconvdata/tst-loading PASS FAIL PASS PASS
io/check-installed-headers-c PASS PASS PASS FAIL
io/check-installed-headers-cxx PASS PASS PASS FAIL
malloc/tst-malloc-backtrace FAIL PASS PASS PASS
malloc/tst-malloc-thread-exit FAIL PASS PASS PASS
malloc/tst-malloc-usable FAIL PASS PASS PASS
malloc/tst-mallocfork FAIL PASS PASS PASS
malloc/tst-mallocstate FAIL PASS PASS PASS
malloc/tst-mallopt FAIL PASS PASS PASS
malloc/tst-mcheck FAIL PASS PASS PASS
malloc/tst-memalign FAIL PASS PASS PASS
malloc/tst-obstack FAIL PASS PASS PASS
malloc/tst-posix_memalign FAIL PASS PASS PASS
malloc/tst-pvalloc FAIL PASS PASS PASS
malloc/tst-realloc FAIL PASS PASS PASS
malloc/tst-scratch_buffer FAIL PASS PASS PASS
malloc/tst-trim1 FAIL PASS PASS PASS
nptl/tst-eintr4 PASS PASS PASS NA
posix/tst-regex2 PASS FAIL FAIL FAIL
posix/tst-getaddrinfo4 PASS PASS FAIL FAIL
posix/tst-getaddrinfo5 PASS PASS FAIL FAIL
sysvipc/test-sysvmsg NA NA NA FAIL
sysvipc/test-sysvsem NA NA NA FAIL
sysvipc/test-sysvshm NA NA NA FAIL
-------------- next part --------------
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^ permalink raw reply
* [BUG] pinctrl: sunxi: sunxi-pinctrl fail to load with CONFIG_DEBUG_TEST_DRIVER_REMOVE
From: LABBE Corentin @ 2016-11-07 8:18 UTC (permalink / raw)
To: linux-arm-kernel
Hello
With CONFIG_DEBUG_TEST_DRIVER_REMOVE=y pinctrl-sunxi fail to load on the second try.
[ 3.900061] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver
[ 3.916251] gpio gpiochip1: GPIO integer space overlap, cannot add chip
[ 3.923016] gpiochip_add_data: GPIOs 0..223 (1c20800.pinctrl) failed to register
[ 3.931099] sun8i-h3-pinctrl: probe of 1c20800.pinctrl failed with error -16
[ 3.944709] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi PIO driver
[ 3.960796] gpio gpiochip2: GPIO integer space overlap, cannot add chip
[ 3.967594] gpiochip_add_data: GPIOs 352..383 (1f02c00.pinctrl) failed to register
[ 3.975633] sun8i-h3-r-pinctrl: probe of 1f02c00.pinctrl failed with error -16
Without it, all subsequent drivers fail to load.
Tested on Orange PI PC board.
Regards
^ permalink raw reply
* Memory range end be inclusive or exclusive? Re: [PATCH v1 1/4] kexec: (bugfix) calc correct end address of memory ranges in device tree
From: Simon Horman @ 2016-11-07 8:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161031085008.GF19531@linaro.org>
Hi Akashi-san,
sorry for the long delay(s).
The patch below seems reasonable to me and I'm happy to apply it.
On Mon, Oct 31, 2016 at 05:50:09PM +0900, AKASHI Takahiro wrote:
> Simon,
>
> On Tue, Sep 06, 2016 at 09:29:59AM +0900, AKASHI Takahiro wrote:
> > Simon,
> >
> > What is your opinion on this issue?
>
> Pinged you several times so far.
>
> Can you please give me your comment?
> (attached below is the original patch.)
>
> -Takahiro AKASHI
>
> >
> > On Mon, Aug 01, 2016 at 01:52:40PM +0900, AKASHI Takahiro wrote:
> > > On Fri, Jul 29, 2016 at 06:23:56PM +0100, Russell King - ARM Linux wrote:
> > > > On Fri, Jul 29, 2016 at 10:12:26AM -0700, Geoff Levand wrote:
> > > > > On Fri, 2016-07-29 at 09:27 +0100, Russell King - ARM Linux wrote:
> > > > >
> > > > > > So, these functions are a mess and need fixing.
> > > > >
> > > > > Since this change isn't really related to arm64 support, I'll
> > > > > drop this patch from my series.
> > > >
> > > > Do you have a case which triggers bugs in this code?
> > >
> > > Actually, this patch was necessary when my kdump used "usable-memory"
> > > properties in "memory" nodes, as on ppc64, to limit the usable memory
> > > regions that can be used by crash dump kernel.
> > > Since then, I've moved to the approach of using "mem=" kernel parameter,
> > > then introducing a new property, "linux,usable-memory-range," under /chosen
> > > and now we don't need this patch any more.
> > >
> > > So, we can drop it but I still believe that it is buggy.
> >
> > Due to the discussions[1], I may want to re-enable "usable-memory"
> > property on arm64. In addition, I would like to add a function,
> > dtb_add_usable_memory_properties(), a variant of
> > add_usable_memory_properties(), to kexec/dt-ops.c.
> > So this issue is quite crucial now.
> >
> > [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-August/452685.html
> >
> > -Takahiro AKASHI
> >
> > > Thanks,
> > > -Takahiro AKASHI
> > >
> > > > --
> > > > RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
> > > > FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
> > > > according to speedtest.net.
> ===8<===
> From: AKASHI Takahiro <takahiro.akashi@linaro.org>
>
> The end address of "reg" attribute in device tree's memory should be
> inclusive.
> ---
> kexec/fs2dt.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/kexec/fs2dt.c b/kexec/fs2dt.c
> index 79aa0f3..953f78a 100644
> --- a/kexec/fs2dt.c
> +++ b/kexec/fs2dt.c
> @@ -236,7 +236,8 @@ static void add_dyn_reconf_usable_mem_property__(int fd)
> ranges_size*8);
> }
> ranges[rlen++] = cpu_to_be64(loc_base);
> - ranges[rlen++] = cpu_to_be64(loc_end - loc_base);
> + ranges[rlen++] = cpu_to_be64(loc_end
> + - loc_base + 1);
> rngs_cnt++;
> }
> }
> @@ -350,7 +351,7 @@ static void add_usable_mem_property(int fd, size_t len)
> ranges_size*sizeof(*ranges));
> }
> ranges[rlen++] = cpu_to_be64(loc_base);
> - ranges[rlen++] = cpu_to_be64(loc_end - loc_base);
> + ranges[rlen++] = cpu_to_be64(loc_end - loc_base + 1);
> }
> }
>
> --
> 2.10.0
>
^ permalink raw reply
* [PATCH V2] arm64: Add support of R_AARCH64_PREL32 relocation in purgatory
From: Simon Horman @ 2016-11-07 8:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3175f823-dd03-07f6-fffe-6ec5487cbf93@infradead.org>
On Fri, Oct 28, 2016 at 11:43:48AM -0700, Geoff Levand wrote:
> On 10/27/2016 09:16 PM, Pratyush Anand wrote:
> > gcc version in fedora koji is 6.2.1-2.fc25. kexec-tools compiled with this
> > gcc produced another relocation error:
> >
> > machine_apply_elf_rel: ERROR Unknown type: 261
> >
> > This patch fixes the above error.
>
> Looks good. Simon, please apply.
>
> Reviewed-by: Geoff Levand <geoff@infradead.org>
Thanks, applied.
^ permalink raw reply
* [PATCH v2] arm64: Add support for additional relocations in the kexec purgatory code
From: Simon Horman @ 2016-11-07 8:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2792b205-dfdd-1362-9cf4-d886472a9357@infradead.org>
On Thu, Oct 20, 2016 at 09:37:03AM -0700, Geoff Levand wrote:
> On 10/20/2016 03:43 AM, Catalin Marinas wrote:
> > When compiling the kexec-tools with gcc6, the following additional
> > reolcations are generated in the purgatory.ro file:
> >
> > R_AARCH64_ADR_PREL_PG_HI21
> > R_AARCH64_ADD_ABS_LO12_NC
> > R_AARCH64_LDST64_ABS_LO12_NC
>
> Looks good. Simon, please apply.
>
> Reviewed-by: Geoff Levand <geoff@infradead.org>
Thanks, applied.
^ permalink raw reply
* [PATCH 2/2] clk: sunxi-ng: fix up PLL_CPUX adjusting for A23/A33
From: Maxime Ripard @ 2016-11-07 7:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161106172932.39478-2-icenowy@aosc.xyz>
Hi,
Same remark for the commit title.
On Mon, Nov 07, 2016 at 01:29:32AM +0800, Icenowy Zheng wrote:
> When adjusting PLL_CPUX on A23/A33, the PLL is driven too high, and the
> system stucks.
>
> Add a notifier to avoid this situation.
>
> The code is ported from ccu-sun6i-a31.c.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Patch 4.9-rc too.
> drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 10 ++++++++++
Have you checked that it was also needed on A23? Not all SoCs are in
this situation.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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