* [PATCH 2/6] pinctrl: rockchip: add support for rk1108
From: Heiko Stübner @ 2016-11-12 21:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFLEztRW8P4kiPZzVX2jM5UZMZun=TBBCij4B7j2TiesCuJYWA@mail.gmail.com>
Hi Jacob,
Am Sonntag, 13. November 2016, 01:41:21 schrieb ??:
> 2016-11-03 20:34 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
> > Add basic support for rk1108 soc
> >
> > Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> > ---
> >
> > drivers/pinctrl/pinctrl-rockchip.c | 27 ++++++++++++++++++++++++++-
> > 1 file changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pinctrl/pinctrl-rockchip.c
> > b/drivers/pinctrl/pinctrl-rockchip.c index 49bf7dc..9f324b1 100644
> > --- a/drivers/pinctrl/pinctrl-rockchip.c
> > +++ b/drivers/pinctrl/pinctrl-rockchip.c
> > @@ -59,6 +59,7 @@
> >
> > #define GPIO_LS_SYNC 0x60
> >
> > enum rockchip_pinctrl_type {
> >
> > + RK1108,
> >
> > RK2928,
> > RK3066B,
> > RK3188,
> >
> > @@ -1123,6 +1124,7 @@ static int rockchip_get_pull(struct
> > rockchip_pin_bank *bank, int pin_num)>
> > return !(data & BIT(bit))
> >
> > ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
> >
> > : PIN_CONFIG_BIAS_DISABLE;
> >
> > + case RK1108:
> > case RK3188:
> > case RK3288:
> >
> > case RK3368:
> > @@ -1169,6 +1171,7 @@ static int rockchip_set_pull(struct
> > rockchip_pin_bank *bank,>
> > spin_unlock_irqrestore(&bank->slock, flags);
> > break;
> >
> > + case RK1108:
> > case RK3188:
> > case RK3288:
> >
> > case RK3368:
> > @@ -1358,6 +1361,7 @@ static bool rockchip_pinconf_pull_valid(struct
> > rockchip_pin_ctrl *ctrl,>
> > pull == PIN_CONFIG_BIAS_DISABLE);
> >
> > case RK3066B:
> > return pull ? false : true;
> >
> > + case RK1108:
> > case RK3188:
> > case RK3288:
> >
> > case RK3368:
> > @@ -1385,7 +1389,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev
> > *pctldev, unsigned int pin,>
> > for (i = 0; i < num_configs; i++) {
> >
> > param = pinconf_to_config_param(configs[i]);
> > arg = pinconf_to_config_argument(configs[i]);
> >
> > -
> >
> > switch (param) {
> >
> > case PIN_CONFIG_BIAS_DISABLE:
> > rc = rockchip_set_pull(bank, pin -
> > bank->pin_base,
> >
> > @@ -2455,6 +2458,26 @@ static int rockchip_pinctrl_probe(struct
> > platform_device *pdev)>
> > return 0;
> >
> > }
> >
> > +static struct rockchip_pin_bank rk1108_pin_banks[] = {
> > + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> > + IOMUX_SOURCE_PMU,
> > + IOMUX_SOURCE_PMU,
> > + IOMUX_SOURCE_PMU),
> > + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
> > + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
> > + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
> > +};
> > +
> > +static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
> > + .pin_banks = rk1108_pin_banks,
> > + .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
> > + .label = "RK1108-GPIO",
> > + .type = RK1108,
> > + .grf_mux_offset = 0x10,
> > + .pmu_mux_offset = 0x0,
> > + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
> > +};
> > +
> >
> > static struct rockchip_pin_bank rk2928_pin_banks[] = {
> >
> > PIN_BANK(0, 32, "gpio0"),
> > PIN_BANK(1, 32, "gpio1"),
> >
> > @@ -2684,6 +2707,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
> >
> > };
> >
> > static const struct of_device_id rockchip_pinctrl_dt_match[] = {
> >
> > + { .compatible = "rockchip,rk1108-pinctrl",
> > + .data = (void *)&rk1108_pin_ctrl },
> >
> > { .compatible = "rockchip,rk2928-pinctrl",
> >
> > .data = (void *)&rk2928_pin_ctrl },
> >
> > { .compatible = "rockchip,rk3036-pinctrl",
> >
> > --
> > 2.7.4
>
> rk3288_calc_pull_reg_and_bit can't be used directly in rk1108.
> rk1108 have a different PULL_PMU_OFFSET and PULL_OFFSET.
yes, you're right, the offsets are different, so need a new function.
Andy, when at it, you might also want to include drive-strength functionality?
It is missing here but from looking at the TRM, it should be pretty easy to
add, as everything looks similar to what other rockchip socs do.
Heiko
^ permalink raw reply
* PM regression with LED changes in next-20161109
From: Hans de Goede @ 2016-11-12 21:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c01cac8b-a921-56d1-7e57-8071d4b9faf6@gmail.com>
Hi,
On 12-11-16 20:14, Jacek Anaszewski wrote:
<snip>
>>>> Why a dedicated file? Are we going to mirror brightness here
>>>> wrt r/w (show/store) behavior ? If not userspace now needs
>>>> 2 open fds which is not really nice. If we are and we are
>>>> not going to use poll for something else on brightness itself
>>>> then why not just poll directly on brightness ?
>>>
>>> My main concern is that reporting only hw brightness changes
>>> wouldn't be consistent with general brightness file purpose.
>>> One could expect that brightness changes made by triggers
>>> should be also reported.
>>
>> Ok, I agree that not notifying poll() while an actual
>> read() would result in a different value is not really good
>> semantics.
>>
>> I don't like to call it hw_brightness_change though, as
>> mentioned before I believe that if we were to start with
>> a clean slate we would make the brightness file's read/write
>> behavior more a mirror of itself.
>>
>> So I would like to propose creating a new read-write
>> user_brightness file.
>>
>> The write behavior would be 100% identical to the brightness
>> file (in code terms it will call the same store function).
>>
>> The the read behavior otoh will be different: it will shows
>> the last brightness as set by the user, this would show the
>> read behavior we really want of brightness: show the real
>> brightness when not blinking / triggers are active and show
>> the brightness used when on when blinking / triggers are active.
>>
>> We could then add poll support on this new user_brightness
>> file, thus avoiding the problem with the extra cpu-load on
>> notifications on blinking / triggers.
>
> I agree that user_brightness allows to solve the issues you raised
> about inconsistent write and read brightness' semantics
> (which is not that painful IMHO).
>
> Reporting non-user brightness changes on user_brightness file
> doesn't sound reasonable though.
The changes I'm interested in are user brightness changes they
are just not done through sysfs, but through a hardwired hotkey,
they are however very much done by the user.
> Also, how would we read the
> brightness set by the firmware? We'd have to read brightness
> file, so still two files would have to be opened which is
> a second drawback of this approach.
No, look carefully at the definition of the read behavior
I plan to put in the ABI doc:
"Reading this file will return the actual led brightness
when not blinking and no triggers are active; reading this
file will return the brightness used when the led is on
when blinking or triggers are active."
So for e.g. the backlit keyboard case reading this single
file will return the actual brightness of the backlight,
since this does not involve blinking or triggers.
Basically the idea is that the user_brightness file
will have the semantics which IMHO the brightness file
itself should have had from the beginning, but which
we can't change now due to ABI reasons.
> Having no difference in this area between the two approaches
> I'm still in favour of the read-only file for notifying
> brightness changes procured by hardware.
That brings back the needing 2 fds problem; and does
not solve userspace not being able to reliably read
the led on brightness when blinking or using triggers.
And this also has the issue that one is doing poll() on
one fd to detect changes on another fd, which is completely
unheard of in any kernel API, so I still vote NACK for the
entire idea of having a different file purely for notifying
changes. The way unix defines poll to work means that the
poll() and read() must be on the same fd, anything else
does not make sense.
Regards,
Hans
^ permalink raw reply
* [PATCH RFC] mm: Add debug_virt_to_phys()
From: Florian Fainelli @ 2016-11-12 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161112054318.GB24127@arm.com>
Le 11/11/2016 ? 21:43, Will Deacon a ?crit :
> On Fri, Nov 11, 2016 at 04:44:43PM -0800, Florian Fainelli wrote:
>> When CONFIG_DEBUG_VM is turned on, virt_to_phys() maps to
>> debug_virt_to_phys() which helps catch vmalloc space addresses being
>> passed. This is helpful in debugging bogus drivers that just assume
>> linear mappings all over the place.
>>
>> For ARM, ARM64, Unicore32 and Microblaze, the architectures define
>> __virt_to_phys() as being the functional implementation of the address
>> translation, so we special case the debug stub to call into
>> __virt_to_phys directly.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>> arch/arm/include/asm/memory.h | 4 ++++
>> arch/arm64/include/asm/memory.h | 4 ++++
>> include/asm-generic/memory_model.h | 4 ++++
>> mm/debug.c | 15 +++++++++++++++
>> 4 files changed, 27 insertions(+)
>
> What's the interaction between this and the DEBUG_VIRTUAL patches from Laura?
>
> http://lkml.kernel.org/r/20161102210054.16621-7-labbott at redhat.com
>
> They seem to be tackling the exact same problem afaict.
Indeed thanks for pointing that out, I guess I could piggy back on this
patchset and try to cover ARM.
Thanks!
--
Florian
^ permalink raw reply
* [PATCH RFT] irqchip: mxs: Enable SKIP_SET_WAKE and MASK_ON_SUSPEND
From: Oleksij Rempel @ 2016-11-12 19:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478885208-18821-1-git-send-email-stefan.wahren@i2se.com>
Am 11.11.2016 um 18:26 schrieb Stefan Wahren:
> The ICOLL controller doesn't provide any facility to configure the
> wakeup sources. That's the reason why this implementation lacks
> the irq_set_wake implementation. But this prevent us from properly
> entering power management states like "suspend to idle".
>
> So enable the flags IRQCHIP_SKIP_SET_WAKE and IRQCHIP_MASK_ON_SUSPEND
> to let the irqchip core allows and handles the power management.
>
> This patch has been tested with a MX23 and a MX28 board. Any further
> tests especially with ASM9260 would be appreciated.
Hi, I wont be able to test this patch on ASM9260 until March.
Please roll it out, so far it looks ok for me.
> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
> ---
> drivers/irqchip/irq-mxs.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/irqchip/irq-mxs.c b/drivers/irqchip/irq-mxs.c
> index 1730470..05fa9f7 100644
> --- a/drivers/irqchip/irq-mxs.c
> +++ b/drivers/irqchip/irq-mxs.c
> @@ -131,12 +131,16 @@ static void asm9260_unmask_irq(struct irq_data *d)
> .irq_ack = icoll_ack_irq,
> .irq_mask = icoll_mask_irq,
> .irq_unmask = icoll_unmask_irq,
> + .flags = IRQCHIP_MASK_ON_SUSPEND |
> + IRQCHIP_SKIP_SET_WAKE,
> };
>
> static struct irq_chip asm9260_icoll_chip = {
> .irq_ack = icoll_ack_irq,
> .irq_mask = asm9260_mask_irq,
> .irq_unmask = asm9260_unmask_irq,
> + .flags = IRQCHIP_MASK_ON_SUSPEND |
> + IRQCHIP_SKIP_SET_WAKE,
> };
>
> asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
>
--
Regards,
Oleksij
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^ permalink raw reply
* PM regression with LED changes in next-20161109
From: Jacek Anaszewski @ 2016-11-12 19:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3eb60c78-d891-27e5-6b7b-a54a5b547a1c@redhat.com>
Hi,
On 11/12/2016 11:33 AM, Hans de Goede wrote:
> Hi,
>
> On 12-11-16 11:24, Jacek Anaszewski wrote:
>> Hi,
>>
>> On 11/11/2016 08:28 PM, Hans de Goede wrote:
>>> Hi,
>>>
>>> On 11-11-16 18:03, Jacek Anaszewski wrote:
>>>> On 11/11/2016 01:01 PM, Pavel Machek wrote:
>>>>> On Thu 2016-11-10 22:34:07, Jacek Anaszewski wrote:
>>>>>> Hi,
>>>>>>
>>>>>> On 11/10/2016 09:29 PM, Pavel Machek wrote:
>>>>>>> On Thu 2016-11-10 10:55:37, Tony Lindgren wrote:
>>>>>>>> * Pavel Machek <pavel@ucw.cz> [161110 09:29]:
>>>>>>>>> Hi!
>>>>>>>>>
>>>>>>>>>>>>> Looks like commit 883d32ce3385 ("leds: core: Add support for
>>>>>>>>>>>>> poll()ing
>>>>>>>>>>>>> the sysfs brightness attr for changes.") breaks runtime PM
>>>>>>>>>>>>> for me.
>>>>>>>>>>>>>
>>>>>>>>>>>>> On my omap dm3730 based test system, idle power consumption
>>>>>>>>>>>>> is over 70
>>>>>>>>>>>>> times higher now with this patch! It goes from about 6mW for
>>>>>>>>>>>>> the core
>>>>>>>>>>>>> system to over 440mW during idle meaning there's some busy
>>>>>>>>>>>>> timer now
>>>>>>>>>>>>> active.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Reverting this patch fixes the issue. Any ideas?
>>>>>>>>>
>>>>>>>>> Are you using any LED that toggles with high frequency? Like
>>>>>>>>> perhaps
>>>>>>>>> LED that is lit when CPU is active?
>>>>>>>>
>>>>>>>> Yeah one of them seems to have cpu0 as the default trigger.
>>>>>>>
>>>>>>> Aha. Its quite obvious we don't want to notify sysfs each time that
>>>>>>> one is toggled, right?
>>>>>>>
>>>>>>> IMO brightness should display max brightness for the trigger, as
>>>>>>> Hans
>>>>>>> suggested, anything else is madness for trigger such as cpu
>>>>>>> activity.
>>>>>>
>>>>>> Are you suggesting that we should revert changes introduced
>>>>>> by below patch?
>>>>>>
>>>>>> commit 29d76dfa29fe22583aefddccda0bc56aa81035dc
>>>>>> Author: Henrique de Moraes Holschuh <hmh@hmh.eng.br>
>>>>>> Date: Tue Mar 18 09:47:48 2008 +0000
>>>>>>
>>>>>> leds: Add support to leds with readable status
>>>>>>
>>>>>> Some led hardware allows drivers to query the led state, and
>>>>>> this patch
>>>>>> adds a hook to let the led class take advantage of that
>>>>>> information when
>>>>>> available.
>>>>>>
>>>>>> Without this functionality, when access to the led hardware is
>>>>>> not
>>>>>> exclusive (i.e. firmware or hardware might change its state
>>>>>> behind the
>>>>>> kernel's back), reality goes out of sync with the led class'
>>>>>> idea of
>>>>>> what
>>>>>> the led is doing, which is annoying at best.
>>>>>
>>>>> Hmm. So userland can read the LED state, and it can get _some_ value
>>>>> back, but it can not know if it is current state or not.
>>>>>
>>>>> I don't think that's a good interface. I see it is from 2008... is
>>>>> someone using it? Maybe it is too late for revert.
>>>>
>>>> I can imagine it being used in flash LED use case. E.g. one
>>>> could use oneshot trigger to trigger flash strobe, and then
>>>> he could periodically read brightness file to check, for whatever
>>>> reason, whether the flash is strobing.
>>>>
>>>>> But I'd certainly not extend it with poll.
>>>>
>>>> We could add a dedicated file e.g. hw_brightness_change for that
>>>> (maybe someone will have a better candidate for the file name).
>>>
>>> Why a dedicated file? Are we going to mirror brightness here
>>> wrt r/w (show/store) behavior ? If not userspace now needs
>>> 2 open fds which is not really nice. If we are and we are
>>> not going to use poll for something else on brightness itself
>>> then why not just poll directly on brightness ?
>>
>> My main concern is that reporting only hw brightness changes
>> wouldn't be consistent with general brightness file purpose.
>> One could expect that brightness changes made by triggers
>> should be also reported.
>
> Ok, I agree that not notifying poll() while an actual
> read() would result in a different value is not really good
> semantics.
>
> I don't like to call it hw_brightness_change though, as
> mentioned before I believe that if we were to start with
> a clean slate we would make the brightness file's read/write
> behavior more a mirror of itself.
>
> So I would like to propose creating a new read-write
> user_brightness file.
>
> The write behavior would be 100% identical to the brightness
> file (in code terms it will call the same store function).
>
> The the read behavior otoh will be different: it will shows
> the last brightness as set by the user, this would show the
> read behavior we really want of brightness: show the real
> brightness when not blinking / triggers are active and show
> the brightness used when on when blinking / triggers are active.
>
> We could then add poll support on this new user_brightness
> file, thus avoiding the problem with the extra cpu-load on
> notifications on blinking / triggers.
I agree that user_brightness allows to solve the issues you raised
about inconsistent write and read brightness' semantics
(which is not that painful IMHO).
Reporting non-user brightness changes on user_brightness file
doesn't sound reasonable though. Also, how would we read the
brightness set by the firmware? We'd have to read brightness
file, so still two files would have to be opened which is
a second drawback of this approach.
Having no difference in this area between the two approaches
I'm still in favour of the read-only file for notifying
brightness changes procured by hardware.
>> I'd make it only readable, so it wouldn't mirror brightness
>> file behavior.
>
> Then userspace which wants to be able to read + write + poll
> the brightness again needs to open 2 fds, as suggested
> above for the new user_brightness file it will be easy
> to just make it mimic the brightness file write behavior
> and then userspace only needs to open one fd.
>
> Regards,
>
> Hans
>
>
>
>
>>
>> Its purpose would be clear: notify hw brightness changes
>> and provide the brightness value that was set by the hardware
>> last time. It implies that this value could be different from
>> the one the brightness file reports. E.g. hw could have changed
>> brightness, which could be later updated through brightness
>> file, but hw_brightness_change would still report brightness level
>> that was set by the hardware last time. It could be useful
>> e.g. in case of showing the difference between the desired
>> value and the currently allowed configuration (e.g. if the
>> firmware automatically adjusted the value set by the user).
>>
>
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* [PATCH v2 1/2] arm64: dts: Add level for cpu dt node for exynos7
From: Krzysztof Kozlowski @ 2016-11-12 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGOxZ50Ttd1hP0x+Z527wc7mLLpz+Dom0TXFk08+mL0vnaxWwA@mail.gmail.com>
On Sat, Nov 12, 2016 at 6:00 PM, Alim Akhtar <alim.akhtar@gmail.com> wrote:
> Hi Javier,
>
> On Sat, Nov 12, 2016 at 7:54 PM, Javier Martinez Canillas
> <javier@osg.samsung.com> wrote:
>> Hello Alim,
>>
>> On 11/12/2016 07:17 AM, Alim Akhtar wrote:
>>> This patch adds level for cpu dt node, so that these levels can be used
>>
>> Do you mean s/level/label here? I'm asking because you are using level
>> consistently in the subject line and commit message but I'm not sure
>> what it means in this context.
>>
>
> Ah!! my bad. Its __label__. If required, will respin.
> Thanks for review.
I think there is no need of respin because this should be squashed
with previous patch. This is quite small and there are no functional
changes here (labels are transparent, except of course conflict
cases). Without the 2/2, this patch does not have much sense yet.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 1/4] ARM: dts: mxs: Add new M28EVK manufacturer compat
From: Marek Vasut @ 2016-11-12 18:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161024065002.GX30578@tiger>
On 10/24/2016 08:50 AM, Shawn Guo wrote:
> On Sun, Oct 23, 2016 at 03:30:32PM +0200, Marek Vasut wrote:
>> On 10/23/2016 03:01 PM, Shawn Guo wrote:
>>> On Mon, Sep 19, 2016 at 11:40:41PM +0200, Marek Vasut wrote:
>>>> The board is now manufactured by Aries Embedded GmbH, update compat string.
>>>>
>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>> Cc: Shawn Guo <shawnguo@kernel.org>
>>>> ---
>>>> arch/arm/boot/dts/imx28-m28.dtsi | 4 ++--
>>>> arch/arm/boot/dts/imx28-m28evk.dts | 4 ++--
>>>> 2 files changed, 4 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
>>>> index 214bb15..a69856e 100644
>>>> --- a/arch/arm/boot/dts/imx28-m28.dtsi
>>>> +++ b/arch/arm/boot/dts/imx28-m28.dtsi
>>>> @@ -12,8 +12,8 @@
>>>> #include "imx28.dtsi"
>>>>
>>>> / {
>>>> - model = "DENX M28";
>>>> - compatible = "denx,m28", "fsl,imx28";
>>>> + model = "Aries/DENX M28";
>>>> + compatible = "aries,m28", "denx,m28", "fsl,imx28";
>>>
>>> Do we have an entry for Aries Embedded GmbH in vendor-prefixes.txt?
>>
>> The patch was submitted, not yet applied though:
>> http://www.spinics.net/lists/arm-kernel/msg533000.html
>
> Okay. Ping me when it gets applied.
Ping, it's in.
http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings/vendor-prefixes.txt?id=553a8bcd6a103f518d1f6a021b8442d8dfec5e6d
--
Best regards,
Marek Vasut
^ permalink raw reply
* [PATCH v2] staging: vc04_services: rework ioctl code path
From: Stefan Wahren @ 2016-11-12 17:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111061531.23507-1-mzoran@crowfest.net>
Hi Michael,
> Michael Zoran <mzoran@crowfest.net> hat am 11. November 2016 um 07:15
> geschrieben:
>
>
> VCHIQ/vc04_services has a userland device interface
> that includes ioctls. The current ioctl implementation
> is a single monolithic function over 1,000+ lines
> that handles 17 different ioctls through a complex
> maze of switch and if statements.
>
> The change reimplements that code path by breaking
> up the code into smaller, easier to maintain functions
> and uses a dispatch table to invoke the correct function.
nice. But please always use scripts/checkpatch.pl before submitting your
patches.
And yes it is not necessary to fix all "line over 80 chars" warnings.
^ permalink raw reply
* [PATCH 2/6] pinctrl: rockchip: add support for rk1108
From: 陈豪 @ 2016-11-12 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478176470-11956-1-git-send-email-andy.yan@rock-chips.com>
2016-11-03 20:34 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
> Add basic support for rk1108 soc
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
>
> drivers/pinctrl/pinctrl-rockchip.c | 27 ++++++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 49bf7dc..9f324b1 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -59,6 +59,7 @@
> #define GPIO_LS_SYNC 0x60
>
> enum rockchip_pinctrl_type {
> + RK1108,
> RK2928,
> RK3066B,
> RK3188,
> @@ -1123,6 +1124,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
> return !(data & BIT(bit))
> ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
> : PIN_CONFIG_BIAS_DISABLE;
> + case RK1108:
> case RK3188:
> case RK3288:
> case RK3368:
> @@ -1169,6 +1171,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
>
> spin_unlock_irqrestore(&bank->slock, flags);
> break;
> + case RK1108:
> case RK3188:
> case RK3288:
> case RK3368:
> @@ -1358,6 +1361,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
> pull == PIN_CONFIG_BIAS_DISABLE);
> case RK3066B:
> return pull ? false : true;
> + case RK1108:
> case RK3188:
> case RK3288:
> case RK3368:
> @@ -1385,7 +1389,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
> for (i = 0; i < num_configs; i++) {
> param = pinconf_to_config_param(configs[i]);
> arg = pinconf_to_config_argument(configs[i]);
> -
> switch (param) {
> case PIN_CONFIG_BIAS_DISABLE:
> rc = rockchip_set_pull(bank, pin - bank->pin_base,
> @@ -2455,6 +2458,26 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
> return 0;
> }
>
> +static struct rockchip_pin_bank rk1108_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
> +};
> +
> +static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
> + .pin_banks = rk1108_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
> + .label = "RK1108-GPIO",
> + .type = RK1108,
> + .grf_mux_offset = 0x10,
> + .pmu_mux_offset = 0x0,
> + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
> +};
> +
> static struct rockchip_pin_bank rk2928_pin_banks[] = {
> PIN_BANK(0, 32, "gpio0"),
> PIN_BANK(1, 32, "gpio1"),
> @@ -2684,6 +2707,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
> };
>
> static const struct of_device_id rockchip_pinctrl_dt_match[] = {
> + { .compatible = "rockchip,rk1108-pinctrl",
> + .data = (void *)&rk1108_pin_ctrl },
> { .compatible = "rockchip,rk2928-pinctrl",
> .data = (void *)&rk2928_pin_ctrl },
> { .compatible = "rockchip,rk3036-pinctrl",
> --
> 2.7.4
>
>
rk3288_calc_pull_reg_and_bit can't be used directly in rk1108.
rk1108 have a different PULL_PMU_OFFSET and PULL_OFFSET.
^ permalink raw reply
* [PATCH] drm/sun4i: constify component_ops structures
From: Julia Lawall @ 2016-11-12 17:19 UTC (permalink / raw)
To: linux-arm-kernel
These component_ops structures are only used as the second argument to
component_add and component_del, which are declared as const, so the
structures can be declared as const as well.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct component_ops i at p = { ... };
@ok1@
identifier r.i;
expression e1;
position p;
@@
component_add(e1,&i at p)
@ok2@
identifier r.i;
expression e1;
position p;
@@
component_del(e1, &i at p)
@bad@
position p != {r.p,ok1.p,ok2.p};
identifier r.i;
struct component_ops e;
@@
e at i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct component_ops i = { ... };
// </smpl>
The result of the size command before the change is (arm):
text data bss dec hex filename
5266 236 8 5510 1586 sun4i_backend.o
6393 236 8 6637 19ed sun4i_tcon.o
3700 368 8 4076 fec sun4i_tv.o
1668 108 0 1776 6f0 sun6i_drc.o
and after the change:
text data bss dec hex filename
5274 228 8 5510 1586 sun4i_backend.o
6401 228 8 6637 19ed sun4i_tcon.o
3708 360 8 4076 fec sun4i_tv.o
1676 100 0 1776 6f0 sun6i_drc.o
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 2 +-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 2 +-
drivers/gpu/drm/sun4i/sun4i_tv.c | 2 +-
drivers/gpu/drm/sun4i/sun6i_drc.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 7eb2a96..2e08f96 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -409,7 +409,7 @@ static void sun4i_backend_unbind(struct device *dev, struct device *master,
reset_control_assert(backend->reset);
}
-static struct component_ops sun4i_backend_ops = {
+static const struct component_ops sun4i_backend_ops = {
.bind = sun4i_backend_bind,
.unbind = sun4i_backend_unbind,
};
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c6afb24..ea2906f 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -545,7 +545,7 @@ static void sun4i_tcon_unbind(struct device *dev, struct device *master,
sun4i_tcon_free_clocks(tcon);
}
-static struct component_ops sun4i_tcon_ops = {
+static const struct component_ops sun4i_tcon_ops = {
.bind = sun4i_tcon_bind,
.unbind = sun4i_tcon_unbind,
};
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 1dd3d9e..d430b331 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -667,7 +667,7 @@ static void sun4i_tv_unbind(struct device *dev, struct device *master,
clk_disable_unprepare(tv->clk);
}
-static struct component_ops sun4i_tv_ops = {
+static const struct component_ops sun4i_tv_ops = {
.bind = sun4i_tv_bind,
.unbind = sun4i_tv_unbind,
};
diff --git a/drivers/gpu/drm/sun4i/sun6i_drc.c b/drivers/gpu/drm/sun4i/sun6i_drc.c
index 6ef707c..09bba85 100644
--- a/drivers/gpu/drm/sun4i/sun6i_drc.c
+++ b/drivers/gpu/drm/sun4i/sun6i_drc.c
@@ -80,7 +80,7 @@ static void sun6i_drc_unbind(struct device *dev, struct device *master,
reset_control_assert(drc->reset);
}
-static struct component_ops sun6i_drc_ops = {
+static const struct component_ops sun6i_drc_ops = {
.bind = sun6i_drc_bind,
.unbind = sun6i_drc_unbind,
};
^ permalink raw reply related
* [PATCH v2 3/6] iio: adc: Add support for STM32 ADC
From: Jonathan Cameron @ 2016-11-12 17:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478794738-28933-4-git-send-email-fabrice.gasnier@st.com>
On 10/11/16 16:18, Fabrice Gasnier wrote:
> This patch adds support for STMicroelectronics STM32 MCU's analog to
> digital converter.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Nice and clean - few minor things inline.
Jonathan
> ---
> drivers/iio/adc/Kconfig | 10 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/stm32-adc.c | 525 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 536 insertions(+)
> create mode 100644 drivers/iio/adc/stm32-adc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 7edcf32..61ba674 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -419,6 +419,16 @@ config ROCKCHIP_SARADC
> To compile this driver as a module, choose M here: the
> module will be called rockchip_saradc.
>
> +config STM32_ADC
> + tristate "STMicroelectronics STM32 adc"
> + depends on MFD_STM32_ADC
> + help
> + Say yes here to build support for STMicroelectronics stm32 Analog
> + to Digital Converter (ADC).
> +
> + This driver can also be built as a module. If so, the module
> + will be called stm32-adc.
> +
> config STX104
> tristate "Apex Embedded Systems STX104 driver"
> depends on X86 && ISA_BUS_API
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index 7a40c04..df7a221 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -41,6 +41,7 @@ obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
> obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o
> obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
> obj-$(CONFIG_STX104) += stx104.o
> +obj-$(CONFIG_STM32_ADC) += stm32-adc.o
> obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
> obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
> obj-$(CONFIG_TI_ADC12138) += ti-adc12138.o
> diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
> new file mode 100644
> index 0000000..2be5fee
> --- /dev/null
> +++ b/drivers/iio/adc/stm32-adc.c
> @@ -0,0 +1,525 @@
> +/*
> + * This file is part of STM32 ADC driver
> + *
> + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
> + * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
> + *
> + * License type: GPLv2
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/iio/iio.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/mfd/stm32-adc-core.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +
> +/* STM32F4 - Registers for each ADC instance */
Not really sure the X adds anything in these, but doesn't do much harm
I guess ;)
> +#define STM32F4_ADCX_SR 0x00
> +#define STM32F4_ADCX_CR1 0x04
> +#define STM32F4_ADCX_CR2 0x08
> +#define STM32F4_ADCX_SMPR1 0x0C
> +#define STM32F4_ADCX_SMPR2 0x10
> +#define STM32F4_ADCX_HTR 0x24
> +#define STM32F4_ADCX_LTR 0x28
> +#define STM32F4_ADCX_SQR1 0x2C
> +#define STM32F4_ADCX_SQR2 0x30
> +#define STM32F4_ADCX_SQR3 0x34
> +#define STM32F4_ADCX_JSQR 0x38
> +#define STM32F4_ADCX_JDR1 0x3C
> +#define STM32F4_ADCX_JDR2 0x40
> +#define STM32F4_ADCX_JDR3 0x44
> +#define STM32F4_ADCX_JDR4 0x48
> +#define STM32F4_ADCX_DR 0x4C
> +
> +/* STM32F4_ADCX_SR - bit fields */
> +#define STM32F4_OVR BIT(5)
> +#define STM32F4_STRT BIT(4)
> +#define STM32F4_EOC BIT(1)
> +
> +/* STM32F4_ADCX_CR1 - bit fields */
> +#define STM32F4_OVRIE BIT(26)
> +#define STM32F4_SCAN BIT(8)
> +#define STM32F4_EOCIE BIT(5)
> +
> +/* STM32F4_ADCX_CR2 - bit fields */
> +#define STM32F4_SWSTART BIT(30)
> +#define STM32F4_EXTEN_MASK GENMASK(29, 28)
> +#define STM32F4_EOCS BIT(10)
> +#define STM32F4_ADON BIT(0)
> +
> +/* STM32F4_ADCX_SQR1 - bit fields */
> +#define STM32F4_L_SHIFT 20
> +#define STM32F4_L_MASK GENMASK(23, 20)
> +
> +/* STM32F4_ADCX_SQR3 - bit fields */
> +#define STM32F4_SQ1_SHIFT 0
> +#define STM32F4_SQ1_MASK GENMASK(4, 0)
> +
> +#define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
> +#define STM32_ADC_TIMEOUT_US 100000
> +#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
> +
> +/**
> + * struct stm32_adc - private data of each ADC IIO instance
> + * @common: reference to ADC block common data
> + * @offset: ADC instance register offset in ADC block
> + * @completion: end of single conversion completion
> + * @buffer: data buffer
> + * @clk: optional adc clock, for this adc instance
> + * @irq: interrupt for this adc instance
> + * @lock: spinlock
> + */
> +struct stm32_adc {
> + struct stm32_adc_common *common;
> + u32 offset;
> + struct completion completion;
> + u16 *buffer;
> + struct clk *clk;
> + int irq;
> + spinlock_t lock; /* interrupt lock */
> +};
> +
> +/**
> + * struct stm32_adc_chan_spec - specification of stm32 adc channel
> + * @type: IIO channel type
> + * @channel: channel number (single ended)
> + * @name: channel name (single ended)
> + */
> +struct stm32_adc_chan_spec {
> + enum iio_chan_type type;
> + int channel;
> + const char *name;
> +};
> +
> +/* Input definitions common for all STM32F4 instances */
> +static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = {
> + { IIO_VOLTAGE, 0, "in0" },
> + { IIO_VOLTAGE, 1, "in1" },
> + { IIO_VOLTAGE, 2, "in2" },
> + { IIO_VOLTAGE, 3, "in3" },
> + { IIO_VOLTAGE, 4, "in4" },
> + { IIO_VOLTAGE, 5, "in5" },
> + { IIO_VOLTAGE, 6, "in6" },
> + { IIO_VOLTAGE, 7, "in7" },
> + { IIO_VOLTAGE, 8, "in8" },
> + { IIO_VOLTAGE, 9, "in9" },
> + { IIO_VOLTAGE, 10, "in10" },
> + { IIO_VOLTAGE, 11, "in11" },
> + { IIO_VOLTAGE, 12, "in12" },
> + { IIO_VOLTAGE, 13, "in13" },
> + { IIO_VOLTAGE, 14, "in14" },
> + { IIO_VOLTAGE, 15, "in15" },
> +};
> +
> +/**
> + * STM32 ADC registers access routines
> + * @adc: stm32 adc instance
> + * @reg: reg offset in adc instance
> + *
> + * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
> + * for adc1, adc2 and adc3.
> + */
> +static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
> +{
> + return readl_relaxed(adc->common->base + adc->offset + reg);
> +}
> +
> +static u32 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
> +{
> + return readw_relaxed(adc->common->base + adc->offset + reg);
> +}
> +
> +static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
> +{
> + writel_relaxed(val, adc->common->base + adc->offset + reg);
> +}
> +
> +static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&adc->lock, flags);
> + stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
> + spin_unlock_irqrestore(&adc->lock, flags);
> +}
> +
> +static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&adc->lock, flags);
> + stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
> + spin_unlock_irqrestore(&adc->lock, flags);
> +}
> +
> +/**
> + * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
> + * @adc: stm32 adc instance
> + */
> +static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
> +{
> + stm32_adc_set_bits(adc, STM32F4_ADCX_CR1, STM32F4_EOCIE);
> +};
> +
> +/**
> + * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
> + * @adc: stm32 adc instance
> + */
> +static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
> +{
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR1, STM32F4_EOCIE);
> +}
> +
> +/**
> + * stm32_adc_start_conv() - Start conversions for regular channels.
> + * @adc: stm32 adc instance
> + */
> +static void stm32_adc_start_conv(struct stm32_adc *adc)
> +{
> + stm32_adc_set_bits(adc, STM32F4_ADCX_CR1, STM32F4_SCAN);
> + stm32_adc_set_bits(adc, STM32F4_ADCX_CR2, STM32F4_EOCS | STM32F4_ADON);
> +
> + /* Wait for Power-up time (tSTAB from datasheet) */
> + usleep_range(2, 3);
> +
> + /* Software start ? (e.g. trigger detection disabled ?) */
> + if (!(stm32_adc_readl(adc, STM32F4_ADCX_CR2) & STM32F4_EXTEN_MASK))
> + stm32_adc_set_bits(adc, STM32F4_ADCX_CR2, STM32F4_SWSTART);
> +}
> +
> +static void stm32_adc_stop_conv(struct stm32_adc *adc)
> +{
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2, STM32F4_EXTEN_MASK);
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_SR, STM32F4_STRT);
> +
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR1, STM32F4_SCAN);
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2, STM32F4_ADON);
> +}
> +
> +/**
> + * stm32_adc_single_conv() - Performs a single conversion
> + * @indio_dev: IIO device
> + * @chan: IIO channel
> + * @res: conversion result
> + *
> + * The function performs a single conversion on a given channel:
> + * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
> + * - Use SW trigger
> + * - Start conversion, then wait for interrupt completion.
> + */
> +static int stm32_adc_single_conv(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + int *res)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + long timeout;
> + u32 val;
> + u16 result;
> + int ret;
> +
> + reinit_completion(&adc->completion);
> +
> + adc->buffer = &result;
> +
> + /* Program chan number in regular sequence */
> + val = stm32_adc_readl(adc, STM32F4_ADCX_SQR3);
> + val &= ~STM32F4_SQ1_MASK;
> + val |= chan->channel << STM32F4_SQ1_SHIFT;
> + stm32_adc_writel(adc, STM32F4_ADCX_SQR3, val);
> +
> + /* Set regular sequence len (0 for 1 conversion) */
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_SQR1, STM32F4_L_MASK);
> +
> + /* Trigger detection disabled (conversion can be launched in SW) */
> + stm32_adc_clr_bits(adc, STM32F4_ADCX_CR2, STM32F4_EXTEN_MASK);
> +
> + stm32_adc_conv_irq_enable(adc);
> +
> + stm32_adc_start_conv(adc);
> +
> + timeout = wait_for_completion_interruptible_timeout(
> + &adc->completion, STM32_ADC_TIMEOUT);
> + if (timeout == 0) {
> + dev_warn(&indio_dev->dev, "Conversion timed out!\n");
> + ret = -ETIMEDOUT;
> + } else if (timeout < 0) {
> + dev_warn(&indio_dev->dev, "Interrupted conversion!\n");
> + ret = -EINTR;
> + } else {
> + *res = result;
> + ret = IIO_VAL_INT;
> + }
> +
> + stm32_adc_stop_conv(adc);
> +
> + stm32_adc_conv_irq_disable(adc);
> +
> + return ret;
> +}
> +
> +static int stm32_adc_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long mask)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> + int ret = -EINVAL;
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + ret = iio_device_claim_direct_mode(indio_dev);
> + if (ret)
> + return ret;
> + if (chan->type == IIO_VOLTAGE)
> + ret = stm32_adc_single_conv(indio_dev, chan, val);
> + else
> + ret = -EINVAL;
> + iio_device_release_direct_mode(indio_dev);
return directly here. Basically always preferred to return directly if
there is not cleanup to be done.
> + break;
> + case IIO_CHAN_INFO_SCALE:
> + *val = adc->common->vref_mv;
> + *val2 = chan->scan_type.realbits;
> + ret = IIO_VAL_FRACTIONAL_LOG2;
return directly here.
> + break;
> + default:
return -EINVAL here.
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static irqreturn_t stm32_adc_isr(int irq, void *data)
> +{
> + struct stm32_adc *adc = data;
> + u32 status = stm32_adc_readl(adc, STM32F4_ADCX_SR);
> + irqreturn_t ret = IRQ_NONE;
> +
> + if (status & STM32F4_EOC) {
> + *adc->buffer = stm32_adc_readw(adc, STM32F4_ADCX_DR);
> + complete(&adc->completion);
> + ret = IRQ_HANDLED;
Slightly tidier to return IRQ_HANDLED here and directly return
IRQ_NONE below.
> + }
> +
> + return ret;
> +}
> +
> +static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
> + const struct of_phandle_args *iiospec)
> +{
> + int i;
> +
> + for (i = 0; i < indio_dev->num_channels; i++)
> + if (indio_dev->channels[i].channel == iiospec->args[0])
> + return i;
> +
> + return -EINVAL;
> +}
> +
> +/**
> + * stm32_adc_debugfs_reg_access - read or write register value
> + *
> + * To read a value from an ADC register:
> + * echo [ADC reg offset] > direct_reg_access
> + * cat direct_reg_access
> + *
> + * To write a value in a ADC register:
> + * echo [ADC_reg_offset] [value] > direct_reg_access
> + */
> +static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
> + unsigned reg, unsigned writeval,
> + unsigned *readval)
> +{
> + struct stm32_adc *adc = iio_priv(indio_dev);
> +
> + if (!readval)
> + stm32_adc_writel(adc, reg, writeval);
> + else
> + *readval = stm32_adc_readl(adc, reg);
> +
> + return 0;
> +}
> +
> +static const struct iio_info stm32_adc_iio_info = {
> + .read_raw = stm32_adc_read_raw,
> + .debugfs_reg_access = stm32_adc_debugfs_reg_access,
> + .of_xlate = stm32_adc_of_xlate,
> + .driver_module = THIS_MODULE,
> +};
> +
> +static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
> + struct iio_chan_spec *chan,
> + const struct stm32_adc_chan_spec *channel,
> + int scan_index)
> +{
> + chan->type = channel->type;
> + chan->channel = channel->channel;
> + chan->datasheet_name = channel->name;
> + chan->extend_name = channel->name;
Don't set extend_name. That name doesn't add sufficient information to
make it worth adding custom ABI to the userspace interface.
> + chan->scan_index = scan_index;
> + chan->indexed = 1;
> + chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
> + chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
> + chan->scan_type.sign = 'u';
> + chan->scan_type.realbits = 12;
> + chan->scan_type.storagebits = 16;
> +}
> +
> +static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
> +{
> + struct device_node *node = indio_dev->dev.of_node;
> + struct property *prop;
> + const __be32 *cur;
> + struct iio_chan_spec *channels;
> + int scan_index = 0, num_channels;
> + u32 val;
> +
> + num_channels = of_property_count_u32_elems(node, "st,adc-channels");
> + if (num_channels < 0 ||
> + num_channels >= ARRAY_SIZE(stm32f4_adc123_channels)) {
> + dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
> + return num_channels < 0 ? num_channels : -EINVAL;
> + }
> +
> + channels = devm_kcalloc(&indio_dev->dev, num_channels,
> + sizeof(struct iio_chan_spec), GFP_KERNEL);
> + if (!channels)
> + return -ENOMEM;
> +
> + of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
> + if (val >= ARRAY_SIZE(stm32f4_adc123_channels)) {
> + dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
> + return -EINVAL;
> + }
> + stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
> + &stm32f4_adc123_channels[val],
> + scan_index);
> + scan_index++;
> + }
> +
> + indio_dev->num_channels = scan_index;
> + indio_dev->channels = channels;
> +
> + return 0;
> +}
> +
> +static int stm32_adc_probe(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev;
> + struct stm32_adc *adc;
> + int ret;
> +
> + if (!pdev->dev.of_node)
> + return -ENODEV;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
> + if (!indio_dev)
> + return -ENOMEM;
> +
> + adc = iio_priv(indio_dev);
> + adc->common = dev_get_drvdata(pdev->dev.parent);
> + spin_lock_init(&adc->lock);
> + init_completion(&adc->completion);
> +
> + indio_dev->name = dev_name(&pdev->dev);
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->info = &stm32_adc_iio_info;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> +
> + platform_set_drvdata(pdev, adc);
> +
> + ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
> + if (ret != 0) {
> + dev_err(&pdev->dev, "missing reg property\n");
> + return -EINVAL;
> + }
> +
> + adc->irq = platform_get_irq(pdev, 0);
> + if (adc->irq < 0) {
> + dev_err(&pdev->dev, "failed to get irq\n");
> + return adc->irq;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
> + 0, pdev->name, adc);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to request IRQ\n");
> + return ret;
> + }
> +
> + adc->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(adc->clk)) {
Could it concievably be deferred? Would be happier if this explicitly
checked for -ENODEV or whatever gets returned when not clock has
been specified.
> + adc->clk = NULL;
> + dev_dbg(&pdev->dev, "No child clk found\n");
> + } else {
> + ret = clk_prepare_enable(adc->clk);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "clk enable failed\n");
> + return ret;
> + }
> + }
> +
> + ret = stm32_adc_chan_of_init(indio_dev);
> + if (ret < 0)
> + goto err_clk_disable;
> +
> + ret = devm_iio_device_register(&pdev->dev, indio_dev);
This use of devm registration is going to cause a race in the remove.
The userspace interface will not be removed until after the remove
function has run. That disables the clock thus leaving us a window
where we could try and access the device with no clock enabled.
Basic rule of thumb is that use of devm must not effect the ordering
of unrolling what you do in probe when it comes to remove.
(which more or less means that you can't use devm_iio_device_register
unless you have no remove at all).
> + if (ret) {
> + dev_err(&pdev->dev, "iio dev register failed\n");
> + goto err_clk_disable;
> + }
> +
> + return 0;
> +
> +err_clk_disable:
> + if (adc->clk)
> + clk_disable_unprepare(adc->clk);
> +
> + return ret;
> +}
> +
> +static int stm32_adc_remove(struct platform_device *pdev)
> +{
> + struct stm32_adc *adc = platform_get_drvdata(pdev);
> +
> + if (adc->clk)
> + clk_disable_unprepare(adc->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id stm32_adc_of_match[] = {
> + { .compatible = "st,stm32f4-adc" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
> +
> +static struct platform_driver stm32_adc_driver = {
> + .probe = stm32_adc_probe,
> + .remove = stm32_adc_remove,
> + .driver = {
> + .name = "stm32-adc",
> + .of_match_table = stm32_adc_of_match,
> + },
> +};
> +module_platform_driver(stm32_adc_driver);
> +
> +MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:stm32-adc");
>
^ permalink raw reply
* [PATCH v2 2/6] mfd: stm32-adc: Add support for stm32 ADC
From: Jonathan Cameron @ 2016-11-12 17:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478794738-28933-3-git-send-email-fabrice.gasnier@st.com>
On 10/11/16 16:18, Fabrice Gasnier wrote:
> Add core driver for STMicroelectronics STM32 ADC (Analog to Digital
> Converter). STM32 ADC can be composed of up to 3 ADCs with shared
> resources like clock prescaler, common interrupt line and analog
> reference voltage.
> This core driver basically manages shared resources.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Looks good to me (other than the build issue obviously ;)
The fun bit will be trying to keep the whole thing this clean as you
add the more 'interesting' functionality. *fingers crossed*
Acked-by: Jonathan Cameron <jic23@kernel.org>
> ---
> drivers/mfd/Kconfig | 14 ++
> drivers/mfd/Makefile | 1 +
> drivers/mfd/stm32-adc-core.c | 301 +++++++++++++++++++++++++++++++++++++
> include/linux/mfd/stm32-adc-core.h | 52 +++++++
> 4 files changed, 368 insertions(+)
> create mode 100644 drivers/mfd/stm32-adc-core.c
> create mode 100644 include/linux/mfd/stm32-adc-core.h
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index c6df644..2580cee 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -1152,6 +1152,20 @@ config MFD_PALMAS
> If you say yes here you get support for the Palmas
> series of PMIC chips from Texas Instruments.
>
> +config MFD_STM32_ADC
> + tristate "STMicroelectronics STM32 adc"
> + depends on ARCH_STM32 || COMPILE_TEST
> + depends on OF
> + select MFD_CORE
> + select REGULATOR
> + select REGULATOR_FIXED_VOLTAGE
> + help
> + Select this option to enable the core driver for STMicroelectronics
> + STM32 analog-to-digital converter (ADC).
> +
> + This driver can also be built as a module. If so, the module
> + will be called stm32-adc-core.
> +
> config TPS6105X
> tristate "TI TPS61050/61052 Boost Converters"
> depends on I2C
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 9834e66..4571506 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -185,6 +185,7 @@ obj-$(CONFIG_MFD_INTEL_LPSS_PCI) += intel-lpss-pci.o
> obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) += intel-lpss-acpi.o
> obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o
> obj-$(CONFIG_MFD_PALMAS) += palmas.o
> +obj-$(CONFIG_MFD_STM32_ADC) += stm32-adc-core.o
> obj-$(CONFIG_MFD_VIPERBOARD) += viperboard.o
> obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o
> obj-$(CONFIG_MFD_RK808) += rk808.o
> diff --git a/drivers/mfd/stm32-adc-core.c b/drivers/mfd/stm32-adc-core.c
> new file mode 100644
> index 0000000..bcf52fb
> --- /dev/null
> +++ b/drivers/mfd/stm32-adc-core.c
> @@ -0,0 +1,301 @@
> +/*
> + * This file is part of STM32 ADC driver
> + *
> + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
> + * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
> + *
> + * Inspired from: fsl-imx25-tsadc
> + *
> + * License type: GPLv2
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/interrupt.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/irqdesc.h>
> +#include <linux/irqdomain.h>
> +#include <linux/mfd/stm32-adc-core.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/slab.h>
> +
> +/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
> +#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
> +#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
> +
> +/* STM32F4_ADC_CSR - bit fields */
> +#define STM32F4_EOC3 BIT(17)
> +#define STM32F4_EOC2 BIT(9)
> +#define STM32F4_EOC1 BIT(1)
> +
> +/* STM32F4_ADC_CCR - bit fields */
> +#define STM32F4_ADC_ADCPRE_SHIFT 16
> +#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
> +
> +/* STM32 F4 maximum analog clock rate (from datasheet) */
> +#define STM32F4_ADC_MAX_CLK_RATE 36000000
> +
> +/**
> + * struct stm32_adc_priv - stm32 ADC core private data
> + * @irq: irq for ADC block
> + * @domain: irq domain reference
> + * @aclk: clock reference for the analog circuitry
> + * @vref: regulator reference
> + * @common: common data for all ADC instances
> + */
> +struct stm32_adc_priv {
> + int irq;
> + struct irq_domain *domain;
> + struct clk *aclk;
> + struct regulator *vref;
> + struct stm32_adc_common common;
> +};
> +
> +static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
> +{
> + return container_of(com, struct stm32_adc_priv, common);
> +}
> +
> +/* STM32F4 ADC internal common clock prescaler division ratios */
> +static int stm32f4_pclk_div[] = {2, 4, 6, 8};
> +
> +/**
> + * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
> + * @priv: stm32 ADC core private data
> + * Select clock prescaler used for analog conversions, before using ADC.
> + */
> +static int stm32f4_adc_clk_sel(struct platform_device *pdev,
> + struct stm32_adc_priv *priv)
> +{
> + unsigned long rate;
> + u32 val;
> + int i;
> +
> + rate = clk_get_rate(priv->aclk);
> + for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
> + if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
> + break;
> + }
> + if (i >= ARRAY_SIZE(stm32f4_pclk_div))
> + return -EINVAL;
> +
> + val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
> + val &= ~STM32F4_ADC_ADCPRE_MASK;
> + val |= i << STM32F4_ADC_ADCPRE_SHIFT;
> + writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
> +
> + dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
> + rate / (stm32f4_pclk_div[i] * 1000));
> +
> + return 0;
> +}
> +
> +/* ADC common interrupt for all instances */
> +static void stm32_adc_irq_handler(struct irq_desc *desc)
> +{
> + struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + u32 status;
> +
> + chained_irq_enter(chip, desc);
> + status = readl_relaxed(priv->common.base + STM32F4_ADC_CSR);
> +
> + if (status & STM32F4_EOC1)
> + generic_handle_irq(irq_find_mapping(priv->domain, 0));
> +
> + if (status & STM32F4_EOC2)
> + generic_handle_irq(irq_find_mapping(priv->domain, 1));
> +
> + if (status & STM32F4_EOC3)
> + generic_handle_irq(irq_find_mapping(priv->domain, 2));
> +
> + chained_irq_exit(chip, desc);
> +};
> +
> +static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
> + irq_hw_number_t hwirq)
> +{
> + irq_set_chip_data(irq, d->host_data);
> + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
> +
> + return 0;
> +}
> +
> +static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
> +{
> + irq_set_chip_and_handler(irq, NULL, NULL);
> + irq_set_chip_data(irq, NULL);
> +}
> +
> +static const struct irq_domain_ops stm32_adc_domain_ops = {
> + .map = stm32_adc_domain_map,
> + .unmap = stm32_adc_domain_unmap,
> + .xlate = irq_domain_xlate_onecell,
> +};
> +
> +static int stm32_adc_irq_probe(struct platform_device *pdev,
> + struct stm32_adc_priv *priv)
> +{
> + struct device_node *np = pdev->dev.of_node;
> +
> + priv->irq = platform_get_irq(pdev, 0);
> + if (priv->irq < 0) {
> + dev_err(&pdev->dev, "failed to get irq\n");
> + return priv->irq;
> + }
> +
> + priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
> + &stm32_adc_domain_ops,
> + priv);
> + if (!priv->domain) {
> + dev_err(&pdev->dev, "Failed to add irq domain\n");
> + return -ENOMEM;
> + }
> +
> + irq_set_chained_handler(priv->irq, stm32_adc_irq_handler);
> + irq_set_handler_data(priv->irq, priv);
> +
> + return 0;
> +}
> +
> +static void stm32_adc_irq_remove(struct platform_device *pdev,
> + struct stm32_adc_priv *priv)
> +{
> + int hwirq;
> +
> + for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
> + irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
> + irq_domain_remove(priv->domain);
> + irq_set_chained_handler(priv->irq, NULL);
> +}
> +
> +static int stm32_adc_probe(struct platform_device *pdev)
> +{
> + struct stm32_adc_priv *priv;
> + struct device_node *np = pdev->dev.of_node;
> + struct resource *res;
> + int ret;
> +
> + if (!pdev->dev.of_node)
> + return -ENODEV;
> +
> + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->common.base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(priv->common.base))
> + return PTR_ERR(priv->common.base);
> +
> + priv->vref = devm_regulator_get(&pdev->dev, "vref");
> + if (IS_ERR(priv->vref)) {
> + ret = PTR_ERR(priv->vref);
> + dev_err(&pdev->dev, "vref get failed, %d\n", ret);
> + return ret;
> + }
> +
> + ret = regulator_enable(priv->vref);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "vref enable failed\n");
> + return ret;
> + }
> +
> + ret = regulator_get_voltage(priv->vref);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
> + goto err_regulator_disable;
> + }
> + priv->common.vref_mv = ret / 1000;
> + dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
> +
> + priv->aclk = devm_clk_get(&pdev->dev, "adc");
> + if (IS_ERR(priv->aclk)) {
> + ret = PTR_ERR(priv->aclk);
> + dev_err(&pdev->dev, "Can't get 'adc' clock\n");
> + goto err_regulator_disable;
> + }
> +
> + ret = clk_prepare_enable(priv->aclk);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "adc clk enable failed\n");
> + goto err_regulator_disable;
> + }
> +
> + ret = stm32f4_adc_clk_sel(pdev, priv);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "adc clk selection failed\n");
> + goto err_clk_disable;
> + }
> +
> + ret = stm32_adc_irq_probe(pdev, priv);
> + if (ret < 0)
> + goto err_clk_disable;
> +
> + platform_set_drvdata(pdev, &priv->common);
> +
> + ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "failed to populate DT children\n");
> + goto err_irq_remove;
> + }
> +
> + return 0;
> +
> +err_irq_remove:
> + stm32_adc_irq_remove(pdev, priv);
> +
> +err_clk_disable:
> + clk_disable_unprepare(priv->aclk);
> +
> +err_regulator_disable:
> + regulator_disable(priv->vref);
> +
> + return ret;
> +}
> +
> +static int stm32_adc_remove(struct platform_device *pdev)
> +{
> + struct stm32_adc_common *common = platform_get_drvdata(pdev);
> + struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
> +
> + of_platform_depopulate(&pdev->dev);
> + stm32_adc_irq_remove(pdev, priv);
> + clk_disable_unprepare(priv->aclk);
> + regulator_disable(priv->vref);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id stm32_adc_of_match[] = {
> + { .compatible = "st,stm32f4-adc-core" },
> +};
> +MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
> +
> +static struct platform_driver stm32_adc_driver = {
> + .probe = stm32_adc_probe,
> + .remove = stm32_adc_remove,
> + .driver = {
> + .name = "stm32-adc-core",
> + .of_match_table = stm32_adc_of_match,
> + },
> +};
> +module_platform_driver(stm32_adc_driver);
> +
> +MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics STM32 ADC MFD driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:stm32-adc-core");
> diff --git a/include/linux/mfd/stm32-adc-core.h b/include/linux/mfd/stm32-adc-core.h
> new file mode 100644
> index 0000000..081fa5f
> --- /dev/null
> +++ b/include/linux/mfd/stm32-adc-core.h
> @@ -0,0 +1,52 @@
> +/*
> + * This file is part of STM32 ADC driver
> + *
> + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
> + * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
> + *
> + * License type: GPLv2
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> + * or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef __STM32_ADC_H
> +#define __STM32_ADC_H
> +
> +/*
> + * STM32 - ADC global register map
> + * ________________________________________________________
> + * | Offset | Register |
> + * --------------------------------------------------------
> + * | 0x000 | Master ADC1 |
> + * --------------------------------------------------------
> + * | 0x100 | Slave ADC2 |
> + * --------------------------------------------------------
> + * | 0x200 | Slave ADC3 |
> + * --------------------------------------------------------
> + * | 0x300 | Master & Slave common regs |
> + * --------------------------------------------------------
> + */
> +#define STM32_ADC_MAX_ADCS 3
> +#define STM32_ADCX_COMN_OFFSET 0x300
> +
> +/**
> + * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
> + * @base: control registers base cpu addr
> + * @vref_mv: vref voltage (mv)
> + */
> +struct stm32_adc_common {
> + void __iomem *base;
> + int vref_mv;
> +};
> +
> +#endif
>
^ permalink raw reply
* [PATCH] ARM: dts: Add minimal support for motorola droid 4 xt894
From: Tony Lindgren @ 2016-11-12 17:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161112165759.17316-1-tony@atomide.com>
* Tony Lindgren <tony@atomide.com> [161112 08:58]:
> Let's add minimal support for droid 4 with MMC and WLAN working.
> It can be booted with appended dtb using kexec to a state where
> MMC and WLAN work with currently no support for it's PMIC or
> display.
>
> Note that we are currently using fixed regulators as we don't
> have support for it's cpcap PMIC. I'll be posting regmap_spi
> based minimal cpcap patches later on for USB and the debug
> UART on droid 4 multiplexed with the USB connector.
I also posted some notes on the UART wiring at [0].
Regards,
Tony
[0] http://muru.com/linux/d4/
^ permalink raw reply
* [PATCH] soc/fsl: fix spelling mistakes in critical error messages
From: Colin King @ 2016-11-12 17:01 UTC (permalink / raw)
To: linux-arm-kernel
From: Colin Ian King <colin.king@canonical.com>
Trivial fix to spelling mistake "uncommited" to "uncommitted" in
critical error messages.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
drivers/soc/fsl/qbman/bman.c | 2 +-
drivers/soc/fsl/qbman/qman.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index ffa48fd..48b7eb6 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -391,7 +391,7 @@ static void bm_rcr_finish(struct bm_portal *portal)
i = bm_in(portal, BM_REG_RCR_PI_CINH) & (BM_RCR_SIZE - 1);
if (i != rcr_ptr2idx(rcr->cursor))
- pr_crit("losing uncommited RCR entries\n");
+ pr_crit("losing uncommitted RCR entries\n");
i = bm_in(portal, BM_REG_RCR_CI_CINH) & (BM_RCR_SIZE - 1);
if (i != rcr->ci)
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 119054b..deeacd5 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -443,7 +443,7 @@ static inline void qm_eqcr_finish(struct qm_portal *portal)
DPAA_ASSERT(!eqcr->busy);
if (pi != eqcr_ptr2idx(eqcr->cursor))
- pr_crit("losing uncommited EQCR entries\n");
+ pr_crit("losing uncommitted EQCR entries\n");
if (ci != eqcr->ci)
pr_crit("missing existing EQCR completions\n");
if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor))
--
2.10.2
^ permalink raw reply related
* [PATCH] ARM: dts: Add minimal support for motorola droid 4 xt894
From: Tony Lindgren @ 2016-11-12 16:57 UTC (permalink / raw)
To: linux-arm-kernel
Let's add minimal support for droid 4 with MMC and WLAN working.
It can be booted with appended dtb using kexec to a state where
MMC and WLAN work with currently no support for it's PMIC or
display.
Note that we are currently using fixed regulators as we don't
have support for it's cpcap PMIC. I'll be posting regmap_spi
based minimal cpcap patches later on for USB and the debug
UART on droid 4 multiplexed with the USB connector.
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/omap4-droid4-xt894.dts | 188 +++++++++++++++++++++++++++++++
2 files changed, 189 insertions(+)
create mode 100644 arch/arm/boot/dts/omap4-droid4-xt894.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -570,6 +570,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-sl50.dtb \
am335x-wega-rdk.dtb
dtb-$(CONFIG_ARCH_OMAP4) += \
+ omap4-droid4-xt894.dtb \
omap4-duovero-parlor.dtb \
omap4-kc1.dtb \
omap4-panda.dtb \
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
new file mode 100644
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -0,0 +1,188 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap443x.dtsi"
+
+/ {
+ model = "Motorola Droid 4 XT894";
+ compatible = "motorola,droid4", "ti,omap4430", "ti,omap4";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ /*
+ * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
+ * then 1023 - 1024 seems to contain mbm. For SRAM, see the notes
+ * below about SRAM and L3_ICLK2 being unused by default,
+ */
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x3fd00000>; /* 1021 MB */
+ };
+
+ /* CPCAP really supports 1650000 to 3400000 range */
+ vmmc: regulator-mmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ /* CPCAP really supports 3000000 to 3100000 range */
+ vemmc: regulator-emmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vemmc";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ /* CPCAP really supports 1650000 to 1950000 range */
+ wl12xx_vmmc: regulator-wl12xx {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1650000>;
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+};
+
+/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */
+&gpmc {
+ status = "disabled";
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc>;
+ bus-width = <4>;
+ cd-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */
+};
+
+&mmc2 {
+ vmmc-supply = <&vemmc>;
+ bus-width = <8>;
+ non-removable;
+};
+
+&mmc3 {
+ vmmc-supply = <&wl12xx_vmmc>;
+ interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0xde>;
+
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore at 2 {
+ compatible = "ti,wl1283";
+ reg = <2>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */
+ ref-clock-frequency = <26000000>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */
+&ocmcram {
+ status = "disabled";
+};
+
+&omap4_pmx_core {
+ usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins {
+ /* gpio_60 */
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
+ usb_ulpi_pins: pinmux_usb_ulpi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, MUX_MODE7)
+ OMAP4_IOPAD(0x198, MUX_MODE7)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0)
+ >;
+ };
+
+ /* usb0_otg_dp and usb0_otg_dm */
+ usb_utmi_pins: pinmux_usb_utmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+
+ /* uart3_tx_irtx and uart3_rx_irrx */
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, MUX_MODE7)
+ OMAP4_IOPAD(0x198, MUX_MODE7)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1ba, MUX_MODE2)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+};
+
+&omap4_pmx_wkup {
+ usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins {
+ /* gpio_wk0 */
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
+ >;
+ };
+};
+
+&uart3 {
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0x17c>;
+};
+
+/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+ power = <50>;
+};
--
2.10.2
^ permalink raw reply
* [PATCH RFC] mm: Add debug_virt_to_phys()
From: Nicolas Pitre @ 2016-11-12 16:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <55bd0bb5-c11c-12bc-7d73-520ae3901f03@gmail.com>
On Fri, 11 Nov 2016, Florian Fainelli wrote:
> Le 11/11/2016 ? 17:49, Nicolas Pitre a ?crit :
> > On Fri, 11 Nov 2016, Florian Fainelli wrote:
> >
> >> When CONFIG_DEBUG_VM is turned on, virt_to_phys() maps to
> >> debug_virt_to_phys() which helps catch vmalloc space addresses being
> >> passed. This is helpful in debugging bogus drivers that just assume
> >> linear mappings all over the place.
> >>
> >> For ARM, ARM64, Unicore32 and Microblaze, the architectures define
> >> __virt_to_phys() as being the functional implementation of the address
> >> translation, so we special case the debug stub to call into
> >> __virt_to_phys directly.
> >>
> >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> >> ---
> >> arch/arm/include/asm/memory.h | 4 ++++
> >> arch/arm64/include/asm/memory.h | 4 ++++
> >> include/asm-generic/memory_model.h | 4 ++++
> >> mm/debug.c | 15 +++++++++++++++
> >> 4 files changed, 27 insertions(+)
> >>
> >> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> >> index 76cbd9c674df..448dec9b8b00 100644
> >> --- a/arch/arm/include/asm/memory.h
> >> +++ b/arch/arm/include/asm/memory.h
> >> @@ -260,11 +260,15 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
> >> * translation for translating DMA addresses. Use the driver
> >> * DMA support - see dma-mapping.h.
> >> */
> >> +#ifndef CONFIG_DEBUG_VM
> >> #define virt_to_phys virt_to_phys
> >> static inline phys_addr_t virt_to_phys(const volatile void *x)
> >> {
> >> return __virt_to_phys((unsigned long)(x));
> >> }
> >> +#else
> >> +#define virt_to_phys debug_virt_to_phys
> >> +#endif
> > [...]
> >
> > Why don't you do something more like:
> >
> > static inline phys_addr_t virt_to_phys(const volatile void *x)
> > {
> > + debug_virt_to_phys(x);
> > return __virt_to_phys((unsigned long)(x));
> > }
> >
> > [...]
> >
> > static inline void debug_virt_to_phys(const void *address)
> > {
> > #ifdef CONFIG_DEBUG_VM
> > BUG_ON(is_vmalloc_addr(address));
> > #endif
> > }
> >
> > ?
>
> This is how I started doing it initially, but to get the
> is_vmalloc_addr() definition, we need to include linux/mm.h and then
> everything falls apart because of the include and dependencies chain. We
> could open code the is_vmalloc_addr() check because that's simple
> enough, but we still need VMALLOC_START and VMALLOC_END and to get there
> we need to include pgtable.h, and there are still some inclusion
> problems in doing so.
>
> The other reason was to avoid putting the same checks in architecture
> specific code, except for those like ARM/ARM64/Unicore32/Microblaze
> where I could not find a simple way to undefined virt_to_phys and
> redefine it to debug_virt_to_phys.
You could still move the check out of line like in your patch. But the
debug function doesn't have to be the one returning the translated
address. This has the advantage of cutting on the amount of ifdefery.
Nicolas
^ permalink raw reply
* [PATCH] ASoC: mioa701_wm9713: add missing white space in dev_err message
From: Colin King @ 2016-11-12 16:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Colin Ian King <colin.king@canonical.com>
There is a missing whitespace in the dev_err message between
"will" and "lead". Add the whitespace.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
sound/soc/pxa/mioa701_wm9713.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/pxa/mioa701_wm9713.c b/sound/soc/pxa/mioa701_wm9713.c
index d1661fa..0fe0abe 100644
--- a/sound/soc/pxa/mioa701_wm9713.c
+++ b/sound/soc/pxa/mioa701_wm9713.c
@@ -187,7 +187,7 @@ static int mioa701_wm9713_probe(struct platform_device *pdev)
mioa701.dev = &pdev->dev;
rc = devm_snd_soc_register_card(&pdev->dev, &mioa701);
if (!rc)
- dev_warn(&pdev->dev, "Be warned that incorrect mixers/muxes setup will"
+ dev_warn(&pdev->dev, "Be warned that incorrect mixers/muxes setup will "
"lead to overheating and possible destruction of your device."
" Do not use without a good knowledge of mio's board design!\n");
return rc;
--
2.10.2
^ permalink raw reply related
* [PATCH 0/6] Add basic support for support for Rockchip RK1108 SOC
From: 陈豪 @ 2016-11-12 16:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com>
patches 1-5 on rk1108-cvr-v10 board.
Tested-by: Jacob Chen <jacob2.chen@rock-chips.com>
2016-11-03 20:26 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
>
> RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core.
> It is designed for varies application scenario such as car DVR, sports
> DV, secure camera and UAV camera.
> This patch series add basic support for it, which can boot a board with
> initramfs into shell.
> More new feathers will come soon.
>
>
> Andy Yan (4):
> pinctrl: rockchip: add support for rk1108
> ARM: dts: add basic support for Rockchip RK1108 SOC
> ARM: add low level debug uart for rk1108
> ARM: dts: rockchip: add rockchip RK1108 Evaluation board
>
> Shawn Lin (2):
> dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description
> clk: rockchip: add clock controller for rk1108
>
> Documentation/devicetree/bindings/arm/rockchip.txt | 3 +
> .../devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
> arch/arm/Kconfig.debug | 30 ++
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/rk1108-evb.dts | 69 +++
> arch/arm/boot/dts/rk1108.dtsi | 420 +++++++++++++++++++
> arch/arm/mach-rockchip/rockchip.c | 1 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk-rk1108.c | 463 +++++++++++++++++++++
> drivers/clk/rockchip/clk.h | 14 +
> drivers/pinctrl/pinctrl-rockchip.c | 27 +-
> include/dt-bindings/clock/rk1108-cru.h | 308 ++++++++++++++
> 12 files changed, 1337 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/rk1108-evb.dts
> create mode 100644 arch/arm/boot/dts/rk1108.dtsi
> create mode 100644 drivers/clk/rockchip/clk-rk1108.c
> create mode 100644 include/dt-bindings/clock/rk1108-cru.h
>
> --
> 2.7.4
>
>
^ permalink raw reply
* [PATCH v2 1/2] arm64: dts: Add level for cpu dt node for exynos7
From: Alim Akhtar @ 2016-11-12 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8a63bfe0-b23c-3583-6e5e-c17fe412e34d@osg.samsung.com>
Hi Javier,
On Sat, Nov 12, 2016 at 7:54 PM, Javier Martinez Canillas
<javier@osg.samsung.com> wrote:
> Hello Alim,
>
> On 11/12/2016 07:17 AM, Alim Akhtar wrote:
>> This patch adds level for cpu dt node, so that these levels can be used
>
> Do you mean s/level/label here? I'm asking because you are using level
> consistently in the subject line and commit message but I'm not sure
> what it means in this context.
>
Ah!! my bad. Its __label__. If required, will respin.
Thanks for review.
>> as a phandle whenever required. For example, adding a "interrupt-affinity"
>> for arm pmu node.
>>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>
> The change looks good to me though.
>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
>
> Best regards,
> --
> Javier Martinez Canillas
> Open Source Group
> Samsung Research America
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Regards,
Alim
^ permalink raw reply
* [GIT PULL 3/3] Rockchip dts64 changes for 4.10
From: Heiko Stuebner @ 2016-11-12 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1698724.ZQnZMjf8xY@phil>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v4.10-rockchip-dts64-1
for you to fetch changes up to c49590691f3819bb6be3f77938ef39038eb76643:
arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" (2016-11-09 15:08:55 +0100)
----------------------------------------------------------------
64bit devicetree changes including the px5 evaluation board
a fix for wrong i2c registers on rk3368 a new nvmem cell and
power-domain on rk3399 as well as moving mmc frequency
properties to the more generic max-frequency one.
----------------------------------------------------------------
Andy Yan (2):
arm64: dts: rockchip: fix i2c resource error of rk3368
arm64: dts: rockchip: Add PX5 Evaluation board
Chris Zhong (1):
arm64: dts: rockchip: add powerdomain for typec on rk3399
Jaehoon Chung (1):
arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
Shawn Lin (2):
arm64: dts: rockchip: Add more properties for emmc on px5-evb
arm64: dts: rockchip: add sdmmc support for px5-evb
Ziyuan Xu (1):
arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399
Documentation/devicetree/bindings/arm/rockchip.txt | 8 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3368-orion-r68-meta.dts | 2 +-
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 314 +++++++++++++++++++++
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 18 +-
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 9 +-
6 files changed, 340 insertions(+), 12 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
^ permalink raw reply
* [GIT PULL 2/3] Rockchip dts32 changes for 4.10
From: Heiko Stuebner @ 2016-11-12 15:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1698724.ZQnZMjf8xY@phil>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v4.10-rockchip-dts32-1
for you to fetch changes up to 6a8883d614c7bede1075a4850139daa9723c291e:
ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" (2016-11-09 14:46:04 +0100)
----------------------------------------------------------------
32bit devicetree changes for Rockchip including removal of skeleton.dtsi
inclusion, missing unit names for memory nodes, various frequency
optimizations allowing for better performance on rk3066, the usage of
pin constants to bridge between the two numbering schemes used (gpio
controllers using 0-31 and pins being labeled A0-A7,..., D0-D7)
and UHS/HS modes for the mmc controllers on the popmetal board.
Two new boards, the PX3-based evaluation board, with the PX3 being an
industrial variant of the rk3188 soc and the Rikomagic MK808 board
based around the rk3066 are also added.
----------------------------------------------------------------
Andy Yan (3):
ARM: dts: rockchip: add rockchip PX3 Evaluation board
include: dt-bindings: Add GPIO pin index definition for rockchip pinctrl
ARM: dts: rockchip: use pin constants to describe gpios on Popmetal-RK3288
Finley Xiao (1):
ARM: dts: rockchip: update compatible strings for Rockchip efuse
Heiko Stuebner (2):
Merge branch 'v4.10-shared/clkids' into v4.10-armsoc/dts32
Merge branch 'v4.10-shared/pinctrl' into v4.10-armsoc/dts32
Jaehoon Chung (1):
ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
Javier Martinez Canillas (8):
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3036.dtsi
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk322x.dtsi
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3288.dtsi
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3xxx.dtsi
ARM: dts: rockchip: Add missing unit name to memory nodes in rk3036 boards
ARM: dts: rockchip: Add missing unit name to memory nodes in rk322x boards
ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards
ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx boards
Pawe? Jarosz (5):
clk: rockchip: Add binding ids for cpu and peri clocks on rk3066
ARM: dts: rockchip: initialize rk3066 PLL clock rate
devicetree: Add vendor prefix for Rikomagic
ARM: dts: rockchip: Add rk3066 MK808 board
ARM: dts: rockchip: Set sdmmc frequency at boot time for rk3066a
Shawn Lin (3):
ARM: dts: rockchip: remove always-on and boot-on from vcc_sd for px3-evb
ARM: dts: rockchip: Support UHS mode for SD card on PopMetal-RK3288 board
ARM: dts: rockchip: enable HS200/DDR52 mode for emmc on rk3288-popmetal
Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/rk3036-evb.dts | 2 +-
arch/arm/boot/dts/rk3036-kylin.dts | 2 +-
arch/arm/boot/dts/rk3036.dtsi | 10 +-
arch/arm/boot/dts/rk3066a-bqcurie2.dts | 2 +-
arch/arm/boot/dts/rk3066a-marsboard.dts | 2 +-
arch/arm/boot/dts/rk3066a-mk808.dts | 195 ++++++++++++
arch/arm/boot/dts/rk3066a-rayeager.dts | 2 +-
arch/arm/boot/dts/rk3066a.dtsi | 12 +-
arch/arm/boot/dts/rk3188-px3-evb.dts | 328 +++++++++++++++++++++
arch/arm/boot/dts/rk3188-radxarock.dts | 2 +-
arch/arm/boot/dts/rk3188.dtsi | 2 +-
arch/arm/boot/dts/rk3228-evb.dts | 2 +-
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
arch/arm/boot/dts/rk322x.dtsi | 6 +-
arch/arm/boot/dts/rk3288-evb.dtsi | 2 +-
arch/arm/boot/dts/rk3288-fennec.dts | 2 +-
arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 2 +-
arch/arm/boot/dts/rk3288-firefly.dtsi | 2 +-
arch/arm/boot/dts/rk3288-miqi.dts | 2 +-
arch/arm/boot/dts/rk3288-popmetal.dts | 34 ++-
arch/arm/boot/dts/rk3288-r89.dts | 2 +-
arch/arm/boot/dts/rk3288-rock2-som.dtsi | 2 +-
arch/arm/boot/dts/rk3288-veyron.dtsi | 2 +-
arch/arm/boot/dts/rk3288.dtsi | 14 +-
arch/arm/boot/dts/rk3xxx.dtsi | 4 +-
include/dt-bindings/clock/rk3188-cru-common.h | 8 +-
include/dt-bindings/pinctrl/rockchip.h | 33 +++
30 files changed, 639 insertions(+), 46 deletions(-)
create mode 100644 arch/arm/boot/dts/rk3066a-mk808.dts
create mode 100644 arch/arm/boot/dts/rk3188-px3-evb.dts
^ permalink raw reply
* [GIT PULL 1/3] Rockchip driver changes for 4.10
From: Heiko Stuebner @ 2016-11-12 15:34 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Kevin, Olof,
please find below and in the following two mails, Rockchip power-domain as
well as dts32 and dts64 changes for 4.10.
I don't think anything big stands out, just the usual mix of incremental
improvements, so if stuff looks ok please pull.
Thanks
Heiko
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v4.10-rockchip-drivers1
for you to fetch changes up to dabc0259db63338f0e64107cc92b2241f98a3284:
soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecell (2016-11-11 02:14:59 +0100)
----------------------------------------------------------------
Changes to the power-domain driver including counter presets now being set
by firmware on the rk3399, avoiding infite loops when powering on/off a
domain and actually returning an error if power-domain addition fails.
The last part requires usage of the (new in 4.9-rc1) pm_genpd_remove
functionality as well.
----------------------------------------------------------------
Caesar Wang (1):
soc: rockchip: power-domain: avoid infinite loop
Douglas Anderson (1):
soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down counts
Heiko Stuebner (1):
soc: rockchip: power-domain: use pm_genpd_remove in error cleanup
Tomeu Vizoso (1):
soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecell
drivers/soc/rockchip/pm_domains.c | 81 ++++++++++++++++++++++++++++++---------
1 file changed, 63 insertions(+), 18 deletions(-)
^ permalink raw reply
* [PATCH] ARM: dts: imx: Remove skeleton.dtsi
From: Fabio Estevam @ 2016-11-12 15:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@nxp.com>
As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark
skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx1.dtsi | 4 +++-
arch/arm/boot/dts/imx23.dtsi | 4 +++-
arch/arm/boot/dts/imx25.dtsi | 4 +++-
arch/arm/boot/dts/imx27.dtsi | 4 +++-
arch/arm/boot/dts/imx28.dtsi | 4 +++-
arch/arm/boot/dts/imx31.dtsi | 5 +++--
arch/arm/boot/dts/imx35.dtsi | 4 +++-
arch/arm/boot/dts/imx50.dtsi | 4 +++-
arch/arm/boot/dts/imx51.dtsi | 4 +++-
arch/arm/boot/dts/imx53.dtsi | 4 +++-
arch/arm/boot/dts/imx6qdl.dtsi | 5 +++--
arch/arm/boot/dts/imx6sl.dtsi | 4 +++-
arch/arm/boot/dts/imx6sx.dtsi | 4 +++-
arch/arm/boot/dts/imx6ul.dtsi | 4 +++-
arch/arm/boot/dts/imx7s.dtsi | 4 +++-
15 files changed, 45 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
index 22f5d1d..b792eee 100644
--- a/arch/arm/boot/dts/imx1.dtsi
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -9,7 +9,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx1-pinfunc.h"
#include <dt-bindings/clock/imx1-clock.h>
@@ -17,6 +16,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 8e1543f..ac2a9da 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -9,10 +9,12 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx23-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
interrupt-parent = <&icoll>;
aliases {
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index af6af87..831d09a 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -9,10 +9,12 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx25-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index f818ea4..9d8b596 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -9,7 +9,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx27-pinfunc.h"
#include <dt-bindings/clock/imx27-clock.h>
@@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 0ad893b..3aabf65 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -10,10 +10,12 @@
*/
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
#include "imx28-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
interrupt-parent = <&icoll>;
aliases {
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index 8d4c0e3..685916e 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -9,9 +9,10 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
serial0 = &uart1;
serial1 = &uart2;
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index f812d58..9f40e62 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -8,10 +8,12 @@
* Free Software Foundation.
*/
-#include "skeleton.dtsi"
#include "imx35-pinfunc.h"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 92a03bc..fe0221e 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -11,11 +11,13 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index d8efdab..33526ca 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -10,7 +10,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx51-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
@@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 88f9e09e..ca51dc0 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -10,7 +10,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "skeleton.dtsi"
#include "imx53-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
@@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 1bbd36f..bc3e12a 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -13,9 +13,10 @@
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
can0 = &can1;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 02378db..4fe5d0c 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -8,11 +8,13 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
-#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index bd9fe67..3926eb5 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -11,9 +11,11 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6sx-pinfunc.h"
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
can0 = &flexcan1;
can1 = &flexcan2;
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index c5c05fd..39845a7 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -11,9 +11,11 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6ul-pinfunc.h"
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
ethernet0 = &fec1;
ethernet1 = &fec2;
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 0d7d5ac..51dfcc1 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -46,9 +46,11 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx7d-pinfunc.h"
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
--
2.7.4
^ permalink raw reply related
* [PATCH] ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED
From: Stefan Wahren @ 2016-11-12 14:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111173821.21491-1-eric@anholt.net>
Hi Eric,
[add Gerd to CC]
> Eric Anholt <eric@anholt.net> hat am 11. November 2016 um 18:38 geschrieben:
>
>
> From: Andrea Merello <andrea.merello@gmail.com>
>
> We are incorrectly defining the pwr LED, attaching it to a gpio line
> that is wired to the Wi-Fi SDIO module (which fails due to this).
i agree with the intention of this patch, but is the upstream kernel really
affected? I can't see any compatible for the Wifi interface.
>
> The actual power LED is connected to the GPIO expander, which we don't
> expose currently.
>
> Thanks-to: Eric Anholt <eric@anholt.net> [for clarifying we can't control the
> LED]
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.")
Stefan
^ permalink raw reply
* [PATCH V6 2/3] ACPI: Add support for ResourceSource/IRQ domain mapping
From: Hanjun Guo @ 2016-11-12 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <713f102418c0fffacf67acb16dbdeec2@codeaurora.org>
On 11/12/2016 11:01 AM, agustinv at codeaurora.org wrote:
> Hey Lorenzo, Hanjun,
>
> On 2016-11-11 08:33, Hanjun Guo wrote:
>> Hi Lorenzo,
>>
>> On 11/11/2016 01:58 AM, Lorenzo Pieralisi wrote:
>>> On Thu, Nov 10, 2016 at 10:02:35AM -0500, agustinv at codeaurora.org wrote:
>>>> Hey Hanjun,
>>>>
>>>> On 2016-11-09 21:36, Hanjun Guo wrote:
>>>>> Hi Marc, Rafael, Lorenzo,
>>>>>
>>>>> Since we agreed to add a probe deferral if we failed to get irq
>>>>> resources which mirroring the DT does (patch 1 in this patch set),
>>>>> I think the last blocker to make things work both for Agustin and
>>>>> me [1] is this patch, which makes the interrupt producer and consumer
>>>>> work in ACPI, we have two different solution for one thing, we'd happy
>>>>> to work together for one solution, could you give some suggestions
>>>>> please?
>>>>>
>>>>> [1]:
>>>>> https://mail-archive.com/linux-kernel at vger.kernel.org/msg1257419.html
>>>>>
>>>>> Agustin, I have some comments below.
>>>>>
>>>>> On 2016/10/29 4:48, Agustin Vega-Frias wrote:
>>>>>> This allows irqchip drivers to associate an ACPI DSDT device to
>>>>>> an IRQ domain and provides support for using the ResourceSource
>>>>>> in Extended IRQ Resources to find the domain and map the IRQs
>>>>>> specified on that domain.
>>>>>>
>>>>>> Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
>>>>>> ---
>>>>>> drivers/acpi/Makefile | 1 +
>>>>>> drivers/acpi/irqdomain.c | 119
>>>>>> +++++++++++++++++++++++++++++++++++++++++++++++
>>>>>
>>>>> Could we just reuse the gsi.c and not introduce a new
>>>>> file, probably we can change the gsi.c to irqdomain.c
>>>>> or something similar, then reuse the code in gsi.c.
>>>>
>>>> I was thinking just that after we chatted off-list.
>>>
>>> Yes, that's a fair point.
>>>
>>>> I might revisit and see what I come up with given that we already have
>>>> a device argument and we could pass the IRQ source there.
>>>
>>> I agree with the approach taken by this patch, I do not like much
>>> passing around struct acpi_resource_source *source (in particular
>>> the dummy struct) I do not think it is needed, I will comment on
>>> the code.
>>
>> thanks for your time to have a look:)
>>
>>>
>>> Hopefully there is not any buggy FW out there that does use the
>>> resource source inappropriately otherwise we will notice on x86/ia64
>>> (ie you can't blame FW if it breaks the kernel) but I suspect the
>>> only way to find out is by trying, the patch has to go through Rafael's
>>> review anyway before getting there so it is fine.
>>
>> I think we can avoid that by not touching the logic that x86/ia64
>> already used, but only adding interrupt producer/consumer function.
>
> I looked at this more today and implemented a new patch that I plan to
> test over the weekend, but I wanted to let you know the approach I am
> pursuing.
>
> On the new patch use of ResourceSource when parsing ACPI Extended IRQ
> Resources is conditional on CONFIG_ACPI_GENERIC_GSI. The reason for this
> is two fold:
>
> 1. Since we wanted to reduce duplication and place the new APIs on the
> same source file as acpi_register_gsi, which is already under that
> config flag.
> 2. So the patch does not have effect on platforms not using the generic
> GSI support, including x86/ia64.
>
> If support for this is needed outside platforms using the generic GSI
> implementation, we can move these APIs out to their own source file
> and eliminate the CONFIG_ACPI_GENERIC_GSI conditionality.
I think is fine because ACPI_GENERIC_GSI is not for x86 at now, please
send out the patch then we can discuss.
Thanks
Hanjun
>
> I'll send the new patch, hopefully some time tomorrow, but please let
> me know if you have concerns with this approach.
>
> Thanks,
> Agustin
>
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