* [PATCH 2/6] pinctrl: rockchip: add support for rk1108
From: Heiko Stübner @ 2016-11-12 21:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFLEztRW8P4kiPZzVX2jM5UZMZun=TBBCij4B7j2TiesCuJYWA@mail.gmail.com>
Hi Jacob,
Am Sonntag, 13. November 2016, 01:41:21 schrieb ??:
> 2016-11-03 20:34 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
> > Add basic support for rk1108 soc
> >
> > Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> > ---
> >
> > drivers/pinctrl/pinctrl-rockchip.c | 27 ++++++++++++++++++++++++++-
> > 1 file changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pinctrl/pinctrl-rockchip.c
> > b/drivers/pinctrl/pinctrl-rockchip.c index 49bf7dc..9f324b1 100644
> > --- a/drivers/pinctrl/pinctrl-rockchip.c
> > +++ b/drivers/pinctrl/pinctrl-rockchip.c
> > @@ -59,6 +59,7 @@
> >
> > #define GPIO_LS_SYNC 0x60
> >
> > enum rockchip_pinctrl_type {
> >
> > + RK1108,
> >
> > RK2928,
> > RK3066B,
> > RK3188,
> >
> > @@ -1123,6 +1124,7 @@ static int rockchip_get_pull(struct
> > rockchip_pin_bank *bank, int pin_num)>
> > return !(data & BIT(bit))
> >
> > ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
> >
> > : PIN_CONFIG_BIAS_DISABLE;
> >
> > + case RK1108:
> > case RK3188:
> > case RK3288:
> >
> > case RK3368:
> > @@ -1169,6 +1171,7 @@ static int rockchip_set_pull(struct
> > rockchip_pin_bank *bank,>
> > spin_unlock_irqrestore(&bank->slock, flags);
> > break;
> >
> > + case RK1108:
> > case RK3188:
> > case RK3288:
> >
> > case RK3368:
> > @@ -1358,6 +1361,7 @@ static bool rockchip_pinconf_pull_valid(struct
> > rockchip_pin_ctrl *ctrl,>
> > pull == PIN_CONFIG_BIAS_DISABLE);
> >
> > case RK3066B:
> > return pull ? false : true;
> >
> > + case RK1108:
> > case RK3188:
> > case RK3288:
> >
> > case RK3368:
> > @@ -1385,7 +1389,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev
> > *pctldev, unsigned int pin,>
> > for (i = 0; i < num_configs; i++) {
> >
> > param = pinconf_to_config_param(configs[i]);
> > arg = pinconf_to_config_argument(configs[i]);
> >
> > -
> >
> > switch (param) {
> >
> > case PIN_CONFIG_BIAS_DISABLE:
> > rc = rockchip_set_pull(bank, pin -
> > bank->pin_base,
> >
> > @@ -2455,6 +2458,26 @@ static int rockchip_pinctrl_probe(struct
> > platform_device *pdev)>
> > return 0;
> >
> > }
> >
> > +static struct rockchip_pin_bank rk1108_pin_banks[] = {
> > + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> > + IOMUX_SOURCE_PMU,
> > + IOMUX_SOURCE_PMU,
> > + IOMUX_SOURCE_PMU),
> > + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
> > + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
> > + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
> > +};
> > +
> > +static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
> > + .pin_banks = rk1108_pin_banks,
> > + .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
> > + .label = "RK1108-GPIO",
> > + .type = RK1108,
> > + .grf_mux_offset = 0x10,
> > + .pmu_mux_offset = 0x0,
> > + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
> > +};
> > +
> >
> > static struct rockchip_pin_bank rk2928_pin_banks[] = {
> >
> > PIN_BANK(0, 32, "gpio0"),
> > PIN_BANK(1, 32, "gpio1"),
> >
> > @@ -2684,6 +2707,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
> >
> > };
> >
> > static const struct of_device_id rockchip_pinctrl_dt_match[] = {
> >
> > + { .compatible = "rockchip,rk1108-pinctrl",
> > + .data = (void *)&rk1108_pin_ctrl },
> >
> > { .compatible = "rockchip,rk2928-pinctrl",
> >
> > .data = (void *)&rk2928_pin_ctrl },
> >
> > { .compatible = "rockchip,rk3036-pinctrl",
> >
> > --
> > 2.7.4
>
> rk3288_calc_pull_reg_and_bit can't be used directly in rk1108.
> rk1108 have a different PULL_PMU_OFFSET and PULL_OFFSET.
yes, you're right, the offsets are different, so need a new function.
Andy, when at it, you might also want to include drive-strength functionality?
It is missing here but from looking at the TRM, it should be pretty easy to
add, as everything looks similar to what other rockchip socs do.
Heiko
^ permalink raw reply
* [PATCH v3] crypto: arm64/sha2: integrate OpenSSL implementations of SHA256/SHA512
From: Will Deacon @ 2016-11-12 22:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478953953-11523-1-git-send-email-ard.biesheuvel@linaro.org>
Hi Ard,
On Sat, Nov 12, 2016 at 01:32:33PM +0100, Ard Biesheuvel wrote:
> This integrates both the accelerated scalar and the NEON implementations
> of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.
>
> Relative performance compared to the respective generic C versions:
>
> | SHA256-scalar | SHA256-NEON* | SHA512 |
> ------------+-----------------+--------------+----------+
> Cortex-A53 | 1.63x | 1.63x | 2.34x |
> Cortex-A57 | 1.43x | 1.59x | 1.95x |
> Cortex-A73 | 1.26x | 1.56x | ? |
>
> The core crypto code was authored by Andy Polyakov of the OpenSSL
> project, in collaboration with whom the upstream code was adapted so
> that this module can be built from the same version of sha512-armv8.pl.
>
> The version in this patch was taken from OpenSSL commit
>
> 866e505e0d66 sha/asm/sha512-armv8.pl: add NEON version of SHA256.
>
> * The core SHA algorithm is fundamentally sequential, but there is a
> secondary transformation involved, called the schedule update, which
> can be performed independently. The NEON version of SHA-224/SHA-256
> only implements this part of the algorithm using NEON instructions,
> the sequential part is always done using scalar instructions.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> v3: at Will's request, the generated assembly files are now included
> as .S_shipped files, for which generic build rules are defined
> already. Note that this has caused issues in the past with
> patchwork, so for Herbert's convenience, the patch can be pulled
> from http://git.kernel.org/cgit/linux/kernel/git/ardb/linux.git,
> branch arm64-sha256 (based on today's cryptodev)
Thanks.
Looking at the generated code, I see references to __ARMEB__ and __ILP32__.
The former is probably a bug, whilst the second is not required. There are
also some commented out instructions, which is weird.
Will
^ permalink raw reply
* [PATCH 10/10] ARM: gr8: Convert to CCU
From: kbuild test robot @ 2016-11-12 23:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <14a9d0306074ca0276831dc42104929a65f3b666.1478625788.git-series.maxime.ripard@free-electrons.com>
Hi Maxime,
[auto build test ERROR on ]
url: https://github.com/0day-ci/linux/commits/Maxime-Ripard/ARM-sun5i-Convert-sun5i-SoCs-to-sunxi-ng/20161109-014935
base:
config: arm-pxa168_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
>> ERROR: Input tree has errors, aborting (use -f to force output)
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
-------------- next part --------------
A non-text attachment was scrubbed...
Name: .config.gz
Type: application/gzip
Size: 11419 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161113/b504f40e/attachment-0001.gz>
^ permalink raw reply
* [PATCH 2/10] clk: sunxi-ng: nkm: Deal with fixed post dividers
From: Chen-Yu Tsai @ 2016-11-13 3:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f8333c3a1f3308fcebd87bfc3710ce605f9bb595.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
It'd be better if you mentioned what clock needs this.
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi-ng/ccu_nkm.c | 17 ++++++++++++++---
> drivers/clk/sunxi-ng/ccu_nkm.h | 2 ++
> 2 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> index 9b840a47a94d..fd3c6a9d987c 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> @@ -75,7 +75,7 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
> - unsigned long n, m, k;
> + unsigned long rate, n, m, k;
> u32 reg;
>
> reg = readl(nkm->common.base + nkm->common.reg);
> @@ -89,7 +89,11 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
> m = reg >> nkm->m.shift;
> m &= (1 << nkm->m.width) - 1;
>
> - return parent_rate * (n + 1) * (k + 1) / (m + 1);
> + rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + rate /= nkm->fixed_post_div;
> +
> + return rate;
> }
>
> static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> @@ -100,6 +104,9 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> struct ccu_nkm *nkm = data;
> struct _ccu_nkm _nkm;
>
> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + rate *= nkm->fixed_post_div;
> +
> _nkm.min_n = nkm->n.min;
> _nkm.max_n = 1 << nkm->n.width;
> _nkm.min_k = nkm->k.min;
> @@ -109,7 +116,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>
> ccu_nkm_find_best(parent_rate, rate, &_nkm);
>
> - return parent_rate * _nkm.n * _nkm.k / _nkm.m;
> + rate = parent_rate * _nkm.n * _nkm.k / _nkm.m;
> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + rate = rate / nkm->fixed_post_div;
> +
> + return rate;
> }
>
You also need to handle this in the set_rate callback. You might need
to read back
the parent index value to determine if the post divider applies, as
this clock supports
a mux. Or don't support mux + post-div, and leave a TODO note.
ChenYu
> static int ccu_nkm_determine_rate(struct clk_hw *hw,
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
> index 34580894f4d1..0f1dbca25719 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.h
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.h
> @@ -32,6 +32,8 @@ struct ccu_nkm {
> struct ccu_mult_internal n;
> struct ccu_mult_internal k;
> struct ccu_div_internal m;
> +
> + unsigned int fixed_post_div;
> struct ccu_mux_internal mux;
>
> struct ccu_common common;
> --
> git-series 0.8.11
^ permalink raw reply
* [PATCH 2/10] clk: sunxi-ng: nkm: Deal with fixed post dividers
From: Chen-Yu Tsai @ 2016-11-13 3:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v64YW+7Grr4NvjuhsDNM2bF_fuhTkdW6Hs1=MXK2LFne0g@mail.gmail.com>
On Sun, Nov 13, 2016 at 11:48 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>
> It'd be better if you mentioned what clock needs this.
>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>> drivers/clk/sunxi-ng/ccu_nkm.c | 17 ++++++++++++++---
>> drivers/clk/sunxi-ng/ccu_nkm.h | 2 ++
>> 2 files changed, 16 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
>> index 9b840a47a94d..fd3c6a9d987c 100644
>> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
>> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
>> @@ -75,7 +75,7 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
>> unsigned long parent_rate)
>> {
>> struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
>> - unsigned long n, m, k;
>> + unsigned long rate, n, m, k;
>> u32 reg;
>>
>> reg = readl(nkm->common.base + nkm->common.reg);
>> @@ -89,7 +89,11 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
>> m = reg >> nkm->m.shift;
>> m &= (1 << nkm->m.width) - 1;
>>
>> - return parent_rate * (n + 1) * (k + 1) / (m + 1);
>> + rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
>> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
>> + rate /= nkm->fixed_post_div;
>> +
>> + return rate;
>> }
>>
>> static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>> @@ -100,6 +104,9 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>> struct ccu_nkm *nkm = data;
>> struct _ccu_nkm _nkm;
>>
>> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
>> + rate *= nkm->fixed_post_div;
>> +
>> _nkm.min_n = nkm->n.min;
>> _nkm.max_n = 1 << nkm->n.width;
>> _nkm.min_k = nkm->k.min;
>> @@ -109,7 +116,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>>
>> ccu_nkm_find_best(parent_rate, rate, &_nkm);
>>
>> - return parent_rate * _nkm.n * _nkm.k / _nkm.m;
>> + rate = parent_rate * _nkm.n * _nkm.k / _nkm.m;
>> + if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
>> + rate = rate / nkm->fixed_post_div;
>> +
>> + return rate;
>> }
>>
>
> You also need to handle this in the set_rate callback. You might need
> to read back
> the parent index value to determine if the post divider applies, as
> this clock supports
> a mux. Or don't support mux + post-div, and leave a TODO note.
Was thinking pre-dividers... sorry. Please ignore the second parent
index part.
ChenYu
>
> ChenYu
>
>> static int ccu_nkm_determine_rate(struct clk_hw *hw,
>> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
>> index 34580894f4d1..0f1dbca25719 100644
>> --- a/drivers/clk/sunxi-ng/ccu_nkm.h
>> +++ b/drivers/clk/sunxi-ng/ccu_nkm.h
>> @@ -32,6 +32,8 @@ struct ccu_nkm {
>> struct ccu_mult_internal n;
>> struct ccu_mult_internal k;
>> struct ccu_div_internal m;
>> +
>> + unsigned int fixed_post_div;
>> struct ccu_mux_internal mux;
>>
>> struct ccu_common common;
>> --
>> git-series 0.8.11
^ permalink raw reply
* [PATCH 3/10] clk: sunxi-ng: Implement multiplier offsets
From: Chen-Yu Tsai @ 2016-11-13 4:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <434b49180c2b5f8668f9fd92f5cba6d8b64a7de8.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The multipliers we've seen so far all had an offset of one. However, on the
Explaining that the offset refers to the difference between the register value
and the actual multiplier/divider applied to the clock rate would be nice.
> earlier Allwinner SoCs, the multipliers could have no offset at all.
>
> Implement an additional field for the multipliers to specify that offset.
You are also doing this for dividers. Please mention that.
And you should mention that you're only doing this for "linear" factors,
not power-of-two ones.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi-ng/ccu_div.h | 10 +++++++++-
> drivers/clk/sunxi-ng/ccu_mp.c | 10 +++++++---
> drivers/clk/sunxi-ng/ccu_mult.c | 4 ++--
> drivers/clk/sunxi-ng/ccu_mult.h | 20 ++++++++++++++------
> drivers/clk/sunxi-ng/ccu_nk.c | 14 ++++++++++----
> drivers/clk/sunxi-ng/ccu_nkm.c | 18 +++++++++++++-----
> drivers/clk/sunxi-ng/ccu_nkmp.c | 17 +++++++++++++----
> drivers/clk/sunxi-ng/ccu_nm.c | 13 ++++++++++---
> 8 files changed, 78 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
> index 06540f7cf41c..08d074451204 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.h
> +++ b/drivers/clk/sunxi-ng/ccu_div.h
> @@ -41,6 +41,7 @@ struct ccu_div_internal {
> u8 width;
>
> u32 max;
> + u32 offset;
>
> u32 flags;
>
> @@ -58,20 +59,27 @@ struct ccu_div_internal {
> #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \
> _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
>
> -#define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \
> +#define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \
> { \
> .shift = _shift, \
> .width = _width, \
> .flags = _flags, \
> .max = _max, \
> + .offset = _off, \
> }
>
> +#define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \
> + _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
> +
> #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \
> _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
>
> #define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \
> _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, 0)
>
> +#define _SUNXI_CCU_DIV_OFFSET(_shift, _width, _offset) \
> + _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _offset, 0, 0)
> +
With this macro, you can have a divider offset of anything but 1, but
no specified maximum. You should handle this in the callbacks somehow.
Same goes for the multiplier. Otherwise with max = (1 << width), you'll
overflow the register field when offset = 0.
Also, if specified, does the maximum apply before or after the offset
is applied? Some clarification is required.
> #define _SUNXI_CCU_DIV(_shift, _width) \
> _SUNXI_CCU_DIV_FLAGS(_shift, _width, 0)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
> index ebb1b31568a5..22c2ca7a2a22 100644
> --- a/drivers/clk/sunxi-ng/ccu_mp.c
> +++ b/drivers/clk/sunxi-ng/ccu_mp.c
> @@ -89,11 +89,14 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
>
> m = reg >> cmp->m.shift;
> m &= (1 << cmp->m.width) - 1;
> + m += cmp->m.offset;
> + if (!m)
> + m++;
>
> p = reg >> cmp->p.shift;
> p &= (1 << cmp->p.width) - 1;
>
> - return (parent_rate >> p) / (m + 1);
> + return (parent_rate >> p) / m;
> }
>
> static int ccu_mp_determine_rate(struct clk_hw *hw,
> @@ -124,9 +127,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
> reg = readl(cmp->common.base + cmp->common.reg);
> reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
> reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
> + reg |= (m - cmp->m.offset) << cmp->m.shift;
> + reg |= ilog2(p) << cmp->p.shift;
>
> - writel(reg | (ilog2(p) << cmp->p.shift) | ((m - 1) << cmp->m.shift),
> - cmp->common.base + cmp->common.reg);
> + writel(reg, cmp->common.base + cmp->common.reg);
>
> spin_unlock_irqrestore(cmp->common.lock, flags);
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
> index 826302464650..bf5e11c803f9 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.c
> +++ b/drivers/clk/sunxi-ng/ccu_mult.c
> @@ -85,7 +85,7 @@ static unsigned long ccu_mult_recalc_rate(struct clk_hw *hw,
> ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
> &parent_rate);
>
> - return parent_rate * (val + 1);
> + return parent_rate * (val + cm->mult.offset);
> }
>
> static int ccu_mult_determine_rate(struct clk_hw *hw,
> @@ -122,7 +122,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
> reg = readl(cm->common.base + cm->common.reg);
> reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift);
>
> - writel(reg | ((_cm.mult - 1) << cm->mult.shift),
> + writel(reg | ((_cm.mult - cm->mult.offset) << cm->mult.shift),
> cm->common.base + cm->common.reg);
>
> spin_unlock_irqrestore(cm->common.lock, flags);
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
> index bd2e38b5a32a..84839641dfdf 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.h
> +++ b/drivers/clk/sunxi-ng/ccu_mult.h
> @@ -6,20 +6,28 @@
> #include "ccu_mux.h"
>
> struct ccu_mult_internal {
> + u8 offset;
> u8 shift;
> u8 width;
> u8 min;
> };
>
> -#define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \
> - { \
> - .shift = _shift, \
> - .width = _width, \
> - .min = _min, \
> +#define _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, _offset, _min) \
> + { \
> + .min = _min, \
> + .offset = _offset, \
> + .shift = _shift, \
> + .width = _width, \
> }
>
> +#define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \
> + _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, 1, _min)
> +
> +#define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \
> + _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, _offset, 1)
> +
> #define _SUNXI_CCU_MULT(_shift, _width) \
> - _SUNXI_CCU_MULT_MIN(_shift, _width, 1)
> + _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, 1, 1)
>
> struct ccu_mult {
> u32 enable;
> diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
> index eaf0fdf78d2b..90117d3ead8c 100644
> --- a/drivers/clk/sunxi-ng/ccu_nk.c
> +++ b/drivers/clk/sunxi-ng/ccu_nk.c
> @@ -76,12 +76,17 @@ static unsigned long ccu_nk_recalc_rate(struct clk_hw *hw,
>
> n = reg >> nk->n.shift;
> n &= (1 << nk->n.width) - 1;
> + n += nk->n.offset;
> + if (!n)
> + n++;
>
> k = reg >> nk->k.shift;
> k &= (1 << nk->k.width) - 1;
> + k += nk->k.offset;
> + if (!k)
> + k++;
>
> - rate = parent_rate * (n + 1) * (k + 1);
> -
> + rate = parent_rate * n * k;
> if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> rate /= nk->fixed_post_div;
>
> @@ -135,8 +140,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
> reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift);
> reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift);
>
> - writel(reg | ((_nk.k - 1) << nk->k.shift) | ((_nk.n - 1) << nk->n.shift),
> - nk->common.base + nk->common.reg);
> + reg |= (_nk.k - nk->k.offset) << nk->k.shift;
> + reg |= (_nk.n - nk->n.offset) << nk->n.shift;
> + writel(reg, nk->common.base + nk->common.reg);
>
> spin_unlock_irqrestore(nk->common.lock, flags);
>
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> index fd3c6a9d987c..e0b4c914d7ac 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> @@ -82,14 +82,23 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
>
> n = reg >> nkm->n.shift;
> n &= (1 << nkm->n.width) - 1;
> + n += nkm->n.offset;
> + if (!n)
> + n++;
>
> k = reg >> nkm->k.shift;
> k &= (1 << nkm->k.width) - 1;
> + k += nkm->k.offset;
> + if (!k)
> + k++;
>
> m = reg >> nkm->m.shift;
> m &= (1 << nkm->m.width) - 1;
> + m += nkm->m.offset;
> + if (!m)
> + m++;
>
> - rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
> + rate = parent_rate * n * k / m;
> if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> rate /= nkm->fixed_post_div;
>
> @@ -156,10 +165,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
> reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift);
> reg &= ~GENMASK(nkm->m.width + nkm->m.shift - 1, nkm->m.shift);
>
> - reg |= (_nkm.n - 1) << nkm->n.shift;
> - reg |= (_nkm.k - 1) << nkm->k.shift;
> - reg |= (_nkm.m - 1) << nkm->m.shift;
> -
> + reg |= (_nkm.n - nkm->n.offset) << nkm->n.shift;
> + reg |= (_nkm.k - nkm->k.offset) << nkm->k.shift;
> + reg |= (_nkm.m - nkm->m.offset) << nkm->m.shift;
> writel(reg, nkm->common.base + nkm->common.reg);
>
> spin_unlock_irqrestore(nkm->common.lock, flags);
> diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> index 684c42da3ebb..da2bba02b845 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> @@ -88,17 +88,26 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
>
> n = reg >> nkmp->n.shift;
> n &= (1 << nkmp->n.width) - 1;
> + n += nkmp->n.offset;
> + if (!n)
> + n++;
>
> k = reg >> nkmp->k.shift;
> k &= (1 << nkmp->k.width) - 1;
> + k += nkmp->k.offset;
> + if (!k)
> + k++;
>
> m = reg >> nkmp->m.shift;
> m &= (1 << nkmp->m.width) - 1;
> + m += nkmp->m.offset;
> + if (!m)
> + m++;
>
> p = reg >> nkmp->p.shift;
> p &= (1 << nkmp->p.width) - 1;
>
> - return (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
> + return parent_rate * n * k >> p / m;
> }
>
> static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
> @@ -148,9 +157,9 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
> reg &= ~GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift);
> reg &= ~GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift);
>
> - reg |= (_nkmp.n - 1) << nkmp->n.shift;
> - reg |= (_nkmp.k - 1) << nkmp->k.shift;
> - reg |= (_nkmp.m - 1) << nkmp->m.shift;
> + reg |= (_nkmp.n - nkmp->n.offset) << nkmp->n.shift;
> + reg |= (_nkmp.k - nkmp->k.offset) << nkmp->k.shift;
> + reg |= (_nkmp.m - nkmp->m.offset) << nkmp->m.shift;
> reg |= ilog2(_nkmp.p) << nkmp->p.shift;
>
> writel(reg, nkmp->common.base + nkmp->common.reg);
> diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
> index c9f3b6c982f0..158d74e0215f 100644
> --- a/drivers/clk/sunxi-ng/ccu_nm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nm.c
> @@ -80,11 +80,17 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
>
> n = reg >> nm->n.shift;
> n &= (1 << nm->n.width) - 1;
> + n += nm->n.offset;
> + if (!n)
> + n++;
>
> m = reg >> nm->m.shift;
> m &= (1 << nm->m.width) - 1;
> + m += nm->m.offset;
> + if (!m)
> + m++;
>
> - return parent_rate * (n + 1) / (m + 1);
> + return parent_rate * n / m;
> }
>
> static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
> @@ -129,8 +135,9 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
> reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift);
> reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
>
> - writel(reg | ((_nm.m - 1) << nm->m.shift) | ((_nm.n - 1) << nm->n.shift),
> - nm->common.base + nm->common.reg);
> + reg |= (_nm.n - nm->n.offset) << nm->n.shift;
> + reg |= (_nm.m - nm->m.offset) << nm->m.shift;
> + writel(reg, nm->common.base + nm->common.reg);
>
> spin_unlock_irqrestore(nm->common.lock, flags);
>
> --
> git-series 0.8.11
The existing bits in this patch look good.
Regards
ChenYu
^ permalink raw reply
* [PATCH 4/10] clk: sunxi-ng: Add clocks and resets indices for sun5i
From: Chen-Yu Tsai @ 2016-11-13 4:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8fbb8e05d73282fb5e7d33f8faffbeaccf63aeae.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The SoCs part of the sun5i family share the DTs, so we need consistant
> indices in order to still share the DTs.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> include/dt-bindings/clock/sun5i-ccu.h | 126 +++++++++++++++++++++++++++-
> include/dt-bindings/reset/sun5i-ccu.h | 32 +++++++-
> 2 files changed, 158 insertions(+), 0 deletions(-)
> create mode 100644 include/dt-bindings/clock/sun5i-ccu.h
> create mode 100644 include/dt-bindings/reset/sun5i-ccu.h
>
> diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h
> new file mode 100644
> index 000000000000..32735b2cf29c
> --- /dev/null
> +++ b/include/dt-bindings/clock/sun5i-ccu.h
> @@ -0,0 +1,126 @@
> +/*
> + * Copyright 2016 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _CCU_SUN5I_H_
> +#define _CCU_SUN5I_H_
> +
> +#define CLK_HOSC 1
> +#define CLK_OSC3M 2
We don't need this one. The clock diagram shows the video PLLs' input
as OSC24M. This means there's a fixed /8 pre-divider at the input.
> +#define CLK_PLL_CORE 3
> +#define CLK_PLL_AUDIO_BASE 4
> +#define CLK_PLL_AUDIO 5
> +#define CLK_PLL_AUDIO_2X 6
> +#define CLK_PLL_AUDIO_4X 7
> +#define CLK_PLL_AUDIO_8X 8
> +#define CLK_PLL_VIDEO0 9
> +#define CLK_PLL_VIDEO0_2X 10
> +#define CLK_PLL_VE 11
> +#define CLK_PLL_DDR_BASE 12
> +#define CLK_PLL_DDR 13
> +#define CLK_PLL_DDR_OTHER 14
> +#define CLK_PLL_PERIPH 15
> +#define CLK_PLL_VIDEO1 16
> +#define CLK_PLL_VIDEO1_2X 17
> +#define CLK_OSC24M 18
> +#define CLK_CPU 19
> +#define CLK_AXI 20
> +#define CLK_AHB 21
> +#define CLK_APB0 22
> +#define CLK_APB1 23
> +#define CLK_DRAM_AXI 24
> +#define CLK_AHB_OTG 25
> +#define CLK_AHB_EHCI 26
> +#define CLK_AHB_OHCI 27
> +#define CLK_AHB_SS 28
> +#define CLK_AHB_DMA 29
> +#define CLK_AHB_BIST 30
> +#define CLK_AHB_MMC0 31
> +#define CLK_AHB_MMC1 32
> +#define CLK_AHB_MMC2 33
> +#define CLK_AHB_NAND 34
> +#define CLK_AHB_SDRAM 35
> +#define CLK_AHB_EMAC 36
> +#define CLK_AHB_TS 37
> +#define CLK_AHB_SPI0 38
> +#define CLK_AHB_SPI1 39
> +#define CLK_AHB_SPI2 40
> +#define CLK_AHB_GPS 41
> +#define CLK_AHB_HSTIMER 42
> +#define CLK_AHB_VE 43
> +#define CLK_AHB_TVE 44
> +#define CLK_AHB_LCD 45
> +#define CLK_AHB_CSI 46
> +#define CLK_AHB_HDMI 47
> +#define CLK_AHB_DE_BE 48
> +#define CLK_AHB_DE_FE 49
> +#define CLK_AHB_IEP 50
> +#define CLK_AHB_GPU 51
> +#define CLK_APB0_CODEC 52
> +#define CLK_APB0_SPDIF 53
> +#define CLK_APB0_I2S 54
> +#define CLK_APB0_PIO 55
> +#define CLK_APB0_IR 56
> +#define CLK_APB0_KEYPAD 57
> +#define CLK_APB1_I2C0 58
> +#define CLK_APB1_I2C1 59
> +#define CLK_APB1_I2C2 60
> +#define CLK_APB1_UART0 61
> +#define CLK_APB1_UART1 62
> +#define CLK_APB1_UART2 63
> +#define CLK_APB1_UART3 64
> +#define CLK_NAND 65
> +#define CLK_MMC0 66
> +#define CLK_MMC1 67
> +#define CLK_MMC2 68
> +#define CLK_TS 69
> +#define CLK_SS 70
> +#define CLK_CE 71
You use 'SS' for the AHB gate. Since the manual uses 'SS',
can we stick to that.
> +#define CLK_SPI0 72
> +#define CLK_SPI1 73
> +#define CLK_SPI2 74
> +#define CLK_IR 75
> +#define CLK_I2S 76
> +#define CLK_SPDIF 77
> +#define CLK_KEYPAD 78
> +#define CLK_USB_OHCI 79
> +#define CLK_USB_PHY0 80
> +#define CLK_USB_PHY1 81
> +#define CLK_GPS 82
> +#define CLK_DRAM_VE 83
> +#define CLK_DRAM_CSI 84
> +#define CLK_DRAM_TS 85
> +#define CLK_DRAM_TVE 86
> +#define CLK_DRAM_DE_FE 87
> +#define CLK_DRAM_DE_BE 88
> +#define CLK_DRAM_ACE 89
> +#define CLK_DRAM_IEP 90
> +#define CLK_DE_BE 91
> +#define CLK_DE_FE 92
> +#define CLK_TCON_CH0 93
> +#define CLK_TCON_CH1_SCLK 94
> +#define CLK_TCON_CH1 95
> +#define CLK_CSI 96
> +#define CLK_VE 97
> +#define CLK_CODEC 98
> +#define CLK_AVS 99
> +#define CLK_HDMI 100
> +#define CLK_GPU 101
> +#define CLK_MBUS 102
> +#define CLK_IEP 103
> +
> +#define CLK_NUMBER (CLK_IEP + 1)
> +
> +#endif /* _CCU_SUN5I_H_ */
> diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h
> new file mode 100644
> index 000000000000..c2b9726b5026
> --- /dev/null
> +++ b/include/dt-bindings/reset/sun5i-ccu.h
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright 2016 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _RST_SUN5I_H_
> +#define _RST_SUN5I_H_
> +
> +#define RST_USB_PHY0 0
> +#define RST_USB_PHY1 1
> +#define RST_GPS 2
> +#define RST_DE_BE 3
> +#define RST_DE_FE 4
> +#define RST_TVE 5
> +#define RST_LCD 6
> +#define RST_CSI 7
> +#define RST_VE 8
> +#define RST_GPU 9
> +#define RST_IEP 10
> +
> +#endif /* _RST_SUN5I_H_ */
> --
> git-series 0.8.11
The rest looks good.
ChenYu
^ permalink raw reply
* [PATCH 5/10] clk: sunxi-ng: Implement multiplier maximum
From: Chen-Yu Tsai @ 2016-11-13 4:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1d12cf2cb0a7364f17691705f3bd018eddc51202.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi-ng/ccu_mult.h | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
> index 84839641dfdf..524acddfcb2e 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.h
> +++ b/drivers/clk/sunxi-ng/ccu_mult.h
> @@ -10,24 +10,26 @@ struct ccu_mult_internal {
> u8 shift;
> u8 width;
> u8 min;
> + u8 max;
> };
>
> -#define _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, _offset, _min) \
> +#define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \
> { \
> .min = _min, \
> + .max = _max, \
> .offset = _offset, \
> .shift = _shift, \
> .width = _width, \
> }
>
> #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \
> - _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, 1, _min)
> + _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
>
> #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \
> - _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, _offset, 1)
> + _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
>
> #define _SUNXI_CCU_MULT(_shift, _width) \
> - _SUNXI_CCU_MULT_OFFSET_MIN(_shift, _width, 1, 1)
> + _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
>
> struct ccu_mult {
> u32 enable;
> --
> git-series 0.8.11
You're missing the code that actually uses the maximum value.
ChenYu
^ permalink raw reply
* [GIT PULL] Qualcomm ARM64 Defconfig Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-arm64-defconfig-for-4.10
for you to fetch changes up to a77a713395392a7f79d89e634fe3e018c4f83898:
arm64: configs: enable configs for msm899(2/4) basic support (2016-11-12 22:44:09 -0600)
----------------------------------------------------------------
Qualcomm ARM64 Based defconfig Updates for v4.10
* Enable defconfig options for MSM8992/8994
----------------------------------------------------------------
Jeremy McNicoll (1):
arm64: configs: enable configs for msm899(2/4) basic support
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
^ permalink raw reply
* [GIT PULL] Qualcomm ARM64 DT Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-arm64-for-4.10
for you to fetch changes up to feeaf56ac78d283efe65ea60ec999d4bf3cf395e:
arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support (2016-11-12 22:57:56 -0600)
----------------------------------------------------------------
Qualcomm ARM64 Updates for v4.10
* Add Hexagon SMD/PIL nodes
* Add DB820c PMIC pins
* Fixup APQ8016 voltage ranges
* Add various MSM8996 nodes to support SMD/SMEM/SMP2P
* Add support for Huawei Nexus 6P (Angler)
* Add support for LG Nexus 5x (Bullhead)
----------------------------------------------------------------
Archit Taneja (1):
arm64: dts: apq8016-sbc: Set up LDO2, LDO6 and LDO17 regulator voltage ranges
Bastian K?cher (1):
arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
Bjorn Andersson (3):
arm64: dts: qcom: msm8916: Add Hexagon SMD edge
arm64: dts: qcom: msm8916: Add Hexagon PIL node
arm64: dts: msm8996: Add SMEM DT nodes
Jeremy McNicoll (2):
arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
dt-bindings: qcom: Add msm899(2/4) bindings
Rajendra Nayak (1):
arm64: dts: qcom: Add missing interrupt entry for pm8994 gpios
Srinivas Kandagatla (2):
dts: arm64: db820c: add pmic pins specific dts file
arm64: dts: apq8016-sbc: add analog audio support with multicodec
spjoshi at codeaurora.org (3):
arm64: dts: msm8996: Add SMEM reserve-memory node
arm64: dts: msm8996: Add reserve-memory nodes
arm64: dts: msm8996: Add SMP2P and APCS nodes
Documentation/devicetree/bindings/arm/qcom.txt | 2 +
arch/arm64/boot/dts/qcom/Makefile | 7 +-
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 73 ++++++-
.../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi | 15 ++
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 2 +
arch/arm64/boot/dts/qcom/msm8916.dtsi | 62 +++++-
.../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 41 ++++
arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 ++++
arch/arm64/boot/dts/qcom/msm8992.dtsi | 184 ++++++++++++++++++
.../arm64/boot/dts/qcom/msm8994-angler-rev-101.dts | 40 ++++
arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++++
arch/arm64/boot/dts/qcom/msm8994.dtsi | 216 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/msm8996.dtsi | 82 ++++++++
arch/arm64/boot/dts/qcom/pm8916.dtsi | 45 ++++-
arch/arm64/boot/dts/qcom/pm8994.dtsi | 1 +
15 files changed, 836 insertions(+), 10 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
^ permalink raw reply
* [GIT PULL] Qualcomm Defconfig Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-defconfig-for-4.10
for you to fetch changes up to 206787737e308bb447d18adef7da7749188212f5:
ARM: qcom_defconfig: Fix MDM9515 LCC and GCC config (2016-10-24 16:04:32 -0500)
----------------------------------------------------------------
Qualcomm ARM Based defconfig Updates for v4.10
* Fixup MDM9615 option names
----------------------------------------------------------------
Neil Armstrong (1):
ARM: qcom_defconfig: Fix MDM9515 LCC and GCC config
arch/arm/configs/qcom_defconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
^ permalink raw reply
* [GIT PULL] Qualcomm Driver Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-drivers-for-4.10
for you to fetch changes up to bd4760ca03156731674a570e44490986189d8228:
firmware: qcom: scm: Use devm_reset_controller_register() (2016-11-12 23:24:51 -0600)
----------------------------------------------------------------
Qualcomm ARM Based Driver Updates for v4.10
* Fixup QCOM SCM to use devm_reset_controller_register
* Add QCOM pinctrl to Qualcomm MAINTAINERS entry
* Add PM8994 regulator definitions
* Add stub for WCNSS_CTRL API
----------------------------------------------------------------
Bjorn Andersson (1):
soc: qcom: wcnss_ctrl: Stub wcnss_ctrl API
Michael Scott (1):
MAINTAINERS: add drivers/pinctrl/qcom to ARM/QUALCOMM SUPPORT
Srinivas Kandagatla (1):
pinctrl: pm8994: add pad voltage regulator defines
Wei Yongjun (1):
firmware: qcom: scm: Use devm_reset_controller_register()
MAINTAINERS | 1 +
drivers/firmware/qcom_scm.c | 4 +++-
include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 4 ++++
include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 6 ++++++
include/linux/soc/qcom/wcnss_ctrl.h | 13 +++++++++++++
5 files changed, 27 insertions(+), 1 deletion(-)
^ permalink raw reply
* [GIT PULL] Qualcomm Device Tree Changes for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-dts-for-4.10
for you to fetch changes up to 52a1a5f773110f687c34a828ef42fdb882b6b908:
ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard (2016-10-25 08:42:37 -0500)
----------------------------------------------------------------
Qualcomm Device Tree Changes for v4.10
* Add EBI2 support to MSM8660
* Add SMSC ethernet support to APQ8060
* Add support for display, pstore, iommu, and hdmi to APQ8064
* Add SDHCI node to MSM8974 Hammerhead
* Add WP8548 MangOH board support (MDM9615)
----------------------------------------------------------------
Archit Taneja (2):
arm: dts: qcom: apq8064: Add display DT nodes
arm: dts: qcom: apq8064-ifc6410: Add HDMI support
Bhushan Shah (1):
ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node
John Stultz (3):
arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes
arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes
arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7
Linus Walleij (2):
ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI
ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
Neil Armstrong (5):
ARM: dts: Add MDM9615 dtsi
dt-bindings: qcom: Add MDM9615 bindings
ARM: dts: Add Sierra Wireless WP8548 dtsi
ARM: dts: Add WP8548 based MangOH Green board DTS
dt-bindings: arm: Add Sierra Wireless modules bindings
Documentation/devicetree/bindings/arm/qcom.txt | 1 +
Documentation/devicetree/bindings/arm/swir.txt | 12 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 119 +++++
arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 77 ++-
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 74 +++
arch/arm/boot/dts/qcom-apq8064.dtsi | 321 ++++++++++++
arch/arm/boot/dts/qcom-mdm9615.dtsi | 557 +++++++++++++++++++++
arch/arm/boot/dts/qcom-msm8660.dtsi | 17 +
.../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 29 ++
arch/arm/boot/dts/swir-wp8548-mangoh-green.dts | 281 +++++++++++
arch/arm/boot/dts/swir-wp8548.dtsi | 170 +++++++
12 files changed, 1658 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/swir.txt
create mode 100644 arch/arm/boot/dts/qcom-mdm9615.dtsi
create mode 100644 arch/arm/boot/dts/swir-wp8548-mangoh-green.dts
create mode 100644 arch/arm/boot/dts/swir-wp8548.dtsi
^ permalink raw reply
* [GIT PULL] Qualcomm SoC Updates for v4.10
From: Andy Gross @ 2016-11-13 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479017736-13564-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-soc-for-4.10
for you to fetch changes up to e19811a89d0f566bb781959e151f244bd3bcde8a:
arm64: qcom: enable GPIOLIB in Kconfig (2016-11-12 23:24:26 -0600)
----------------------------------------------------------------
Qualcomm ARM Based SoC Updates for v4.10
* Enable GPIOLIB for QCOM ARM64 platforms
----------------------------------------------------------------
Michael Scott (1):
arm64: qcom: enable GPIOLIB in Kconfig
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
^ permalink raw reply
* [PATCH 2/6] pinctrl: rockchip: add support for rk1108
From: Andy Yan @ 2016-11-13 7:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2910206.ioRrj8ivkn@diego>
Hi Heiko, Jacob:
On 2016?11?13? 05:44, Heiko St?bner wrote:
> Hi Jacob,
>
> Am Sonntag, 13. November 2016, 01:41:21 schrieb ??:
>> 2016-11-03 20:34 GMT+08:00 Andy Yan <andy.yan@rock-chips.com>:
>>> Add basic support for rk1108 soc
>>>
>>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>>> ---
>>>
>>> drivers/pinctrl/pinctrl-rockchip.c | 27 ++++++++++++++++++++++++++-
>>> 1 file changed, 26 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/pinctrl/pinctrl-rockchip.c
>>> b/drivers/pinctrl/pinctrl-rockchip.c index 49bf7dc..9f324b1 100644
>>> --- a/drivers/pinctrl/pinctrl-rockchip.c
>>> +++ b/drivers/pinctrl/pinctrl-rockchip.c
>>> @@ -59,6 +59,7 @@
>>>
>>> #define GPIO_LS_SYNC 0x60
>>>
>>> enum rockchip_pinctrl_type {
>>>
>>> + RK1108,
>>>
>>> RK2928,
>>> RK3066B,
>>> RK3188,
>>>
>>> @@ -1123,6 +1124,7 @@ static int rockchip_get_pull(struct
>>> rockchip_pin_bank *bank, int pin_num)>
>>> return !(data & BIT(bit))
>>>
>>> ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
>>>
>>> : PIN_CONFIG_BIAS_DISABLE;
>>>
>>> + case RK1108:
>>> case RK3188:
>>> case RK3288:
>>>
>>> case RK3368:
>>> @@ -1169,6 +1171,7 @@ static int rockchip_set_pull(struct
>>> rockchip_pin_bank *bank,>
>>> spin_unlock_irqrestore(&bank->slock, flags);
>>> break;
>>>
>>> + case RK1108:
>>> case RK3188:
>>> case RK3288:
>>>
>>> case RK3368:
>>> @@ -1358,6 +1361,7 @@ static bool rockchip_pinconf_pull_valid(struct
>>> rockchip_pin_ctrl *ctrl,>
>>> pull == PIN_CONFIG_BIAS_DISABLE);
>>>
>>> case RK3066B:
>>> return pull ? false : true;
>>>
>>> + case RK1108:
>>> case RK3188:
>>> case RK3288:
>>>
>>> case RK3368:
>>> @@ -1385,7 +1389,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev
>>> *pctldev, unsigned int pin,>
>>> for (i = 0; i < num_configs; i++) {
>>>
>>> param = pinconf_to_config_param(configs[i]);
>>> arg = pinconf_to_config_argument(configs[i]);
>>>
>>> -
>>>
>>> switch (param) {
>>>
>>> case PIN_CONFIG_BIAS_DISABLE:
>>> rc = rockchip_set_pull(bank, pin -
>>> bank->pin_base,
>>>
>>> @@ -2455,6 +2458,26 @@ static int rockchip_pinctrl_probe(struct
>>> platform_device *pdev)>
>>> return 0;
>>>
>>> }
>>>
>>> +static struct rockchip_pin_bank rk1108_pin_banks[] = {
>>> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
>>> + IOMUX_SOURCE_PMU,
>>> + IOMUX_SOURCE_PMU,
>>> + IOMUX_SOURCE_PMU),
>>> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
>>> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
>>> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
>>> +};
>>> +
>>> +static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
>>> + .pin_banks = rk1108_pin_banks,
>>> + .nr_banks = ARRAY_SIZE(rk1108_pin_banks),
>>> + .label = "RK1108-GPIO",
>>> + .type = RK1108,
>>> + .grf_mux_offset = 0x10,
>>> + .pmu_mux_offset = 0x0,
>>> + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
>>> +};
>>> +com
>>>
>>> static struct rockchip_pin_bank rk2928_pin_banks[] = {
>>>
>>> PIN_BANK(0, 32, "gpio0"),
>>> PIN_BANK(1, 32, "gpio1"),
>>>
>>> @@ -2684,6 +2707,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
>>>
>>> };
>>>
>>> static const struct of_device_id rockchip_pinctrl_dt_match[] = {
>>>
>>> + { .compatible = "rockchip,rk1108-pinctrl",
>>> + .data = (void *)&rk1108_pin_ctrl },
>>>
>>> { .compatible = "rockchip,rk2928-pinctrl",
>>>
>>> .data = (void *)&rk2928_pin_ctrl },
>>>
>>> { .compatible = "rockchip,rk3036-pinctrl",
>>>
>>> --
>>> 2.7.4
>> rk3288_calc_pull_reg_and_bit can't be used directly in rk1108.
>> rk1108 have a different PULL_PMU_OFFSET and PULL_OFFSET.
> yes, you're right, the offsets are different, so need a new function.
>
> Andy, when at it, you might also want to include drive-strength functionality?
> It is missing here but from looking at the TRM, it should be pretty easy to
> add, as everything looks similar to what other rockchip socs do.
I had already found it, it will be fixed in next version.
Thank you!
>
> Heiko
>
>
>
^ permalink raw reply
* [PATCH 1/2] ARM: dts: rockchip: add the sdmmc pinctrl for rk1108
From: Jacob Chen @ 2016-11-13 8:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
---
arch/arm/boot/dts/rk1108.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
index 9dccfea..6a06ad7 100644
--- a/arch/arm/boot/dts/rk1108.dtsi
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -321,6 +321,31 @@
input-enable;
};
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+
+ sdmmc_cd: sdmmc-cd {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
+ <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
+ <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
+ <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
+ };
+ };
+
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: rockchip: enable sdmmc for rk1108-evb
From: Jacob Chen @ 2016-11-13 8:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479024799-29198-1-git-send-email-jacob-chen@iotwrt.com>
From: Jacob Chen <jacob2.chen@rock-chips.com>
This patch add sdmmc support for rk1108-evb, now I can load the rootfs
from sdmmc.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
---
arch/arm/boot/dts/rk1108-evb.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts
index 3956cff..cea26e5 100644
--- a/arch/arm/boot/dts/rk1108-evb.dts
+++ b/arch/arm/boot/dts/rk1108-evb.dts
@@ -56,6 +56,18 @@
};
};
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
@@ -67,3 +79,12 @@
&uart2 {
status = "okay";
};
+
+&pinctrl {
+
+ sdmmc {
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: rockchip: add the sdmmc pinctrl for rk1108
From: 陈豪 @ 2016-11-13 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479024799-29198-1-git-send-email-jacob-chen@iotwrt.com>
2016-11-13 16:13 GMT+08:00 Jacob Chen <jacob-chen@iotwrt.com>:
> From: Jacob Chen <jacob2.chen@rock-chips.com>
>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
> arch/arm/boot/dts/rk1108.dtsi | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
> index 9dccfea..6a06ad7 100644
> --- a/arch/arm/boot/dts/rk1108.dtsi
> +++ b/arch/arm/boot/dts/rk1108.dtsi
> @@ -321,6 +321,31 @@
> input-enable;
> };
>
> + sdmmc {
> + sdmmc_clk: sdmmc-clk {
> + rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
> + };
> +
> + sdmmc_cmd: sdmmc-cmd {
> + rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
> + };
> +
> + sdmmc_cd: sdmmc-cd {
> + rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
> + };
> +
> + sdmmc_bus1: sdmmc-bus1 {
> + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
> + };
> +
> + sdmmc_bus4: sdmmc-bus4 {
> + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
> + <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
> + <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
> + <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
> + };
> + };
> +
> i2c1 {
> i2c1_xfer: i2c1-xfer {
> rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
> --
> 2.7.4
>
Those patches are based on andy's patch set "Add basic support for
support for Rockchip RK1108 SOC ", assuming he will include
drive-strength functionality in pinctrl.
^ permalink raw reply
* Three different LED brightnesses (was Re: PM regression with LED changes in next-20161109)
From: Pavel Machek @ 2016-11-13 9:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3ca04742-6376-5a88-8d10-5b88fcd8f5e5@redhat.com>
On Sat 2016-11-12 09:03:42, Hans de Goede wrote:
> Hi,
>
> On 11-11-16 23:12, Pavel Machek wrote:
> >Hi!
> >
> >Reason #1:
> >
> >>>>Hmm. So userland can read the LED state, and it can get _some_ value
> >>>>back, but it can not know if it is current state or not.
>
> That is not correct, the current behavior for eading the brightness
> atrribute is to always return the current state.
No. (Because some hardware can't get back current state of
hardware-controlled leds, and because of blinking).
> >>Why a dedicated file? Are we going to mirror brightness here
> >>wrt r/w (show/store) behavior ? If not userspace now needs
> >>2 open fds which is not really nice. If we are and we are
> >>not going to use poll for something else on brightness itself
> >>then why not just poll directly on brightness ?
> >
> >Reason #1 is above.
>
> See my reply above.
>
> >Reason #2 is "if userspace sees brightness file, it can not know if
> >the notifications on change actually work or not".
>
> If it needs to know that it can simply check the kernel version.
No. Because in case of hardware blinking we can't provide poll()
functionality.
Plus, saying "simply check the kernel version" simply means you should
not be submitting patches to kernel... at all. (Hint... it also does
not work.)
> >Reason #3 is that you broke Tony's system. Polling does not make sense
> >when trigger such as "CPU in use" is active.
>
> Have you seen v4 of my patch? It fixes this while keeping the
> polling on the brightness attribute itself, it basically goes
> back (more or less) to v1 of my patch which did not have this
> problem. I never wanted notification of trigger / blinking
> changes because I already feared Tony's problem would happen.
Have you seen v67123 of my latest facebook post? It explains why you
are completely wrong.
> >Reason #4 is that there are really two brightnesses:
> >
> >1) maximum brightness trigger is going to use
> >
> >2) current brightness
> >
> >Currently writing to "brightness" file changes 1), but reading returns
> >2) when available.
>
> Right and Jacek has already said that we cannot change the
> reading behavior on the brightness file because of ABI concerns.
Until there's user that actually reads that, ABI can be fixed. Given
that it basically returns random value,
> >So, feel free to propose better interface. One that solves #1..#4
> >above.
>
> Proposal 1:
>
> v4 of my patch, see the list. It solves all but #4, which
> is out of scope for my patch, feel free to submit a patch to
> solve #4 (with a new sysfs attr).
NAK on that. (And it does not solve #1 and #2 at least.)
> Proposal 2:
>
> Add a new "user_brightness" file, which shows the last brightness
> as set by the user, this would show the read behavior we really
> want of brightness: show the real brightness when not blinking /
> triggers are active, show the brightness used when on when
> blinking / triggers are active.
No, that's just adding more mess on the system.
Here's better proposal:
brightness (write): what we do today. (Mess, but too late to change it)
(read): -Esomething or what we do today (if someone
acutally uses it)
(poll): -Esomething
current_brightness (write): -Esomething, or maybe change brightness
for triggers that can work with that
(read, poll): if the current trigger can get current
state of led, do it, otherwise -Esomething...
or maybe file should be simply hidden from sysfs.
trigger_max_brightness (read,write): change the maximum brightness for
a trigger.
(poll): -Esomething
If you have hardware changing the brightness behind kernel's back,
that should be modelled as a trigger. Userspace should know
there's hardware changing it autonomously ... there should be
"hardware-keylight-brightness" trigger, probably impossible to change
(depends on hardware behaviour).
On thinkpad, for example, for many LEDs kernel can select either
"hardware drives the LED", but then current_brightness is unavailable,
or "kernel drives the LED", but then hardware does not touch the led
at all.
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* Applied "ASoC: mioa701_wm9713: add missing white space in dev_err message" to the regulator tree
From: Mark Brown @ 2016-11-13 9:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161112163025.4801-1-colin.king@canonical.com>
The patch
ASoC: mioa701_wm9713: add missing white space in dev_err message
has been applied to the regulator tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 28cbed38973cd458e4cdba1df9a240ce739da841 Mon Sep 17 00:00:00 2001
From: Colin Ian King <colin.king@canonical.com>
Date: Sat, 12 Nov 2016 16:30:25 +0000
Subject: [PATCH] ASoC: mioa701_wm9713: add missing white space in dev_err
message
There is a missing whitespace in the dev_err message between
"will" and "lead". Add the whitespace.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/pxa/mioa701_wm9713.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/pxa/mioa701_wm9713.c b/sound/soc/pxa/mioa701_wm9713.c
index d1661fa6ee08..0fe0abec8fc4 100644
--- a/sound/soc/pxa/mioa701_wm9713.c
+++ b/sound/soc/pxa/mioa701_wm9713.c
@@ -187,7 +187,7 @@ static int mioa701_wm9713_probe(struct platform_device *pdev)
mioa701.dev = &pdev->dev;
rc = devm_snd_soc_register_card(&pdev->dev, &mioa701);
if (!rc)
- dev_warn(&pdev->dev, "Be warned that incorrect mixers/muxes setup will"
+ dev_warn(&pdev->dev, "Be warned that incorrect mixers/muxes setup will "
"lead to overheating and possible destruction of your device."
" Do not use without a good knowledge of mio's board design!\n");
return rc;
--
2.10.2
^ permalink raw reply related
* [PATCH 6/10] clk: sunxi-ng: Add A10s CCU driver
From: Chen-Yu Tsai @ 2016-11-13 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2110deed00d33bdb557efebe8f988976fbf5a440.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi-ng/Kconfig | 10 +-
> drivers/clk/sunxi-ng/Makefile | 1 +-
> drivers/clk/sunxi-ng/ccu-sun5i-a10s.c | 755 +++++++++++++++++++++++++++-
> drivers/clk/sunxi-ng/ccu-sun5i.h | 129 +++++-
> 4 files changed, 895 insertions(+), 0 deletions(-)
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun5i-a10s.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun5i.h
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 8454c6e3dd65..e2becd36a1f9 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -64,6 +64,16 @@ config SUN50I_A64_CCU
> select SUNXI_CCU_PHASE
> default ARM64 && ARCH_SUNXI
>
> +config SUN5I_A10S_CCU
> + bool "Support for the Allwinner A10s CCM"
> + select SUNXI_CCU_DIV
> + select SUNXI_CCU_NK
> + select SUNXI_CCU_NKM
> + select SUNXI_CCU_NM
> + select SUNXI_CCU_MP
> + select SUNXI_CCU_PHASE
> + default MACH_SUN5I
> +
> config SUN6I_A31_CCU
> bool "Support for the Allwinner A31/A31s CCU"
> select SUNXI_CCU_DIV
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 24fbc6e5deb8..79e9a166dc83 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
>
> # SoC support
> obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
> +obj-$(CONFIG_SUN5I_A10S_CCU) += ccu-sun5i-a10s.o
> obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
> obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
> obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun5i-a10s.c b/drivers/clk/sunxi-ng/ccu-sun5i-a10s.c
> new file mode 100644
> index 000000000000..94d9a5cbf60b
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun5i-a10s.c
> @@ -0,0 +1,755 @@
> +/*
> + * Copyright (c) 2016 Maxime Ripard. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +#include "ccu_phase.h"
> +
> +#include "ccu-sun5i.h"
> +
> +static struct ccu_nkmp pll_core_clk = {
> + .enable = BIT(31),
> + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .m = _SUNXI_CCU_DIV(0, 2),
> + .p = _SUNXI_CCU_DIV(16, 2),
> + .common = {
> + .reg = 0x000,
> + .hw.init = CLK_HW_INIT("pll-core",
> + "hosc",
> + &ccu_nkmp_ops,
> + 0),
> + },
> +};
> +
> +/*
> + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
> + * the base (2x, 4x and 8x), and one variable divider (the one true
> + * pll audio).
> + *
> + * We don't have any need for the variable divider for now, so we just
> + * hardcode it to match with the clock names
> + */
> +#define SUN5I_PLL_AUDIO_REG 0x008
> +
> +static struct ccu_nm pll_audio_base_clk = {
> + .enable = BIT(31),
> + .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
> + .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
Nit: a note explaining that the datasheet is wrong would be nice.
> + .common = {
> + .reg = 0x008,
> + .hw.init = CLK_HW_INIT("pll-audio-base",
> + "hosc",
> + &ccu_nm_ops,
> + 0),
> + },
> +};
> +
> +static struct ccu_mult pll_video0_clk = {
> + .enable = BIT(31),
> + .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
> + .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
> + 270000000, 297000000),
> + .common = {
> + .reg = 0x010,
> + .features = CCU_FEATURE_FRACTIONAL,
> + .hw.init = CLK_HW_INIT("pll-video0",
> + "osc3M",
> + &ccu_mult_ops,
> + 0),
> + },
> +};
> +
> +static struct ccu_nkmp pll_ve_clk = {
> + .enable = BIT(31),
> + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .m = _SUNXI_CCU_DIV(0, 2),
> + .p = _SUNXI_CCU_DIV(16, 2),
Any chance we'll support the bypass switch on this one?
> + .common = {
> + .reg = 0x018,
> + .hw.init = CLK_HW_INIT("pll-ve",
> + "hosc",
> + &ccu_nkmp_ops,
> + 0),
> + },
> +};
> +
> +static struct ccu_nk pll_ddr_base_clk = {
> + .enable = BIT(31),
> + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .common = {
> + .reg = 0x020,
> + .hw.init = CLK_HW_INIT("pll-ddr-base",
> + "hosc",
> + &ccu_nk_ops,
> + 0),
> + },
> +};
> +
> +static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2, 0);
Maybe we should set CLK_IS_CRITICAL on this one as well... in case the
bootloader uses pll-periph for mbus, and none of the dram gates are enabled.
> +
> +static struct ccu_div pll_ddr_other_clk = {
> + .div = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
> +
> + .common = {
> + .reg = 0x020,
> + .hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
> + &ccu_div_ops,
> + 0),
> + },
> +};
> +
> +static struct ccu_nk pll_periph_clk = {
> + .enable = BIT(31),
> + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .fixed_post_div = 2,
> + .common = {
> + .reg = 0x028,
> + .features = CCU_FEATURE_FIXED_POSTDIV,
> + .hw.init = CLK_HW_INIT("pll-periph",
> + "hosc",
> + &ccu_nk_ops,
> + 0),
> + },
> +};
> +
> +static struct ccu_mult pll_video1_clk = {
> + .enable = BIT(31),
> + .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
> + .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
> + 270000000, 297000000),
> + .common = {
> + .reg = 0x030,
> + .features = CCU_FEATURE_FRACTIONAL,
> + .hw.init = CLK_HW_INIT("pll-video1",
> + "osc3M",
> + &ccu_mult_ops,
> + 0),
> + },
> +};
> +
> +static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
Why the extra "hosc" clock here? You should probably just internalize "osc24M".
> +
> +#define SUN5I_AHB_REG 0x054
> +static const char * const cpu_parents[] = { "osc32k", "hosc",
> + "pll-core" , "pll-periph" };
> +static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
> + { .index = 3, .div = 3, },
> +};
> +static struct ccu_mux cpu_clk = {
> + .mux = {
> + .shift = 16,
> + .width = 2,
> + .fixed_predivs = cpu_predivs,
> + .n_predivs = ARRAY_SIZE(cpu_predivs),
> + },
> + .common = {
> + .reg = 0x054,
> + .features = CCU_FEATURE_FIXED_PREDIV,
> + .hw.init = CLK_HW_INIT_PARENTS("cpu",
> + cpu_parents,
> + &ccu_mux_ops,
> + CLK_IS_CRITICAL),
> + }
> +};
> +
> +static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
> +
> +static const char * const ahb_parents[] = { "axi" , "cpu", "pll-periph" };
> +static struct ccu_div ahb_clk = {
> + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
> + .mux = _SUNXI_CCU_MUX(6, 2),
There's a fixed /2 pre-divider on pll-periph.
> +
> + .common = {
> + .reg = 0x054,
> + .hw.init = CLK_HW_INIT_PARENTS("ahb",
> + ahb_parents,
> + &ccu_div_ops,
> + 0),
> + },
> +};
> +
> +static struct clk_div_table apb0_div_table[] = {
> + { .val = 0, .div = 2 },
> + { .val = 1, .div = 2 },
> + { .val = 2, .div = 4 },
> + { .val = 3, .div = 8 },
> + { /* Sentinel */ },
> +};
> +static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
> + 0x054, 8, 2, apb0_div_table, 0);
> +
> +static const char * const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
> +static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
> + 0, 5, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + 0);
> +
> +static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "axi",
> + 0x05c, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
> + 0x060, BIT(0), 0);
> +static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
> + 0x060, BIT(1), 0);
> +static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
> + 0x060, BIT(2), 0);
> +static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
> + 0x060, BIT(5), 0);
> +static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
> + 0x060, BIT(6), 0);
> +static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
> + 0x060, BIT(6), 0);
> +static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
> + 0x060, BIT(8), 0);
> +static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
> + 0x060, BIT(9), 0);
> +static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
> + 0x060, BIT(10), 0);
> +static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
> + 0x060, BIT(13), 0);
> +static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
> + 0x060, BIT(14), CLK_IS_CRITICAL);
> +static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
> + 0x060, BIT(17), 0);
> +static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
> + 0x060, BIT(18), 0);
> +static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
> + 0x060, BIT(20), 0);
> +static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
> + 0x060, BIT(21), 0);
> +static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
> + 0x060, BIT(22), 0);
> +static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
> + 0x060, BIT(26), 0);
> +static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
> + 0x060, BIT(28), 0);
> +
> +static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
> + 0x064, BIT(0), 0);
> +static SUNXI_CCU_GATE(ahb_tve_clk, "ahb-tve", "ahb",
> + 0x064, BIT(2), 0);
> +static SUNXI_CCU_GATE(ahb_lcd_clk, "ahb-lcd", "ahb",
> + 0x064, BIT(4), 0);
> +static SUNXI_CCU_GATE(ahb_csi_clk, "ahb-csi", "ahb",
> + 0x064, BIT(8), 0);
> +static SUNXI_CCU_GATE(ahb_hdmi_clk, "ahb-hdmi", "ahb",
> + 0x064, BIT(11), 0);
> +static SUNXI_CCU_GATE(ahb_de_be_clk, "ahb-de-be", "ahb",
> + 0x064, BIT(12), 0);
> +static SUNXI_CCU_GATE(ahb_de_fe_clk, "ahb-de-fe", "ahb",
> + 0x064, BIT(14), 0);
> +static SUNXI_CCU_GATE(ahb_iep_clk, "ahb-iep", "ahb",
> + 0x064, BIT(19), 0);
> +static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
> + 0x064, BIT(20), 0);
> +
> +static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
> + 0x068, BIT(0), 0);
> +static SUNXI_CCU_GATE(apb0_i2s_clk, "apb0-i2s", "apb0",
> + 0x068, BIT(3), 0);
> +static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
> + 0x068, BIT(5), 0);
> +static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
> + 0x068, BIT(6), 0);
> +static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
> + 0x068, BIT(10), 0);
> +
> +static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
> + 0x06c, BIT(0), 0);
> +static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
> + 0x06c, BIT(1), 0);
> +static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
> + 0x06c, BIT(2), 0);
> +static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
> + 0x06c, BIT(16), 0);
> +static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
> + 0x06c, BIT(17), 0);
> +static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
> + 0x06c, BIT(18), 0);
> +static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
> + 0x06c, BIT(19), 0);
> +
> +static const char * const mod0_default_parents[] = { "hosc", "pll-periph",
> + "pll-ddr-other" };
> +static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", mod0_default_parents, 0x0b0,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +
> +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
> + "pll-audio-2x", "pll-audio" };
> +static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_parents,
> + 0x0b8, 16, 2, BIT(31), 0);
CLK_SET_RATE_PARENT please.
> +
> +static const char * const keypad_parents[] = { "hosc", "losc"};
> +static const u8 keypad_table[] = { 0, 2 };
> +static struct ccu_mp keypad_clk = {
> + .enable = BIT(31),
> + .m = _SUNXI_CCU_DIV(8, 5),
> + .p = _SUNXI_CCU_DIV(20, 2),
> + .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
> +
> + .common = {
> + .reg = 0x0c4,
> + .hw.init = CLK_HW_INIT_PARENTS("keypad",
> + keypad_parents,
> + &ccu_mp_ops,
> + 0),
> + },
> +};
> +
> +static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "pll-periph",
> + 0x0cc, BIT(6), 0);
> +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "pll-periph",
> + 0x0cc, BIT(8), 0);
> +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "pll-periph",
> + 0x0cc, BIT(9), 0);
> +
> +static const char * const gps_parents[] = { "hosc", "pll-periph",
> + "pll-video1", "pll-ve" };
> +static SUNXI_CCU_M_WITH_MUX_GATE(gps_clk, "gps", gps_parents,
> + 0x0d0, 0, 3, 24, 2, BIT(31), 0);
> +
> +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
> + 0x100, BIT(0), 0);
> +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
> + 0x100, BIT(1), 0);
> +static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
> + 0x100, BIT(3), 0);
> +static SUNXI_CCU_GATE(dram_tve_clk, "dram-tve", "pll-ddr",
> + 0x100, BIT(5), 0);
> +static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
> + 0x100, BIT(25), 0);
> +static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
> + 0x100, BIT(26), 0);
> +static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
> + 0x100, BIT(29), 0);
> +static SUNXI_CCU_GATE(dram_iep_clk, "dram-iep", "pll-ddr",
> + 0x100, BIT(31), 0);
> +
> +static const char * const de_parents[] = { "pll-video0", "pll-video1",
> + "pll-ddr-other" };
> +static SUNXI_CCU_M_WITH_MUX_GATE(de_be_clk, "de-be", de_parents,
> + 0x104, 0, 4, 24, 2, BIT(31), 0);
> +
> +static SUNXI_CCU_M_WITH_MUX_GATE(de_fe_clk, "de-fe", de_parents,
> + 0x10c, 0, 4, 24, 2, BIT(31), 0);
> +
> +static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
> + "pll-video0-2x", "pll-video1-2x" };
> +static SUNXI_CCU_MUX_WITH_GATE(tcon_ch0_clk, "tcon-ch0-sclk", tcon_parents,
> + 0x118, 24, 2, BIT(31), 0);
CLK_SET_RATE_PARENT?
> +
> +static SUNXI_CCU_M_WITH_MUX_GATE(tcon_ch1_sclk2_clk, "tcon-ch1-sclk2",
> + tcon_parents,
> + 0x12c, 0, 4, 24, 2, BIT(31), 0);
CLK_SET_RATE_PARENT?
> +
> +static SUNXI_CCU_M_WITH_GATE(tcon_ch1_sclk1_clk, "tcon-ch1-sclk1", "tcon-ch1-sclk2",
> + 0x12c, 11, 1, BIT(15), 0);
CLK_SET_RATE_PARENT?
> +
> +static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
> + "pll-video0-2x", "pll-video1-2x" };
> +static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
> +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
> + csi_parents, csi_table,
> + 0x134, 0, 5, 24, 2, BIT(31), 0);
Do you know if CSI needs to change the module clock?
> +
> +static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve",
> + 0x13c, BIT(31), 0);
CLK_SET_RATE_PARENT?
> +
> +static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
> + 0x140, BIT(31), 0);
CLK_SET_RATE_PARENT?
> +
> +static SUNXI_CCU_GATE(avs_clk, "avs", "hosc",
> + 0x144, BIT(31), 0);
> +
> +static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-2x" };
> +static const u8 hdmi_table[] = { 0, 2 };
> +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi",
> + hdmi_parents, hdmi_table,
> + 0x150, 0, 4, 24, 2, BIT(31), 0);
CLK_SET_RATE_PARENT?
> +
> +static const char * const gpu_parents[] = { "pll-video0", "pll-ve",
> + "pll-ddr-other", "pll-video1",
> + "pll-video1-2x" };
> +static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents,
> + 0x154, 0, 4, 24, 3, BIT(31), 0);
> +
> +static const char * const mbus_parents[] = { "hosc", "pll-periph", "pll-ddr" };
> +static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
> + 0x15c, 0, 4, 16, 2, 24, 2, BIT(31), CLK_IS_CRITICAL);
> +
> +static SUNXI_CCU_GATE(iep_clk, "iep", "de-be",
> + 0x160, BIT(31), 0);
> +
> +static struct ccu_common *sun5i_a10s_ccu_clks[] = {
> + &hosc_clk.common,
> + &pll_core_clk.common,
> + &pll_audio_base_clk.common,
> + &pll_video0_clk.common,
> + &pll_ve_clk.common,
> + &pll_ddr_base_clk.common,
> + &pll_ddr_clk.common,
> + &pll_ddr_other_clk.common,
> + &pll_periph_clk.common,
> + &pll_video1_clk.common,
> + &cpu_clk.common,
> + &axi_clk.common,
> + &ahb_clk.common,
> + &apb0_clk.common,
> + &apb1_clk.common,
> + &axi_dram_clk.common,
> + &ahb_otg_clk.common,
> + &ahb_ehci_clk.common,
> + &ahb_ohci_clk.common,
> + &ahb_ss_clk.common,
> + &ahb_dma_clk.common,
> + &ahb_bist_clk.common,
> + &ahb_mmc0_clk.common,
> + &ahb_mmc1_clk.common,
> + &ahb_mmc2_clk.common,
> + &ahb_nand_clk.common,
> + &ahb_sdram_clk.common,
> + &ahb_emac_clk.common,
> + &ahb_ts_clk.common,
> + &ahb_spi0_clk.common,
> + &ahb_spi1_clk.common,
> + &ahb_spi2_clk.common,
> + &ahb_gps_clk.common,
> + &ahb_hstimer_clk.common,
> + &ahb_ve_clk.common,
> + &ahb_tve_clk.common,
> + &ahb_lcd_clk.common,
> + &ahb_csi_clk.common,
> + &ahb_hdmi_clk.common,
> + &ahb_de_be_clk.common,
> + &ahb_de_fe_clk.common,
> + &ahb_iep_clk.common,
> + &ahb_gpu_clk.common,
> + &apb0_codec_clk.common,
> + &apb0_i2s_clk.common,
> + &apb0_pio_clk.common,
> + &apb0_ir_clk.common,
> + &apb0_keypad_clk.common,
> + &apb1_i2c0_clk.common,
> + &apb1_i2c1_clk.common,
> + &apb1_i2c2_clk.common,
> + &apb1_uart0_clk.common,
> + &apb1_uart1_clk.common,
> + &apb1_uart2_clk.common,
> + &apb1_uart3_clk.common,
> + &nand_clk.common,
> + &mmc0_clk.common,
> + &mmc1_clk.common,
> + &mmc2_clk.common,
> + &ts_clk.common,
> + &ss_clk.common,
> + &spi0_clk.common,
> + &spi1_clk.common,
> + &spi2_clk.common,
> + &ir_clk.common,
> + &i2s_clk.common,
> + &keypad_clk.common,
> + &usb_ohci_clk.common,
> + &usb_phy0_clk.common,
> + &usb_phy1_clk.common,
> + &gps_clk.common,
> + &dram_ve_clk.common,
> + &dram_csi_clk.common,
> + &dram_ts_clk.common,
> + &dram_tve_clk.common,
> + &dram_de_fe_clk.common,
> + &dram_de_be_clk.common,
> + &dram_ace_clk.common,
> + &dram_iep_clk.common,
> + &de_be_clk.common,
> + &de_fe_clk.common,
> + &tcon_ch0_clk.common,
> + &tcon_ch1_sclk2_clk.common,
> + &tcon_ch1_sclk1_clk.common,
> + &csi_clk.common,
> + &ve_clk.common,
> + &codec_clk.common,
> + &avs_clk.common,
> + &hdmi_clk.common,
> + &gpu_clk.common,
> + &mbus_clk.common,
> + &iep_clk.common,
> +};
> +
> +static CLK_FIXED_FACTOR(osc3M_clk, "osc3M", "hosc", 8, 1, 0);
> +/* We hardcode the divider to 4 for now */
> +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
> + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
> + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
> + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
> + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
> + "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
> + "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
> +
> +static struct clk_hw_onecell_data sun5i_a10s_hw_clks = {
> + .hws = {
> + [CLK_HOSC] = &hosc_clk.common.hw,
> + [CLK_OSC3M] = &osc3M_clk.hw,
> + [CLK_PLL_CORE] = &pll_core_clk.common.hw,
> + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
> + [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
> + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
> + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
> + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
> + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
> + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
> + [CLK_PLL_VE] = &pll_ve_clk.common.hw,
> + [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
> + [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
> + [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
> + [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
> + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
> + [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
> + [CLK_CPU] = &cpu_clk.common.hw,
> + [CLK_AXI] = &axi_clk.common.hw,
> + [CLK_AHB] = &ahb_clk.common.hw,
> + [CLK_APB0] = &apb0_clk.common.hw,
> + [CLK_APB1] = &apb1_clk.common.hw,
> + [CLK_DRAM_AXI] = &axi_dram_clk.common.hw,
> + [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
> + [CLK_AHB_EHCI] = &ahb_ehci_clk.common.hw,
> + [CLK_AHB_OHCI] = &ahb_ohci_clk.common.hw,
> + [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
> + [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
> + [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
> + [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
> + [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
> + [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
> + [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
> + [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
> + [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
> + [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
> + [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
> + [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
> + [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
> + [CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
> + [CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
> + [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
> + [CLK_AHB_TVE] = &ahb_tve_clk.common.hw,
> + [CLK_AHB_LCD] = &ahb_lcd_clk.common.hw,
> + [CLK_AHB_CSI] = &ahb_csi_clk.common.hw,
> + [CLK_AHB_HDMI] = &ahb_hdmi_clk.common.hw,
> + [CLK_AHB_DE_BE] = &ahb_de_be_clk.common.hw,
> + [CLK_AHB_DE_FE] = &ahb_de_fe_clk.common.hw,
> + [CLK_AHB_IEP] = &ahb_iep_clk.common.hw,
> + [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
> + [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
> + [CLK_APB0_I2S] = &apb0_i2s_clk.common.hw,
> + [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
> + [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
> + [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
> + [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
> + [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
> + [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
> + [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
> + [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
> + [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
> + [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
> + [CLK_NAND] = &nand_clk.common.hw,
> + [CLK_MMC0] = &mmc0_clk.common.hw,
> + [CLK_MMC1] = &mmc1_clk.common.hw,
> + [CLK_MMC2] = &mmc2_clk.common.hw,
> + [CLK_TS] = &ts_clk.common.hw,
> + [CLK_SS] = &ss_clk.common.hw,
> + [CLK_SPI0] = &spi0_clk.common.hw,
> + [CLK_SPI1] = &spi1_clk.common.hw,
> + [CLK_SPI2] = &spi2_clk.common.hw,
> + [CLK_IR] = &ir_clk.common.hw,
> + [CLK_I2S] = &i2s_clk.common.hw,
> + [CLK_KEYPAD] = &keypad_clk.common.hw,
> + [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
> + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
> + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
> + [CLK_GPS] = &gps_clk.common.hw,
> + [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
> + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
> + [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
> + [CLK_DRAM_TVE] = &dram_tve_clk.common.hw,
> + [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
> + [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
> + [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
> + [CLK_DRAM_IEP] = &dram_iep_clk.common.hw,
> + [CLK_DE_BE] = &de_be_clk.common.hw,
> + [CLK_DE_FE] = &de_fe_clk.common.hw,
> + [CLK_TCON_CH0] = &tcon_ch0_clk.common.hw,
> + [CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
> + [CLK_TCON_CH1] = &tcon_ch1_sclk1_clk.common.hw,
> + [CLK_CSI] = &csi_clk.common.hw,
> + [CLK_VE] = &ve_clk.common.hw,
> + [CLK_CODEC] = &codec_clk.common.hw,
> + [CLK_AVS] = &avs_clk.common.hw,
> + [CLK_HDMI] = &hdmi_clk.common.hw,
> + [CLK_GPU] = &gpu_clk.common.hw,
> + [CLK_MBUS] = &mbus_clk.common.hw,
> + [CLK_IEP] = &iep_clk.common.hw,
> + },
> + .num = CLK_NUMBER,
> +};
> +
> +static struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
> + [RST_USB_PHY0] = { 0x0cc, BIT(0) },
> + [RST_USB_PHY1] = { 0x0cc, BIT(1) },
> +
> + [RST_GPS] = { 0x0d0, BIT(30) },
> +
> + [RST_DE_BE] = { 0x104, BIT(30) },
> +
> + [RST_DE_FE] = { 0x10c, BIT(30) },
> +
> + [RST_TVE] = { 0x118, BIT(29) },
> + [RST_LCD] = { 0x118, BIT(30) },
> +
> + [RST_CSI] = { 0x134, BIT(30) },
> +
> + [RST_VE] = { 0x13c, BIT(0) },
> +
> + [RST_GPU] = { 0x154, BIT(30) },
> +
> + [RST_IEP] = { 0x160, BIT(30) },
> +};
> +
> +static const struct sunxi_ccu_desc sun5i_a10s_ccu_desc = {
> + .ccu_clks = sun5i_a10s_ccu_clks,
> + .num_ccu_clks = ARRAY_SIZE(sun5i_a10s_ccu_clks),
> +
> + .hw_clks = &sun5i_a10s_hw_clks,
> +
> + .resets = sun5i_a10s_ccu_resets,
> + .num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
> +};
> +
> +static void __init sun5i_a10s_ccu_setup(struct device_node *node)
> +{
> + void __iomem *reg;
> + u32 val;
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg)) {
> + pr_err("%s: Could not map the clock registers\n",
> + of_node_full_name(node));
> + return;
> + }
> +
> + /* Force the PLL-Audio-1x divider to 4 */
> + val = readl(reg + SUN5I_PLL_AUDIO_REG);
> + val &= ~GENMASK(19, 16);
> + writel(val | (3 << 16), reg + SUN5I_PLL_AUDIO_REG);
> +
> + /*
> + * Use the peripheral PLL as the AHB parent, instead of CPU /
> + * AXI which have rate changes due to cpufreq.
> + *
> + * This is especially a big deal for the HS timer whose parent
> + * clock is AHB.
> + */
> + val = readl(reg + SUN5I_AHB_REG);
> + val &= ~GENMASK(7, 6);
> + writel(val | (2 << 6), reg + SUN5I_AHB_REG);
> +
> + sunxi_ccu_probe(node, reg, &sun5i_a10s_ccu_desc);
> +}
> +CLK_OF_DECLARE(sun5i_a10s_ccu, "allwinner,sun5i-a10s-ccu",
> + sun5i_a10s_ccu_setup);
> diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.h b/drivers/clk/sunxi-ng/ccu-sun5i.h
> new file mode 100644
> index 000000000000..43f2ce3e9e6e
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun5i.h
> @@ -0,0 +1,129 @@
> +/*
> + * Copyright 2016 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _CCU_SUN5I_H_
> +#define _CCU_SUN5I_H_
> +
> +#include <dt-bindings/clock/sun5i-ccu.h>
> +#include <dt-bindings/reset/sun5i-ccu.h>
> +
> +#define CLK_HOSC 1
> +#define CLK_OSC3M 2
> +#define CLK_PLL_CORE 3
> +#define CLK_PLL_AUDIO_BASE 4
> +#define CLK_PLL_AUDIO 5
> +#define CLK_PLL_AUDIO_2X 6
> +#define CLK_PLL_AUDIO_4X 7
> +#define CLK_PLL_AUDIO_8X 8
> +#define CLK_PLL_VIDEO0 9
> +#define CLK_PLL_VIDEO0_2X 10
> +#define CLK_PLL_VE 11
> +#define CLK_PLL_DDR_BASE 12
> +#define CLK_PLL_DDR 13
> +#define CLK_PLL_DDR_OTHER 14
> +#define CLK_PLL_PERIPH 15
> +#define CLK_PLL_VIDEO1 16
> +#define CLK_PLL_VIDEO1_2X 17
> +#define CLK_OSC24M 18
> +#define CLK_CPU 19
> +#define CLK_AXI 20
> +#define CLK_AHB 21
> +#define CLK_APB0 22
> +#define CLK_APB1 23
> +#define CLK_DRAM_AXI 24
> +#define CLK_AHB_OTG 25
> +#define CLK_AHB_EHCI 26
> +#define CLK_AHB_OHCI 27
> +#define CLK_AHB_SS 28
> +#define CLK_AHB_DMA 29
> +#define CLK_AHB_BIST 30
> +#define CLK_AHB_MMC0 31
> +#define CLK_AHB_MMC1 32
> +#define CLK_AHB_MMC2 33
> +#define CLK_AHB_NAND 34
> +#define CLK_AHB_SDRAM 35
> +#define CLK_AHB_EMAC 36
> +#define CLK_AHB_TS 37
> +#define CLK_AHB_SPI0 38
> +#define CLK_AHB_SPI1 39
> +#define CLK_AHB_SPI2 40
> +#define CLK_AHB_GPS 41
> +#define CLK_AHB_HSTIMER 42
> +#define CLK_AHB_VE 43
> +#define CLK_AHB_TVE 44
> +#define CLK_AHB_LCD 45
> +#define CLK_AHB_CSI 46
> +#define CLK_AHB_HDMI 47
> +#define CLK_AHB_DE_BE 48
> +#define CLK_AHB_DE_FE 49
> +#define CLK_AHB_IEP 50
> +#define CLK_AHB_GPU 51
> +#define CLK_APB0_CODEC 52
> +#define CLK_APB0_SPDIF 53
> +#define CLK_APB0_I2S 54
> +#define CLK_APB0_PIO 55
> +#define CLK_APB0_IR 56
> +#define CLK_APB0_KEYPAD 57
> +#define CLK_APB1_I2C0 58
> +#define CLK_APB1_I2C1 59
> +#define CLK_APB1_I2C2 60
> +#define CLK_APB1_UART0 61
> +#define CLK_APB1_UART1 62
> +#define CLK_APB1_UART2 63
> +#define CLK_APB1_UART3 64
> +#define CLK_NAND 65
> +#define CLK_MMC0 66
> +#define CLK_MMC1 67
> +#define CLK_MMC2 68
> +#define CLK_TS 69
> +#define CLK_SS 70
> +#define CLK_CE 71
> +#define CLK_SPI0 72
> +#define CLK_SPI1 73
> +#define CLK_SPI2 74
> +#define CLK_IR 75
> +#define CLK_I2S 76
> +#define CLK_SPDIF 77
> +#define CLK_KEYPAD 78
> +#define CLK_USB_OHCI 79
> +#define CLK_USB_PHY0 80
> +#define CLK_USB_PHY1 81
> +#define CLK_GPS 82
> +#define CLK_DRAM_VE 83
> +#define CLK_DRAM_CSI 84
> +#define CLK_DRAM_TS 85
> +#define CLK_DRAM_TVE 86
> +#define CLK_DRAM_DE_FE 87
> +#define CLK_DRAM_DE_BE 88
> +#define CLK_DRAM_ACE 89
> +#define CLK_DRAM_IEP 90
> +#define CLK_DE_BE 91
> +#define CLK_DE_FE 92
> +#define CLK_TCON_CH0 93
> +#define CLK_TCON_CH1_SCLK 94
> +#define CLK_TCON_CH1 95
> +#define CLK_CSI 96
> +#define CLK_VE 97
> +#define CLK_CODEC 98
> +#define CLK_AVS 99
> +#define CLK_HDMI 100
> +#define CLK_GPU 101
> +#define CLK_MBUS 102
> +#define CLK_IEP 103
> +
> +#define CLK_NUMBER (CLK_IEP + 1)
> +
> +#endif /* _CCU_SUN5I_H_ */
Didn't you already list all the clocks in the device tree bindings header
patch 5?
Regards
ChenYu
^ permalink raw reply
* Three different LED brightnesses (was Re: PM regression with LED changes in next-20161109)
From: Hans de Goede @ 2016-11-13 9:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161113091054.GA17790@amd>
Hi,
On 13-11-16 10:10, Pavel Machek wrote:
> On Sat 2016-11-12 09:03:42, Hans de Goede wrote:
>> Hi,
>>
>> On 11-11-16 23:12, Pavel Machek wrote:
>>> Hi!
>>>
>>> Reason #1:
>>>
>>>>>> Hmm. So userland can read the LED state, and it can get _some_ value
>>>>>> back, but it can not know if it is current state or not.
>>
>> That is not correct, the current behavior for eading the brightness
>> atrribute is to always return the current state.
>
> No. (Because some hardware can't get back current state of
> hardware-controlled leds, and because of blinking).
>
>>>> Why a dedicated file? Are we going to mirror brightness here
>>>> wrt r/w (show/store) behavior ? If not userspace now needs
>>>> 2 open fds which is not really nice. If we are and we are
>>>> not going to use poll for something else on brightness itself
>>>> then why not just poll directly on brightness ?
>>>
>>> Reason #1 is above.
>>
>> See my reply above.
>>
>>> Reason #2 is "if userspace sees brightness file, it can not know if
>>> the notifications on change actually work or not".
>>
>> If it needs to know that it can simply check the kernel version.
>
> No. Because in case of hardware blinking we can't provide poll()
> functionality.
We have already decided that we do not want to wakeup poll()
on blinking because it causes to many wakeups, and there is
no use-case for waking poll for blinking (or for triggers).
> Plus, saying "simply check the kernel version" simply means you should
> not be submitting patches to kernel... at all. (Hint... it also does
> not work.)
Lets keep things civil please.
>>> Reason #3 is that you broke Tony's system. Polling does not make sense
>>> when trigger such as "CPU in use" is active.
>>
>> Have you seen v4 of my patch? It fixes this while keeping the
>> polling on the brightness attribute itself, it basically goes
>> back (more or less) to v1 of my patch which did not have this
>> problem. I never wanted notification of trigger / blinking
>> changes because I already feared Tony's problem would happen.
>
> Have you seen v67123 of my latest facebook post? It explains why you
> are completely wrong.
Lets keep things civil please.
>>> Reason #4 is that there are really two brightnesses:
>>>
>>> 1) maximum brightness trigger is going to use
>>>
>>> 2) current brightness
>>>
>>> Currently writing to "brightness" file changes 1), but reading returns
>>> 2) when available.
>>
>> Right and Jacek has already said that we cannot change the
>> reading behavior on the brightness file because of ABI concerns.
>
> Until there's user that actually reads that, ABI can be fixed. Given
> that it basically returns random value,
Jacek has pretty much nacked fixing this because of ABI concerns,
so I see no use in further discussing changing the read behavior
of the existing brightness sysfs attribute.
>>> So, feel free to propose better interface. One that solves #1..#4
>>> above.
>>
>> Proposal 1:
>>
>> v4 of my patch, see the list. It solves all but #4, which
>> is out of scope for my patch, feel free to submit a patch to
>> solve #4 (with a new sysfs attr).
>
> NAK on that. (And it does not solve #1 and #2 at least.)
>
>> Proposal 2:
>>
>> Add a new "user_brightness" file, which shows the last brightness
>> as set by the user, this would show the read behavior we really
>> want of brightness: show the real brightness when not blinking /
>> triggers are active, show the brightness used when on when
>> blinking / triggers are active.
>
> No, that's just adding more mess on the system.
>
> Here's better proposal:
>
> brightness (write): what we do today. (Mess, but too late to change it)
> (read): -Esomething or what we do today (if someone
> acutally uses it)
As said Jacek has already nacked any changes to read behavior.
> (poll): -Esomething
Making poll() on sysfs attributes return -Esomething is not possible,
the internal sysfs API does not allow this.
> current_brightness (write): -Esomething, or maybe change brightness
> for triggers that can work with that
> (read, poll): if the current trigger can get current
> state of led, do it, otherwise -Esomething...
> or maybe file should be simply hidden from sysfs.
So write is -EINVAL and read is the same as what brightness currently does,
so I see no use in introducing this new file.
Also this reintroduces all the issues of v2 of my poll() patch since the
CPU load problem is not actually in waking up userspace, it is in
even checking if there are any userspace waiters. TLDR we simply cannot
have poll behavior where we need to try and wakeup userspace on
every blink / every time a trigger triggers.
> trigger_max_brightness (read,write): change the maximum brightness for
> a trigger.
> (poll): -Esomething
The write behavior here is the same as what brightness currently does
and the read behavior is that of what I suggested for user_brightness,
minus that you've not definied the read behavior for when no trigger /
blinking is active.
In itself I would be fine with this file to work around the read
behavior of trigger_max_brightness, but you've not solved the
polling problem.
We've 2 sorts of brightness really:
1) transient brightness, aka current brightness, when blinking or
triggers are used this will switch many times a second
between off and some on level.
2) non-transient brightness, for non blinking leds this is the
actual brightness, for blinking leds this is the brightness
level used when the led is on.
Now we want to have a sysfs attribute reflecting 2, so that
userspace can poll on that, both for my use-case as well as so
that userspace process a can detect changes made by writing to
the brightness file by process b.
So maybe we need to simply call the new attribute
non_transient_brightness instead of user_brightness?
> If you have hardware changing the brightness behind kernel's back,
> that should be modelled as a trigger. Userspace should know
> there's hardware changing it autonomously ... there should be
> "hardware-keylight-brightness" trigger, probably impossible to change
> (depends on hardware behaviour).
>
> On thinkpad, for example, for many LEDs kernel can select either
> "hardware drives the LED", but then current_brightness is unavailable,
> or "kernel drives the LED", but then hardware does not touch the led
> at all.
Whether or not the hardware changing the brightness behind kernel's
should be modeled as a trigger is really outside of the scope of
this discussion, as it is not related to the issues with the
brightness atrribute / polling on the brightness attribute.
Regards,
Hans
^ permalink raw reply
* [PATCH 7/10] clk: sunxi-ng: Add A13 CCU driver
From: Chen-Yu Tsai @ 2016-11-13 9:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1fe10e9ca64dce0a06a2d83693cbaf6ee3a76bde.1478625788.git-series.maxime.ripard@free-electrons.com>
On Wed, Nov 9, 2016 at 1:23 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi-ng/Kconfig | 10 +-
> drivers/clk/sunxi-ng/Makefile | 1 +-
> drivers/clk/sunxi-ng/ccu-sun5i-a13.c | 681 ++++++++++++++++++++++++++++-
> 3 files changed, 692 insertions(+), 0 deletions(-)
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun5i-a13.c
I'm not sure what to make of this one. Presumably this is the same as the A10s,
with some bits (TS, HDMI, I2S, GPS) removed. BTW you kept the GPS reset control
in this one.
Hans and others have said and IIRC proven that the sun5i is the same die, with
some exposing more peripherals than others. Wouldn't it make sense to use the
same CCU driver for all of them? It's not like Allwinner actually disabled the
clock control or hardware block.
If you don't like it, perhaps you can share the same set of definitions, but
have separate lists of what clocks are registered, for each SoC variant. That
would at least cut down on code size and the effort to maintain 3 copies of
almost the exact same thing.
I guess the same applies to the GR8 CCU driver patch. And the comments from
the previous (A10s CCU driver) patch applies to both.
Let me know what you think.
Regards
ChenYu
^ permalink raw reply
* [PATCH devicetree/next] ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1
From: Rafał Miłecki @ 2016-11-13 10:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Rafa? Mi?ecki <rafal@milecki.pl>
It's BCM4709A0 based device with 16 MiB flash, 128 MiB of RAM and two
PCIe based on-PCB BCM4360 chipsets.
Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 114 ++++++++++++++++++++++
2 files changed, 115 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 837703a..7a52a9f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-buffalo-wxr-1900dhp.dtb \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb \
+ bcm4709-tplink-archer-c9-v1.dtb \
bcm47094-dlink-dir-885l.dtb \
bcm47094-luxul-xwr-3100.dtb \
bcm47094-netgear-r8500.dtb \
diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
new file mode 100644
index 0000000..9a92c24
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2016 Rafa? Mi?ecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm4709.dtsi"
+
+/ {
+ compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708";
+ model = "TP-LINK Archer C9 V1";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory {
+ reg = <0x00000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ lan {
+ label = "bcm53xx:blue:lan";
+ gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wps {
+ label = "bcm53xx:blue:wps";
+ gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ 2ghz {
+ label = "bcm53xx:blue:2ghz";
+ gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ 5ghz {
+ label = "bcm53xx:blue:5ghz";
+ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb3 {
+ label = "bcm53xx:blue:usb3";
+ gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ usb2 {
+ label = "bcm53xx:blue:usb2";
+ gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wan-blue {
+ label = "bcm53xx:blue:wan";
+ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ wan-amber {
+ label = "bcm53xx:amber:wan";
+ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-off";
+ };
+
+ power {
+ label = "bcm53xx:blue:power";
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+ };
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb2 {
+ vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
+};
+
+&spi_nor {
+ status = "okay";
+};
--
2.10.1
^ permalink raw reply related
* [PATCH 0/2] mmc: allow mmc_alloc_host() and tmio_mmc_host_alloc()
From: Greg Kroah-Hartman @ 2016-11-13 10:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK7LNAThxsE3QW4EdPUyxmxbnt_PPjeogi8Fox5AHkddsuu-Sg@mail.gmail.com>
On Fri, Nov 11, 2016 at 12:19:05PM +0900, Masahiro Yamada wrote:
> 2016-11-10 22:35 GMT+09:00 Greg Kroah-Hartman <gregkh@linuxfoundation.org>:
> > On Thu, Nov 10, 2016 at 10:24:21PM +0900, Masahiro Yamada wrote:
> >>
> >> sdhci_alloc_host() returns an error pointer when it fails.
> >> but mmc_alloc_host() cannot.
> >>
> >> This series allow to propagate a proper error code
> >> when host-allocation fails.
> >
> > Why? What can we really do about the error except give up? Why does
> > having a explicit error value make any difference to the caller, they
> > can't do anything different, right?
>
>
> The error code is shown in the console, like
>
> probe of 5a000000.sdhc failed with error -12
>
>
> The proper error code will give a clue why the driver failed to probe.
Can't the mmc core show the reason once, and not require each and every
individual driver to show/say the same thing? All a driver needs to
know is if it worked or didn't work. Every time it didn't work, it
needs to unwind stuff and then recover properly.
The drivers do not do different things based on what type of error
happened, as they don't care at all.
So I strongly suggest leaving it simple, as it is today, as this makes
drivers simpler, they don't have to duplicate the same type of error
reporting all over the place, and it's easy to audit for.
It also makes it so that large patchsets that touch every driver like
this are not needed at all.
> > I suggest just leaving it as-is, it's simple, and you don't have to mess
> > with PTR_ERR() anywhere.
>
>
> Why?
>
> Most of driver just give up probing for any error,
> but we still do ERR_PTR()/PTR_ERR() here and there.
> I think this patch is the same pattern.
I think we need to get rid of more of the ERR_PTR() stuff, as again,
it's useless. All we need to know is an error happened, that's it.
> If a function returns NULL on failure, we need to think about
> "what is the most common failure case".
>
> Currently, MMC drivers assume -ENOMEM is the best
> fit for mmc_alloc_host(), but the assumption is fragile.
>
> Already, mmc_alloc_host() calls a function
> that returns not only -ENOMEM, but also -ENOSPC.
>
> In the future, some other failure cases might be
> added to mmc_alloc_host().
>
> Once we decide the API returns an error pointer,
> drivers just propagate the return value from the API.
> This is much more stable implementation.
Again, no, it makes more work for the different drivers, duplicates code
all over the place, and really doesn't help any user, or developer, out
at all.
Just have the mmc core properly log what went wrong, and all should be
fine.
Again, keep it simple, that's the best policy for the kernel, and
really, most software :)
thanks,
greg k-h
^ permalink raw reply
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