* [PATCH 14/20] arm/bL_switcher: Convert to hotplug state machine
From: Sebastian Andrzej Siewior @ 2016-11-17 18:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117183541.8588-1-bigeasy@linutronix.de>
Install the callbacks via the state machine.
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
arch/arm/common/bL_switcher.c | 34 ++++++++++++++++++++--------------
include/linux/cpuhotplug.h | 1 +
2 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/arch/arm/common/bL_switcher.c b/arch/arm/common/bL_switcher.c
index 37dc0fe1093f..46730017b3c5 100644
--- a/arch/arm/common/bL_switcher.c
+++ b/arch/arm/common/bL_switcher.c
@@ -757,19 +757,18 @@ EXPORT_SYMBOL_GPL(bL_switcher_put_enabled);
* while the switcher is active.
* We're just not ready to deal with that given the trickery involved.
*/
-static int bL_switcher_hotplug_callback(struct notifier_block *nfb,
- unsigned long action, void *hcpu)
+static int bL_switcher_cpu_pre(unsigned int cpu)
{
- if (bL_switcher_active) {
- int pairing = bL_switcher_cpu_pairing[(unsigned long)hcpu];
- switch (action & 0xf) {
- case CPU_UP_PREPARE:
- case CPU_DOWN_PREPARE:
- if (pairing == -1)
- return NOTIFY_BAD;
- }
- }
- return NOTIFY_DONE;
+ int pairing;
+
+ if (!bL_switcher_active)
+ return 0;
+
+ pairing = bL_switcher_cpu_pairing[cpu];
+
+ if (pairing == -1)
+ return -EINVAL;
+ return 0;
}
static bool no_bL_switcher;
@@ -782,8 +781,15 @@ static int __init bL_switcher_init(void)
if (!mcpm_is_available())
return -ENODEV;
- cpu_notifier(bL_switcher_hotplug_callback, 0);
-
+ cpuhp_setup_state_nocalls(CPUHP_ARM_BL_PREPARE, "arm/bl:prepare",
+ bL_switcher_cpu_pre, NULL);
+ ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "arm/bl:predown",
+ NULL, bL_switcher_cpu_pre);
+ if (ret < 0) {
+ cpuhp_remove_state_nocalls(CPUHP_ARM_BL_PREPARE);
+ pr_err("bL_switcher: Failed to allocate a hotplug state\n");
+ return ret;
+ }
if (!no_bL_switcher) {
ret = bL_switcher_enable();
if (ret)
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 69abf2c09f6c..4b99b79c16e5 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -64,6 +64,7 @@ enum cpuhp_state {
CPUHP_X86_CPUID_PREPARE,
CPUHP_X86_MSR_PREPARE,
CPUHP_NET_IUCV_PREPARE,
+ CPUHP_ARM_BL_PREPARE,
CPUHP_TIMERS_DEAD,
CPUHP_NOTF_ERR_INJ_PREPARE,
CPUHP_MIPS_SOC_PREPARE,
--
2.10.2
^ permalink raw reply related
* [PATCH 07/20] pci/xgene-msi: Convert to hotplug state machine
From: Sebastian Andrzej Siewior @ 2016-11-17 18:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117183541.8588-1-bigeasy@linutronix.de>
Install the callbacks via the state machine and let the core invoke
the callbacks on the already online CPUs.
Cc: Duc Dang <dhdang@apm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
drivers/pci/host/pci-xgene-msi.c | 69 +++++++++++-----------------------------
include/linux/cpuhotplug.h | 1 +
2 files changed, 20 insertions(+), 50 deletions(-)
diff --git a/drivers/pci/host/pci-xgene-msi.c b/drivers/pci/host/pci-xgene-msi.c
index a6456b578269..1f38d0836751 100644
--- a/drivers/pci/host/pci-xgene-msi.c
+++ b/drivers/pci/host/pci-xgene-msi.c
@@ -360,16 +360,16 @@ static void xgene_msi_isr(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
+static enum cpuhp_state pci_xgene_online;
+
static int xgene_msi_remove(struct platform_device *pdev)
{
- int virq, i;
struct xgene_msi *msi = platform_get_drvdata(pdev);
- for (i = 0; i < NR_HW_IRQS; i++) {
- virq = msi->msi_groups[i].gic_irq;
- if (virq != 0)
- irq_set_chained_handler_and_data(virq, NULL, NULL);
- }
+ if (pci_xgene_online)
+ cpuhp_remove_state(pci_xgene_online);
+ cpuhp_remove_state(CPUHP_PCI_XGENE_DEAD);
+
kfree(msi->msi_groups);
kfree(msi->bitmap);
@@ -427,7 +427,7 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu)
return 0;
}
-static void xgene_msi_hwirq_free(unsigned int cpu)
+static int xgene_msi_hwirq_free(unsigned int cpu)
{
struct xgene_msi *msi = &xgene_msi_ctrl;
struct xgene_msi_group *msi_group;
@@ -441,33 +441,9 @@ static void xgene_msi_hwirq_free(unsigned int cpu)
irq_set_chained_handler_and_data(msi_group->gic_irq, NULL,
NULL);
}
+ return 0;
}
-static int xgene_msi_cpu_callback(struct notifier_block *nfb,
- unsigned long action, void *hcpu)
-{
- unsigned cpu = (unsigned long)hcpu;
-
- switch (action) {
- case CPU_ONLINE:
- case CPU_ONLINE_FROZEN:
- xgene_msi_hwirq_alloc(cpu);
- break;
- case CPU_DEAD:
- case CPU_DEAD_FROZEN:
- xgene_msi_hwirq_free(cpu);
- break;
- default:
- break;
- }
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block xgene_msi_cpu_notifier = {
- .notifier_call = xgene_msi_cpu_callback,
-};
-
static const struct of_device_id xgene_msi_match_table[] = {
{.compatible = "apm,xgene1-msi"},
{},
@@ -478,7 +454,6 @@ static int xgene_msi_probe(struct platform_device *pdev)
struct resource *res;
int rc, irq_index;
struct xgene_msi *xgene_msi;
- unsigned int cpu;
int virt_msir;
u32 msi_val, msi_idx;
@@ -540,28 +515,22 @@ static int xgene_msi_probe(struct platform_device *pdev)
}
}
- cpu_notifier_register_begin();
-
- for_each_online_cpu(cpu)
- if (xgene_msi_hwirq_alloc(cpu)) {
- dev_err(&pdev->dev, "failed to register MSI handlers\n");
- cpu_notifier_register_done();
- goto error;
- }
-
- rc = __register_hotcpu_notifier(&xgene_msi_cpu_notifier);
- if (rc) {
- dev_err(&pdev->dev, "failed to add CPU MSI notifier\n");
- cpu_notifier_register_done();
- goto error;
- }
-
- cpu_notifier_register_done();
+ rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online",
+ xgene_msi_hwirq_alloc, NULL);
+ if (rc)
+ goto err_cpuhp;
+ pci_xgene_online = rc;
+ rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL,
+ xgene_msi_hwirq_free);
+ if (rc)
+ goto err_cpuhp;
dev_info(&pdev->dev, "APM X-Gene PCIe MSI driver loaded\n");
return 0;
+err_cpuhp:
+ dev_err(&pdev->dev, "failed to add CPU MSI notifier\n");
error:
xgene_msi_remove(pdev);
return rc;
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 6506dce8343a..fd5598b8353a 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -38,6 +38,7 @@ enum cpuhp_state {
CPUHP_RADIX_DEAD,
CPUHP_PAGE_ALLOC_DEAD,
CPUHP_NET_DEV_DEAD,
+ CPUHP_PCI_XGENE_DEAD,
CPUHP_WORKQUEUE_PREP,
CPUHP_POWER_NUMA_PREPARE,
CPUHP_HRTIMERS_PREPARE,
--
2.10.2
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: sun5i: Add touchscreen node to reference-design-tablet.dtsi
From: Maxime Ripard @ 2016-11-17 18:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0c3a9e9c-d310-c6c3-ae10-1ae9e520963e@redhat.com>
Hi Hans,
On Tue, Nov 15, 2016 at 11:12:35AM +0100, Hans de Goede wrote:
> Hi,
>
> On 14-11-16 21:08, Maxime Ripard wrote:
> > Hi,
> >
> > On Sun, Nov 13, 2016 at 08:22:02PM +0100, Hans de Goede wrote:
> > > Just like on sun8i all sun5i tablets use the same interrupt and power
> > > gpios for their touchscreens. I've checked all known a13 fex files and
> > > only the UTOO P66 uses a different gpio for the interrupt.
> > >
> > > Add a touchscreen node to sun5i-reference-design-tablet.dtsi, which
> > > fills in the necessary gpios to avoid duplication in the tablet dts files,
> > > just like we do in sun8i-reference-design-tablet.dtsi.
> > >
> > > This will make future patches adding touchscreen nodes to a13 tablets
> > > simpler.
> > >
> > > Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> > > ---
> > > arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 38 ++++++++--------------
> > > .../boot/dts/sun5i-reference-design-tablet.dtsi | 25 ++++++++++++++
> > > 2 files changed, 39 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
> > > index a8b0bcc..3d7ff10 100644
> > > --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
> > > +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
> > > @@ -83,22 +83,6 @@
> > > allwinner,pins = "PG3";
> > > };
> > >
> > > -&i2c1 {
> > > - icn8318: touchscreen at 40 {
> > > - compatible = "chipone,icn8318";
> > > - reg = <0x40>;
> > > - interrupt-parent = <&pio>;
> > > - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
> > > - pinctrl-names = "default";
> > > - pinctrl-0 = <&ts_wake_pin_p66>;
> > > - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
> > > - touchscreen-size-x = <800>;
> > > - touchscreen-size-y = <480>;
> > > - touchscreen-inverted-x;
> > > - touchscreen-swapped-x-y;
> > > - };
> > > -};
> > > -
> > > &mmc2 {
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&mmc2_pins_a>;
> > > @@ -121,20 +105,26 @@
> > > allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> > > allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> > > };
> > > -
> > > - ts_wake_pin_p66: ts_wake_pin at 0 {
> > > - allwinner,pins = "PB3";
> > > - allwinner,function = "gpio_out";
> > > - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> > > - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> > > - };
> > > -
> > > };
> > >
> > > ®_usb0_vbus {
> > > gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
> > > };
> > >
> > > +&touchscreen {
> > > + compatible = "chipone,icn8318";
> > > + reg = <0x40>;
> > > + /* The P66 uses a different EINT then the reference design */
> > > + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
> > > + /* The icn8318 binding expects wake-gpios instead of power-gpios */
> > > + wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
> > > + touchscreen-size-x = <800>;
> > > + touchscreen-size-y = <480>;
> > > + touchscreen-inverted-x;
> > > + touchscreen-swapped-x-y;
> > > + status = "okay";
> > > +};
> > > +
> > > &uart1 {
> > > /* The P66 uses the uart pins as gpios */
> > > status = "disabled";
> > > diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
> > > index 20cc940..7af488a 100644
> > > --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
> > > +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
> > > @@ -41,6 +41,7 @@
> > > */
> > > #include "sunxi-reference-design-tablet.dtsi"
> > >
> > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > #include <dt-bindings/pwm/pwm.h>
> > >
> > > / {
> > > @@ -84,6 +85,23 @@
> > > };
> > >
> > > &i2c1 {
> > > + /*
> > > + * The gsl1680 is rated at 400KHz and it will not work reliable at
> > > + * 100KHz, this has been confirmed on multiple different q8 tablets.
> > > + * All other devices on this bus are also rated for 400KHz.
> > > + */
> > > + clock-frequency = <400000>;
> > > +
> > > + touchscreen: touchscreen {
> > > + interrupt-parent = <&pio>;
> > > + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&ts_power_pin>;
> > > + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
> > > + /* Tablet dts must provide reg and compatible */
> > > + status = "disabled";
> > > + };
> > > +
> > > pcf8563: rtc at 51 {
> > > compatible = "nxp,pcf8563";
> > > reg = <0x51>;
> > > @@ -125,6 +143,13 @@
> > > allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> > > };
> > >
> > > + ts_power_pin: ts_power_pin {
> > > + allwinner,pins = "PB3";
> > > + allwinner,function = "gpio_out";
> > > + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> > > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> > > + };
> > > +
> >
> > For the next release, we'll switch to the generic pin mux properties
> > ("pins" and "function"), and we actually implemented the fact that the
> > drive and pull properties are optional, so you can drop them both.
> >
> > You'll need next + http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/467123.html
>
> Ok, before I send a v2 first a question about this, for the touchscreen
> case I actually need:
>
> allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>
> Because otherwise when the touchscreen controller is powered by a separate
> regulator and that regulator is off, then it may draw just enough current
> from its enable pin to be sort-of listening to the i2c bus and mess up
> that bus.
>
> So is this the default, or do we get the power-on default when not
> specifying these? If it is the power-on default then we do need to
> specify these, because AFAICT the power-on drive strength typically
> is 20 mA.
Leaving them out will keep whatever state has been programmed. Putting
them in the DT will force them to whatever value has been set.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH fpga 4/9] fpga zynq: Check for errors after completing DMA
From: Jason Gunthorpe @ 2016-11-17 18:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAAtXAHeGJjQ22d=OP6cEt8Ssg1bhAEVQ5_GWFFd26xp-j8EUFg@mail.gmail.com>
On Wed, Nov 16, 2016 at 10:10:35PM -0800, Moritz Fischer wrote:
> > /* FPGA programmed */
> > #define IXR_PCFG_DONE_MASK BIT(2)
> > -#define IXR_ERROR_FLAGS_MASK 0x00F0F860
> > +#define IXR_ERROR_FLAGS_MASK 0x00F0C860
>
> True. Ouch.
Yeah, this only works at all by accident..
> > -static void zynq_fpga_mask_irqs(struct zynq_fpga_priv *priv)
> > +static inline void zynq_fpga_set_irq_mask(struct zynq_fpga_priv *priv,
> > + u32 enable)
> > {
> > - u32 intr_mask;
> > -
> > - intr_mask = zynq_fpga_read(priv, INT_MASK_OFFSET);
> > - zynq_fpga_write(priv, INT_MASK_OFFSET,
> > - intr_mask | IXR_DMA_DONE_MASK | IXR_ERROR_FLAGS_MASK);
> > -}
> > + zynq_fpga_write(priv, INT_MASK_OFFSET, ~enable);
>
> Not a fan of this ~enable here. Function name indicates you're doing
> the opposite
Lets call it zynq_fpga_set_irq then
The ~ is best placed here because it is after the compiler has coerced
the argument into u32 so the ~ will always do the right
thing
I've been reading the IXR_*_MASK as indicating it is a bit pattern for
the INT_MASK register not as actually meaning literal masking.
> > +out_clk:
> > clk_disable(priv->clk);
> > -
>
> Personally found it more readable with newline.
sure
Jason
^ permalink raw reply
* System/uncore PMUs and unit aggregation
From: Will Deacon @ 2016-11-17 18:17 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
We currently have support for three arm64 system PMUs in flight:
[Cavium ThunderX] http://lkml.kernel.org/r/cover.1477741719.git.jglauber at cavium.com
[Hisilicon Hip0x] http://lkml.kernel.org/r/1478151727-20250-1-git-send-email-anurup.m at huawei.com
[Qualcomm L2] http://lkml.kernel.org/r/1477687813-11412-1-git-send-email-nleeder at codeaurora.org
Each of which have to deal with multiple underlying hardware units in one
way or another. Mark and I recently expressed a desire to expose these
units to userspace as individual PMU instances, since this can allow:
* Fine-grained control of events from userspace, when you want to see
individual numbers as opposed to a summed total
* Potentially ease migration to new SoC revisions, where the units
are laid out slightly differently
* Easier handling of cases where the units aren't quite identical
however, this received pushback from all of the patch authors, so there's
clearly a problem with this approach. I'm hoping we can try to resolve
this here.
Speaking to Mark earlier today, we came up with the following rough rules
for drivers that present multiple hardware units as a single PMU:
1. If the units share some part of the programming interface (e.g. control
registers or interrupts), then they must be handled by the same PMU.
Otherwise, they should be treated independently as separate PMU
instances.
2. If the units are handled by the same PMU, then care must be taken to
handle event groups correctly. That is, if the units cannot be started
and stopped atomically, cross-unit groups must be rejected by the
driver. Furthermore, any cross-unit scheduling constraints must be
honoured so that all the units targetted by a group can schedule the
group concurrently.
3. Summing the counters across units is only permitted if the units
can all be started and stopped atomically. Otherwise, the counters
should be exposed individually. It's up to the driver author to
decide what makes sense to sum.
4. Unit topology can optionally be described in sysfs (we should pick
some standard directory naming here), and then events targetting
specific units can have the unit identifier extracted from the topology
encoded in some configN fields.
The million dollar question is: how does that fit in with the drivers I
mentioned at the top? Is this overly restrictive, or have we missed stuff?
We certainly want to allow flexibility in the way in which the drivers
talk to the hardware, but given that these decisions directly affect the
user ABI, some consistent ground rules are required.
For Cavium ThunderX, it's not clear whether or not the individual units
could be expressed as separate PMUs, or whether they're caught by one of
the rules above. The Qualcomm L2 looks like it's doing the right thing
and we can't quite work out what the Hisilicon Hip0x topology looks like,
since the interaction with djtag is confusing.
If the driver authors (on To:) could shed some light on this, then that
would be much appreciated!
Thanks,
Will
^ permalink raw reply
* [PATCH v4 1/5] arm64: perf: Basic uncore counter support for Cavium ThunderX SOC
From: Will Deacon @ 2016-11-17 18:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111103029.GD16907@hardcore>
On Fri, Nov 11, 2016 at 11:30:29AM +0100, Jan Glauber wrote:
> On Tue, Nov 08, 2016 at 11:50:10PM +0000, Will Deacon wrote:
> > On Sat, Oct 29, 2016 at 01:55:29PM +0200, Jan Glauber wrote:
> > > +/* node attribute depending on number of NUMA nodes */
> > > +static ssize_t node_show(struct device *dev, struct device_attribute *attr,
> > > + char *page)
> > > +{
> > > + if (NODES_SHIFT)
> > > + return sprintf(page, "config:16-%d\n", 16 + NODES_SHIFT - 1);
> >
> > If NODES_SHIFT is 1, you'll end up with "config:16-16", which might confuse
> > userspace.
>
> So should I use "config:16" in that case? Is it OK to use this also for
> NODES_SHIFT=0 ?
If you only need one bit, then "config:16" is the right thing to do.
Will
^ permalink raw reply
* [PATCH v27 1/9] memblock: add memblock_cap_memory_range()
From: James Morse @ 2016-11-17 18:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117111917.GA22855@arm.com>
Hi Will, Akashi,
On 17/11/16 11:19, Will Deacon wrote:
> It looks much better, thanks! Just one question below.
>
> On Thu, Nov 17, 2016 at 02:34:24PM +0900, AKASHI Takahiro wrote:
>> diff --git a/mm/memblock.c b/mm/memblock.c
>> index 7608bc3..fea1688 100644
>> --- a/mm/memblock.c
>> +++ b/mm/memblock.c
>> @@ -1514,11 +1514,37 @@ void __init memblock_enforce_memory_limit(phys_addr_t limit)
>> (phys_addr_t)ULLONG_MAX);
>> }
>>
>> +void __init memblock_cap_memory_range(phys_addr_t base, phys_addr_t size)
>> +{
>> + int start_rgn, end_rgn;
>> + int i, ret;
>> +
>> + if (!size)
>> + return;
>> +
>> + ret = memblock_isolate_range(&memblock.memory, base, size,
>> + &start_rgn, &end_rgn);
>> + if (ret)
>> + return;
>> +
>> + /* remove all the MAP regions */
>> + for (i = memblock.memory.cnt - 1; i >= end_rgn; i--)
>> + if (!memblock_is_nomap(&memblock.memory.regions[i]))
>> + memblock_remove_region(&memblock.memory, i);
>
> In the case that we have only one, giant memblock that covers base all
> of base + size, can't we end up with start_rgn = end_rgn = 0? In which
Can this happen? If we only have one memblock that exactly spans
base:(base+size), memblock_isolate_range() will hit the '@rgn is fully
contained, record it' code and set start_rgn=0,end_rgn=1. (rbase==base,
rend==end). We only go round the loop once.
If we only have one memblock that is bigger than base:(base+size) we end up with
three regions, start_rgn=1,end_rgn=2. The trickery here is the '@rgn intersects
from above' code decreases the loop counter so we process the same entry twice,
hitting '@rgn is fully contained, record it' the second time round... so we go
round the loop four times.
I can't see how we hit the:
> if (rbase >= end)
> break;
> if (rend <= base)
> continue;
code in either case...
Thanks,
James
> case, we'd end up accidentally removing the map regions here.
>
> The existing code:
>
>> - /* remove all the MAP regions above the limit */
>> - for (i = end_rgn - 1; i >= start_rgn; i--) {
>> - if (!memblock_is_nomap(&type->regions[i]))
>> - memblock_remove_region(type, i);
>> - }
>
> seems to handle this.
^ permalink raw reply
* [PATCH net 1/3] net: phy: realtek: add eee advertisement disable options
From: Anand Moon @ 2016-11-17 18:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479378055.17538.57.camel@baylibre.com>
Hi Jerone,
On 17 November 2016 at 15:50, Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Wed, 2016-11-16 at 22:36 +0530, Anand Moon wrote:
>> Hi Jerome.
>>
>> On 15 November 2016 at 19:59, Jerome Brunet <jbrunet@baylibre.com>
>> wrote:
>> >
>> > On some platforms, energy efficient ethernet with rtl8211 devices
>> > is
>> > causing issue, like throughput drop or broken link.
>> >
>> > This was reported on the OdroidC2 (DWMAC + RTL8211F). While the
>> > issue root
>> > cause is not fully understood yet, disabling EEE advertisement
>> > prevent auto
>> > negotiation from enabling EEE.
>> >
>> > This patch provides options to disable 1000T and 100TX EEE
>> > advertisement
>> > individually for the realtek phys supporting this feature.
>> >
>> > Reported-by: Martin Blumenstingl <martin.blumenstingl@googlemail.co
>> > m>
>> > Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
>> > Cc: Alexandre TORGUE <alexandre.torgue@st.com>
>> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
>> > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> > Tested-by: Andre Roth <neolynx@gmail.com>
>> > ---
>> > drivers/net/phy/realtek.c | 65
>> > ++++++++++++++++++++++++++++++++++++++++++++++-
>> > 1 file changed, 64 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
>> > index aadd6e9f54ad..77235fd5faaf 100644
>> > --- a/drivers/net/phy/realtek.c
>> > +++ b/drivers/net/phy/realtek.c
>> > @@ -15,6 +15,12 @@
>> > */
>> > #include <linux/phy.h>
>> > #include <linux/module.h>
>> > +#include <linux/of.h>
>> > +
>> > +struct rtl8211x_phy_priv {
>> > + bool eee_1000t_disable;
>> > + bool eee_100tx_disable;
>> > +};
>> >
>> > #define RTL821x_PHYSR 0x11
>> > #define RTL821x_PHYSR_DUPLEX 0x2000
>> > @@ -93,12 +99,44 @@ static int rtl8211f_config_intr(struct
>> > phy_device *phydev)
>> > return err;
>> > }
>> >
>> > +static void rtl8211x_clear_eee_adv(struct phy_device *phydev)
>> > +{
>> > + struct rtl8211x_phy_priv *priv = phydev->priv;
>> > + u16 val;
>> > +
>> > + if (priv->eee_1000t_disable || priv->eee_100tx_disable) {
>> > + val = phy_read_mmd_indirect(phydev,
>> > MDIO_AN_EEE_ADV,
>> > + MDIO_MMD_AN);
>> > +
>> > + if (priv->eee_1000t_disable)
>> > + val &= ~MDIO_AN_EEE_ADV_1000T;
>> > + if (priv->eee_100tx_disable)
>> > + val &= ~MDIO_AN_EEE_ADV_100TX;
>> > +
>> > + phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
>> > + MDIO_MMD_AN, val);
>> > + }
>> > +}
>> > +
>> > +static int rtl8211x_config_init(struct phy_device *phydev)
>> > +{
>> > + int ret;
>> > +
>> > + ret = genphy_config_init(phydev);
>> > + if (ret < 0)
>> > + return ret;
>> > +
>> > + rtl8211x_clear_eee_adv(phydev);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > static int rtl8211f_config_init(struct phy_device *phydev)
>> > {
>> > int ret;
>> > u16 reg;
>> >
>> > - ret = genphy_config_init(phydev);
>> > + ret = rtl8211x_config_init(phydev);
>> > if (ret < 0)
>> > return ret;
>> >
>> > @@ -115,6 +153,26 @@ static int rtl8211f_config_init(struct
>> > phy_device *phydev)
>> > return 0;
>> > }
>> >
>> > +static int rtl8211x_phy_probe(struct phy_device *phydev)
>> > +{
>> > + struct device *dev = &phydev->mdio.dev;
>> > + struct device_node *of_node = dev->of_node;
>> > + struct rtl8211x_phy_priv *priv;
>> > +
>> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> > + if (!priv)
>> > + return -ENOMEM;
>> > +
>> > + priv->eee_1000t_disable =
>> > + of_property_read_bool(of_node, "realtek,disable-
>> > eee-1000t");
>> > + priv->eee_100tx_disable =
>> > + of_property_read_bool(of_node, "realtek,disable-
>> > eee-100tx");
>> > +
>> > + phydev->priv = priv;
>> > +
>> > + return 0;
>> > +}
>> > +
>> > static struct phy_driver realtek_drvs[] = {
>> > {
>> > .phy_id = 0x00008201,
>> > @@ -140,7 +198,9 @@ static struct phy_driver realtek_drvs[] = {
>> > .phy_id_mask = 0x001fffff,
>> > .features = PHY_GBIT_FEATURES,
>> > .flags = PHY_HAS_INTERRUPT,
>> > + .probe = &rtl8211x_phy_probe,
>> > .config_aneg = genphy_config_aneg,
>> > + .config_init = &rtl8211x_config_init,
>> > .read_status = genphy_read_status,
>> > .ack_interrupt = rtl821x_ack_interrupt,
>> > .config_intr = rtl8211e_config_intr,
>> > @@ -152,7 +212,9 @@ static struct phy_driver realtek_drvs[] = {
>> > .phy_id_mask = 0x001fffff,
>> > .features = PHY_GBIT_FEATURES,
>> > .flags = PHY_HAS_INTERRUPT,
>> > + .probe = &rtl8211x_phy_probe,
>> > .config_aneg = &genphy_config_aneg,
>> > + .config_init = &rtl8211x_config_init,
>> > .read_status = &genphy_read_status,
>> > .ack_interrupt = &rtl821x_ack_interrupt,
>> > .config_intr = &rtl8211e_config_intr,
>> > @@ -164,6 +226,7 @@ static struct phy_driver realtek_drvs[] = {
>> > .phy_id_mask = 0x001fffff,
>> > .features = PHY_GBIT_FEATURES,
>> > .flags = PHY_HAS_INTERRUPT,
>> > + .probe = &rtl8211x_phy_probe,
>> > .config_aneg = &genphy_config_aneg,
>> > .config_init = &rtl8211f_config_init,
>> > .read_status = &genphy_read_status,
>> > --
>> > 2.7.4
>> >
>>
>> How about adding callback functionality for .soft_reset to handle
>> BMCR
>> where we update the Auto-Negotiation for the phy,
>> as per the datasheet of the rtl8211f.
>
> I'm not sure I understand how this would help with our issue (and EEE).
> Am I missing something or is it something unrelated that you would like
> to see happening on this driver ?
>
[snip]
I was just tying other phy module to understand the feature.
But in order to improve the throughput I tried to integrate blow u-boot commit.
commit 3d6af748ebd831524cb22a29433e9092af469ec7
Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Date: Thu Mar 12 18:54:59 2015 +0800
net/phy: Add support for realtek RTL8211F
RTL8211F has different registers from RTL8211E.
This patch adds support for RTL8211F PHY which
can be found on Freescale's T1023 RDB board.
And added the similar functionality to .config_aneg = &rtl8211f_config_aneg,
And I seem to have better results in through put with periodic drop
but it recovers.
-----
odroid at odroid64:~$ iperf3 -c 10.0.0.102 -p 2006 -i 1 -t 100 -V
iperf 3.0.11
Linux odroid64 4.9.0-rc5-xc2ml #18 SMP PREEMPT Thu Nov 17 22:56:00 IST
2016 aarch64 aarch64 aarch64 GNU/Linux
Time: Thu, 17 Nov 2016 17:35:25 GMT
Connecting to host 10.0.0.102, port 2006
Cookie: odroid64.1479404125.404729.3b45146e7
TCP MSS: 1448 (default)
[ 4] local 10.0.0.105 port 40238 connected to 10.0.0.102 port 2006
Starting Test: protocol: TCP, 1 streams, 131072 byte blocks, omitting
0 seconds, 100 second test
[ ID] Interval Transfer Bandwidth Retr Cwnd
[ 4] 0.00-1.00 sec 114 MBytes 952 Mbits/sec 0 368 KBytes
[ 4] 1.00-2.00 sec 112 MBytes 937 Mbits/sec 0 368 KBytes
[ 4] 2.00-3.00 sec 111 MBytes 935 Mbits/sec 0 368 KBytes
[ 4] 3.00-4.00 sec 112 MBytes 936 Mbits/sec 0 368 KBytes
[ 4] 4.00-5.00 sec 112 MBytes 939 Mbits/sec 0 368 KBytes
[ 4] 5.00-6.00 sec 112 MBytes 936 Mbits/sec 0 368 KBytes
[ 4] 6.00-7.00 sec 111 MBytes 933 Mbits/sec 0 368 KBytes
[ 4] 7.00-8.00 sec 112 MBytes 942 Mbits/sec 0 368 KBytes
[ 4] 8.00-9.00 sec 111 MBytes 935 Mbits/sec 0 368 KBytes
[ 4] 9.00-10.00 sec 111 MBytes 932 Mbits/sec 0 368 KBytes
[ 4] 10.00-11.00 sec 112 MBytes 937 Mbits/sec 0 368 KBytes
[ 4] 11.00-12.00 sec 111 MBytes 935 Mbits/sec 0 368 KBytes
[ 4] 12.00-13.00 sec 112 MBytes 938 Mbits/sec 0 368 KBytes
[ 4] 13.00-14.00 sec 112 MBytes 940 Mbits/sec 0 368 KBytes
[ 4] 14.00-15.00 sec 111 MBytes 934 Mbits/sec 0 368 KBytes
[ 4] 15.00-16.00 sec 111 MBytes 935 Mbits/sec 0 368 KBytes
[ 4] 16.00-17.00 sec 112 MBytes 939 Mbits/sec 0 368 KBytes
[ 4] 17.00-18.00 sec 112 MBytes 936 Mbits/sec 0 368 KBytes
[ 4] 18.00-19.00 sec 111 MBytes 934 Mbits/sec 0 368 KBytes
[ 4] 19.00-20.00 sec 112 MBytes 940 Mbits/sec 0 368 KBytes
[ 4] 20.00-21.00 sec 111 MBytes 933 Mbits/sec 0 368 KBytes
[ 4] 21.00-22.00 sec 112 MBytes 941 Mbits/sec 0 368 KBytes
[ 4] 22.00-23.00 sec 111 MBytes 931 Mbits/sec 0 368 KBytes
[ 4] 23.00-24.00 sec 112 MBytes 938 Mbits/sec 0 368 KBytes
[ 4] 24.00-25.00 sec 112 MBytes 938 Mbits/sec 0 368 KBytes
[ 4] 25.00-26.00 sec 111 MBytes 934 Mbits/sec 0 368 KBytes
[ 4] 26.00-27.00 sec 112 MBytes 940 Mbits/sec 0 368 KBytes
[ 4] 27.00-28.00 sec 112 MBytes 936 Mbits/sec 0 368 KBytes
[ 4] 28.00-29.00 sec 111 MBytes 934 Mbits/sec 0 368 KBytes
[ 4] 29.00-30.00 sec 112 MBytes 937 Mbits/sec 0 368 KBytes
[ 4] 30.00-31.00 sec 111 MBytes 934 Mbits/sec 0 368 KBytes
[ 4] 31.00-32.00 sec 112 MBytes 942 Mbits/sec 0 368 KBytes
[ 4] 32.00-33.00 sec 111 MBytes 933 Mbits/sec 0 368 KBytes
[ 4] 33.00-34.00 sec 111 MBytes 935 Mbits/sec 0 368 KBytes
[ 4] 34.00-35.00 sec 112 MBytes 941 Mbits/sec 0 368 KBytes
[ 4] 35.00-36.00 sec 107 MBytes 896 Mbits/sec 0 368 KBytes
[ 4] 36.00-37.00 sec 0.00 Bytes 0.00 bits/sec 2 1.41 KBytes
[ 4] 37.00-38.00 sec 0.00 Bytes 0.00 bits/sec 1 1.41 KBytes
[ 4] 38.00-39.00 sec 0.00 Bytes 0.00 bits/sec 0 1.41 KBytes
[ 4] 39.00-40.00 sec 38.0 MBytes 319 Mbits/sec 1 385 KBytes
[ 4] 40.00-41.00 sec 112 MBytes 939 Mbits/sec 0 385 KBytes
[ 4] 41.00-42.00 sec 112 MBytes 939 Mbits/sec 0 385 KBytes
[ 4] 42.00-43.00 sec 112 MBytes 937 Mbits/sec 0 385 KBytes
[ 4] 43.00-44.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 44.00-45.00 sec 112 MBytes 939 Mbits/sec 0 385 KBytes
[ 4] 45.00-46.00 sec 112 MBytes 939 Mbits/sec 0 385 KBytes
[ 4] 46.00-47.00 sec 111 MBytes 931 Mbits/sec 0 385 KBytes
[ 4] 47.00-48.00 sec 112 MBytes 936 Mbits/sec 0 385 KBytes
[ 4] 48.00-49.00 sec 112 MBytes 939 Mbits/sec 0 385 KBytes
[ 4] 49.00-50.00 sec 112 MBytes 936 Mbits/sec 0 385 KBytes
[ 4] 50.00-51.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 51.00-52.00 sec 111 MBytes 934 Mbits/sec 0 385 KBytes
[ 4] 52.00-53.00 sec 112 MBytes 941 Mbits/sec 0 385 KBytes
[ 4] 53.00-54.00 sec 112 MBytes 937 Mbits/sec 0 385 KBytes
[ 4] 54.00-55.00 sec 111 MBytes 930 Mbits/sec 0 385 KBytes
[ 4] 55.00-56.00 sec 112 MBytes 941 Mbits/sec 0 385 KBytes
[ 4] 56.00-57.00 sec 112 MBytes 936 Mbits/sec 0 385 KBytes
[ 4] 57.00-58.00 sec 111 MBytes 933 Mbits/sec 0 385 KBytes
[ 4] 58.00-59.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 59.00-60.00 sec 112 MBytes 940 Mbits/sec 0 385 KBytes
[ 4] 60.00-61.00 sec 112 MBytes 936 Mbits/sec 0 385 KBytes
[ 4] 61.00-62.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 62.00-63.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 63.00-64.00 sec 112 MBytes 938 Mbits/sec 0 385 KBytes
[ 4] 64.00-65.00 sec 111 MBytes 932 Mbits/sec 0 385 KBytes
[ 4] 65.00-66.00 sec 112 MBytes 940 Mbits/sec 0 385 KBytes
[ 4] 66.00-67.00 sec 112 MBytes 938 Mbits/sec 0 385 KBytes
[ 4] 67.00-68.00 sec 111 MBytes 934 Mbits/sec 0 385 KBytes
[ 4] 68.00-69.00 sec 111 MBytes 933 Mbits/sec 0 385 KBytes
[ 4] 69.00-70.00 sec 112 MBytes 937 Mbits/sec 0 385 KBytes
[ 4] 70.00-71.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 71.00-72.00 sec 112 MBytes 941 Mbits/sec 0 385 KBytes
[ 4] 72.00-73.00 sec 111 MBytes 933 Mbits/sec 0 385 KBytes
[ 4] 73.00-74.00 sec 112 MBytes 939 Mbits/sec 0 385 KBytes
[ 4] 74.00-75.00 sec 111 MBytes 934 Mbits/sec 0 385 KBytes
[ 4] 75.00-76.00 sec 111 MBytes 934 Mbits/sec 0 385 KBytes
[ 4] 76.00-77.00 sec 112 MBytes 937 Mbits/sec 0 385 KBytes
[ 4] 77.00-78.00 sec 112 MBytes 938 Mbits/sec 0 385 KBytes
[ 4] 78.00-79.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 79.00-80.00 sec 111 MBytes 934 Mbits/sec 0 385 KBytes
[ 4] 80.00-81.00 sec 112 MBytes 939 Mbits/sec 0 385 KBytes
[ 4] 81.00-82.00 sec 112 MBytes 936 Mbits/sec 0 385 KBytes
[ 4] 82.00-83.00 sec 111 MBytes 934 Mbits/sec 0 385 KBytes
[ 4] 83.00-84.00 sec 112 MBytes 937 Mbits/sec 0 385 KBytes
[ 4] 84.00-85.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 85.00-86.00 sec 112 MBytes 937 Mbits/sec 0 385 KBytes
[ 4] 86.00-87.00 sec 112 MBytes 939 Mbits/sec 0 385 KBytes
[ 4] 87.00-88.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 88.00-89.00 sec 112 MBytes 937 Mbits/sec 0 385 KBytes
[ 4] 89.00-90.00 sec 112 MBytes 936 Mbits/sec 0 385 KBytes
[ 4] 90.00-91.00 sec 112 MBytes 937 Mbits/sec 0 385 KBytes
[ 4] 91.00-92.00 sec 111 MBytes 934 Mbits/sec 0 385 KBytes
[ 4] 92.00-93.00 sec 112 MBytes 939 Mbits/sec 0 385 KBytes
[ 4] 93.00-94.00 sec 111 MBytes 935 Mbits/sec 0 385 KBytes
[ 4] 94.00-95.00 sec 112 MBytes 936 Mbits/sec 0 385 KBytes
[ 4] 95.00-96.00 sec 112 MBytes 936 Mbits/sec 0 385 KBytes
[ 4] 96.00-97.00 sec 112 MBytes 936 Mbits/sec 0 385 KBytes
[ 4] 97.00-98.00 sec 113 MBytes 945 Mbits/sec 0 559 KBytes
[ 4] 98.00-99.00 sec 112 MBytes 937 Mbits/sec 0 559 KBytes
[ 4] 99.00-100.00 sec 111 MBytes 928 Mbits/sec 0 559 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
Test Complete. Summary Results:
[ ID] Interval Transfer Bandwidth Retr
[ 4] 0.00-100.00 sec 10.5 GBytes 902 Mbits/sec 4 sender
[ 4] 0.00-100.00 sec 10.5 GBytes 902 Mbits/sec receiver
CPU Utilization: local/sender 5.6% (0.2%u/5.4%s), remote/receiver
17.1% (1.2%u/15.9%s)
Can your confirm this at your end.
Once confirm I will try to send this as a fix for this issue.
-Best Regards
Anand Moon
^ permalink raw reply
* [PATCH fpga 5/9] fpga zynq: Remove priv->dev
From: Moritz Fischer @ 2016-11-17 18:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.10.1611140913280.3739@atull-VirtualBox>
Hi Jason,
On Mon, Nov 14, 2016 at 09:13:49AM -0600, atull wrote:
> On Wed, 9 Nov 2016, Jason Gunthorpe wrote:
>
> Hi Jason,
>
> Acked-by: Alan Tull <atull@opensource.altera.com>
>
> Alan
>
> > socfpga uses mgr->dev for debug prints, there should be consistency
> > here, so standardize on that. The only other use was for dma
> > which can be replaced with mgr->dev.parent.
> >
> > Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
For the priv->dev removal part.
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
> > ---
> > drivers/fpga/zynq-fpga.c | 22 ++++++++++------------
> > 1 file changed, 10 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> > index 3ffc5fcc3072..ac2deae92dbd 100644
> > --- a/drivers/fpga/zynq-fpga.c
> > +++ b/drivers/fpga/zynq-fpga.c
> > @@ -118,7 +118,6 @@
> > #define FPGA_RST_NONE_MASK 0x0
> >
> > struct zynq_fpga_priv {
> > - struct device *dev;
> > int irq;
> > struct clk *clk;
> >
> > @@ -188,7 +187,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> > * least the sync word and something else to do anything.
> > */
> > if (count <= 4 || (count % 4) != 0) {
> > - dev_err(priv->dev,
> > + dev_err(&mgr->dev,
> > "Invalid bitstream size, must be multiples of 4 bytes\n");
> > return -EINVAL;
> > }
> > @@ -200,7 +199,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> > /* don't globally reset PL if we're doing partial reconfig */
> > if (!(flags & FPGA_MGR_PARTIAL_RECONFIG)) {
> > if (!zynq_fpga_has_sync(buf, count)) {
> > - dev_err(priv->dev,
> > + dev_err(&mgr->dev,
> > "Invalid bitstream, could not find a sync word. Bitstream must be a byte swaped .bin file\n");
> > err = -EINVAL;
> > goto out_err;
> > @@ -233,7 +232,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> > INIT_POLL_DELAY,
> > INIT_POLL_TIMEOUT);
> > if (err) {
> > - dev_err(priv->dev, "Timeout waiting for PCFG_INIT\n");
> > + dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
> > goto out_err;
> > }
> >
> > @@ -247,7 +246,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> > INIT_POLL_DELAY,
> > INIT_POLL_TIMEOUT);
> > if (err) {
> > - dev_err(priv->dev, "Timeout waiting for !PCFG_INIT\n");
> > + dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");
> > goto out_err;
> > }
> >
> > @@ -261,7 +260,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> > INIT_POLL_DELAY,
> > INIT_POLL_TIMEOUT);
> > if (err) {
> > - dev_err(priv->dev, "Timeout waiting for PCFG_INIT\n");
> > + dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
> > goto out_err;
> > }
> > }
> > @@ -278,7 +277,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
> > /* check that we have room in the command queue */
> > status = zynq_fpga_read(priv, STATUS_OFFSET);
> > if (status & STATUS_DMA_Q_F) {
> > - dev_err(priv->dev, "DMA command queue full\n");
> > + dev_err(&mgr->dev, "DMA command queue full\n");
> > err = -EBUSY;
> > goto out_err;
> > }
> > @@ -309,7 +308,8 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr,
> >
> > priv = mgr->priv;
> >
> > - kbuf = dma_alloc_coherent(priv->dev, count, &dma_addr, GFP_KERNEL);
> > + kbuf =
> > + dma_alloc_coherent(mgr->dev.parent, count, &dma_addr, GFP_KERNEL);
> > if (!kbuf)
> > return -ENOMEM;
> >
> > @@ -356,7 +356,7 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr,
> > goto out_clk;
> >
> > out_report:
> > - dev_err(priv->dev,
> > + dev_err(&mgr->dev,
> > "%s: INT_STS:0x%x CTRL:0x%x LOCK:0x%x INT_MASK:0x%x STATUS:0x%x MCTRL:0x%x\n",
> > why,
> > intr_status,
> > @@ -368,7 +368,7 @@ out_report:
> > out_clk:
> > clk_disable(priv->clk);
> > out_free:
> > - dma_free_coherent(priv->dev, count, kbuf, dma_addr);
> > + dma_free_coherent(mgr->dev.parent, count, kbuf, dma_addr);
> > return err;
> > }
> >
> > @@ -445,8 +445,6 @@ static int zynq_fpga_probe(struct platform_device *pdev)
> > if (!priv)
> > return -ENOMEM;
> >
> > - priv->dev = dev;
> > -
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > priv->io_base = devm_ioremap_resource(dev, res);
> > if (IS_ERR(priv->io_base))
> > --
> > 2.1.4
> >
> >
Thanks,
Moritz
^ permalink raw reply
* [PATCH] PCI: Add information about describing PCI in ACPI
From: Bjorn Helgaas @ 2016-11-17 17:59 UTC (permalink / raw)
To: linux-arm-kernel
Add a writeup about how PCI host bridges should be described in ACPI
using PNP0A03/PNP0A08 devices, PNP0C02 devices, and the MCFG table.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
Documentation/PCI/00-INDEX | 2 +
Documentation/PCI/acpi-info.txt | 136 +++++++++++++++++++++++++++++++++++++++
2 files changed, 138 insertions(+)
create mode 100644 Documentation/PCI/acpi-info.txt
diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index 147231f..0780280 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -1,5 +1,7 @@
00-INDEX
- this file
+acpi-info.txt
+ - info on how PCI host bridges are represented in ACPI
MSI-HOWTO.txt
- the Message Signaled Interrupts (MSI) Driver Guide HOWTO and FAQ.
PCIEBUS-HOWTO.txt
diff --git a/Documentation/PCI/acpi-info.txt b/Documentation/PCI/acpi-info.txt
new file mode 100644
index 0000000..ccbcfda
--- /dev/null
+++ b/Documentation/PCI/acpi-info.txt
@@ -0,0 +1,136 @@
+ ACPI considerations for PCI host bridges
+
+The basic requirement is that the ACPI namespace should describe
+*everything* that consumes address space unless there's another
+standard way for the OS to find it [1, 2]. ?For example, windows that
+are forwarded to PCI by a PCI host bridge should be described via ACPI
+devices, since the OS can't locate the host bridge by itself. ?PCI
+devices *below* the host bridge do not need to be described via ACPI,
+because the resources they consume are inside the host bridge windows,
+and the OS can discover them via the standard PCI enumeration
+mechanism (using config accesses to read and size the BARs).
+
+This ACPI resource description is done via _CRS methods of devices in
+the ACPI namespace [2]. ? _CRS methods are like generalized PCI BARs:
+the OS can read _CRS and figure out what resource is being consumed
+even if it doesn't have a driver for the device [3]. ?That's important
+because it means an old OS can work correctly even on a system with
+new devices unknown to the OS. ?The new devices won't do anything, but
+the OS can at least make sure no resources conflict with them.
+
+Static tables like MCFG, HPET, ECDT, etc., are *not* mechanisms for
+reserving address space! The static tables are for things the OS
+needs to know early in boot, before it can parse the ACPI namespace.
+If a new table is defined, an old OS needs to operate correctly even
+though it ignores the table. _CRS allows that because it is generic
+and understood by the old OS; a static table does not.
+
+If the OS is expected to manage an ACPI device, that device will have
+a specific _HID/_CID that tells the OS what driver to bind to it, and
+the _CRS tells the OS and the driver where the device's registers are.
+
+PNP0C02 "motherboard" devices are basically a catch-all. ?There's no
+programming model for them other than "don't use these resources for
+anything else." ?So any address space that is (1) not claimed by some
+other ACPI device and (2) should not be assigned by the OS to
+something else, should be claimed by a PNP0C02 _CRS method.
+
+PCI host bridges are PNP0A03 or PNP0A08 devices. ?Their _CRS should
+describe all the address space they consume. ?In principle, this would
+be all the windows they forward down to the PCI bus, as well as the
+bridge registers themselves. ?The bridge registers include things like
+secondary/subordinate bus registers that determine the bus range below
+the bridge, window registers that describe the apertures, etc. ?These
+are all device-specific, non-architected things, so the only way a
+PNP0A03/PNP0A08 driver can manage them is via _PRS/_CRS/_SRS, which
+contain the device-specific details. ?These bridge registers also
+include ECAM space, since it is consumed by the bridge.
+
+ACPI defined a Producer/Consumer bit that was intended to distinguish
+the bridge apertures from the bridge registers [4, 5]. ?However,
+BIOSes didn't use that bit correctly, and the result is that OSes have
+to assume that everything in a PCI host bridge _CRS is a window. ?That
+leaves no way to describe the bridge registers in the PNP0A03/PNP0A08
+device itself.
+
+The workaround is to describe the bridge registers (including ECAM
+space) in PNP0C02 catch-all devices [6]. ?With the exception of ECAM,
+the bridge register space is device-specific anyway, so the generic
+PNP0A03/PNP0A08 driver (pci_root.c) has no need to know about it. ?For
+ECAM, pci_root.c learns about the space from either MCFG or the _CBA
+method.
+
+Note that the PCIe spec actually does require ECAM unless there's a
+standard firmware interface for config access, e.g., the ia64 SAL
+interface [7]. One reason is that we want a generic host bridge
+driver (pci_root.c), and a generic driver requires a generic way to
+access config space.
+
+
+[1] ACPI 6.0, sec 6.1:
+ For any device that is on a non-enumerable type of bus (for
+ example, an ISA bus), OSPM enumerates the devices' identifier(s)
+ and the ACPI system firmware must supply an _HID object ... for
+ each device to enable OSPM to do that.
+
+[2] ACPI 6.0, sec 3.7:
+ The OS enumerates motherboard devices simply by reading through
+ the ACPI Namespace looking for devices with hardware IDs.
+
+ Each device enumerated by ACPI includes ACPI-defined objects in
+ the ACPI Namespace that report the hardware resources the device
+ could occupy [_PRS], an object that reports the resources that are
+ currently used by the device [_CRS], and objects for configuring
+ those resources [_SRS]. The information is used by the Plug and
+ Play OS (OSPM) to configure the devices.
+
+[3] ACPI 6.0, sec 6.2:
+ OSPM uses device configuration objects to configure hardware
+ resources for devices enumerated via ACPI. Device configuration
+ objects provide information about current and possible resource
+ requirements, the relationship between shared resources, and
+ methods for configuring hardware resources.
+
+ When OSPM enumerates a device, it calls _PRS to determine the
+ resource requirements of the device. It may also call _CRS to
+ find the current resource settings for the device. Using this
+ information, the Plug and Play system determines what resources
+ the device should consume and sets those resources by calling the
+ device?s _SRS control method.
+
+ In ACPI, devices can consume resources (for example, legacy
+ keyboards), provide resources (for example, a proprietary PCI
+ bridge), or do both. Unless otherwise specified, resources for a
+ device are assumed to be taken from the nearest matching resource
+ above the device in the device hierarchy.
+
+[4] ACPI 6.0, sec 6.4.3.5.4:
+ Extended Address Space Descriptor
+ General Flags: Bit [0] Consumer/Producer:
+ 1?This device consumes this resource
+ 0?This device produces and consumes this resource
+
+[5] ACPI 6.0, sec 19.6.43:
+ ResourceUsage specifies whether the Memory range is consumed by
+ this device (ResourceConsumer) or passed on to child devices
+ (ResourceProducer). If nothing is specified, then
+ ResourceConsumer is assumed.
+
+[6] PCI Firmware 3.0, sec 4.1.2:
+ If the operating system does not natively comprehend reserving the
+ MMCFG region, the MMCFG region must be reserved by firmware. The
+ address range reported in the MCFG table or by _CBA method (see
+ Section 4.1.3) must be reserved by declaring a motherboard
+ resource. For most systems, the motherboard resource would appear
+ at the root of the ACPI namespace (under \_SB) in a node with a
+ _HID of EISAID (PNP0C02), and the resources in this case should
+ not be claimed in the root PCI bus?s _CRS. The resources can
+ optionally be returned in Int15 E820 or EFIGetMemoryMap as
+ reserved memory but must always be reported through ACPI as a
+ motherboard resource.
+
+[7] PCI Express 3.0, sec 7.2.2:
+ For systems that are PC-compatible, or that do not implement a
+ processor-architecture-specific firmware interface standard that
+ allows access to the Configuration Space, the ECAM is required as
+ defined in this section.
^ permalink raw reply related
* [PATCH 8/9] arm64: tegra: Enable PSCI on P3310
From: Thierry Reding @ 2016-11-17 17:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <786f354d-a1f2-f2c6-fde7-7b1af3df756c@arm.com>
On Thu, Nov 17, 2016 at 05:21:34PM +0000, Sudeep Holla wrote:
>
>
> On 17/11/16 17:11, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > The P3310 processor module comes ships with a firmware that implements
> > PSCI 1.0. Enable and use it to bring up all CPUs.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 36 ++++++++++++++++++++++++++
> > 1 file changed, 36 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > index 807af7b68761..2c158c6809a5 100644
> > --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > @@ -26,7 +26,43 @@
> > status = "okay";
> > };
> >
> > + cpus {
> > + cpu at 0 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 1 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 2 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 3 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 4 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 5 {
> > + enable-method = "psci";
> > + };
> > + };
> > +
> > bpmp {
> > status = "okay";
> > };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + status = "okay";
> > + method = "smc";
>
> [...]
>
> > +
> > + cpu_off = <0x84000002>;
> > + cpu_on = <0xc4000003>;
> > + cpu_suspend = <0xc4000001>;
>
> These are applicable only for "arm,psci"(i.e. PSCI v0.1), so you need to
> drop them.
Oh, indeed. I obviously skipped the arm,psci and arm,psci-0.2 entries in
the binding documentation and then assumed the optional properties
applied regardless of PSCI version.
Removed these and everything still works as expected.
Thanks,
Thierry
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^ permalink raw reply
* Boot failures in -next due to 'ARM: dts: imx: Remove skeleton.dtsi'
From: Guenter Roeck @ 2016-11-17 17:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117163906.GB21742@leverpostej>
On 11/17/2016 08:39 AM, Mark Rutland wrote:
> On Thu, Nov 17, 2016 at 08:17:00AM -0800, Guenter Roeck wrote:
>> On 11/17/2016 07:05 AM, Mark Rutland wrote:
>>> On Thu, Nov 17, 2016 at 06:44:55AM -0800, Guenter Roeck wrote:
>>>> On 11/17/2016 02:55 AM, Mark Rutland wrote:
>>>>> Memory nodes require this property per ePAPR and the devicetree.org
>>>>> spec, so the bug is that we didn't add those when removing the
>>>>> skeleton.dtsi include.
>>>>
>>>> The downside from qemu perspective is that the real hardware seems
>>>> to add the property unconditionally, or the boot failure would have
>>>> been seen there as well.
>>>>
>>>> I submitted https://patchwork.ozlabs.org/patch/695951/; we'll see how it goes.
>>>
>>> Sure, the firmare/bootlaoder you're using may add this automatically.
>>>
>>> My worry is that adding this to a generic file in QEMU only serves to
>>> mask this class of bug for other boards (i.e. they'll work fine in QEMU,
>>> but not on real HW using whatever bootlaoder happens ot be there).
>>>
>> Good point.
>>
>> What would be the correct behavior for qemu ? Adding a chosen node if it does
>> not exist is one detail we already established. Also, I think a check if
>> /memory/device_type exists (and to bail out if it doesn't) would make sense.
>
> We'd also need to check for /memory@<n> nodes, as they can validly have
> unit-addresses (and many do).
>
> Generally, the "correct" way to find them is to iterate over all ndoes
> with device_type = "memory", so one could do that and give up if none
> are found, ignoring the naming entirely.
>
>> What about the memory node ? Does it have to exist, or should it be added
>> (including the device_type property) if not ?
>
> I'm not sure what QEMU does in this area. I suspect it may expect a node
> in some cases, or may generate one in others.
>
> There's no point generating one when we don't have the information to
> hand, certainly.
>
So far, for arm, qemu assumes that the /memory node exists, and it fills in
/memory/reg. This is done if a devicetree file is specified and numa is disabled.
Numa node handling is different; if NUMA is enabled, qemu removes an existing
/memory node and creates /memory@ nodes as configured. It does not expect
to see pre-existing /memory@ nodes.
Thanks,
Guenter
^ permalink raw reply
* [PATCH 8/9] arm64: tegra: Enable PSCI on P3310
From: Sudeep Holla @ 2016-11-17 17:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117171131.20062-8-thierry.reding@gmail.com>
On 17/11/16 17:11, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The P3310 processor module comes ships with a firmware that implements
> PSCI 1.0. Enable and use it to bring up all CPUs.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 36 ++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index 807af7b68761..2c158c6809a5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -26,7 +26,43 @@
> status = "okay";
> };
>
> + cpus {
> + cpu at 0 {
> + enable-method = "psci";
> + };
> +
> + cpu at 1 {
> + enable-method = "psci";
> + };
> +
> + cpu at 2 {
> + enable-method = "psci";
> + };
> +
> + cpu at 3 {
> + enable-method = "psci";
> + };
> +
> + cpu at 4 {
> + enable-method = "psci";
> + };
> +
> + cpu at 5 {
> + enable-method = "psci";
> + };
> + };
> +
> bpmp {
> status = "okay";
> };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + status = "okay";
> + method = "smc";
[...]
> +
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
> + cpu_suspend = <0xc4000001>;
These are applicable only for "arm,psci"(i.e. PSCI v0.1), so you need to
drop them.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH 9/9] arm64: tegra: Add NVIDIA P2771 board support
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117171131.20062-1-thierry.reding@gmail.com>
From: Joseph Lo <josephl@nvidia.com>
The NVIDIA P2771 is composed of a P3310 processor module that connects
to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is
connected via the P2597's display connector and has several connectors
such as HDMI, USB 3.0, PCIe and ethernet.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/Makefile | 1 +
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 8 ++++++++
2 files changed, 9 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 0f7cdf3e05c1..18941458cb4d 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
+dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
always := $(dtb-y)
clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
new file mode 100644
index 000000000000..0d3c0996d832
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "tegra186-p3310.dtsi"
+
+/ {
+ model = "NVIDIA Tegra186 P2771-0000 Development Board";
+ compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+};
--
2.10.2
^ permalink raw reply related
* [PATCH 8/9] arm64: tegra: Enable PSCI on P3310
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117171131.20062-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
The P3310 processor module comes ships with a firmware that implements
PSCI 1.0. Enable and use it to bring up all CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 36 ++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 807af7b68761..2c158c6809a5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -26,7 +26,43 @@
status = "okay";
};
+ cpus {
+ cpu at 0 {
+ enable-method = "psci";
+ };
+
+ cpu at 1 {
+ enable-method = "psci";
+ };
+
+ cpu at 2 {
+ enable-method = "psci";
+ };
+
+ cpu at 3 {
+ enable-method = "psci";
+ };
+
+ cpu at 4 {
+ enable-method = "psci";
+ };
+
+ cpu at 5 {
+ enable-method = "psci";
+ };
+ };
+
bpmp {
status = "okay";
};
+
+ psci {
+ compatible = "arm,psci-1.0";
+ status = "okay";
+ method = "smc";
+
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ cpu_suspend = <0xc4000001>;
+ };
};
--
2.10.2
^ permalink raw reply related
* [PATCH 7/9] arm64: tegra: Add NVIDIA P3310 processor module support
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117171131.20062-1-thierry.reding@gmail.com>
From: Joseph Lo <josephl@nvidia.com>
The NVIDIA P3310 is a processor module used in several reference designs
that features a Tegra186 SoC, 8 GiB of LPDDR4 RAM, 32 GiB eMMC and other
essentials such as ethernet, WiFi and a PMIC. It is typically connected
to an I/O board (such as the P2597) that provides the connecters needed
to hook it up to the outside world.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 32 ++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
new file mode 100644
index 000000000000..807af7b68761
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -0,0 +1,32 @@
+#include "tegra186.dtsi"
+
+/ {
+ model = "NVIDIA Tegra186 P3310 Processor Module";
+ compatible = "nvidia,p3310", "nvidia,tegra186";
+
+ aliases {
+ serial0 = &uarta;
+ };
+
+ chosen {
+ bootargs = "earlycon console=ttyS0,115200n8";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ serial at 3100000 {
+ status = "okay";
+ };
+
+ hsp at 3c00000 {
+ status = "okay";
+ };
+
+ bpmp {
+ status = "okay";
+ };
+};
--
2.10.2
^ permalink raw reply related
* [PATCH 6/9] arm64: tegra: Add GPIO controllers on Tegra186
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117171131.20062-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 1aca69f24fb0..62fa85ae0271 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1,4 +1,5 @@
#include <dt-bindings/clock/tegra186-clock.h>
+#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/reset/tegra186-reset.h>
@@ -9,6 +10,23 @@
#address-cells = <2>;
#size-cells = <2>;
+ gpio: gpio at 2200000 {
+ compatible = "nvidia,tegra186-gpio";
+ reg-names = "security", "gpio";
+ reg = <0x0 0x2200000 0x0 0x10000>,
+ <0x0 0x2210000 0x0 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
uarta: serial at 3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;
@@ -277,6 +295,18 @@
status = "disabled";
};
+ gpio_aon: gpio at c2f0000 {
+ compatible = "nvidia,tegra186-gpio-aon";
+ reg-names = "security", "gpio";
+ reg = <0x0 0xc2f0000 0x0 0x1000>,
+ <0x0 0xc2f1000 0x0 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
sysram at 30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
--
2.10.2
^ permalink raw reply related
* [PATCH 5/9] arm64: tegra: Add SDHCI controllers on Tegra186
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117171131.20062-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOST 4.1 (up to UHS-I speed).
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 ++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index b1a77d78d202..1aca69f24fb0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -163,6 +163,50 @@
status = "disabled";
};
+ sdmmc1: sdhci at 3400000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03400000 0x0 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC1>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc2: sdhci at 3420000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03420000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC2>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc3: sdhci at 3440000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC3>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc4: sdhci at 3460000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03460000 0x0 0x10000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC4>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
gic: interrupt-controller at 3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.10.2
^ permalink raw reply related
* [PATCH 4/9] arm64: tegra: Add I2C controllers on Tegra186
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117171131.20062-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads with two DPAUX controllers (for AUX transactions).
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 120 +++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 911f288966ba..b1a77d78d202 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -69,6 +69,100 @@
status = "disabled";
};
+ gen1_i2c: i2c at 3160000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x03160000 0x0 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C1>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C1>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ cam_i2c: i2c at 3180000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x03180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C3>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C3>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* shares pads with dpaux1 */
+ dp_aux_ch1_i2c: i2c at 3190000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x03190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C4>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C4>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* controlled by BPMP, should not be enabled */
+ pwr_i2c: i2c at 31a0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C5>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C5>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* shares pads with dpaux0 */
+ dp_aux_ch0_i2c: i2c at 31b0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C6>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C6>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen7_i2c: i2c at 31c0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C7>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C7>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen9_i2c: i2c at 31e0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C9>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C9>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
gic: interrupt-controller at 3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -89,6 +183,32 @@
status = "disabled";
};
+ gen2_i2c: i2c at c240000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x0c240000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C2>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C2>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen8_i2c: i2c at c250000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x0c250000 0x0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C8>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C8>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
uartc: serial at c280000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x0c280000 0x0 0x40>;
--
2.10.2
^ permalink raw reply related
* [PATCH 3/9] arm64: tegra: Add serial ports on Tegra186
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117171131.20062-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for UARTA.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 78 ++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index eadbfacd16c2..911f288966ba 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1,5 +1,7 @@
+#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/reset/tegra186-reset.h>
/ {
compatible = "nvidia,tegra186";
@@ -12,6 +14,58 @@
reg = <0x0 0x03100000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTA>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTA>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartb: serial at 3110000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03110000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTB>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTB>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartd: serial at 3130000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03130000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTD>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTD>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uarte: serial at 3140000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03140000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTE>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTE>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartf: serial at 3150000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03150000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTF>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTF>;
+ reset-names = "serial";
status = "disabled";
};
@@ -35,6 +89,30 @@
status = "disabled";
};
+ uartc: serial at c280000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0c280000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTC>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTC>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartg: serial at c290000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0c290000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTG>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTG>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
sysram at 30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
--
2.10.2
^ permalink raw reply related
* [PATCH 2/9] arm64: tegra: Add CPU nodes for Tegra186
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117171131.20062-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 41 ++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6cb8ac918530..eadbfacd16c2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -57,6 +57,47 @@
};
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "nvidia,tegra186-denver", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x000>;
+ };
+
+ cpu at 1 {
+ compatible = "nvidia,tegra186-denver", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x001>;
+ };
+
+ cpu at 2 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x100>;
+ };
+
+ cpu at 3 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x101>;
+ };
+
+ cpu at 4 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x102>;
+ };
+
+ cpu at 5 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x103>;
+ };
+ };
+
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
--
2.10.2
^ permalink raw reply related
* [PATCH 1/9] arm64: tegra: Add Tegra186 support
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Joseph Lo <josephl@nvidia.com>
This adds the initial support of Tegra186 SoC. It provides enough to
enable the serial console and boot from an initial ramdisk.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[treding at nvidia.com: remove leading 0 from unit-addresses]
[treding at nvidia.com: remove unused nvidia,bpmp property]
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 89 ++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra186.dtsi
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
new file mode 100644
index 000000000000..6cb8ac918530
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -0,0 +1,89 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/tegra186-hsp.h>
+
+/ {
+ compatible = "nvidia,tegra186";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ uarta: serial at 3100000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03100000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller at 3881000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x03881000 0x0 0x1000>,
+ <0x0 0x03882000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-parent = <&gic>;
+ };
+
+ hsp_top0: hsp at 3c00000 {
+ compatible = "nvidia,tegra186-hsp";
+ reg = <0x0 0x03c00000 0x0 0xa0000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "doorbell";
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ sysram at 30000000 {
+ compatible = "nvidia,tegra186-sysram", "mmio-sram";
+ reg = <0x0 0x30000000 0x0 0x50000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
+
+ cpu_bpmp_tx: shmem at 4e000 {
+ compatible = "nvidia,tegra186-bpmp-shmem";
+ reg = <0x0 0x4e000 0x0 0x1000>;
+ label = "cpu-bpmp-tx";
+ pool;
+ };
+
+ cpu_bpmp_rx: shmem at 4f000 {
+ compatible = "nvidia,tegra186-bpmp-shmem";
+ reg = <0x0 0x4f000 0x0 0x1000>;
+ label = "cpu-bpmp-rx";
+ pool;
+ };
+ };
+
+ bpmp: bpmp {
+ compatible = "nvidia,tegra186-bpmp";
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
+ TEGRA_HSP_DB_MASTER_BPMP>;
+ shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ bpmp_i2c: i2c {
+ compatible = "nvidia,tegra186-bpmp-i2c";
+ nvidia,bpmp-bus-id = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&gic>;
+ };
+};
--
2.10.2
^ permalink raw reply related
* [PATCH 01/16] ARM: scu: Provide support for parsing SCU device node to enable SCU
From: Arnd Bergmann @ 2016-11-17 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <fe90b6cc-81b1-772e-ab78-f2199957ec96@samsung.com>
On Thursday, November 17, 2016 9:50:27 AM CET pankaj.dubey wrote:
>
> >>> of_scu_enable() which _only_ looks up the SCU address in DT and enables
> >>> it if it finds it, otherwise returning failure.
> >>>
> >>> a9_scu_enable() which tries to use the A9 provided SCU address and
> >>> enables it if it finds it, otherwise returning failure.
> >>>
>
> OK, In that case I can see need for following four helpers as:
>
> 1: of_scu_enable() which will __only__ lookup the SCU address in DT and
> enables it if it finds, otherwise return -ENOMEM failure.
> This helper APIs is required and sufficient for most of platforms such
> as exynos, berlin, realview, socfpga, STi, ux500, vexpress, rockchip and
> mvebu
>
> 2: a9_scu_enable(), which will __only__ use A9 provided SCU address and
> enables it, if address mapped successfully, otherwise returning failure.
> This helper APIs is required and sufficient for two ARM platforms as of
> now tegra and hisi.
>
> 3: of_scu_get_base() which will lookup the SCU address in DT and if node
> found maps address and returns ioremapped address to caller.
> This helper APIs is required for three ARM plaforms rockchip, mvebu and
> ux500, along with scu_enable() API to enable and find number_of_cores.
>
> 4: s9_scu_iomap_base() which will internally use s9_scu_get_base() and
> do ioremap of scu address and returns ioremapped address to the caller
> along with ownership (caller has responsibility to unmap it).
> This helper APIs is required to simplify SCU enable and related code in
> two ARM plaforms BCM ans ZX.
>
> For remaining two ARM platforms (IMX and ZYNQ), none of these helpers
> are useful for the time-being, as they need SCU mapping very early of
> boot, where we can't use iomap APIs. So I will drop patches related to
> these platforms in v2 version.
>
> Please let me know if any concern in this approach.
I think ideally we wouldn't even need to know the virtual address
outside of smp_scu.c. If we can move all users of the address
into that file directly, it could become a local variable and
we change scu_power_mode() and scu_get_core_count() instead to
not require the address argument.
The only user I could find outside of that file is
static int shmobile_smp_scu_psr_core_disabled(int cpu)
{
unsigned long mask = SCU_PM_POWEROFF << (cpu * 8);
if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
return 1;
return 0;
}
which can be done in the same file as well.
> >>> Then callers can decide which of these to call, and what error messages
> >>> to print on their failures.
> >>
> >> Splitting the function in two is probably simpler overall, but
> >> we may still have to look at all the callers: Any platform that
> >> currently tries to map it on any CPU and doesn't warn about the
> >> absence of the device node (or about scu_a9_has_base() == false)
> >> should really continue not to warn about that.
> >
> > Did you miss the bit where none of of_scu_enable() or a9_scu_enable()
> > should produce any warnings or errors to be printed. It's up to the
> > caller to report the failure, otherwise doing this doesn't make sense:
> >
> > if (of_scu_enable() < 0 && a9_scu_enable() < 0)
> > pr_err("Failed to map and enable the SCU\n");
> >
> > because if of_scu_enable() prints a warning/error, then it's patently
> > misleading.
> >
That's why I said "otherwise we can leave the warning in the caller
after checking the return code of the new APIs." for the case where
we actually need it.
> I will move out error message out of these helpers and let caller
> (platform specific code) handle and print error if required.
Ok.
Arnd
^ permalink raw reply
* [PATCH] clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock
From: Icenowy Zheng @ 2016-11-17 16:49 UTC (permalink / raw)
To: linux-arm-kernel
In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control
register is called "LDO{1,2}_EN", and according to the BSP source code
from Allwinner [1], the LDOs are enabled during the clock's enabling
process.
The clock failed to generate output if the two LDOs are not enabled.
Add the two bits to the clock's gate bits, so that the LDOs are enabled
when the PLL is enabled.
[1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429
Fixes: d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Dear Chen-Yu:
As you said, the two bits are also present in the CCU of A23 and A31.
Could you please check whether the PLL works on the two SoCs?
I remembered you mentioned you failed to make TCON enabled on A23.
On A31, you may hack the parent of tcon-ch0 to force the tcon clock to
use pll-mipi as parent, in order to check whether the pll works.
However, I didn't found the code that enables the LDOs in the BSP A23/31
sources, so you must test them to ensure whether the code is needed for
these SoCs.
Regards,
Icenowy
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 96b40ca..9bd1f78 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -131,7 +131,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
8, 4, /* N */
4, 2, /* K */
0, 4, /* M */
- BIT(31), /* gate */
+ BIT(31) | BIT(23) | BIT(22), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
--
2.10.1
^ permalink raw reply related
* Boot failures in -next due to 'ARM: dts: imx: Remove skeleton.dtsi'
From: Mark Rutland @ 2016-11-17 16:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2eaf84f9-ea00-d331-1875-56adafb62378@roeck-us.net>
On Thu, Nov 17, 2016 at 08:17:00AM -0800, Guenter Roeck wrote:
> On 11/17/2016 07:05 AM, Mark Rutland wrote:
> >On Thu, Nov 17, 2016 at 06:44:55AM -0800, Guenter Roeck wrote:
> >>On 11/17/2016 02:55 AM, Mark Rutland wrote:
> >>>Memory nodes require this property per ePAPR and the devicetree.org
> >>>spec, so the bug is that we didn't add those when removing the
> >>>skeleton.dtsi include.
> >>
> >>The downside from qemu perspective is that the real hardware seems
> >>to add the property unconditionally, or the boot failure would have
> >>been seen there as well.
> >>
> >>I submitted https://patchwork.ozlabs.org/patch/695951/; we'll see how it goes.
> >
> >Sure, the firmare/bootlaoder you're using may add this automatically.
> >
> >My worry is that adding this to a generic file in QEMU only serves to
> >mask this class of bug for other boards (i.e. they'll work fine in QEMU,
> >but not on real HW using whatever bootlaoder happens ot be there).
> >
> Good point.
>
> What would be the correct behavior for qemu ? Adding a chosen node if it does
> not exist is one detail we already established. Also, I think a check if
> /memory/device_type exists (and to bail out if it doesn't) would make sense.
We'd also need to check for /memory@<n> nodes, as they can validly have
unit-addresses (and many do).
Generally, the "correct" way to find them is to iterate over all ndoes
with device_type = "memory", so one could do that and give up if none
are found, ignoring the naming entirely.
> What about the memory node ? Does it have to exist, or should it be added
> (including the device_type property) if not ?
I'm not sure what QEMU does in this area. I suspect it may expect a node
in some cases, or may generate one in others.
There's no point generating one when we don't have the information to
hand, certainly.
Thanks,
Mark.
^ permalink raw reply
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