* [PATCH 14/20] arm/bL_switcher: Convert to hotplug state machine
From: Sebastian Andrzej Siewior @ 2016-11-17 18:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117183541.8588-1-bigeasy@linutronix.de>
Install the callbacks via the state machine.
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
arch/arm/common/bL_switcher.c | 34 ++++++++++++++++++++--------------
include/linux/cpuhotplug.h | 1 +
2 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/arch/arm/common/bL_switcher.c b/arch/arm/common/bL_switcher.c
index 37dc0fe1093f..46730017b3c5 100644
--- a/arch/arm/common/bL_switcher.c
+++ b/arch/arm/common/bL_switcher.c
@@ -757,19 +757,18 @@ EXPORT_SYMBOL_GPL(bL_switcher_put_enabled);
* while the switcher is active.
* We're just not ready to deal with that given the trickery involved.
*/
-static int bL_switcher_hotplug_callback(struct notifier_block *nfb,
- unsigned long action, void *hcpu)
+static int bL_switcher_cpu_pre(unsigned int cpu)
{
- if (bL_switcher_active) {
- int pairing = bL_switcher_cpu_pairing[(unsigned long)hcpu];
- switch (action & 0xf) {
- case CPU_UP_PREPARE:
- case CPU_DOWN_PREPARE:
- if (pairing == -1)
- return NOTIFY_BAD;
- }
- }
- return NOTIFY_DONE;
+ int pairing;
+
+ if (!bL_switcher_active)
+ return 0;
+
+ pairing = bL_switcher_cpu_pairing[cpu];
+
+ if (pairing == -1)
+ return -EINVAL;
+ return 0;
}
static bool no_bL_switcher;
@@ -782,8 +781,15 @@ static int __init bL_switcher_init(void)
if (!mcpm_is_available())
return -ENODEV;
- cpu_notifier(bL_switcher_hotplug_callback, 0);
-
+ cpuhp_setup_state_nocalls(CPUHP_ARM_BL_PREPARE, "arm/bl:prepare",
+ bL_switcher_cpu_pre, NULL);
+ ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "arm/bl:predown",
+ NULL, bL_switcher_cpu_pre);
+ if (ret < 0) {
+ cpuhp_remove_state_nocalls(CPUHP_ARM_BL_PREPARE);
+ pr_err("bL_switcher: Failed to allocate a hotplug state\n");
+ return ret;
+ }
if (!no_bL_switcher) {
ret = bL_switcher_enable();
if (ret)
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 69abf2c09f6c..4b99b79c16e5 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -64,6 +64,7 @@ enum cpuhp_state {
CPUHP_X86_CPUID_PREPARE,
CPUHP_X86_MSR_PREPARE,
CPUHP_NET_IUCV_PREPARE,
+ CPUHP_ARM_BL_PREPARE,
CPUHP_TIMERS_DEAD,
CPUHP_NOTF_ERR_INJ_PREPARE,
CPUHP_MIPS_SOC_PREPARE,
--
2.10.2
^ permalink raw reply related
* [PATCH 15/20] ARM/hw_breakpoint: Convert to hotplug state machine
From: Sebastian Andrzej Siewior @ 2016-11-17 18:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117183541.8588-1-bigeasy@linutronix.de>
Install the callbacks via the state machine and let the core invoke
the callbacks on the already online CPUs.
smp_call_function_single() has been removed because the function is already
invoked on the target CPU.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/arm/kernel/hw_breakpoint.c | 44 ++++++++++++++++++-----------------------
1 file changed, 19 insertions(+), 25 deletions(-)
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index b8df45883cf7..51cff5a8feff 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -925,9 +925,9 @@ static bool core_has_os_save_restore(void)
}
}
-static void reset_ctrl_regs(void *unused)
+static void reset_ctrl_regs(unsigned int cpu)
{
- int i, raw_num_brps, err = 0, cpu = smp_processor_id();
+ int i, raw_num_brps, err = 0;
u32 val;
/*
@@ -1020,25 +1020,20 @@ static void reset_ctrl_regs(void *unused)
cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
}
-static int dbg_reset_notify(struct notifier_block *self,
- unsigned long action, void *cpu)
+static int dbg_reset_online(unsigned int cpu)
{
- if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
- smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
-
- return NOTIFY_OK;
+ local_irq_disable();
+ reset_ctrl_regs(cpu);
+ local_irq_enable();
+ return 0;
}
-static struct notifier_block dbg_reset_nb = {
- .notifier_call = dbg_reset_notify,
-};
-
#ifdef CONFIG_CPU_PM
static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
void *v)
{
if (action == CPU_PM_EXIT)
- reset_ctrl_regs(NULL);
+ reset_ctrl_regs(smp_processor_id());
return NOTIFY_OK;
}
@@ -1059,6 +1054,8 @@ static inline void pm_init(void)
static int __init arch_hw_breakpoint_init(void)
{
+ int ret;
+
debug_arch = get_debug_arch();
if (!debug_arch_supported()) {
@@ -1072,8 +1069,6 @@ static int __init arch_hw_breakpoint_init(void)
core_num_brps = get_num_brps();
core_num_wrps = get_num_wrps();
- cpu_notifier_register_begin();
-
/*
* We need to tread carefully here because DBGSWENABLE may be
* driven low on this core and there isn't an architected way to
@@ -1082,15 +1077,18 @@ static int __init arch_hw_breakpoint_init(void)
register_undef_hook(&debug_reg_hook);
/*
- * Reset the breakpoint resources. We assume that a halting
- * debugger will leave the world in a nice state for us.
+ * Register CPU notifier which resets the breakpoint resources. We
+ * assume that a halting debugger will leave the world in a nice state
+ * for us.
*/
- on_each_cpu(reset_ctrl_regs, NULL, 1);
+ ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm/hw_breakpoint:online",
+ dbg_reset_online, NULL);
unregister_undef_hook(&debug_reg_hook);
- if (!cpumask_empty(&debug_err_mask)) {
+ if (WARN_ON(ret < 0) || !cpumask_empty(&debug_err_mask)) {
core_num_brps = 0;
core_num_wrps = 0;
- cpu_notifier_register_done();
+ if (ret > 0)
+ cpuhp_remove_state_nocalls(ret);
return 0;
}
@@ -1109,11 +1107,7 @@ static int __init arch_hw_breakpoint_init(void)
hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
TRAP_HWBKPT, "breakpoint debug exception");
- /* Register hotplug and PM notifiers. */
- __register_cpu_notifier(&dbg_reset_nb);
-
- cpu_notifier_register_done();
-
+ /* Register PM notifiers. */
pm_init();
return 0;
}
--
2.10.2
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: sun5i: Add touchscreen node to reference-design-tablet.dtsi
From: Hans de Goede @ 2016-11-17 18:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117183520.vpyw72mchynpqx7d@lukather>
Hi,
On 17-11-16 19:35, Maxime Ripard wrote:
> Hi Hans,
>
> On Tue, Nov 15, 2016 at 11:12:35AM +0100, Hans de Goede wrote:
>> Hi,
>>
>> On 14-11-16 21:08, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Sun, Nov 13, 2016 at 08:22:02PM +0100, Hans de Goede wrote:
>>>> Just like on sun8i all sun5i tablets use the same interrupt and power
>>>> gpios for their touchscreens. I've checked all known a13 fex files and
>>>> only the UTOO P66 uses a different gpio for the interrupt.
>>>>
>>>> Add a touchscreen node to sun5i-reference-design-tablet.dtsi, which
>>>> fills in the necessary gpios to avoid duplication in the tablet dts files,
>>>> just like we do in sun8i-reference-design-tablet.dtsi.
>>>>
>>>> This will make future patches adding touchscreen nodes to a13 tablets
>>>> simpler.
>>>>
>>>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>>>> ---
>>>> arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 38 ++++++++--------------
>>>> .../boot/dts/sun5i-reference-design-tablet.dtsi | 25 ++++++++++++++
>>>> 2 files changed, 39 insertions(+), 24 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
>>>> index a8b0bcc..3d7ff10 100644
>>>> --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
>>>> +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
>>>> @@ -83,22 +83,6 @@
>>>> allwinner,pins = "PG3";
>>>> };
>>>>
>>>> -&i2c1 {
>>>> - icn8318: touchscreen at 40 {
>>>> - compatible = "chipone,icn8318";
>>>> - reg = <0x40>;
>>>> - interrupt-parent = <&pio>;
>>>> - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
>>>> - pinctrl-names = "default";
>>>> - pinctrl-0 = <&ts_wake_pin_p66>;
>>>> - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
>>>> - touchscreen-size-x = <800>;
>>>> - touchscreen-size-y = <480>;
>>>> - touchscreen-inverted-x;
>>>> - touchscreen-swapped-x-y;
>>>> - };
>>>> -};
>>>> -
>>>> &mmc2 {
>>>> pinctrl-names = "default";
>>>> pinctrl-0 = <&mmc2_pins_a>;
>>>> @@ -121,20 +105,26 @@
>>>> allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>>> allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
>>>> };
>>>> -
>>>> - ts_wake_pin_p66: ts_wake_pin at 0 {
>>>> - allwinner,pins = "PB3";
>>>> - allwinner,function = "gpio_out";
>>>> - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>>> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>>> - };
>>>> -
>>>> };
>>>>
>>>> ®_usb0_vbus {
>>>> gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
>>>> };
>>>>
>>>> +&touchscreen {
>>>> + compatible = "chipone,icn8318";
>>>> + reg = <0x40>;
>>>> + /* The P66 uses a different EINT then the reference design */
>>>> + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
>>>> + /* The icn8318 binding expects wake-gpios instead of power-gpios */
>>>> + wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
>>>> + touchscreen-size-x = <800>;
>>>> + touchscreen-size-y = <480>;
>>>> + touchscreen-inverted-x;
>>>> + touchscreen-swapped-x-y;
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> &uart1 {
>>>> /* The P66 uses the uart pins as gpios */
>>>> status = "disabled";
>>>> diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
>>>> index 20cc940..7af488a 100644
>>>> --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
>>>> +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
>>>> @@ -41,6 +41,7 @@
>>>> */
>>>> #include "sunxi-reference-design-tablet.dtsi"
>>>>
>>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>>> #include <dt-bindings/pwm/pwm.h>
>>>>
>>>> / {
>>>> @@ -84,6 +85,23 @@
>>>> };
>>>>
>>>> &i2c1 {
>>>> + /*
>>>> + * The gsl1680 is rated at 400KHz and it will not work reliable at
>>>> + * 100KHz, this has been confirmed on multiple different q8 tablets.
>>>> + * All other devices on this bus are also rated for 400KHz.
>>>> + */
>>>> + clock-frequency = <400000>;
>>>> +
>>>> + touchscreen: touchscreen {
>>>> + interrupt-parent = <&pio>;
>>>> + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&ts_power_pin>;
>>>> + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
>>>> + /* Tablet dts must provide reg and compatible */
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> pcf8563: rtc at 51 {
>>>> compatible = "nxp,pcf8563";
>>>> reg = <0x51>;
>>>> @@ -125,6 +143,13 @@
>>>> allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
>>>> };
>>>>
>>>> + ts_power_pin: ts_power_pin {
>>>> + allwinner,pins = "PB3";
>>>> + allwinner,function = "gpio_out";
>>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>>> + };
>>>> +
>>>
>>> For the next release, we'll switch to the generic pin mux properties
>>> ("pins" and "function"), and we actually implemented the fact that the
>>> drive and pull properties are optional, so you can drop them both.
>>>
>>> You'll need next + http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/467123.html
>>
>> Ok, before I send a v2 first a question about this, for the touchscreen
>> case I actually need:
>>
>> allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>
>> Because otherwise when the touchscreen controller is powered by a separate
>> regulator and that regulator is off, then it may draw just enough current
>> from its enable pin to be sort-of listening to the i2c bus and mess up
>> that bus.
>>
>> So is this the default, or do we get the power-on default when not
>> specifying these? If it is the power-on default then we do need to
>> specify these, because AFAICT the power-on drive strength typically
>> is 20 mA.
>
> Leaving them out will keep whatever state has been programmed. Putting
> them in the DT will force them to whatever value has been set.
Thanks for the answer, in the mean time I've send a v2 which leaves
them in using the new names (which according to your answer seems to
be the right thing to do).
Regards,
Hans
^ permalink raw reply
* [PATCH v4] arm64: dts: qcom: Add msm8916 CoreSight components
From: Mathieu Poirier @ 2016-11-17 18:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117153522.11630-1-georgi.djakov@linaro.org>
On Thu, Nov 17, 2016 at 05:35:22PM +0200, Georgi Djakov wrote:
> From: "Ivan T. Ivanov" <ivan.ivanov@linaro.org>
>
> Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.
Hello Georgi,
Could you add a better desccription for the SoC? To me "8x16" doesn't
say much.
With that change:
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>
> Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
>
> This patch was on hold for some time, as it has a dependency on RPM clocks,
> which is now merged into clk-next.
>
> Changes since v3: (https://lkml.org/lkml/2015/5/11/134)
> * Include msm8916-coresight.dtsi into msm8916.dtsi
>
> Changes since v2: (https://lkml.org/lkml/2015/4/29/242)
> * Added "1x" to "qcom,coresight-replicator" compatible string, to match what
> devicetree bindings documentations says.
>
>
> arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi | 254 ++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +
> 2 files changed, 256 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
> new file mode 100644
> index 000000000000..900f1f484a0a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
> @@ -0,0 +1,254 @@
> +/*
> + * Copyright (c) 2013 - 2015, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +&soc {
> +
> + tpiu at 820000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0x820000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + port {
> + tpiu_in: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out1>;
> + };
> + };
> + };
> +
> + funnel at 821000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x821000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /*
> + * Not described input ports:
> + * 0 - connected to Resource and Power Manger CPU ETM
> + * 1 - not-connected
> + * 2 - connected to Modem CPU ETM
> + * 3 - not-connected
> + * 5 - not-connected
> + * 6 - connected trought funnel to Wireless CPU ETM
> + * 7 - connected to STM component
> + */
> + port at 4 {
> + reg = <4>;
> + funnel0_in4: endpoint {
> + slave-mode;
> + remote-endpoint = <&funnel1_out>;
> + };
> + };
> + port at 8 {
> + reg = <0>;
> + funnel0_out: endpoint {
> + remote-endpoint = <&etf_in>;
> + };
> + };
> + };
> + };
> +
> + replicator at 824000 {
> + compatible = "qcom,coresight-replicator1x", "arm,primecell";
> + reg = <0x824000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + replicator_out0: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + port at 1 {
> + reg = <1>;
> + replicator_out1: endpoint {
> + remote-endpoint = <&tpiu_in>;
> + };
> + };
> + port at 2 {
> + reg = <0>;
> + replicator_in: endpoint {
> + slave-mode;
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf at 825000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x825000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + etf_out: endpoint {
> + slave-mode;
> + remote-endpoint = <&funnel0_out>;
> + };
> + };
> + port at 1 {
> + reg = <0>;
> + etf_in: endpoint {
> + remote-endpoint = <&replicator_in>;
> + };
> + };
> + };
> + };
> +
> + etr at 826000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x826000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + port {
> + etr_in: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out0>;
> + };
> + };
> + };
> +
> + funnel at 841000 { /* APSS funnel only 4 inputs are used */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x841000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + funnel1_in0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm0_out>;
> + };
> + };
> + port at 1 {
> + reg = <1>;
> + funnel1_in1: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm1_out>;
> + };
> + };
> + port at 2 {
> + reg = <2>;
> + funnel1_in2: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm2_out>;
> + };
> + };
> + port at 3 {
> + reg = <3>;
> + funnel1_in3: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm3_out>;
> + };
> + };
> + port at 4 {
> + reg = <0>;
> + funnel1_out: endpoint {
> + remote-endpoint = <&funnel0_in4>;
> + };
> + };
> + };
> + };
> +
> + etm at 85c000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x85c000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU0>;
> +
> + port {
> + etm0_out: endpoint {
> + remote-endpoint = <&funnel1_in0>;
> + };
> + };
> + };
> +
> + etm at 85d000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x85d000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU1>;
> +
> + port {
> + etm1_out: endpoint {
> + remote-endpoint = <&funnel1_in1>;
> + };
> + };
> + };
> +
> + etm at 85e000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x85e000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU2>;
> +
> + port {
> + etm2_out: endpoint {
> + remote-endpoint = <&funnel1_in2>;
> + };
> + };
> + };
> +
> + etm at 85f000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x85f000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU3>;
> +
> + port {
> + etm3_out: endpoint {
> + remote-endpoint = <&funnel1_in3>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 4221b7d2c0ce..bfaeb9364190 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -14,6 +14,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,gcc-msm8916.h>
> #include <dt-bindings/reset/qcom,gcc-msm8916.h>
> +#include <dt-bindings/clock/qcom,rpmcc.h>
>
> / {
> model = "Qualcomm Technologies, Inc. MSM8916";
> @@ -993,4 +994,5 @@
> };
> };
>
> +#include "msm8916-coresight.dtsi"
> #include "msm8916-pins.dtsi"
^ permalink raw reply
* [PATCH] drm/sun4i: Only count TCON endpoints as valid outputs
From: Maxime Ripard @ 2016-11-17 19:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116093732.12828-1-wens@csie.org>
On Wed, Nov 16, 2016 at 05:37:31PM +0800, Chen-Yu Tsai wrote:
> The sun4i DRM driver counts the number of endpoints it found and
> registers the whole DRM pipeline if any endpoints are found.
>
> However, if the TCON and its child endpoints (LCD panels, TV encoder,
> HDMI encoder, MIPI DSI encoder, etc.) aren't found, that means we
> don't have any usable CRTCs, and the display pipeline is incomplete
> and useless.
If some node set as available is not probed, then yes, it does, but
I'm not really sure how it's a problem. Quite the opposite actually.
> The whole DRM display pipeline should only be registered and enabled
> if there are proper outputs available.
Unless I've misunderstood what you're saying, we could have the
writeback for example that would just need the display engine.
> The debug message "Queued %d outputs on pipeline %d\n" is also telling.
>
> This patch makes the driver only count enabled TCON endpoints. If
> none are found, the DRM pipeline is not used. This avoids screwing
> up the simple framebuffer provided by the bootloader in cases where
> we aren't able to support the display with the DRM subsystem, due
> to lack of panel or bridge drivers, or just lack of progress.
The framebuffer is removed only at bind time, which means that all the
drivers have probed already. Lack of progress isn't an issue here,
since the node simply won't be there, and we wouldn't have it in the
component lists. And lack of drivers shouldn't be an issue either,
since in order for bind to be called, all the drivers would have
gone through their probe.
So I'm not really sure what it fixes.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH] ARM: dts: qcom: Add apq8064 CoreSight components
From: Mathieu Poirier @ 2016-11-17 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117153609.11705-1-georgi.djakov@linaro.org>
On Thu, Nov 17, 2016 at 05:36:09PM +0200, Georgi Djakov wrote:
> From: "Ivan T. Ivanov" <ivan.ivanov@linaro.org>
>
> Add initial set of CoreSight components found on Qualcomm's
> 8064 chipset.
>
> Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
> arch/arm/boot/dts/qcom-apq8064-coresight.dtsi | 196 ++++++++++++++++++++++++++
> arch/arm/boot/dts/qcom-apq8064.dtsi | 11 +-
> 2 files changed, 203 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm/boot/dts/qcom-apq8064-coresight.dtsi
>
> diff --git a/arch/arm/boot/dts/qcom-apq8064-coresight.dtsi b/arch/arm/boot/dts/qcom-apq8064-coresight.dtsi
> new file mode 100644
> index 000000000000..9395fddb1bf0
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-apq8064-coresight.dtsi
> @@ -0,0 +1,196 @@
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +&soc {
> +
> + etb at 1a01000 {
> + compatible = "coresight-etb10", "arm,primecell";
> + reg = <0x1a01000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etb_in: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out0>;
> + };
> + };
> + };
> +
> + tpiu at 1a03000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0x1a03000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>;
> + clock-names = "apb_pclk";
> +
> + port {
> + tpiu_in: endpoint {
> + slave-mode;
> + remote-endpoint = <&replicator_out1>;
> + };
> + };
> + };
> +
> + replicator {
> + compatible = "arm,coresight-replicator";
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>;
> + clock-names = "apb_pclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + replicator_out0: endpoint {
> + remote-endpoint = <&etb_in>;
> + };
> + };
> + port at 1 {
> + reg = <1>;
> + replicator_out1: endpoint {
> + remote-endpoint = <&tpiu_in>;
> + };
> + };
> + port at 2 {
> + reg = <0>;
> + replicator_in: endpoint {
> + slave-mode;
> + remote-endpoint = <&funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel at 1a04000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0x1a04000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>;
> + clock-names = "apb_pclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /*
> + * Not described input ports:
> + * 2 - connected to STM component
> + * 3 - not-connected
> + * 6 - not-connected
> + * 7 - not-connected
> + */
> + port at 0 {
> + reg = <0>;
> + funnel_in0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm0_out>;
> + };
> + };
> + port at 1 {
> + reg = <1>;
> + funnel_in1: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm1_out>;
> + };
> + };
> + port at 4 {
> + reg = <4>;
> + funnel_in4: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm2_out>;
> + };
> + };
> + port at 5 {
> + reg = <5>;
> + funnel_in5: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm3_out>;
> + };
> + };
> + port at 8 {
> + reg = <0>;
> + funnel_out: endpoint {
> + remote-endpoint = <&replicator_in>;
> + };
> + };
> + };
> + };
> +
> + etm at 1a1c000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
> + reg = <0x1a1c000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&CPU0>;
> +
> + port {
> + etm0_out: endpoint {
> + remote-endpoint = <&funnel_in0>;
> + };
> + };
> + };
> +
> + etm at 1a1d000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
> + reg = <0x1a1d000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&CPU1>;
> +
> + port {
> + etm1_out: endpoint {
> + remote-endpoint = <&funnel_in1>;
> + };
> + };
> + };
> +
> + etm at 1a1e000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
> + reg = <0x1a1e000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&CPU2>;
> +
> + port {
> + etm2_out: endpoint {
> + remote-endpoint = <&funnel_in4>;
> + };
> + };
> + };
> +
> + etm at 1a1f000 {
> + compatible = "arm,coresight-etm3x", "arm,primecell";
> + reg = <0x1a1f000 0x1000>;
> +
> + clocks = <&rpmcc RPM_QDSS_CLK>;
> + clock-names = "apb_pclk";
> +
> + cpu = <&CPU3>;
> +
> + port {
> + etm3_out: endpoint {
> + remote-endpoint = <&funnel_in5>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 268bd470c865..18469c632e2f 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -4,6 +4,7 @@
> #include <dt-bindings/clock/qcom,gcc-msm8960.h>
> #include <dt-bindings/reset/qcom,gcc-msm8960.h>
> #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
> +#include <dt-bindings/clock/qcom,rpmcc.h>
> #include <dt-bindings/soc/qcom,gsbi.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -27,7 +28,7 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> - cpu at 0 {
> + CPU0: cpu at 0 {
> compatible = "qcom,krait";
> enable-method = "qcom,kpss-acc-v1";
> device_type = "cpu";
> @@ -38,7 +39,7 @@
> cpu-idle-states = <&CPU_SPC>;
> };
>
> - cpu at 1 {
> + CPU1: cpu at 1 {
> compatible = "qcom,krait";
> enable-method = "qcom,kpss-acc-v1";
> device_type = "cpu";
> @@ -49,7 +50,7 @@
> cpu-idle-states = <&CPU_SPC>;
> };
>
> - cpu at 2 {
> + CPU2: cpu at 2 {
> compatible = "qcom,krait";
> enable-method = "qcom,kpss-acc-v1";
> device_type = "cpu";
> @@ -60,7 +61,7 @@
> cpu-idle-states = <&CPU_SPC>;
> };
>
> - cpu at 3 {
> + CPU3: cpu at 3 {
> compatible = "qcom,krait";
> enable-method = "qcom,kpss-acc-v1";
> device_type = "cpu";
> @@ -1418,4 +1419,6 @@
> };
> };
> };
> +
> +#include "qcom-apq8064-coresight.dtsi"
> #include "qcom-apq8064-pins.dtsi"
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
^ permalink raw reply
* [PATCH] drm/sun4i: tcon: Initialize regmap after enabling bus clocks
From: Maxime Ripard @ 2016-11-17 19:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116093732.12828-2-wens@csie.org>
On Wed, Nov 16, 2016 at 05:37:32PM +0800, Chen-Yu Tsai wrote:
> If we attempt to read/write the TCON registers before the bus clock
> is enabled, those accesses get ignored.
>
> In practice this almost never occurs because U-boot had already enabled
> the bus clock as part of its firmware provided framebuffer (simplefb).
>
> Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>
> I was looking around the DRM driver and noticed this sequence was off.
>
> ---
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> index c6afb2448655..8c2db65ea229 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> @@ -506,16 +506,16 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
> return ret;
> }
>
> - ret = sun4i_tcon_init_regmap(dev, tcon);
> + ret = sun4i_tcon_init_clocks(dev, tcon);
> if (ret) {
> - dev_err(dev, "Couldn't init our TCON regmap\n");
> + dev_err(dev, "Couldn't init our TCON clocks\n");
> goto err_assert_reset;
> }
>
> - ret = sun4i_tcon_init_clocks(dev, tcon);
> + ret = sun4i_tcon_init_regmap(dev, tcon);
> if (ret) {
> - dev_err(dev, "Couldn't init our TCON clocks\n");
> - goto err_assert_reset;
> + dev_err(dev, "Couldn't init our TCON regmap\n");
> + goto err_free_clocks;
> }
That won't work either. sun4i_tcon_init_clocks requires the regmap to
be enabled before it calls sun4i_dclk_create.
Maybe we should just move that call outside of sun4i_tcon_init_clocks
and put it directly into the bind then.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH fpga 8/9] fpga socfpga: Use the scatterlist interface
From: atull @ 2016-11-17 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116202329.GD19593@obsidianresearch.com>
On Wed, 16 Nov 2016, Jason Gunthorpe wrote:
> On Wed, Nov 16, 2016 at 09:45:23AM -0600, atull wrote:
> > > What is the point of this if write_init gets a copy of the buffer -
> > > what is that supposed to be?
> >
> > Sometimes write_init needs to look at the header of the image.
> > You can see that in the socfpga-a10.c (on linux-next/master)
>
> I know what it is for, I'm asking what should it be if we are calling
> write_init multiple times.
>
> It feels like the driver needs to indicate the header length it wants
> to inspect and the core core needs to make that much of the bitstream
> available to write_init() before calling write().
>
> Is that what you were thinking?
That would make sense. socfpga-a10.c requires a certain amount
of header in write_init, but the current API didn't have a way
for socfgpa-a10.c to specify that to fpga-mgr.c core. Should
probably happen during registration. If you have an idea about
that, that's good, otherwise we'll get back to that separately.
>
> > at this stuff, this is coming at a busy time). My point there
> > was that there was code that needed to go into the core so that
> > the ICE40 and the cyclone spi driver that are on the mailing
> > list won't have to have the same workaround that you were
> > adding to the socfpga.c driver.
>
> Sure, that is easy for write() - not clear on write_init sematics?
> I will send a revised series.
>
> I'd also like to close on the zynq bitfile verification patch, did you
> have any comments on that?
I think Joshua had some comments. Besides that, I'm ok with that
patch.
Alan
>
> Jason
>
^ permalink raw reply
* [PATCH v2] ARM: dts: sun5i: Add touchscreen node to reference-design-tablet.dtsi
From: Maxime Ripard @ 2016-11-17 20:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116131508.12541-1-hdegoede@redhat.com>
On Wed, Nov 16, 2016 at 02:15:08PM +0100, Hans de Goede wrote:
> Just like on sun8i all sun5i tablets use the same interrupt and power
> gpios for their touchscreens. I've checked all known a13 fex files and
> only the UTOO P66 uses a different gpio for the interrupt.
>
> Add a touchscreen node to sun5i-reference-design-tablet.dtsi, which
> fills in the necessary gpios to avoid duplication in the tablet dts files,
> just like we do in sun8i-reference-design-tablet.dtsi.
>
> This will make future patches adding touchscreen nodes to a13 tablets
> simpler.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v4 2/2] ARM: dts: sun6i: hummingbird-a31: Enable display output through VGA bridge
From: Maxime Ripard @ 2016-11-17 20:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161116154232.872-3-wens@csie.org>
On Wed, Nov 16, 2016 at 11:42:32PM +0800, Chen-Yu Tsai wrote:
> The Hummingbird A31 board has a VGA DAC which converts RGB output
> from the LCD interface to VGA analog signals.
>
> Add nodes for the VGA DAC, its power supply, and enable this part
> of the display pipeline.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH] kirkwood: fix spelling mistake
From: p.wassi at gmx.at @ 2016-11-17 20:29 UTC (permalink / raw)
To: linux-arm-kernel
From: Paul Wassi <p.wassi@gmx.at>
Fix a spelling mistake in arch/arm/boot/dts/kirkwood-topkick.dts
Signed-off-by: Paul Wassi <p.wassi@gmx.at>
---
The manufacturer's name is Univer*s*al Scientific Industrial...
Compare with footer of page here:
http://www.usish.com/english/products_topkick1281p2.php
arch/arm/boot/dts/kirkwood-topkick.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -rupN a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -4,7 +4,7 @@
#include "kirkwood-6282.dtsi"
/ {
- model = "Univeral Scientific Industrial Co. Topkick-1281P2";
+ model = "Universal Scientific Industrial Co. Topkick-1281P2";
compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood";
memory {
^ permalink raw reply
* [PATCH fpga 8/9] fpga socfpga: Use the scatterlist interface
From: atull @ 2016-11-17 20:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.20.1611171350590.4425@atull-VirtualBox2>
On Thu, 17 Nov 2016, atull wrote:
> On Wed, 16 Nov 2016, Jason Gunthorpe wrote:
>
> > On Wed, Nov 16, 2016 at 09:45:23AM -0600, atull wrote:
> > > > What is the point of this if write_init gets a copy of the buffer -
> > > > what is that supposed to be?
> > >
> > > Sometimes write_init needs to look at the header of the image.
> > > You can see that in the socfpga-a10.c (on linux-next/master)
> >
> > I know what it is for, I'm asking what should it be if we are calling
> > write_init multiple times.
> >
> > It feels like the driver needs to indicate the header length it wants
> > to inspect and the core core needs to make that much of the bitstream
> > available to write_init() before calling write().
> >
> > Is that what you were thinking?
>
> That would make sense. socfpga-a10.c requires a certain amount
> of header in write_init, but the current API didn't have a way
> for socfgpa-a10.c to specify that to fpga-mgr.c core. Should
> probably happen during registration. If you have an idea about
> that, that's good, otherwise we'll get back to that separately.
>
> >
> > > at this stuff, this is coming at a busy time). My point there
> > > was that there was code that needed to go into the core so that
> > > the ICE40 and the cyclone spi driver that are on the mailing
> > > list won't have to have the same workaround that you were
> > > adding to the socfpga.c driver.
> >
> > Sure, that is easy for write() - not clear on write_init sematics?
> > I will send a revised series.
> >
> > I'd also like to close on the zynq bitfile verification patch, did you
> > have any comments on that?
>
> I think Joshua had some comments. Besides that, I'm ok with that
> patch.
>
> Alan
I didn't have any other specific issues with on the other
zynq patches.
For the sg patches, I don't have anything more to say
that I haven't already said.
I want to keep open the possibility of streaming an FPGA image
in. In this case the FPGA image is not complete in memory
and write() will be called multiple times. One case is where
maybe hopefully the firmware layer can be extended to not
allocate a large buffer (scattered or contiguous) and can
stream in the image.
If you have a nice way to move the workarounds that you had
to add to socfpga.c into the core so they don't replicated
in socfpga-a10.c, ICE40, cyclone5 spi and other new drivers
that aren't using sg natively, that would be good.
I think I've already said all this before so please figure
that into he your v2 when you rebase onto linux-next.
Alan
>
> >
> > Jason
> >
>
^ permalink raw reply
* [PATCH] ARM: dts: sunxi: Explicitly enable pull-ups for MMC pins
From: Maxime Ripard @ 2016-11-17 20:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117093438.17988-1-wens@csie.org>
On Thu, Nov 17, 2016 at 05:34:38PM +0800, Chen-Yu Tsai wrote:
> In the past, all the MMC pins had
>
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>
> which was actually a no-op. We were relying on U-boot to set the bias
> pull up for us. These properties were removed as part of the fix up to
> actually support no bias on the pins. During the transition some boards
> experienced regular MMC time-outs during normal operation, while others
> completely failed to initialize the SD card.
>
> Given that MMC starts in open-drain mode and the pull-ups are required,
> it's best to enable it for all the pin settings.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH] ARM: dts: sunxi: Explicitly enable pull-ups for MMC pins
From: klaus.goger at theobroma-systems.com @ 2016-11-17 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117093438.17988-1-wens@csie.org>
On 2016-11-17 10:34, Chen-Yu Tsai wrote:
> Given that MMC starts in open-drain mode and the pull-ups are required,
> it's best to enable it for all the pin settings.
It's even more complicated than that with MMC. It starts in open-drain
mode for
CMD during initialization but changes to push-pull afterwards. The card
has
internal pull-ups to prevent bus floating during setup and will disable
them
after switching to 4bit mode (or 8bit for eMMC when available).
But even after switching to push-pull drivers there are states the bus
would
float and pull ups have to ensure a high level on the bus.
See JESD84-A441 chapter 7.15 ff as reference.
The difference between the P-bit and Z-bit is that a P-bit is actively
driven
to HIGH by the card respectively host output driver, while Z-bit is
driven to
(respectively kept) HIGH by the pull-up resistors Rcmd respectively
Rdat.
Enabling the pull ups on the CPU would be the right choice considering
that
most boards will not have external pull-ups. Even if they would have
one,
adding the internal in parallel would work in almost all cases and the
increase in power consumption would be negligible.
Cheers,
Klaus
^ permalink raw reply
* [PATCH] kirkwood: fix spelling mistake
From: Andrew Lunn @ 2016-11-17 21:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <trinity-6911950b-e19a-4b44-aeed-adaccbc33164-1479414587776@3capp-gmx-bs50>
On Thu, Nov 17, 2016 at 09:29:47PM +0100, p.wassi at gmx.at wrote:
> From: Paul Wassi <p.wassi@gmx.at>
>
> Fix a spelling mistake in arch/arm/boot/dts/kirkwood-topkick.dts
>
> Signed-off-by: Paul Wassi <p.wassi@gmx.at>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Thanks
Andrew
^ permalink raw reply
* [PATCH] kirkwood: fix spelling mistake
From: Andrew Lunn @ 2016-11-17 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <trinity-6911950b-e19a-4b44-aeed-adaccbc33164-1479414587776@3capp-gmx-bs50>
On Thu, Nov 17, 2016 at 09:29:47PM +0100, p.wassi at gmx.at wrote:
> From: Paul Wassi <p.wassi@gmx.at>
Hi Paul
You should also send the patch to the Marvell MVEBU
maintainers. Otherwise it can fall through the cracks.
Andrew
^ permalink raw reply
* [PATCH 1/1] drivers: dma-contiguous: Ensure cma reserve region never cross the low/high mem boundary
From: Laura Abbott @ 2016-11-17 21:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <VI1PR04MB1136F319039F61FECA4DCD11AEB10@VI1PR04MB1136.eurprd04.prod.outlook.com>
On 11/16/2016 09:21 PM, Jason Liu wrote:
>
>
>> -----Original Message-----
>> From: Laura Abbott [mailto:labbott at redhat.com]
>> Sent: Thursday, November 17, 2016 4:00 AM
>> To: Jason Liu <jason.hui.liu@nxp.com>; linux-arm-kernel at lists.infradead.org
>> Cc: gregkh at linuxfoundation.org; iamjoonsoo.kim at lge.com; linux-
>> kernel at vger.kernel.org; m.szyprowski at samsung.com
>> Subject: Re: [PATCH 1/1] drivers: dma-contiguous: Ensure cma reserve region
>> never cross the low/high mem boundary
>>
>> On 11/16/2016 06:19 AM, Jason Liu wrote:
>>> If the cma reserve region goes through the device-tree method, also
>>> need ensure the cma reserved region not cross the low/high mem
>>> boundary. This patch did the similar fix as commit:16195dd
>>> ("mm: cma: Ensure that reservations never cross the low/high mem
>>> boundary")
>>>
>>> Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
>>> Cc: Marek Szyprowski <m.szyprowski@samsung.com>
>>> Cc: Joonsoo Kim <iamjoonsoo.kim@lge.com>
>>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>>> ---
>>> drivers/base/dma-contiguous.c | 27 +++++++++++++++++++++++++++
>>> 1 file changed, 27 insertions(+)
>>>
>>> diff --git a/drivers/base/dma-contiguous.c
>>> b/drivers/base/dma-contiguous.c index e167a1e1..2bc093c 100644
>>> --- a/drivers/base/dma-contiguous.c
>>> +++ b/drivers/base/dma-contiguous.c
>>> @@ -244,6 +244,7 @@ static int __init rmem_cma_setup(struct
>>> reserved_mem *rmem) {
>>> phys_addr_t align = PAGE_SIZE << max(MAX_ORDER - 1,
>> pageblock_order);
>>> phys_addr_t mask = align - 1;
>>> + phys_addr_t highmem_start;
>>> unsigned long node = rmem->fdt_node;
>>> struct cma *cma;
>>> int err;
>>> @@ -256,6 +257,32 @@ static int __init rmem_cma_setup(struct
>> reserved_mem *rmem)
>>> pr_err("Reserved memory: incorrect alignment of CMA
>> region\n");
>>> return -EINVAL;
>>> }
>>> +#ifdef CONFIG_X86
>>> + /*
>>> + * high_memory isn't direct mapped memory so retrieving its physical
>>> + * address isn't appropriate. But it would be useful to check the
>>> + * physical address of the highmem boundary so it's justfiable to get
>>> + * the physical address from it. On x86 there is a validation check for
>>> + * this case, so the following workaround is needed to avoid it.
>>> + */
>>> + highmem_start = __pa_nodebug(high_memory); #else
>>> + highmem_start = __pa(high_memory);
>>> +#endif
>>
>> The inline #ifdef is not great style, we shouldn't be spreading it around.
>
> This is the similar fix in the 16195dd ("mm: cma: Ensure that reservations never cross
> the low/high mem boundary". Do you have a better idea for this?
>
See an example in https://marc.info/?l=linux-kernel&m=147812049024611&w=2
this is getting cleaned up as part of some work I'm doing for CONFIG_DEBUG_VIRTUAL
>>
>>> +
>>> + /*
>>> + * All pages in the reserved area must come from the same zone.
>>> + * If the reserved region crosses the low/high memory boundary,
>>> + * try to fix it up and then fall back to allocate from the low mem
>>> + */
>>> + if (rmem->base < highmem_start &&
>>> + (rmem->base + rmem->size) > highmem_start) {
>>> + memblock_free(rmem->base, rmem->size);
>>> + rmem->base = memblock_alloc_range(rmem->size, align, 0,
>>> + highmem_start,
>> MEMBLOCK_NONE);
>>> + if (!rmem->base)
>>> + return -ENOMEM;
>>> + }
>>
>> Given the alloc happened in the of code, it seems bad form to be bringing the
>> free and re-alloc here. Perhaps we should be doing the limiting and checking in
>> the reserved mem code?
>
> I original though to fix it into the drivers/of/of_reserved_mem.c, but hesitate to
> do it due to this of_reserved_mem is common code to do the reservation, which
> is something not related with CMA requirement.
>
Agreed this case is CMA specific. It might be worth discussion whether allowing
reservation across zones is even something that should be allowed by the generic
code though.
> Appreciated that anyone can provide comments to improve this solution. Without this,
> the Linux kernel will not boot up when do the CMA reservation from the DTS method,
> since the dma_alloc_coherent will fail when do the dma memory allocation.
>
I'd suggest bringing this up on the devicetree mailing list. If you get a negative
or no response there this approach can be reviewed some more.
Thanks,
Laura
^ permalink raw reply
* ILP32 for ARM64: testing with glibc testsuite
From: Steve Ellcey @ 2016-11-17 21:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CC4F99A7-1FD2-486A-BD66-ED06F1B8BF50@linaro.org>
On Wed, 2016-11-16 at 15:22 +0400, Maxim Kuvyrkov wrote:
> >
> > On Nov 9, 2016, at 1:56 PM, Yury Norov <ynorov@caviumnetworks.com>
> > wrote:
> >
> > >
> > > Below is the results of glibc testsuite run for aarch64/lp64
I have been running the glibc testsuite as well. ?I have only run it on
an ILP32 enabled kernel. ?Using that kernel, top-of-tree glibc, and the
ILP32 glibc patches I have no LP64 regressions. ?There are 5 failures
in LP64 mode but I get them with vanilla top-of-tree glibc sources too.
They are:
nptl/eintr1 (I actually don't run this because it kills the 'make check')
debug/tst-backtrace5
debug/tst-backtrace6
nptl/tst-stack4
nptl/tst-thread_local1
In ILP32 mode I get 33 failures, they include the above failures (minus
nptl/tst-thread_local1) plus:
c++-types-check
conform/ISO11/inttypes.h/conform
conform/ISO11/stdint.h/conform
conform/ISO99/inttypes.h/conform
conform/ISO99/stdint.h/conform
conform/POSIX2008/inttypes.h/conform
conform/POSIX2008/stdint.h/conform
conform/XOPEN2K/inttypes.h/conform
conform/XOPEN2K/stdint.h/conform
conform/XOPEN2K8/inttypes.h/conform
conform/XOPEN2K8/stdint.h/conform
elf/tst-tls1
elf/tst-tls1-static
elf/tst-tls2
elf/tst-tls2-static
elf/tst-tls3
math/check-abi-libm
math/test-double
math/test-double-finite
math/test-float
math/test-float-finite
misc/tst-sync_file_range
nptl/tst-cancel26
nptl/tst-cancel27
nptl/tst-sem3
rt/tst-mqueue1
rt/tst-mqueue2
rt/tst-mqueue4
rt/tst-mqueue7
stdlib/tst-makecontext3
I am currently looking at these ILP32 regressions (starting with the
tls failures) to see if I can figure out what is happening with them.
Steve Ellcey
sellcey at caviumnetworks.com
^ permalink raw reply
* [PATCH net 1/3] net: phy: realtek: add eee advertisement disable options
From: Jerome Brunet @ 2016-11-17 21:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANAwSgTB5=8tVj1FrZF3EgjK5mjUMwLYb90NeWSFDCsRjsuB6A@mail.gmail.com>
On Thu, 2016-11-17 at 23:30 +0530, Anand Moon wrote:
> Hi Jerone,
>
> > > How about adding callback functionality for .soft_reset to handle
> > > BMCR
> > > where we update the Auto-Negotiation for the phy,
> > > as per the datasheet of the rtl8211f.
I think BMCR is already pretty well handled by the genphy, don't you
think ?
> >
> > I'm not sure I understand how this would help with our issue (and
> > EEE).
> > Am I missing something or is it something unrelated that you would
> > like
> > to see happening on this driver ?
> >
> [snip]
>
> I was just tying other phy module to understand the feature.
> But in order to improve??the throughput I tried to integrate blow u-
> boot commit.
>
> commit 3d6af748ebd831524cb22a29433e9092af469ec7
> Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> Date:???Thu Mar 12 18:54:59 2015 +0800
>
> ????net/phy: Add support for realtek RTL8211F
>
> ????RTL8211F has different registers from RTL8211E.
> ????This patch adds support for RTL8211F PHY which
> ????can be found on Freescale's T1023 RDB board.
>
> And added the similar functionality to??.config_aneg????=
> &rtl8211f_config_aneg,
>
I assume this is the commit you are referring to :?
http://git.denx.de/?p=u-boot.git;a=commit;h=3d6af748ebd831524cb22a29433
e9092af469ec7
I tried looking a this particular commit and the other ones in
realtek.c history of u-boot. I don't really see what it does that linux
is not already doing.
> And I seem to have better results in through put with periodic drop
> but it recovers.
> -----
> odroid at odroid64:~$ iperf3 -c 10.0.0.102 -p 2006 -i 1 -t 100 -V
> iperf 3.0.11
> Linux odroid64 4.9.0-rc5-xc2ml #18 SMP PREEMPT Thu Nov 17 22:56:00
[...]
>
> Test Complete. Summary Results:
> [ ID] Interval???????????Transfer?????Bandwidth???????Retr
> [??4]???0.00-100.00 sec??10.5 GBytes???902
> Mbits/sec????4?????????????sender
> [??4]???0.00-100.00 sec??10.5 GBytes???902
> Mbits/sec??????????????????receiver
> CPU Utilization: local/sender 5.6% (0.2%u/5.4%s), remote/receiver
> 17.1% (1.2%u/15.9%s)
>
That's the kind of throughput we have on the C2 once the link is
reliable (with EEE switch off for GbE)
> Can your confirm this at your end.
> Once confirm I will try to send this as a fix for this issue.
>
I'm testing the code to disable EEE in a generic way. I'll post the RFC
for it asap.
> -Best Regards
> Anand Moon
^ permalink raw reply
* [GIT PULL] ARM: mvebu: drivers for v4.10 (#1)
From: Gregory CLEMENT @ 2016-11-17 21:49 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here is the first pull request for drivers for mvebu for v4.10.
Gregory
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-drivers-4.10-1
for you to fetch changes up to d6ea689345ecc27b636a8bb62bf07080f21f110c:
ARM/orion/gpio: Replace three seq_printf() calls by seq_puts() in orion_gpio_dbg_show() (2016-10-17 17:40:24 +0200)
----------------------------------------------------------------
mvebu drivers for 4.10 (part 1)
Clean-up on thegpio driver for old SoCs(non DT)
----------------------------------------------------------------
Markus Elfring (1):
ARM/orion/gpio: Replace three seq_printf() calls by seq_puts() in orion_gpio_dbg_show()
arch/arm/plat-orion/gpio.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt for v4.10 (#1)
From: Gregory CLEMENT @ 2016-11-17 21:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here is the first pull request for dt for mvebu for v4.10.
I hope being able to send a second part very soon with the series
removing all the DT warning.
Gregory
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-dt-4.10-1
for you to fetch changes up to cf20c489de6fcef88405d4febef7a078d2053b9e:
ARM: dt: orion5x: convert ls-chl to FDT (2016-11-07 17:23:34 +0100)
----------------------------------------------------------------
mvebu fixes for 4.10 (part 1)
Most of the commit are pinmux and i2c fix for netgear NASes
Fix on a wrong comment about PLL frequency
Bigger commit: conversion of on otion5x based board to the device tree
----------------------------------------------------------------
Ashley Hughes (1):
ARM: dt: orion5x: convert ls-chl to FDT
Chris Packham (1):
ARM: dts: mvebu: Update comment for main PLL frequency
Uwe Kleine-K?nig (6):
ARM: dts: armada-370-rn104: add pinmuxing for i2c0
ARM: dts: armada-370-rn104: drop specification of compatible for i2c0
ARM: dts: armada-xp-rn2120: drop wrong compatible for i2c0
ARM: dts: armada-xp-rn2120: add pinmuxing for ethernet
ARM: dts: armada-370-rn102: drop specification of compatible for i2c0
ARM: dts: armada-370-rn102: add pinmuxing for i2c0
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 5 +-
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 5 +-
arch/arm/boot/dts/armada-375.dtsi | 2 +-
arch/arm/boot/dts/armada-38x.dtsi | 2 +-
arch/arm/boot/dts/armada-39x.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 7 +-
arch/arm/boot/dts/orion5x-lschl.dts | 171 +++++++++++++
arch/arm/mach-orion5x/Kconfig | 4 +-
arch/arm/mach-orion5x/Makefile | 1 -
arch/arm/mach-orion5x/ls-chl-setup.c | 331 -------------------------
11 files changed, 191 insertions(+), 340 deletions(-)
create mode 100644 arch/arm/boot/dts/orion5x-lschl.dts
delete mode 100644 arch/arm/mach-orion5x/ls-chl-setup.c
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt64 for v4.10 (#1)
From: Gregory CLEMENT @ 2016-11-17 21:51 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here is the first pull request for dt64 for mvebu for v4.10.
Here again, I hope being able to send a second part very soon with the
series removing all the remaining DT warning.
Gregory
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-dt64-4.10-1
for you to fetch changes up to e735aaf8fc4ac84dbdb3642a135da8dcdb84587b:
arm64: dts: marvell: Add definition for the Globalscale Marvell ESPRESSOBin Board (2016-10-17 17:19:56 +0200)
----------------------------------------------------------------
mvebu dt64 for 4.10 (part 1)
Adding the new "community" board for Armada 3700
----------------------------------------------------------------
Romain Perier (1):
arm64: dts: marvell: Add definition for the Globalscale Marvell ESPRESSOBin Board
arch/arm64/boot/dts/marvell/Makefile | 1 +
.../boot/dts/marvell/armada-3720-espressobin.dts | 82 ++++++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
^ permalink raw reply
* [v4, 1/3] i2c: pxa: Add support for the I2C units found in Armada 3700
From: Wolfram Sang @ 2016-11-17 21:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161109115715.2557-2-romain.perier@free-electrons.com>
> + [REGS_A3700] = {
> + .ibmr = 0x00,
> + .idbr = 0x04,
> + .icr = 0x08,
> + .isr = 0x0c,
> + .isar = 0x10,
> + },
Can't you reuse REGS_PXA3XX?
> static const struct platform_device_id i2c_pxa_id_table[] = {
> @@ -98,6 +106,7 @@ static const struct platform_device_id i2c_pxa_id_table[] = {
> { "pxa3xx-pwri2c", REGS_PXA3XX },
> { "ce4100-i2c", REGS_CE4100 },
> { "pxa910-i2c", REGS_PXA910 },
> + { "armada-3700-i2c", REGS_A3700 },
So, you declare a platform_device_id here...
> + if (of_device_is_compatible(np, "marvell,armada-3700-i2c")) {
> + i2c->fm_mask = ICR_BUSMODE_FM;
> + i2c->hs_mask = ICR_BUSMODE_HS;
> + } else {
> + i2c->fm_mask = ICR_FM;
> + i2c->hs_mask = ICR_HS;
> + }
... but don't consider this case here?
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^ permalink raw reply
* LEDs that change brightness "itself" -- that's a trigger. Re: PM regression with LED changes in next-20161109
From: Hans de Goede @ 2016-11-17 22:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <aeccbb02-6e33-390c-d72d-2a580dd67ed8@redhat.com>
Hi,
On 15-11-16 13:06, Hans de Goede wrote:
> Hi,
>
> On 15-11-16 12:48, Pavel Machek wrote:
>> Hi!
>>
>>>>>> The LED you are talking about _has_ a trigger, implemented in
>>>>>> hardware. That trigger can change LED brightness behind kernel's (and
>>>>>> userspace's) back. Don't pretend the trigger does not exist, it does.
>>>>>>
>>>>>> And when you do that, you'll have nice place to report changes to
>>>>>> userspace -- trigger can now export that information, and offer poll()
>>>>>> interface.
>>>>>
>>>>> Well, that sounds interesting. It is logically justifiable.
>>>>
>>>> Thanks.
>>>>
>>>>> I initially proposed exactly this solution, with recently
>>>>> added userspace LED being a trigger listener. It seems a bit
>>>>> awkward though. How would you listen to the trigger events?
>>>>
>>>> Trigger exposes a file in sysfs, with poll() working on that file
>>>
>>> Hmm, a new file would give the advantage of making it easy for
>>> userspace to see if the trigger is poll-able, this is likely
>>> better then my own proposal I just send.
>>
>> Good.
>>
>>>> (and
>>>> probably read exposing the current brightness).
>>>
>>> If we do this, can we please make it mirror brightness, iow
>>> also make it writable, that will make it easier for userspace
>>> to deal with it. We can simply re-use the existing show / store
>>> methods for brightness for this.
>>
>> Actually, echo 0 > brightness disables the trigger, IIRC. I'd avoid
>> that here, you want to be able to turn off the backlight but still
>> keep the trigger (and be notified of future changes).
>
> True, that is easy to do the store method will just need to call
> led_set_brightness_nosleep instead of led_set_brightness, this
> will skip the checks to stop blinking in led_set_brightness and
> otherwise is equivalent.
>
>>> I suggest we call it:
>>>
>>> trigger_brightness
>>>
>>> And only register it when a poll-able trigger is present.
>>
>> I'd call it 'current_brightness', but that's no big deal. Yes, only
>> registering it for poll-able triggers makes sense.
>
> current_brightness works for me. I will take a shot a patch-set
> implementing this.
Done, this actually turned out pretty nice, the trigger also helps
in propagating the change events from dell-wmi to the led-classdev
in dell-laptop without needing the ugly hacks I needed before.
v5 coming up.
Regards,
Hans
>
>
>
>>
>>>> Key difference is that only triggers where this makes sense (keyboard
>>>> backlight) expose it and carry the overhead. CPU trigger would
>>>> definitely not do this.
>>>
>>> Ack only having some triggers pollable is important.
>>
>> Thanks,
>> Pavel
>>
^ permalink raw reply
* [PATCH] ARM: dts: qcom: Add apq8064 CoreSight components
From: Stephen Boyd @ 2016-11-17 22:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161117153609.11705-1-georgi.djakov@linaro.org>
On 11/17/2016 07:36 AM, Georgi Djakov wrote:
> From: "Ivan T. Ivanov" <ivan.ivanov@linaro.org>
>
> Add initial set of CoreSight components found on Qualcomm's
> 8064 chipset.
>
> Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
> arch/arm/boot/dts/qcom-apq8064-coresight.dtsi | 196 ++++++++++++++++++++++++++
Why not put this inside the soc file? This would be the first time we
add a new file for something that's inside the SoC node that probably
won't change thereafter. At least for pins I slightly agree with having
a different file, we're adding more and more things there so it's nice
to have a consolidated place of all possible configurations to choose
from. But here it's mostly a static device description so what's the gain?
--
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a Linux Foundation Collaborative Project
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