* [PATCH 5/7] add bindings for stm32 IIO timer drivers
From: Benjamin Gaignard @ 2016-11-23 8:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122171820.GL10134@dell.home>
If it is ok for you I will add "id" parameter in mfd driver and
forward it to the sub-devices drivers
to be able to distinguish the hardware blocks
2016-11-22 18:18 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
>
>> [snip]
>> >> + "st,stm32-iio-timer5"
>> >> + "st,stm32-iio-timer6"
>> >> + "st,stm32-iio-timer7"
>> >> + "st,stm32-iio-timer8"
>> >> + "st,stm32-iio-timer9"
>> >> + "st,stm32-iio-timer10"
>> >> + "st,stm32-iio-timer11"
>> >> + "st,stm32-iio-timer12"
>> >> + "st,stm32-iio-timer13"
>> >> + "st,stm32-iio-timer14"
>> >
>> > We can't do this. This is a binding for a driver, not for the hardware.
>> >
>>
>> Unfortunately each instance for the hardware IP have little
>> differences like which triggers they could accept or size of the
>> counter register,
>> and I doesn't have value inside the hardware to distinguish them so
>> the only way I found is to use compatible.
>
> Can't you represent these as properties?
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org ? Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
--
Benjamin Gaignard
Graphic Study Group
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 2/2] arm64: Pass RAM boundary and enable-dcache flag to purgatory
From: Pratyush Anand @ 2016-11-23 8:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123080816.GA30255@verge.net.au>
Hi Simon,
Thanks for your review comment.
On Wed, Nov 23, 2016 at 1:38 PM, Simon Horman <horms@verge.net.au> wrote:
> On Wed, Nov 23, 2016 at 07:41:52AM +0530, Pratyush Anand wrote:
>>
>>
>> On Wednesday 23 November 2016 07:33 AM, Dave Young wrote:
>> >>Although this is very unlikely that a hardware will support only 16K page
>> >>> sizes, however it is possible. Therefore, its better to keep it disabled by
>> >>> default.
>> >If it is *unlikely* it could be better to make it as default and add a
>> >--disable-dcache instead.
>> >
>>
>> I think, I can do that.
>
> Can this be detected at run-time?
Thats doable. OK, so if everyone agrees then I can send a V2 where
neither --enable-dcache nor --disable-dcache will be used. It will
enable dcache if 4K/64K page is supported and will do nothing
otherwise.
~Pratyush
^ permalink raw reply
* [PATCH 1/7] add binding for stm32 multifunctions timer driver
From: Benjamin Gaignard @ 2016-11-23 8:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122165228.GK10134@dell.home>
2016-11-22 17:52 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
>
>> Add bindings information for stm32 timer MFD
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> .../devicetree/bindings/mfd/stm32-timer.txt | 53 ++++++++++++++++++++++
>> 1 file changed, 53 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timer.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/stm32-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-timer.txt
>> new file mode 100644
>> index 0000000..3cefce1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/stm32-timer.txt
>> @@ -0,0 +1,53 @@
>> +STM32 multifunctions timer driver
>
> "STM32 Multi-Function Timer/PWM device bindings"
>
> Doesn't this shared device have a better name?
In SoC documentation those hardware blocks are named "advanced-control
timers", "general purpose timers" or "basic timers"
"stm32-timer" name is already used for clock source driver, that why I
have prefix it with mfd
>
>> +stm32 timer MFD allow to handle at the same time pwm and IIO timer devices
>
> No need for this sentence.
>
OK
>> +Required parameters:
>> +- compatible: must be one of the follow value:
>> + "st,stm32-mfd-timer1"
>> + "st,stm32-mfd-timer2"
>> + "st,stm32-mfd-timer3"
>> + "st,stm32-mfd-timer4"
>> + "st,stm32-mfd-timer5"
>> + "st,stm32-mfd-timer6"
>> + "st,stm32-mfd-timer7"
>> + "st,stm32-mfd-timer8"
>> + "st,stm32-mfd-timer9"
>> + "st,stm32-mfd-timer10"
>> + "st,stm32-mfd-timer11"
>> + "st,stm32-mfd-timer12"
>> + "st,stm32-mfd-timer13"
>> + "st,stm32-mfd-timer14"
>
> We don't normally number devices.
>
> What's stopping you from simply doing:
>
> pwm1: pwm1 at 40010000 {
> compatible = "st,stm32-pwm";
> };
> pwm2: pwm1 at 40020000 {
> compatible = "st,stm32-pwm";
> };
> pwm3: pwm1 at 40030000 {
> compatible = "st,stm32-pwm";
> };
>
Because each instance of the hardware is slightly different: number of
pwm channels, triggers capabilities, etc ..
so I need to distinguish them.
Since it look to be a problem I will follow your suggestion and add a
property this driver to be able to identify each instance.
Do you think that "id" parameter (integer for 1 to 14) is acceptable ?
>> +- reg : Physical base address and length of the controller's
>> + registers.
>> +- clock-names: Set to "mfd_timer_clk".
>
Only one but I use devm_regmap_init_mmio_clk() to avoid calling
clk_{enable/disable}
everywhere in the drivers when reading/writing regsister.
devm_regmap_init_mmio_clk() find the clock by it name that why I have
put it here
In the doc this clock in named "clk_int" I will use this name.
> How many clocks are there?
>
> If only 1, you don't need this property.
>
> "mfd_timer_clk" is not the correct name.
>
> What is it called in the datasheet?
>
>> +- clocks: Phandle of the clock used by the timer module.
>
> "Phandle to the clock ..."
>
>> + For Clk properties, please refer to [1].
>> +- interrupts : Reference to the timer interrupt
>
> Reference to?
>
> See how other binding documents describe this property.
>
>> +Optional parameters:
>> +- resets : Reference to a reset controller asserting the timer
>
> As above.
>
>> +Optional subnodes:
>
> Either use ":" or " :" or "<tab>:", but keep it consistent.
>
>> +- pwm: See Documentation/devicetree/bindings/pwm/pwm-stm32.txt
>> +- iiotimer: See Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>
> Use the relative paths "../clock/", "../pwm/", "../iio/".
>
OK
>> +Example:
>> + mfd_timer1: mfdtimer1 at 40010000 {
>
> This is not an "MFD timer". MFD is a Linuxisum.
>
>> + compatible = "st,stm32-mfd-timer1";
>
> Better description required.
>
>> + reg = <0x40010000 0x400>;
>> + clocks = <&rcc 0 160>;
>> + clock-names = "mfd_timer_clk";
>> + interrupts = <27>;
>> +
>> + pwm1: pwm1 at 40010000 {
>> + compatible = "st,stm32-pwm1";
>> + };
>> +
>> + iiotimer1: iiotimer1 at 40010000 {
>> + compatible = "st,stm32-iio-timer1";
>> + };
>> + };
^ permalink raw reply
* [PATCH v2 1/3] arm64: dts: add USB1-related nodes of Allwinner A64
From: Maxime Ripard @ 2016-11-23 8:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122155831.8724-1-icenowy@aosc.xyz>
On Tue, Nov 22, 2016 at 11:58:29PM +0800, Icenowy Zheng wrote:
> Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
> PHY device which have two ports. One of the port is wired to both a HCI
> USB controller and the OTG controller, which is currently not supported.
> The another one is only wired to a HCI controller, and the device node of
> OHCI/EHCI controller of the port can be added now.
>
> Also the A64 USB PHY device node is also added for the HCI controllers to
> work.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes since v1:
> - Remove manual CLK_USB_OHCI0 gate, as it's dealed by ccu driver now.
> - Sort the nodes and fixed {e,o}hci1 regs.
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 44 +++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 3d70be3..2572dd6 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -122,6 +122,50 @@
> #size-cells = <1>;
> ranges;
>
> + usbphy: phy at 01c19400 {
> + compatible = "allwinner,sun50i-a64-usb-phy";
> + reg = <0x01c19400 0x14>,
> + <0x01c1b800 0x4>;
> + reg-names = "phy_ctrl",
> + "pmu1";
> + clocks = <&ccu CLK_USB_PHY0>,
> + <&ccu CLK_USB_PHY1>;
> + clock-names = "usb0_phy",
> + "usb1_phy";
> + resets = <&ccu RST_USB_PHY0>,
> + <&ccu RST_USB_PHY1>;
> + reset-names = "usb0_reset",
> + "usb1_reset";
> + status = "disabled";
> + #phy-cells = <1>;
> + };
> +
> + ohci1: usb at 01c1b400 {
> + compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
> + reg = <0x01c1b400 0x100>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci1: usb at 01c1b000 {
> + compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
> + reg = <0x01c1b000 0x100>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_BUS_EHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>,
> + <&ccu RST_BUS_EHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
The nodes were inverted, also, please use "arm64: dts: allwinner:" for
your prefix in the future.
I fixed both issues and queued for 4.11.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 2/2] arm64: Pass RAM boundary and enable-dcache flag to purgatory
From: Simon Horman @ 2016-11-23 8:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <81975e6e-b97a-0401-0e18-b2d26722c1dd@redhat.com>
On Wed, Nov 23, 2016 at 07:41:52AM +0530, Pratyush Anand wrote:
>
>
> On Wednesday 23 November 2016 07:33 AM, Dave Young wrote:
> >>Although this is very unlikely that a hardware will support only 16K page
> >>> sizes, however it is possible. Therefore, its better to keep it disabled by
> >>> default.
> >If it is *unlikely* it could be better to make it as default and add a
> >--disable-dcache instead.
> >
>
> I think, I can do that.
Can this be detected at run-time?
It sounds like it will be painful if on some setups the default
doesn't work.
^ permalink raw reply
* [RFC V2: PATCH 2/2] reset: hisilicon: add reset-hi3660
From: Zhangfei Gao @ 2016-11-23 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479888476-13138-1-git-send-email-zhangfei.gao@linaro.org>
Add hi3660 reset driver
Reset offset & bits should be listed in dts
Like:
iomcu_rst: iomcu_rst_controller {
compatible = "hisilicon,hi3660-reset";
#reset-cells = <1>;
hisi,rst-syscon = <&iomcu>;
hisi,reset-bits = <0x20 0x8 /* 0: i2c0 */
0x20 0x10 /* 1: i2c1 */
0x20 0x20 /* 2: i2c2 */
0x20 0x8000000>; /* 3: i2c6 */
};
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/reset/hisilicon/Kconfig | 7 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/reset-hi3660.c | 144 +++++++++++++++++++++++++++++++++
3 files changed, 152 insertions(+)
create mode 100644 drivers/reset/hisilicon/reset-hi3660.c
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
index 1ff8b0c..10134dc 100644
--- a/drivers/reset/hisilicon/Kconfig
+++ b/drivers/reset/hisilicon/Kconfig
@@ -1,3 +1,10 @@
+config COMMON_RESET_HI3660
+ tristate "Hi3660 Reset Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi3660 reset driver.
+
config COMMON_RESET_HI6220
tristate "Hi6220 Reset Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
index c932f86..ab8a7bf 100644
--- a/drivers/reset/hisilicon/Makefile
+++ b/drivers/reset/hisilicon/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
+obj-$(CONFIG_COMMON_RESET_HI3660) += reset-hi3660.o
diff --git a/drivers/reset/hisilicon/reset-hi3660.c b/drivers/reset/hisilicon/reset-hi3660.c
new file mode 100644
index 0000000..3307252
--- /dev/null
+++ b/drivers/reset/hisilicon/reset-hi3660.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+struct hi3660_reset_data {
+ unsigned int off;
+ unsigned int bits;
+};
+
+struct hi3660_reset_controller {
+ struct reset_controller_dev rst;
+ struct regmap *map;
+ const struct hi3660_reset_data *datas;
+};
+
+#define to_hi3660_reset_controller(_rst) \
+ container_of(_rst, struct hi3660_reset_controller, rst)
+
+static int hi3660_reset_program_hw(struct reset_controller_dev *rcdev,
+ unsigned long idx, bool assert)
+{
+ struct hi3660_reset_controller *rc = to_hi3660_reset_controller(rcdev);
+ const struct hi3660_reset_data *d;
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ d = &rc->datas[idx];
+
+ if (assert)
+ return regmap_write(rc->map, d->off, d->bits);
+ else
+ return regmap_write(rc->map, d->off + 4, d->bits);
+}
+
+static int hi3660_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return hi3660_reset_program_hw(rcdev, idx, true);
+}
+
+static int hi3660_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return hi3660_reset_program_hw(rcdev, idx, false);
+}
+
+static int hi3660_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ int err;
+
+ err = hi3660_reset_assert(rcdev, idx);
+ if (err)
+ return err;
+
+ return hi3660_reset_deassert(rcdev, idx);
+}
+
+static struct reset_control_ops hi3660_reset_ops = {
+ .reset = hi3660_reset_dev,
+ .assert = hi3660_reset_assert,
+ .deassert = hi3660_reset_deassert,
+};
+
+static int hi3660_reset_probe(struct platform_device *pdev)
+{
+ struct hi3660_reset_controller *rc;
+ struct device_node *np = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct hi3660_reset_data *datas;
+ const __be32 *list;
+ int size, nr, i;
+
+ rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
+ if (!rc)
+ return -ENOMEM;
+
+ rc->map = syscon_regmap_lookup_by_phandle(np, "hisi,rst-syscon");
+ if (IS_ERR(rc->map)) {
+ dev_err(dev, "failed to get hi3660,rst-syscon\n");
+ return PTR_ERR(rc->map);
+ }
+
+ list = of_get_property(np, "hisi,reset-bits", &size);
+ if (!list || (size / sizeof(*list)) % 2 != 0) {
+ dev_err(dev, "invalid DT reset description\n");
+ return -EINVAL;
+ }
+
+ nr = (size / sizeof(*list)) / 2;
+ datas = devm_kzalloc(dev, nr * sizeof(*datas), GFP_KERNEL);
+ if (!datas)
+ return -ENOMEM;
+
+ for (i = 0; i < nr; i++) {
+ datas[i].off = be32_to_cpup(list++);
+ datas[i].bits = be32_to_cpup(list++);
+ }
+
+ rc->rst.ops = &hi3660_reset_ops,
+ rc->rst.of_node = np;
+ rc->rst.nr_resets = nr;
+ rc->datas = datas;
+
+ return reset_controller_register(&rc->rst);
+}
+
+static const struct of_device_id hi3660_reset_match[] = {
+ { .compatible = "hisilicon,hi3660-reset", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, hi3660_reset_match);
+
+static struct platform_driver hi3660_reset_driver = {
+ .probe = hi3660_reset_probe,
+ .driver = {
+ .name = "hi3660-reset",
+ .of_match_table = hi3660_reset_match,
+ },
+};
+
+static int __init hi3660_reset_init(void)
+{
+ return platform_driver_register(&hi3660_reset_driver);
+}
+arch_initcall(hi3660_reset_init);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:hi3660-reset");
+MODULE_DESCRIPTION("HiSilicon Hi3660 Reset Driver");
--
2.7.4
^ permalink raw reply related
* [RFC v2: PATCH 1/2] dt-bindings: Document the hi3660 reset bindings
From: Zhangfei Gao @ 2016-11-23 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479888476-13138-1-git-send-email-zhangfei.gao@linaro.org>
Add DT bindings documentation for hi3660 SoC reset controller.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
.../bindings/reset/hisilicon,hi3660-reset.txt | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
new file mode 100644
index 0000000..250daf2
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
@@ -0,0 +1,51 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller registers are part of the system-ctl block on
+hi3660 SoC.
+
+Required properties:
+- compatible: should be
+ "hisilicon,hi3660-reset"
+- #reset-cells: 1, see below
+- hisi,rst-syscon: phandle of the reset's syscon.
+- hisi,reset-bits: Contains the reset control register information
+ Should contain 2 cells for each reset exposed to
+ consumers, defined as:
+ Cell #1 : offset from the syscon register base
+ Cell #2 : bits position of the control register
+
+Example:
+ iomcu: iomcu at ffd7e000 {
+ compatible = "hisilicon,hi3660-iomcu", "syscon";
+ reg = <0x0 0xffd7e000 0x0 0x1000>;
+ };
+
+ iomcu_rst: iomcu_rst_controller {
+ compatible = "hisilicon,hi3660-reset";
+ #reset-cells = <1>;
+ hisi,rst-syscon = <&iomcu>;
+ hisi,reset-bits = <0x20 0x8 /* 0: i2c0 */
+ 0x20 0x10 /* 1: i2c1 */
+ 0x20 0x20 /* 2: i2c2 */
+ 0x20 0x8000000>; /* 3: i2c6 */
+ };
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+ i2c0: i2c at ..... {
+ ...
+ resets = <&iomcu_rst 0>;
+ ...
+ };
+
+ i2c1: i2c at ..... {
+ ...
+ resets = <&iomcu_rst 1>;
+ ...
+ };
--
2.7.4
^ permalink raw reply related
* [RFC V2:PATCH 0/2] add reset-hi3660
From: Zhangfei Gao @ 2016-11-23 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <Arnd Bergmann <arnd@arndb.de>
Considering Arnd and Philipp suggestions,
move reset register to dts as table instead of dts header in case of ABI issue
Zhangfei Gao (2):
dt-bindings: Document the hi3660 reset bindings
reset: hisilicon: add reset-hi3660
.../bindings/reset/hisilicon,hi3660-reset.txt | 51 ++++++++
drivers/reset/hisilicon/Kconfig | 7 +
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/reset-hi3660.c | 144 +++++++++++++++++++++
4 files changed, 203 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
create mode 100644 drivers/reset/hisilicon/reset-hi3660.c
--
2.7.4
^ permalink raw reply
* [PATCH] ARM: dts: sunxi: Enable UEXT related nodes for Olimex A20 SOM EVB
From: Maxime Ripard @ 2016-11-23 8:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121164911.76900-1-manu@bidouilliste.com>
On Mon, Nov 21, 2016 at 05:49:11PM +0100, Emmanuel Vadot wrote:
> UEXT are Universal EXTension connector from Olimex. They embed i2c, spi
> and uart pins along power in one connector and are found on most,
> if not all, Olimex boards.
> The Olimex A20 SOM EVB have two UEXT connector so enable the nodes found on
> those two connectors.
>
> Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Fixed the indentation of the spi pinctrl cells, and applied.
Please note that I'm note planning to send any new pull request, so
this will likely end up in 4.11.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* Synopsys Ethernet QoS Driver
From: Giuseppe CAVALLARO @ 2016-11-23 8:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1806171479803900@web16j.yandex.ru>
Hello Ozgur
On 11/22/2016 9:38 AM, Ozgur Karatas wrote:
> Hello all,
>
> I think, ethtool and mdio don't work because the tool's not support to "QoS", right?
>
> Maybe, need a new API. I'm looking for dwceqos code but "tc" tools is very idea.
>
> I hope to be me always helpful.
tools work but indeed should be extended to support more for QoS.
This is another task we have to keep in mind, well spot.
Peppe
>
> Regards,
>
> Ozgur
>
> 21.11.2016, 16:38, "Giuseppe CAVALLARO" <peppe.cavallaro@st.com>:
>> Hello Joao
>>
>> On 11/21/2016 2:48 PM, Joao Pinto wrote:
>>> Synopsys QoS IP is a separated hardware component, so it should be reusable by
>>> all implementations using it and so have its own "core driver" and platform +
>>> pci glue drivers. This is necessary for example in hardware validation, where
>>> you prototype an IP and instantiate its drivers and test it.
>>>
>>> Was there a strong reason to integrate QoS features directly in stmmac and not
>>> in synopsys/dwc_eth_qos.*?
>>
>> We decided to enhance the stmmac on supporting the QoS for several
>> reasons; for example the common APIs that the driver already exposed and
>> actually suitable for other SYNP chips. Then, PTP, EEE,
>> S/RGMII, MMC could be shared among different chips with a minimal
>> effort. This meant a lot of code already ready.
>>
>> For sure, the net-core, Ethtool, mdio parts were reused. Same for the
>> glue logic files.
>> For the latter, this helped to easily bring-up new platforms also
>> because the stmmac uses the HW cap register to auto-configure many
>> parts of the MAC core, DMA and modules. This helped many users, AFAIK.
>>
>> For validation purpose, this is my experience, the stmmac helped
>> a lot because people used the same code to validate different HW
>> and it was easy to switch to a platform to another one in order to
>> verify / check if the support was ok or if a regression was introduced.
>> This is important for complex supports like PTP or EEE.
>>
>> Hoping this can help.
>>
>> Do not hesitate to contact me for further details
>>
>> peppe
>
^ permalink raw reply
* [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: zhangfei @ 2016-11-23 8:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479810156.13701.1.camel@pengutronix.de>
Hi, Philipp
On 2016?11?22? 18:22, Philipp Zabel wrote:
> Am Dienstag, den 22.11.2016, 10:42 +0100 schrieb Arnd Bergmann:
>> On Tuesday, November 22, 2016 5:34:05 PM CET zhangfei wrote:
>>> On 2016?11?22? 16:50, Arnd Bergmann wrote:
>>>> On Tuesday, November 22, 2016 3:49:18 PM CET Zhangfei Gao wrote:
>>>>> +static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
>>>>> + [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
>>>>> + [HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
>>>>> + [HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
>>>>> + [HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
>>>>> +};
>>>>> +
>>>>> +static struct hisi_reset_controller_data hi3660_iomcu_controller = {
>>>>> + .nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
>>>>> + .channels = hi3660_iomcu_rst,
>>>>> +};
>>>>> +
>>>>> +static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
>>>>> + [HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
>>>>> + [HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
>>>>> + [HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
>>>>> + [HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
>>>>> + [HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
>>>>> + [HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
>>>>> + [HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
>>>>> + [HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
>>>>> + [HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
>>>>> + [HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
>>>>> + [HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
>>>>> + [HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
>>>>> + [HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
>>>>> + [HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
>>>>> + [HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
>>>>> +};
>>>> I think you can avoid the trap of the ABI incompatibility if
>>>> you just define those as in the binding as tuples, using #reset-cells=2.
>>>>
>>>> In particular for the first set, it seems really silly to redefine
>>>> the numbers when there is just a simple integer number.
>>> Could you clarify more, still not understand.
>>> The number is index of the arrays, and the index will be used in dts.
>>> The arrays lists the registers offset and bit shift.
>>> For example:
>>>
>>> [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3), means register offset : 0x20, and bit shift = 3.
>>>
>>> And Documentation/devicetree/bindings/reset/reset.txt
>>> Required properties:
>>> #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
>>> with a single reset output and 1 for nodes with multiple
>>> reset outputs.
> This is just a suggestion, for reset controllers where the reset lines
> can reasonably be enumerated by a single integer. If there is a good
> reason to use more complicated bindings, more cells can be used.
> That being said, I dislike having to spread register/bit information
> throughout the device trees at the consumer/phandle sites, if the
> register/bit information absolutely has to be put into the device tree,
> I'd prefer a binding similar to ti-syscon, where it's all in one place.
Thanks for the suggestion.
Will use table in dts instead of
include/dt-bindings/reset/hisi,hi3660-resets.h
like
+ hisi,reset-bits = <0x20 0x8 /* 0: i2c0 */
+ 0x20 0x10 /* 1: i2c1 */
+ 0x20 0x20 /* 2: i2c2 */
+ 0x20 0x8000000>; /* 3: i2c6 */
To remove the potential ABI issue as pointed by Arnd.
>
>> You can easily enumerate the registers that contain reset bits here,
>> so just use one cell for the register and another one for the index.
> Changing the reset cells is an incompatible change, and this is not a
> straight forward register/bit mapping in hardware either. There are
> currently three registers involved: enable (+0x0), disable (+0x4), and
> status (+0x8). Also, what if in the future one of these reset bits have
> to be handled inverted (as just happened for hi3519)?
Discussed with Jianchen, we are only considering Kirin series now.
The inverted in hi3519 is only for some line, not the whole controller.
It is more like a bug and kirin does not have such issue.
Will send a new RFC, help take a look.
Thanks
^ permalink raw reply
* [PATCH 3/3] ARM: dts: sunxi: enable SDIO Wi-Fi on Orange Pi Zero
From: Maxime Ripard @ 2016-11-23 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121162421.800-3-icenowy@aosc.xyz>
Hi,
On Tue, Nov 22, 2016 at 12:24:21AM +0800, Icenowy Zheng wrote:
> There's a Allwinner's XR819 SDIO Wi-Fi module soldered on the board of
> Orange Pi Zero, which used a dedicated regulator to power.
>
> Add the device tree node of the regulator, the enable gpio (with
> mmc-pwrseq) and the sdio controller.
>
> There's a out-of-tree driver tested to work with this device tree.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> New patch in the patchset, since a out-of-tree working xradio driver is done.
>
> If there is any problem in this patch, it can be omitted.
No particular problem with this one, however it can and should be
merged with the previous one.
Minor comments below though.
>
> arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts | 42 ++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> index b428e47..39cac26 100644
> --- a/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> +++ b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> @@ -79,6 +79,24 @@
> gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
> };
> };
> +
> + reg_vcc_wifi: reg_vcc_wifi {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&vcc_wifi_pin_opi0>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-wifi";
> + enable-active-high;
> + gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
> + };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi_pwrseq_pin_opi0>;
> + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
> + };
> };
>
> &ehci1 {
> @@ -95,6 +113,20 @@
> status = "okay";
> };
>
> +&mmc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc1_pins_a>;
> + vmmc-supply = <®_vcc_wifi>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&mmc1_pins_a {
> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
This should be bias-pull-up.
> +};
> +
> &ohci1 {
> status = "okay";
> };
> @@ -104,6 +136,11 @@
> pins = "PA17";
> function = "gpio_out";
> };
> +
> + vcc_wifi_pin_opi0: vcc_wifi_pin at 0 {
> + allwinner,pins = "PA20";
This should be pins
> + allwinner,function = "gpio_out";
This should be function
> + };
> };
>
> &r_pio {
> @@ -111,6 +148,11 @@
> pins = "PL10";
> function = "gpio_out";
> };
> +
> + wifi_pwrseq_pin_opi0: wifi_pwrseq_pin at 0 {
> + allwinner,pins = "PL7";
> + allwinner,function = "gpio_out";
And same thing here.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 2/3] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Maxime Ripard @ 2016-11-23 7:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121162421.800-2-icenowy@aosc.xyz>
On Tue, Nov 22, 2016 at 12:24:20AM +0800, Icenowy Zheng wrote:
> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC.
>
> Add a device tree file for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes since v2:
> - Use generic pinconf binding instead of legacy allwinner pinctrl binding.
> - removed uart3, which is not accessible on Orange Pi Zero.
> - Removed sun8i-h2plus.dtsi and make Orange Pi Zero dts directly include
> sun8i-h3.dtsi.
> - Removed allwinner,sun8i-h3 compatible.
>
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts | 137 +++++++++++++++++++++++
Ditto, h2-plus-orangepi-zero.
> 2 files changed, 138 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 802a10d..51a1dd7 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -834,6 +834,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-a33-sinlinx-sina33.dtb \
> sun8i-a83t-allwinner-h8homlet-v2.dtb \
> sun8i-a83t-cubietruck-plus.dtb \
> + sun8i-h2plus-orangepi-zero.dtb \
> sun8i-h3-bananapi-m2-plus.dtb \
> sun8i-h3-nanopi-neo.dtb \
> sun8i-h3-orangepi-2.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> new file mode 100644
> index 0000000..b428e47
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> @@ -0,0 +1,137 @@
> +/*
> + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
> + *
> + * Based on sun8i-h3-orangepi-one.dts, which is:
> + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-h3.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + model = "Xunlong Orange Pi Zero";
> + compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2plus";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&leds_opi0>, <&leds_r_opi0>;
> +
> + pwr_led {
> + label = "orangepi:green:pwr";
> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + status_led {
> + label = "orangepi:red:status";
> + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + cd-inverted;
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&pio {
> + leds_opi0: led_pins at 0 {
> + pins = "PA17";
> + function = "gpio_out";
> + };
> +};
> +
> +&r_pio {
> + leds_r_opi0: led_pins at 0 {
> + pins = "PL10";
> + function = "gpio_out";
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "disabled";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_pins>;
> + status = "disabled";
> +};
I'm not sure you answered me on this one. Are those exposed on the
headers? why did you put them as disabled here?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v2 1/3] ARM: sunxi: add support for H2+ SoC
From: Maxime Ripard @ 2016-11-23 7:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121162421.800-1-icenowy@aosc.xyz>
Hi,
On Tue, Nov 22, 2016 at 12:24:19AM +0800, Icenowy Zheng wrote:
> Allwinner H2+ is a quad-core Cortex-A7 SoC.
>
> It is very like H3, that they share the same SoC ID (0x1680), and H3
> memory maps as well as drivers works well on the SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Documentation/arm/sunxi/README | 4 ++++
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> arch/arm/mach-sunxi/sunxi.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
> index cd02433..1fe4d99c 100644
> --- a/Documentation/arm/sunxi/README
> +++ b/Documentation/arm/sunxi/README
> @@ -63,6 +63,10 @@ SunXi family
> + User Manual
> http://dl.linux-sunxi.org/A33/A33%20user%20manual%20release%201.1.pdf
>
> + - Allwinner H2+ (sun8i)
> + + No document available now, but is known to be working properly with
> + H3 drivers and memory map.
> +
I'm not sure the phrasing is right here. I would prefer something like:
"No document publicly available now, but looks very similar to the H3"
> - Allwinner H3 (sun8i)
> + Datasheet
> http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 4d6467c..26b35a7 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -13,6 +13,7 @@ using one of the following compatible strings:
> allwinner,sun8i-a33
> allwinner,sun8i-a83t
> allwinner,sun8i-h3
> + allwinner,sun8i-h2plus
h2-plus please.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 1/3] of: base: add support to get machine compatible string
From: Sekhar Nori @ 2016-11-23 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <fdb93150-9089-c7bb-2b0a-21ded241a647@arm.com>
On Tuesday 22 November 2016 09:16 PM, Sudeep Holla wrote:
> Hi Sekhar,
>
> On 22/11/16 15:06, Sekhar Nori wrote:
>> Hi Sudeep,
>>
>> On Tuesday 22 November 2016 04:23 PM, Sudeep Holla wrote:
>>>
>>>
>>> On 22/11/16 10:41, Bartosz Golaszewski wrote:
>>>> Add a function allowing to retrieve the compatible string of the root
>>>> node of the device tree.
>>>>
>>>
>>> Rob has queued [1] and it's in -next today. You can reuse that if you
>>> are planning to target this for v4.11 or just use open coding in your
>>> driver for v4.10 and target this move for v4.11 to avoid cross tree
>>> dependencies as I already mentioned in your previous thread.
>>
>> I dont have your original patch in my mailbox, but I wonder if
>> returning a pointer to property string for a node whose reference has
>> already been released is safe to do? Probably not an issue for the root
>> node, but still feels counter-intuitive.
>>
>
> I am not sure if I understand the issue here. Are you referring a case
> where of_root is freed ?
Yes, right, thats what I was hinting at. Since you are giving up the
reference to the device node before the function returns, the user can
be left with a dangling reference.
> Also I have seen drivers today just using this pointer directly, but
> it's better to copy the string(I just saw this done in one case)
Hmm, the reference is given up before the API returns, so I doubt
copying it later is any additional benefit.
I suspect this is a theoretical issue though since root device node is
probably never freed.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] PCI: Add information about describing PCI in ACPI
From: Ard Biesheuvel @ 2016-11-23 7:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161123010600.GF4832@bhelgaas-glaptop.roam.corp.google.com>
On 23 November 2016 at 01:06, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Tue, Nov 22, 2016 at 10:09:50AM +0000, Ard Biesheuvel wrote:
>> On 17 November 2016 at 17:59, Bjorn Helgaas <bhelgaas@google.com> wrote:
>
>> > +PCI host bridges are PNP0A03 or PNP0A08 devices. Their _CRS should
>> > +describe all the address space they consume. In principle, this would
>> > +be all the windows they forward down to the PCI bus, as well as the
>> > +bridge registers themselves. The bridge registers include things like
>> > +secondary/subordinate bus registers that determine the bus range below
>> > +the bridge, window registers that describe the apertures, etc. These
>> > +are all device-specific, non-architected things, so the only way a
>> > +PNP0A03/PNP0A08 driver can manage them is via _PRS/_CRS/_SRS, which
>> > +contain the device-specific details. These bridge registers also
>> > +include ECAM space, since it is consumed by the bridge.
>> > +
>> > +ACPI defined a Producer/Consumer bit that was intended to distinguish
>> > +the bridge apertures from the bridge registers [4, 5]. However,
>> > +BIOSes didn't use that bit correctly, and the result is that OSes have
>> > +to assume that everything in a PCI host bridge _CRS is a window. That
>> > +leaves no way to describe the bridge registers in the PNP0A03/PNP0A08
>> > +device itself.
>>
>> Is that universally true? Or is it still possible to do the right
>> thing here on new ACPI architectures such as arm64?
>
> That's a very good question. I had thought that the ACPI spec had
> given up on Consumer/Producer completely, but I was wrong. In the 6.0
> spec, the Consumer/Producer bit is still documented in the Extended
> Address Space Descriptor (sec 6.4.3.5.4). It is documented as
> "ignored" in the QWord, DWord, and Word descriptors (sec 6.4.3.5.1,2,3).
>
> Linux looks at the producer_consumer bit in acpi_decode_space(), which
> I think is used for all these descriptors (QWord, DWord, Word, and
> Extended). This doesn't quite follow the spec -- we probably should
> ignore it except for Extended. In any event, acpi_decode_space() sets
> IORESOURCE_WINDOW for Producer descriptors, but we don't test
> IORESOURCE_WINDOW in the PCI host bridge code.
>
> x86 and ia64 supply their own pci_acpi_root_prepare_resources()
> functions that call acpi_pci_probe_root_resources(), which parses _CRS
> and looks at producer_consumer. Then they do a little arch-specific
> stuff on the result.
>
> On arm64 we use acpi_pci_probe_root_resources() directly, with no
> arch-specific stuff.
>
> On all three arches, we ignore the Consumer/Producer bit, so all the
> resources are treated as Producers, e.g., as bridge windows.
>
> I think we *could* implement an arm64 version of
> pci_acpi_root_prepare_resources() that would pay attention to the
> Consumer/Producer bit by checking IORESOURCE_WINDOW. To be spec
> compliant, we would have to use Extended descriptors for all bridge
> windows, even if they would fit in a DWord or QWord.
>
> Should we do that? I dunno. I'd like to hear your opinion(s).
>
Yes, I think we should. If the spec allows for a way for a PNP0A03
device to describe all of its resources unambiguously, we should not
be relying on workarounds that were designed for another architecture
in another decade (for, presumably, another OS)
Just for my understanding, we will need to use extended descriptors
for all consumed *and* produced regions, even though dword/qword are
implicitly produced-only, due to the fact that the bit is ignored?
> It *would* be nice to have bridge registers in the bridge _CRS. That
> would eliminate the need for looking up the HISI0081/PNP0C02 devices
> to find the bridge registers. Avoiding that lookup is only a
> temporary advantage -- the next round of bridges are supposed to fully
> implement ECAM, and then we won't need to know where the registers
> are.
>
> Apart from the lookup, there's still some advantage in describing the
> registers in the PNP0A03 device instead of an unrelated PNP0C02
> device, because it makes /proc/iomem more accurate and potentially
> makes host bridge hotplug cleaner. We would have to enhance the host
> bridge driver to do the reservations currently done by pnp/system.c.
>
> There's some value in doing it the same way as on x86, even though
> that way is somewhat broken.
>
> Whatever we decide, I think it's very important to get it figured out
> ASAP because it affects the ECAM quirks that we're trying to merge in
> v4.10.
>
I agree. What exactly is the impact for the quirks mechanism as proposed?
^ permalink raw reply
* [PATCH v2] clk: qoriq: added ls1012a clock configuration
From: Scott Wood @ 2016-11-23 7:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479802499-9083-1-git-send-email-yuantian.tang@nxp.com>
On 11/22/2016 02:28 AM, yuantian.tang at nxp.com wrote:
> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>
> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
> ---
> v2:
> - remove commit message as it is duplicated to title
>
> drivers/clk/clk-qoriq.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> index 1bece0f..65c21d7 100644
> --- a/drivers/clk/clk-qoriq.c
> +++ b/drivers/clk/clk-qoriq.c
> @@ -202,6 +202,14 @@ static const struct clockgen_muxinfo ls1021a_cmux = {
> }
> };
>
> +static const struct clockgen_muxinfo ls1012a_cmux = {
> + {
> + [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
> + {},
> + [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
> + }
> +};
> +
> static const struct clockgen_muxinfo t1040_cmux = {
> {
> [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
> @@ -482,6 +490,16 @@ static const struct clockgen_chipinfo chipinfo[] = {
> .pll_mask = 0x03,
> },
> {
> + .compat = "fsl,ls1012a-clockgen",
> + .cmux_groups = {
> + &ls1012a_cmux
> + },
> + .cmux_to_group = {
> + 0, -1
> + },
> + .pll_mask = 0x03,
> + },
> + {
> .compat = "fsl,ls1043a-clockgen",
> .init_periph = t2080_init_periph,
> .cmux_groups = {
> @@ -1282,6 +1300,7 @@ static void __init clockgen_init(struct device_node *np)
> CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
> CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
> CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
> +CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
> CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
> CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
Again, can you please keep the chip lists sorted? ls1012a doesn't go
after ls1021a.
-Scott
^ permalink raw reply
* [PATCH] clk: qoriq: added ls1012a clock configuration
From: Scott Wood @ 2016-11-23 7:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR0402MB28371BAAD862417B8AC8AED4F0B40@DB6PR0402MB2837.eurprd04.prod.outlook.com>
On 11/22/2016 02:20 AM, Y.T. Tang wrote:
> Hi Scott,
>
>> -----Original Message-----
>> From: Scott Wood [mailto:oss at buserror.net]
>> Sent: Wednesday, November 16, 2016 2:54 PM
>> To: Y.T. Tang <yuantian.tang@nxp.com>; mturquette at baylibre.com
>> Cc: sboyd at codeaurora.org; linux-kernel at vger.kernel.org; Scott Wood
>> <scott.wood@nxp.com>; linux-clk at vger.kernel.org; linux-arm-
>> kernel at lists.infradead.org
>> Subject: Re: [PATCH] clk: qoriq: added ls1012a clock configuration
>>
>> On Wed, 2016-11-16 at 13:58 +0800, yuantian.tang at nxp.com wrote:
>>> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>>>
>>> Added ls1012a clock configuation information.
>>
>> Do we really need the same line in the changelog twice?
>>
>>>
>>> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
>>> ---
>>> drivers/clk/clk-qoriq.c | 19 +++++++++++++++++++
>>> 1 file changed, 19 insertions(+)
>>>
>>> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
>>> 1bece0f..563d874 100644
>>> --- a/drivers/clk/clk-qoriq.c
>>> +++ b/drivers/clk/clk-qoriq.c
>>> @@ -202,6 +202,14 @@ static const struct clockgen_muxinfo ls1021a_cmux
>> = {
>>> }
>>> };
>>>
>>> +static const struct clockgen_muxinfo ls1012a_cmux = {
>>> + {
>>> + [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
>>> + {},
>>> + [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
>>> + }
>>> +};
>>> +
>>
>> Based on the "ls1021a_cmux" in the context it looks like this patch is
>> intended to apply on top
>> of https://patchwork.kernel.org/patch/8923541/ but I don't see any mention
>> of that.
>>
> I saw this patch had been merged already.
>
> Regards,
> Yuantian
I don't see it in linux-next.
-Scott
^ permalink raw reply
* [PATCH] arm/dts: ls1021a: Add dma-coherent property to usb3 node
From: Changming Huang @ 2016-11-23 7:15 UTC (permalink / raw)
To: linux-arm-kernel
This sets dma ops as coherent for usb 3.0 platform device
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..81fb4d9 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -627,6 +627,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ dma-coherent;
};
pcie at 3400000 {
--
1.7.9.5
^ permalink raw reply related
* [PATCH V3 1/2] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Troy Jia @ 2016-11-23 7:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479884833.21746.44.camel@buserror.net>
> -----Original Message-----
> From: Scott Wood [mailto:oss at buserror.net]
> Sent: Wednesday, November 23, 2016 3:07 PM
> To: Troy Jia <hongtao.jia@nxp.com>; rui.zhang at intel.com; edubezval at gmail.com;
> robh+dt at kernel.org; Scott Wood <scott.wood@nxp.com>; shawnguo at kernel.org
> Cc: devicetree at vger.kernel.org; linuxppc-dev at lists.ozlabs.org; linux-
> kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH V3 1/2] powerpc/mpc85xx: Update TMU device tree node for
> T1040/T1042
>
> On Tue, 2016-10-25 at 10:15 +0800, Jia Hongtao wrote:
> > From: Hongtao Jia <hongtao.jia@nxp.com>
> >
> > Update #thermal-sensor-cells from 0 to 1 according to the new binding.
> > The sensor specifier added is the monitoring site ID, and represents
> > the "n" in TRITSRn and TRATSRn.
> >
> > Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
>
> Where can I find this new binding? ?As of the current linux-next I don't see anything
> in qoriq-thermal.txt about this.
Hi Rui Zhang,
As we discussed before. The time was inappropriate as merge window was about to close.
So do you have any plan for applying the binding file recently?
-Hongtao.
^ permalink raw reply
* [PATCH V3 1/2] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Scott Wood @ 2016-11-23 7:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1477361742-589-1-git-send-email-hongtao.jia@nxp.com>
On Tue, 2016-10-25 at 10:15 +0800, Jia Hongtao wrote:
> From: Hongtao Jia <hongtao.jia@nxp.com>
>
> Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
> sensor specifier added is the monitoring site ID, and represents the "n" in
> TRITSRn and TRATSRn.
>
> Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
Where can I find this new binding? ?As of the current linux-next I don't see
anything in qoriq-thermal.txt about this.
-Scott
^ permalink raw reply
* [PATCH v16 10/15] clocksource/drivers/arm_arch_timer: Refactor the timer init code to prepare for GTDT
From: Fu Wei @ 2016-11-23 6:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118200335.GN1197@leverpostej>
Hi Mark,
On 19 November 2016 at 04:03, Mark Rutland <mark.rutland@arm.com> wrote:
> On Wed, Nov 16, 2016 at 09:49:03PM +0800, fu.wei at linaro.org wrote:
>> From: Fu Wei <fu.wei@linaro.org>
>>
>> The patch refactor original memory-mapped timer init code:
>> (1) Extract a subfunction for detecting a bast time frame:
>> is_best_frame.
>
> Please leave this logic in arch_timer_mem_init(). Pulling it out gains
> us nothing, but makes the patch harder to review.
OK, I have put it back to arch_timer_mem_init() in next version: v17
>
>> (2) Refactor "arch_timer_mem_init", make it become a common code for
>> memory-mapped timer init.
>> (3) Add a new function "arch_timer_mem_of_init" for DT init.
>
> These generally look fine.
>
> Thanks,
> Mark.
>
>> Signed-off-by: Fu Wei <fu.wei@linaro.org>
>> ---
>> drivers/clocksource/arm_arch_timer.c | 162 +++++++++++++++++++++++------------
>> 1 file changed, 107 insertions(+), 55 deletions(-)
>>
>> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
>> index 9ddc091..0836bb9 100644
>> --- a/drivers/clocksource/arm_arch_timer.c
>> +++ b/drivers/clocksource/arm_arch_timer.c
>> @@ -923,17 +923,35 @@ static int __init arch_timer_of_init(struct device_node *np)
>> CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
>> CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
>>
>> -static int __init arch_timer_mem_init(struct device_node *np)
>> +static bool __init is_best_frame(void __iomem *cntctlbase, u32 cnttidr, int n)
>> +{
>> + u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | CNTACR_RWVT |
>> + CNTACR_RVOFF | CNTACR_RVCT;
>> +
>> + /* Try enabling everything, and see what sticks */
>> + writel_relaxed(cntacr, cntctlbase + CNTACR(n));
>> + cntacr = readl_relaxed(cntctlbase + CNTACR(n));
>> +
>> + if ((cnttidr & CNTTIDR_VIRT(n)) &&
>> + !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT)))
>> + arch_timer_mem_use_virtual = true;
>> + else if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
>> + return false;
>> +
>> + return true;
>> +}
>> +
>> +static int __init arch_timer_mem_init(struct arch_timer_mem *timer_mem)
>> {
>> - struct device_node *frame, *best_frame = NULL;
>> void __iomem *cntctlbase, *base;
>> - unsigned int irq, ret = -EINVAL;
>> + struct arch_timer_mem_frame *best_frame = NULL;
>> + unsigned int irq;
>> u32 cnttidr;
>> + int i, ret;
>>
>> - arch_timers_present |= ARCH_TIMER_TYPE_MEM;
>> - cntctlbase = of_iomap(np, 0);
>> + cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
>> if (!cntctlbase) {
>> - pr_err("Can't find CNTCTLBase\n");
>> + pr_err("Can't map CNTCTLBase.\n");
>> return -ENXIO;
>> }
>>
>> @@ -943,76 +961,110 @@ static int __init arch_timer_mem_init(struct device_node *np)
>> * Try to find a virtual capable frame. Otherwise fall back to a
>> * physical capable frame.
>> */
>> - for_each_available_child_of_node(np, frame) {
>> - int n;
>> - u32 cntacr;
>> -
>> - if (of_property_read_u32(frame, "frame-number", &n)) {
>> - pr_err("Missing frame-number\n");
>> - of_node_put(frame);
>> - goto out;
>> - }
>> -
>> - /* Try enabling everything, and see what sticks */
>> - cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
>> - CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
>> - writel_relaxed(cntacr, cntctlbase + CNTACR(n));
>> - cntacr = readl_relaxed(cntctlbase + CNTACR(n));
>> -
>> - if ((cnttidr & CNTTIDR_VIRT(n)) &&
>> - !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
>> - of_node_put(best_frame);
>> - best_frame = frame;
>> - arch_timer_mem_use_virtual = true;
>> - break;
>> + for (i = 0; i < timer_mem->num_frames; i++) {
>> + if (is_best_frame(cntctlbase, cnttidr,
>> + timer_mem->frame[i].frame_nr)) {
>> + best_frame = &timer_mem->frame[i];
>> + if (arch_timer_mem_use_virtual)
>> + break;
>> }
>> -
>> - if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
>> - continue;
>> -
>> - of_node_put(best_frame);
>> - best_frame = of_node_get(frame);
>> }
>> + iounmap(cntctlbase);
>>
>> - ret= -ENXIO;
>> - base = arch_counter_base = of_iomap(best_frame, 0);
>> - if (!base) {
>> - pr_err("Can't map frame's registers\n");
>> - goto out;
>> + if (!best_frame) {
>> + pr_err("Can't find frame for register\n");
>> + return -EINVAL;
>> }
>>
>> if (arch_timer_mem_use_virtual)
>> - irq = irq_of_parse_and_map(best_frame, ARCH_TIMER_VIRT_SPI);
>> + irq = best_frame->virt_irq;
>> else
>> - irq = irq_of_parse_and_map(best_frame, ARCH_TIMER_PHYS_SPI);
>> + irq = best_frame->phys_irq;
>>
>> - ret = -EINVAL;
>> if (!irq) {
>> pr_err("Frame missing %s irq",
>> arch_timer_mem_use_virtual ? "virt" : "phys");
>> - goto out;
>> + return -EINVAL;
>> }
>>
>> - /*
>> - * Try to determine the frequency from the device tree,
>> - * if fail, get the frequency from CNTFRQ.
>> - */
>> - if (!arch_timer_rate &&
>> - of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
>> - arch_timer_detect_rate(base);
>> + base = ioremap(best_frame->cntbase, best_frame->size);
>> + if (!base) {
>> + pr_err("Can't map frame's registers\n");
>> + return -ENXIO;
>> + }
>> +
>> + arch_timer_detect_rate(base);
>>
>> ret = arch_timer_mem_register(base, irq);
>> - if (ret)
>> + if (ret) {
>> + iounmap(base);
>> + return ret;
>> + }
>> +
>> + arch_counter_base = base;
>> + arch_timers_present |= ARCH_TIMER_TYPE_MEM;
>> +
>> + return 0;
>> +}
>> +
>> +static int __init arch_timer_mem_of_init(struct device_node *np)
>> +{
>> + struct arch_timer_mem *timer_mem;
>> + struct device_node *frame_node;
>> + struct resource res;
>> + int i, ret = -EINVAL;
>> +
>> + timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
>> + if (!timer_mem)
>> + return -ENOMEM;
>> +
>> + if (of_address_to_resource(np, 0, &res))
>> goto out;
>> + timer_mem->cntctlbase = res.start;
>> + timer_mem->size = resource_size(&res);
>>
>> - return arch_timer_common_init();
>> + i = 0;
>> + for_each_available_child_of_node(np, frame_node) {
>> + int n;
>> + struct arch_timer_mem_frame *frame = &timer_mem->frame[i];
>> +
>> + if (of_property_read_u32(frame_node, "frame-number", &n)) {
>> + pr_err("Missing frame-number\n");
>> + of_node_put(frame_node);
>> + goto out;
>> + }
>> + frame->frame_nr = n;
>> +
>> + if (of_address_to_resource(frame_node, 0, &res)) {
>> + of_node_put(frame_node);
>> + goto out;
>> + }
>> + frame->cntbase = res.start;
>> + frame->size = resource_size(&res);
>> +
>> + frame->virt_irq = irq_of_parse_and_map(frame_node,
>> + ARCH_TIMER_VIRT_SPI);
>> + frame->phys_irq = irq_of_parse_and_map(frame_node,
>> + ARCH_TIMER_PHYS_SPI);
>> +
>> + if (++i >= ARCH_TIMER_MEM_MAX_FRAMES)
>> + break;
>> + }
>> + timer_mem->num_frames = i;
>> +
>> + /* Try to determine the frequency from the device tree */
>> + if (!arch_timer_rate)
>> + of_property_read_u32(np, "clock-frequency", &arch_timer_rate);
>> +
>> + ret = arch_timer_mem_init(timer_mem);
>> + if (!ret)
>> + ret = arch_timer_common_init();
>> out:
>> - iounmap(cntctlbase);
>> - of_node_put(best_frame);
>> + kfree(timer_mem);
>> return ret;
>> }
>> CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
>> - arch_timer_mem_init);
>> + arch_timer_mem_of_init);
>>
>> #ifdef CONFIG_ACPI
>> static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
>> --
>> 2.7.4
>>
--
Best regards,
Fu Wei
Software Engineer
Red Hat
^ permalink raw reply
* [PATCH v2 1/5] ARM: memory: da8xx-ddrctl: new driver
From: Sekhar Nori @ 2016-11-23 5:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <58348CB8.7050304@gmail.com>
On Tuesday 22 November 2016 11:51 PM, Frank Rowand wrote:
> Please note that the compatible property might contain several strings, not just
> a single string.
So I guess the best thing to do is to use
of_property_read_string_index() and print the sting at index 0.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH 2/4] ARM: dts: davinci: da850: add VPIF
From: Kevin Hilman @ 2016-11-23 5:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <51071aa1-50c5-1121-3e64-018edaf544bf@lechnology.com>
David Lechner <david@lechnology.com> writes:
> On 11/22/2016 01:45 PM, Kevin Hilman wrote:
>> Add VPIF and VPIF capture nodes to da850. VPIF capture has two input
>> channels describe using the standard DT ports and enpoints.
>>
>> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
>> ---
>> arch/arm/boot/dts/da850.dtsi | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
>> index 6205917b4f59..e05e2bb834e8 100644
>> --- a/arch/arm/boot/dts/da850.dtsi
>> +++ b/arch/arm/boot/dts/da850.dtsi
>> @@ -453,7 +453,35 @@
>> interrupts = <52>;
>> status = "disabled";
>> };
>> +
>> + vpif: video at 0x00217000 {
>
> Should be @217000
>
>> + compatible = "ti,da850-vpif";
>> + reg = <0x00217000 0x1000>;
>
> Could omit leading 0's to be consistent with existing entries.
>
> reg = <0x217000 0x1000>;
Ugh, yeah. I hate that convention, but better to be consistent, I guess.
>> + status = "disabled";
>> + };
>> +
>> + vpif_capture: video-capture at 0x00217000 {
>
> Again, @217000. But it seems odd to have two device nodes with the
> same address. Is enabling these mutually exclusive?
They're not mutually exclusive because the vpif is the one that actually
maps the register range (since it's shared between vpif_display and
vpif_capture) so I guess I should just drop the reg property from the
vpif_capture node.
>> + compatible = "ti,da850-vpif-capture";
>> + reg = <0x00217000 0x1000>;
>
> Ditto on the leading 0's.
>
Thanks for the review,
Kevin
^ permalink raw reply
* [PATCH 1/4] ARM: davinci: da8xx: VPIF: enable DT init
From: Kevin Hilman @ 2016-11-23 5:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <31948202-333f-b465-07b8-6260cce29b59@lechnology.com>
David Lechner <david@lechnology.com> writes:
> On 11/22/2016 01:45 PM, Kevin Hilman wrote:
>> Add basic support for DT initializaion of VPIF (capture) via DT. Clocks
>> and mux still need to happen in this file until there are real clock and
>> pinctrl drivers, but the video nodes and subdevs can all come from DT.
>>
>> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
>> ---
>> arch/arm/mach-davinci/da8xx-dt.c | 17 +++++++++++++++++
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
>> index c9f7e9274aa8..7b41611f2665 100644
>> --- a/arch/arm/mach-davinci/da8xx-dt.c
>> +++ b/arch/arm/mach-davinci/da8xx-dt.c
>> @@ -17,6 +17,7 @@
>> #include <mach/common.h>
>> #include "cp_intc.h"
>> #include <mach/da8xx.h>
>> +#include <mach/mux.h>
>>
>> static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
>> OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
>> @@ -38,14 +39,30 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
>> NULL),
>> OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL),
>> OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", NULL),
>> + OF_DEV_AUXDATA("ti,da850-vpif", 0x01e17000, "vpif", NULL),
>> {}
>> };
>>
>> #ifdef CONFIG_ARCH_DAVINCI_DA850
>>
>> +#if IS_ENABLED(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE)
>> +static __init void da850_vpif_capture_init(void)
>> +{
>> + int ret;
>> +
>> + ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
>
> Why can't we use the existing pinctrl-single node in device tree for
> muxing the pins?
Oops, you're right. They can.
Kevin
^ permalink raw reply
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