* [PATCH v3 6/6] mfd: dt: Move syscon bindings to syscon subdirectory
From: Andrew Jeffery @ 2016-12-06 2:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206025321.1792-1-andrew@aj.id.au>
The use of syscons is growing, lets collate them in their own part of
the bindings tree.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
Documentation/devicetree/bindings/mfd/{ => syscon}/aspeed-scu.txt | 0
Documentation/devicetree/bindings/mfd/{ => syscon}/atmel-gpbr.txt | 0
Documentation/devicetree/bindings/mfd/{ => syscon}/atmel-matrix.txt | 0
Documentation/devicetree/bindings/mfd/{ => syscon}/atmel-smc.txt | 0
Documentation/devicetree/bindings/mfd/{ => syscon}/qcom,tcsr.txt | 0
Documentation/devicetree/bindings/mfd/{ => syscon}/syscon.txt | 0
.../devicetree/bindings/mfd/{ => syscon}/ti-keystone-devctrl.txt | 0
7 files changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/mfd/{ => syscon}/aspeed-scu.txt (100%)
rename Documentation/devicetree/bindings/mfd/{ => syscon}/atmel-gpbr.txt (100%)
rename Documentation/devicetree/bindings/mfd/{ => syscon}/atmel-matrix.txt (100%)
rename Documentation/devicetree/bindings/mfd/{ => syscon}/atmel-smc.txt (100%)
rename Documentation/devicetree/bindings/mfd/{ => syscon}/qcom,tcsr.txt (100%)
rename Documentation/devicetree/bindings/mfd/{ => syscon}/syscon.txt (100%)
rename Documentation/devicetree/bindings/mfd/{ => syscon}/ti-keystone-devctrl.txt (100%)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/syscon/aspeed-scu.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mfd/aspeed-scu.txt
rename to Documentation/devicetree/bindings/mfd/syscon/aspeed-scu.txt
diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/syscon/atmel-gpbr.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
rename to Documentation/devicetree/bindings/mfd/syscon/atmel-gpbr.txt
diff --git a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt b/Documentation/devicetree/bindings/mfd/syscon/atmel-matrix.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mfd/atmel-matrix.txt
rename to Documentation/devicetree/bindings/mfd/syscon/atmel-matrix.txt
diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/syscon/atmel-smc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mfd/atmel-smc.txt
rename to Documentation/devicetree/bindings/mfd/syscon/atmel-smc.txt
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/syscon/qcom,tcsr.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
rename to Documentation/devicetree/bindings/mfd/syscon/qcom,tcsr.txt
diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon/syscon.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mfd/syscon.txt
rename to Documentation/devicetree/bindings/mfd/syscon/syscon.txt
diff --git a/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt b/Documentation/devicetree/bindings/mfd/syscon/ti-keystone-devctrl.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt
rename to Documentation/devicetree/bindings/mfd/syscon/ti-keystone-devctrl.txt
--
2.9.3
^ permalink raw reply
* [PATCH] ipmi: bt-bmc: Use a regmap for register access
From: Andrew Jeffery @ 2016-12-06 2:57 UTC (permalink / raw)
To: linux-arm-kernel
The registers for the bt-bmc device live under the Aspeed LPC
controller. Devicetree bindings have recently been introduced for the
LPC controller where the "host" portion of the LPC register space is
described as a syscon device. Future devicetrees describing the bt-bmc
device should nest its node under the appropriate "simple-mfd", "syscon"
compatible node.
This change allows the bt-bmc driver to function with both syscon and
non-syscon- based devicetree descriptions by always using a regmap for
register access, either retrieved from the parent syscon device or
instantiated if none exists.
The patch has been tested on an OpenPOWER Palmetto machine, successfully
booting, rebooting and powering down the host.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/char/ipmi/Kconfig | 1 +
drivers/char/ipmi/bt-bmc.c | 82 ++++++++++++++++++++++++++++++++++------------
2 files changed, 62 insertions(+), 21 deletions(-)
diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
index 7f816655cbbf..b5d48d9af124 100644
--- a/drivers/char/ipmi/Kconfig
+++ b/drivers/char/ipmi/Kconfig
@@ -79,6 +79,7 @@ endif # IPMI_HANDLER
config ASPEED_BT_IPMI_BMC
depends on ARCH_ASPEED
+ depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
tristate "BT IPMI bmc driver"
help
Provides a driver for the BT (Block Transfer) IPMI interface
diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
index fc9e8891eae3..ca1e20f6c6c5 100644
--- a/drivers/char/ipmi/bt-bmc.c
+++ b/drivers/char/ipmi/bt-bmc.c
@@ -12,10 +12,13 @@
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/mfd/syscon.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/poll.h>
+#include <linux/regmap.h>
#include <linux/sched.h>
#include <linux/timer.h>
@@ -60,7 +63,8 @@
struct bt_bmc {
struct device dev;
struct miscdevice miscdev;
- void __iomem *base;
+ struct regmap *map;
+ int offset;
int irq;
wait_queue_head_t queue;
struct timer_list poll_timer;
@@ -69,14 +73,31 @@ struct bt_bmc {
static atomic_t open_count = ATOMIC_INIT(0);
+static struct regmap_config bt_regmap_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
static u8 bt_inb(struct bt_bmc *bt_bmc, int reg)
{
- return ioread8(bt_bmc->base + reg);
+ uint32_t val = 0;
+ int rc;
+
+ rc = regmap_read(bt_bmc->map, bt_bmc->offset + reg, &val);
+ WARN(rc != 0, "%s:%d: regmap_read() failed: %d\n",
+ __FILE__, __LINE__, rc);
+
+ return rc == 0 ? (u8) val : 0;
}
static void bt_outb(struct bt_bmc *bt_bmc, u8 data, int reg)
{
- iowrite8(data, bt_bmc->base + reg);
+ int rc;
+
+ rc = regmap_write(bt_bmc->map, bt_bmc->offset + reg, data);
+ WARN(rc != 0, "%s:%d: regmap_write() failed: %d\n",
+ __FILE__, __LINE__, rc);
}
static void clr_rd_ptr(struct bt_bmc *bt_bmc)
@@ -367,14 +388,18 @@ static irqreturn_t bt_bmc_irq(int irq, void *arg)
{
struct bt_bmc *bt_bmc = arg;
u32 reg;
+ int rc;
+
+ rc = regmap_read(bt_bmc->map, bt_bmc->offset + BT_CR2, ®);
+ if (rc)
+ return IRQ_NONE;
- reg = ioread32(bt_bmc->base + BT_CR2);
reg &= BT_CR2_IRQ_H2B | BT_CR2_IRQ_HBUSY;
if (!reg)
return IRQ_NONE;
/* ack pending IRQs */
- iowrite32(reg, bt_bmc->base + BT_CR2);
+ regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR2, reg);
wake_up(&bt_bmc->queue);
return IRQ_HANDLED;
@@ -384,7 +409,6 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- u32 reg;
int rc;
bt_bmc->irq = platform_get_irq(pdev, 0);
@@ -405,18 +429,17 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
* will be cleared (along with B2H) when we can write the next
* message to the BT buffer
*/
- reg = ioread32(bt_bmc->base + BT_CR1);
- reg |= BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY;
- iowrite32(reg, bt_bmc->base + BT_CR1);
+ rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset + BT_CR1,
+ (BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY),
+ (BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY));
- return 0;
+ return rc;
}
static int bt_bmc_probe(struct platform_device *pdev)
{
struct bt_bmc *bt_bmc;
struct device *dev;
- struct resource *res;
int rc;
if (!pdev || !pdev->dev.of_node)
@@ -431,10 +454,27 @@ static int bt_bmc_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, bt_bmc);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- bt_bmc->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(bt_bmc->base))
- return PTR_ERR(bt_bmc->base);
+ bt_bmc->map = syscon_node_to_regmap(pdev->dev.parent->of_node);
+ if (IS_ERR(bt_bmc->map)) {
+ struct resource *res;
+ void __iomem *base;
+
+ /*
+ * Assume it's not the MFD-based devicetree description, in
+ * which case generate a regmap ourselves
+ */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ bt_bmc->map = devm_regmap_init_mmio(dev, base, &bt_regmap_cfg);
+ bt_bmc->offset = 0;
+ } else {
+ rc = of_property_read_u32(dev->of_node, "reg", &bt_bmc->offset);
+ if (rc)
+ return rc;
+ }
mutex_init(&bt_bmc->mutex);
init_waitqueue_head(&bt_bmc->queue);
@@ -461,12 +501,12 @@ static int bt_bmc_probe(struct platform_device *pdev)
add_timer(&bt_bmc->poll_timer);
}
- iowrite32((BT_IO_BASE << BT_CR0_IO_BASE) |
- (BT_IRQ << BT_CR0_IRQ) |
- BT_CR0_EN_CLR_SLV_RDP |
- BT_CR0_EN_CLR_SLV_WRP |
- BT_CR0_ENABLE_IBT,
- bt_bmc->base + BT_CR0);
+ regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR0,
+ (BT_IO_BASE << BT_CR0_IO_BASE) |
+ (BT_IRQ << BT_CR0_IRQ) |
+ BT_CR0_EN_CLR_SLV_RDP |
+ BT_CR0_EN_CLR_SLV_WRP |
+ BT_CR0_ENABLE_IBT);
clr_b_busy(bt_bmc);
--
2.9.3
^ permalink raw reply related
* [PATCH v4 0/6] aspeed: Integrate pinctrl and gpio drivers
From: Andrew Jeffery @ 2016-12-06 3:53 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This picks up some work from a while back that adds pinctrl and GPIO support to
the Aspeed devicetrees. See the previous series:
https://lkml.org/lkml/2016/8/30/74
Since v3 two new patches have been added, describing the Low Pin Count bus and
SoC Display Controller nodes. These are essential for the aspeed-g5 pinctrl.
Cheers,
Andrew
Andrew Jeffery (6):
arm: dts: aspeed-g4: Add syscon and pin controller nodes
arm: dts: aspeed-g4: Add gpio controller to devicetree
arm: dts: aspeed-g5: Add SoC Display Controller node
arm: dts: aspeed-g5: Add LPC Controller node
arm: dts: aspeed-g5: Add syscon and pin controller nodes
arm: dts: aspeed-g5: Add gpio controller to devicetree
arch/arm/boot/dts/aspeed-g4.dtsi | 760 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 863 +++++++++++++++++++++++++++++++++++++++
2 files changed, 1623 insertions(+)
--
2.9.3
^ permalink raw reply
* [PATCH v4 1/6] arm: dts: aspeed-g4: Add syscon and pin controller nodes
From: Andrew Jeffery @ 2016-12-06 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206035348.29948-1-andrew@aj.id.au>
The pin controller's child nodes expose the functions currently
implemented in the the g4 pin controller driver.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 750 +++++++++++++++++++++++++++++++++++++++
1 file changed, 750 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 22dee5937d5c..b00dfc7a3bf7 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -54,6 +54,756 @@
clocks = <&clk_clkin>;
};
+ syscon: syscon at 1e6e2000 {
+ compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g4-pinctrl";
+
+ pinctrl_acpi_default: acpi_default {
+ function = "ACPI";
+ groups = "ACPI";
+ };
+
+ pinctrl_adc0_default: adc0_default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
+
+ pinctrl_adc1_default: adc1_default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
+
+ pinctrl_adc10_default: adc10_default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
+
+ pinctrl_adc11_default: adc11_default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
+
+ pinctrl_adc12_default: adc12_default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
+
+ pinctrl_adc13_default: adc13_default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
+
+ pinctrl_adc14_default: adc14_default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
+
+ pinctrl_adc15_default: adc15_default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
+
+ pinctrl_adc2_default: adc2_default {
+ function = "ADC2";
+ groups = "ADC2";
+ };
+
+ pinctrl_adc3_default: adc3_default {
+ function = "ADC3";
+ groups = "ADC3";
+ };
+
+ pinctrl_adc4_default: adc4_default {
+ function = "ADC4";
+ groups = "ADC4";
+ };
+
+ pinctrl_adc5_default: adc5_default {
+ function = "ADC5";
+ groups = "ADC5";
+ };
+
+ pinctrl_adc6_default: adc6_default {
+ function = "ADC6";
+ groups = "ADC6";
+ };
+
+ pinctrl_adc7_default: adc7_default {
+ function = "ADC7";
+ groups = "ADC7";
+ };
+
+ pinctrl_adc8_default: adc8_default {
+ function = "ADC8";
+ groups = "ADC8";
+ };
+
+ pinctrl_adc9_default: adc9_default {
+ function = "ADC9";
+ groups = "ADC9";
+ };
+
+ pinctrl_bmcint_default: bmcint_default {
+ function = "BMCINT";
+ groups = "BMCINT";
+ };
+
+ pinctrl_ddcclk_default: ddcclk_default {
+ function = "DDCCLK";
+ groups = "DDCCLK";
+ };
+
+ pinctrl_ddcdat_default: ddcdat_default {
+ function = "DDCDAT";
+ groups = "DDCDAT";
+ };
+
+ pinctrl_extrst_default: extrst_default {
+ function = "EXTRST";
+ groups = "EXTRST";
+ };
+
+ pinctrl_flack_default: flack_default {
+ function = "FLACK";
+ groups = "FLACK";
+ };
+
+ pinctrl_flbusy_default: flbusy_default {
+ function = "FLBUSY";
+ groups = "FLBUSY";
+ };
+
+ pinctrl_flwp_default: flwp_default {
+ function = "FLWP";
+ groups = "FLWP";
+ };
+
+ pinctrl_gpid_default: gpid_default {
+ function = "GPID";
+ groups = "GPID";
+ };
+
+ pinctrl_gpid0_default: gpid0_default {
+ function = "GPID0";
+ groups = "GPID0";
+ };
+
+ pinctrl_gpid2_default: gpid2_default {
+ function = "GPID2";
+ groups = "GPID2";
+ };
+
+ pinctrl_gpid4_default: gpid4_default {
+ function = "GPID4";
+ groups = "GPID4";
+ };
+
+ pinctrl_gpid6_default: gpid6_default {
+ function = "GPID6";
+ groups = "GPID6";
+ };
+
+ pinctrl_gpie0_default: gpie0_default {
+ function = "GPIE0";
+ groups = "GPIE0";
+ };
+
+ pinctrl_gpie2_default: gpie2_default {
+ function = "GPIE2";
+ groups = "GPIE2";
+ };
+
+ pinctrl_gpie4_default: gpie4_default {
+ function = "GPIE4";
+ groups = "GPIE4";
+ };
+
+ pinctrl_gpie6_default: gpie6_default {
+ function = "GPIE6";
+ groups = "GPIE6";
+ };
+
+ pinctrl_i2c10_default: i2c10_default {
+ function = "I2C10";
+ groups = "I2C10";
+ };
+
+ pinctrl_i2c11_default: i2c11_default {
+ function = "I2C11";
+ groups = "I2C11";
+ };
+
+ pinctrl_i2c12_default: i2c12_default {
+ function = "I2C12";
+ groups = "I2C12";
+ };
+
+ pinctrl_i2c13_default: i2c13_default {
+ function = "I2C13";
+ groups = "I2C13";
+ };
+
+ pinctrl_i2c14_default: i2c14_default {
+ function = "I2C14";
+ groups = "I2C14";
+ };
+
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+
+ pinctrl_i2c4_default: i2c4_default {
+ function = "I2C4";
+ groups = "I2C4";
+ };
+
+ pinctrl_i2c5_default: i2c5_default {
+ function = "I2C5";
+ groups = "I2C5";
+ };
+
+ pinctrl_i2c6_default: i2c6_default {
+ function = "I2C6";
+ groups = "I2C6";
+ };
+
+ pinctrl_i2c7_default: i2c7_default {
+ function = "I2C7";
+ groups = "I2C7";
+ };
+
+ pinctrl_i2c8_default: i2c8_default {
+ function = "I2C8";
+ groups = "I2C8";
+ };
+
+ pinctrl_i2c9_default: i2c9_default {
+ function = "I2C9";
+ groups = "I2C9";
+ };
+
+ pinctrl_lpcpd_default: lpcpd_default {
+ function = "LPCPD";
+ groups = "LPCPD";
+ };
+
+ pinctrl_lpcpme_default: lpcpme_default {
+ function = "LPCPME";
+ groups = "LPCPME";
+ };
+
+ pinctrl_lpcrst_default: lpcrst_default {
+ function = "LPCRST";
+ groups = "LPCRST";
+ };
+
+ pinctrl_lpcsmi_default: lpcsmi_default {
+ function = "LPCSMI";
+ groups = "LPCSMI";
+ };
+
+ pinctrl_mac1link_default: mac1link_default {
+ function = "MAC1LINK";
+ groups = "MAC1LINK";
+ };
+
+ pinctrl_mac2link_default: mac2link_default {
+ function = "MAC2LINK";
+ groups = "MAC2LINK";
+ };
+
+ pinctrl_mdio1_default: mdio1_default {
+ function = "MDIO1";
+ groups = "MDIO1";
+ };
+
+ pinctrl_mdio2_default: mdio2_default {
+ function = "MDIO2";
+ groups = "MDIO2";
+ };
+
+ pinctrl_ncts1_default: ncts1_default {
+ function = "NCTS1";
+ groups = "NCTS1";
+ };
+
+ pinctrl_ncts2_default: ncts2_default {
+ function = "NCTS2";
+ groups = "NCTS2";
+ };
+
+ pinctrl_ncts3_default: ncts3_default {
+ function = "NCTS3";
+ groups = "NCTS3";
+ };
+
+ pinctrl_ncts4_default: ncts4_default {
+ function = "NCTS4";
+ groups = "NCTS4";
+ };
+
+ pinctrl_ndcd1_default: ndcd1_default {
+ function = "NDCD1";
+ groups = "NDCD1";
+ };
+
+ pinctrl_ndcd2_default: ndcd2_default {
+ function = "NDCD2";
+ groups = "NDCD2";
+ };
+
+ pinctrl_ndcd3_default: ndcd3_default {
+ function = "NDCD3";
+ groups = "NDCD3";
+ };
+
+ pinctrl_ndcd4_default: ndcd4_default {
+ function = "NDCD4";
+ groups = "NDCD4";
+ };
+
+ pinctrl_ndsr1_default: ndsr1_default {
+ function = "NDSR1";
+ groups = "NDSR1";
+ };
+
+ pinctrl_ndsr2_default: ndsr2_default {
+ function = "NDSR2";
+ groups = "NDSR2";
+ };
+
+ pinctrl_ndsr3_default: ndsr3_default {
+ function = "NDSR3";
+ groups = "NDSR3";
+ };
+
+ pinctrl_ndsr4_default: ndsr4_default {
+ function = "NDSR4";
+ groups = "NDSR4";
+ };
+
+ pinctrl_ndtr1_default: ndtr1_default {
+ function = "NDTR1";
+ groups = "NDTR1";
+ };
+
+ pinctrl_ndtr2_default: ndtr2_default {
+ function = "NDTR2";
+ groups = "NDTR2";
+ };
+
+ pinctrl_ndtr3_default: ndtr3_default {
+ function = "NDTR3";
+ groups = "NDTR3";
+ };
+
+ pinctrl_ndtr4_default: ndtr4_default {
+ function = "NDTR4";
+ groups = "NDTR4";
+ };
+
+ pinctrl_ndts4_default: ndts4_default {
+ function = "NDTS4";
+ groups = "NDTS4";
+ };
+
+ pinctrl_nri1_default: nri1_default {
+ function = "NRI1";
+ groups = "NRI1";
+ };
+
+ pinctrl_nri2_default: nri2_default {
+ function = "NRI2";
+ groups = "NRI2";
+ };
+
+ pinctrl_nri3_default: nri3_default {
+ function = "NRI3";
+ groups = "NRI3";
+ };
+
+ pinctrl_nri4_default: nri4_default {
+ function = "NRI4";
+ groups = "NRI4";
+ };
+
+ pinctrl_nrts1_default: nrts1_default {
+ function = "NRTS1";
+ groups = "NRTS1";
+ };
+
+ pinctrl_nrts2_default: nrts2_default {
+ function = "NRTS2";
+ groups = "NRTS2";
+ };
+
+ pinctrl_nrts3_default: nrts3_default {
+ function = "NRTS3";
+ groups = "NRTS3";
+ };
+
+ pinctrl_oscclk_default: oscclk_default {
+ function = "OSCCLK";
+ groups = "OSCCLK";
+ };
+
+ pinctrl_pwm0_default: pwm0_default {
+ function = "PWM0";
+ groups = "PWM0";
+ };
+
+ pinctrl_pwm1_default: pwm1_default {
+ function = "PWM1";
+ groups = "PWM1";
+ };
+
+ pinctrl_pwm2_default: pwm2_default {
+ function = "PWM2";
+ groups = "PWM2";
+ };
+
+ pinctrl_pwm3_default: pwm3_default {
+ function = "PWM3";
+ groups = "PWM3";
+ };
+
+ pinctrl_pwm4_default: pwm4_default {
+ function = "PWM4";
+ groups = "PWM4";
+ };
+
+ pinctrl_pwm5_default: pwm5_default {
+ function = "PWM5";
+ groups = "PWM5";
+ };
+
+ pinctrl_pwm6_default: pwm6_default {
+ function = "PWM6";
+ groups = "PWM6";
+ };
+
+ pinctrl_pwm7_default: pwm7_default {
+ function = "PWM7";
+ groups = "PWM7";
+ };
+
+ pinctrl_rgmii1_default: rgmii1_default {
+ function = "RGMII1";
+ groups = "RGMII1";
+ };
+
+ pinctrl_rgmii2_default: rgmii2_default {
+ function = "RGMII2";
+ groups = "RGMII2";
+ };
+
+ pinctrl_rmii1_default: rmii1_default {
+ function = "RMII1";
+ groups = "RMII1";
+ };
+
+ pinctrl_rmii2_default: rmii2_default {
+ function = "RMII2";
+ groups = "RMII2";
+ };
+
+ pinctrl_rom16_default: rom16_default {
+ function = "ROM16";
+ groups = "ROM16";
+ };
+
+ pinctrl_rom8_default: rom8_default {
+ function = "ROM8";
+ groups = "ROM8";
+ };
+
+ pinctrl_romcs1_default: romcs1_default {
+ function = "ROMCS1";
+ groups = "ROMCS1";
+ };
+
+ pinctrl_romcs2_default: romcs2_default {
+ function = "ROMCS2";
+ groups = "ROMCS2";
+ };
+
+ pinctrl_romcs3_default: romcs3_default {
+ function = "ROMCS3";
+ groups = "ROMCS3";
+ };
+
+ pinctrl_romcs4_default: romcs4_default {
+ function = "ROMCS4";
+ groups = "ROMCS4";
+ };
+
+ pinctrl_rxd1_default: rxd1_default {
+ function = "RXD1";
+ groups = "RXD1";
+ };
+
+ pinctrl_rxd2_default: rxd2_default {
+ function = "RXD2";
+ groups = "RXD2";
+ };
+
+ pinctrl_rxd3_default: rxd3_default {
+ function = "RXD3";
+ groups = "RXD3";
+ };
+
+ pinctrl_rxd4_default: rxd4_default {
+ function = "RXD4";
+ groups = "RXD4";
+ };
+
+ pinctrl_salt1_default: salt1_default {
+ function = "SALT1";
+ groups = "SALT1";
+ };
+
+ pinctrl_salt2_default: salt2_default {
+ function = "SALT2";
+ groups = "SALT2";
+ };
+
+ pinctrl_salt3_default: salt3_default {
+ function = "SALT3";
+ groups = "SALT3";
+ };
+
+ pinctrl_salt4_default: salt4_default {
+ function = "SALT4";
+ groups = "SALT4";
+ };
+
+ pinctrl_sd1_default: sd1_default {
+ function = "SD1";
+ groups = "SD1";
+ };
+
+ pinctrl_sd2_default: sd2_default {
+ function = "SD2";
+ groups = "SD2";
+ };
+
+ pinctrl_sgpmck_default: sgpmck_default {
+ function = "SGPMCK";
+ groups = "SGPMCK";
+ };
+
+ pinctrl_sgpmi_default: sgpmi_default {
+ function = "SGPMI";
+ groups = "SGPMI";
+ };
+
+ pinctrl_sgpmld_default: sgpmld_default {
+ function = "SGPMLD";
+ groups = "SGPMLD";
+ };
+
+ pinctrl_sgpmo_default: sgpmo_default {
+ function = "SGPMO";
+ groups = "SGPMO";
+ };
+
+ pinctrl_sgpsck_default: sgpsck_default {
+ function = "SGPSCK";
+ groups = "SGPSCK";
+ };
+
+ pinctrl_sgpsi0_default: sgpsi0_default {
+ function = "SGPSI0";
+ groups = "SGPSI0";
+ };
+
+ pinctrl_sgpsi1_default: sgpsi1_default {
+ function = "SGPSI1";
+ groups = "SGPSI1";
+ };
+
+ pinctrl_sgpsld_default: sgpsld_default {
+ function = "SGPSLD";
+ groups = "SGPSLD";
+ };
+
+ pinctrl_sioonctrl_default: sioonctrl_default {
+ function = "SIOONCTRL";
+ groups = "SIOONCTRL";
+ };
+
+ pinctrl_siopbi_default: siopbi_default {
+ function = "SIOPBI";
+ groups = "SIOPBI";
+ };
+
+ pinctrl_siopbo_default: siopbo_default {
+ function = "SIOPBO";
+ groups = "SIOPBO";
+ };
+
+ pinctrl_siopwreq_default: siopwreq_default {
+ function = "SIOPWREQ";
+ groups = "SIOPWREQ";
+ };
+
+ pinctrl_siopwrgd_default: siopwrgd_default {
+ function = "SIOPWRGD";
+ groups = "SIOPWRGD";
+ };
+
+ pinctrl_sios3_default: sios3_default {
+ function = "SIOS3";
+ groups = "SIOS3";
+ };
+
+ pinctrl_sios5_default: sios5_default {
+ function = "SIOS5";
+ groups = "SIOS5";
+ };
+
+ pinctrl_siosci_default: siosci_default {
+ function = "SIOSCI";
+ groups = "SIOSCI";
+ };
+
+ pinctrl_spi1_default: spi1_default {
+ function = "SPI1";
+ groups = "SPI1";
+ };
+
+ pinctrl_spi1debug_default: spi1debug_default {
+ function = "SPI1DEBUG";
+ groups = "SPI1DEBUG";
+ };
+
+ pinctrl_spi1passthru_default: spi1passthru_default {
+ function = "SPI1PASSTHRU";
+ groups = "SPI1PASSTHRU";
+ };
+
+ pinctrl_spics1_default: spics1_default {
+ function = "SPICS1";
+ groups = "SPICS1";
+ };
+
+ pinctrl_timer3_default: timer3_default {
+ function = "TIMER3";
+ groups = "TIMER3";
+ };
+
+ pinctrl_timer4_default: timer4_default {
+ function = "TIMER4";
+ groups = "TIMER4";
+ };
+
+ pinctrl_timer5_default: timer5_default {
+ function = "TIMER5";
+ groups = "TIMER5";
+ };
+
+ pinctrl_timer6_default: timer6_default {
+ function = "TIMER6";
+ groups = "TIMER6";
+ };
+
+ pinctrl_timer7_default: timer7_default {
+ function = "TIMER7";
+ groups = "TIMER7";
+ };
+
+ pinctrl_timer8_default: timer8_default {
+ function = "TIMER8";
+ groups = "TIMER8";
+ };
+
+ pinctrl_txd1_default: txd1_default {
+ function = "TXD1";
+ groups = "TXD1";
+ };
+
+ pinctrl_txd2_default: txd2_default {
+ function = "TXD2";
+ groups = "TXD2";
+ };
+
+ pinctrl_txd3_default: txd3_default {
+ function = "TXD3";
+ groups = "TXD3";
+ };
+
+ pinctrl_txd4_default: txd4_default {
+ function = "TXD4";
+ groups = "TXD4";
+ };
+
+ pinctrl_uart6_default: uart6_default {
+ function = "UART6";
+ groups = "UART6";
+ };
+
+ pinctrl_usbcki_default: usbcki_default {
+ function = "USBCKI";
+ groups = "USBCKI";
+ };
+
+ pinctrl_vgabios_rom_default: vgabios_rom_default {
+ function = "VGABIOS_ROM";
+ groups = "VGABIOS_ROM";
+ };
+
+ pinctrl_vgahs_default: vgahs_default {
+ function = "VGAHS";
+ groups = "VGAHS";
+ };
+
+ pinctrl_vgavs_default: vgavs_default {
+ function = "VGAVS";
+ groups = "VGAVS";
+ };
+
+ pinctrl_vpi18_default: vpi18_default {
+ function = "VPI18";
+ groups = "VPI18";
+ };
+
+ pinctrl_vpi24_default: vpi24_default {
+ function = "VPI24";
+ groups = "VPI24";
+ };
+
+ pinctrl_vpi30_default: vpi30_default {
+ function = "VPI30";
+ groups = "VPI30";
+ };
+
+ pinctrl_vpo12_default: vpo12_default {
+ function = "VPO12";
+ groups = "VPO12";
+ };
+
+ pinctrl_vpo24_default: vpo24_default {
+ function = "VPO24";
+ groups = "VPO24";
+ };
+
+ pinctrl_wdtrst1_default: wdtrst1_default {
+ function = "WDTRST1";
+ groups = "WDTRST1";
+ };
+
+ pinctrl_wdtrst2_default: wdtrst2_default {
+ function = "WDTRST2";
+ groups = "WDTRST2";
+ };
+
+ };
+ };
+
clk_apb: clk_apb at 1e6e2008 {
#clock-cells = <0>;
compatible = "aspeed,g4-apb-clock";
--
2.9.3
^ permalink raw reply related
* [PATCH v4 2/6] arm: dts: aspeed-g4: Add gpio controller to devicetree
From: Andrew Jeffery @ 2016-12-06 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206035348.29948-1-andrew@aj.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b00dfc7a3bf7..20b75667286f 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -822,6 +822,16 @@
reg = <0x1e720000 0x8000>; // 32K
};
+ gpio: gpio at 1e780000 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2400-gpio";
+ reg = <0x1e780000 0x1000>;
+ interrupts = <20>;
+ gpio-ranges = <&pinctrl 0 0 220>;
+ interrupt-controller;
+ };
+
timer: timer at 1e782000 {
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
--
2.9.3
^ permalink raw reply related
* [PATCH v4 3/6] arm: dts: aspeed-g5: Add SoC Display Controller node
From: Andrew Jeffery @ 2016-12-06 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206035348.29948-1-andrew@aj.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index dd94d9361fda..c7ff3ea4bf37 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -71,6 +71,12 @@
reg = <0x1e6e202c 0x4>;
};
+ gfx: display at 1e6e6000 {
+ compatible = "aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ reg-io-width = <4>;
+ };
+
sram at 1e720000 {
compatible = "mmio-sram";
reg = <0x1e720000 0x9000>; // 36K
--
2.9.3
^ permalink raw reply related
* [PATCH v4 4/6] arm: dts: aspeed-g5: Add LPC Controller node
From: Andrew Jeffery @ 2016-12-06 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206035348.29948-1-andrew@aj.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index c7ff3ea4bf37..1968607326dd 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -92,6 +92,7 @@
clocks = <&clk_apb>;
};
+
wdt1: wdt at 1e785000 {
compatible = "aspeed,wdt";
reg = <0x1e785000 0x1c>;
@@ -121,6 +122,36 @@
status = "disabled";
};
+ lpc: lpc at 1e789000 {
+ compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1e789000 0x1000>;
+
+ lpc_bmc: lpc-bmc at 0 {
+ compatible = "aspeed,ast2500-lpc-bmc";
+ reg = <0x0 0x80>;
+ };
+
+ lpc_host: lpc-host at 80 {
+ compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x80 0x1e0>;
+
+ reg-io-width = <4>;
+
+ lhc: lhc at 20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+ };
+ };
+ };
+
uart2: serial at 1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x1000>;
--
2.9.3
^ permalink raw reply related
* [PATCH v4 5/6] arm: dts: aspeed-g5: Add syscon and pin controller nodes
From: Andrew Jeffery @ 2016-12-06 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206035348.29948-1-andrew@aj.id.au>
The pin controller's child nodes expose the functions currently
implemented in the g5 pin controller driver.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 816 +++++++++++++++++++++++++++++++++++++++
1 file changed, 816 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 1968607326dd..6ccabdb90e95 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -44,6 +44,822 @@
reg = <0x1e6e2070 0x04>;
};
+ syscon: syscon at 1e6e2000 {
+ compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g5-pinctrl";
+ aspeed,external-nodes = <&gfx &lhc>;
+
+ pinctrl_acpi_default: acpi_default {
+ function = "ACPI";
+ groups = "ACPI";
+ };
+
+ pinctrl_adc0_default: adc0_default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
+
+ pinctrl_adc1_default: adc1_default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
+
+ pinctrl_adc10_default: adc10_default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
+
+ pinctrl_adc11_default: adc11_default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
+
+ pinctrl_adc12_default: adc12_default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
+
+ pinctrl_adc13_default: adc13_default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
+
+ pinctrl_adc14_default: adc14_default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
+
+ pinctrl_adc15_default: adc15_default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
+
+ pinctrl_adc2_default: adc2_default {
+ function = "ADC2";
+ groups = "ADC2";
+ };
+
+ pinctrl_adc3_default: adc3_default {
+ function = "ADC3";
+ groups = "ADC3";
+ };
+
+ pinctrl_adc4_default: adc4_default {
+ function = "ADC4";
+ groups = "ADC4";
+ };
+
+ pinctrl_adc5_default: adc5_default {
+ function = "ADC5";
+ groups = "ADC5";
+ };
+
+ pinctrl_adc6_default: adc6_default {
+ function = "ADC6";
+ groups = "ADC6";
+ };
+
+ pinctrl_adc7_default: adc7_default {
+ function = "ADC7";
+ groups = "ADC7";
+ };
+
+ pinctrl_adc8_default: adc8_default {
+ function = "ADC8";
+ groups = "ADC8";
+ };
+
+ pinctrl_adc9_default: adc9_default {
+ function = "ADC9";
+ groups = "ADC9";
+ };
+
+ pinctrl_bmcint_default: bmcint_default {
+ function = "BMCINT";
+ groups = "BMCINT";
+ };
+
+ pinctrl_ddcclk_default: ddcclk_default {
+ function = "DDCCLK";
+ groups = "DDCCLK";
+ };
+
+ pinctrl_ddcdat_default: ddcdat_default {
+ function = "DDCDAT";
+ groups = "DDCDAT";
+ };
+
+ pinctrl_espi_default: espi_default {
+ function = "ESPI";
+ groups = "ESPI";
+ };
+
+ pinctrl_fwspics1_default: fwspics1_default {
+ function = "FWSPICS1";
+ groups = "FWSPICS1";
+ };
+
+ pinctrl_fwspics2_default: fwspics2_default {
+ function = "FWSPICS2";
+ groups = "FWSPICS2";
+ };
+
+ pinctrl_gpid0_default: gpid0_default {
+ function = "GPID0";
+ groups = "GPID0";
+ };
+
+ pinctrl_gpid2_default: gpid2_default {
+ function = "GPID2";
+ groups = "GPID2";
+ };
+
+ pinctrl_gpid4_default: gpid4_default {
+ function = "GPID4";
+ groups = "GPID4";
+ };
+
+ pinctrl_gpid6_default: gpid6_default {
+ function = "GPID6";
+ groups = "GPID6";
+ };
+
+ pinctrl_gpie0_default: gpie0_default {
+ function = "GPIE0";
+ groups = "GPIE0";
+ };
+
+ pinctrl_gpie2_default: gpie2_default {
+ function = "GPIE2";
+ groups = "GPIE2";
+ };
+
+ pinctrl_gpie4_default: gpie4_default {
+ function = "GPIE4";
+ groups = "GPIE4";
+ };
+
+ pinctrl_gpie6_default: gpie6_default {
+ function = "GPIE6";
+ groups = "GPIE6";
+ };
+
+ pinctrl_i2c10_default: i2c10_default {
+ function = "I2C10";
+ groups = "I2C10";
+ };
+
+ pinctrl_i2c11_default: i2c11_default {
+ function = "I2C11";
+ groups = "I2C11";
+ };
+
+ pinctrl_i2c12_default: i2c12_default {
+ function = "I2C12";
+ groups = "I2C12";
+ };
+
+ pinctrl_i2c13_default: i2c13_default {
+ function = "I2C13";
+ groups = "I2C13";
+ };
+
+ pinctrl_i2c14_default: i2c14_default {
+ function = "I2C14";
+ groups = "I2C14";
+ };
+
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+
+ pinctrl_i2c4_default: i2c4_default {
+ function = "I2C4";
+ groups = "I2C4";
+ };
+
+ pinctrl_i2c5_default: i2c5_default {
+ function = "I2C5";
+ groups = "I2C5";
+ };
+
+ pinctrl_i2c6_default: i2c6_default {
+ function = "I2C6";
+ groups = "I2C6";
+ };
+
+ pinctrl_i2c7_default: i2c7_default {
+ function = "I2C7";
+ groups = "I2C7";
+ };
+
+ pinctrl_i2c8_default: i2c8_default {
+ function = "I2C8";
+ groups = "I2C8";
+ };
+
+ pinctrl_i2c9_default: i2c9_default {
+ function = "I2C9";
+ groups = "I2C9";
+ };
+
+ pinctrl_lad0_default: lad0_default {
+ function = "LAD0";
+ groups = "LAD0";
+ };
+
+ pinctrl_lad1_default: lad1_default {
+ function = "LAD1";
+ groups = "LAD1";
+ };
+
+ pinctrl_lad2_default: lad2_default {
+ function = "LAD2";
+ groups = "LAD2";
+ };
+
+ pinctrl_lad3_default: lad3_default {
+ function = "LAD3";
+ groups = "LAD3";
+ };
+
+ pinctrl_lclk_default: lclk_default {
+ function = "LCLK";
+ groups = "LCLK";
+ };
+
+ pinctrl_lframe_default: lframe_default {
+ function = "LFRAME";
+ groups = "LFRAME";
+ };
+
+ pinctrl_lpchc_default: lpchc_default {
+ function = "LPCHC";
+ groups = "LPCHC";
+ };
+
+ pinctrl_lpcpd_default: lpcpd_default {
+ function = "LPCPD";
+ groups = "LPCPD";
+ };
+
+ pinctrl_lpcplus_default: lpcplus_default {
+ function = "LPCPLUS";
+ groups = "LPCPLUS";
+ };
+
+ pinctrl_lpcpme_default: lpcpme_default {
+ function = "LPCPME";
+ groups = "LPCPME";
+ };
+
+ pinctrl_lpcrst_default: lpcrst_default {
+ function = "LPCRST";
+ groups = "LPCRST";
+ };
+
+ pinctrl_lpcsmi_default: lpcsmi_default {
+ function = "LPCSMI";
+ groups = "LPCSMI";
+ };
+
+ pinctrl_lsirq_default: lsirq_default {
+ function = "LSIRQ";
+ groups = "LSIRQ";
+ };
+
+ pinctrl_mac1link_default: mac1link_default {
+ function = "MAC1LINK";
+ groups = "MAC1LINK";
+ };
+
+ pinctrl_mac2link_default: mac2link_default {
+ function = "MAC2LINK";
+ groups = "MAC2LINK";
+ };
+
+ pinctrl_mdio1_default: mdio1_default {
+ function = "MDIO1";
+ groups = "MDIO1";
+ };
+
+ pinctrl_mdio2_default: mdio2_default {
+ function = "MDIO2";
+ groups = "MDIO2";
+ };
+
+ pinctrl_ncts1_default: ncts1_default {
+ function = "NCTS1";
+ groups = "NCTS1";
+ };
+
+ pinctrl_ncts2_default: ncts2_default {
+ function = "NCTS2";
+ groups = "NCTS2";
+ };
+
+ pinctrl_ncts3_default: ncts3_default {
+ function = "NCTS3";
+ groups = "NCTS3";
+ };
+
+ pinctrl_ncts4_default: ncts4_default {
+ function = "NCTS4";
+ groups = "NCTS4";
+ };
+
+ pinctrl_ndcd1_default: ndcd1_default {
+ function = "NDCD1";
+ groups = "NDCD1";
+ };
+
+ pinctrl_ndcd2_default: ndcd2_default {
+ function = "NDCD2";
+ groups = "NDCD2";
+ };
+
+ pinctrl_ndcd3_default: ndcd3_default {
+ function = "NDCD3";
+ groups = "NDCD3";
+ };
+
+ pinctrl_ndcd4_default: ndcd4_default {
+ function = "NDCD4";
+ groups = "NDCD4";
+ };
+
+ pinctrl_ndsr1_default: ndsr1_default {
+ function = "NDSR1";
+ groups = "NDSR1";
+ };
+
+ pinctrl_ndsr2_default: ndsr2_default {
+ function = "NDSR2";
+ groups = "NDSR2";
+ };
+
+ pinctrl_ndsr3_default: ndsr3_default {
+ function = "NDSR3";
+ groups = "NDSR3";
+ };
+
+ pinctrl_ndsr4_default: ndsr4_default {
+ function = "NDSR4";
+ groups = "NDSR4";
+ };
+
+ pinctrl_ndtr1_default: ndtr1_default {
+ function = "NDTR1";
+ groups = "NDTR1";
+ };
+
+ pinctrl_ndtr2_default: ndtr2_default {
+ function = "NDTR2";
+ groups = "NDTR2";
+ };
+
+ pinctrl_ndtr3_default: ndtr3_default {
+ function = "NDTR3";
+ groups = "NDTR3";
+ };
+
+ pinctrl_ndtr4_default: ndtr4_default {
+ function = "NDTR4";
+ groups = "NDTR4";
+ };
+
+ pinctrl_nri1_default: nri1_default {
+ function = "NRI1";
+ groups = "NRI1";
+ };
+
+ pinctrl_nri2_default: nri2_default {
+ function = "NRI2";
+ groups = "NRI2";
+ };
+
+ pinctrl_nri3_default: nri3_default {
+ function = "NRI3";
+ groups = "NRI3";
+ };
+
+ pinctrl_nri4_default: nri4_default {
+ function = "NRI4";
+ groups = "NRI4";
+ };
+
+ pinctrl_nrts1_default: nrts1_default {
+ function = "NRTS1";
+ groups = "NRTS1";
+ };
+
+ pinctrl_nrts2_default: nrts2_default {
+ function = "NRTS2";
+ groups = "NRTS2";
+ };
+
+ pinctrl_nrts3_default: nrts3_default {
+ function = "NRTS3";
+ groups = "NRTS3";
+ };
+
+ pinctrl_nrts4_default: nrts4_default {
+ function = "NRTS4";
+ groups = "NRTS4";
+ };
+
+ pinctrl_oscclk_default: oscclk_default {
+ function = "OSCCLK";
+ groups = "OSCCLK";
+ };
+
+ pinctrl_pewake_default: pewake_default {
+ function = "PEWAKE";
+ groups = "PEWAKE";
+ };
+
+ pinctrl_pnor_default: pnor_default {
+ function = "PNOR";
+ groups = "PNOR";
+ };
+
+ pinctrl_pwm0_default: pwm0_default {
+ function = "PWM0";
+ groups = "PWM0";
+ };
+
+ pinctrl_pwm1_default: pwm1_default {
+ function = "PWM1";
+ groups = "PWM1";
+ };
+
+ pinctrl_pwm2_default: pwm2_default {
+ function = "PWM2";
+ groups = "PWM2";
+ };
+
+ pinctrl_pwm3_default: pwm3_default {
+ function = "PWM3";
+ groups = "PWM3";
+ };
+
+ pinctrl_pwm4_default: pwm4_default {
+ function = "PWM4";
+ groups = "PWM4";
+ };
+
+ pinctrl_pwm5_default: pwm5_default {
+ function = "PWM5";
+ groups = "PWM5";
+ };
+
+ pinctrl_pwm6_default: pwm6_default {
+ function = "PWM6";
+ groups = "PWM6";
+ };
+
+ pinctrl_pwm7_default: pwm7_default {
+ function = "PWM7";
+ groups = "PWM7";
+ };
+
+ pinctrl_rgmii1_default: rgmii1_default {
+ function = "RGMII1";
+ groups = "RGMII1";
+ };
+
+ pinctrl_rgmii2_default: rgmii2_default {
+ function = "RGMII2";
+ groups = "RGMII2";
+ };
+
+ pinctrl_rmii1_default: rmii1_default {
+ function = "RMII1";
+ groups = "RMII1";
+ };
+
+ pinctrl_rmii2_default: rmii2_default {
+ function = "RMII2";
+ groups = "RMII2";
+ };
+
+ pinctrl_rxd1_default: rxd1_default {
+ function = "RXD1";
+ groups = "RXD1";
+ };
+
+ pinctrl_rxd2_default: rxd2_default {
+ function = "RXD2";
+ groups = "RXD2";
+ };
+
+ pinctrl_rxd3_default: rxd3_default {
+ function = "RXD3";
+ groups = "RXD3";
+ };
+
+ pinctrl_rxd4_default: rxd4_default {
+ function = "RXD4";
+ groups = "RXD4";
+ };
+
+ pinctrl_salt1_default: salt1_default {
+ function = "SALT1";
+ groups = "SALT1";
+ };
+
+ pinctrl_salt10_default: salt10_default {
+ function = "SALT10";
+ groups = "SALT10";
+ };
+
+ pinctrl_salt11_default: salt11_default {
+ function = "SALT11";
+ groups = "SALT11";
+ };
+
+ pinctrl_salt12_default: salt12_default {
+ function = "SALT12";
+ groups = "SALT12";
+ };
+
+ pinctrl_salt13_default: salt13_default {
+ function = "SALT13";
+ groups = "SALT13";
+ };
+
+ pinctrl_salt14_default: salt14_default {
+ function = "SALT14";
+ groups = "SALT14";
+ };
+
+ pinctrl_salt2_default: salt2_default {
+ function = "SALT2";
+ groups = "SALT2";
+ };
+
+ pinctrl_salt3_default: salt3_default {
+ function = "SALT3";
+ groups = "SALT3";
+ };
+
+ pinctrl_salt4_default: salt4_default {
+ function = "SALT4";
+ groups = "SALT4";
+ };
+
+ pinctrl_salt5_default: salt5_default {
+ function = "SALT5";
+ groups = "SALT5";
+ };
+
+ pinctrl_salt6_default: salt6_default {
+ function = "SALT6";
+ groups = "SALT6";
+ };
+
+ pinctrl_salt7_default: salt7_default {
+ function = "SALT7";
+ groups = "SALT7";
+ };
+
+ pinctrl_salt8_default: salt8_default {
+ function = "SALT8";
+ groups = "SALT8";
+ };
+
+ pinctrl_salt9_default: salt9_default {
+ function = "SALT9";
+ groups = "SALT9";
+ };
+
+ pinctrl_scl1_default: scl1_default {
+ function = "SCL1";
+ groups = "SCL1";
+ };
+
+ pinctrl_scl2_default: scl2_default {
+ function = "SCL2";
+ groups = "SCL2";
+ };
+
+ pinctrl_sd1_default: sd1_default {
+ function = "SD1";
+ groups = "SD1";
+ };
+
+ pinctrl_sd2_default: sd2_default {
+ function = "SD2";
+ groups = "SD2";
+ };
+
+ pinctrl_sda1_default: sda1_default {
+ function = "SDA1";
+ groups = "SDA1";
+ };
+
+ pinctrl_sda2_default: sda2_default {
+ function = "SDA2";
+ groups = "SDA2";
+ };
+
+ pinctrl_sgps1_default: sgps1_default {
+ function = "SGPS1";
+ groups = "SGPS1";
+ };
+
+ pinctrl_sgps2_default: sgps2_default {
+ function = "SGPS2";
+ groups = "SGPS2";
+ };
+
+ pinctrl_sioonctrl_default: sioonctrl_default {
+ function = "SIOONCTRL";
+ groups = "SIOONCTRL";
+ };
+
+ pinctrl_siopbi_default: siopbi_default {
+ function = "SIOPBI";
+ groups = "SIOPBI";
+ };
+
+ pinctrl_siopbo_default: siopbo_default {
+ function = "SIOPBO";
+ groups = "SIOPBO";
+ };
+
+ pinctrl_siopwreq_default: siopwreq_default {
+ function = "SIOPWREQ";
+ groups = "SIOPWREQ";
+ };
+
+ pinctrl_siopwrgd_default: siopwrgd_default {
+ function = "SIOPWRGD";
+ groups = "SIOPWRGD";
+ };
+
+ pinctrl_sios3_default: sios3_default {
+ function = "SIOS3";
+ groups = "SIOS3";
+ };
+
+ pinctrl_sios5_default: sios5_default {
+ function = "SIOS5";
+ groups = "SIOS5";
+ };
+
+ pinctrl_siosci_default: siosci_default {
+ function = "SIOSCI";
+ groups = "SIOSCI";
+ };
+
+ pinctrl_spi1_default: spi1_default {
+ function = "SPI1";
+ groups = "SPI1";
+ };
+
+ pinctrl_spi1cs1_default: spi1cs1_default {
+ function = "SPI1CS1";
+ groups = "SPI1CS1";
+ };
+
+ pinctrl_spi1debug_default: spi1debug_default {
+ function = "SPI1DEBUG";
+ groups = "SPI1DEBUG";
+ };
+
+ pinctrl_spi1passthru_default: spi1passthru_default {
+ function = "SPI1PASSTHRU";
+ groups = "SPI1PASSTHRU";
+ };
+
+ pinctrl_spi2ck_default: spi2ck_default {
+ function = "SPI2CK";
+ groups = "SPI2CK";
+ };
+
+ pinctrl_spi2cs0_default: spi2cs0_default {
+ function = "SPI2CS0";
+ groups = "SPI2CS0";
+ };
+
+ pinctrl_spi2cs1_default: spi2cs1_default {
+ function = "SPI2CS1";
+ groups = "SPI2CS1";
+ };
+
+ pinctrl_spi2miso_default: spi2miso_default {
+ function = "SPI2MISO";
+ groups = "SPI2MISO";
+ };
+
+ pinctrl_spi2mosi_default: spi2mosi_default {
+ function = "SPI2MOSI";
+ groups = "SPI2MOSI";
+ };
+
+ pinctrl_timer3_default: timer3_default {
+ function = "TIMER3";
+ groups = "TIMER3";
+ };
+
+ pinctrl_timer4_default: timer4_default {
+ function = "TIMER4";
+ groups = "TIMER4";
+ };
+
+ pinctrl_timer5_default: timer5_default {
+ function = "TIMER5";
+ groups = "TIMER5";
+ };
+
+ pinctrl_timer6_default: timer6_default {
+ function = "TIMER6";
+ groups = "TIMER6";
+ };
+
+ pinctrl_timer7_default: timer7_default {
+ function = "TIMER7";
+ groups = "TIMER7";
+ };
+
+ pinctrl_timer8_default: timer8_default {
+ function = "TIMER8";
+ groups = "TIMER8";
+ };
+
+ pinctrl_txd1_default: txd1_default {
+ function = "TXD1";
+ groups = "TXD1";
+ };
+
+ pinctrl_txd2_default: txd2_default {
+ function = "TXD2";
+ groups = "TXD2";
+ };
+
+ pinctrl_txd3_default: txd3_default {
+ function = "TXD3";
+ groups = "TXD3";
+ };
+
+ pinctrl_txd4_default: txd4_default {
+ function = "TXD4";
+ groups = "TXD4";
+ };
+
+ pinctrl_uart6_default: uart6_default {
+ function = "UART6";
+ groups = "UART6";
+ };
+
+ pinctrl_usbcki_default: usbcki_default {
+ function = "USBCKI";
+ groups = "USBCKI";
+ };
+
+ pinctrl_vgabiosrom_default: vgabiosrom_default {
+ function = "VGABIOSROM";
+ groups = "VGABIOSROM";
+ };
+
+ pinctrl_vgahs_default: vgahs_default {
+ function = "VGAHS";
+ groups = "VGAHS";
+ };
+
+ pinctrl_vgavs_default: vgavs_default {
+ function = "VGAVS";
+ groups = "VGAVS";
+ };
+
+ pinctrl_vpi24_default: vpi24_default {
+ function = "VPI24";
+ groups = "VPI24";
+ };
+
+ pinctrl_vpo_default: vpo_default {
+ function = "VPO";
+ groups = "VPO";
+ };
+
+ pinctrl_wdtrst1_default: wdtrst1_default {
+ function = "WDTRST1";
+ groups = "WDTRST1";
+ };
+
+ pinctrl_wdtrst2_default: wdtrst2_default {
+ function = "WDTRST2";
+ groups = "WDTRST2";
+ };
+
+ };
+ };
+
clk_hpll: clk_hpll at 1e6e2024 {
#clock-cells = <0>;
compatible = "aspeed,g5-hpll-clock";
--
2.9.3
^ permalink raw reply related
* [PATCH v4 6/6] arm: dts: aspeed-g5: Add gpio controller to devicetree
From: Andrew Jeffery @ 2016-12-06 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206035348.29948-1-andrew@aj.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 6ccabdb90e95..a95c1b08a816 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -898,6 +898,16 @@
reg = <0x1e720000 0x9000>; // 36K
};
+ gpio: gpio at 1e780000 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2500-gpio";
+ reg = <0x1e780000 0x1000>;
+ interrupts = <20>;
+ gpio-ranges = <&pinctrl 0 0 220>;
+ interrupt-controller;
+ };
+
timer: timer at 1e782000 {
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
--
2.9.3
^ permalink raw reply related
* [RESEND PATCH V6 5/6] dmaengine: pl330: Make sure microcode is privileged
From: Vinod Koul @ 2016-12-06 5:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1480690509-13490-6-git-send-email-sricharan@codeaurora.org>
On Fri, Dec 02, 2016 at 08:25:08PM +0530, Sricharan R wrote:
> From: Mitchel Humpherys <mitchelh@codeaurora.org>
>
> The PL330 performs privileged instruction fetches. This can result in
> SMMU permission faults on SMMUs that implement the ARMv8 VMSA, which
> specifies that mappings that are writeable at one execution level shall
> not be executable at any higher-privileged level. Fix this by using the
> DMA_ATTR_PRIVILEGED attribute, which will ensure that the microcode
> IOMMU mapping is only accessible to the privileged level.
Acked-by: Vinod Koul <vinod.koul@intel.com>
--
~Vinod
^ permalink raw reply
* Tearing down DMA transfer setup after DMA client has finished
From: Vinod Koul @ 2016-12-06 5:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20fc9020-7278-bc2f-2a8d-43aff5cabff8@free.fr>
On Tue, Nov 29, 2016 at 07:25:02PM +0100, Mason wrote:
Sorry I was away for a week in meeting with laptop down.
> [ Nothing new added below.
> Vinod, was the description of my HW's quirks clear enough?
Yes
> Is there a way to write a driver within the existing framework?
I think so, looking back at comments from Russell, I do tend to agree with
that. Is there a specfic reason why sbox can't be tied to alloc and free
channels?
> How can I get that HW block supported upstream?
> Regards. ]
>
> On 25/11/2016 13:46, Mason wrote:
>
> > On 25/11/2016 05:55, Vinod Koul wrote:
> >
> >> On Wed, Nov 23, 2016 at 11:25:44AM +0100, Mason wrote:
> >>
> >>> On my platform, setting up a DMA transfer is a two-step process:
> >>>
> >>> 1) configure the "switch box" to connect a device to a memory channel
> >>> 2) configure the transfer details (address, size, command)
> >>>
> >>> When the transfer is done, the sbox setup can be torn down,
> >>> and the DMA driver can start another transfer.
> >>>
> >>> The current software architecture for my NFC (NAND Flash controller)
> >>> driver is as follows (for one DMA transfer).
> >>>
> >>> sg_init_one
> >>> dma_map_sg
> >>> dmaengine_prep_slave_sg
> >>> dmaengine_submit
> >>> dma_async_issue_pending
> >>> configure_NFC_transfer
> >>> wait_for_IRQ_from_DMA_engine // via DMA_PREP_INTERRUPT
> >>> wait_for_NFC_idle
> >>> dma_unmap_sg
> >>
> >> Looking at thread and discussion now, first thinking would be to ensure
> >> the transaction is completed properly and then isr fired. You may need
> >> to talk to your HW designers to find a way for that. It is quite common
> >> that DMA controllers will fire and complete whereas the transaction is
> >> still in flight.
> >
> > It seems there is a disconnect between what Linux expects - an IRQ
> > when the transfer is complete - and the quirks of this HW :-(
> >
> > On this system, there are MBUS "agents" connected via a "switch box".
> > An agent fires an IRQ when it has dealt with its *half* of the transfer.
> >
> > SOURCE_AGENT <---> SBOX <---> DESTINATION_AGENT
> >
> > Here are the steps for a transfer, in the general case:
> >
> > 1) setup the sbox to connect SOURCE TO DEST
> > 2) configure source to send N bytes
> > 3) configure dest to receive N bytes
> >
> > When SOURCE_AGENT has sent N bytes, it fires an IRQ
> > When DEST_AGENT has received N bytes, it fires an IRQ
> > The sbox connection can be torn down only when the destination
> > agent has received all bytes.
> > (And the twist is that some agents do not have an IRQ line.)
> >
> > The system provides 3 RAM-to-sbox agents (read channels)
> > and 3 sbox-to-RAM agents (write channels).
> >
> > The NAND Flash controller read and write agents do not have
> > IRQ lines.
> >
> > So for a NAND-to-memory transfer (read from device)
> > - nothing happens when the NFC has finished sending N bytes to the sbox
> > - the write channel fires an IRQ when it has received N bytes
> >
> > In that case, one IRQ fires when the transfer is complete,
> > like Linux expects.
> >
> > For a memory-to-NAND transfer (write to device)
> > - the read channel fires an IRQ when it has sent N bytes
> > - the NFC driver is supposed to poll the NFC to determine
> > when the controller has finished writing N bytes
> >
> > In that case, the IRQ does not indicate that the transfer
> > is complete, merely that the sending half has finished
> > its part.
> >
> > For a memory-to-memory transfer (memcpy)
> > - the read channel fires an IRQ when it has sent N bytes
> > - the write channel fires an IRQ when it has received N bytes
> >
> > So you actually get two IRQs in that case, which I don't
> > think Linux (or the current DMA driver) expects.
> >
> > I'm not sure how we're supposed to handle this kind of HW
> > in Linux? (That's why I started this thread.)
> >
> >
> >> If that is not doable, then since you claim this is custom part which
> >> other vendors won't use (hope we are wrong down the line),
> >
> > I'm not sure how to interpret "you claim this is custom part".
> > Do you mean I may be wrong, that it is not custom?
> > I don't know if other vendors may have HW with the same
> > quirky behavior. What do you mean about being wrong down
> > the line?
> >
> >> then we can have a custom api,
> >>
> >> foo_sbox_configure(bool enable, ...);
> >>
> >> This can be invoked from NFC driver when required for configuration and
> >> teardown. For very specific cases where people need some specific
> >> configuration we do allow custom APIs.
> >
> > I don't think that would work. The fundamental issue is
> > that Linux expects a single IRQ to indicate "transfer
> > complete". And the driver (as written) starts a new
> > transfer as soon as the IRQ fires.
> >
> > But the HW may generate 0, 1, or even 2 IRQs for a single
> > transfer. And when there is a single IRQ, it may not
> > indicate "transfer complete" (as seen above).
> >
> >> Only problem with that would be it wont be a generic solution
> >> and you seem to be fine with that.
> >
> > I think it is possible to have a generic solution:
> > Right now, the callback is called from tasklet context.
> > If we can have a new flag to have the callback invoked
> > directly from the ISR, then the driver for the client
> > device can do what is required.
> >
> > For example, the NFC driver waits for the IRQ from the
> > memory agent, and then polls the controller itself.
> >
> > I can whip up a proof-of-concept if it's better to
> > illustrate with a patch?
>
--
~Vinod
^ permalink raw reply
* ILP32 for ARM64: testing with glibc testsuite
From: Yury Norov @ 2016-12-06 5:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d4dedc32-b324-107d-7de1-d1e670ffc00a@huawei.com>
On Mon, Dec 05, 2016 at 06:24:11PM +0800, Zhangjian (Bamvor) wrote:
>
>
> On 2016/12/5 18:07, Andreas Schwab wrote:
> >On Dez 05 2016, "Zhangjian (Bamvor)" <bamvor.zhangjian@huawei.com> wrote:
> >
> >>Is there some progresses on it? We could collabrate to fix those issues.
> >
> >All the elf/nptl/rt fails should be fixed by the recent binutils fixes.
> Cool. How about the conform and other failures?
I think conform is only my local problem. I use pretty non-standard
environment for build and testing - cross-compilation + qemu. Steve
builds and runs tests natively, and he doesn't see that regressions.
Yury
^ permalink raw reply
* [PATCH 16/18] arm64: ptrace: handle ptrace_request differently for aarch32 and ilp32
From: Yury Norov @ 2016-12-06 6:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161205163422.GG14429@e104818-lin.cambridge.arm.com>
On Mon, Dec 05, 2016 at 04:34:23PM +0000, Catalin Marinas wrote:
> On Fri, Oct 21, 2016 at 11:33:15PM +0300, Yury Norov wrote:
> > New aarch32 ptrace syscall handler is introduced to avoid run-time
> > detection of the task type.
>
> What's wrong with the run-time detection? If it's just to avoid a
> negligible overhead, I would rather keep the code simpler by avoiding
> duplicating the generic compat_sys_ptrace().
Nothing wrong. This is how Arnd asked me to do. You already asked this
question: http://lkml.iu.edu/hypermail/linux/kernel/1604.3/00930.html
If it's still looking weird to you, I can switch back to runtime
ptrace. But I'd like to see Arnd's opinion.
Yury.
^ permalink raw reply
* [PATCH 16/18] arm64: ptrace: handle ptrace_request differently for aarch32 and ilp32
From: Yury Norov @ 2016-12-06 6:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206062508.GA17835@yury-N73SV>
On Tue, Dec 06, 2016 at 11:55:08AM +0530, Yury Norov wrote:
> On Mon, Dec 05, 2016 at 04:34:23PM +0000, Catalin Marinas wrote:
> > On Fri, Oct 21, 2016 at 11:33:15PM +0300, Yury Norov wrote:
> > > New aarch32 ptrace syscall handler is introduced to avoid run-time
> > > detection of the task type.
> >
> > What's wrong with the run-time detection? If it's just to avoid a
> > negligible overhead, I would rather keep the code simpler by avoiding
> > duplicating the generic compat_sys_ptrace().
>
> Nothing wrong. This is how Arnd asked me to do. You already asked this
> question: http://lkml.iu.edu/hypermail/linux/kernel/1604.3/00930.html
>
> If it's still looking weird to you, I can switch back to runtime
> ptrace. But I'd like to see Arnd's opinion.
This is the Arnd's email:
https://patchwork.kernel.org/patch/7980521/
Yury.
^ permalink raw reply
* [LINUX RFC v4 3/4] mtd: spi-nor: add stripe support
From: Naga Sureshkumar Relli @ 2016-12-06 6:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <10b6175b-d26c-0266-96e3-0d6a471e76ee@atmel.com>
Hi Cyrille,
> -----Original Message-----
> From: Cyrille Pitchen [mailto:cyrille.pitchen at atmel.com]
> Sent: Monday, December 05, 2016 6:34 PM
> To: Naga Sureshkumar Relli <nagasure@xilinx.com>; broonie at kernel.org;
> michal.simek at xilinx.com; Soren Brinkmann <sorenb@xilinx.com>; Harini
> Katakam <harinik@xilinx.com>; Punnaiah Choudary Kalluri
> <punnaia@xilinx.com>
> Cc: linux-spi at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org; linux-mtd at lists.infradead.org
> Subject: Re: [LINUX RFC v4 3/4] mtd: spi-nor: add stripe support
>
> Hi Naga,
>
> Le 05/12/2016 ? 08:02, Naga Sureshkumar Relli a ?crit :
> > Hi Cyrille,
> >
> >>> Hi Cyrille,
> >>>
> >>>> I have not finished to review the whole series yet but here some
> >>>> first
> >>>> comments:
> >>>
> >>> Thanks for reviewing these patch series.
> >>>
> >>>>
> >>>> Le 27/11/2016 ? 09:33, Naga Sureshkumar Relli a ?crit :
> >>>>> This patch adds stripe support and it is needed for GQSPI parallel
> >>>>> configuration mode by:
> >>>>>
> >>>>> - Adding required parameters like stripe and shift to spi_nor
> >>>>> structure.
> >>>>> - Initializing all added parameters in spi_nor_scan()
> >>>>> - Updating read_sr() and read_fsr() for getting status from both
> >>>>> flashes
> >>>>> - Increasing page_size, sector_size, erase_size and toatal flash
> >>>>> size as and when required.
> >>>>> - Dividing address by 2
> >>>>> - Updating spi->master->flags for qspi driver to change CS
> >>>>>
> >>>>> Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
> >>>>> ---
> >>>>> Changes for v4:
> >>>>> - rename isparallel to stripe
> >>>>> Changes for v3:
> >>>>> - No change
> >>>>> Changes for v2:
> >>>>> - Splitted to separate MTD layer changes from SPI core changes
> >>>>> ---
> >>>>> drivers/mtd/spi-nor/spi-nor.c | 130
> >>>> ++++++++++++++++++++++++++++++++----------
> >>>>> include/linux/mtd/spi-nor.h | 2 +
> >>>>> 2 files changed, 103 insertions(+), 29 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/mtd/spi-nor/spi-nor.c
> >>>>> b/drivers/mtd/spi-nor/spi-nor.c index d0fc165..4252239 100644
> >>>>> --- a/drivers/mtd/spi-nor/spi-nor.c
> >>>>> +++ b/drivers/mtd/spi-nor/spi-nor.c
> >>>>> @@ -22,6 +22,7 @@
> >>>>> #include <linux/of_platform.h>
> >>>>> #include <linux/spi/flash.h>
> >>>>> #include <linux/mtd/spi-nor.h>
> >>>>> +#include <linux/spi/spi.h>
> >>>>>
> >>>>> /* Define max times to check status register before we give up.
> >>>>> */
> >>>>>
> >>>>> @@ -89,15 +90,24 @@ static const struct flash_info
> >>>>> *spi_nor_match_id(const char *name); static int read_sr(struct
> >>>>> spi_nor *nor) {
> >>>>> int ret;
> >>>>> - u8 val;
> >>>>> + u8 val[2];
> >>>>>
> >>>>> - ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
> >>>>> - if (ret < 0) {
> >>>>> - pr_err("error %d reading SR\n", (int) ret);
> >>>>> - return ret;
> >>>>> + if (nor->stripe) {
> >>>>> + ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val[0], 2);
> >>>>> + if (ret < 0) {
> >>>>> + pr_err("error %d reading SR\n", (int) ret);
> >>>>> + return ret;
> >>>>> + }
> >>>>> + val[0] |= val[1];
> >>>> Why '|' rather than '&' ?
> >>>> I guess because of the 'Write In Progress/Busy' bit: when called by
> >>>> spi_nor_sr_ready(), you want to be sure that this 'BUSY' bit is
> >>>> cleared on both memories.
> >>>>
> >>>> But what about when the Status Register is read for purpose other
> >>>> than checking the state of the 'BUSY' bit?
> >>>>
> >>> Yes you are correct, I will change this.
> >>>
> >>>> What about SPI controllers supporting more than 2 memories in
> parallel?
> >>>>
> >>>> This solution might fit the ZynqMP controller but doesn't look so
> generic.
> >>>>
> >>>>> + } else {
> >>>>> + ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val[0], 1);
> >>>>> + if (ret < 0) {
> >>>>> + pr_err("error %d reading SR\n", (int) ret);
> >>>>> + return ret;
> >>>>> + }
> >>>>> }
> >>>>>
> >>>>> - return val;
> >>>>> + return val[0];
> >>>>> }
> >>>>>
> >>>>> /*
> >>>>> @@ -108,15 +118,24 @@ static int read_sr(struct spi_nor *nor)
> >>>>> static int read_fsr(struct spi_nor *nor) {
> >>>>> int ret;
> >>>>> - u8 val;
> >>>>> + u8 val[2];
> >>>>>
> >>>>> - ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
> >>>>> - if (ret < 0) {
> >>>>> - pr_err("error %d reading FSR\n", ret);
> >>>>> - return ret;
> >>>>> + if (nor->stripe) {
> >>>>> + ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val[0], 2);
> >>>>> + if (ret < 0) {
> >>>>> + pr_err("error %d reading FSR\n", ret);
> >>>>> + return ret;
> >>>>> + }
> >>>>> + val[0] &= val[1];
> >>>> Same comment here: why '&' rather than '|'?
> >>>> Surely because of the the 'READY' bit which should be set for both
> >> memories.
> >>> I will update this also.
> >>>>
> >>>>> + } else {
> >>>>> + ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val[0], 1);
> >>>>> + if (ret < 0) {
> >>>>> + pr_err("error %d reading FSR\n", ret);
> >>>>> + return ret;
> >>>>> + }
> >>>>> }
> >>>>>
> >>>>> - return val;
> >>>>> + return val[0];
> >>>>> }
> >>>>>
> >>>>> /*
> >>>>> @@ -290,9 +309,16 @@ static int spi_nor_wait_till_ready(struct
> >>>>> spi_nor
> >>>> *nor)
> >>>>> */
> >>>>> static int erase_chip(struct spi_nor *nor) {
> >>>>> + u32 ret;
> >>>>> +
> >>>>> dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >>
> >>>>> 10));
> >>>>>
> >>>>> - return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
> >>>>> + ret = nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); if
> >>>>> + (ret)
> >>>>> + return ret;
> >>>>> +
> >>>>> + return ret;
> >>>>> +
> >>>>
> >>>> if (ret)
> >>>> return ret;
> >>>> else
> >>>> return ret;
> >>>>
> >>>> This chunk should be removed, it doesn't ease the patch review ;)
> >>> Ok, I will remove.
> >>>>
> >>>>> }
> >>>>>
> >>>>> static int spi_nor_lock_and_prep(struct spi_nor *nor, enum
> >>>>> spi_nor_ops ops) @@ -349,7 +375,7 @@ static int
> >>>>> spi_nor_erase_sector(struct spi_nor *nor, u32 addr) static int
> >>>>> spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) {
> >>>>> struct spi_nor *nor = mtd_to_spi_nor(mtd);
> >>>>> - u32 addr, len;
> >>>>> + u32 addr, len, offset;
> >>>>> uint32_t rem;
> >>>>> int ret;
> >>>>>
> >>>>> @@ -399,9 +425,13 @@ static int spi_nor_erase(struct mtd_info
> >>>>> *mtd,
> >>>> struct erase_info *instr)
> >>>>> /* "sector"-at-a-time erase */
> >>>>> } else {
> >>>>> while (len) {
> >>>>> +
> >>>>> write_enable(nor);
> >>>>> + offset = addr;
> >>>>> + if (nor->stripe)
> >>>>> + offset /= 2;
> >>>>
> >>>> I guess this should be /= 4 for controllers supporting 4 memories
> >>>> in
> >> parallel.
> >>>> Shouldn't you use nor->shift and define shift as an unsigned int
> >>>> instead of a bool?
> >>>> offset >>= nor->shift;
> >>>>
> >>> Yes we can use this shift, I will update
> >>>
> >>>> Anyway, by tuning the address here in spi-nor.c rather than in the
> >>>> SPI controller driver, you impose a model to support parallel
> >>>> memories that might not be suited to other controllers.
> >>>
> >>> For this ZynqMP GQSPI controller parallel configuration, globally
> >>> spi-nor should know about this stripe feature And based on that
> >>> address
> >> has to change.
> >>> As I mentioned in cover letter, this controller in parallel
> >>> configuration will
> >> work with even addresses only.
> >>> i.e. Before creating address format(m25p_addr2cmd) in mtd layer,
> >>> spi-nor
> >> should change that address based on stripe option.
> >>>
> >>> I am updating this offset based on stripe option, and stripe option
> >>> will
> >> update by reading dt property in nor_scan().
> >>> So the controller which doesn't support, then the stripe will be zero.
> >>> Or Can you please suggest any other way?
> >>>
> >>>>
> >>>>>
> >>>>> - ret = spi_nor_erase_sector(nor, addr);
> >>>>> + ret = spi_nor_erase_sector(nor, offset);
> >>>>> if (ret)
> >>>>> goto erase_err;
> >>>>>
> >>>>> @@ -525,6 +555,8 @@ static int stm_lock(struct spi_nor *nor,
> >>>>> loff_t ofs,
> >>>> uint64_t len)
> >>>>> bool use_top;
> >>>>> int ret;
> >>>>>
> >>>>> + ofs = ofs >> nor->shift;
> >>>>> +
> >>>>> status_old = read_sr(nor);
> >>>>> if (status_old < 0)
> >>>>> return status_old;
> >>>>> @@ -610,6 +642,8 @@ static int stm_unlock(struct spi_nor *nor,
> >>>>> loff_t ofs,
> >>>> uint64_t len)
> >>>>> bool use_top;
> >>>>> int ret;
> >>>>>
> >>>>> + ofs = ofs >> nor->shift;
> >>>>> +
> >>>>> status_old = read_sr(nor);
> >>>>> if (status_old < 0)
> >>>>> return status_old;
> >>>>> @@ -709,6 +743,8 @@ static int spi_nor_lock(struct mtd_info *mtd,
> >>>>> loff_t
> >>>> ofs, uint64_t len)
> >>>>> if (ret)
> >>>>> return ret;
> >>>>>
> >>>>> + ofs = ofs >> nor->shift;
> >>>>> +
> >>>>> ret = nor->flash_lock(nor, ofs, len);
> >>>>>
> >>>>> spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK); @@ -
> >>>> 724,6 +760,8
> >>>>> @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs,
> >>>>> uint64_t
> >>>> len)
> >>>>> if (ret)
> >>>>> return ret;
> >>>>>
> >>>>> + ofs = ofs >> nor->shift;
> >>>>> +
> >>>>> ret = nor->flash_unlock(nor, ofs, len);
> >>>>>
> >>>>> spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); @@ -
> >>>> 1018,6 +1056,9
> >>>>> @@ static const struct flash_info *spi_nor_read_id(struct spi_nor
> *nor)
> >>>>> u8 id[SPI_NOR_MAX_ID_LEN];
> >>>>> const struct flash_info *info;
> >>>>>
> >>>>> + nor->spi->master->flags &= ~(SPI_MASTER_BOTH_CS |
> >>>>> + SPI_MASTER_DATA_STRIPE);
> >>>>> +
> >>>>> tmp = nor->read_reg(nor, SPINOR_OP_RDID, id,
> >>>> SPI_NOR_MAX_ID_LEN);
> >>>>> if (tmp < 0) {
> >>>>> dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
> >>>> @@ -1041,6
> >>>>> +1082,7 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t
> >>>>> +from,
> >>>>> size_t len, {
> >>>>> struct spi_nor *nor = mtd_to_spi_nor(mtd);
> >>>>> int ret;
> >>>>> + u32 offset = from;
> >>>>>
> >>>>> dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
> >>>>>
> >>>>> @@ -1049,7 +1091,13 @@ static int spi_nor_read(struct mtd_info
> >>>>> *mtd,
> >>>> loff_t from, size_t len,
> >>>>> return ret;
> >>>>>
> >>>>> while (len) {
> >>>>> - ret = nor->read(nor, from, len, buf);
> >>>>> +
> >>>>> + offset = from;
> >>>>> +
> >>>>> + if (nor->stripe)
> >>>>> + offset /= 2;
> >>>>> +
> >>>>> + ret = nor->read(nor, offset, len, buf);
> >>>>> if (ret == 0) {
> >>>>> /* We shouldn't see 0-length reads */
> >>>>> ret = -EIO;
> >>>>> @@ -1161,6 +1209,7 @@ static int spi_nor_write(struct mtd_info
> >>>>> *mtd,
> >>>> loff_t to, size_t len,
> >>>>> struct spi_nor *nor = mtd_to_spi_nor(mtd);
> >>>>> size_t page_offset, page_remain, i;
> >>>>> ssize_t ret;
> >>>>> + u32 offset;
> >>>>>
> >>>>> dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
> >>>>>
> >>>>> @@ -1178,9 +1227,13 @@ static int spi_nor_write(struct mtd_info
> >>>>> *mtd,
> >>>> loff_t to, size_t len,
> >>>>> /* the size of data remaining on the first page */
> >>>>> page_remain = min_t(size_t,
> >>>>> nor->page_size - page_offset, len -
> >>>>> i);
> >>>>> + offset = (to + i);
> >>>>> +
> >>>>> + if (nor->stripe)
> >>>>> + offset /= 2;
> >>>>>
> >>>>> write_enable(nor);
> >>>>> - ret = nor->write(nor, to + i, page_remain, buf + i);
> >>>>> + ret = nor->write(nor, (offset), page_remain, buf + i);
> >>>>> if (ret < 0)
> >>>>> goto write_err;
> >>>>> written = ret;
> >>>>> @@ -1302,22 +1355,22 @@ static int spi_nor_check(struct spi_nor
> >>>>> *nor)
> >>>>>
> >>>>> int spi_nor_scan(struct spi_nor *nor, const char *name, enum
> >>>>> read_mode mode) {
> >>>>> - const struct flash_info *info = NULL;
> >>>>> + struct flash_info *info = NULL;
> >>>>
> >>>> You should not remove the const and should not try to modify
> >>>> members of *info.
> >>>>
> >>>>> struct device *dev = nor->dev;
> >>>>> struct mtd_info *mtd = &nor->mtd;
> >>>>> struct device_node *np = spi_nor_get_flash_node(nor);
> >>>>> - int ret;
> >>>>> - int i;
> >>>>> + struct device_node *np_spi;
> >>>>> + int ret, i, xlnx_qspi_mode;
> >>>>>
> >>>>> ret = spi_nor_check(nor);
> >>>>> if (ret)
> >>>>> return ret;
> >>>>>
> >>>>> if (name)
> >>>>> - info = spi_nor_match_id(name);
> >>>>> + info = (struct flash_info *)spi_nor_match_id(name);
> >>>>> /* Try to auto-detect if chip name wasn't specified or not found */
> >>>>> if (!info)
> >>>>> - info = spi_nor_read_id(nor);
> >>>>> + info = (struct flash_info *)spi_nor_read_id(nor);
> >>>>> if (IS_ERR_OR_NULL(info))
> >>>>> return -ENOENT;
> >>>>>
> >>>> Both spi_nor_match_id() and spi_nor_read_id(), when they succeed,
> >>>> return a pointer to an entry of the spi_nor_ids[] array, which is
> >>>> located in a read- only memory area.
> >>>>
> >>>> Since your patch doesn't remove the const attribute of the
> >>>> spi_nor_ids[], I wonder whether it has been tested. I expect it not
> >>>> to work on most architecture.
> >>>>
> >>>> Anyway spi_nor_ids[] should remain const. Let's take the case of
> >>>> eXecution In Place (XIP) from an external memory: if spi_nor_ids[]
> >>>> is const, it can be read directly from this external (read-only)
> >>>> memory and we never need to copy the array in RAM, so we save
> some
> >>>> KB of
> >> RAM.
> >>>> This is just an example but I guess we can find other reasons to
> >>>> keep this array const.
> >>>>
> >>>>> @@ -1341,7 +1394,7 @@ int spi_nor_scan(struct spi_nor *nor, const
> >>>>> char
> >>>> *name, enum read_mode mode)
> >>>>> */
> >>>>> dev_warn(dev, "found %s, expected %s\n",
> >>>>> jinfo->name, info->name);
> >>>>> - info = jinfo;
> >>>>> + info = (struct flash_info *)jinfo;
> >>>>> }
> >>>>> }
> >>>>>
> >>>>> @@ -1370,6 +1423,27 @@ int spi_nor_scan(struct spi_nor *nor, const
> >>>>> char
> >>>> *name, enum read_mode mode)
> >>>>> mtd->size = info->sector_size * info->n_sectors;
> >>>>> mtd->_erase = spi_nor_erase;
> >>>>> mtd->_read = spi_nor_read;
> >>>>> +#ifdef CONFIG_OF
> >>>>> + np_spi = of_get_next_parent(np);
> >>>>> +
> >>>>> + if (of_property_read_u32(np_spi, "xlnx,qspi-mode",
> >>>>> + &xlnx_qspi_mode) < 0) {
> >>>> This really looks controller specific so should not be placed in
> >>>> the generic spi- nor.c file.
> >>>
> >>> Const is removed in info struct, because to update info members
> >>> based
> >> parallel configuration.
> >>> As I mentioned above, for this parallel configuration, mtd and
> >>> spi-nor should know the details like
> >>> mtd->size, info->sectors, sector_size and page_size.
> >>
> >> You can tune the values of nor->mtd.size, nor->mtd.erasesize, nor-
> >>> page_size or whatever member of nor/nor.mtd as needed without ever
> >> modifying members of *info.
> >>
> >> If you modify *info then spi_nor_scan() is called a 2nd time to probe
> >> and configure SPI memories of the same part but connected to another
> >> controller, the values of the modified members in this *info would
> >> not be those expected.
> >> So *info and the spi_nor_ids[] array must remain const.
> >>
> >> The *info structure is not used outside spi_nor_scan(); none of
> >> spi_nor_read(),
> >> spi_nor_write() and spi_nor_erase() refers to *info hence every
> >> relevant value can be set only nor or nor->mtd members.
> >>
> >>
> >> Anyway, I think OR'ing or AND'ing values of memory registers
> >> depending on the relevant bit we want to check is not the right solution.
> >> If done in spi-nor.c, there would be a specific case for each memory
> >> register we read, each register bit would have to be handled differently.
> >>
> >> spi-nor.c tries to support as much memory parts as possible, it deals
> >> with many registers and bits: Status/Control registers, Quad Enable bits...
> >>
> >> If we start to OR or AND each of these register values to support the
> >> stripping mode, spi-nor will become really hard to maintain.
> >>
> >> I don't know whether it could be done with the xilinx controller but
> >> I thought about first configuring the two memories independently
> >> calling
> >> spi_nor_scan() twice; one call for each memory.
> >>
> >> Then the xilinx driver could register only one struct mtd_info,
> >> overriding
> >> mtd->_read() [and likely mtd->_write() and mtd->_erase() too] set by
> >> spi_nor_scan() with a xilinx driver custom implementation so this
> >> driver supports its controller stripping mode as it wants.
> >>
> >> Of course, this solution assumes that the SPI controller has one
> >> dedicated chip-select line for each memory and not a single
> >> chip-select line shared by both memories. The memories should be
> >> configured independently: you can't assume multiple instances of the
> >> very same memory part always return the exact same value when reading
> >> one of their register. Logical AND/OR is not a generic solution, IMHO.
> >>
> >> If the xilinx controller has only one shared chip-select line then
> >> let's see whether 2 GPIO lines could be used as independent chip-select
> lines.
> >>
> >>
> > In parallel configuration, Physically we have two flashes but mtd will
> > see as single flash memory (sum of both memories) If we call
> spi_nor_scan(), twice then read/write will override but nor->mtd.size, nor-
> >mtd.erasesize, nor->page_size will remain same, I,e they will also override,
> they won't append.
> > I tried calling spi_nor_scan() twice by some hacks but nor->mtd.size,
> > nor->mtd.erasesize, nor->page_size are not changing Also the same issue
> we are getting for flash address, need to shift the address to work in this
> configuration.
> > Also to tune nor->mtd.size, nor->mtd.erasesize, nor->page_size, we
> > need to touch this spi-nor.c
> >
> > Please kindly suggest, if I am wrong.
> >
>
> What I've been suggesting is:
>
> {
> struct spi_nor *nor1, *nor2;
> struct mtd_info *mtd;
> enum read_mode mode = SPI_NOR_QUAD;
> int err;
>
> [...]
>
> err = spi_nor_scan(nor1, NULL, mode);
> if (err)
> return err; /* or handle error properly. */
>
> err = spi_nor_scan(nor2, NULL, mode);
> if (err)
> return err;
>
> mtd = &nor1->mtd;
> mtd->erasesize <<= 1;
> mtd->size <<= 1;
> mtd->writebufsize <<= 1;
> nor1->page_size <<= 1;
> /* tune all other relevant members of nor1/mtd. */
>
> /* override relevant mtd hooks. */
> mtd->_read = stripping_read;
> mtd->_erase = stripping_erase;
> mtd->_write = stripping_write;
> mtd->_lock = ...;
> mtd->_unlock = ...;
> mtd->_is_lock = ...;
>
> /* register a single mtd_info structure. */
> err = mtd_device_register(mtd, NULL, 0);
> if (err)
> return err;
>
> [...]
> }
>
It's really good for us to have our controller specific mtd hooks instead of changing the layer calls and thanks for this suggestion.
But spi-zynqmp-gqspi.c is spi driver and all above mentioned parameters and function pointers are related to flash layer.
So is it ok to update and change flash related stuff in our spi driver?
> Best regards,
>
> Cyrille
>
Thanks,
Naga Sureshkumar Relli
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply
* [PATCH v2 0/3] ARM: dts: imx6: Support Poslab Savageboard dual & quad
From: Milo Kim @ 2016-12-06 7:08 UTC (permalink / raw)
To: linux-arm-kernel
Poslab Savageboard is i.MX6 SoC base, but BSP code from the vendor is
not mainline u-boot and kernel. Personal reason of using this board is
testing etnaviv user-space driver, so I re-write device tree files based on
mainline kernel for the first step.
This patchset includes common DT file, dual and quad board files.
Supported components are
- Display: HDMI and LVDS panel
- eMMC and SD card
- Ethernet
- Pinmux configuration
- SATA: only for Savageboard quad
- UART1 for debug console
- USB host
Missing features are
- Audio (WM8903)
- USB OTG
- PMIC WM8326: default settings are used so no issue to bring-up the system
- MIPI DSI, CSI
Patches are tested on the Savageboard quad but the dual version should work
because the only difference between dual and quad is SATA support.
More information in http://www.savageboard.org
v2:
Fix DT node for regulator, phy-reset-gpios and iomuxc node.
Milo Kim (3):
ARM: dts: imx6: Add Savageboard common file
ARM: dts: imx6: Support Savageboard dual
ARM: dts: imx6: Support Savageboard quad
arch/arm/boot/dts/imx6dl-savageboard.dts | 50 ++++++
arch/arm/boot/dts/imx6q-savageboard.dts | 54 ++++++
arch/arm/boot/dts/imx6qdl-savageboard.dtsi | 262 +++++++++++++++++++++++++++++
3 files changed, 366 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-savageboard.dts
create mode 100644 arch/arm/boot/dts/imx6q-savageboard.dts
create mode 100644 arch/arm/boot/dts/imx6qdl-savageboard.dtsi
--
2.9.3
^ permalink raw reply
* [PATCH v2 1/3] ARM: dts: imx6: Add Savageboard common file
From: Milo Kim @ 2016-12-06 7:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206070829.24098-1-woogyom.kim@gmail.com>
* Memory
memblock for DDR3 1GB
* Regulator
3.3V for panel and backlight.
* Display
Enable HDMI and LVDS panel. Savageboard supports AVIC TM097TDH02 panel
which is compatible with Hannstar HSD100PXN1, so reuse it.
* Clock
The commit d28be499c45e6 is applied to support LVDS and HDMI output
simultaneously.
* Pinmux
eMMC, ethernet, HDMI, I2C, power button, PWM, SD card and UART.
* Others
Enable ethernet, UART1 debug, USB host, USDHC3 for microSD card and
USDHC4 for built-in eMMC storage.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/imx6qdl-savageboard.dtsi | 262 +++++++++++++++++++++++++++++
1 file changed, 262 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6qdl-savageboard.dtsi
diff --git a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/imx6qdl-savageboard.dtsi
new file mode 100644
index 0000000..a7a7e1d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-savageboard.dtsi
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory at 10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+
+ backlight: panel_bl {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <4>;
+ power-supply = <®_3p3v>;
+ pwms = <&pwm1 0 10000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ power {
+ gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ label = "Power Button";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ panel {
+ compatible = "avic, tm097tdh02", "hannstar,hsd100pxn1";
+ backlight = <&backlight>;
+ power-supply = <®_3p3v>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&fec {
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_tx_cec>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&ldb {
+ status = "okay";
+
+ lvds-channel at 0 {
+ reg = <0>;
+ status = "okay";
+
+ port at 4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+/* SD card */
+&usdhc3 {
+ bus-width = <4>;
+ cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc4 {
+ bus-width = <8>;
+ keep-power-in-suspend;
+ no-1-8-v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_emmc: emmcgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ /* PHY reset */
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+ >;
+ };
+
+ pinctrl_hdmi_tx_cec: hdmitxcecgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_sd: sdgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ /* CD pin */
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+};
--
2.9.3
^ permalink raw reply related
* [PATCH v2 2/3] ARM: dts: imx6: Support Savageboard dual
From: Milo Kim @ 2016-12-06 7:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206070829.24098-1-woogyom.kim@gmail.com>
Common savageboard DT file is used for board support.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/imx6dl-savageboard.dts | 50 ++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-savageboard.dts
diff --git a/arch/arm/boot/dts/imx6dl-savageboard.dts b/arch/arm/boot/dts/imx6dl-savageboard.dts
new file mode 100644
index 0000000..2cac30d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-savageboard.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-savageboard.dtsi"
+
+/ {
+ model = "Poslab SavageBoard Dual";
+ compatible = "poslab,imx6dl-savageboard", "fsl,imx6dl";
+};
--
2.9.3
^ permalink raw reply related
* [PATCH v2 3/3] ARM: dts: imx6: Support Savageboard quad
From: Milo Kim @ 2016-12-06 7:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206070829.24098-1-woogyom.kim@gmail.com>
Use common board file and support SATA interface additionally.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/imx6q-savageboard.dts | 54 +++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-savageboard.dts
diff --git a/arch/arm/boot/dts/imx6q-savageboard.dts b/arch/arm/boot/dts/imx6q-savageboard.dts
new file mode 100644
index 0000000..8d74002
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-savageboard.dts
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-savageboard.dtsi"
+
+/ {
+ model = "Poslab SavageBoard Quad";
+ compatible = "poslab,imx6q-savageboard", "fsl,imx6q";
+};
+
+&sata {
+ status = "okay";
+};
--
2.9.3
^ permalink raw reply related
* [PATCH 1/3] ARM: dts: imx6: Add Savageboard common file
From: Milo Kim @ 2016-12-06 7:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5BzLc7Xr9G0hLP1O4aYx+7J5gy0VHdQ3Kz0GFq=WdQ1gw@mail.gmail.com>
On 12/05/2016 08:36 PM, Fabio Estevam wrote:
> On Sun, Dec 4, 2016 at 11:07 PM, Milo Kim <woogyom.kim@gmail.com> wrote:
>
>> + regulators {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + reg_3p3v: regulator at 0 {
>> + compatible = "regulator-fixed";
>> + reg = <0>;
>> + regulator-name = "3P3V";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>
> Please remove the regulators container and put the regulator node
> directly as follows:
>
> reg_3p3v: regulator-3p3v {
> compatible = "regulator-fixed";
> regulator-name = "3P3V";
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> regulator-always-on;
> }
>
>> + };
>> +};
>> +
>> +&clks {
>> + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
>> + <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
>> + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
>> + <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
>> +};
>> +
>> +&fec {
>> + phy-mode = "rgmii";
>> + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
>
> I think you meant
> phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
>
>> +&iomuxc {
>> + savageboard {
>> + pinctrl_emmc: emmcgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
>> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
>> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
>> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
>> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
>> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
>> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
>> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
>> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>> + >;
>> + };
>
> You can remove the savegeboard level. Please check
> arch/arm/boot/dts/imx6q-tbs2910.dts.
>
> iomux usually go as the last node of the dts file.
Thanks a lot for all your feedback. I just submitted the v2.
Best regards,
Milo
^ permalink raw reply
* [PATCH] ipmi: bt-bmc: Use a regmap for register access
From: Cédric Le Goater @ 2016-12-06 7:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206025715.2002-1-andrew@aj.id.au>
On 12/06/2016 03:57 AM, Andrew Jeffery wrote:
> The registers for the bt-bmc device live under the Aspeed LPC
> controller. Devicetree bindings have recently been introduced for the
> LPC controller where the "host" portion of the LPC register space is
> described as a syscon device. Future devicetrees describing the bt-bmc
> device should nest its node under the appropriate "simple-mfd", "syscon"
> compatible node.
>
> This change allows the bt-bmc driver to function with both syscon and
> non-syscon- based devicetree descriptions by always using a regmap for
> register access, either retrieved from the parent syscon device or
> instantiated if none exists.
>
> The patch has been tested on an OpenPOWER Palmetto machine, successfully
> booting, rebooting and powering down the host.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
It would be nice to have an example of the associated binding.
I did not see it. A part from that :
Reviewed-by: C?dric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> drivers/char/ipmi/Kconfig | 1 +
> drivers/char/ipmi/bt-bmc.c | 82 ++++++++++++++++++++++++++++++++++------------
> 2 files changed, 62 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
> index 7f816655cbbf..b5d48d9af124 100644
> --- a/drivers/char/ipmi/Kconfig
> +++ b/drivers/char/ipmi/Kconfig
> @@ -79,6 +79,7 @@ endif # IPMI_HANDLER
>
> config ASPEED_BT_IPMI_BMC
> depends on ARCH_ASPEED
> + depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
> tristate "BT IPMI bmc driver"
> help
> Provides a driver for the BT (Block Transfer) IPMI interface
> diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
> index fc9e8891eae3..ca1e20f6c6c5 100644
> --- a/drivers/char/ipmi/bt-bmc.c
> +++ b/drivers/char/ipmi/bt-bmc.c
> @@ -12,10 +12,13 @@
> #include <linux/errno.h>
> #include <linux/interrupt.h>
> #include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/miscdevice.h>
> #include <linux/module.h>
> +#include <linux/of.h>
> #include <linux/platform_device.h>
> #include <linux/poll.h>
> +#include <linux/regmap.h>
> #include <linux/sched.h>
> #include <linux/timer.h>
>
> @@ -60,7 +63,8 @@
> struct bt_bmc {
> struct device dev;
> struct miscdevice miscdev;
> - void __iomem *base;
> + struct regmap *map;
> + int offset;
> int irq;
> wait_queue_head_t queue;
> struct timer_list poll_timer;
> @@ -69,14 +73,31 @@ struct bt_bmc {
>
> static atomic_t open_count = ATOMIC_INIT(0);
>
> +static struct regmap_config bt_regmap_cfg = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> static u8 bt_inb(struct bt_bmc *bt_bmc, int reg)
> {
> - return ioread8(bt_bmc->base + reg);
> + uint32_t val = 0;
> + int rc;
> +
> + rc = regmap_read(bt_bmc->map, bt_bmc->offset + reg, &val);
> + WARN(rc != 0, "%s:%d: regmap_read() failed: %d\n",
> + __FILE__, __LINE__, rc);
> +
> + return rc == 0 ? (u8) val : 0;
> }
>
> static void bt_outb(struct bt_bmc *bt_bmc, u8 data, int reg)
> {
> - iowrite8(data, bt_bmc->base + reg);
> + int rc;
> +
> + rc = regmap_write(bt_bmc->map, bt_bmc->offset + reg, data);
> + WARN(rc != 0, "%s:%d: regmap_write() failed: %d\n",
> + __FILE__, __LINE__, rc);
> }
>
> static void clr_rd_ptr(struct bt_bmc *bt_bmc)
> @@ -367,14 +388,18 @@ static irqreturn_t bt_bmc_irq(int irq, void *arg)
> {
> struct bt_bmc *bt_bmc = arg;
> u32 reg;
> + int rc;
> +
> + rc = regmap_read(bt_bmc->map, bt_bmc->offset + BT_CR2, ®);
> + if (rc)
> + return IRQ_NONE;
>
> - reg = ioread32(bt_bmc->base + BT_CR2);
> reg &= BT_CR2_IRQ_H2B | BT_CR2_IRQ_HBUSY;
> if (!reg)
> return IRQ_NONE;
>
> /* ack pending IRQs */
> - iowrite32(reg, bt_bmc->base + BT_CR2);
> + regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR2, reg);
>
> wake_up(&bt_bmc->queue);
> return IRQ_HANDLED;
> @@ -384,7 +409,6 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - u32 reg;
> int rc;
>
> bt_bmc->irq = platform_get_irq(pdev, 0);
> @@ -405,18 +429,17 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> * will be cleared (along with B2H) when we can write the next
> * message to the BT buffer
> */
> - reg = ioread32(bt_bmc->base + BT_CR1);
> - reg |= BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY;
> - iowrite32(reg, bt_bmc->base + BT_CR1);
> + rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset + BT_CR1,
> + (BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY),
> + (BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY));
>
> - return 0;
> + return rc;
> }
>
> static int bt_bmc_probe(struct platform_device *pdev)
> {
> struct bt_bmc *bt_bmc;
> struct device *dev;
> - struct resource *res;
> int rc;
>
> if (!pdev || !pdev->dev.of_node)
> @@ -431,10 +454,27 @@ static int bt_bmc_probe(struct platform_device *pdev)
>
> dev_set_drvdata(&pdev->dev, bt_bmc);
>
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - bt_bmc->base = devm_ioremap_resource(&pdev->dev, res);
> - if (IS_ERR(bt_bmc->base))
> - return PTR_ERR(bt_bmc->base);
> + bt_bmc->map = syscon_node_to_regmap(pdev->dev.parent->of_node);
> + if (IS_ERR(bt_bmc->map)) {
> + struct resource *res;
> + void __iomem *base;
> +
> + /*
> + * Assume it's not the MFD-based devicetree description, in
> + * which case generate a regmap ourselves
> + */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + bt_bmc->map = devm_regmap_init_mmio(dev, base, &bt_regmap_cfg);
> + bt_bmc->offset = 0;
> + } else {
> + rc = of_property_read_u32(dev->of_node, "reg", &bt_bmc->offset);
> + if (rc)
> + return rc;
> + }
>
> mutex_init(&bt_bmc->mutex);
> init_waitqueue_head(&bt_bmc->queue);
> @@ -461,12 +501,12 @@ static int bt_bmc_probe(struct platform_device *pdev)
> add_timer(&bt_bmc->poll_timer);
> }
>
> - iowrite32((BT_IO_BASE << BT_CR0_IO_BASE) |
> - (BT_IRQ << BT_CR0_IRQ) |
> - BT_CR0_EN_CLR_SLV_RDP |
> - BT_CR0_EN_CLR_SLV_WRP |
> - BT_CR0_ENABLE_IBT,
> - bt_bmc->base + BT_CR0);
> + regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR0,
> + (BT_IO_BASE << BT_CR0_IO_BASE) |
> + (BT_IRQ << BT_CR0_IRQ) |
> + BT_CR0_EN_CLR_SLV_RDP |
> + BT_CR0_EN_CLR_SLV_WRP |
> + BT_CR0_ENABLE_IBT);
>
> clr_b_busy(bt_bmc);
>
>
^ permalink raw reply
* [PATCH 1/2] ARM: dts: sun8i: Specify memblock for Nano Pi M1
From: Milo Kim @ 2016-12-06 7:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161205080932.xaqyl2httgxgso67@lukather>
On 12/05/2016 05:09 PM, Maxime Ripard wrote:
> On Mon, Dec 05, 2016 at 11:00:31AM +0900, Milo Kim wrote:
>> The board has DDR3 512MB. This patch helps scanning the memory and
>> adding memblock through the DT.
>>
>> Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
>> ---
>> arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
>> index ec63d10..be3668f 100644
>> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
>> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
>> @@ -45,6 +45,11 @@
>> / {
>> model = "FriendlyArm NanoPi M1";
>> compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3";
>> +
>> + memory at 40000000 {
>> + device_type = "memory";
>> + reg = <0x40000000 0x20000000>;
>> + };
>
> U-boot will fill that up, so there's no need to put it there.
Right, my intention was adding memblock through the DT whether the
bootload does or not. However I'm not sure the situation (missing
memblock in u-boot) could really happen.
Best regards,
Milo
^ permalink raw reply
* [PATCH 11/18] arm64: ilp32: share aarch32 syscall handlers
From: Yury Norov @ 2016-12-06 7:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161205171242.GH14429@e104818-lin.cambridge.arm.com>
On Mon, Dec 05, 2016 at 05:12:43PM +0000, Catalin Marinas wrote:
> On Fri, Oct 21, 2016 at 11:33:10PM +0300, Yury Norov wrote:
> > off_t is passed in register pair just like in aarch32.
> > In this patch corresponding aarch32 handlers are shared to
> > ilp32 code.
> [...]
> > +/*
> > + * Note: off_4k (w5) is always in units of 4K. If we can't do the
> > + * requested offset because it is not page-aligned, we return -EINVAL.
> > + */
> > +ENTRY(compat_sys_mmap2_wrapper)
> > +#if PAGE_SHIFT > 12
> > + tst w5, #~PAGE_MASK >> 12
> > + b.ne 1f
> > + lsr w5, w5, #PAGE_SHIFT - 12
> > +#endif
> > + b sys_mmap_pgoff
> > +1: mov x0, #-EINVAL
> > + ret
> > +ENDPROC(compat_sys_mmap2_wrapper)
>
> For compat sys_mmap2, the pgoff argument is in multiples of 4K. This was
> traditionally used for architectures where off_t is 32-bit to allow
> mapping files to 2^44.
>
> Since off_t is 64-bit with AArch64/ILP32, should we just pass the off_t
> as a 64-bit value in two different registers (w5 and w6)?
Current glibc implementation becomes broken for 64-bit off_t if
if I'll do what you want.
sysdeps/unix/sysv/linux/generic/wordsize-32/mmap.c
28 __ptr_t
29 __mmap (__ptr_t addr, size_t len, int prot, int flags, int fd, off_t offset)
30 {
31 if (offset & (MMAP_PAGE_UNIT - 1))
32 {
33 __set_errno (EINVAL);
34 return MAP_FAILED;
35 }
36 return (__ptr_t) INLINE_SYSCALL (mmap2, 6, addr, len, prot, flags, fd,
37 offset / MMAP_PAGE_UNIT);
38 }
39
40 weak_alias (__mmap, mmap)
So it requires changes both in glibc and in kernel. I can do it. But
I'd like to collect opinions of kernel and glibc developers before
starting it.
Yury
^ permalink raw reply
* [PATCH] media/platform/exynos4-is/fimc-is - Unmap region obtained by of_iomap
From: Arvind Yadav @ 2016-12-06 7:42 UTC (permalink / raw)
To: linux-arm-kernel
Free memory mapping, if fimc_is_probe is not successful.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
---
drivers/media/platform/exynos4-is/fimc-is.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/exynos4-is/fimc-is.c b/drivers/media/platform/exynos4-is/fimc-is.c
index 32ca55f..10d98a5 100644
--- a/drivers/media/platform/exynos4-is/fimc-is.c
+++ b/drivers/media/platform/exynos4-is/fimc-is.c
@@ -818,12 +818,13 @@ static int fimc_is_probe(struct platform_device *pdev)
is->irq = irq_of_parse_and_map(dev->of_node, 0);
if (!is->irq) {
dev_err(dev, "no irq found\n");
- return -EINVAL;
+ ret = -EINVAL;
+ goto err_iounmap;
}
ret = fimc_is_get_clocks(is);
if (ret < 0)
- return ret;
+ goto err_iounmap;
platform_set_drvdata(pdev, is);
@@ -877,6 +878,8 @@ err_irq:
free_irq(is->irq, is);
err_clk:
fimc_is_put_clocks(is);
+err_iounmap:
+ iounmap(is->pmu_regs);
return ret;
}
@@ -932,6 +935,7 @@ static int fimc_is_remove(struct platform_device *pdev)
fimc_is_unregister_subdevs(is);
vb2_dma_contig_clear_max_seg_size(dev);
fimc_is_put_clocks(is);
+ iounmap(is->pmu_regs);
fimc_is_debugfs_remove(is);
release_firmware(is->fw.f_w);
fimc_is_free_cpu_memory(is);
--
1.7.9.5
^ permalink raw reply related
* [PATCH] ACPI/IORT: Make dma masks set-up IORT specific
From: Hanjun Guo @ 2016-12-06 7:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161205122619.25045-1-lorenzo.pieralisi@arm.com>
On 2016/12/5 20:26, Lorenzo Pieralisi wrote:
> The introduction of acpi_dma_configure() allows to configure DMA
> and related IOMMU for any device that is DMA capable. To achieve
> that goal it ensures DMA masks are set-up to sane default values
> before proceeding with IOMMU and DMA ops configuration.
>
> On x86/ia64 systems, through acpi_bind_one(), acpi_dma_configure() is
> called for every device that has an ACPI companion, in that every device
> is considered DMA capable on x86/ia64 systems (ie acpi_get_dma_attr() API),
> which has the side effect of initializing dma masks also for
> pseudo-devices (eg CPUs and memory nodes) and potentially for devices
> whose dma masks were not set-up before the acpi_dma_configure() API was
> introduced, which may have noxious side effects.
>
> Therefore, in preparation for IORT firmware specific DMA masks set-up,
> wrap the default DMA masks set-up in acpi_dma_configure() inside an IORT
> specific wrapper that reverts to a NOP on x86/ia64 systems, restoring the
> default expected behaviour on x86/ia64 systems and keeping DMA default
> masks set-up on IORT based (ie ARM) arch configurations.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Hanjun Guo <hanjun.guo@linaro.org>
Add this patch on top of your v9 acpi smmu patchset,
tested on Hisilicon D03 (ARM64), devices with SMMU
enabled work fine,
Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org>
Thanks
Hanjun
^ permalink raw reply
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