* [PATCH 2/2] arm64:dt:ls1012a: Add TMU device tree support for LS1012A
From: Jia Hongtao @ 2016-12-08 3:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481167706-44234-1-git-send-email-hongtao.jia@nxp.com>
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
---
Depend on patch "[v3] arm64: Add DTS support for FSL's LS1012A SoC".
https://patchwork.kernel.org/patch/9462399/
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 76 ++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 92e64f3..bc694b4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -43,6 +43,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1012a";
@@ -127,6 +128,81 @@
#clock-cells = <2>;
clocks = <&sysclk>;
};
+ tmu: tmu at 1f00000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f00000 0x0 0x10000>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x00000000 0x00000026
+ 0x00000001 0x0000002d
+ 0x00000002 0x00000032
+ 0x00000003 0x00000039
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000046
+ 0x00000006 0x0000004d
+ 0x00000007 0x00000054
+ 0x00000008 0x0000005a
+ 0x00000009 0x00000061
+ 0x0000000a 0x0000006a
+ 0x0000000b 0x00000071
+
+ 0x00010000 0x00000025
+ 0x00010001 0x0000002c
+ 0x00010002 0x00000035
+ 0x00010003 0x0000003d
+ 0x00010004 0x00000045
+ 0x00010005 0x0000004e
+ 0x00010006 0x00000057
+ 0x00010007 0x00000061
+ 0x00010008 0x0000006b
+ 0x00010009 0x00000076
+
+ 0x00020000 0x00000029
+ 0x00020001 0x00000033
+ 0x00020002 0x0000003d
+ 0x00020003 0x00000049
+ 0x00020004 0x00000056
+ 0x00020005 0x00000061
+ 0x00020006 0x0000006d
+
+ 0x00030000 0x00000021
+ 0x00030001 0x0000002a
+ 0x00030002 0x0000003c
+ 0x00030003 0x0000004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
i2c0: i2c at 2180000 {
compatible = "fsl,vf610-i2c";
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 1/2] arm64:dt:ls1046a: Add TMU device tree support for LS1046A
From: Jia Hongtao @ 2016-12-08 3:28 UTC (permalink / raw)
To: linux-arm-kernel
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 79 ++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..40604e9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,8 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +69,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu at 1 {
@@ -279,6 +282,82 @@
clocks = <&sysclk>;
};
+ tmu: tmu at 1f00000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f00000 0x0 0x10000>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x00000000 0x00000026
+ 0x00000001 0x0000002d
+ 0x00000002 0x00000032
+ 0x00000003 0x00000039
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000046
+ 0x00000006 0x0000004d
+ 0x00000007 0x00000054
+ 0x00000008 0x0000005a
+ 0x00000009 0x00000061
+ 0x0000000a 0x0000006a
+ 0x0000000b 0x00000071
+
+ 0x00010000 0x00000025
+ 0x00010001 0x0000002c
+ 0x00010002 0x00000035
+ 0x00010003 0x0000003d
+ 0x00010004 0x00000045
+ 0x00010005 0x0000004e
+ 0x00010006 0x00000057
+ 0x00010007 0x00000061
+ 0x00010008 0x0000006b
+ 0x00010009 0x00000076
+
+ 0x00020000 0x00000029
+ 0x00020001 0x00000033
+ 0x00020002 0x0000003d
+ 0x00020003 0x00000049
+ 0x00020004 0x00000056
+ 0x00020005 0x00000061
+ 0x00020006 0x0000006d
+
+ 0x00030000 0x00000021
+ 0x00030001 0x0000002a
+ 0x00030002 0x0000003c
+ 0x00030003 0x0000004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
dspi: dspi at 2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
--
2.1.0.27.g96db324
^ permalink raw reply related
* [Linaro-acpi] [PATCH v17 08/15] clocksource/drivers/arm_arch_timer: move arch_timer_needs_of_probing into DT init call
From: Fu Wei @ 2016-12-08 3:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOZdJXU7Lg66RKvA=sYtUXUdwLLbh9FtcW0_U-fmjaztnqS3Ng@mail.gmail.com>
Hi Timur,
On 8 December 2016 at 01:25, Timur Tabi <timur@codeaurora.org> wrote:
> On Fri, Nov 25, 2016 at 9:06 AM, Fu Wei <fu.wei@linaro.org> wrote:
>>
>> a "+ int ret;" should be move from [12/15] to here, I have fix the
>> problem in my repo, it would happen in next patchset
>>
>> https://git.linaro.org/people/fu.wei/linux.git/log/?h=topic-gtdt-wakeup-timer_upstream_v18_devel
>
> Fu, please post v18 to the mailing list so that it can be picked up
> for 4.10 (if it's not too late already).
Great thanks for your suggestion! :-)
yes, you are right, I would love to post v18 ASAP.
But I am still waiting for more feedback from the maintainers.
For Now, the only feedback is this fix from "kbuild test robot" :-(
>
> --
> Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project.
--
Best regards,
Fu Wei
Software Engineer
Red Hat
^ permalink raw reply
* [PATCH] drm: zte: add overlay plane support
From: Shawn Guo @ 2016-12-08 3:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Shawn Guo <shawn.guo@linaro.org>
It enables VOU VL (Video Layer) to support overlay plane with scaling
function. VL0 has some quirks on scaling support. We chose to skip it
and only adds VL1 and VL2 into DRM core for now.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/gpu/drm/zte/zx_plane.c | 290 ++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/zte/zx_plane_regs.h | 51 +++++++
drivers/gpu/drm/zte/zx_vou.c | 149 +++++++++++++++++-
drivers/gpu/drm/zte/zx_vou.h | 3 +
drivers/gpu/drm/zte/zx_vou_regs.h | 18 +++
5 files changed, 494 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/zte/zx_plane.c b/drivers/gpu/drm/zte/zx_plane.c
index 546eb92a94e8..0dd48c66a02e 100644
--- a/drivers/gpu/drm/zte/zx_plane.c
+++ b/drivers/gpu/drm/zte/zx_plane.c
@@ -40,6 +40,266 @@ struct zx_plane {
DRM_FORMAT_ARGB4444,
};
+static const uint32_t vl_formats[] = {
+ DRM_FORMAT_NV12, /* Semi-planar YUV420 */
+ DRM_FORMAT_YUV420, /* Planar YUV420 */
+ DRM_FORMAT_YUYV, /* Packed YUV422 */
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_YUV444, /* YUV444 8bit */
+ /*
+ * TODO: add formats below that HW supports:
+ * - YUV420 P010
+ * - YUV420 Hantro
+ * - YUV444 10bit
+ */
+};
+
+#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
+
+static int zx_vl_plane_atomic_check(struct drm_plane *plane,
+ struct drm_plane_state *plane_state)
+{
+ struct drm_framebuffer *fb = plane_state->fb;
+ struct drm_crtc *crtc = plane_state->crtc;
+ struct drm_crtc_state *crtc_state;
+ struct drm_rect clip;
+ int min_scale = FRAC_16_16(1, 8);
+ int max_scale = FRAC_16_16(8, 1);
+
+ if (!crtc || !fb)
+ return 0;
+
+ crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state,
+ crtc);
+ if (WARN_ON(!crtc_state))
+ return -EINVAL;
+
+ /* nothing to check when disabling or disabled */
+ if (!crtc_state->enable)
+ return 0;
+
+ /* plane must be enabled */
+ if (!plane_state->crtc)
+ return -EINVAL;
+
+ clip.x1 = 0;
+ clip.y1 = 0;
+ clip.x2 = crtc_state->adjusted_mode.hdisplay;
+ clip.y2 = crtc_state->adjusted_mode.vdisplay;
+
+ return drm_plane_helper_check_state(plane_state, &clip,
+ min_scale, max_scale,
+ true, true);
+}
+
+static u32 zx_vl_get_fmt(uint32_t format)
+{
+ u32 val = 0;
+
+ switch (format) {
+ case DRM_FORMAT_NV12:
+ val = VL_FMT_YUV420;
+ break;
+ case DRM_FORMAT_YUV420:
+ val = VL_YUV420_PLANAR | VL_FMT_YUV420;
+ break;
+ case DRM_FORMAT_YUYV:
+ val = VL_YUV422_YUYV | VL_FMT_YUV422;
+ break;
+ case DRM_FORMAT_YVYU:
+ val = VL_YUV422_YVYU | VL_FMT_YUV422;
+ break;
+ case DRM_FORMAT_UYVY:
+ val = VL_YUV422_UYVY | VL_FMT_YUV422;
+ break;
+ case DRM_FORMAT_VYUY:
+ val = VL_YUV422_VYUY | VL_FMT_YUV422;
+ break;
+ case DRM_FORMAT_YUV444:
+ val = VL_FMT_YUV444_8BIT;
+ break;
+ default:
+ WARN_ONCE(1, "invalid pixel format %d\n", format);
+ }
+
+ return val;
+}
+
+static inline void zx_vl_set_update(struct zx_plane *zplane)
+{
+ void __iomem *layer = zplane->layer;
+
+ zx_writel_mask(layer + VL_CTRL0, VL_UPDATE, VL_UPDATE);
+}
+
+static inline void zx_vl_rsz_set_update(struct zx_plane *zplane)
+{
+ zx_writel(zplane->rsz + RSZ_VL_ENABLE_CFG, 1);
+}
+
+static u32 zx_vl_rsz_get_fmt(uint32_t format)
+{
+ u32 val = 0;
+
+ switch (format) {
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_YUV420:
+ val = RSZ_VL_FMT_YCBCR420;
+ break;
+ case DRM_FORMAT_YUYV:
+ case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_VYUY:
+ val = RSZ_VL_FMT_YCBCR422;
+ break;
+ case DRM_FORMAT_YUV444:
+ val = RSZ_VL_FMT_YCBCR444;
+ break;
+ default:
+ WARN_ONCE(1, "invalid pixel format %d\n", format);
+ }
+
+ return val;
+}
+
+static inline u32 rsz_step_value(u32 src, u32 dst)
+{
+ u32 val = 0;
+
+ if (src == dst)
+ val = 0;
+ else if (src < dst)
+ val = RSZ_PARA_STEP((src << 16) / dst);
+ else if (src > dst)
+ val = RSZ_DATA_STEP(src / dst) |
+ RSZ_PARA_STEP(((src << 16) / dst) & 0xffff);
+
+ return val;
+}
+
+static void zx_vl_rsz_setup(struct zx_plane *zplane, uint32_t format,
+ u32 src_w, u32 src_h, u32 dst_w, u32 dst_h)
+{
+ void __iomem *rsz = zplane->rsz;
+ u32 src_chroma_w = src_w;
+ u32 src_chroma_h = src_h;
+ u32 fmt;
+
+ /* Set up source and destination resolution */
+ zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1));
+ zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1));
+
+ /* Configure data format for VL RSZ */
+ fmt = zx_vl_rsz_get_fmt(format);
+ zx_writel_mask(rsz + RSZ_VL_CTRL_CFG, RSZ_VL_FMT_MASK, fmt);
+
+ /* Calculate Chroma heigth and width */
+ if (fmt == RSZ_VL_FMT_YCBCR420) {
+ src_chroma_w = src_w >> 1;
+ src_chroma_h = src_h >> 1;
+ } else if (fmt == RSZ_VL_FMT_YCBCR422) {
+ src_chroma_w = src_w >> 1;
+ }
+
+ /* Set up Luma and Chroma step registers */
+ zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w));
+ zx_writel(rsz + RSZ_VL_LUMA_VER, rsz_step_value(src_h, dst_h));
+ zx_writel(rsz + RSZ_VL_CHROMA_HOR, rsz_step_value(src_chroma_w, dst_w));
+ zx_writel(rsz + RSZ_VL_CHROMA_VER, rsz_step_value(src_chroma_h, dst_h));
+
+ zx_vl_rsz_set_update(zplane);
+}
+
+static void zx_vl_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ struct zx_plane *zplane = to_zx_plane(plane);
+ struct drm_framebuffer *fb = plane->state->fb;
+ struct drm_gem_cma_object *cma_obj;
+ void __iomem *layer = zplane->layer;
+ void __iomem *hbsc = zplane->hbsc;
+ void __iomem *paddr_reg;
+ dma_addr_t paddr;
+ u32 src_x, src_y, src_w, src_h;
+ u32 dst_x, dst_y, dst_w, dst_h;
+ uint32_t format;
+ u32 fmt;
+ int num_planes;
+ int i;
+
+ if (!fb)
+ return;
+
+ format = fb->pixel_format;
+
+ src_x = plane->state->src_x >> 16;
+ src_y = plane->state->src_y >> 16;
+ src_w = plane->state->src_w >> 16;
+ src_h = plane->state->src_h >> 16;
+
+ dst_x = plane->state->crtc_x;
+ dst_y = plane->state->crtc_y;
+ dst_w = plane->state->crtc_w;
+ dst_h = plane->state->crtc_h;
+
+ /* Set up data address registers for Y, Cb and Cr planes */
+ num_planes = drm_format_num_planes(format);
+ paddr_reg = layer + VL_Y;
+ for (i = 0; i < num_planes; i++) {
+ cma_obj = drm_fb_cma_get_gem_obj(fb, i);
+ paddr = cma_obj->paddr + fb->offsets[i];
+ paddr += src_y * fb->pitches[i];
+ paddr += src_x * drm_format_plane_cpp(format, i);
+ zx_writel(paddr_reg, paddr);
+ paddr_reg += 4;
+ }
+
+ /* Set up source height/width register */
+ zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h));
+
+ /* Set up start position register */
+ zx_writel(layer + VL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y));
+
+ /* Set up end position register */
+ zx_writel(layer + VL_POS_END,
+ GL_POS_X(dst_x + dst_w) | GL_POS_Y(dst_y + dst_h));
+
+ /* Strides of Cb and Cr planes should be identical */
+ zx_writel(layer + VL_STRIDE, LUMA_STRIDE(fb->pitches[0]) |
+ CHROMA_STRIDE(fb->pitches[1]));
+
+ /* Set up video layer data format */
+ fmt = zx_vl_get_fmt(format);
+ zx_writel(layer + VL_CTRL1, fmt);
+
+ /* Always use scaler since it exists (set for not bypass) */
+ zx_writel_mask(layer + VL_CTRL2, VL_SCALER_BYPASS_MODE,
+ VL_SCALER_BYPASS_MODE);
+
+ zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h);
+
+ /* Enable HBSC block */
+ zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
+
+ zx_overlay_enable(plane);
+
+ zx_vl_set_update(zplane);
+}
+
+static void zx_vl_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ zx_overlay_disable(plane);
+}
+
+static const struct drm_plane_helper_funcs zx_vl_plane_helper_funcs = {
+ .atomic_check = zx_vl_plane_atomic_check,
+ .atomic_update = zx_vl_plane_atomic_update,
+ .atomic_disable = zx_vl_plane_atomic_disable,
+};
+
static int zx_gl_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *plane_state)
{
@@ -107,14 +367,6 @@ static inline void zx_gl_rsz_set_update(struct zx_plane *zplane)
zx_writel(zplane->rsz + RSZ_ENABLE_CFG, 1);
}
-void zx_plane_set_update(struct drm_plane *plane)
-{
- struct zx_plane *zplane = to_zx_plane(plane);
-
- zx_gl_rsz_set_update(zplane);
- zx_gl_set_update(zplane);
-}
-
static void zx_gl_rsz_setup(struct zx_plane *zplane, u32 src_w, u32 src_h,
u32 dst_w, u32 dst_h)
{
@@ -230,6 +482,24 @@ static void zx_plane_destroy(struct drm_plane *plane)
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
};
+void zx_plane_set_update(struct drm_plane *plane)
+{
+ struct zx_plane *zplane = to_zx_plane(plane);
+
+ switch (plane->type) {
+ case DRM_PLANE_TYPE_PRIMARY:
+ zx_gl_rsz_set_update(zplane);
+ zx_gl_set_update(zplane);
+ break;
+ case DRM_PLANE_TYPE_OVERLAY:
+ zx_vl_rsz_set_update(zplane);
+ zx_vl_set_update(zplane);
+ break;
+ default:
+ WARN_ONCE(1, "unsupported plane type %d\n", plane->type);
+ }
+}
+
static void zx_plane_hbsc_init(struct zx_plane *zplane)
{
void __iomem *hbsc = zplane->hbsc;
@@ -279,7 +549,9 @@ struct drm_plane *zx_plane_init(struct drm_device *drm, struct device *dev,
format_count = ARRAY_SIZE(gl_formats);
break;
case DRM_PLANE_TYPE_OVERLAY:
- /* TODO: add video layer (vl) support */
+ helper = &zx_vl_plane_helper_funcs;
+ formats = vl_formats;
+ format_count = ARRAY_SIZE(vl_formats);
break;
default:
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/zte/zx_plane_regs.h b/drivers/gpu/drm/zte/zx_plane_regs.h
index 3dde6716a558..65f271aeabed 100644
--- a/drivers/gpu/drm/zte/zx_plane_regs.h
+++ b/drivers/gpu/drm/zte/zx_plane_regs.h
@@ -46,6 +46,37 @@
#define GL_POS_X(x) (((x) << GL_POS_X_SHIFT) & GL_POS_X_MASK)
#define GL_POS_Y(x) (((x) << GL_POS_Y_SHIFT) & GL_POS_Y_MASK)
+/* VL registers */
+#define VL_CTRL0 0x00
+#define VL_UPDATE BIT(3)
+#define VL_CTRL1 0x04
+#define VL_YUV420_PLANAR BIT(5)
+#define VL_YUV422_SHIFT 3
+#define VL_YUV422_YUYV (0 << VL_YUV422_SHIFT)
+#define VL_YUV422_YVYU (1 << VL_YUV422_SHIFT)
+#define VL_YUV422_UYVY (2 << VL_YUV422_SHIFT)
+#define VL_YUV422_VYUY (3 << VL_YUV422_SHIFT)
+#define VL_FMT_YUV420 0
+#define VL_FMT_YUV422 1
+#define VL_FMT_YUV420_P010 2
+#define VL_FMT_YUV420_HANTRO 3
+#define VL_FMT_YUV444_8BIT 4
+#define VL_FMT_YUV444_10BIT 5
+#define VL_CTRL2 0x08
+#define VL_SCALER_BYPASS_MODE BIT(0)
+#define VL_STRIDE 0x0c
+#define LUMA_STRIDE_SHIFT 16
+#define LUMA_STRIDE_MASK (0xffff << LUMA_STRIDE_SHIFT)
+#define CHROMA_STRIDE_SHIFT 0
+#define CHROMA_STRIDE_MASK (0xffff << CHROMA_STRIDE_SHIFT)
+#define VL_SRC_SIZE 0x10
+#define VL_Y 0x14
+#define VL_POS_START 0x30
+#define VL_POS_END 0x34
+
+#define LUMA_STRIDE(x) (((x) << LUMA_STRIDE_SHIFT) & LUMA_STRIDE_MASK)
+#define CHROMA_STRIDE(x) (((x) << CHROMA_STRIDE_SHIFT) & CHROMA_STRIDE_MASK)
+
/* CSC registers */
#define CSC_CTRL0 0x30
#define CSC_COV_MODE_SHIFT 16
@@ -69,6 +100,18 @@
#define RSZ_DEST_CFG 0x04
#define RSZ_ENABLE_CFG 0x14
+#define RSZ_VL_LUMA_HOR 0x08
+#define RSZ_VL_LUMA_VER 0x0c
+#define RSZ_VL_CHROMA_HOR 0x10
+#define RSZ_VL_CHROMA_VER 0x14
+#define RSZ_VL_CTRL_CFG 0x18
+#define RSZ_VL_FMT_SHIFT 3
+#define RSZ_VL_FMT_MASK (0x3 << RSZ_VL_FMT_SHIFT)
+#define RSZ_VL_FMT_YCBCR420 (0x0 << RSZ_VL_FMT_SHIFT)
+#define RSZ_VL_FMT_YCBCR422 (0x1 << RSZ_VL_FMT_SHIFT)
+#define RSZ_VL_FMT_YCBCR444 (0x2 << RSZ_VL_FMT_SHIFT)
+#define RSZ_VL_ENABLE_CFG 0x1c
+
#define RSZ_VER_SHIFT 16
#define RSZ_VER_MASK (0xffff << RSZ_VER_SHIFT)
#define RSZ_HOR_SHIFT 0
@@ -77,6 +120,14 @@
#define RSZ_VER(x) (((x) << RSZ_VER_SHIFT) & RSZ_VER_MASK)
#define RSZ_HOR(x) (((x) << RSZ_HOR_SHIFT) & RSZ_HOR_MASK)
+#define RSZ_DATA_STEP_SHIFT 16
+#define RSZ_DATA_STEP_MASK (0xffff << RSZ_DATA_STEP_SHIFT)
+#define RSZ_PARA_STEP_SHIFT 0
+#define RSZ_PARA_STEP_MASK (0xffff << RSZ_PARA_STEP_SHIFT)
+
+#define RSZ_DATA_STEP(x) (((x) << RSZ_DATA_STEP_SHIFT) & RSZ_DATA_STEP_MASK)
+#define RSZ_PARA_STEP(x) (((x) << RSZ_PARA_STEP_SHIFT) & RSZ_PARA_STEP_MASK)
+
/* HBSC registers */
#define HBSC_SATURATION 0x00
#define HBSC_HUE 0x04
diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c
index 73fe15c17c32..8ca9c4bdeeaf 100644
--- a/drivers/gpu/drm/zte/zx_vou.c
+++ b/drivers/gpu/drm/zte/zx_vou.c
@@ -93,10 +93,38 @@ struct zx_crtc {
const struct zx_crtc_bits *bits;
enum vou_chn_type chn_type;
struct clk *pixclk;
+ u32 overlay_bitmap;
};
#define to_zx_crtc(x) container_of(x, struct zx_crtc, crtc)
+struct zx_vl_bits {
+ u32 enable;
+ u32 chnsel;
+ u32 clksel;
+};
+
+static const struct zx_vl_bits zx_vl_bits[VL_NUM] = {
+ {
+ .enable = OSD_CTRL0_VL0_EN,
+ .chnsel = OSD_CTRL0_VL0_SEL,
+ .clksel = VOU_CLK_VL0_SEL,
+ }, {
+ .enable = OSD_CTRL0_VL1_EN,
+ .chnsel = OSD_CTRL0_VL1_SEL,
+ .clksel = VOU_CLK_VL1_SEL,
+ }, {
+ .enable = OSD_CTRL0_VL2_EN,
+ .chnsel = OSD_CTRL0_VL2_SEL,
+ .clksel = VOU_CLK_VL2_SEL,
+ },
+};
+
+struct zx_overlay {
+ struct drm_plane *plane;
+ const struct zx_vl_bits *bits;
+};
+
struct zx_vou_hw {
struct device *dev;
void __iomem *osd;
@@ -110,6 +138,7 @@ struct zx_vou_hw {
struct clk *aux_clk;
struct zx_crtc *main_crtc;
struct zx_crtc *aux_crtc;
+ struct zx_overlay overlays[VL_NUM];
};
static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
@@ -404,6 +433,112 @@ void zx_vou_disable_vblank(struct drm_device *drm, unsigned int pipe)
zcrtc->bits->int_frame_mask, 0);
}
+static int zx_overlay_find_vl_idx(struct drm_plane *plane,
+ struct zx_vou_hw *vou)
+{
+ int i;
+
+ for (i = 0; i < VL_NUM; i++) {
+ if (vou->overlays[i].plane == plane)
+ break;
+ }
+
+ if (i == VL_NUM) {
+ DRM_DEV_ERROR(vou->dev, "failed to find VL\n");
+ return -EINVAL;
+ }
+
+ return i;
+}
+
+void zx_overlay_enable(struct drm_plane *plane)
+{
+ struct zx_crtc *zcrtc = to_zx_crtc(plane->state->crtc);
+ struct zx_vou_hw *vou = zcrtc->vou;
+ const struct zx_vl_bits *bits;
+ int idx;
+
+ idx = zx_overlay_find_vl_idx(plane, vou);
+ if (idx < 0)
+ return;
+
+ bits = vou->overlays[idx].bits;
+ zcrtc->overlay_bitmap |= 1 << idx;
+
+ if (zcrtc->chn_type == VOU_CHN_MAIN) {
+ zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, 0);
+ zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0);
+ } else {
+ zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel,
+ bits->chnsel);
+ zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel,
+ bits->clksel);
+ }
+
+ zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, bits->enable);
+}
+
+void zx_overlay_disable(struct drm_plane *plane)
+{
+ struct zx_crtc *zcrtc = to_zx_crtc(plane->crtc);
+ struct zx_vou_hw *vou = zcrtc->vou;
+ const struct zx_vl_bits *bits;
+ int idx;
+
+ idx = zx_overlay_find_vl_idx(plane, vou);
+ if (idx < 0)
+ return;
+
+ bits = vou->overlays[idx].bits;
+ zcrtc->overlay_bitmap &= ~(1 << idx);
+
+ zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, 0);
+}
+
+static void zx_overlay_init(struct drm_device *drm, struct zx_vou_hw *vou)
+{
+ struct device *dev = vou->dev;
+ struct drm_plane *plane;
+ struct zx_layer_data data;
+ int i;
+
+ /*
+ * VL0 has some quirks on scaling support which need special handling.
+ * Let's leave it out for now.
+ */
+ for (i = 1; i < VL_NUM; i++) {
+ data.layer = vou->osd + OSD_VL_OFFSET(i);
+ data.hbsc = vou->osd + HBSC_VL_OFFSET(i);
+ data.rsz = vou->otfppu + RSZ_VL_OFFSET(i);
+
+ plane = zx_plane_init(drm, dev, &data, DRM_PLANE_TYPE_OVERLAY);
+ if (IS_ERR(plane)) {
+ DRM_DEV_ERROR(dev, "failed to init overlay %d\n", i);
+ continue;
+ }
+
+ vou->overlays[i].plane = plane;
+ vou->overlays[i].bits = &zx_vl_bits[i];
+ }
+}
+
+static inline void zx_osd_int_update(struct zx_crtc *zcrtc)
+{
+ u32 bitmap = zcrtc->overlay_bitmap;
+ int i;
+
+ vou_chn_set_update(zcrtc);
+ zx_plane_set_update(zcrtc->primary);
+
+ if (bitmap) {
+ for (i = 0; i < VL_NUM; i++) {
+ if ((bitmap & (1 << i)) == 0)
+ continue;
+ zx_plane_set_update(zcrtc->vou->overlays[i].plane);
+ }
+ }
+}
+
static irqreturn_t vou_irq_handler(int irq, void *dev_id)
{
struct zx_vou_hw *vou = dev_id;
@@ -423,15 +558,11 @@ static irqreturn_t vou_irq_handler(int irq, void *dev_id)
state = zx_readl(vou->osd + OSD_INT_STA);
zx_writel(vou->osd + OSD_INT_CLRSTA, state);
- if (state & OSD_INT_MAIN_UPT) {
- vou_chn_set_update(vou->main_crtc);
- zx_plane_set_update(vou->main_crtc->primary);
- }
+ if (state & OSD_INT_MAIN_UPT)
+ zx_osd_int_update(vou->main_crtc);
- if (state & OSD_INT_AUX_UPT) {
- vou_chn_set_update(vou->aux_crtc);
- zx_plane_set_update(vou->aux_crtc->primary);
- }
+ if (state & OSD_INT_AUX_UPT)
+ zx_osd_int_update(vou->aux_crtc);
if (state & OSD_INT_ERROR)
DRM_DEV_ERROR(vou->dev, "OSD ERROR: 0x%08x!\n", state);
@@ -611,6 +742,8 @@ static int zx_crtc_bind(struct device *dev, struct device *master, void *data)
goto disable_ppu_clk;
}
+ zx_overlay_init(drm, vou);
+
return 0;
disable_ppu_clk:
diff --git a/drivers/gpu/drm/zte/zx_vou.h b/drivers/gpu/drm/zte/zx_vou.h
index 349e06cd86f4..1559c1f79db7 100644
--- a/drivers/gpu/drm/zte/zx_vou.h
+++ b/drivers/gpu/drm/zte/zx_vou.h
@@ -43,4 +43,7 @@ struct vou_inf {
int zx_vou_enable_vblank(struct drm_device *drm, unsigned int pipe);
void zx_vou_disable_vblank(struct drm_device *drm, unsigned int pipe);
+void zx_overlay_enable(struct drm_plane *plane);
+void zx_overlay_disable(struct drm_plane *plane);
+
#endif /* __ZX_VOU_H__ */
diff --git a/drivers/gpu/drm/zte/zx_vou_regs.h b/drivers/gpu/drm/zte/zx_vou_regs.h
index f44e7a4ae441..193c1ce01fe7 100644
--- a/drivers/gpu/drm/zte/zx_vou_regs.h
+++ b/drivers/gpu/drm/zte/zx_vou_regs.h
@@ -22,6 +22,15 @@
#define AUX_HBSC_OFFSET 0x860
#define AUX_RSZ_OFFSET 0x800
+#define OSD_VL0_OFFSET 0x040
+#define OSD_VL_OFFSET(i) (OSD_VL0_OFFSET + 0x050 * (i))
+
+#define HBSC_VL0_OFFSET 0x760
+#define HBSC_VL_OFFSET(i) (HBSC_VL0_OFFSET + 0x040 * (i))
+
+#define RSZ_VL1_U0 0xa00
+#define RSZ_VL_OFFSET(i) (RSZ_VL1_U0 + 0x200 * (i))
+
/* OSD (GPC_GLOBAL) registers */
#define OSD_INT_STA 0x04
#define OSD_INT_CLRSTA 0x08
@@ -42,6 +51,12 @@
)
#define OSD_INT_ENABLE (OSD_INT_ERROR | OSD_INT_AUX_UPT | OSD_INT_MAIN_UPT)
#define OSD_CTRL0 0x10
+#define OSD_CTRL0_VL0_EN BIT(13)
+#define OSD_CTRL0_VL0_SEL BIT(12)
+#define OSD_CTRL0_VL1_EN BIT(11)
+#define OSD_CTRL0_VL1_SEL BIT(10)
+#define OSD_CTRL0_VL2_EN BIT(9)
+#define OSD_CTRL0_VL2_SEL BIT(8)
#define OSD_CTRL0_GL0_EN BIT(7)
#define OSD_CTRL0_GL0_SEL BIT(6)
#define OSD_CTRL0_GL1_EN BIT(5)
@@ -146,6 +161,9 @@
#define VOU_INF_DATA_SEL 0x08
#define VOU_SOFT_RST 0x14
#define VOU_CLK_SEL 0x18
+#define VOU_CLK_VL2_SEL BIT(8)
+#define VOU_CLK_VL1_SEL BIT(7)
+#define VOU_CLK_VL0_SEL BIT(6)
#define VOU_CLK_GL1_SEL BIT(5)
#define VOU_CLK_GL0_SEL BIT(4)
#define VOU_CLK_REQEN 0x20
--
1.9.1
^ permalink raw reply related
* [RESEND-PATCH] ARM: EXYNOS: remove smp hook from machine descriptor
From: Pankaj Dubey @ 2016-12-08 3:02 UTC (permalink / raw)
To: linux-arm-kernel
Use CPU_METHOD_OF_DECLARE() for smp_ops instead of using it
via machine descriptor.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
Resending as I missed to include samsung mailing list.
arch/arm/boot/dts/exynos3250.dtsi | 1 +
arch/arm/boot/dts/exynos4210.dtsi | 1 +
arch/arm/boot/dts/exynos4212.dtsi | 1 +
arch/arm/boot/dts/exynos4412.dtsi | 1 +
arch/arm/boot/dts/exynos5250.dtsi | 1 +
arch/arm/boot/dts/exynos5260.dtsi | 1 +
arch/arm/boot/dts/exynos5410.dtsi | 1 +
arch/arm/boot/dts/exynos5420-cpus.dtsi | 1 +
arch/arm/boot/dts/exynos5422-cpus.dtsi | 1 +
arch/arm/boot/dts/exynos5440.dtsi | 1 +
arch/arm/mach-exynos/common.h | 2 --
arch/arm/mach-exynos/exynos.c | 1 -
arch/arm/mach-exynos/platsmp.c | 2 ++
13 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index ba17ee1..f28f669 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -53,6 +53,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu at 0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 7f3a18c..6dfd98d 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -35,6 +35,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu at 900 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 5389011..3e8982e 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,6 +25,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu at A00 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 40beede..faf2fb8 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,6 +25,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu at A00 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b6d7444..580897c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -52,6 +52,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu at 0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 5818718..1af6e76 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -32,6 +32,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu at 0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 2b6adaf..b092cdc 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -33,6 +33,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu at 0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 5c052d7..a587704 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -24,6 +24,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu at 0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index bf3c6f1..7fcdfd0 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -23,6 +23,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu at 100 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 2a2e570..0a958e8 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -50,6 +50,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu at 0 {
device_type = "cpu";
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index fb12d11..051e1ab 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -143,8 +143,6 @@ static inline void exynos_pm_init(void) {}
extern void exynos_cpu_resume(void);
extern void exynos_cpu_resume_ns(void);
-extern const struct smp_operations exynos_smp_ops;
-
extern void exynos_cpu_power_down(int cpu);
extern void exynos_cpu_power_up(int cpu);
extern int exynos_cpu_power_state(int cpu);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index fa08ef9..f0a766e 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -211,7 +211,6 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.l2c_aux_val = 0x3c400001,
.l2c_aux_mask = 0xc20fffff,
- .smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_early = exynos_firmware_init,
.init_irq = exynos_init_irq,
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 94405c7..43eec10 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -474,3 +474,5 @@ const struct smp_operations exynos_smp_ops __initconst = {
.cpu_die = exynos_cpu_die,
#endif
};
+
+CPU_METHOD_OF_DECLARE(exynos_smp, "samsung,exynos-smp", &exynos_smp_ops);
--
2.7.4
^ permalink raw reply related
* [PATCH] MAINTAINERS: Add Patchwork URL to Samsung Exynos entry
From: Kukjin Kim @ 2016-12-08 2:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481131115-11143-1-git-send-email-krzk@kernel.org>
2016. 12. 8. 02:18 Krzysztof Kozlowski <krzk@kernel.org> wrote:
> I use Patchwork for handling incoming patches. Put its address here so
> submitters could know what is in the queue.
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 191887bdc49b..ec5137c39572 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1689,6 +1689,7 @@ M: Krzysztof Kozlowski <krzk@kernel.org>
> R: Javier Martinez Canillas <javier@osg.samsung.com>
> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> L: linux-samsung-soc at vger.kernel.org (moderated for non-subscribers)
> +Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
to use http would be better instead of https?
then,
Acked-by: Kukjin Kim <kgene@kernel.org>
> S: Maintained
> F: arch/arm/boot/dts/s3c*
> F: arch/arm/boot/dts/s5p*
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v3 1/3] soc: zte: pm_domains: Prepare for supporting ARMv8 2967 family
From: Jun Nie @ 2016-12-08 2:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481091204-6559-1-git-send-email-baoyou.xie@linaro.org>
2016-12-07 14:13 GMT+08:00 Baoyou Xie <baoyou.xie@linaro.org>:
> The ARMv8 2967 family (296718, 296716 etc) uses different value
> for controlling the power domain on/off registers, Choose the
> value depending on the compatible.
>
> Multiple domains are prepared for the family, this patch prepares
> the common functions.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
> ---
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/zte/Kconfig | 13 ++++
> drivers/soc/zte/Makefile | 4 ++
> drivers/soc/zte/pm_domains.c | 150 +++++++++++++++++++++++++++++++++++++++++++
> drivers/soc/zte/pm_domains.h | 48 ++++++++++++++
> 6 files changed, 217 insertions(+)
> create mode 100644 drivers/soc/zte/Kconfig
> create mode 100644 drivers/soc/zte/Makefile
> create mode 100644 drivers/soc/zte/pm_domains.c
> create mode 100644 drivers/soc/zte/pm_domains.h
>
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index f31bceb..f09023f 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -11,5 +11,6 @@ source "drivers/soc/tegra/Kconfig"
> source "drivers/soc/ti/Kconfig"
> source "drivers/soc/ux500/Kconfig"
> source "drivers/soc/versatile/Kconfig"
> +source "drivers/soc/zte/Kconfig"
>
> endmenu
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 50c23d0..05eae52 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -16,3 +16,4 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-$(CONFIG_SOC_TI) += ti/
> obj-$(CONFIG_ARCH_U8500) += ux500/
> obj-$(CONFIG_PLAT_VERSATILE) += versatile/
> +obj-$(CONFIG_ARCH_ZX) += zte/
> diff --git a/drivers/soc/zte/Kconfig b/drivers/soc/zte/Kconfig
> new file mode 100644
> index 0000000..4953c3fa
> --- /dev/null
> +++ b/drivers/soc/zte/Kconfig
> @@ -0,0 +1,13 @@
> +#
> +# zx SoC drivers
> +#
> +menuconfig SOC_ZX
> + bool "zx SoC driver support"
> +
> +if SOC_ZX
> +
> +config ZX_PM_DOMAINS
> + bool "zx PM domains"
> + depends on PM_GENERIC_DOMAINS
> +
> +endif
> diff --git a/drivers/soc/zte/Makefile b/drivers/soc/zte/Makefile
> new file mode 100644
> index 0000000..97ac8ea
> --- /dev/null
> +++ b/drivers/soc/zte/Makefile
> @@ -0,0 +1,4 @@
> +#
> +# zx SOC drivers
> +#
> +obj-$(CONFIG_ZX_PM_DOMAINS) += pm_domains.o
> diff --git a/drivers/soc/zte/pm_domains.c b/drivers/soc/zte/pm_domains.c
> new file mode 100644
> index 0000000..e4d1235
> --- /dev/null
> +++ b/drivers/soc/zte/pm_domains.c
> @@ -0,0 +1,150 @@
> +/*
> + * Copyright (C) 2015 ZTE Ltd.
> + *
> + * Author: Baoyou Xie <baoyou.xie@linaro.org>
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include "pm_domains.h"
> +
> +#define PCU_DM_CLKEN(zpd) ((zpd)->reg_offset[REG_CLKEN])
> +#define PCU_DM_ISOEN(zpd) ((zpd)->reg_offset[REG_ISOEN])
> +#define PCU_DM_RSTEN(zpd) ((zpd)->reg_offset[REG_RSTEN])
> +#define PCU_DM_PWREN(zpd) ((zpd)->reg_offset[REG_PWREN])
> +#define PCU_DM_PWRDN(zpd) ((zpd)->reg_offset[REG_PWRDN])
> +#define PCU_DM_ACK_SYNC(zpd) ((zpd)->reg_offset[REG_ACK_SYNC])
> +
> +static void __iomem *pcubase;
> +
> +int zx_normal_power_on(struct generic_pm_domain *domain)
> +{
> + struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
> + unsigned long loop = 1000;
> + u32 val;
> +
> + if (zpd->polarity == PWREN) {
> + val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd));
> + val |= BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd));
> + } else {
> + val = readl_relaxed(pcubase + PCU_DM_PWRDN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_PWRDN(zpd));
> + }
Only manipulate value in if/else clause can save 3 lines of register
read/write and keep code simple.
> +
> + do {
> + udelay(1);
> + val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd))
> + & BIT(zpd->bit);
> + } while (--loop && !val);
> +
> + if (!loop) {
> + pr_err("Error: %s %s fail\n", __func__, domain->name);
> + return -EIO;
> + }
> +
> + val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val | BIT(zpd->bit), pcubase + PCU_DM_RSTEN(zpd));
> + udelay(5);
> +
> + val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd));
> + udelay(5);
> +
> + val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val | BIT(zpd->bit), pcubase + PCU_DM_CLKEN(zpd));
> + udelay(5);
> +
> + pr_info("normal poweron %s\n", domain->name);
> +
> + return 0;
> +}
> +
> +int zx_normal_power_off(struct generic_pm_domain *domain)
> +{
> + struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
> + unsigned long loop = 1000;
> + u32 val;
> +
> + val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd));
> + udelay(5);
> +
> + val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val | BIT(zpd->bit), pcubase + PCU_DM_ISOEN(zpd));
> + udelay(5);
> +
> + val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd));
> + udelay(5);
> +
> + if (zpd->polarity == PWREN) {
> + val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd));
> + val &= ~BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd));
> + } else {
> + val = readl_relaxed(pcubase + PCU_DM_PWRDN(zpd));
> + val |= BIT(zpd->bit);
> + writel_relaxed(val, pcubase + PCU_DM_PWRDN(zpd));
> + }
Ditto.
> +
> + do {
> + udelay(1);
> + val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd))
> + & BIT(zpd->bit);
> + } while (--loop && val);
> +
> + if (!loop) {
> + pr_err("Error: %s %s fail\n", __func__, domain->name);
> + return -EIO;
> + }
> +
> + pr_info("normal poweroff %s\n", domain->name);
> +
> + return 0;
> +}
> +
> +int
> +zx_pd_probe(struct platform_device *pdev,
> + struct generic_pm_domain **zx_pm_domains,
> + int domain_num)
Alignment should match open parenthesis. One more space is needed
here. You do not need a single line for int.
> +{
> + struct genpd_onecell_data *genpd_data;
> + struct resource *res;
> + int i;
> +
> + genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL);
> + if (!genpd_data)
> + return -ENOMEM;
> +
> + genpd_data->domains = zx_pm_domains;
> + genpd_data->num_domains = domain_num;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(&pdev->dev, "no memory resource defined\n");
> + return -ENODEV;
> + }
> +
> + pcubase = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(pcubase)) {
> + dev_err(&pdev->dev, "ioremap fail.\n");
> + return -EIO;
> + }
> +
> + for (i = 0; i < domain_num; ++i)
> + pm_genpd_init(zx_pm_domains[i], NULL, false);
> +
> + of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data);
> + dev_info(&pdev->dev, "powerdomain init ok\n");
> + return 0;
> +}
> diff --git a/drivers/soc/zte/pm_domains.h b/drivers/soc/zte/pm_domains.h
> new file mode 100644
> index 0000000..d3a52fd
> --- /dev/null
> +++ b/drivers/soc/zte/pm_domains.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (c) 2015 ZTE Co., Ltd.
> + * http://www.zte.com.cn
> + *
> + * Header for ZTE's Power Domain Driver support
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ZTE_PM_DOMAIN_H
> +#define __ZTE_PM_DOMAIN_H
> +
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +
> +enum {
> + REG_CLKEN,
> + REG_ISOEN,
> + REG_RSTEN,
> + REG_PWREN,
> + REG_PWRDN,
> + REG_ACK_SYNC,
> +
> + /* The size of the array - must be last */
> + REG_ARRAY_SIZE,
> +};
> +
> +enum zx_power_polarity {
> + PWREN,
> + PWRDN,
> +};
> +
> +struct zx_pm_domain {
> + struct generic_pm_domain dm;
> + const u16 bit;
> + const enum zx_power_polarity polarity;
> + const u16 *reg_offset;
> +};
> +
> +extern int zx_normal_power_on(struct generic_pm_domain *domain);
> +extern int zx_normal_power_off(struct generic_pm_domain *domain);
> +extern int
> +zx_pd_probe(struct platform_device *pdev,
> + struct generic_pm_domain **zx_pm_domains,
> + int domain_num);
> +#endif /* __ZTE_PM_DOMAIN_H */
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
From: Joel Stanley @ 2016-12-08 2:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206025321.1792-5-andrew@aj.id.au>
On Tue, Dec 6, 2016 at 1:23 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends
> on bits in both the System Control Unit and the LPC Host Controller.
>
> The Aspeed LPC Host Controller is described as a child node of the
> LPC host-range syscon device for arbitration of access by the host
> controller and pinmux drivers.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> index a97131aba446..9de318ef72da 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> @@ -109,3 +109,25 @@ lpc: lpc at 1e789000 {
> };
> };
>
> +Host Node Children
> +==================
> +
> +LPC Host Controller
> +-------------------
> +
> +The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
> +between the host and the baseboard management controller. The registers exist
> +in the "host" portion of the Aspeed LPC controller, which must be the parent of
> +the LPC host controller node.
> +
> +Required properties:
> +- compatible: "aspeed,ast2500-lhc";
Can you remind me why this binding doesn't cover the ast2400?
Cheers,
Joel
> +- reg: contains offset/length value of the LHC memory
> + region.
> +
> +Example:
> +
> +lhc: lhc at 20 {
> + compatible = "aspeed,ast2500-lhc";
> + reg = <0x20 0x24 0x48 0x8>;
> +};
> --
> 2.9.3
>
^ permalink raw reply
* [PATCH v3 3/6] mfd: dt: Add Aspeed Low Pin Count Controller bindings
From: Joel Stanley @ 2016-12-08 2:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206025321.1792-4-andrew@aj.id.au>
On Tue, Dec 6, 2016 at 1:23 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 111 +++++++++++++++++++++
> 1 file changed, 111 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
^ permalink raw reply
* [PATCH] USB: OHCI: nxp: fix code warnings
From: Vladimir Zapolskiy @ 2016-12-08 1:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481154851-20876-1-git-send-email-csmanjuvijay@gmail.com>
On 12/08/2016 01:54 AM, csmanjuvijay at gmail.com wrote:
> From: Manjunath Goudar <csmanjuvijay@gmail.com>
>
> This patch will fix the checkpatch.pl following warnings:
> WARNING: Missing a blank line after declarations
> WARNING: braces {} are not necessary for single statement blocks
>
> Signed-off-by: Manjunath Goudar <csmanjuvijay@gmail.com>
> Cc: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-usb at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> ---
Looks good, thank you for the change.
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
--
With best wishes,
Vladimir
^ permalink raw reply
* [PATCH v2 3/3] USB: OHCI: nxp: remove useless extern declaration
From: Vladimir Zapolskiy @ 2016-12-08 1:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481150056-3623-4-git-send-email-csmanjuvijay@gmail.com>
On 12/08/2016 12:34 AM, csmanjuvijay at gmail.com wrote:
> From: Manjunath Goudar <csmanjuvijay@gmail.com>
>
> Remove usb_disabled() extern declaration as it is already declared
> as extern in include/linux/usb.h.
>
> Signed-off-by: Manjunath Goudar <csmanjuvijay@gmail.com>
> Cc: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-usb at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> ---
> changelog V1->V2:
> patch discrition is update with proper message.
>
I'm fine with the change, thank you for the clean-up.
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
--
With best wishes,
Vladimir
^ permalink raw reply
* [PATCH] Input: lpc32xx-keys - fix invalid error handling of a requested irq
From: Dmitry Torokhov @ 2016-12-08 1:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481134387.9248.8.camel@localhost>
On Wed, Dec 07, 2016 at 01:13:07PM -0500, Sylvain Lemieux wrote:
> On Mon, 2016-12-05 at 03:47 +0200, Vladimir Zapolskiy wrote:
> > Semantics of NR_IRQS is different on machines with SPARSE_IRQ option
> > disabled or enabled, in the latter case IRQs are allocated starting
> > at least from the value specified by NR_IRQS and going upwards, so
> > the check of (irq >= NR_IRQ) to decide about an error code returned by
> > platform_get_irq() is completely invalid, don't attempt to overrule
> > irq subsystem in the driver.
> >
> > The change fixes lpc32xx_keys driver initialization on boot:
> >
> > lpc32xx_keys 40050000.key: failed to get platform irq
> > lpc32xx_keys: probe of 40050000.key failed with error -22
> >
> > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> > ---
> > drivers/input/keyboard/lpc32xx-keys.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> Cosmetic - please update the subject line when doing the commit:
> replace " -" by ":" after lpc32xx-keys
>
> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Applied, thank you.
--
Dmitry
^ permalink raw reply
* [PATCH 12/12] gpu: ipu-v3: Add smfc and ic client devices
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Adds IPU client devices for the SMFC and IC task units.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
drivers/gpu/ipu-v3/ipu-common.c | 87 +++++++++++++++++++++++++++++++++++++++--
include/video/imx-ipu-v3.h | 3 ++
2 files changed, 87 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index b6ca36b..729581d 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -1161,18 +1161,77 @@ static struct ipu_platform_reg client_reg[] = {
.pdata = {
.type = IPU_CSI,
.csi = 0,
- .dma[0] = IPUV3_CHANNEL_CSI0,
- .dma[1] = -EINVAL,
+ .dma[0] = -EINVAL,
},
.name = "imx-ipuv3-csi",
}, {
.pdata = {
.type = IPU_CSI,
.csi = 1,
+ .dma[0] = -EINVAL,
+ },
+ .name = "imx-ipuv3-csi",
+ }, {
+ .pdata = {
+ .type = IPU_SMFC,
+ .smfc = 0,
+ .dma[0] = IPUV3_CHANNEL_CSI0,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-smfc",
+ }, {
+ .pdata = {
+ .type = IPU_SMFC,
+ .smfc = 1,
.dma[0] = IPUV3_CHANNEL_CSI1,
.dma[1] = -EINVAL,
},
- .name = "imx-ipuv3-csi",
+ .name = "imx-ipuv3-smfc",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_ENCODER,
+ .ic = 0,
+ .dma[0] = IPUV3_CHANNEL_IC_PRP_ENC_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_VIEWFINDER,
+ .ic = 0,
+ .dma[0] = IPUV3_CHANNEL_IC_PRP_VF_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_POST_PROCESSOR,
+ .ic = 0,
+ .dma[0] = IPUV3_CHANNEL_IC_PP_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_POST_PROCESSOR,
+ .ic = 1,
+ .dma[0] = IPUV3_CHANNEL_IC_PP_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_POST_PROCESSOR,
+ .ic = 2,
+ .dma[0] = IPUV3_CHANNEL_IC_PP_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
}, {
.pdata = {
.type = IPU_DI,
@@ -1213,6 +1272,28 @@ of_get_ipu_client_node(struct ipu_soc *ipu, struct ipu_platform_reg *reg)
"ipu%d_csi", ipu->id + 1);
client_id = reg->pdata.csi;
break;
+ case IPU_SMFC:
+ snprintf(node_name, sizeof(node_name), "ipu%d_smfc",
+ ipu->id + 1);
+ client_id = reg->pdata.smfc;
+ break;
+ case IPU_IC:
+ switch (reg->pdata.ic_task) {
+ case IC_TASK_ENCODER:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_ic_prpenc", ipu->id + 1);
+ break;
+ case IC_TASK_VIEWFINDER:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_ic_prpvf", ipu->id + 1);
+ break;
+ case IC_TASK_POST_PROCESSOR:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_ic_pp", ipu->id + 1);
+ break;
+ }
+ client_id = reg->pdata.ic;
+ break;
case IPU_DI:
snprintf(node_name, sizeof(node_name),
"ipu%d_di", ipu->id + 1);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 7709af7..4e70ca4 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -418,6 +418,9 @@ int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
struct ipu_client_platformdata {
enum ipu_unit_type type;
int csi;
+ int smfc;
+ int ic_task;
+ int ic;
int di;
int dc;
int dp;
--
2.7.4
^ permalink raw reply related
* [PATCH 11/12] gpu: ipu-v3: lookup ipu client nodes by name
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
To allow for IPU clients containing multiple ports, they are no longer
a single port node name, but have a name of the format
"ipu<id>_<unit>". So we can no longer use of_graph_get_port_by_id()
to lookup the client node.
Create the function of_get_ipu_client_node() that looks up the client
node by node name and unit id. The ipu_unit_type enumeration is added
to the client_reg[] entries to compose the node names.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
drivers/gpu/ipu-v3/ipu-common.c | 55 +++++++++++++++++++++++++++++++++++------
1 file changed, 47 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 97218af..b6ca36b 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -1159,6 +1159,7 @@ struct ipu_platform_reg {
static struct ipu_platform_reg client_reg[] = {
{
.pdata = {
+ .type = IPU_CSI,
.csi = 0,
.dma[0] = IPUV3_CHANNEL_CSI0,
.dma[1] = -EINVAL,
@@ -1166,6 +1167,7 @@ static struct ipu_platform_reg client_reg[] = {
.name = "imx-ipuv3-csi",
}, {
.pdata = {
+ .type = IPU_CSI,
.csi = 1,
.dma[0] = IPUV3_CHANNEL_CSI1,
.dma[1] = -EINVAL,
@@ -1173,6 +1175,7 @@ static struct ipu_platform_reg client_reg[] = {
.name = "imx-ipuv3-csi",
}, {
.pdata = {
+ .type = IPU_DI,
.di = 0,
.dc = 5,
.dp = IPU_DP_FLOW_SYNC_BG,
@@ -1182,6 +1185,7 @@ static struct ipu_platform_reg client_reg[] = {
.name = "imx-ipuv3-crtc",
}, {
.pdata = {
+ .type = IPU_DI,
.di = 1,
.dc = 1,
.dp = -EINVAL,
@@ -1195,6 +1199,46 @@ static struct ipu_platform_reg client_reg[] = {
static DEFINE_MUTEX(ipu_client_id_mutex);
static int ipu_client_id;
+static struct device_node *
+of_get_ipu_client_node(struct ipu_soc *ipu, struct ipu_platform_reg *reg)
+{
+ struct device *dev = ipu->dev;
+ struct device_node *client;
+ char node_name[32];
+ u32 id, client_id = 0;
+
+ switch (reg->pdata.type) {
+ case IPU_CSI:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_csi", ipu->id + 1);
+ client_id = reg->pdata.csi;
+ break;
+ case IPU_DI:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_di", ipu->id + 1);
+ client_id = reg->pdata.di;
+ break;
+ default:
+ client = NULL;
+ goto out;
+ }
+
+ for_each_child_of_node(dev->of_node, client) {
+ if (client->name &&
+ (of_node_cmp(client->name, node_name) == 0)) {
+ of_property_read_u32(client, "reg", &id);
+ if (id == client_id)
+ break;
+ }
+ }
+out:
+ if (!client)
+ dev_info(dev, "no %s%d node in %s, not using %s%d\n",
+ node_name, client_id, dev->of_node->full_name,
+ node_name, client_id);
+ return client;
+}
+
static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
{
struct device *dev = ipu->dev;
@@ -1211,15 +1255,10 @@ static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
struct platform_device *pdev;
struct device_node *of_node;
- /* Associate subdevice with the corresponding port node */
- of_node = of_graph_get_port_by_id(dev->of_node, i);
- if (!of_node) {
- dev_info(dev,
- "no port@%d node in %s, not using %s%d\n",
- i, dev->of_node->full_name,
- (i / 2) ? "DI" : "CSI", i % 2);
+ /* Associate subdevice with the corresponding client node */
+ of_node = of_get_ipu_client_node(ipu, reg);
+ if (!of_node)
continue;
- }
pdev = platform_device_alloc(reg->name, id++);
if (!pdev) {
--
2.7.4
^ permalink raw reply related
* [PATCH 10/12] gpu: ipu-v3: Add ipu_unit_type enumeration
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Adds an enumeration of the major IPUv3 subunits. Provide that info
in struct ipu_client_platformdata to more easily determine the IPU
client type.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
include/video/imx-ipu-v3.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 53cd07c..7709af7 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -28,6 +28,23 @@ enum ipuv3_type {
IPUV3H,
};
+/*
+ * Enumeration of the major IPU subunits
+ */
+enum ipu_unit_type {
+ IPU_IDMAC = 0,
+ IPU_CM,
+ IPU_CSI,
+ IPU_SMFC,
+ IPU_IC,
+ IPU_VDI,
+ IPU_IRT,
+ IPU_DC,
+ IPU_DI,
+ IPU_DP,
+ IPU_DMFC,
+};
+
#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
/*
@@ -399,6 +416,7 @@ int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
bool hflip, bool vflip);
struct ipu_client_platformdata {
+ enum ipu_unit_type type;
int csi;
int di;
int dc;
--
2.7.4
^ permalink raw reply related
* [PATCH 09/12] ARM: dts: imx6-sabreauto: add the ADV7180 video decoder
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Enables the ADV7180 decoder sensor. The ADV7180 connects to the
parallel-bus mux input on ipu1_csi0_mux.
On the sabreauto, two analog video inputs are routed to the ADV7180,
composite on Ain1, and composite on Ain3. Those inputs are defined
via inputs and input-names under the ADV7180 node. The ADV7180 power
pin is via max7310_b port expander.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 62 ++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index d74882a..9222026 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -147,10 +147,48 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ camera: adv7180 at 21 {
+ compatible = "adi,adv7180";
+ reg = <0x21>;
+ powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <27 0x8>;
+ inputs = <0x00 0x02>;
+ input-names = "ADV7180 Composite on Ain1",
+ "ADV7180 Composite on Ain3";
+
+ port {
+ adv7180_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
};
};
};
+&ipu1_smfc0 {
+ fim {
+ enable = <1>;
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
+ bus-width = <8>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
&clks {
assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_PLL4_BYPASS>,
@@ -451,6 +489,30 @@
>;
};
+ pinctrl_ipu1_csi0: ipu1grp-csi0 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
+ MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
+ MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
+ MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
+ MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
+ MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
+ MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
+ MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ >;
+ };
+
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
--
2.7.4
^ permalink raw reply related
* [PATCH 08/12] ARM: dts: imx6-sabreauto: add pinctrl for gpt input capture
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Add pinctrl groups for both GPT input capture channels.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 944a4fa..d74882a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -457,6 +457,18 @@
>;
};
+ pinctrl_gpt_input_capture0: gptinputcapture0grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x80000000
+ >;
+ };
+
+ pinctrl_gpt_input_capture1: gptinputcapture1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x80000000
+ >;
+ };
+
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
--
2.7.4
^ permalink raw reply related
* [PATCH 07/12] ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_b
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
The reset pin to the port expander chip (MAX7310) is controlled by a gpio,
so define a reset-gpios property to control it. There are three MAX7310's
on the SabreAuto CPU card (max7310_[abc]), but all use the same pin for
their reset. Since all can't acquire the same pin, assign it to max7310_b,
that chip is needed by more functions (usb and adv7180).
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 043d20c..944a4fa 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -136,6 +136,9 @@
reg = <0x32>;
gpio-controller;
#gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max7310>;
+ reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
max7310_c: gpio at 34 {
@@ -442,6 +445,12 @@
>;
};
+ pinctrl_max7310: max7310grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000
+ >;
+ };
+
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
--
2.7.4
^ permalink raw reply related
* [PATCH 06/12] ARM: dts: imx6-sabreauto: create i2cmux for i2c3
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
The sabreauto uses a steering pin to select between the SDA signal on
i2c3 bus, and a data-in pin for an SPI NOR chip. Use i2cmux to control
this steering pin. Idle state of the i2cmux selects SPI NOR. This is not
a classic way to use i2cmux, since one side of the mux selects something
other than an i2c bus, but it works and is probably the cleanest
solution. Note that if one thread is attempting to access SPI NOR while
another thread is accessing i2c3, the SPI NOR access will fail since the
i2cmux has selected the SDA pin rather than SPI NOR data-in. This couldn't
be avoided in any case, the board is not designed to allow concurrent
i2c3 and SPI NOR functions (and the default device-tree does not enable
SPI NOR anyway).
Devices hanging off i2c3 should now be defined under i2cmux, so
that the steering pin can be properly controlled to access those
devices. The port expanders (MAX7310) are thus moved into i2cmux.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 65 +++++++++++++++++++++-----------
1 file changed, 44 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index e000e6f..043d20c 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -108,6 +108,44 @@
default-brightness-level = <7>;
status = "okay";
};
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3mux>;
+ mux-gpios = <&gpio5 4 0>;
+ i2c-parent = <&i2c3>;
+ idle-state = <0>;
+
+ i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ max7310_a: gpio at 30 {
+ compatible = "maxim,max7310";
+ reg = <0x30>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_b: gpio at 32 {
+ compatible = "maxim,max7310";
+ reg = <0x32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_c: gpio at 34 {
+ compatible = "maxim,max7310";
+ reg = <0x34>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
};
&clks {
@@ -291,27 +329,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
-
- max7310_a: gpio at 30 {
- compatible = "maxim,max7310";
- reg = <0x30>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max7310_b: gpio at 32 {
- compatible = "maxim,max7310";
- reg = <0x32>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max7310_c: gpio at 34 {
- compatible = "maxim,max7310";
- reg = <0x34>;
- gpio-controller;
- #gpio-cells = <2>;
- };
};
&iomuxc {
@@ -419,6 +436,12 @@
>;
};
+ pinctrl_i2c3mux: i2c3muxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
+ >;
+ };
+
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
--
2.7.4
^ permalink raw reply related
* [PATCH 05/12] ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor.
The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux.
The OV5640 connects to the input port on the MIPI CSI-2 receiver on
mipi_csi. It is set to transmit over MIPI virtual channel 1.
Until the OV5652 sensor module compatible with the SabreSD becomes
available for testing, the ov5642 node is currently disabled.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6dl-sabresd.dts | 5 ++
arch/arm/boot/dts/imx6q-sabresd.dts | 5 ++
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 114 ++++++++++++++++++++++++++++++++-
3 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 1e45f2f..6cf7a50 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -15,3 +15,8 @@
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 9cbdfe7..8c1d7ad 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -23,3 +23,8 @@
&sata {
status = "okay";
};
+
+&ipu1_csi1_from_mipi_vc1 {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 8e9e0d9..e36e1e7 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -10,6 +10,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
+#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -146,6 +147,33 @@
};
};
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vsync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
+&mipi_csi {
+ status = "okay";
+};
+
+/* Incoming port from sensor */
+&mipi_csi_from_mipi_sensor {
+ remote-endpoint = <&ov5640_to_mipi_csi>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
+
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@@ -214,7 +242,33 @@
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
- };
+ };
+
+ camera: ov5642 at 3c {
+ compatible = "ovti,ov5642";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ reg = <0x3c>;
+ xclk = <24000000>;
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen5_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwdn-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* SD1_DAT0 */
+ reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; /* SD1_DAT1 */
+ status = "disabled";
+
+ port {
+ ov5642_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
};
&i2c2 {
@@ -322,6 +376,34 @@
};
};
};
+
+ mipi_camera: ov5640 at 3c {
+ compatible = "ovti,ov5640_mipi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ reg = <0x3c>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ xclk = <24000000>;
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen5_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwdn-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; /* SD1_DAT2 */
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; /* SD1_CLK */
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_to_mipi_csi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_csi_from_mipi_sensor>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+ };
+ };
+ };
};
&i2c3 {
@@ -426,6 +508,36 @@
>;
};
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x80000000
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x80000000
+ >;
+ };
+
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1grp-csi0 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
--
2.7.4
^ permalink raw reply related
* [PATCH 04/12] ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor.
Both hang off the same i2c2 bus, so they require different (and non-
default) i2c slave addresses.
The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux.
The OV5640 connects to the input port on the MIPI CSI-2 receiver on
mipi_csi. It is set to transmit over MIPI virtual channel 1.
Note there is a pin conflict with GPIO6. This pin functions as a power
input pin to the OV5642, but ENET uses it as the h/w workaround for
erratum ERR006687, to wake-up the ARM cores on normal RX and TX packet
done events (see 6261c4c8). So workaround 6261c4c8 is reverted here to
support the OV5642, and the "fsl,err006687-workaround-present" boolean
also must be removed. The result is that the CPUidle driver will no longer
allow entering the deep idle states on the sabrelite.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6dl-sabrelite.dts | 5 ++
arch/arm/boot/dts/imx6q-sabrelite.dts | 6 ++
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 122 ++++++++++++++++++++++++++++++-
3 files changed, 129 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/imx6dl-sabrelite.dts
index 0f06ca5..fec2524 100644
--- a/arch/arm/boot/dts/imx6dl-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6dl-sabrelite.dts
@@ -48,3 +48,8 @@
model = "Freescale i.MX6 DualLite SABRE Lite Board";
compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl";
};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 66d10d8..9e2d26d 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -52,3 +52,9 @@
&sata {
status = "okay";
};
+
+&ipu1_csi1_from_mipi_vc1 {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
+
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 81dd6cd..d7fcb1a2 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -39,6 +39,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -96,6 +98,15 @@
};
};
+ mipi_xclk: mipi_xclk {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ clock-output-names = "mipi_pwm3";
+ pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
+ status = "okay";
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -220,6 +231,22 @@
};
};
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@@ -271,9 +298,6 @@
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
- fsl,err006687-workaround-present;
status = "okay";
};
@@ -302,6 +326,52 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+
+ camera: ov5642 at 42 {
+ compatible = "ovti,ov5642";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ clock-names = "xclk";
+ reg = <0x42>;
+ xclk = <24000000>;
+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ pwdn-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov5642_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
+
+ mipi_camera: ov5640 at 40 {
+ compatible = "ovti,ov5640_mipi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ clocks = <&mipi_xclk>;
+ clock-names = "xclk";
+ reg = <0x40>;
+ xclk = <22000000>;
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
+ pwdn-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_to_mipi_csi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_csi_from_mipi_sensor>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+ };
+ };
+ };
};
&i2c3 {
@@ -374,7 +444,6 @@
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
@@ -449,6 +518,39 @@
>;
};
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x80000000
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
+ MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x80000000
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1grp-csi0 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
+ >;
+ };
+
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
+ >;
+ };
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
@@ -605,3 +707,15 @@
vmmc-supply = <®_3p3v>;
status = "okay";
};
+
+&mipi_csi {
+ status = "okay";
+};
+
+/* Incoming port from sensor */
+&mipi_csi_from_mipi_sensor {
+ remote-endpoint = <&ov5640_to_mipi_csi>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
+
--
2.7.4
^ permalink raw reply related
* [PATCH 03/12] ARM: dts: imx6qdl: add video capture devices and connections
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
From: Philipp Zabel <p.zabel@pengutronix.de>
This patch adds the IPU subunit devices involved in video capture and
image conversion, and defines all the possible hardware connections
between them via OF graphs.
External to the IPU:
Video input multiplexers are defined that multiplex inputs from camera
sensors and the MIPI-CSI2 gasket, to the IPU CSIs.
On i.MX6Q/D two two-input multiplexers in front of IPU1 CSI0 and IPU2 CSI1
allow to select between CSI0/1 parallel input pads and the MIPI CSI-2 virtual
channels 0/3.
On i.MX6DL/S two five-input multiplexers in front of IPU1 CSI0 and IPU1 CSI1
allow to select between CSI0/1 parallel input pads and any of the four MIPI
CSI-2 virtual channels.
Internal to the IPU:
The IPU CSI, SMFC, IC-PRPENC, IC-PRPVF, and IC-PP subunits are added
as children of the IPUs, along with the hardware-supported connections
between them.
Finally, a media device node is defined. A video camera interface
and mem2mem device are defined as children of the media device.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
arch/arm/boot/dts/imx6dl.dtsi | 190 ++++++++++++++++
arch/arm/boot/dts/imx6q.dtsi | 487 +++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/imx6qdl.dtsi | 368 +++++++++++++++++++++++++++++++
3 files changed, 1045 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 1ade195..4bab076 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -109,6 +109,120 @@
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>;
};
+
+ ipu1_csi0_mux: ipu1_csi0_mux at 34 {
+ compatible = "imx-video-mux";
+ reg = <0x34 0x07>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <5>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ ipu1_csi0_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 5 {
+ reg = <5>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu1_csi1_mux: ipu1_csi1_mux at 34 {
+ compatible = "imx-video-mux";
+ reg = <0x34 0x38>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <5>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu1_csi1_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu1_csi1_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu1_csi1_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ ipu1_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+
+ ipu1_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 5 {
+ reg = <5>;
+
+ ipu1_csi1_mux_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
+ };
+ };
+ };
};
&gpio1 {
@@ -184,3 +298,79 @@
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};
+
+&ipu1_csi1 {
+ port at 0 {
+ reg = <0>;
+ ipu1_csi1_from_ipu1_csi1_mux: endpoint {
+ remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
+ };
+ };
+};
+
+&mipi_csi {
+ sink-ports = <1>;
+
+ port at 0 {
+ reg = <0>;
+
+ mipi_csi_from_mipi_sensor: endpoint {
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+
+ mipi_vc0_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc1_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
+ };
+
+ mipi_vc1_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc2_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
+ };
+
+ mipi_vc2_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc3_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
+ };
+
+ mipi_vc3_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 2b261ba..a0602c5 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -142,11 +142,270 @@
resets = <&src 4>;
ipu2_csi0: ipu2_csi at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_csi0_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_csi0_to_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_from_csi0>;
+ };
+ ipu2_csi0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_csi0>;
+ };
+ ipu2_csi0_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_from_csi0>;
+ };
+ };
};
ipu2_csi1: ipu2_csi at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_csi1_from_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_csi1_to_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_from_csi1>;
+ };
+ ipu2_csi1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_csi1>;
+ };
+ ipu2_csi1_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_from_csi1>;
+ };
+ };
+ };
+
+ ipu2_smfc0: ipu2_smfc at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_smfc0_from_csi0: endpoint {
+ remote-endpoint = <&ipu2_csi0_to_smfc0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_smfc0_to_ic_pp1: pp-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_from_smfc0>;
+ };
+ ipu2_smfc0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_smfc0>;
+ };
+ ipu2_smfc0_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_smfc0>;
+ };
+ ipu2_smfc0_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_smfc0>;
+ };
+ };
+ };
+
+ ipu2_smfc1: ipu2_smfc at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_smfc1_from_csi1: endpoint {
+ remote-endpoint = <&ipu2_csi1_to_smfc1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_smfc1_to_ic_pp2: pp-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_from_smfc1>;
+ };
+ ipu2_smfc1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_smfc1>;
+ };
+ ipu2_smfc1_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_smfc1>;
+ };
+ ipu2_smfc1_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_smfc1>;
+ };
+ };
+ };
+
+ ipu2_ic_prpenc: ipu2_ic_prpenc at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_prpenc_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu2_csi0_to_ic_prpenc>;
+ };
+ ipu2_ic_prpenc_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu2_csi1_to_ic_prpenc>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_prpenc_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_prpenc>;
+ };
+ ipu2_ic_prpenc_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_prpenc>;
+ };
+ };
+ };
+
+ ipu2_ic_prpvf: ipu2_ic_prpvf at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_prpvf_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu2_csi0_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu2_csi1_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_m2m1: m2m1-endpoint {
+ remote-endpoint = <&m2m1_to_ic_prpvf>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_prpvf_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu2_ic_pp0_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_m2m1: m2m1-endpoint {
+ remote-endpoint = <&m2m1_from_ic_prpvf>;
+ };
+ };
+ };
+
+ ipu2_ic_pp0: ipu2_ic_pp at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_pp0_from_m2m1: m2m1-endpoint {
+ remote-endpoint = <&m2m1_to_ic_pp0>;
+ };
+ ipu2_ic_pp0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_ic_pp0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_pp0_to_m2m1: endpoint {
+ remote-endpoint = <&m2m1_from_ic_pp0>;
+ };
+ };
+ };
+
+ ipu2_ic_pp1: ipu2_ic_pp at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_pp1_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_ic_pp1>;
+ };
+ ipu2_ic_pp1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_ic_pp1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_pp1_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_pp1>;
+ };
+ ipu2_ic_pp1_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_pp1>;
+ };
+ };
+ };
+
+ ipu2_ic_pp2: ipu2_ic_pp at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <2>;
+
+ port at 0 {
+ reg = <0>;
+ ipu2_ic_pp2_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_ic_pp2>;
+ };
+ ipu2_ic_pp2_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_ic_pp2>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu2_ic_pp2_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_pp2>;
+ };
+ ipu2_ic_pp2_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_pp2>;
+ };
+ };
};
ipu2_di0: ipu2_di at 0 {
@@ -207,6 +466,73 @@
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
};
+
+
+ ipu1_csi0_mux: ipu1_csi0_mux at 4 {
+ compatible = "imx-video-mux";
+ reg = <0x04 0x80000>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu2_csi1_mux: ipu2_csi1_mux at 4 {
+ compatible = "imx-video-mux";
+ reg = <0x04 0x100000>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu2_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu2_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu2_csi1_mux_to_ipu2_csi1: endpoint {
+ remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
+ };
+ };
+ };
};
&gpio1 {
@@ -266,6 +592,15 @@
};
};
+&ipu1_csi1 {
+ port at 0 {
+ reg = <0>;
+ ipu1_csi1_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
+ };
+ };
+};
+
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -312,6 +647,49 @@
};
};
+&mipi_csi {
+ sink-ports = <1>;
+
+ port at 0 {
+ reg = <0>;
+
+ mipi_csi_from_mipi_sensor: endpoint {
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ mipi_vc1_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ mipi_vc2_to_ipu2_csi0: endpoint {
+ remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+
+ mipi_vc3_to_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
+
&mipi_dsi {
ports {
port at 2 {
@@ -335,3 +713,112 @@
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};
+
+&media0 {
+ m2m1: m2m at 1 {
+ compatible = "fsl,imx-media-mem2mem";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ };
+
+ port at 1 {
+ reg = <1>;
+ m2m1_from_ic_pp0: endpoint {
+ remote-endpoint = <&ipu2_ic_pp0_to_m2m1>;
+ };
+ m2m1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_m2m1>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+ m2m1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_m2m1>;
+ };
+ m2m1_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu2_ic_pp0_from_m2m1>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+ };
+ };
+
+ camif2: camif at 2 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <2>;
+
+ port at 0 {
+ reg = <0>;
+ camif2_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_camif2>;
+ };
+ camif2_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_camif2>;
+ };
+ camif2_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_to_camif2>;
+ };
+ camif2_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_camif2>;
+ };
+ camif2_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_to_camif2>;
+ };
+ camif2_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_to_camif2>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+ };
+
+ camif3: camif at 3 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <3>;
+
+ port at 0 {
+ reg = <0>;
+ camif3_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_camif3>;
+ };
+ camif3_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_camif3>;
+ };
+ camif3_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_to_camif3>;
+ };
+ camif3_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_camif3>;
+ };
+ camif3_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_to_camif3>;
+ };
+ camif3_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_to_camif3>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 2465187..ea1e2f3 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1123,6 +1123,8 @@
mipi_csi: mipi at 021dc000 {
compatible = "fsl,imx-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 100 0x04>, <0 101 0x04>;
clocks = <&clks IMX6QDL_CLK_HSI_TX>,
<&clks IMX6QDL_CLK_VIDEO_27M>,
@@ -1227,11 +1229,263 @@
resets = <&src 2>;
ipu1_csi0: ipu1_csi at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_csi0_from_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_csi0_to_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_from_csi0>;
+ };
+ ipu1_csi0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_csi0>;
+ };
+ ipu1_csi0_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_from_csi0>;
+ };
+ };
};
ipu1_csi1: ipu1_csi at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 1 {
+ reg = <1>;
+ ipu1_csi1_to_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_from_csi1>;
+ };
+ ipu1_csi1_to_ic_prpvf: prendpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_csi1>;
+ };
+ ipu1_csi1_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_from_csi1>;
+ };
+ };
+ };
+
+ ipu1_smfc0: ipu1_smfc at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_smfc0_from_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_to_smfc0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_smfc0_to_ic_pp1: pp-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_from_smfc0>;
+ };
+ ipu1_smfc0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_smfc0>;
+ };
+ ipu1_smfc0_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_smfc0>;
+ };
+ ipu1_smfc0_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_smfc0>;
+ };
+ };
+ };
+
+ ipu1_smfc1: ipu1_smfc at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_smfc1_from_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_to_smfc1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_smfc1_to_ic_pp2: pp-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_from_smfc1>;
+ };
+ ipu1_smfc1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_smfc1>;
+ };
+ ipu1_smfc1_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_smfc1>;
+ };
+ ipu1_smfc1_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_smfc1>;
+ };
+ };
+ };
+
+ ipu1_ic_prpenc: ipu1_ic_prpenc at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_prpenc_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu1_csi0_to_ic_prpenc>;
+ };
+ ipu1_ic_prpenc_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu1_csi1_to_ic_prpenc>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_prpenc_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_prpenc>;
+ };
+ ipu1_ic_prpenc_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_prpenc>;
+ };
+ };
+ };
+
+ ipu1_ic_prpvf: ipu1_ic_prpvf at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_prpvf_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu1_csi0_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu1_csi1_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_m2m0: m2m0-endpoint {
+ remote-endpoint = <&m2m0_to_ic_prpvf>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_prpvf_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu1_ic_pp0_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_m2m0: m2m0-endpoint {
+ remote-endpoint = <&m2m0_from_ic_prpvf>;
+ };
+ };
+ };
+
+ ipu1_ic_pp0: ipu1_ic_pp at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_pp0_from_m2m0: m2m0-endpoint {
+ remote-endpoint = <&m2m0_to_ic_pp0>;
+ };
+ ipu1_ic_pp0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_ic_pp0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_pp0_to_m2m0: endpoint {
+ remote-endpoint = <&m2m0_from_ic_pp0>;
+ };
+ };
+ };
+
+ ipu1_ic_pp1: ipu1_ic_pp at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_pp1_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_ic_pp1>;
+ };
+ ipu1_ic_pp1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_ic_pp1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_pp1_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_pp1>;
+ };
+ ipu1_ic_pp1_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_pp1>;
+ };
+ };
+ };
+
+ ipu1_ic_pp2: ipu1_ic_pp at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <2>;
+
+ port at 0 {
+ reg = <0>;
+ ipu1_ic_pp2_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_ic_pp2>;
+ };
+ ipu1_ic_pp2_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_ic_pp2>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ ipu1_ic_pp2_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_pp2>;
+ };
+ ipu1_ic_pp2_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_pp2>;
+ };
+ };
};
ipu1_di0: ipu1_di at 0 {
@@ -1284,5 +1538,119 @@
};
};
};
+
+ media0: media at 0 {
+ compatible = "fsl,imx-media", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ m2m0: m2m at 0 {
+ compatible = "fsl,imx-media-mem2mem";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ };
+
+ port at 1 {
+ reg = <1>;
+ m2m0_from_ic_pp0: endpoint {
+ remote-endpoint = <&ipu1_ic_pp0_to_m2m0>;
+ };
+ m2m0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_m2m0>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+ m2m0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_m2m0>;
+ };
+ m2m0_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu1_ic_pp0_from_m2m0>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+ };
+ };
+
+ camif0: camif at 0 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <0>;
+
+ port at 0 {
+ reg = <0>;
+ camif0_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_camif0>;
+ };
+ camif0_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_camif0>;
+ };
+ camif0_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_to_camif0>;
+ };
+ camif0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_camif0>;
+ };
+ camif0_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_to_camif0>;
+ };
+ camif0_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_to_camif0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+ };
+
+ camif1: camif at 1 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <1>;
+
+ port at 0 {
+ reg = <0>;
+ camif1_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_camif1>;
+ };
+ camif1_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_camif1>;
+ };
+ camif1_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_to_camif1>;
+ };
+ camif1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_camif1>;
+ };
+ camif1_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_to_camif1>;
+ };
+ camif1_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_to_camif1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+ };
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 02/12] ARM: dts: imx6qdl: rename ipu client nodes
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
To allow for IPU client devices that are composed of more than one
port for input and output (SMFC and IC), change the nodes from being
a single port node to nodes that can contain multiple ports. Rename
the nodes to use the following format: "ipu<id>_<subunit>".
The IPUv3 driver will then need to lookup the client nodes by name
rather than by port id.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6q.dtsi | 12 ++++++------
arch/arm/boot/dts/imx6qdl.dtsi | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9a5d0b..2b261ba 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -141,18 +141,18 @@
clock-names = "bus", "di0", "di1";
resets = <&src 4>;
- ipu2_csi0: port at 0 {
+ ipu2_csi0: ipu2_csi at 0 {
reg = <0>;
};
- ipu2_csi1: port at 1 {
+ ipu2_csi1: ipu2_csi at 1 {
reg = <1>;
};
- ipu2_di0: port at 2 {
+ ipu2_di0: ipu2_di at 0 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <2>;
+ reg = <0>;
ipu2_di0_disp0: disp0-endpoint {
};
@@ -174,10 +174,10 @@
};
};
- ipu2_di1: port at 3 {
+ ipu2_di1: ipu2_di at 1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <3>;
+ reg = <1>;
ipu2_di1_hdmi: hdmi-endpoint {
remote-endpoint = <&hdmi_mux_3>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e01e5d5..2465187 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1226,18 +1226,18 @@
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
- ipu1_csi0: port at 0 {
+ ipu1_csi0: ipu1_csi at 0 {
reg = <0>;
};
- ipu1_csi1: port at 1 {
+ ipu1_csi1: ipu1_csi at 1 {
reg = <1>;
};
- ipu1_di0: port at 2 {
+ ipu1_di0: ipu1_di at 0 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <2>;
+ reg = <0>;
ipu1_di0_disp0: disp0-endpoint {
};
@@ -1259,10 +1259,10 @@
};
};
- ipu1_di1: port at 3 {
+ ipu1_di1: ipu1_di at 1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <3>;
+ reg = <1>;
ipu1_di1_disp1: disp1-endpoint {
};
--
2.7.4
^ permalink raw reply related
* [PATCH 01/12] ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 node
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Add to the MIPI CSI2 receiver node: compatible string, interrupt sources,
clocks.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index b13b0b2..e01e5d5 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1121,7 +1121,14 @@
};
mipi_csi: mipi at 021dc000 {
+ compatible = "fsl,imx-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ interrupts = <0 100 0x04>, <0 101 0x04>;
+ clocks = <&clks IMX6QDL_CLK_HSI_TX>,
+ <&clks IMX6QDL_CLK_VIDEO_27M>,
+ <&clks IMX6QDL_CLK_EIM_SEL>;
+ clock-names = "dphy_clk", "cfg_clk", "pix_clk";
+ status = "disabled";
};
mipi_dsi: mipi at 021e0000 {
--
2.7.4
^ permalink raw reply related
* [PATCH 00/12] i.MX media devices and connections
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Philipp, Sascha, Shawn, et al,
I've been working for the past few months on a media driver for i.MX.
In addition to the media entities for the IPU-external units involved
with video capture (video mux and MIPI CSI-2 receiver), I've created
media entities for the IPU CSI, SMFC, and IC subunits. The IC entities
carry out scaling, CSC, horizontal/vertical flip, and rotation. In
addition, the IC-PRPVF entity carries out motion compensated
de-interlace.
The following series adds the OF device nodes and graphs that define
all the possible hardware connections supported by the i.MX involved
in video capture and image conversion.
Here are some of the pipelines defined by the OF graphs:
CSI -> IC-PRPENC
CSI -> IC-PRPVF
CSI -> IC-PRPVF -> IC-PP
CSI -> SMFC
CSI -> SMFC -> IC-PRPVF
CSI -> SMFC -> IC-PP
CSI -> SMFC -> IC-PRPVF -> IC-PP
You will notice that three IC-PP nodes are defined (ipu1_ic_pp0,
ipu1_ic_pp1, ipu1_ic_pp2, and same for ipu2). The reason for that
is that the IC-PP media entity uses the new ipu-image-conversion
API, which allows for multiple conversion contexts to be created.
Each IC-PP entity thus creates its own conversion context, and there
can be any number of IC-PP entities instantiated as needed by the OF
graph.
Camera sensor nodes are also added for the SabreAuto, SabreSD, and
SabreLite reference platforms.
The media driver is now in fairly good shape. It parses the OF graphs
to create the media pads and links. All the pipelines defined by the
OF graphs have been tested and are working. My media driver work is
at:
git at github.com:slongerbeam/mediatree.git, branch imx-media-staging-md-v2.
For an overview of the pipelines supported and usage notes for the
reference boards, you can refer to Documentation/media/v4l-drivers/imx.rst.
I realize there is collision here with the recent patch series posted by
Philipp, particularly around the video multiplexer and mipi csi-2 receiver
subdevs and OF graphs, as well as v4l2 capture drivers.
Philipp Zabel (1):
ARM: dts: imx6qdl: add video capture devices and connections
Steve Longerbeam (11):
ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 node
ARM: dts: imx6qdl: rename ipu client nodes
ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors
ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors
ARM: dts: imx6-sabreauto: create i2cmux for i2c3
ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_b
ARM: dts: imx6-sabreauto: add pinctrl for gpt input capture
ARM: dts: imx6-sabreauto: add the ADV7180 video decoder
gpu: ipu-v3: Add ipu_unit_type enumeration
gpu: ipu-v3: lookup ipu client nodes by name
gpu: ipu-v3: Add smfc and ic client devices
arch/arm/boot/dts/imx6dl-sabrelite.dts | 5 +
arch/arm/boot/dts/imx6dl-sabresd.dts | 5 +
arch/arm/boot/dts/imx6dl.dtsi | 190 ++++++++++++
arch/arm/boot/dts/imx6q-sabrelite.dts | 6 +
arch/arm/boot/dts/imx6q-sabresd.dts | 5 +
arch/arm/boot/dts/imx6q.dtsi | 497 ++++++++++++++++++++++++++++++-
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 148 +++++++--
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 122 +++++++-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 114 ++++++-
arch/arm/boot/dts/imx6qdl.dtsi | 385 +++++++++++++++++++++++-
drivers/gpu/ipu-v3/ipu-common.c | 142 ++++++++-
include/video/imx-ipu-v3.h | 21 ++
12 files changed, 1593 insertions(+), 47 deletions(-)
--
2.7.4
^ permalink raw reply
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