* [PATCH V7 5/8] arm64/dma-mapping: Implement DMA_ATTR_PRIVILEGED
From: Robin Murphy @ 2016-12-13 19:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <005f01d25571$3f75b5f0$be6121d0$@codeaurora.org>
On 13/12/16 18:46, Sricharan wrote:
> Hi Robin,
>
> <snip..>
>
>>>>>> return prot | IOMMU_READ | IOMMU_WRITE;
>>>>>
>>>>> ...and applying against -next now also needs this hunk:
>>>>>
>>>>> @@ -639,7 +639,7 @@ dma_addr_t iommu_dma_map_resource(struct device
>>>>> *dev, phys_addr_t phys,
>>>>> size_t size, enum dma_data_direction dir, unsigned long attrs)
>>>>> {
>>>>> return __iommu_dma_map(dev, phys, size,
>>>>> - dma_direction_to_prot(dir, false) | IOMMU_MMIO);
>>>>> + dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO);
>>>>> }
>>>>>
>>>>> void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
>>>>>
>>>>> With those two issues fixed up, I've given the series (applied to
>>>>> next-20161213) a spin on a SMMUv3/PL330 fast model and it still checks out.
>>>>>
>>>>
>>>> oops, sorry that i missed this in rebase. I can repost now with this fixed,
>>>> 'checks out' you mean something is not working correct ?
>>>
>>> No, I mean it _is_ still correct - I guess that's more of an idiom than
>>> I thought :)
>>>
>>
>> ha ok, thanks for the testing as well. I will just send a v8 with those two fixed now.
>
> Just while checking that i have not missed anything else, realized that the
> dma-mapping apis in arm as to be modified to pass the PRIVILIGED attributes
> as well. While my testing path was using the iommu_map directly i was not
> seeing this, but then i did a patch like below. I will just figure out another
> other codebase where the master uses the dma apis, test and add it in the
> V8 that i would send.
True, adding support to 32-bit as well can't hurt, and I guess it's
equally relevant to QC's GPU use-case. I haven't considered it myself
because AArch32 is immune to the specific PL330 problem which caught me
out - that subtle corner of VMSAv8 is unique to AArch64.
> From: Sricharan R <sricharan@codeaurora.org>
> Date: Tue, 13 Dec 2016 23:25:01 +0530
> Subject: [PATCH V8 6/9] arm/dma-mapping: Implement DMA_ATTR_PRIVILEGED
>
> The newly added DMA_ATTR_PRIVILEGED is useful for creating mappings that
> are only accessible to privileged DMA engines. Implementing it in dma-mapping
> for it to get used from the dma mappings apis.
>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> ---
> arch/arm/mm/dma-mapping.c | 24 +++++++++++++++---------
> 1 file changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index ab77100..e0d9923 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -1394,7 +1394,8 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages,
> * Create a mapping in device IO address space for specified pages
> */
> static dma_addr_t
> -__iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
> +__iommu_create_mapping(struct device *dev, struct page **pages, size_t size,
> + unsigned long attrs)
> {
> struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
> unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
> @@ -1419,7 +1420,7 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages,
>
> len = (j - i) << PAGE_SHIFT;
> ret = iommu_map(mapping->domain, iova, phys, len,
> - IOMMU_READ|IOMMU_WRITE);
> + __dma_info_to_prot(DMA_BIRECTIONAL, attrs));
> if (ret < 0)
> goto fail;
> iova += len;
> @@ -1476,7 +1477,8 @@ static struct page **__iommu_get_pages(void *cpu_addr, unsigned long attrs)
> }
>
> static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp,
> - dma_addr_t *handle, int coherent_flag)
> + dma_addr_t *handle, int coherent_flag,
> + unsigned long attrs)
> {
> struct page *page;
> void *addr;
> @@ -1488,7 +1490,7 @@ static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp,
> if (!addr)
> return NULL;
>
> - *handle = __iommu_create_mapping(dev, &page, size);
> + *handle = __iommu_create_mapping(dev, &page, size, attrs);
> if (*handle == DMA_ERROR_CODE)
> goto err_mapping;
>
> @@ -1522,7 +1524,8 @@ static void *__arm_iommu_alloc_attrs(struct device *dev, size_t size,
>
> if (coherent_flag == COHERENT || !gfpflags_allow_blocking(gfp))
> return __iommu_alloc_simple(dev, size, gfp, handle,
> - coherent_flag);
> + coherent_flag,
> + attrs);
Super-nit: unnecessary line break.
>
> /*
> * Following is a work-around (a.k.a. hack) to prevent pages
> @@ -1672,10 +1675,13 @@ static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
> GFP_KERNEL);
> }
>
> -static int __dma_direction_to_prot(enum dma_data_direction dir)
> +static int __dma_info_to_prot(enum dma_data_direction dir, unsigned long attrs)
> {
> int prot;
>
> + if (attrs & DMA_ATTR_PRIVILEGED)
> + prot |= IOMMU_PRIV;
> +
> switch (dir) {
> case DMA_BIDIRECTIONAL:
> prot = IOMMU_READ | IOMMU_WRITE;
> @@ -1722,7 +1728,7 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
> if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
> __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
>
> - prot = __dma_direction_to_prot(dir);
> + prot = __dma_info_to_prot(dir, attrs);
>
> ret = iommu_map(mapping->domain, iova, phys, len, prot);
> if (ret < 0)
> @@ -1930,7 +1936,7 @@ static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *p
> if (dma_addr == DMA_ERROR_CODE)
> return dma_addr;
>
> - prot = __dma_direction_to_prot(dir);
> + prot = __dma_info_to_prot(dir, attrs);
>
> ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
> if (ret < 0)
> @@ -2036,7 +2042,7 @@ static dma_addr_t arm_iommu_map_resource(struct device *dev,
> if (dma_addr == DMA_ERROR_CODE)
> return dma_addr;
>
> - prot = __dma_direction_to_prot(dir) | IOMMU_MMIO;
> + prot = __dma_info_to_prot(dir, attrs) | IOMMU_MMIO;
>
> ret = iommu_map(mapping->domain, dma_addr, addr, len, prot);
> if (ret < 0)
>
Looks reasonable to me. Assuming it survives testing:
Acked-by: Robin Murphy <robin.murphy@arm.com>
^ permalink raw reply
* [PATCH 4/6] ARM: dts: sun8i: add opp-v2 table for A33
From: Maxime Ripard @ 2016-12-13 19:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213152252.53749-5-icenowy@aosc.xyz>
On Tue, Dec 13, 2016 at 11:22:50PM +0800, Icenowy Zheng wrote:
> An operating point table is needed for the cpu frequency adjusting to
> work.
>
> The operating point table is converted from the common value in
> extracted script.fex from many A33 board/tablets.
>
> 1.344GHz is set as a turbo-mode operating point, as it's described as
> "extremity_freq" in the FEX file. (the "max_freq" is 1.2GHz)
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> arch/arm/boot/dts/sun8i-a33.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
> index 504996cbee29..035c058324b8 100644
> --- a/arch/arm/boot/dts/sun8i-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
> @@ -46,7 +46,45 @@
> #include <dt-bindings/dma/sun4i-a10.h>
>
> / {
> + cpu0_opp_table: opp_table0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp at 648000000 {
> + opp-hz = /bits/ 64 <648000000>;
> + opp-microvolt = <1040000>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
Please add new lines between the nodes.
> + opp at 816000000 {
> + opp-hz = /bits/ 64 <816000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
> + opp at 1008000000 {
> + opp-hz = /bits/ 64 <1008000000>;
> + opp-microvolt = <1200000>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
> + opp at 1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1320000>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + };
> + opp at 1344000000 {
> + opp-hz = /bits/ 64 <1344000000>;
> + opp-microvolt = <1460000>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + turbo-mode;
> + };
As far as I know, this OPP is not used by Allwinner, is not usable in
any A33 board so far (both the A33-olinuxino and the SinA33 do not
allow such a voltage on their CPU regulator), and overvolting and
overclocking is something that is very risky, and might lead to
stability issues.
Please remove this OPP.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 5/6] ARM: dts: sun8i: set cpu-supply in reference tablet DTSI
From: Maxime Ripard @ 2016-12-13 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213152252.53749-6-icenowy@aosc.xyz>
On Tue, Dec 13, 2016 at 11:22:51PM +0800, Icenowy Zheng wrote:
> All reference design A33 tablets uses DCDC2 of AXP223 as the power
> supply of the Cortex-A7 cores.
>
> Set the cpu-supply in the DTSI of sun8i reference tablets.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Applied, thanks
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH] Input: imx6ul_tsc - generalize the averaging property
From: Dmitry Torokhov @ 2016-12-13 19:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213191050.3yrmxaubpgjh65bz@rob-hp-laptop>
On December 13, 2016 11:10:50 AM PST, Rob Herring <robh@kernel.org> wrote:
>On Sun, Dec 11, 2016 at 09:06:43AM +0200, Guy Shapiro wrote:
>> Make the avarage-samples property a general touchscreen property
>> rather than imx6ul device specific.
>>
>> Signed-off-by: Guy Shapiro <guy.shapiro@mobi-wize.com>
>> ---
>> .../bindings/input/touchscreen/imx6ul_tsc.txt | 11 ++----
>> .../bindings/input/touchscreen/touchscreen.txt | 3 ++
>> drivers/input/touchscreen/imx6ul_tsc.c | 46
>++++++++++++++++------
>> 3 files changed, 41 insertions(+), 19 deletions(-)
>
>You can't just switch existing bindings as that breaks compatibility
>with old dtbs. The kernel driver would need to support both. Just
>introduce the new common property and use it for your device.
>
The old binding is only in my tree at the moment, so I do not think there is compatibility concerns.
Are you OK with the new binding itself?
Thanks.
--
Dmitry
^ permalink raw reply
* [PATCH 6/6] ARM: dts: sun8i: raise the max voltage of DCDC2 in sun8i reference tablets
From: Maxime Ripard @ 2016-12-13 19:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213152252.53749-7-icenowy@aosc.xyz>
On Tue, Dec 13, 2016 at 11:22:52PM +0800, Icenowy Zheng wrote:
> The "extremity_freq" frequency described in the original FEX files uses
> a voltage of 1.46v, which is beyond the current maximum voltage value of
> DCDC2 (Cortex-A7 supply) in the sun8i reference tablet DTSI file.
>
> Raise the maximum value to 1.46v.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
> index 7ac8bb4bc95a..325ca5bd67a5 100644
> --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
> +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
> @@ -180,7 +180,7 @@
> ®_dcdc2 {
> regulator-always-on;
> regulator-min-microvolt = <900000>;
> - regulator-max-microvolt = <1400000>;
> + regulator-max-microvolt = <1460000>;
This is outside of the voltage range tolerated by the CPU. NAK.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v6] arm64: fpsimd: improve stacking logic in non-interruptible context
From: Ard Biesheuvel @ 2016-12-13 19:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213173457.GF23377@e104818-lin.cambridge.arm.com>
On 13 December 2016 at 17:34, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Tue, Dec 13, 2016 at 12:35:29PM +0000, Ard Biesheuvel wrote:
>> Currently, we allow kernel mode NEON in softirq or hardirq context by
>> stacking and unstacking a slice of the NEON register file for each call
>> to kernel_neon_begin() and kernel_neon_end(), respectively.
>>
>> Given that
>> a) a CPU typically spends most of its time in userland, during which time
>> no kernel mode NEON in process context is in progress,
>> b) a CPU spends most of its time in the kernel doing other things than
>> kernel mode NEON when it gets interrupted to perform kernel mode NEON
>> in softirq context
>>
>> the stacking and subsequent unstacking is only necessary if we are
>> interrupting a thread while it is performing kernel mode NEON in process
>> context, which means that in all other cases, we can simply preserve the
>> userland FPSIMD state once, and only restore it upon return to userland,
>> even if we are being invoked from softirq or hardirq context.
>>
>> So instead of checking whether we are running in interrupt context, keep
>> track of the level of nested kernel mode NEON calls in progress, and only
>> perform the eager stack/unstack if the level exceeds 1.
>>
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>> v6:
>> - use a spinlock instead of disabling interrupts
>
> My concern with the spinlock or disabling interrupts is the latency if
> we ever get some insanely long SVE vectors.
>
Thinking about this a bit more, and trying a couple of things in code,
I think this looks like it could be a nasty problem.
The primary issue is that *any* code that handles the FP/SIMD state,
i.e., preserve it, restore it, etc, could be interrupted, and if
kernel_neon_begin()/_end() was used during that time, the top SVE end
of the registers is just blown away if we don't make the nested
save/restore SVE aware.
For instance, looking at
void fpsimd_restore_current_state(void)
{
preempt_disable();
if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
struct fpsimd_state *st = ¤t->thread.fpsimd_state;
fpsimd_load_state(st);
this_cpu_write(fpsimd_last_state, st);
st->cpu = smp_processor_id();
}
preempt_enable();
}
if fpsimd_load_state() is interrupted and the NEON is used, the
registers that were restored before the interruption will have
incorrect values if SVE is being used by userland.
On the preserve side, we can deal with this by preserving into a temp
buffer, and only store the value that was recorded when the flag was
set, i.e.,
static void safe_preserve_fpsimd_state(void)
{
union __fpsimd_percpu_state *s = this_cpu_ptr(nested_fpsimdstate);
if (in_irq()) {
/* No interruptions possible, so just proceed */
if (!test_and_set_thread_flag(TIF_FOREIGN_FPSTATE))
fpsimd_save_state(¤t->thread.fpsimd_state);
} else {
struct fpsimd_state *fp;
fp = in_interrupt() ? &s[0].full : &s[1].full;
fpsimd_save_state(fp);
if (!test_and_set_thread_flag(TIF_FOREIGN_FPSTATE))
current->thread.fpsimd_state = *fp;
}
}
which is already cumbersome if the full FP/SIMD state grows to 64 KB
However, on the restore side, I fail to see how we can tolerate
interruptions in a similar way.
--
Ard.
^ permalink raw reply
* [PATCH] ARM: dts: Add missing CPU frequencies for Exynos5422/5800
From: Javier Martinez Canillas @ 2016-12-13 19:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5220084.l31t5oJbsy@amdc3058>
Hello Bartlomiej,
On 12/13/2016 01:52 PM, Bartlomiej Zolnierkiewicz wrote:
> Add missing 2000MHz & 1900MHz OPPs (for A15 cores) and 1400MHz OPP
> (for A7 cores). Also update common Odroid-XU3 Lite/XU3/XU4 thermal
> cooling maps to account for new OPPs.
>
> Since new OPPs are not available on all Exynos5422/5800 boards modify
> dts files for Odroid-XU3 Lite (limited to 1.8 GHz / 1.3 GHz) & Peach
> Pi (limited to 2.0 GHz / 1.3 GHz) accordingly.
>
> Tested on Odroid-XU3 and XU3 Lite.
>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> Cc: Andreas Faerber <afaerber@suse.de>
> Cc: Thomas Abraham <thomas.ab@samsung.com>
> Cc: Ben Gamari <ben@smart-cactus.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 14 +++++++-------
> arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 17 +++++++++++++++++
> arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++++
> arch/arm/boot/dts/exynos5800.dtsi | 15 +++++++++++++++
> 4 files changed, 43 insertions(+), 7 deletions(-)
>
> Index: b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
> ===================================================================
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 2016-12-13 15:59:33.779763261 +0100
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 2016-12-13 15:59:33.775763261 +0100
> @@ -118,7 +118,7 @@
> /*
> * When reaching cpu_alert3, reduce CPU
> * by 2 steps. On Exynos5422/5800 that would
> - * be: 1600 MHz and 1100 MHz.
> + * (usually) be: 1800 MHz and 1200 MHz.
> */
> map3 {
> trip = <&cpu_alert3>;
> @@ -131,16 +131,16 @@
>
> /*
> * When reaching cpu_alert4, reduce CPU
> - * further, down to 600 MHz (11 steps for big,
> - * 7 steps for LITTLE).
> + * further, down to 600 MHz (13 steps for big,
> + * 8 steps for LITTLE).
> */
> - map5 {
> + cooling_map5: map5 {
> trip = <&cpu_alert4>;
> - cooling-device = <&cpu0 3 7>;
> + cooling-device = <&cpu0 3 8>;
> };
> - map6 {
> + cooling_map6: map6 {
> trip = <&cpu_alert4>;
> - cooling-device = <&cpu4 3 11>;
> + cooling-device = <&cpu4 3 13>;
> };
> };
> };
> Index: b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
> ===================================================================
> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts 2016-12-13 15:59:33.779763261 +0100
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts 2016-12-13 15:59:33.775763261 +0100
> @@ -21,6 +21,23 @@
> compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5";
> };
>
> +&cluster_a15_opp_table {
> + /delete-node/opp at 2000000000;
> + /delete-node/opp at 1900000000;
> +};
> +
> +&cluster_a7_opp_table {
> + /delete-node/opp at 1400000000;
> +};
> +
I think that a comment in the DTS why these operating points aren't available
in this board will make more clear why the nodes are being deleted.
> +&cooling_map5 {
> + cooling-device = <&cpu0 3 7>;
> +};
> +
> +&cooling_map6 {
> + cooling-device = <&cpu4 3 11>;
> +};
> +
> &pwm {
> /*
> * PWM 0 -- fan
> Index: b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> ===================================================================
> --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts 2016-12-13 15:59:33.779763261 +0100
> +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts 2016-12-13 15:59:33.779763261 +0100
> @@ -146,6 +146,10 @@
> vdd-supply = <&ldo9_reg>;
> };
>
> +&cluster_a7_opp_table {
> + /delete-property/opp at 1400000000;
> +};
> +
> &cpu0 {
> cpu-supply = <&buck2_reg>;
> };
> Index: b/arch/arm/boot/dts/exynos5800.dtsi
> ===================================================================
> --- a/arch/arm/boot/dts/exynos5800.dtsi 2016-12-13 15:59:33.779763261 +0100
> +++ b/arch/arm/boot/dts/exynos5800.dtsi 2016-12-13 15:59:33.779763261 +0100
> @@ -24,6 +24,16 @@
> };
>
> &cluster_a15_opp_table {
> + opp at 2000000000 {
> + opp-hz = /bits/ 64 <2000000000>;
> + opp-microvolt = <1250000>;
> + clock-latency-ns = <140000>;
> + };
> + opp at 1900000000 {
> + opp-hz = /bits/ 64 <1900000000>;
> + opp-microvolt = <1250000>;
> + clock-latency-ns = <140000>;
> + };
> opp at 1700000000 {
> opp-microvolt = <1250000>;
> };
> @@ -85,6 +95,11 @@
> };
>
AFAIK Thomas restricted the maximum OPP, because for A15 freqs > 1.8GHz the
INT rail would need to be scaled up as well since there's a maximum voltage
difference between the ARM and INT rails before the system becomes unstable:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/276766.html
https://lkml.org/lkml/2014/5/2/419
The ChromiumOS vendor tree uses a virtual regulator driver that makes sure
the maximum voltage skew is between a limit. But that never made to mainline:
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.8/arch/arm/boot/dts/exynos5420-peach-pit.dtsi#90
https://lkml.org/lkml/2014/4/29/28
Did that change and there's infrastructure in mainline now to cope with that?
If that's the case, I think it would be good to mention in the commit message.
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* [PATCH v6] arm64: fpsimd: improve stacking logic in non-interruptible context
From: Ard Biesheuvel @ 2016-12-13 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu9+Rcuc3Ubbom_NrYW5sR5B9teSfhM1+zi2JKhj4GUXWQ@mail.gmail.com>
On 13 December 2016 at 19:17, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> On 13 December 2016 at 17:34, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> On Tue, Dec 13, 2016 at 12:35:29PM +0000, Ard Biesheuvel wrote:
>>> Currently, we allow kernel mode NEON in softirq or hardirq context by
>>> stacking and unstacking a slice of the NEON register file for each call
>>> to kernel_neon_begin() and kernel_neon_end(), respectively.
>>>
>>> Given that
>>> a) a CPU typically spends most of its time in userland, during which time
>>> no kernel mode NEON in process context is in progress,
>>> b) a CPU spends most of its time in the kernel doing other things than
>>> kernel mode NEON when it gets interrupted to perform kernel mode NEON
>>> in softirq context
>>>
>>> the stacking and subsequent unstacking is only necessary if we are
>>> interrupting a thread while it is performing kernel mode NEON in process
>>> context, which means that in all other cases, we can simply preserve the
>>> userland FPSIMD state once, and only restore it upon return to userland,
>>> even if we are being invoked from softirq or hardirq context.
>>>
>>> So instead of checking whether we are running in interrupt context, keep
>>> track of the level of nested kernel mode NEON calls in progress, and only
>>> perform the eager stack/unstack if the level exceeds 1.
>>>
>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>> ---
>>> v6:
>>> - use a spinlock instead of disabling interrupts
>>
>> My concern with the spinlock or disabling interrupts is the latency if
>> we ever get some insanely long SVE vectors.
>>
>
> Thinking about this a bit more, and trying a couple of things in code,
> I think this looks like it could be a nasty problem.
>
> The primary issue is that *any* code that handles the FP/SIMD state,
> i.e., preserve it, restore it, etc, could be interrupted, and if
> kernel_neon_begin()/_end() was used during that time, the top SVE end
> of the registers is just blown away if we don't make the nested
> save/restore SVE aware.
>
> For instance, looking at
>
> void fpsimd_restore_current_state(void)
> {
> preempt_disable();
> if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
> struct fpsimd_state *st = ¤t->thread.fpsimd_state;
>
> fpsimd_load_state(st);
> this_cpu_write(fpsimd_last_state, st);
> st->cpu = smp_processor_id();
> }
> preempt_enable();
> }
>
> if fpsimd_load_state() is interrupted and the NEON is used, the
> registers that were restored before the interruption will have
> incorrect values if SVE is being used by userland.
>
> On the preserve side, we can deal with this by preserving into a temp
> buffer, and only store the value that was recorded when the flag was
> set, i.e.,
>
> static void safe_preserve_fpsimd_state(void)
> {
> union __fpsimd_percpu_state *s = this_cpu_ptr(nested_fpsimdstate);
>
> if (in_irq()) {
> /* No interruptions possible, so just proceed */
> if (!test_and_set_thread_flag(TIF_FOREIGN_FPSTATE))
> fpsimd_save_state(¤t->thread.fpsimd_state);
The indentation is slightly off here: the 'else' treats the !in_irq() case
> } else {
> struct fpsimd_state *fp;
>
> fp = in_interrupt() ? &s[0].full : &s[1].full;
>
> fpsimd_save_state(fp);
> if (!test_and_set_thread_flag(TIF_FOREIGN_FPSTATE))
> current->thread.fpsimd_state = *fp;
> }
> }
>
> which is already cumbersome if the full FP/SIMD state grows to 64 KB
>
> However, on the restore side, I fail to see how we can tolerate
> interruptions in a similar way.
>
> --
> Ard.
^ permalink raw reply
* [GIT PULL] arm64 updates for 4.10
From: Catalin Marinas @ 2016-12-13 19:21 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
Please pull the arm64 updates for 4.10 below.
The patches touch the generic include/linux/thread_info.h to factor out
struct restart_block into a separate include/linux/restart_block.h file
(needed for arm64 moving thread_info off stack; acked by Andy
Lutomirski).
There is also a small refactoring touching drivers/irqchip/irq-gic-v3.c
and additional watchpoint lengths added to
include/uapi/linux/hw_breakpoint.h.
Thanks.
The following changes since commit bc33b0ca11e3df467777a4fa7639ba488c9d4911:
Linux 4.9-rc4 (2016-11-05 16:23:36 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-upstream
for you to fetch changes up to 75037120e62b58c536999eb23d70cfcb6d6c0bcc:
arm64: Disable PAN on uaccess_enable() (2016-12-12 17:52:27 +0000)
----------------------------------------------------------------
arm64 updates for 4.10:
- struct thread_info moved off-stack (also touching
include/linux/thread_info.h and include/linux/restart_block.h)
- cpus_have_cap() reworked to avoid __builtin_constant_p() for static
key use (also touching drivers/irqchip/irq-gic-v3.c)
- Uprobes support (currently only for native 64-bit tasks)
- Emulation of kernel Privileged Access Never (PAN) using TTBR0_EL1
switching to a reserved page table
- CPU capacity information passing via DT or sysfs (used by the
scheduler)
- Support for systems without FP/SIMD (IOW, kernel avoids touching these
registers; there is no soft-float ABI, nor kernel emulation for
AArch64 FP/SIMD)
- Handling of hardware watchpoint with unaligned addresses, varied
lengths and offsets from base
- Use of the page table contiguous hint for kernel mappings
- Hugetlb fixes for sizes involving the contiguous hint
- Remove unnecessary I-cache invalidation in flush_cache_range()
- CNTHCTL_EL2 access fix for CPUs with VHE support (ARMv8.1)
- Boot-time checks for writable+executable kernel mappings
- Simplify asm/opcodes.h and avoid including the 32-bit ARM counterpart
and make the arm64 kernel headers self-consistent (Xen headers patch
merged separately)
- Workaround for broken .inst support in certain binutils versions
----------------------------------------------------------------
Ard Biesheuvel (3):
arm64: mm: BUG on unsupported manipulations of live kernel mappings
arm64: mm: replace 'block_mappings_allowed' with 'page_mappings_only'
arm64: mm: set the contiguous bit for kernel mappings where appropriate
Catalin Marinas (12):
arm64: Fix typo in add_default_hugepagesz() for 64K pages
arm64: Update the synchronous external abort fault description
arm64: Factor out PAN enabling/disabling into separate uaccess_* macros
arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro
arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1
arm64: Disable TTBR0_EL1 during normal kernel execution
arm64: Handle faults caused by inadvertent user access with PAN enabled
arm64: xen: Enable user access before a privcmd hvc call
arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN
arm64: Enable HIBERNATION in defconfig
arm64: Remove I-cache invalidation from flush_cache_range()
Merge Will Deacon's for-next/perf branch into for-next/core
Huang Shijie (2):
arm64: hugetlb: remove the wrong pmd check in find_num_contig()
arm64: hugetlb: fix the wrong address for several functions
Jintack (1):
arm64: head.S: Fix CNTHCTL_EL2 access on VHE system
Juri Lelli (3):
Documentation: arm: define DT cpu capacity-dmips-mhz bindings
arm64: parse cpu capacity-dmips-mhz from DT
arm64: add sysfs cpu_capacity attribute
Laura Abbott (4):
arm64: dump: Make ptdump debugfs a separate option
arm64: dump: Make the page table dumping seq_file optional
arm64: dump: Remove max_addr
arm64: dump: Add checking for writable and exectuable pages
Marc Zyngier (5):
arm64: Get rid of asm/opcodes.h
arm64: Remove reference to asm/opcodes.h
arm64: Add detection code for broken .inst support in binutils
arm64: Work around broken .inst when defective gas is detected
arm64: Disable PAN on uaccess_enable()
Mark Rutland (14):
arm64: percpu: kill off final ACCESS_ONCE() uses
thread_info: factor out restart_block
thread_info: include <current.h> for THREAD_INFO_IN_TASK
arm64: thread_info remove stale items
arm64: asm-offsets: remove unused definitions
arm64: factor out current_stack_pointer
arm64: traps: simplify die() and __die()
arm64: unexport walk_stackframe
arm64: prep stack walkers for THREAD_INFO_IN_TASK
arm64: move sp_el0 and tpidr_el1 into cpu_suspend_ctx
arm64: smp: prepare for smp_processor_id() rework
arm64: make cpu number a percpu variable
arm64: assembler: introduce ldr_this_cpu
arm64: split thread_info from task stack
Pavel Labath (1):
arm64: hw_breakpoint: Handle inexact watchpoint addresses
Pratyush Anand (11):
arm64: kprobe: protect/rename few definitions to be reused by uprobe
arm64: kgdb_step_brk_fn: ignore other's exception
arm64: Handle TRAP_TRACE for user mode as well
arm64: Handle TRAP_BRKPT for user mode as well
arm64: introduce mm context flag to keep 32 bit task information
arm64: Add uprobe support
arm64: fix error: conflicting types for 'kprobe_fault_handler'
hw_breakpoint: Allow watchpoint of length 3,5,6 and 7
arm64: Allow hw watchpoint at varied offset from base address
arm64: Allow hw watchpoint of length 3,5,6 and 7
selftests: arm64: add test for unaligned/inexact watchpoint handling
Robin Murphy (3):
arm64/kprobes: Tidy up sign-extension usage
arm64: Remove pointless WARN_ON in DMA teardown
arm64: smp: Prevent raw_smp_processor_id() recursion
Suzuki K Poulose (2):
arm64: Add hypervisor safe helper for checking constant capabilities
arm64: Support systems without FP/ASIMD
.../devicetree/bindings/arm/cpu-capacity.txt | 236 +++++++++++++++++++++
Documentation/devicetree/bindings/arm/cpus.txt | 10 +
arch/arm64/Kconfig | 12 ++
arch/arm64/Kconfig.debug | 35 ++-
arch/arm64/Makefile | 10 +-
arch/arm64/configs/defconfig | 1 +
arch/arm64/include/asm/Kbuild | 1 -
arch/arm64/include/asm/assembler.h | 48 ++++-
arch/arm64/include/asm/cacheflush.h | 7 +-
arch/arm64/include/asm/cpufeature.h | 37 +++-
arch/arm64/include/asm/current.h | 22 ++
arch/arm64/include/asm/debug-monitors.h | 3 +
arch/arm64/include/asm/efi.h | 26 ++-
arch/arm64/include/asm/elf.h | 12 +-
arch/arm64/include/asm/futex.h | 17 +-
arch/arm64/include/asm/hw_breakpoint.h | 6 +-
arch/arm64/include/asm/kernel-pgtable.h | 7 +
arch/arm64/include/asm/mmu.h | 3 +-
arch/arm64/include/asm/mmu_context.h | 53 +++--
arch/arm64/include/asm/neon.h | 3 +-
arch/arm64/include/asm/opcodes.h | 5 -
arch/arm64/include/asm/percpu.h | 18 +-
arch/arm64/include/asm/perf_event.h | 2 +
arch/arm64/include/asm/probes.h | 21 +-
arch/arm64/include/asm/ptdump.h | 22 +-
arch/arm64/include/asm/ptrace.h | 8 +
arch/arm64/include/asm/smp.h | 14 +-
arch/arm64/include/asm/stack_pointer.h | 9 +
arch/arm64/include/asm/suspend.h | 2 +-
arch/arm64/include/asm/sysreg.h | 45 +++-
arch/arm64/include/asm/thread_info.h | 40 +---
arch/arm64/include/asm/uaccess.h | 175 ++++++++++++++-
arch/arm64/include/asm/uprobes.h | 36 ++++
arch/arm64/kernel/armv8_deprecated.c | 16 +-
arch/arm64/kernel/asm-offsets.c | 13 +-
arch/arm64/kernel/cpufeature.c | 18 +-
arch/arm64/kernel/debug-monitors.c | 40 ++--
arch/arm64/kernel/efi.c | 8 +-
arch/arm64/kernel/entry.S | 110 +++++++---
arch/arm64/kernel/fpsimd.c | 14 ++
arch/arm64/kernel/head.S | 30 ++-
arch/arm64/kernel/hw_breakpoint.c | 153 +++++++++----
arch/arm64/kernel/insn.c | 1 -
arch/arm64/kernel/kgdb.c | 3 +
arch/arm64/kernel/probes/Makefile | 2 +
arch/arm64/kernel/probes/decode-insn.c | 33 +--
arch/arm64/kernel/probes/decode-insn.h | 8 +-
arch/arm64/kernel/probes/kprobes.c | 36 ++--
arch/arm64/kernel/probes/simulate-insn.c | 16 +-
arch/arm64/kernel/probes/uprobes.c | 216 +++++++++++++++++++
arch/arm64/kernel/process.c | 38 +++-
arch/arm64/kernel/ptrace.c | 7 +-
arch/arm64/kernel/return_address.c | 1 +
arch/arm64/kernel/setup.c | 9 +
arch/arm64/kernel/signal.c | 3 +
arch/arm64/kernel/sleep.S | 3 -
arch/arm64/kernel/smp.c | 14 +-
arch/arm64/kernel/stacktrace.c | 7 +-
arch/arm64/kernel/suspend.c | 6 -
arch/arm64/kernel/topology.c | 223 ++++++++++++++++++-
arch/arm64/kernel/traps.c | 28 ++-
arch/arm64/kernel/vmlinux.lds.S | 5 +
arch/arm64/kvm/handle_exit.c | 11 +
arch/arm64/kvm/hyp/hyp-entry.S | 9 +-
arch/arm64/kvm/hyp/switch.c | 5 +-
arch/arm64/lib/clear_user.S | 11 +-
arch/arm64/lib/copy_from_user.S | 11 +-
arch/arm64/lib/copy_in_user.S | 11 +-
arch/arm64/lib/copy_to_user.S | 11 +-
arch/arm64/mm/Makefile | 3 +-
arch/arm64/mm/cache.S | 6 +-
arch/arm64/mm/context.c | 7 +-
arch/arm64/mm/dma-mapping.c | 5 -
arch/arm64/mm/dump.c | 106 ++++++---
arch/arm64/mm/fault.c | 22 +-
arch/arm64/mm/flush.c | 9 +-
arch/arm64/mm/hugetlbpage.c | 22 +-
arch/arm64/mm/mmu.c | 137 ++++++++----
arch/arm64/mm/proc.S | 12 +-
arch/arm64/mm/ptdump_debugfs.c | 31 +++
arch/arm64/xen/hypercall.S | 15 ++
drivers/firmware/efi/arm-runtime.c | 4 +-
drivers/irqchip/irq-gic-v3.c | 13 +-
include/linux/restart_block.h | 51 +++++
include/linux/thread_info.h | 45 +---
include/uapi/linux/hw_breakpoint.h | 4 +
tools/include/uapi/linux/hw_breakpoint.h | 4 +
tools/testing/selftests/breakpoints/Makefile | 5 +-
.../selftests/breakpoints/breakpoint_test_arm64.c | 236 +++++++++++++++++++++
89 files changed, 2288 insertions(+), 525 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/cpu-capacity.txt
create mode 100644 arch/arm64/include/asm/current.h
delete mode 100644 arch/arm64/include/asm/opcodes.h
create mode 100644 arch/arm64/include/asm/stack_pointer.h
create mode 100644 arch/arm64/include/asm/uprobes.h
create mode 100644 arch/arm64/kernel/probes/uprobes.c
create mode 100644 arch/arm64/mm/ptdump_debugfs.c
create mode 100644 include/linux/restart_block.h
create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c
--
Catalin
^ permalink raw reply
* [PATCH] Input: imx6ul_tsc - generalize the averaging property
From: Rob Herring @ 2016-12-13 19:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1CDAF0C6-25E1-4CE9-8F98-F07333827B98@gmail.com>
On Tue, Dec 13, 2016 at 1:14 PM, Dmitry Torokhov
<dmitry.torokhov@gmail.com> wrote:
> On December 13, 2016 11:10:50 AM PST, Rob Herring <robh@kernel.org> wrote:
>>On Sun, Dec 11, 2016 at 09:06:43AM +0200, Guy Shapiro wrote:
>>> Make the avarage-samples property a general touchscreen property
>>> rather than imx6ul device specific.
>>>
>>> Signed-off-by: Guy Shapiro <guy.shapiro@mobi-wize.com>
>>> ---
>>> .../bindings/input/touchscreen/imx6ul_tsc.txt | 11 ++----
>>> .../bindings/input/touchscreen/touchscreen.txt | 3 ++
>>> drivers/input/touchscreen/imx6ul_tsc.c | 46
>>++++++++++++++++------
>>> 3 files changed, 41 insertions(+), 19 deletions(-)
>>
>>You can't just switch existing bindings as that breaks compatibility
>>with old dtbs. The kernel driver would need to support both. Just
>>introduce the new common property and use it for your device.
>>
>
> The old binding is only in my tree at the moment, so I do not think there is compatibility concerns.
>
> Are you OK with the new binding itself?
Ah, then yes. For the binding:
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH] Input: imx6ul_tsc - generalize the averaging property
From: Rob Herring @ 2016-12-13 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481440003-27168-1-git-send-email-guy.shapiro@mobi-wize.com>
On Sun, Dec 11, 2016 at 1:06 AM, Guy Shapiro <guy.shapiro@mobi-wize.com> wrote:
> Make the avarage-samples property a general touchscreen property
> rather than imx6ul device specific.
>
> Signed-off-by: Guy Shapiro <guy.shapiro@mobi-wize.com>
> ---
> .../bindings/input/touchscreen/imx6ul_tsc.txt | 11 ++----
> .../bindings/input/touchscreen/touchscreen.txt | 3 ++
> drivers/input/touchscreen/imx6ul_tsc.c | 46 ++++++++++++++++------
> 3 files changed, 41 insertions(+), 19 deletions(-)
[...]
> + switch (average_samples) {
> + case 1:
> + tsc->average_enable = false;
> + tsc->average_select = 0; /* value unused; initialize anyway */
> + break;
> + case 4:
> + tsc->average_enable = true;
> + tsc->average_select = 0;
> + break;
> + case 8:
> + tsc->average_enable = true;
> + tsc->average_select = 1;
> + break;
> + case 16:
> + tsc->average_enable = true;
> + tsc->average_select = 2;
> + break;
> + case 32:
> + tsc->average_enable = true;
> + tsc->average_select = 3;
> + break;
This could be more efficiently written as
tsc->average_select = log2(average_samples) - 2;
Then enable if >=0.
Rob
^ permalink raw reply
* [PATCH v2 2/2] crypto: mediatek - add DT bindings documentation
From: Rob Herring @ 2016-12-13 20:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481592676-2248-3-git-send-email-ryder.lee@mediatek.com>
On Tue, Dec 13, 2016 at 09:31:16AM +0800, Ryder Lee wrote:
> Add DT bindings documentation for the crypto driver
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---
> .../devicetree/bindings/crypto/mediatek-crypto.txt | 32 ++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
>
> diff --git a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
> new file mode 100644
> index 0000000..47a786e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
> @@ -0,0 +1,32 @@
> +MediaTek cryptographic accelerators
> +
> +Required properties:
> +- compatible: Should be "mediatek,eip97-crypto"
> +- reg: Address and length of the register set for the device
> +- interrupts: Should contain the five crypto engines interrupts in numeric
> + order. These are global system and four descriptor rings.
> +- clocks: the clock used by the core
> +- clock-names: the names of the clock listed in the clocks property. These are
> + "ethif", "cryp"
> +- power-domains: Must contain a reference to the PM domain.
> +
> +
> +Optional properties:
> +- interrupt-parent: Should be the phandle for the interrupt controller
> + that services interrupts for this device
This is not optional. It's perhaps inherited from the parent. You can
drop it as it's implied by interrupts property.
Rob
^ permalink raw reply
* [PATCH 1/3] dt-bindings: arm: update Armada CP110 system controller binding
From: Rob Herring @ 2016-12-13 20:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481632880-9198-2-git-send-email-thomas.petazzoni@free-electrons.com>
On Tue, Dec 13, 2016 at 01:41:18PM +0100, Thomas Petazzoni wrote:
> It turns out that in the CP110 HW block present in Marvell Armada
> 7K/8K SoCs, gatable clock n?18 not only controls SD/MMC, but also the
> GOP block. This commit updates the Device Tree binding for this piece
> of hardware accordingly.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
> .../devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH 3/9] dt-bindings: stm32-dma: Fix typo regarding DMA client binding
From: Rob Herring @ 2016-12-13 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481636451-27863-4-git-send-email-cedric.madianga@gmail.com>
On Tue, Dec 13, 2016 at 02:40:45PM +0100, M'boumba Cedric Madianga wrote:
> Only four cells are required for dma client binding not five.
>
> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
> Reviewed-by: Ludovic BARRE <ludovic.barre@st.com>
> ---
> Documentation/devicetree/bindings/dma/stm32-dma.txt | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 0/4] ARM: Add support for CONFIG_DEBUG_VIRTUAL
From: Florian Fainelli @ 2016-12-13 20:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161209233628.6642-1-f.fainelli@gmail.com>
On 12/09/2016 03:36 PM, Florian Fainelli wrote:
> This patch series builds on top of Laura's [PATCHv5 00/10] CONFIG_DEBUG_VIRTUAL
> for arm64 to add support for CONFIG_DEBUG_VIRTUAL for ARM.
>
> This was tested on a Brahma B15 platform (ARMv7 + HIGHMEM + LPAE).
>
> Note that the treewide changes would involve a huge CC list, which
> is why it has been purposely trimmed to just focusing on the DEBUG_VIRTUAL
> aspect.
Any comments on this? How would you approach merging these patches?
Thank you!
>
> Changes in v3:
>
> - fix build failures reported by Kbuild test robot
>
> Changes in v2:
>
> - Modified MTD LART driver not to create symbol conflicts with
> KERNEL_START
> - Fixed patch that defines and uses KERNEL_START/END
> - Fixed __pa_symbol()'s definition
> - Inline __pa_symbol() check wihtin the VIRTUAL_BUG_ON statement
> - Simplified check for virtual addresses
> - Added a tree-wide patch changing SMP/PM implementations to use
> __pa_symbol(), build tested against multi_v{5,7}_defconfig
>
> Thanks!
>
> Florian Fainelli (4):
> mtd: lart: Rename partition defines to be prefixed with PART_
> ARM: Define KERNEL_START and KERNEL_END
> ARM: Add support for CONFIG_DEBUG_VIRTUAL
> ARM: treewide: Replace uses of virt_to_phys with __pa_symbol
>
> arch/arm/Kconfig | 1 +
> arch/arm/boot/compressed/piggy.xzkern | Bin 0 -> 2998584 bytes
> arch/arm/common/mcpm_entry.c | 12 +++----
> arch/arm/include/asm/memory.h | 23 ++++++++++++--
> arch/arm/mach-alpine/platsmp.c | 2 +-
> arch/arm/mach-axxia/platsmp.c | 2 +-
> arch/arm/mach-bcm/bcm63xx_smp.c | 2 +-
> arch/arm/mach-bcm/platsmp-brcmstb.c | 2 +-
> arch/arm/mach-bcm/platsmp.c | 4 +--
> arch/arm/mach-berlin/platsmp.c | 2 +-
> arch/arm/mach-exynos/firmware.c | 4 +--
> arch/arm/mach-exynos/mcpm-exynos.c | 2 +-
> arch/arm/mach-exynos/platsmp.c | 4 +--
> arch/arm/mach-exynos/pm.c | 6 ++--
> arch/arm/mach-exynos/suspend.c | 6 ++--
> arch/arm/mach-hisi/platmcpm.c | 2 +-
> arch/arm/mach-hisi/platsmp.c | 6 ++--
> arch/arm/mach-imx/platsmp.c | 2 +-
> arch/arm/mach-imx/pm-imx6.c | 2 +-
> arch/arm/mach-imx/src.c | 2 +-
> arch/arm/mach-mediatek/platsmp.c | 2 +-
> arch/arm/mach-mvebu/pm.c | 2 +-
> arch/arm/mach-mvebu/pmsu.c | 2 +-
> arch/arm/mach-mvebu/system-controller.c | 2 +-
> arch/arm/mach-omap2/control.c | 8 ++---
> arch/arm/mach-omap2/omap-mpuss-lowpower.c | 8 ++---
> arch/arm/mach-omap2/omap-smp.c | 4 +--
> arch/arm/mach-prima2/platsmp.c | 2 +-
> arch/arm/mach-prima2/pm.c | 2 +-
> arch/arm/mach-pxa/palmz72.c | 2 +-
> arch/arm/mach-pxa/pxa25x.c | 2 +-
> arch/arm/mach-pxa/pxa27x.c | 2 +-
> arch/arm/mach-pxa/pxa3xx.c | 2 +-
> arch/arm/mach-realview/platsmp-dt.c | 2 +-
> arch/arm/mach-rockchip/platsmp.c | 4 +--
> arch/arm/mach-rockchip/pm.c | 2 +-
> arch/arm/mach-s3c24xx/mach-jive.c | 2 +-
> arch/arm/mach-s3c24xx/pm-s3c2410.c | 2 +-
> arch/arm/mach-s3c24xx/pm-s3c2416.c | 2 +-
> arch/arm/mach-s3c64xx/pm.c | 2 +-
> arch/arm/mach-s5pv210/pm.c | 2 +-
> arch/arm/mach-sa1100/pm.c | 2 +-
> arch/arm/mach-shmobile/platsmp-apmu.c | 6 ++--
> arch/arm/mach-shmobile/platsmp-scu.c | 4 +--
> arch/arm/mach-socfpga/platsmp.c | 4 +--
> arch/arm/mach-spear/platsmp.c | 2 +-
> arch/arm/mach-sti/platsmp.c | 2 +-
> arch/arm/mach-sunxi/platsmp.c | 4 +--
> arch/arm/mach-tango/platsmp.c | 2 +-
> arch/arm/mach-tango/pm.c | 2 +-
> arch/arm/mach-tegra/reset.c | 4 +--
> arch/arm/mach-ux500/platsmp.c | 2 +-
> arch/arm/mach-vexpress/dcscb.c | 2 +-
> arch/arm/mach-vexpress/platsmp.c | 2 +-
> arch/arm/mach-vexpress/tc2_pm.c | 4 +--
> arch/arm/mach-zx/platsmp.c | 4 +--
> arch/arm/mach-zynq/platsmp.c | 2 +-
> arch/arm/mm/Makefile | 1 +
> arch/arm/mm/init.c | 7 ++--
> arch/arm/mm/mmu.c | 6 +---
> arch/arm/mm/physaddr.c | 51 ++++++++++++++++++++++++++++++
> drivers/mtd/devices/lart.c | 24 +++++++-------
> 62 files changed, 173 insertions(+), 108 deletions(-)
> create mode 100644 arch/arm/boot/compressed/piggy.xzkern
> create mode 100644 arch/arm/mm/physaddr.c
>
--
Florian
^ permalink raw reply
* [RFC v4 00/16] KVM PCIe/MSI passthrough on ARM/ARM64 and IOVA reserved regions
From: Eric Auger @ 2016-12-13 20:30 UTC (permalink / raw)
To: linux-arm-kernel
Following LPC discussions, we now report reserved regions through
iommu-group sysfs reserved_regions attribute file.
Reserved regions are populated through the IOMMU get_resv_region
callback (former get_dm_regions), now implemented by amd-iommu,
intel-iommu and arm-smmu:
- the amd-iommu reports device direct mapped regions.
- the intel-iommu reports the [0xfee00000 - 0xfeefffff] MSI window
as an IOMMU_RESV_NOMAP reserved region.
- the arm-smmu reports the MSI window (arbitrarily located at
0x8000000 and 1MB large).
Unsafe interrupt assignment is tested by enumerating all MSI irq
domains and checking they support MSI remapping. This check is done
in case we detect the iommu translates MSI (an IOMMU_RESV_MSI
window exists). Otherwise the IRQ remapping capability is checked
at IOMMU level. Obviously this is a defensive IRQ safety assessment.
Assuming there are several MSI controllers in the system and at
least one does not implement IRQ remapping, the assignment will be
considered as unsafe (even if this controller is not acessible from
the assigned devices).
The series integrates a not officially posted patch from Robin:
"iommu/dma: Allow MSI-only cookies".
Best Regards
Eric
Git: complete series available at
https://github.com/eauger/linux/tree/v4.9-reserved-v4
History:
RFCv3 -> RFCv4:
- arm-smmu driver does not register PCI host bridge windows as
reserved regions anymore
- Implement reserved region get/put callbacks also in arm-smmuv3
- take the iommu_group lock on iommu_get_group_resv_regions
- add a type field in iommu_resv_region instead of using prot
- init the region list_head in iommu_alloc_resv_region, also
add type parameter
- iommu_insert_resv_region manage overlaps and sort reserved
windows
- address IRQ safety assessment by enumerating all the MSI irq
domains and checking the MSI_REMAP flag
- update Documentation/ABI/testing/sysfs-kernel-iommu_groups
- Did not add T-b since the code has significantly changed
RFCv2 -> RFCv3:
- switch to an iommu-group sysfs API
- use new dummy allocator provided by Robin
- dummy allocator initialized by vfio-iommu-type1 after enumerating
the reserved regions
- at the moment ARM MSI base address/size is left unchanged compared
to v2
- we currently report reserved regions and not usable IOVA regions as
requested by Alex
RFC v1 -> v2:
- fix intel_add_reserved_regions
- add mutex lock/unlock in vfio_iommu_type1
Eric Auger (16):
iommu/dma: Allow MSI-only cookies
iommu: Rename iommu_dm_regions into iommu_resv_regions
iommu: Add a new type field in iommu_resv_region
iommu: iommu_alloc_resv_region
iommu: Only map direct mapped regions
iommu: iommu_get_group_resv_regions
iommu: Implement reserved_regions iommu-group sysfs file
iommu/vt-d: Implement reserved region get/put callbacks
iommu/arm-smmu: Implement reserved region get/put callbacks
iommu/arm-smmu-v3: Implement reserved region get/put callbacks
irqdomain: Add IRQ_DOMAIN_FLAG_MSI_REMAP value
irqdomain: irq_domain_check_msi_remap
irqchip/gicv3-its: Sets IRQ_DOMAIN_FLAG_MSI_REMAP
vfio/type1: Allow transparent MSI IOVA allocation
vfio/type1: Check MSI remapping at irq domain level
iommu/arm-smmu: Do not advertise IOMMU_CAP_INTR_REMAP anymore
.../ABI/testing/sysfs-kernel-iommu_groups | 9 ++
drivers/iommu/amd_iommu.c | 21 +--
drivers/iommu/arm-smmu-v3.c | 30 +++-
drivers/iommu/arm-smmu.c | 30 +++-
drivers/iommu/dma-iommu.c | 116 +++++++++++++---
drivers/iommu/intel-iommu.c | 50 +++++--
drivers/iommu/iommu.c | 152 +++++++++++++++++++--
drivers/irqchip/irq-gic-v3-its.c | 1 +
drivers/vfio/vfio_iommu_type1.c | 37 ++++-
include/linux/dma-iommu.h | 7 +
include/linux/iommu.h | 46 +++++--
include/linux/irqdomain.h | 8 ++
kernel/irq/irqdomain.c | 24 ++++
13 files changed, 455 insertions(+), 76 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH] i2c: designware: add reset interface
From: Wolfram Sang @ 2016-12-13 20:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479789700-19532-1-git-send-email-zhangfei.gao@linaro.org>
On Tue, Nov 22, 2016 at 12:41:40PM +0800, Zhangfei Gao wrote:
> Some platforms like hi3660 need do reset first to allow accessing registers
>
> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Adding designware maintainers to CC...
> ---
> drivers/i2c/busses/i2c-designware-core.h | 1 +
> drivers/i2c/busses/i2c-designware-platdrv.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
> index 0d44d2a..94b14fa 100644
> --- a/drivers/i2c/busses/i2c-designware-core.h
> +++ b/drivers/i2c/busses/i2c-designware-core.h
> @@ -80,6 +80,7 @@ struct dw_i2c_dev {
> void __iomem *base;
> struct completion cmd_complete;
> struct clk *clk;
> + struct reset_control *rst;
> u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
> struct dw_pci_controller *controller;
> int cmd_err;
> diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
> index 0b42a12..fd80e58 100644
> --- a/drivers/i2c/busses/i2c-designware-platdrv.c
> +++ b/drivers/i2c/busses/i2c-designware-platdrv.c
> @@ -38,6 +38,7 @@
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> #include <linux/io.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/acpi.h>
> #include <linux/platform_data/i2c-designware.h>
> @@ -176,6 +177,10 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
> dev->irq = irq;
> platform_set_drvdata(pdev, dev);
>
> + dev->rst = devm_reset_control_get(&pdev->dev, NULL);
> + if (!IS_ERR(dev->rst))
> + reset_control_reset(dev->rst);
> +
> /* fast mode by default because of legacy reasons */
> dev->clk_freq = 400000;
>
> --
> 2.7.4
>
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^ permalink raw reply
* [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33
From: Icenowy Zheng @ 2016-12-13 20:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213154451.y4wcrqhtcc5sqli7@lukather>
13.12.2016, 23:44, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote:
>> ?The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
>> ?be changeable by changing the rate of PLL_CPUX.
>>
>> ?Add CLK_SET_RATE_PARENT flag to this clock.
>>
>> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Excuse me, have you merged this patch?
If merged, I won't contain it in my PATCH v2, thus the PATCH v2 will contain
only an updated OPP patch.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply
* [PATCH v6 1/8] MFD: add bindings for STM32 Timers driver
From: Rob Herring @ 2016-12-13 21:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+M3ks4ukP14YE5-6+gAzJBjEmjEyGyVbsVGOm8ehVm0EfzO-w@mail.gmail.com>
On Tue, Dec 13, 2016 at 3:29 AM, Benjamin Gaignard
<benjamin.gaignard@linaro.org> wrote:
> 2016-12-12 19:51 GMT+01:00 Rob Herring <robh@kernel.org>:
>> On Fri, Dec 09, 2016 at 03:15:12PM +0100, Benjamin Gaignard wrote:
>>> Add bindings information for STM32 Timers
>>>
>>> version 6:
>>> - rename stm32-gtimer to stm32-timers
>>> - change compatible
>>> - add description about the IPs
>>>
>>> version 2:
>>> - rename stm32-mfd-timer to stm32-gptimer
>>> - only keep one compatible string
>>>
>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>>> ---
>>> .../devicetree/bindings/mfd/stm32-timers.txt | 46 ++++++++++++++++++++++
>>> 1 file changed, 46 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
>>> new file mode 100644
>>> index 0000000..b30868e
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
>>> @@ -0,0 +1,46 @@
>>> +STM32 Timers driver bindings
>>> +
>>> +This IP provides 3 types of timer along with PWM functionality:
>>> +- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable
>>> + prescaler, break input feature, PWM outputs and complementary PWM ouputs channels.
>>> +- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a
>>> + programmable prescaler and PWM outputs.
>>> +- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
>>> +
>>> +Required parameters:
>>> +- compatible: must be "st,stm32-timers"
>>> +
>>> +- reg: Physical base address and length of the controller's
>>> + registers.
>>> +- clock-names: Set to "clk_int".
>>
>> 'clk' is redundant. Also, you don't really need -names when there is
>> only one of them.
>
> I use devm_regmap_init_mmio_clk() which get the clock by it name so
> I have to define it in DT.
Are you sure NULL is not allowed? I don't know, but at least clk_get()
allows NULL.
It's fine to keep, just drop the "clk_" part.
>
>>> +- clocks: Phandle to the clock used by the timer module.
>>> + For Clk properties, please refer to ../clock/clock-bindings.txt
>>> +
>>> +Optional parameters:
>>> +- resets: Phandle to the parent reset controller.
>>> + See ../reset/st,stm32-rcc.txt
>>> +
>>> +Optional subnodes:
>>> +- pwm: See ../pwm/pwm-stm32.txt
>>> +- timer: See ../iio/timer/stm32-timer-trigger.txt
>>> +
>>> +Example:
>>> + timers at 40010000 {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + compatible = "st,stm32-timers";
>>> + reg = <0x40010000 0x400>;
>>> + clocks = <&rcc 0 160>;
>>> + clock-names = "clk_int";
>>> +
>>> + pwm {
>>> + compatible = "st,stm32-pwm";
>>> + pinctrl-0 = <&pwm1_pins>;
>>> + pinctrl-names = "default";
>>> + };
>>> +
>>> + timer {
>>> + compatible = "st,stm32-timer-trigger";
>>> + reg = <0>;
>>
>> You don't need reg here as there is only one. In turn, you don't need
>> #address-cells or #size-cells.
>
> I use "reg" to set each timer configuration.
> From hardware point of view they are all the same except for which hardware
> signals they could consume and/or send.
This sounds okay, but...
> "reg" is used as index of the two tables in driver code.
this statement doesn't really sound like valid use of reg.
If you keep reg, then the node needs a unit address (timer at 0).
Rob
^ permalink raw reply
* [PATCH 2/4] dt-bindings: mfd: Remove TPS65217 interrupts
From: Rob Herring @ 2016-12-13 21:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <fe4985c0-d60a-2562-12a7-064404efd64c@gmail.com>
On Mon, Dec 12, 2016 at 5:24 PM, Milo Kim <woogyom.kim@gmail.com> wrote:
> On 12/13/2016 02:25 AM, Rob Herring wrote:
>>
>> On Fri, Dec 09, 2016 at 03:28:31PM +0900, Milo Kim wrote:
>>>
>>> Interrupt numbers are from the datasheet, so no need to keep them in
>>> the ABI. Use the number in the DT file.
>>
>> I don't see the purpose of ripping this out. The headers have always
>> been for convienence, not whether the values come from the datasheet or
>> not.
>
>
> My understanding is it's a same rule as other interrupt controllers.
Oh yes, that's true. We never use defines for interrupts. In that case:
Acked-by: Rob Herring <robh@kernel.org>
Rob
^ permalink raw reply
* [PATCH 5/5] Documentation: fsl-quadspi: Add fsl, ls1012a-qspi compatible string
From: Rob Herring @ 2016-12-13 21:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR0402MB2902DADEB4E6D06418AD311F899B0@DB6PR0402MB2902.eurprd04.prod.outlook.com>
On Mon, Dec 12, 2016 at 8:47 PM, Yao Yuan <yao.yuan@nxp.com> wrote:
> On Thu, Dec 13, 2016 at 05:23:02PM +0800, Rob Herring wrote:
>> On Thu, Dec 08, 2016 at 05:23:04PM +0800, Yuan Yao wrote:
>> > From: Yuan Yao <yao.yuan@nxp.com>
>>
>> Same problem in this subject too.
>>
>> >
>> > new compatible string: "fsl,ls1012a-qspi".
>> >
>> > Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
>> > ---
>> > Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
>> > 1 file changed, 1 insertion(+)
>>
>> Acked-by: Rob Herring <robh@kernel.org>
>
> Thanks for your review.
> And do you have any suggestion for this subject?
The problem is you have a space in the compatible string: "fsl,
ls1012a-qspi" rather than "fsl,ls1012a-qspi"
Also, I prefer "dt/bindings: " as the beginning of binding patch subjects.
Rob
^ permalink raw reply
* [PATCH v3] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller
From: Jon Masters @ 2016-12-13 21:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206201835.GA19700@bhelgaas-glaptop.roam.corp.google.com>
On 12/06/2016 03:18 PM, Bjorn Helgaas wrote:
> I just merged pci/ecam into my "next" branch, so as long as tomorrow's
> linux-next boots out of the box, we should be set. I made the following
> changes compared to v11:
>
> - dropped the x86 change to use acpi_resource_consumer()
> - added parens around macro args used in arithmetic expressions
> - renamed "seg" to "node" in THUNDER_PEM_RES and THUNDER_PEM_QUIRK
> - incorporated (u64) cast and dropped "UL" postfix for THUNDER_PEM_QUIRK
>
> Let me know if you see any issues.
Just following up. Please find attached a boot log from an HPE ProLiant m400
Moonshot X-Gene based cartridge running next-20161213 with pci/ecam branch.
Here is the /proc/iomem output as well:
# cat /proc/iomem
10520000-10523fff : APMC0D18:00
10520000-10523fff : APMC0D18:00
10524000-10527fff : APMC0D17:00
10540000-1054a0ff : APMC0D01:00
10546000-10546fff : APMC0D50:00
1054a000-1054a00f : APMC0D12:03
1054a000-1054a00f : APMC0D12:02
1054a000-1054a00f : APMC0D12:01
1054a000-1054a00f : APMC0D12:00
17000000-17000fff : APMC0D01:00
17001000-17001fff : APMC0D01:00
17001000-170013ff : APMC0D15:00
17001000-170013ff : APMC0D15:00
1701c000-1701cfff : APMC0D14:00
1a800000-1a800fff : APMC0D0D:00
1a800000-1a800fff : APMC0D0D:00
1c000200-1c0002ff : APMC0D06:00
1c021000-1c0210ff : APMC0D08:00
1c021000-1c02101f : serial
1c024000-1c024fff : APMC0D07:00
1f230000-1f230fff : APMC0D0D:00
1f230000-1f230fff : APMC0D0D:00
1f23d000-1f23dfff : APMC0D0D:00
1f23d000-1f23dfff : APMC0D0D:00
1f23e000-1f23efff : APMC0D0D:00
1f23e000-1f23efff : APMC0D0D:00
1f2a0000-1f31ffff : APMC0D06:00
1f500000-1f50ffff : PNP0A08:00
78800000-78800fff : APMC0D13:00
78800000-78800fff : APMC0D12:03
78800000-78800fff : APMC0D12:02
78800000-78800fff : APMC0D12:01
78800000-78800fff : APMC0D12:00
78800000-78800fff : APMC0D11:00
78800000-78800fff : APMC0D10:03
78800000-78800fff : APMC0D10:02
78800000-78800fff : APMC0D10:01
78800000-78800fff : APMC0D10:00
79000000-798fffff : APMC0D0E:00
7c000000-7c1fffff : APMC0D12:00
7c200000-7c3fffff : APMC0D12:01
7c400000-7c5fffff : APMC0D12:02
7c600000-7c7fffff : APMC0D12:03
7e000000-7e000fff : APMC0D13:00
7e200000-7e200fff : APMC0D10:03
7e200000-7e200fff : APMC0D10:02
7e200000-7e200fff : APMC0D10:01
7e200000-7e200fff : APMC0D10:00
7e600000-7e600fff : APMC0D11:00
7e700000-7e700fff : APMC0D10:03
7e700000-7e700fff : APMC0D10:02
7e700000-7e700fff : APMC0D10:01
7e700000-7e700fff : APMC0D10:00
7e720000-7e720fff : APMC0D10:03
7e720000-7e720fff : APMC0D10:02
7e720000-7e720fff : APMC0D10:01
7e720000-7e720fff : APMC0D10:00
7e800000-7e800fff : APMC0D10:00
7e840000-7e840fff : APMC0D10:01
7e880000-7e880fff : APMC0D10:02
7e8c0000-7e8c0fff : APMC0D10:03
7e930000-7e930fff : APMC0D13:00
4000000000-4001ffffff : System RAM
4000080000-4000c9ffff : Kernel code
4000e20000-400171ffff : Kernel data
40023a0000-4ff733ffff : System RAM
4ff7340000-4ff77cffff : reserved
4ff77d0000-4ff79cffff : System RAM
4ff79d0000-4ff7e7ffff : reserved
4ff7e80000-4ff7e8ffff : System RAM
4ff7e90000-4ff7efffff : reserved
4ff7f10000-4ff800ffff : reserved
4ff8010000-4fffffffff : System RAM
a020000000-a03fffffff : PCI Bus 0000:00
a020000000-a0201fffff : PCI Bus 0000:01
a020000000-a0200fffff : 0000:01:00.0
a020000000-a0200fffff : mlx4_core
a020100000-a0201fffff : 0000:01:00.0
a060000000-a07fffffff : PCI Bus 0000:00
a0d0000000-a0dfffffff : PCI ECAM
a110000000-a14fffffff : PCI Bus 0000:00
a110000000-a121ffffff : PCI Bus 0000:01
a110000000-a111ffffff : 0000:01:00.0
a110000000-a111ffffff : mlx4_core
a112000000-a121ffffff : 0000:01:00.0
Thanks again, Bjorn. Looking forward to seeing this upstream.
Tested-by: Jon Masters <jcm@redhat.com>
--
Computer Architect | Sent from my Fedora powered laptop
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[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.9.0-next-20161213.next20161213_jcm1 (root at hp-moonshot-02-c08.khw.lab.eng.bos.redhat.com) (gcc version 4.8.5 20150623 (Red Hat 4.8.5-11) (GCC) ) #1 SMP Tue Dec 13 15:42:15 EST 2016
[ 0.000000] Boot CPU: AArch64 Processor [500f0001]
[ 0.000000] earlycon: uart8250 at MMIO32 0x000000001c021000 (options '')
[ 0.000000] bootconsole [uart8250] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: EFI v2.60 by HPE
[ 0.000000] efi: ACPI 2.0=0x4ff8000000 SMBIOS 3.0=0x4ff7a90000 MEMATTR=0x4ff2410698 RNG=0x4ff7e7f518
[ 0.000000] cma: Reserved 512 MiB at 0x00000040e0000000
[ 0.000000] ACPI: Early table checksum verification disabled
[ 0.000000] ACPI: RSDP 0x0000004FF8000000 000024 (v02 HP )
[ 0.000000] ACPI: XSDT 0x0000004FF7FF0000 000084 (v01 HP ProLiant 00000001 01000013)
[ 0.000000] ACPI: FACP 0x0000004FF7FB0000 000114 (v06 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: DSDT 0x0000004FF7F80000 0023CA (v05 HPE DSDT 00000001 INTL 20160527)
[ 0.000000] ACPI: SSDT 0x0000004FF7FE0000 000032 (v02 HPE UARTCLKS 00000001 01000013)
[ 0.000000] ACPI: BERT 0x0000004FF7FD0000 000030 (v01 HPE ProLiant 00000002 INTL 20160527)
[ 0.000000] ACPI: HEST 0x0000004FF7FC0000 0002A8 (v01 HPE ProLiant 00000002 INTL 20160527)
[ 0.000000] ACPI: DBG2 0x0000004FF7FA0000 0000A8 (v00 HPE ProLiant 00000000 INTL 20160527)
[ 0.000000] ACPI: GTDT 0x0000004FF7F90000 0000E0 (v02 HPE ProLiant 00000001 INTL 20160527)
[ 0.000000] ACPI: APIC 0x0000004FF7F70000 0002C4 (v03 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: MCFG 0x0000004FF7F60000 00003C (v01 APM XGENE 00000001 HP 00000001)
[ 0.000000] ACPI: SPMI 0x0000004FF7F50000 000041 (v05 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: RASF 0x0000004FF7F40000 000030 (v01 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: SPCR 0x0000004FF7F30000 000050 (v02 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: SSDT 0x0000004FF7F20000 000313 (v02 HPE PCISSDT 00000002 HPAG 00020000)
[ 0.000000] ACPI: SPCR: console: uart,mmio,0x1c021000,9600
[ 0.000000] ACPI: NUMA: Failed to initialise from firmware
[ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x0000004fffffffff]
[ 0.000000] NUMA: Adding memblock [0x4000000000 - 0x4001ffffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x40023a0000 - 0x4ff733ffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff7340000 - 0x4ff77cffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff77d0000 - 0x4ff79cffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff79d0000 - 0x4ff7e7ffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff7e80000 - 0x4ff7e8ffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff7e90000 - 0x4ff7efffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff7f10000 - 0x4ff800ffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff8010000 - 0x4fffffffff] on node 0
[ 0.000000] NUMA: Initmem setup node 0 [mem 0x4000000000-0x4fffffffff]
[ 0.000000] NUMA: NODE_DATA [mem 0x4fffff2680-0x4fffffffff]
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000004000000000-0x00000040ffffffff]
[ 0.000000] Normal [mem 0x0000004100000000-0x0000004fffffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000004000000000-0x0000004001ffffff]
[ 0.000000] node 0: [mem 0x00000040023a0000-0x0000004ff733ffff]
[ 0.000000] node 0: [mem 0x0000004ff7340000-0x0000004ff77cffff]
[ 0.000000] node 0: [mem 0x0000004ff77d0000-0x0000004ff79cffff]
[ 0.000000] node 0: [mem 0x0000004ff79d0000-0x0000004ff7e7ffff]
[ 0.000000] node 0: [mem 0x0000004ff7e80000-0x0000004ff7e8ffff]
[ 0.000000] node 0: [mem 0x0000004ff7e90000-0x0000004ff7efffff]
[ 0.000000] node 0: [mem 0x0000004ff7f10000-0x0000004ff800ffff]
[ 0.000000] node 0: [mem 0x0000004ff8010000-0x0000004fffffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000004000000000-0x0000004fffffffff]
[ 0.000000] On node 0 totalpages: 1048517
[ 0.000000] DMA zone: 64 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 65478 pages, LIFO batch:1
[ 0.000000] Normal zone: 960 pages used for memmap
[ 0.000000] Normal zone: 983039 pages, LIFO batch:1
[ 0.000000] psci: is not implemented in ACPI.
[ 0.000000] percpu: Embedded 3 pages/cpu @fffffe0fffdd0000 s117248 r8192 d71168 u196608
[ 0.000000] pcpu-alloc: s117248 r8192 d71168 u196608 alloc=3*65536
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7
[ 0.000000] Detected PIPT I-cache on CPU0
[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 1047493
[ 0.000000] Policy zone: Normal
[ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-4.9.0-next-20161213.next20161213_jcm1 root=/dev/mapper/rhel_hp--moonshot--02--c08-root ro crashkernel=auto rd.lvm.lv=rhel_hp-moonshot-02-c08/root rd.lvm.lv=rhel_hp-moonshot-02-c08/swap LANG=en_US.UTF-8 acpi=on earlycon=uart8250,mmio32,0x1c021000 console=ttyS0,9600
[ 0.000000] PID hash table entries: 4096 (order: -1, 32768 bytes)
[ 0.000000] software IO TLB [mem 0x40dbff0000-0x40dfff0000] (64MB) mapped at [fffffe00dbff0000-fffffe00dffeffff]
[ 0.000000] Memory: 66377408K/67105088K available (8572K kernel code, 1626K rwdata, 3776K rodata, 1536K init, 7219K bss, 203392K reserved, 524288K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] modules : 0xfffffc0000000000 - 0xfffffc0008000000 ( 128 MB)
[ 0.000000] vmalloc : 0xfffffc0008000000 - 0xfffffdff5fff0000 ( 2045 GB)
[ 0.000000] .text : 0xfffffc0008080000 - 0xfffffc00088e0000 ( 8576 KB)
[ 0.000000] .rodata : 0xfffffc00088e0000 - 0xfffffc0008ca0000 ( 3840 KB)
[ 0.000000] .init : 0xfffffc0008ca0000 - 0xfffffc0008e20000 ( 1536 KB)
[ 0.000000] .data : 0xfffffc0008e20000 - 0xfffffc0008fb6a00 ( 1627 KB)
[ 0.000000] .bss : 0xfffffc0008fb6a00 - 0xfffffc00096c38d0 ( 7220 KB)
[ 0.000000] fixed : 0xfffffdff7e7d0000 - 0xfffffdff7ec00000 ( 4288 KB)
[ 0.000000] PCI I/O : 0xfffffdff7ee00000 - 0xfffffdff7fe00000 ( 16 MB)
[ 0.000000] vmemmap : 0xfffffdff80000000 - 0xfffffe0000000000 ( 2 GB maximum)
[ 0.000000] 0xfffffdff80000000 - 0xfffffdff84000000 ( 64 MB actual)
[ 0.000000] memory : 0xfffffe0000000000 - 0xfffffe1000000000 ( 65536 MB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 64.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4096 to nr_cpu_ids=8.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=8
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] arm_arch_timer: Architected cp15 timer(s) running at 50.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0xb8812736b, max_idle_ns: 440795202655 ns
[ 0.000002] sched_clock: 56 bits at 50MHz, resolution 20ns, wraps every 4398046511100ns
[ 0.095859] Console: colour dummy device 80x25
[ 0.149059] Calibrating delay loop (skipped), value calculated using timer frequency.. 100.00 BogoMIPS (lpj=50000)
[ 0.273029] pid_max: default: 32768 minimum: 301
[ 0.328350] ACPI: Core revision 20160930
[ 0.377378] ACPI: 3 ACPI AML tables successfully acquired and loaded
[ 0.453514] Security Framework initialized
[ 0.502501] Yama: becoming mindful.
[ 0.544208] SELinux: Initializing.
[ 0.586151] SELinux: Starting in permissive mode
[ 0.586902] Dentry cache hash table entries: 8388608 (order: 10, 67108864 bytes)
[ 0.686317] Inode-cache hash table entries: 4194304 (order: 9, 33554432 bytes)
[ 0.778042] Mount-cache hash table entries: 131072 (order: 4, 1048576 bytes)
[ 0.862396] Mountpoint-cache hash table entries: 131072 (order: 4, 1048576 bytes)
[ 0.952631] ftrace: allocating 31238 entries in 8 pages
[ 1.040528] ASID allocator initialised with 65536 entries
[ 1.105893] Remapping and enabling EFI services.
[ 1.161155] EFI remap 0x0000000010510000 => 0000000020000000
[ 1.230941] EFI remap 0x0000000010548000 => 0000000020018000
[ 1.300723] EFI remap 0x0000000017000000 => 0000000020020000
[ 1.370507] EFI remap 0x000000001c024000 => 0000000020034000
[ 1.440187] EFI remap 0x000000001f2a0000 => 0000000020040000
[ 1.509867] EFI remap 0x0000004002310000 => 0000000020050000
[ 1.579547] EFI remap 0x0000004ff7340000 => 00000000200b0000
[ 1.649331] EFI remap 0x0000004ff79d0000 => 0000000020540000
[ 1.719184] smp: Bringing up secondary CPUs ...
[ 1.773561] Detected PIPT I-cache on CPU1
[ 1.773591] CPU1: Booted secondary processor [500f0001]
[ 1.773810] Detected PIPT I-cache on CPU2
[ 1.773831] CPU2: Booted secondary processor [500f0001]
[ 1.774052] Detected PIPT I-cache on CPU3
[ 1.774065] CPU3: Booted secondary processor [500f0001]
[ 1.774263] Detected PIPT I-cache on CPU4
[ 1.774283] CPU4: Booted secondary processor [500f0001]
[ 1.774502] Detected PIPT I-cache on CPU5
[ 1.774516] CPU5: Booted secondary processor [500f0001]
[ 1.774715] Detected PIPT I-cache on CPU6
[ 1.774735] CPU6: Booted secondary processor [500f0001]
[ 1.774947] Detected PIPT I-cache on CPU7
[ 1.774960] CPU7: Booted secondary processor [500f0001]
[ 1.774998] smp: Brought up 1 node, 8 CPUs
[ 2.595763] SMP: Total of 8 processors activated.
[ 2.651925] CPU features: detected feature: 32-bit EL0 Support
[ 2.863045] CPU: All CPU(s) started at EL2
[ 2.912933] devtmpfs: initialized
[ 2.952981] SMBIOS 3.0.0 present.
[ 2.992611] DMI: HPE ProLiant m400 Server/ProLiant m400 Server, BIOS U02 06/25/2016
[ 3.084336] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
[ 3.201380] atomic64_test: passed
[ 3.241036] pinctrl core: initialized pinctrl subsystem
[ 3.303945] NET: Registered protocol family 16
[ 3.357675] cpuidle: using governor menu
[ 3.404583] PCCT header not found.
[ 3.445296] vdso: 2 pages (1 code @ fffffc0008900000, 1 data @ fffffc0008e40000)
[ 3.533818] hw-breakpoint: found 4 breakpoint and 4 watchpoint registers.
[ 3.615473] DMA: preallocated 256 KiB pool for atomic allocations
[ 3.688440] ACPI: bus type PCI registered
[ 3.736390] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[ 3.813544] Serial: AMBA PL011 UART driver
[ 3.865355] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 3.941388] HugeTLB registered 512 MB page size, pre-allocated 0 pages
[ 4.020035] ACPI: Added _OSI(Module Device)
[ 4.070067] ACPI: Added _OSI(Processor Device)
[ 4.123208] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 4.179473] ACPI: Added _OSI(Processor Aggregator Device)
[ 4.244129] ACPI: Executed 1 blocks of module-level executable AML code
[ 4.327259] ACPI: Interpreter enabled
[ 4.371051] ACPI: Using GIC for interrupt routing
[ 4.427339] ACPI: MCFG table detected, 1 entries
[ 4.485254] ACPI: Power Resource [SCVR] (off)
[ 4.540968] ACPI: PCI Root Bridge [PCI3] (domain 0000 [bus 00-ff])
[ 4.614943] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
[ 4.713012] acpi PNP0A08:00: _OSC: platform does not support [AER]
[ 4.787128] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME PCIeCapability]
[ 4.878780] acpi PNP0A08:00: MCFG quirk: ECAM at [mem 0xa0d0000000-0xa0dfffffff] for [bus 00-ff] with xgene_v1_pcie_ecam_ops
[ 5.013499] acpi PNP0A08:00: [Firmware Bug]: ECAM area [mem 0xa0d0000000-0xa0dfffffff] not reserved in ACPI namespace
[ 5.140522] acpi PNP0A08:00: ECAM at [mem 0xa0d0000000-0xa0dfffffff] for [bus 00-ff]
[ 5.233212] Remapped I/O 0x000000a100010000 to [io 0x0000-0xffff window]
[ 5.314538] PCI host bridge to bus 0000:00
[ 5.363532] pci_bus 0000:00: root bus resource [io 0x0000-0xffff window] (bus address [0x10000-0x1ffff])
[ 5.478041] pci_bus 0000:00: root bus resource [mem 0xa020000000-0xa03fffffff window] (bus address [0x20000000-0x3fffffff])
[ 5.611273] pci_bus 0000:00: root bus resource [mem 0xa060000000-0xa07fffffff window] (bus address [0x40000000-0x5fffffff])
[ 5.744502] pci_bus 0000:00: root bus resource [mem 0xa110000000-0xa14fffffff window]
[ 5.838210] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 5.903849] pci 0000:00:00.0: [10e8:e004] type 01 class 0x060400
[ 5.903922] pci 0000:00:00.0: supports D1 D2
[ 5.904276] pci 0000:01:00.0: [15b3:1007] type 00 class 0x020000
[ 5.904601] pci 0000:01:00.0: reg 0x10: [mem 0xa020000000-0xa0200fffff 64bit]
[ 5.904846] pci 0000:01:00.0: reg 0x18: [mem 0xa122000000-0xa123ffffff 64bit pref]
[ 5.905278] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x000fffff pref]
[ 5.907014] pci 0000:01:00.0: reg 0x134: [mem 0xa112000000-0xa113ffffff 64bit pref]
[ 5.907016] pci 0000:01:00.0: VF(n) BAR2 space: [mem 0xa112000000-0xa121ffffff 64bit pref] (contains BAR2 for 8 VFs)
[ 6.037078] pci_bus 0000:00: on NUMA node 0
[ 6.037098] pci 0000:00:00.0: BAR 15: assigned [mem 0xa110000000-0xa121ffffff 64bit pref]
[ 6.134970] pci 0000:00:00.0: BAR 14: assigned [mem 0xa020000000-0xa0201fffff]
[ 6.221401] pci 0000:01:00.0: BAR 2: assigned [mem 0xa110000000-0xa111ffffff 64bit pref]
[ 6.318379] pci 0000:01:00.0: BAR 9: assigned [mem 0xa112000000-0xa121ffffff 64bit pref]
[ 6.415273] pci 0000:01:00.0: BAR 0: assigned [mem 0xa020000000-0xa0200fffff 64bit]
[ 6.507043] pci 0000:01:00.0: BAR 6: assigned [mem 0xa020100000-0xa0201fffff pref]
[ 6.597633] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 6.657022] pci 0000:00:00.0: bridge window [mem 0xa020000000-0xa0201fffff]
[ 6.742414] pci 0000:00:00.0: bridge window [mem 0xa110000000-0xa121ffffff 64bit pref]
[ 6.839684] vgaarb: loaded
[ 6.872357] SCSI subsystem initialized
[ 6.917272] libata version 3.00 loaded.
[ 6.917319] ACPI: bus type USB registered
[ 6.965300] usbcore: registered new interface driver usbfs
[ 7.030944] usbcore: registered new interface driver hub
[ 7.094523] usbcore: registered new device driver usb
[ 7.154974] pps_core: LinuxPPS API ver. 1 registered
[ 7.214363] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 7.323672] PTP clock support registered
[ 7.370675] Registered efivars operations
[ 7.419358] NetLabel: Initializing
[ 7.460028] NetLabel: domain hash size = 128
[ 7.512133] NetLabel: protocols = UNLABELED CIPSOv4
[ 7.571547] NetLabel: unlabeled traffic allowed by default
[ 7.638361] clocksource: Switched to clocksource arch_sys_counter
[ 7.728243] VFS: Disk quotas dquot_6.6.0
[ 7.775223] VFS: Dquot-cache hash table entries: 8192 (order 0, 65536 bytes)
[ 7.859807] pnp: PnP ACPI init
[ 7.896705] pnp: PnP ACPI: found 0 devices
[ 8.091440] NET: Registered protocol family 2
[ 8.143915] TCP established hash table entries: 524288 (order: 6, 4194304 bytes)
[ 8.233776] TCP bind hash table entries: 65536 (order: 4, 1048576 bytes)
[ 8.314326] TCP: Hash tables configured (established 524288 bind 65536)
[ 8.393534] UDP hash table entries: 32768 (order: 4, 1048576 bytes)
[ 8.469053] UDP-Lite hash table entries: 32768 (order: 4, 1048576 bytes)
[ 8.549917] NET: Registered protocol family 1
[ 8.602063] PCI: CLS 64 bytes, default 128
[ 8.602177] Unpacking initramfs...
[ 9.396621] Freeing initrd memory: 35200K
[ 9.444989] kvm [1]: 8-bit VMID
[ 9.482540] kvm [1]: IDMAP page: 40008ce000
[ 9.532565] kvm [1]: HYP VA range: 20000000000:3ffffffffff
[ 9.598280] kvm [1]: Hyp mode initialized successfully
[ 9.659763] kvm [1]: GICV region size/alignment is unsafe, using trapping (reduced performance)
[ 9.763887] kvm [1]: vgic-v2 at 780cf000
[ 9.807757] kvm [1]: vgic interrupt IRQ1
[ 9.854665] kvm [1]: virtual timer IRQ4
[ 9.916744] futex hash table entries: 2048 (order: 2, 262144 bytes)
[ 9.991796] audit: initializing netlink subsys (disabled)
[ 10.056453] audit: type=2000 audit(6.770:1): initialized
[ 10.056630] Initialise system trusted keyrings
[ 10.056778] workingset: timestamp_bits=37 max_order=20 bucket_order=0
[ 10.059968] zbud: loaded
[ 10.061498] SELinux: Registering netfilter hooks
[ 10.135674] alg: acomp: Compression test 1 failed for lzo-scomp: output len = 27
[ 10.135777] alg: drbg: Test 0 failed for drbg_pr_ctr_aes128
[ 10.139874] alg: drbg: Test 0 failed for drbg_nopr_ctr_aes128
[ 10.139966] alg: drbg: Test 0 failed for drbg_nopr_ctr_aes192
[ 10.140039] alg: drbg: Test 0 failed for drbg_nopr_ctr_aes256
[ 10.141015] NET: Registered protocol family 38
[ 10.141020] Key type asymmetric registered
[ 10.141022] Asymmetric key parser 'x509' registered
[ 10.141066] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 248)
[ 10.141127] io scheduler noop registered
[ 10.141129] io scheduler deadline registered (default)
[ 10.141158] io scheduler cfq registered
[ 11.044288] xgene-gpio APMC0D14:00: X-Gene GPIO driver registered.
[ 11.118317] pcieport 0000:00:00.0: can't derive routing for PCI INT A
[ 11.195387] pcieport 0000:00:00.0: PCI INT A: no GSI
[ 11.254927] pcie_pme: probe of 0000:00:00.0:pcie001 failed with error -22
[ 11.336367] acpi ACPI0007:00: CPPC data invalid or not present
[ 11.406182] acpi ACPI0007:01: CPPC data invalid or not present
[ 11.475988] acpi ACPI0007:02: CPPC data invalid or not present
[ 11.545790] acpi ACPI0007:03: CPPC data invalid or not present
[ 11.615591] acpi ACPI0007:04: CPPC data invalid or not present
[ 11.685386] acpi ACPI0007:05: CPPC data invalid or not present
[ 11.755183] acpi ACPI0007:06: CPPC data invalid or not present
[ 11.824979] acpi ACPI0007:07: CPPC data invalid or not present
[ 11.895296] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
[ 11.985565] console [ttyS0] disabled
[ 12.048458] APMC0D08:00: ttyS0 at MMIO 0x1c021000 (irq = 23, base_baud = 3125000) is a U6_16550A
[ 12.153622] console [ttyS0] enabled
[ 12.237185] bootconsole [uart8250] disabled
[ 12.337600] msm_serial: driver initialized
[ 12.387004] cacheinfo: Unable to detect cache hierarchy for CPU 0
[ 12.460306] hisi_sas: driver version v1.6
[ 12.508614] xgene-ahci APMC0D0D:00: skip clock and PHY initialization
[ 12.585926] xgene-ahci APMC0D0D:00: controller can't do NCQ, turning off CAP_NCQ
[ 12.674726] xgene-ahci APMC0D0D:00: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl platform mode
[ 12.781242] xgene-ahci APMC0D0D:00: flags: 64bit sntf pm only pmp fbs pio slum part ccc
[ 12.878376] xgene-ahci APMC0D0D:00: port 0 is not capable of FBS
[ 12.950530] xgene-ahci APMC0D0D:00: port 1 is not capable of FBS
[ 13.023086] scsi host0: xgene-ahci
[ 13.064107] scsi host1: xgene-ahci
[ 13.104993] ata1: SATA max UDMA/133 mmio [mem 0x1a800000-0x1a800fff] port 0x100 irq 24
[ 13.200036] ata2: SATA max UDMA/133 mmio [mem 0x1a800000-0x1a800fff] port 0x180 irq 24
[ 13.295220] libphy: Fixed MDIO Bus: probed
[ 13.344622] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 13.423035] ehci-pci: EHCI PCI platform driver
[ 13.476382] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 13.550566] ohci-pci: OHCI PCI platform driver
[ 13.603485] ata2: SATA link down (SStatus 0 SControl 4300)
[ 13.669714] uhci_hcd: USB Universal Host Controller Interface driver
[ 13.746061] usbcore: registered new interface driver usbserial
[ 13.816074] usbcore: registered new interface driver usbserial_generic
[ 13.894431] usbserial: USB Serial support registered for generic
[ 13.918368] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 4300)
[ 13.918575] ata1.00: ATA-9: XR0120GEBLT, HPS4, max UDMA/133
[ 13.918577] ata1.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 0/32)
[ 13.918793] ata1.00: configured for UDMA/133
[ 13.919075] scsi 0:0:0:0: Direct-Access ATA XR0120GEBLT HPS4 PQ: 0 ANSI: 5
[ 14.337526] mousedev: PS/2 mouse device common for all mice
[ 14.337731] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 14.337813] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 14.337816] sd 0:0:0:0: [sda] 4096-byte physical blocks
[ 14.337844] sd 0:0:0:0: [sda] Write Protect is off
[ 14.337847] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 14.337878] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 14.340377] sda: sda1 sda2 sda3
[ 14.340976] sd 0:0:0:0: [sda] Attached SCSI disk
[ 14.882043] rtc-efi rtc-efi: rtc core: registered rtc-efi as rtc0
[ 14.955405] device-mapper: uevent: version 1.0.3
[ 15.010948] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel at redhat.com
[ 15.112879] EFI Variables Facility v0.08 2004-May-17
[ 15.173571] hidraw: raw HID events driver (C) Jiri Kosina
[ 15.238435] usbcore: registered new interface driver usbhid
[ 15.305312] usbhid: USB HID core driver
[ 15.351500] drop_monitor: Initializing network drop monitor service
[ 15.426836] ip_tables: (C) 2000-2006 Netfilter Core Team
[ 15.490607] Initializing XFRM netlink socket
[ 15.542068] NET: Registered protocol family 10
[ 15.595815] Segment Routing with IPv6
[ 15.639769] mip6: Mobile IPv6
[ 15.675345] NET: Registered protocol family 17
[ 15.728962] registered taskstats version 1
[ 15.778126] Loading compiled-in X.509 certificates
[ 15.838950] alg: No test for pkcs1pad(rsa,sha256) (pkcs1pad(rsa-generic,sha256))
[ 15.929166] Loaded X.509 cert 'Build time autogenerated kernel key: 1fab4053cdef4de1ccc5ce05e1cbfed5d5537af3'
[ 16.048260] zswap: loaded using pool lzo/zbud
[ 16.121521] Key type big_key registered
[ 16.167696] rtc-efi rtc-efi: setting system clock to 2016-12-13 21:36:35 UTC (1481664995)
[ 16.265895] PM: Hibernation image not present or could not be loaded.
[ 16.266097] Freeing unused kernel memory: 1536K
[ 16.326138] random: systemd: uninitialized urandom read (16 bytes read)
[ 16.406164] random: systemd: uninitialized urandom read (16 bytes read)
[ 16.487457] systemd[1]: systemd 219 running in system mode. (+PAM +AUDIT +SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID +ELFUTILS +KMOD +IDN)
[ 16.703839] systemd[1]: Detected architecture arm64.
[ 16.763425] systemd[1]: Running in initial RAM disk.
[ 16.933524] systemd[1]: Set hostname to <localhost.localdomain>.
[ 17.048780] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.128253] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.207713] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.287210] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.367813] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.447496] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.527253] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.607728] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.742418] systemd[1]: Created slice Root Slice.
[ 17.798887] systemd[1]: Starting Root Slice.
[ 17.906399] systemd[1]: Listening on udev Kernel Socket.
[ 17.970171] systemd[1]: Starting udev Kernel Socket.
[ 18.086397] systemd[1]: Listening on udev Control Socket.
[ 18.151212] systemd[1]: Starting udev Control Socket.
[ 19.673565] mlx4_core: Mellanox ConnectX core driver v2.2-1 (Feb, 2014)
[ 19.789919] mlx4_core: Initializing 0000:01:00.0
[ 26.231135] mlx4_core 0000:01:00.0: PCIe BW is different than device's capability
[ 26.320967] mlx4_core 0000:01:00.0: PCIe link speed is 5.0GT/s, device supports 8.0GT/s
[ 26.417049] mlx4_core 0000:01:00.0: PCIe link width is x8, device supports x8
[ 26.564318] mlx4_en: Mellanox ConnectX HCA Ethernet driver v2.2-1 (Feb 2014)
[ 26.649193] mlx4_en 0000:01:00.0: Activating port:1
[ 26.711378] mlx4_en: 0000:01:00.0: Port 1: Using 64 TX rings
[ 26.779299] mlx4_en: 0000:01:00.0: Port 1: Using 4 RX rings
[ 26.846181] mlx4_en: 0000:01:00.0: Port 1: frag:0 - size:1522 prefix:0 stride:1536
[ 26.939499] mlx4_en: 0000:01:00.0: Port 1: Initializing port
[ 27.007785] mlx4_en 0000:01:00.0: registered PHC clock
[ 27.070877] mlx4_en 0000:01:00.0: Activating port:2
[ 27.133993] mlx4_en: 0000:01:00.0: Port 2: Using 64 TX rings
[ 27.201915] mlx4_en: 0000:01:00.0: Port 2: Using 4 RX rings
[ 27.268798] mlx4_en: 0000:01:00.0: Port 2: frag:0 - size:1522 prefix:0 stride:1536
[ 27.362021] mlx4_en: 0000:01:00.0: Port 2: Initializing port
[ 27.434754] mlx4_core 0000:01:00.0 eno1: renamed from eth0
[ 27.512496] mlx4_core 0000:01:00.0 eno1d1: renamed from eth1
[ 27.735069] random: fast init done
[ 28.250283] SGI XFS with ACLs, security attributes, no debug enabled
[ 28.329275] XFS (dm-0): Mounting V5 Filesystem
[ 28.425520] XFS (dm-0): Ending clean mount
[ 28.505469] mlx4_en: eno1d1: Link Up
[ 28.798515] systemd-journald[278]: Received SIGTERM from PID 1 (systemd).
[ 28.816777] systemd: 20 output lines suppressed due to ratelimiting
[ 28.843206] audit: type=1404 audit(1481665008.174:2): enforcing=1 old_enforcing=0 auid=4294967295 ses=4294967295
[ 29.275766] SELinux: 32768 avtab hash slots, 104865 rules.
[ 29.311159] SELinux: 32768 avtab hash slots, 104865 rules.
[ 29.396915] SELinux: 8 users, 14 roles, 4983 types, 301 bools, 1 sens, 1024 cats
[ 29.396921] SELinux: 91 classes, 104865 rules
[ 29.405995] SELinux: Permission validate_trans in class security not defined in policy.
[ 29.534735] SELinux: Permission module_load in class system not defined in policy.
[ 29.693475] SELinux: Class binder not defined in policy.
[ 29.824717] SELinux: Class cap_userns not defined in policy.
[ 29.960328] SELinux: Class cap2_userns not defined in policy.
[ 30.096987] SELinux: Class sctp_socket not defined in policy.
[ 30.233647] SELinux: Class icmp_socket not defined in policy.
[ 30.370305] SELinux: Class ax25_socket not defined in policy.
[ 30.506963] SELinux: Class ipx_socket not defined in policy.
[ 30.642581] SELinux: Class netrom_socket not defined in policy.
[ 30.781326] SELinux: Class bridge_socket not defined in policy.
[ 30.920071] SELinux: Class atmpvc_socket not defined in policy.
[ 31.058818] SELinux: Class x25_socket not defined in policy.
[ 31.194433] SELinux: Class rose_socket not defined in policy.
[ 31.331091] SELinux: Class decnet_socket not defined in policy.
[ 31.469842] SELinux: Class atmsvc_socket not defined in policy.
[ 31.608584] SELinux: Class rds_socket not defined in policy.
[ 31.744199] SELinux: Class irda_socket not defined in policy.
[ 31.880859] SELinux: Class pppox_socket not defined in policy.
[ 32.018561] SELinux: Class llc_socket not defined in policy.
[ 32.154176] SELinux: Class ib_socket not defined in policy.
[ 32.288749] SELinux: Class mpls_socket not defined in policy.
[ 32.425408] SELinux: Class can_socket not defined in policy.
[ 32.561024] SELinux: Class tipc_socket not defined in policy.
[ 32.697683] SELinux: Class bluetooth_socket not defined in policy.
[ 32.839559] SELinux: Class iucv_socket not defined in policy.
[ 32.976219] SELinux: Class rxrpc_socket not defined in policy.
[ 33.113920] SELinux: Class isdn_socket not defined in policy.
[ 33.250580] SELinux: Class phonet_socket not defined in policy.
[ 33.389325] SELinux: Class ieee802154_socket not defined in policy.
[ 33.532248] SELinux: Class caif_socket not defined in policy.
[ 33.656387] SELinux: Class alg_socket not defined in policy.
[ 33.725348] SELinux: Class nfc_socket not defined in policy.
[ 33.794301] SELinux: Class vsock_socket not defined in policy.
[ 33.865345] SELinux: Class kcm_socket not defined in policy.
[ 33.934298] SELinux: Class qipcrtr_socket not defined in policy.
[ 34.007429] SELinux: the above unknown classes and permissions will be allowed
[ 34.094131] SELinux: Completing initialization.
[ 34.094132] SELinux: Setting up existing superblocks.
[ 34.115577] audit: type=1403 audit(1481665013.447:3): policy loaded auid=4294967295 ses=4294967295
[ 34.119916] systemd[1]: Successfully loaded SELinux policy in 5.276847s.
[ 34.223152] systemd[1]: RTC configured in localtime, applying delta of -300 minutes to system time.
[ 34.274091] systemd[1]: Relabelled /dev and /run in 47.393ms.
[ 34.696398] systemd-journald[579]: Received request to flush runtime journal from PID 1
[ 34.824700] RPC: Registered named UNIX socket transport module.
[ 34.954590] RPC: Registered udp transport module.
[ 34.954592] RPC: Registered tcp transport module.
[ 34.954593] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 35.206778] Installing knfsd (copyright (C) 1996 okir at monad.swb.de).
[ 35.569775] input: Power Button as /devices/LNXSYSTM:00/PNP0C0C:00/input/input0
[ 35.572132] xgene-slimpro-mbox APMC0D01:00: APM X-Gene SLIMpro MailBox registered
[ 35.865673] ACPI: Power Button [PWRB]
[ 35.985733] xgene-gpio-sb APMC0D15:00: Support 22 gpios, 6 irqs start from pin 8
[ 36.132022] xgene-gpio-sb APMC0D15:00: X-Gene GPIO Standby driver registered
[ 36.282950] xgene-rng APMC0D18:00: Couldn't get the clock for RNG
[ 36.422797] xgene-slimpro-i2c APMC0D40:00: i2c mailbox channel request failed
[ 36.591693] Adding 11722688k swap on /dev/mapper/rhel_hp--moonshot--02--c08-swap. Priority:-1 extents:1 across:11722688k SSFS
[ 36.787069] XFS (sda2): Mounting V5 Filesystem
[ 36.868688] <mlx4_ib> mlx4_ib_add: mlx4_ib: Mellanox ConnectX InfiniBand driver v2.2-1 (Feb 2014)
[ 36.869195] <mlx4_ib> mlx4_ib_add: counter index 2 for port 1 allocated 1
[ 36.869196] <mlx4_ib> mlx4_ib_add: counter index 3 for port 2 allocated 1
[ 37.308253] Rounding down aligned max_sectors from 4294967295 to 4294967168
[ 37.350909] Loading iSCSI transport class v2.0-870.
[ 37.392750] iscsi: registered transport (iser)
[ 37.637247] RPC: Registered rdma transport module.
[ 37.637249] RPC: Registered rdma backchannel transport module.
[ 38.038304] XFS (dm-2): Mounting V5 Filesystem
[ 38.079284] XFS (sda2): Ending clean mount
[ 38.297433] XFS (dm-2): Ending clean mount
[ 43.639471] IPv6: ADDRCONF(NETDEV_UP): eno1: link is not ready
[ 43.710421] mlx4_en: eno1: frag:0 - size:1522 prefix:0 stride:1536
[ 43.838542] mlx4_en: eno1: Link Up
[ 43.838572] IPv6: ADDRCONF(NETDEV_UP): eno1: link is not ready
[ 43.908671] IPv6: ADDRCONF(NETDEV_CHANGE): eno1: link becomes ready
[ 43.991371] IPv6: ADDRCONF(NETDEV_UP): eno1d1: link is not ready
[ 44.064245] mlx4_en: eno1d1: frag:0 - size:1522 prefix:0 stride:1536
[ 90.846478] random: crng init done
^ permalink raw reply
* [PATCHv4 00/15] clk: ti: add support for hwmod clocks
From: Michael Turquette @ 2016-12-13 22:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213153724.GT4920@atomide.com>
Quoting Tony Lindgren (2016-12-13 07:37:24)
> * Tero Kristo <t-kristo@ti.com> [161213 00:31]:
> > On 13/12/16 06:40, Michael Turquette wrote:
> > > Quoting Tony Lindgren (2016-12-12 17:31:34)
> > > > * Stephen Boyd <sboyd@codeaurora.org> [161212 16:49]:
> > > > > I spent a bunch of time looking at this again today. From a DT
> > > > > perspective we don't want to have clocks or clockdomains nodes
> > > > > below the cm1/cm2/prm dt nodes. That's getting to the point of
> > > > > describing individual elements of a device that should be
> > > > > described in the driver instead of DT.
> > > >
> > > > I agree we don't need separate clocks and clockdomain nodes.. But
> > > > I think you're missing something here though. The clockdomains in
> > > > this case are separate devices on the interconnect, not individual
> > > > elements within a device. The outputs of a clockdomain are individual
> > > > elements of a clockdomain and can be just described as indexed
> > > > outputs of the clockdomain.
> > >
> > > Is the goal to describe this hardware topology in DT? Is that right
> > > thing to do? I think it's cool to have this modeled *somehow* in Linux,
> > > but I'm not sure DT is the right place to model the interconnect and
> > > every device hanging off of it.
>
> Well struct device is what we should use, the DT nodes pretty much
> map with that :)
>
> > > I don't want to put words in Stephen's mouth, but I think the issue over
> > > whether clockdomains are CCF clock providers or some genpd thing is
> > > probably less important to him than the fact that the DT bindings are
> > > super detailed to inner workings of the SoC.
> >
> > Ok, so your preference would be to reduce the data under DT, and the ideal
> > approach would be a single prcm node. I think we still need to keep the prm
> > / cm1 / cm2 as separate nodes, as they are pretty individual from hardware
> > point of view, provide quite different features, and they reside in some
> > cases in quite different address spaces also. Anyway, here's what I gather
> > we should probably have in DT:
> >
> > - reset provider
> > * example: resets = <&prm OMAP4_IVA2_RESET>;
> > * only from 'prm' node
> >
> > - genpd provider (for the hwmods, clockdomains, powerdomains, voltage
> > domains)
> > * examples: power-domains = <&cm2 OMAP4_DSS_CORE_MOD>;
> > power-domains = <&cm2 OMAP4_DSS_CLKDM>;
> > power-domains = <&prm OMAP4_DSS_PWRDM>;
> > power-domains = <&prm OMAP4_CORE_VOLTDM>;
> > * from all 'prm', 'cm1' and 'cm2' nodes, though 'prm' would be the only
> > one providing _CLKDM, _PWRDM, _VOLTDM genpds.
> >
> > - clock provider (for anything that requires clocks)
> > * example: clocks = <&cm1 OMAP4_DPLL_MPU_CK>;
> > * from all 'prm', 'cm1' and 'cm2' nodes
>
> Makes sense to me in general.
>
> For the clkctrl clocks, here's what I'd like to see. The driver should be
> just a regular device driver along the lines we did with the ADPLL as in
> Documentation/devicetree/bindings/clock/ti/adpll.txt.
>
> For the binding, something like the following should work as a minimal
> example, this follows what we have in the hardware:
>
> &prm {
> ...
>
> /* See "CD_WKUP Clock Domain" in 4430 TRM page 393 */
> wkup_cm: clock at 1800 {
> compatible = "ti,clkctrl";
> reg = <0x1800 0x100>;
> #clock-cells = <1>;
> clocks = <&wkup_l4_iclk2 &wkup_32k_fclk
> &32k_fclk &gp1_fclk>;
> clock-output-names =
> "sysctrl_padconf_wkup",
> "badgap",
> "sysctrl_general_wkup",
> "gpio1",
> "keyboard",
> "sar_ram",
> "32ktimer",
> "gptimer1";
Is there a technical reason to use clock-output-names? If you share a
header between the clock provider driver and DT with the phandle offsets
then we should be able to avoid this property altogether. Stephen and I
are trying to phase this one out as much as possible.
Regards,
Mike
> };
> ...
>
> /* See "CD_EMU Clock Domain" in 4430 TRM page 424 */
> emu_cm: clock at 1a00 {
> compatible = "ti,clkctrl";
> reg = <0x1a00 0x100>;
> #clock-cells = <1>;
> clocks = <&emu_sys_clk &core_dpll_emu_clk>;
> clock-output-names = "debug";
> };
> ...
> };
>
> So the device tree nodes could be minimal as above and the rest can
> be taken care of by the driver. We may need separate compatible strings
> for the various instances, not sure about that.
>
> Note that the clkctrl hardware manages multiple clocks for each
> interconnect target module. AFAIK we don't need to care about that from
> the consumer device driver point of view as it can't separately manage
> functional and interface clock.
>
> We need few clockctrl clocks early for system timers, but those can
> be registered earlier in the driver.
>
> Then some clkctrl clocks have optional aux clocks. I think those can
> be just be regular child clocks of the module clocks.
>
> > This would eventually cause an ABI breakage for the clock handles, if we
> > transfer the existing clocks to this format, and remove the existing clock
> > handles from DT. Otherwise, I think we could just transition the existing
> > hwmod data to this new format only, and add the clockdomain / powerdomain /
> > voltagedomain support a bit later.
>
> Let's not break anything while doing this.. And let's not mess with the
> hwmod except where it helps moving that into regular device drivers.
> If necessary we can maybe first register the new clock instances, then
> register the old clocks if new clock is not found?
>
> Regards,
>
> Tony
^ permalink raw reply
* [PATCH 1/2] arm64: setup: introduce kaslr_offset()
From: Alexander Popov @ 2016-12-13 22:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161212112914.GC21248@arm.com>
On 12.12.2016 14:29, Will Deacon wrote:
> On Sun, Dec 11, 2016 at 03:50:55AM +0300, Alexander Popov wrote:
>> Introduce kaslr_offset() similarly to x86_64 for fixing kcov.
>>
>> Signed-off-by: Alexander Popov <alex.popov@linux.com>
>> ---
>> arch/arm64/include/asm/setup.h | 19 +++++++++++++++++++
>> arch/arm64/include/uapi/asm/setup.h | 4 ++--
>> arch/arm64/kernel/setup.c | 8 ++++----
>> 3 files changed, 25 insertions(+), 6 deletions(-)
>> create mode 100644 arch/arm64/include/asm/setup.h
>
> You could probably just stick this in asm/memory.h, since that's where
> kimage_vaddr is declared and it would save adding a new header file.
Thanks, Will. I'll do that.
--
Alexander
^ permalink raw reply
* [GIT PULL] arm64 updates for 4.10
From: Stephen Rothwell @ 2016-12-13 23:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213192156.GA12471@e104818-lin.cambridge.arm.com>
Hi Linus,
On Tue, 13 Dec 2016 19:21:59 +0000 Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> Please pull the arm64 updates for 4.10 below.
>
> The patches touch the generic include/linux/thread_info.h to factor out
> struct restart_block into a separate include/linux/restart_block.h file
> (needed for arm64 moving thread_info off stack; acked by Andy
> Lutomirski).
>
> There is also a small refactoring touching drivers/irqchip/irq-gic-v3.c
> and additional watchpoint lengths added to
> include/uapi/linux/hw_breakpoint.h.
I have also been carrying a merge fix up patch due to a conflict in the
merge of the arm64 tree with commit
272d01bd790f ("arm64: Fix circular include of asm/lse.h through linux/jump_label.h")
from v4.9-rc5:
From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Tue, 22 Nov 2016 10:30:40 +1100
Subject: [PATCH] arm64: merge fix for code movement to cpucaps.h
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 87b446535185..4174f09678c4 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -34,7 +34,8 @@
#define ARM64_HAS_32BIT_EL0 13
#define ARM64_HYP_OFFSET_LOW 14
#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15
+#define ARM64_HAS_NO_FPSIMD 16
-#define ARM64_NCAPS 16
+#define ARM64_NCAPS 17
#endif /* __ASM_CPUCAPS_H */
--
2.10.2
--
Cheers,
Stephen Rothwell
^ permalink raw reply related
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