* [PATCH v3 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
From: Florian Fainelli @ 2016-12-14 2:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214023553.9377-1-f.fainelli@gmail.com>
Register the TS-7300 FPGA manager device drivers which allows us to load
bitstreams into the on-board Altera Cyclone II FPGA.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 3b39ea353d30..acf72ea670ef 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
.phy_id = 1,
};
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+
+/* Relative to EP93XX_CS1_PHYS_BASE */
+#define TS73XX_FPGA_LOADER_BASE 0x03c00000
+
+static struct resource ts73xx_fpga_resources[] = {
+ {
+ .start = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
+ .end = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device ts73xx_fpga_device = {
+ .name = "ts73xx-fpga-mgr",
+ .id = -1,
+ .resource = ts73xx_fpga_resources,
+ .num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
+};
+
+#endif
+
static void __init ts72xx_init_machine(void)
{
ep93xx_init_devices();
@@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
platform_device_register(&ts72xx_wdt_device);
ep93xx_register_eth(&ts72xx_eth_data, 1);
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+ if (board_is_ts7300())
+ platform_device_register(&ts73xx_fpga_device);
+#endif
}
MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
--
2.9.3
^ permalink raw reply related
* [PATCH v3 0/2] FPGA: TS-7300 FPGA manager
From: Florian Fainelli @ 2016-12-14 2:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This patch series adds support for loading bitstreams into the Altera Cyclone II
connected to an EP9302 on a TS-7300 board.
Changes in v3:
- fix write_init and write_complete signatures
Changes in v2:
- rebased against fpga/for-next
- added defines for configuration bits and delays
- added error mesage if ioremap() fails
- detailed how the configuration through CPLD is done
Florian Fainelli (2):
ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
FPGA: Add TS-7300 FPGA manager
arch/arm/mach-ep93xx/ts72xx.c | 26 +++++++
drivers/fpga/Kconfig | 7 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/ts73xx-fpga.c | 163 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 197 insertions(+)
create mode 100644 drivers/fpga/ts73xx-fpga.c
--
2.9.3
^ permalink raw reply
* [PATCH v2 0/2] FPGA: TS-7300 FPGA manager
From: Florian Fainelli @ 2016-12-14 2:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214022845.5692-1-f.fainelli@gmail.com>
On 12/13/2016 06:28 PM, Florian Fainelli wrote:
> Hi all,
>
> This patch series adds support for loading bitstreams into the Altera Cyclone II
> connected to an EP9302 on a TS-7300 board.
>
> Changes in v2:
>
> - rebased against fpga/for-next
> - added defines for configuration bits and delays
> - added error mesage if ioremap() fails
> - detailed how the configuration through CPLD is done
I forgot to fix a function signature while rebasing, let me resubmit this.
>
> Florian Fainelli (2):
> ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
> FPGA: Add TS-7300 FPGA manager
>
> arch/arm/mach-ep93xx/ts72xx.c | 26 +++++++
> drivers/fpga/Kconfig | 7 ++
> drivers/fpga/Makefile | 1 +
> drivers/fpga/ts73xx-fpga.c | 162 ++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 196 insertions(+)
> create mode 100644 drivers/fpga/ts73xx-fpga.c
>
--
Florian
^ permalink raw reply
* [PATCH v2 2/2] FPGA: Add TS-7300 FPGA manager
From: Florian Fainelli @ 2016-12-14 2:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214022845.5692-1-f.fainelli@gmail.com>
Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.
The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/fpga/Kconfig | 7 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/ts73xx-fpga.c | 162 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 170 insertions(+)
create mode 100644 drivers/fpga/ts73xx-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2853a4..d9cbef60db80 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -33,6 +33,13 @@ config FPGA_MGR_SOCFPGA_A10
help
FPGA manager driver support for Altera Arria10 SoCFPGA.
+config FPGA_MGR_TS73XX
+ tristate "Technologic Systems TS-73xx SBC FPGA Manager"
+ depends on ARCH_EP93XX && MACH_TS72XX
+ help
+ FPGA manager driver support for the Altera Cyclone II FPGA
+ present on the TS-73xx SBC boards.
+
config FPGA_MGR_ZYNQ_FPGA
tristate "Xilinx Zynq FPGA"
depends on ARCH_ZYNQ || COMPILE_TEST
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bcf42a6..a1160169e6d9 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Manager Drivers
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
+obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
# FPGA Bridge Drivers
diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
new file mode 100644
index 000000000000..c004be5954ae
--- /dev/null
+++ b/drivers/fpga/ts73xx-fpga.c
@@ -0,0 +1,162 @@
+/*
+ * Technologic Systems TS-73xx SBC FPGA loader
+ *
+ * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
+ *
+ * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
+ * TS-7300, heavily based on load_fpga.c in their vendor tree.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <linux/iopoll.h>
+#include <linux/fpga/fpga-mgr.h>
+
+#define TS73XX_FPGA_DATA_REG 0
+#define TS73XX_FPGA_CONFIG_REG 1
+
+#define TS73XX_FPGA_WRITE_DONE 0x1
+#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000 /* us */
+#define TS73XX_FPGA_RESET 0x2
+#define TS73XX_FPGA_RESET_LOW_DELAY 30 /* us */
+#define TS73XX_FPGA_RESET_HIGH_DELAY 80 /* us */
+#define TS73XX_FPGA_LOAD_OK 0x4
+#define TS73XX_FPGA_CONFIG_LOAD 0x8
+
+struct ts73xx_fpga_priv {
+ void __iomem *io_base;
+ struct device *dev;
+};
+
+static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int ts73xx_fpga_write_init(struct fpga_manager *mgr, u32 flags,
+ const char *buf, size_t count)
+{
+ struct ts73xx_fpga_priv *priv = mgr->priv;
+
+ /* Reset the FPGA */
+ writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ udelay(TS73XX_FPGA_RESET_LOW_DELAY);
+ writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
+
+ return 0;
+}
+
+static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
+ size_t count)
+{
+ struct ts73xx_fpga_priv *priv = mgr->priv;
+ size_t i = 0;
+ int ret;
+ u8 reg;
+
+ while (count--) {
+ ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
+ reg, !(reg & TS73XX_FPGA_WRITE_DONE),
+ 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
+ if (ret < 0)
+ return ret;
+
+ writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
+ i++;
+ }
+
+ usleep_range(1000, 2000);
+ reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ reg |= TS73XX_FPGA_CONFIG_LOAD;
+ writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ usleep_range(1000, 2000);
+
+ reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ reg &= ~TS73XX_FPGA_CONFIG_LOAD;
+ writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
+
+ return 0;
+}
+
+static int ts73xx_fpga_write_complete(struct fpga_manager *mgr, u32 flags)
+{
+ struct ts73xx_fpga_priv *priv = mgr->priv;
+ u8 reg;
+
+ reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
+ if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static const struct fpga_manager_ops ts73xx_fpga_ops = {
+ .state = ts73xx_fpga_state,
+ .write_init = ts73xx_fpga_write_init,
+ .write = ts73xx_fpga_write,
+ .write_complete = ts73xx_fpga_write_complete,
+};
+
+static int ts73xx_fpga_probe(struct platform_device *pdev)
+{
+ struct device *kdev = &pdev->dev;
+ struct ts73xx_fpga_priv *priv;
+ struct fpga_manager *mgr;
+ struct resource *res;
+ int err;
+
+ priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = kdev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->io_base = devm_ioremap_resource(kdev, res);
+ if (IS_ERR(priv->io_base)) {
+ dev_err(kdev, "unable to remap registers\n");
+ return PTR_ERR(priv->io_base);
+ }
+
+ err = fpga_mgr_register(kdev, "TS-73xx FPGA Manager",
+ &ts73xx_fpga_ops, priv);
+ if (err) {
+ dev_err(kdev, "failed to register FPGA manager\n");
+ return err;
+ }
+
+ return err;
+}
+
+static int ts73xx_fpga_remove(struct platform_device *pdev)
+{
+ fpga_mgr_unregister(&pdev->dev);
+
+ return 0;
+}
+
+static struct platform_driver ts73xx_fpga_driver = {
+ .driver = {
+ .name = "ts73xx-fpga-mgr",
+ },
+ .probe = ts73xx_fpga_probe,
+ .remove = ts73xx_fpga_remove,
+};
+module_platform_driver(ts73xx_fpga_driver);
+
+MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
+MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
+MODULE_LICENSE("GPL v2");
--
2.9.3
^ permalink raw reply related
* [PATCH v2 1/2] ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
From: Florian Fainelli @ 2016-12-14 2:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161214022845.5692-1-f.fainelli@gmail.com>
Register the TS-7300 FPGA manager device drivers which allows us to load
bitstreams into the on-board Altera Cyclone II FPGA.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/mach-ep93xx/ts72xx.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 3b39ea353d30..acf72ea670ef 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -230,6 +230,28 @@ static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
.phy_id = 1,
};
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+
+/* Relative to EP93XX_CS1_PHYS_BASE */
+#define TS73XX_FPGA_LOADER_BASE 0x03c00000
+
+static struct resource ts73xx_fpga_resources[] = {
+ {
+ .start = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE,
+ .end = EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device ts73xx_fpga_device = {
+ .name = "ts73xx-fpga-mgr",
+ .id = -1,
+ .resource = ts73xx_fpga_resources,
+ .num_resources = ARRAY_SIZE(ts73xx_fpga_resources),
+};
+
+#endif
+
static void __init ts72xx_init_machine(void)
{
ep93xx_init_devices();
@@ -238,6 +260,10 @@ static void __init ts72xx_init_machine(void)
platform_device_register(&ts72xx_wdt_device);
ep93xx_register_eth(&ts72xx_eth_data, 1);
+#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX)
+ if (board_is_ts7300())
+ platform_device_register(&ts73xx_fpga_device);
+#endif
}
MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
--
2.9.3
^ permalink raw reply related
* [PATCH v2 0/2] FPGA: TS-7300 FPGA manager
From: Florian Fainelli @ 2016-12-14 2:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This patch series adds support for loading bitstreams into the Altera Cyclone II
connected to an EP9302 on a TS-7300 board.
Changes in v2:
- rebased against fpga/for-next
- added defines for configuration bits and delays
- added error mesage if ioremap() fails
- detailed how the configuration through CPLD is done
Florian Fainelli (2):
ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300
FPGA: Add TS-7300 FPGA manager
arch/arm/mach-ep93xx/ts72xx.c | 26 +++++++
drivers/fpga/Kconfig | 7 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/ts73xx-fpga.c | 162 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 196 insertions(+)
create mode 100644 drivers/fpga/ts73xx-fpga.c
--
2.9.3
^ permalink raw reply
* [PATCH] arm: Adjust memory boundaries after reservations
From: Laura Abbott @ 2016-12-14 2:11 UTC (permalink / raw)
To: linux-arm-kernel
The poorly named sanity_check_meminfo is responsible for setting up the
boundary for lowmem/highmem. This needs to be set up before memblock
reservations can occur. At the time memblock reservations can occur,
memory can also be removed from the system. This can throw off the
calculation of the lowmem/highmem boundary. On some systems this may be
harmless, on others this may result in incorrect ranges being passed to
the main memory allocator. Correct this by recalcuating the
lowmem/highmem boundary after all reservations have been made.
As part of this, rename sanity_check_meminfo to actually refect what the
function is doing.
Reported-by: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Laura Abbott <labbott@redhat.com>
---
The particular issue I reproduced for
https://marc.info/?l=linux-arm-kernel&m=148145259511248 involved the lowmem
boundary being greater than the end of ram thanks to the memblock_steal.
The re-calcuation should have no effect unless memory was actually removed
from the system. Putting it in arm_memblock_steal doesn't cover all cases
either since the devicetree memory map can also remove memory.
---
arch/arm/kernel/setup.c | 12 ++++++++++--
arch/arm/mm/mmu.c | 15 +++++++++------
arch/arm/mm/nommu.c | 2 +-
3 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 34e3f3c..62f91bd 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -81,7 +81,7 @@ __setup("fpe=", fpe_setup);
extern void init_default_cache_policy(unsigned long);
extern void paging_init(const struct machine_desc *desc);
extern void early_paging_init(const struct machine_desc *);
-extern void sanity_check_meminfo(void);
+extern void update_memory_bounds(void);
extern enum reboot_mode reboot_mode;
extern void setup_dma_zone(const struct machine_desc *desc);
@@ -1093,8 +1093,16 @@ void __init setup_arch(char **cmdline_p)
setup_dma_zone(mdesc);
xen_early_init();
efi_init();
- sanity_check_meminfo();
+ /*
+ * We need to make sure the calculation for lowmem/highmem is set
+ * appropriately before reserving/allocating any memory
+ */
+ update_memory_bounds();
arm_memblock_init(mdesc);
+ /*
+ * Memory may have been removed so the bounds need to be recalcuated.
+ */
+ update_memory_bounds();
early_ioremap_reset();
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4001dd1..666e789 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1152,13 +1152,14 @@ early_param("vmalloc", early_vmalloc);
phys_addr_t arm_lowmem_limit __initdata = 0;
-void __init sanity_check_meminfo(void)
+void __init update_memory_bounds(void)
{
phys_addr_t memblock_limit = 0;
int highmem = 0;
u64 vmalloc_limit;
struct memblock_region *reg;
bool should_use_highmem = false;
+ phys_addr_t lowmem_limit = 0;
/*
* Let's use our own (unoptimized) equivalent of __pa() that is
@@ -1196,18 +1197,18 @@ void __init sanity_check_meminfo(void)
pr_notice("Truncating RAM at %pa-%pa",
&block_start, &block_end);
block_end = vmalloc_limit;
- pr_cont(" to -%pa", &block_end);
+ pr_cont(" to -%pa\n", &block_end);
memblock_remove(vmalloc_limit, overlap_size);
should_use_highmem = true;
}
}
if (!highmem) {
- if (block_end > arm_lowmem_limit) {
+ if (block_end > lowmem_limit) {
if (reg->size > size_limit)
- arm_lowmem_limit = vmalloc_limit;
+ lowmem_limit = vmalloc_limit;
else
- arm_lowmem_limit = block_end;
+ lowmem_limit = block_end;
}
/*
@@ -1227,12 +1228,14 @@ void __init sanity_check_meminfo(void)
if (!IS_ALIGNED(block_start, PMD_SIZE))
memblock_limit = block_start;
else if (!IS_ALIGNED(block_end, PMD_SIZE))
- memblock_limit = arm_lowmem_limit;
+ memblock_limit = lowmem_limit;
}
}
}
+ arm_lowmem_limit = lowmem_limit;
+
if (should_use_highmem)
pr_notice("Consider using a HIGHMEM enabled kernel.\n");
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 2740967..e5bc874 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -295,7 +295,7 @@ void __init arm_mm_memblock_reserve(void)
#endif
}
-void __init sanity_check_meminfo(void)
+void __init update_memory_bounds(void)
{
phys_addr_t end;
sanity_check_meminfo_mpu();
--
2.7.4
^ permalink raw reply related
* [PATCH] iopoll: include <linux/ktime.h> instead of <linux/hrtimer.h>
From: Masahiro Yamada @ 2016-12-14 1:33 UTC (permalink / raw)
To: linux-arm-kernel
The timer APIs this header needs are ktime_get(), ktime_add_us(),
and ktime_compare(). So, including <linux/ktime.h> seems enough.
This commit will cut unnecessary header file parsing.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
I was not quite sure whom I should send this patch to.
I am sending this to Will Deacon because commit 54c523127bcc
("iopoll: Introduce memory-mapped IO polling macros") was applied
by him.
include/linux/iopoll.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
index 1c30014..d29e1e2 100644
--- a/include/linux/iopoll.h
+++ b/include/linux/iopoll.h
@@ -17,7 +17,7 @@
#include <linux/kernel.h>
#include <linux/types.h>
-#include <linux/hrtimer.h>
+#include <linux/ktime.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
--
2.7.4
^ permalink raw reply related
* [PATCH] ipmi: bt-bmc: Use a regmap for register access
From: Joel Stanley @ 2016-12-14 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206025715.2002-1-andrew@aj.id.au>
On Tue, Dec 6, 2016 at 1:27 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The registers for the bt-bmc device live under the Aspeed LPC
> controller. Devicetree bindings have recently been introduced for the
> LPC controller where the "host" portion of the LPC register space is
> described as a syscon device. Future devicetrees describing the bt-bmc
> device should nest its node under the appropriate "simple-mfd", "syscon"
> compatible node.
>
> This change allows the bt-bmc driver to function with both syscon and
> non-syscon- based devicetree descriptions by always using a regmap for
> register access, either retrieved from the parent syscon device or
> instantiated if none exists.
>
> The patch has been tested on an OpenPOWER Palmetto machine, successfully
> booting, rebooting and powering down the host.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> drivers/char/ipmi/Kconfig | 1 +
> drivers/char/ipmi/bt-bmc.c | 82 ++++++++++++++++++++++++++++++++++------------
> 2 files changed, 62 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
> index 7f816655cbbf..b5d48d9af124 100644
> --- a/drivers/char/ipmi/Kconfig
> +++ b/drivers/char/ipmi/Kconfig
> @@ -79,6 +79,7 @@ endif # IPMI_HANDLER
>
> config ASPEED_BT_IPMI_BMC
> depends on ARCH_ASPEED
If you do a v2 of this series it would be great to add || COMPILE_TEST here.
> + depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
> tristate "BT IPMI bmc driver"
> help
> Provides a driver for the BT (Block Transfer) IPMI interface
> diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
> index fc9e8891eae3..ca1e20f6c6c5 100644
> --- a/drivers/char/ipmi/bt-bmc.c
> +++ b/drivers/char/ipmi/bt-bmc.c
> @@ -12,10 +12,13 @@
> #include <linux/errno.h>
> #include <linux/interrupt.h>
> #include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/miscdevice.h>
> #include <linux/module.h>
> +#include <linux/of.h>
> #include <linux/platform_device.h>
> #include <linux/poll.h>
> +#include <linux/regmap.h>
> #include <linux/sched.h>
> #include <linux/timer.h>
>
> @@ -60,7 +63,8 @@
> struct bt_bmc {
> struct device dev;
> struct miscdevice miscdev;
> - void __iomem *base;
> + struct regmap *map;
> + int offset;
> int irq;
> wait_queue_head_t queue;
> struct timer_list poll_timer;
> @@ -69,14 +73,31 @@ struct bt_bmc {
>
> static atomic_t open_count = ATOMIC_INIT(0);
>
> +static struct regmap_config bt_regmap_cfg = {
const?
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> static u8 bt_inb(struct bt_bmc *bt_bmc, int reg)
> {
> - return ioread8(bt_bmc->base + reg);
> + uint32_t val = 0;
> + int rc;
> +
> + rc = regmap_read(bt_bmc->map, bt_bmc->offset + reg, &val);
> + WARN(rc != 0, "%s:%d: regmap_read() failed: %d\n",
> + __FILE__, __LINE__, rc);
Under what circumstances do we expect the read to fail?
This isn't much cleaner, but I prefer it slightly:
rc = regmap_read(bt_bmc->map, bt_bmc->offset + reg, &val);
if (rc) {
dev_warn(bt_bmc->dev, "read failed %d\n", rc);
return rc;
}
return val;
> +
> + return rc == 0 ? (u8) val : 0;
> }
>
> static void bt_outb(struct bt_bmc *bt_bmc, u8 data, int reg)
> {
> - iowrite8(data, bt_bmc->base + reg);
> + int rc;
> +
> + rc = regmap_write(bt_bmc->map, bt_bmc->offset + reg, data);
> + WARN(rc != 0, "%s:%d: regmap_write() failed: %d\n",
> + __FILE__, __LINE__, rc);
> }
>
> static void clr_rd_ptr(struct bt_bmc *bt_bmc)
> @@ -367,14 +388,18 @@ static irqreturn_t bt_bmc_irq(int irq, void *arg)
> {
> struct bt_bmc *bt_bmc = arg;
> u32 reg;
> + int rc;
> +
> + rc = regmap_read(bt_bmc->map, bt_bmc->offset + BT_CR2, ®);
> + if (rc)
> + return IRQ_NONE;
>
> - reg = ioread32(bt_bmc->base + BT_CR2);
> reg &= BT_CR2_IRQ_H2B | BT_CR2_IRQ_HBUSY;
> if (!reg)
> return IRQ_NONE;
>
> /* ack pending IRQs */
> - iowrite32(reg, bt_bmc->base + BT_CR2);
> + regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR2, reg);
>
> wake_up(&bt_bmc->queue);
> return IRQ_HANDLED;
> @@ -384,7 +409,6 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - u32 reg;
> int rc;
>
> bt_bmc->irq = platform_get_irq(pdev, 0);
> @@ -405,18 +429,17 @@ static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> * will be cleared (along with B2H) when we can write the next
> * message to the BT buffer
> */
> - reg = ioread32(bt_bmc->base + BT_CR1);
> - reg |= BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY;
> - iowrite32(reg, bt_bmc->base + BT_CR1);
> + rc = regmap_update_bits(bt_bmc->map, bt_bmc->offset + BT_CR1,
> + (BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY),
> + (BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY));
You could drop the ( ) around the flags if you want.
>
> - return 0;
> + return rc;
> }
>
> static int bt_bmc_probe(struct platform_device *pdev)
> {
> struct bt_bmc *bt_bmc;
> struct device *dev;
> - struct resource *res;
> int rc;
>
> if (!pdev || !pdev->dev.of_node)
> @@ -431,10 +454,27 @@ static int bt_bmc_probe(struct platform_device *pdev)
>
> dev_set_drvdata(&pdev->dev, bt_bmc);
>
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - bt_bmc->base = devm_ioremap_resource(&pdev->dev, res);
> - if (IS_ERR(bt_bmc->base))
> - return PTR_ERR(bt_bmc->base);
> + bt_bmc->map = syscon_node_to_regmap(pdev->dev.parent->of_node);
> + if (IS_ERR(bt_bmc->map)) {
> + struct resource *res;
> + void __iomem *base;
> +
> + /*
> + * Assume it's not the MFD-based devicetree description, in
> + * which case generate a regmap ourselves
> + */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + bt_bmc->map = devm_regmap_init_mmio(dev, base, &bt_regmap_cfg);
> + bt_bmc->offset = 0;
> + } else {
> + rc = of_property_read_u32(dev->of_node, "reg", &bt_bmc->offset);
> + if (rc)
> + return rc;
> + }
>
> mutex_init(&bt_bmc->mutex);
> init_waitqueue_head(&bt_bmc->queue);
> @@ -461,12 +501,12 @@ static int bt_bmc_probe(struct platform_device *pdev)
> add_timer(&bt_bmc->poll_timer);
> }
>
> - iowrite32((BT_IO_BASE << BT_CR0_IO_BASE) |
> - (BT_IRQ << BT_CR0_IRQ) |
> - BT_CR0_EN_CLR_SLV_RDP |
> - BT_CR0_EN_CLR_SLV_WRP |
> - BT_CR0_ENABLE_IBT,
> - bt_bmc->base + BT_CR0);
> + regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR0,
> + (BT_IO_BASE << BT_CR0_IO_BASE) |
> + (BT_IRQ << BT_CR0_IRQ) |
> + BT_CR0_EN_CLR_SLV_RDP |
> + BT_CR0_EN_CLR_SLV_WRP |
> + BT_CR0_ENABLE_IBT);
>
> clr_b_busy(bt_bmc);
>
> --
> 2.9.3
>
^ permalink raw reply
* [GIT PULL] arm64 updates for 4.10
From: Linus Torvalds @ 2016-12-14 0:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213192156.GA12471@e104818-lin.cambridge.arm.com>
On Tue, Dec 13, 2016 at 11:21 AM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
>
> Please pull the arm64 updates for 4.10 below.
Mind checking that I got the conflict resolution right?
The conflict looked completely trivial, but with stuff moving across
files and since I don't build the end result (much less boot it) I
could easily have missed some screw-up of mine.
Thanks,
Linus
^ permalink raw reply
* [PATCH 2/2] kbuild: make modversion for exported asm symbols more convivial
From: Nicolas Pitre @ 2016-12-14 0:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9b2f99ca-0ac6-12b0-e753-5ce6feec96e8@suse.com>
On Wed, 14 Dec 2016, Michal Marek wrote:
> Dne 8.12.2016 v 05:24 Nicolas Pitre napsal(a):
> > Rather than having an asm-prototypes.h file where C prototypes for exported
> > asm symbols are centralized, let's have some macros that can be used
> > directly in the code where those symbols are exported for genksyms
> > consumption. Either the prototype is provided directly if no include
> > files has it, or the include file containing it is specified.
> >
> > Signed-off-by: Nicolas Pitre <nico@linaro.org>
> > ---
> > include/asm-generic/export.h | 15 +++++++++++++++
> > scripts/Makefile.build | 22 +++++++++++++++-------
> > 2 files changed, 30 insertions(+), 7 deletions(-)
> >
> > diff --git a/include/asm-generic/export.h b/include/asm-generic/export.h
> > index 39a19dc366..83dda5f840 100644
> > --- a/include/asm-generic/export.h
> > +++ b/include/asm-generic/export.h
> > @@ -84,11 +84,26 @@ KSYM(__kcrctab_\name):
> > #define __EXPORT_SYMBOL(sym, val, sec) ___EXPORT_SYMBOL sym, val, sec
> > #endif
> >
> > +/* in the non genksyms case those are no-ops */
> > +#define SYMBOL_CPROTO(expr)
> > +#define SYMBOL_CPROTO_INCLUDE(file)
>
> Do we really _need_ the SYMBOL_CPROTO macro? The exported functions are
> called from C files presumably, so there ought to be headers with the
> declarations. If these headers can't be included easily, we should fix
> them, but having copies of the declarations in the asm files is no big
> improvement over the asm-prototypes.h approach, IMO.
On ARM there are a few symbols that are part of the gcc support library
such as division routines and so on. Those are never called directly
from C code. It is the compiler that implicitly creates references to
them. However, in order to be able to export those symbols, dummy C
prototypes were used before it was possible to export symbols from asm
code but those prototypes make no sense otherwise. So the SYMBOL_CPROTO
macro is there mainly to maintain backward compatibility with the
traditional symbol version signature for those symbols.
The SYMBOL_CPROTO macro, being close to the actual code, could mark the
intended definition for symbols in assembly code and allow for a tool to
ensure there is no mismatch with the actual declaration located
elsewhere. That could be useful for all global symbols, not just
exported ones. But that's not the primary reason why I created it.
Nicolas
^ permalink raw reply
* [PATCHv4 00/15] clk: ti: add support for hwmod clocks
From: Tony Lindgren @ 2016-12-14 0:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <148166654419.37646.7680435609801736363@resonance>
* Michael Turquette <mturquette@baylibre.com> [161213 14:02]:
> Quoting Tony Lindgren (2016-12-13 07:37:24)
> > For the clkctrl clocks, here's what I'd like to see. The driver should be
> > just a regular device driver along the lines we did with the ADPLL as in
> > Documentation/devicetree/bindings/clock/ti/adpll.txt.
> >
> > For the binding, something like the following should work as a minimal
> > example, this follows what we have in the hardware:
> >
> > &prm {
> > ...
> >
> > /* See "CD_WKUP Clock Domain" in 4430 TRM page 393 */
> > wkup_cm: clock at 1800 {
> > compatible = "ti,clkctrl";
> > reg = <0x1800 0x100>;
> > #clock-cells = <1>;
> > clocks = <&wkup_l4_iclk2 &wkup_32k_fclk
> > &32k_fclk &gp1_fclk>;
> > clock-output-names =
> > "sysctrl_padconf_wkup",
> > "badgap",
> > "sysctrl_general_wkup",
> > "gpio1",
> > "keyboard",
> > "sar_ram",
> > "32ktimer",
> > "gptimer1";
>
> Is there a technical reason to use clock-output-names? If you share a
> header between the clock provider driver and DT with the phandle offsets
> then we should be able to avoid this property altogether. Stephen and I
> are trying to phase this one out as much as possible.
Oh OK no reason for names, defines for the offsets will work just fine.
Regards,
Tony
^ permalink raw reply
* [linux-sunxi] Re: [PATCH v3 -next 2/2] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Alexey Kardashevskiy @ 2016-12-13 23:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161207100132.1Qp0ZxGD@smtp3o.mail.yandex.net>
On 07/12/16 18:01, Icenowy Zheng wrote:
>
> 2016?12?7? 05:52? Alexey Kardashevskiy <aik@ozlabs.ru>???
>>
>> On 06/12/16 18:43, Icenowy Zheng wrote:
>>>
>>> 2016?12?6? 09:51? Alexey Kardashevskiy <aik@ozlabs.ru>???
>>>>
>>>> On 03/12/16 02:05, Icenowy Zheng wrote:
>>>>> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC and a
>>>>> SDIO Wi-Fi chip by Allwinner (XR819).
>>>>>
>>>>> Add a device tree file for it.
>>>>>
>>>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>>>>> ---
>>>>> Changes since v2:
>>>>> - Merged SDIO Wi-Fi patch into it.
>>>>> - SDIO Wi-Fi: add a ethernet1 alias to it, as it has no internal NVRAM.
>>>>> - SDIO Wi-Fi: changed pinctrl binding to generic pinconf
>>>>> - removed all gpio pinctrl nodes
>>>>> - changed h2plus to h2-plus
>>>>> Changes since v1:
>>>>> - Convert to generic pinconf bindings.
>>>>> - SDIO Wi-Fi: add patch.
>>>>>
>>>>> Some notes:
>>>>> - The uart1 and uart2 is available on the unsoldered gpio header.
>>>>> - The onboard USB connector has its Vbus directly connected to DCIN-5V (the
>>>>> power jack)
>>>>>
>>>>> arch/arm/boot/dts/Makefile | 1 +
>>>>> arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 159 ++++++++++++++++++++++
>>>>> 2 files changed, 160 insertions(+)
>>>>> create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>>>> index 6447abc..59f6e86 100644
>>>>> --- a/arch/arm/boot/dts/Makefile
>>>>> +++ b/arch/arm/boot/dts/Makefile
>>>>> @@ -844,6 +844,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>>>>> sun8i-a33-sinlinx-sina33.dtb \
>>>>> sun8i-a83t-allwinner-h8homlet-v2.dtb \
>>>>> sun8i-a83t-cubietruck-plus.dtb \
>>>>> + sun8i-h2-plus-orangepi-zero.dtb \
>>>>> sun8i-h3-bananapi-m2-plus.dtb \
>>>>> sun8i-h3-nanopi-neo.dtb \
>>>>> sun8i-h3-orangepi-2.dtb \
>>>>> diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
>>>>> new file mode 100644
>>>>> index 0000000..d18807f
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
>>>>> @@ -0,0 +1,159 @@
>>>>> +/*
>>>>> + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
>>>>> + *
>>>>> + * Based on sun8i-h3-orangepi-one.dts, which is:
>>>>> + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
>>>>> + *
>>>>> + * This file is dual-licensed: you can use it either under the terms
>>>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>>>> + * licensing only applies to this file, and not this project as a
>>>>> + * whole.
>>>>> + *
>>>>> + * a) This file is free software; you can redistribute it and/or
>>>>> + * modify it under the terms of the GNU General Public License as
>>>>> + * published by the Free Software Foundation; either version 2 of the
>>>>> + * License, or (at your option) any later version.
>>>>> + *
>>>>> + * This file is distributed in the hope that it will be useful,
>>>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>>>> + * GNU General Public License for more details.
>>>>> + *
>>>>> + * Or, alternatively,
>>>>> + *
>>>>> + * b) Permission is hereby granted, free of charge, to any person
>>>>> + * obtaining a copy of this software and associated documentation
>>>>> + * files (the "Software"), to deal in the Software without
>>>>> + * restriction, including without limitation the rights to use,
>>>>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>>>>> + * sell copies of the Software, and to permit persons to whom the
>>>>> + * Software is furnished to do so, subject to the following
>>>>> + * conditions:
>>>>> + *
>>>>> + * The above copyright notice and this permission notice shall be
>>>>> + * included in all copies or substantial portions of the Software.
>>>>> + *
>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>>>> + */
>>>>> +
>>>>> +/dts-v1/;
>>>>> +#include "sun8i-h3.dtsi"
>>>>> +#include "sunxi-common-regulators.dtsi"
>>>>> +
>>>>> +#include <dt-bindings/gpio/gpio.h>
>>>>> +#include <dt-bindings/input/input.h>
>>>>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>>>>> +
>>>>> +/ {
>>>>> + model = "Xunlong Orange Pi Zero";
>>>>> + compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2-plus";
>>>>> +
>>>>> + aliases {
>>>>> + serial0 = &uart0;
>>>>> + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
>>>>
>>>>
>>>> It is not defined there as for:
>>>>
>>>> cef87e9 (tag: next-20161205) 20 hours ago Stephen Rothwell Add linux-next
>>>> specific files for 20161205
>>>
>>> The driver of H3's obfuscated DesignWare MAC is not yet mainlined, so there won't be one ethernet0 now.
>>>
>>> But it's reserved for the onboard Ethernet.
>>
>>
>> Could you please elaborate how you tested this patch (ideally some tree
>> somewhere on github)? This patch added RX819, it assumes EMAC support is
>> there, neither is there nor there is a way to test this... Thanks.
>
> It do not assume EMAC is there.
> It only assume EMAC will be there someday :-)
>
> For tree... wait for my push :-)
Has it happened yet? :)
--
Alexey
^ permalink raw reply
* [PATCH 2/2] kbuild: make modversion for exported asm symbols more convivial
From: Michal Marek @ 2016-12-13 23:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1481171047-333-3-git-send-email-nicolas.pitre@linaro.org>
Dne 8.12.2016 v 05:24 Nicolas Pitre napsal(a):
> Rather than having an asm-prototypes.h file where C prototypes for exported
> asm symbols are centralized, let's have some macros that can be used
> directly in the code where those symbols are exported for genksyms
> consumption. Either the prototype is provided directly if no include
> files has it, or the include file containing it is specified.
>
> Signed-off-by: Nicolas Pitre <nico@linaro.org>
> ---
> include/asm-generic/export.h | 15 +++++++++++++++
> scripts/Makefile.build | 22 +++++++++++++++-------
> 2 files changed, 30 insertions(+), 7 deletions(-)
>
> diff --git a/include/asm-generic/export.h b/include/asm-generic/export.h
> index 39a19dc366..83dda5f840 100644
> --- a/include/asm-generic/export.h
> +++ b/include/asm-generic/export.h
> @@ -84,11 +84,26 @@ KSYM(__kcrctab_\name):
> #define __EXPORT_SYMBOL(sym, val, sec) ___EXPORT_SYMBOL sym, val, sec
> #endif
>
> +/* in the non genksyms case those are no-ops */
> +#define SYMBOL_CPROTO(expr)
> +#define SYMBOL_CPROTO_INCLUDE(file)
Do we really _need_ the SYMBOL_CPROTO macro? The exported functions are
called from C files presumably, so there ought to be headers with the
declarations. If these headers can't be included easily, we should fix
them, but having copies of the declarations in the asm files is no big
improvement over the asm-prototypes.h approach, IMO.
Michal
^ permalink raw reply
* [PATCH 03/11] driver: clk: imx: Add clock driver for imx6sll
From: Stephen Boyd @ 2016-12-13 23:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AM3PR04MB5302BE33BE1F2C9913FF61587980@AM3PR04MB530.eurprd04.prod.outlook.com>
On 12/12, Jacky Bai wrote:
> > On 12/02, Bai Ping wrote:
> > > diff --git a/drivers/clk/imx/clk-imx6sll.c
> > > b/drivers/clk/imx/clk-imx6sll.c new file mode 100644 index
> > > 0000000..c5219e1
> > > --- /dev/null
> > > +++ b/drivers/clk/imx/clk-imx6sll.c
> > > +0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels),
> > > +CLK_SET_RATE_PARENT);
> > > +
> > > + /* Do not bypass PLLs initially */
> > > + clk_set_parent(clks[IMX6SLL_PLL1_BYPASS], clks[IMX6SLL_CLK_PLL1]);
> > > + clk_set_parent(clks[IMX6SLL_PLL2_BYPASS], clks[IMX6SLL_CLK_PLL2]);
> > > + clk_set_parent(clks[IMX6SLL_PLL3_BYPASS], clks[IMX6SLL_CLK_PLL3]);
> > > + clk_set_parent(clks[IMX6SLL_PLL4_BYPASS], clks[IMX6SLL_CLK_PLL4]);
> > > + clk_set_parent(clks[IMX6SLL_PLL5_BYPASS], clks[IMX6SLL_CLK_PLL5]);
> > > + clk_set_parent(clks[IMX6SLL_PLL6_BYPASS], clks[IMX6SLL_CLK_PLL6]);
> > > + clk_set_parent(clks[IMX6SLL_PLL7_BYPASS], clks[IMX6SLL_CLK_PLL7]);
> >
> > Can we just put raw register writes here instead? I'd prefer we didn't use clk
> > consumer APIs to do things to the clk tree from the providers. The problem
> > there being that:
> >
> > 1) We're trying to move away from using consumer APIs in provider drivers.
> > It's ok if they're used during probe, but inside clk_ops is not preferred.
> >
> > 2) Even if you have a clk pointer, it may be "orphaned" at the time of
> > registration and so calling the APIs here works now but eventually we may
> > want to return an EPROBE_DEFER error in that case and this may block that
> > effort.
> >
> > I suppose if this is the only clk driver on this machine then this last point isn't a
> > concern and things are probably ok here.
> >
>
> Using raw register writing has an issue. The register is modified, but it seems the clock 'parent-child' relationship can
> not match the register setting. The register setting is not bypass the pll, but in debug 'clk_summary', the
> pll is bypassed.
So program the register settings before registering the clocks
with the framework?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [GIT PULL] arm64 updates for 4.10
From: Stephen Rothwell @ 2016-12-13 23:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213192156.GA12471@e104818-lin.cambridge.arm.com>
Hi Linus,
On Tue, 13 Dec 2016 19:21:59 +0000 Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> Please pull the arm64 updates for 4.10 below.
>
> The patches touch the generic include/linux/thread_info.h to factor out
> struct restart_block into a separate include/linux/restart_block.h file
> (needed for arm64 moving thread_info off stack; acked by Andy
> Lutomirski).
>
> There is also a small refactoring touching drivers/irqchip/irq-gic-v3.c
> and additional watchpoint lengths added to
> include/uapi/linux/hw_breakpoint.h.
I have also been carrying a merge fix up patch due to a conflict in the
merge of the arm64 tree with commit
272d01bd790f ("arm64: Fix circular include of asm/lse.h through linux/jump_label.h")
from v4.9-rc5:
From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Tue, 22 Nov 2016 10:30:40 +1100
Subject: [PATCH] arm64: merge fix for code movement to cpucaps.h
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 87b446535185..4174f09678c4 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -34,7 +34,8 @@
#define ARM64_HAS_32BIT_EL0 13
#define ARM64_HYP_OFFSET_LOW 14
#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15
+#define ARM64_HAS_NO_FPSIMD 16
-#define ARM64_NCAPS 16
+#define ARM64_NCAPS 17
#endif /* __ASM_CPUCAPS_H */
--
2.10.2
--
Cheers,
Stephen Rothwell
^ permalink raw reply related
* [PATCH 1/2] arm64: setup: introduce kaslr_offset()
From: Alexander Popov @ 2016-12-13 22:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161212112914.GC21248@arm.com>
On 12.12.2016 14:29, Will Deacon wrote:
> On Sun, Dec 11, 2016 at 03:50:55AM +0300, Alexander Popov wrote:
>> Introduce kaslr_offset() similarly to x86_64 for fixing kcov.
>>
>> Signed-off-by: Alexander Popov <alex.popov@linux.com>
>> ---
>> arch/arm64/include/asm/setup.h | 19 +++++++++++++++++++
>> arch/arm64/include/uapi/asm/setup.h | 4 ++--
>> arch/arm64/kernel/setup.c | 8 ++++----
>> 3 files changed, 25 insertions(+), 6 deletions(-)
>> create mode 100644 arch/arm64/include/asm/setup.h
>
> You could probably just stick this in asm/memory.h, since that's where
> kimage_vaddr is declared and it would save adding a new header file.
Thanks, Will. I'll do that.
--
Alexander
^ permalink raw reply
* [PATCHv4 00/15] clk: ti: add support for hwmod clocks
From: Michael Turquette @ 2016-12-13 22:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213153724.GT4920@atomide.com>
Quoting Tony Lindgren (2016-12-13 07:37:24)
> * Tero Kristo <t-kristo@ti.com> [161213 00:31]:
> > On 13/12/16 06:40, Michael Turquette wrote:
> > > Quoting Tony Lindgren (2016-12-12 17:31:34)
> > > > * Stephen Boyd <sboyd@codeaurora.org> [161212 16:49]:
> > > > > I spent a bunch of time looking at this again today. From a DT
> > > > > perspective we don't want to have clocks or clockdomains nodes
> > > > > below the cm1/cm2/prm dt nodes. That's getting to the point of
> > > > > describing individual elements of a device that should be
> > > > > described in the driver instead of DT.
> > > >
> > > > I agree we don't need separate clocks and clockdomain nodes.. But
> > > > I think you're missing something here though. The clockdomains in
> > > > this case are separate devices on the interconnect, not individual
> > > > elements within a device. The outputs of a clockdomain are individual
> > > > elements of a clockdomain and can be just described as indexed
> > > > outputs of the clockdomain.
> > >
> > > Is the goal to describe this hardware topology in DT? Is that right
> > > thing to do? I think it's cool to have this modeled *somehow* in Linux,
> > > but I'm not sure DT is the right place to model the interconnect and
> > > every device hanging off of it.
>
> Well struct device is what we should use, the DT nodes pretty much
> map with that :)
>
> > > I don't want to put words in Stephen's mouth, but I think the issue over
> > > whether clockdomains are CCF clock providers or some genpd thing is
> > > probably less important to him than the fact that the DT bindings are
> > > super detailed to inner workings of the SoC.
> >
> > Ok, so your preference would be to reduce the data under DT, and the ideal
> > approach would be a single prcm node. I think we still need to keep the prm
> > / cm1 / cm2 as separate nodes, as they are pretty individual from hardware
> > point of view, provide quite different features, and they reside in some
> > cases in quite different address spaces also. Anyway, here's what I gather
> > we should probably have in DT:
> >
> > - reset provider
> > * example: resets = <&prm OMAP4_IVA2_RESET>;
> > * only from 'prm' node
> >
> > - genpd provider (for the hwmods, clockdomains, powerdomains, voltage
> > domains)
> > * examples: power-domains = <&cm2 OMAP4_DSS_CORE_MOD>;
> > power-domains = <&cm2 OMAP4_DSS_CLKDM>;
> > power-domains = <&prm OMAP4_DSS_PWRDM>;
> > power-domains = <&prm OMAP4_CORE_VOLTDM>;
> > * from all 'prm', 'cm1' and 'cm2' nodes, though 'prm' would be the only
> > one providing _CLKDM, _PWRDM, _VOLTDM genpds.
> >
> > - clock provider (for anything that requires clocks)
> > * example: clocks = <&cm1 OMAP4_DPLL_MPU_CK>;
> > * from all 'prm', 'cm1' and 'cm2' nodes
>
> Makes sense to me in general.
>
> For the clkctrl clocks, here's what I'd like to see. The driver should be
> just a regular device driver along the lines we did with the ADPLL as in
> Documentation/devicetree/bindings/clock/ti/adpll.txt.
>
> For the binding, something like the following should work as a minimal
> example, this follows what we have in the hardware:
>
> &prm {
> ...
>
> /* See "CD_WKUP Clock Domain" in 4430 TRM page 393 */
> wkup_cm: clock at 1800 {
> compatible = "ti,clkctrl";
> reg = <0x1800 0x100>;
> #clock-cells = <1>;
> clocks = <&wkup_l4_iclk2 &wkup_32k_fclk
> &32k_fclk &gp1_fclk>;
> clock-output-names =
> "sysctrl_padconf_wkup",
> "badgap",
> "sysctrl_general_wkup",
> "gpio1",
> "keyboard",
> "sar_ram",
> "32ktimer",
> "gptimer1";
Is there a technical reason to use clock-output-names? If you share a
header between the clock provider driver and DT with the phandle offsets
then we should be able to avoid this property altogether. Stephen and I
are trying to phase this one out as much as possible.
Regards,
Mike
> };
> ...
>
> /* See "CD_EMU Clock Domain" in 4430 TRM page 424 */
> emu_cm: clock at 1a00 {
> compatible = "ti,clkctrl";
> reg = <0x1a00 0x100>;
> #clock-cells = <1>;
> clocks = <&emu_sys_clk &core_dpll_emu_clk>;
> clock-output-names = "debug";
> };
> ...
> };
>
> So the device tree nodes could be minimal as above and the rest can
> be taken care of by the driver. We may need separate compatible strings
> for the various instances, not sure about that.
>
> Note that the clkctrl hardware manages multiple clocks for each
> interconnect target module. AFAIK we don't need to care about that from
> the consumer device driver point of view as it can't separately manage
> functional and interface clock.
>
> We need few clockctrl clocks early for system timers, but those can
> be registered earlier in the driver.
>
> Then some clkctrl clocks have optional aux clocks. I think those can
> be just be regular child clocks of the module clocks.
>
> > This would eventually cause an ABI breakage for the clock handles, if we
> > transfer the existing clocks to this format, and remove the existing clock
> > handles from DT. Otherwise, I think we could just transition the existing
> > hwmod data to this new format only, and add the clockdomain / powerdomain /
> > voltagedomain support a bit later.
>
> Let's not break anything while doing this.. And let's not mess with the
> hwmod except where it helps moving that into regular device drivers.
> If necessary we can maybe first register the new clock instances, then
> register the old clocks if new clock is not found?
>
> Regards,
>
> Tony
^ permalink raw reply
* [PATCH v3] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller
From: Jon Masters @ 2016-12-13 21:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161206201835.GA19700@bhelgaas-glaptop.roam.corp.google.com>
On 12/06/2016 03:18 PM, Bjorn Helgaas wrote:
> I just merged pci/ecam into my "next" branch, so as long as tomorrow's
> linux-next boots out of the box, we should be set. I made the following
> changes compared to v11:
>
> - dropped the x86 change to use acpi_resource_consumer()
> - added parens around macro args used in arithmetic expressions
> - renamed "seg" to "node" in THUNDER_PEM_RES and THUNDER_PEM_QUIRK
> - incorporated (u64) cast and dropped "UL" postfix for THUNDER_PEM_QUIRK
>
> Let me know if you see any issues.
Just following up. Please find attached a boot log from an HPE ProLiant m400
Moonshot X-Gene based cartridge running next-20161213 with pci/ecam branch.
Here is the /proc/iomem output as well:
# cat /proc/iomem
10520000-10523fff : APMC0D18:00
10520000-10523fff : APMC0D18:00
10524000-10527fff : APMC0D17:00
10540000-1054a0ff : APMC0D01:00
10546000-10546fff : APMC0D50:00
1054a000-1054a00f : APMC0D12:03
1054a000-1054a00f : APMC0D12:02
1054a000-1054a00f : APMC0D12:01
1054a000-1054a00f : APMC0D12:00
17000000-17000fff : APMC0D01:00
17001000-17001fff : APMC0D01:00
17001000-170013ff : APMC0D15:00
17001000-170013ff : APMC0D15:00
1701c000-1701cfff : APMC0D14:00
1a800000-1a800fff : APMC0D0D:00
1a800000-1a800fff : APMC0D0D:00
1c000200-1c0002ff : APMC0D06:00
1c021000-1c0210ff : APMC0D08:00
1c021000-1c02101f : serial
1c024000-1c024fff : APMC0D07:00
1f230000-1f230fff : APMC0D0D:00
1f230000-1f230fff : APMC0D0D:00
1f23d000-1f23dfff : APMC0D0D:00
1f23d000-1f23dfff : APMC0D0D:00
1f23e000-1f23efff : APMC0D0D:00
1f23e000-1f23efff : APMC0D0D:00
1f2a0000-1f31ffff : APMC0D06:00
1f500000-1f50ffff : PNP0A08:00
78800000-78800fff : APMC0D13:00
78800000-78800fff : APMC0D12:03
78800000-78800fff : APMC0D12:02
78800000-78800fff : APMC0D12:01
78800000-78800fff : APMC0D12:00
78800000-78800fff : APMC0D11:00
78800000-78800fff : APMC0D10:03
78800000-78800fff : APMC0D10:02
78800000-78800fff : APMC0D10:01
78800000-78800fff : APMC0D10:00
79000000-798fffff : APMC0D0E:00
7c000000-7c1fffff : APMC0D12:00
7c200000-7c3fffff : APMC0D12:01
7c400000-7c5fffff : APMC0D12:02
7c600000-7c7fffff : APMC0D12:03
7e000000-7e000fff : APMC0D13:00
7e200000-7e200fff : APMC0D10:03
7e200000-7e200fff : APMC0D10:02
7e200000-7e200fff : APMC0D10:01
7e200000-7e200fff : APMC0D10:00
7e600000-7e600fff : APMC0D11:00
7e700000-7e700fff : APMC0D10:03
7e700000-7e700fff : APMC0D10:02
7e700000-7e700fff : APMC0D10:01
7e700000-7e700fff : APMC0D10:00
7e720000-7e720fff : APMC0D10:03
7e720000-7e720fff : APMC0D10:02
7e720000-7e720fff : APMC0D10:01
7e720000-7e720fff : APMC0D10:00
7e800000-7e800fff : APMC0D10:00
7e840000-7e840fff : APMC0D10:01
7e880000-7e880fff : APMC0D10:02
7e8c0000-7e8c0fff : APMC0D10:03
7e930000-7e930fff : APMC0D13:00
4000000000-4001ffffff : System RAM
4000080000-4000c9ffff : Kernel code
4000e20000-400171ffff : Kernel data
40023a0000-4ff733ffff : System RAM
4ff7340000-4ff77cffff : reserved
4ff77d0000-4ff79cffff : System RAM
4ff79d0000-4ff7e7ffff : reserved
4ff7e80000-4ff7e8ffff : System RAM
4ff7e90000-4ff7efffff : reserved
4ff7f10000-4ff800ffff : reserved
4ff8010000-4fffffffff : System RAM
a020000000-a03fffffff : PCI Bus 0000:00
a020000000-a0201fffff : PCI Bus 0000:01
a020000000-a0200fffff : 0000:01:00.0
a020000000-a0200fffff : mlx4_core
a020100000-a0201fffff : 0000:01:00.0
a060000000-a07fffffff : PCI Bus 0000:00
a0d0000000-a0dfffffff : PCI ECAM
a110000000-a14fffffff : PCI Bus 0000:00
a110000000-a121ffffff : PCI Bus 0000:01
a110000000-a111ffffff : 0000:01:00.0
a110000000-a111ffffff : mlx4_core
a112000000-a121ffffff : 0000:01:00.0
Thanks again, Bjorn. Looking forward to seeing this upstream.
Tested-by: Jon Masters <jcm@redhat.com>
--
Computer Architect | Sent from my Fedora powered laptop
-------------- next part --------------
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.9.0-next-20161213.next20161213_jcm1 (root at hp-moonshot-02-c08.khw.lab.eng.bos.redhat.com) (gcc version 4.8.5 20150623 (Red Hat 4.8.5-11) (GCC) ) #1 SMP Tue Dec 13 15:42:15 EST 2016
[ 0.000000] Boot CPU: AArch64 Processor [500f0001]
[ 0.000000] earlycon: uart8250 at MMIO32 0x000000001c021000 (options '')
[ 0.000000] bootconsole [uart8250] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: EFI v2.60 by HPE
[ 0.000000] efi: ACPI 2.0=0x4ff8000000 SMBIOS 3.0=0x4ff7a90000 MEMATTR=0x4ff2410698 RNG=0x4ff7e7f518
[ 0.000000] cma: Reserved 512 MiB at 0x00000040e0000000
[ 0.000000] ACPI: Early table checksum verification disabled
[ 0.000000] ACPI: RSDP 0x0000004FF8000000 000024 (v02 HP )
[ 0.000000] ACPI: XSDT 0x0000004FF7FF0000 000084 (v01 HP ProLiant 00000001 01000013)
[ 0.000000] ACPI: FACP 0x0000004FF7FB0000 000114 (v06 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: DSDT 0x0000004FF7F80000 0023CA (v05 HPE DSDT 00000001 INTL 20160527)
[ 0.000000] ACPI: SSDT 0x0000004FF7FE0000 000032 (v02 HPE UARTCLKS 00000001 01000013)
[ 0.000000] ACPI: BERT 0x0000004FF7FD0000 000030 (v01 HPE ProLiant 00000002 INTL 20160527)
[ 0.000000] ACPI: HEST 0x0000004FF7FC0000 0002A8 (v01 HPE ProLiant 00000002 INTL 20160527)
[ 0.000000] ACPI: DBG2 0x0000004FF7FA0000 0000A8 (v00 HPE ProLiant 00000000 INTL 20160527)
[ 0.000000] ACPI: GTDT 0x0000004FF7F90000 0000E0 (v02 HPE ProLiant 00000001 INTL 20160527)
[ 0.000000] ACPI: APIC 0x0000004FF7F70000 0002C4 (v03 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: MCFG 0x0000004FF7F60000 00003C (v01 APM XGENE 00000001 HP 00000001)
[ 0.000000] ACPI: SPMI 0x0000004FF7F50000 000041 (v05 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: RASF 0x0000004FF7F40000 000030 (v01 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: SPCR 0x0000004FF7F30000 000050 (v02 HPE ProLiant 00000001 HP 00000001)
[ 0.000000] ACPI: SSDT 0x0000004FF7F20000 000313 (v02 HPE PCISSDT 00000002 HPAG 00020000)
[ 0.000000] ACPI: SPCR: console: uart,mmio,0x1c021000,9600
[ 0.000000] ACPI: NUMA: Failed to initialise from firmware
[ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x0000004fffffffff]
[ 0.000000] NUMA: Adding memblock [0x4000000000 - 0x4001ffffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x40023a0000 - 0x4ff733ffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff7340000 - 0x4ff77cffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff77d0000 - 0x4ff79cffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff79d0000 - 0x4ff7e7ffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff7e80000 - 0x4ff7e8ffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff7e90000 - 0x4ff7efffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff7f10000 - 0x4ff800ffff] on node 0
[ 0.000000] NUMA: Adding memblock [0x4ff8010000 - 0x4fffffffff] on node 0
[ 0.000000] NUMA: Initmem setup node 0 [mem 0x4000000000-0x4fffffffff]
[ 0.000000] NUMA: NODE_DATA [mem 0x4fffff2680-0x4fffffffff]
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000004000000000-0x00000040ffffffff]
[ 0.000000] Normal [mem 0x0000004100000000-0x0000004fffffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000004000000000-0x0000004001ffffff]
[ 0.000000] node 0: [mem 0x00000040023a0000-0x0000004ff733ffff]
[ 0.000000] node 0: [mem 0x0000004ff7340000-0x0000004ff77cffff]
[ 0.000000] node 0: [mem 0x0000004ff77d0000-0x0000004ff79cffff]
[ 0.000000] node 0: [mem 0x0000004ff79d0000-0x0000004ff7e7ffff]
[ 0.000000] node 0: [mem 0x0000004ff7e80000-0x0000004ff7e8ffff]
[ 0.000000] node 0: [mem 0x0000004ff7e90000-0x0000004ff7efffff]
[ 0.000000] node 0: [mem 0x0000004ff7f10000-0x0000004ff800ffff]
[ 0.000000] node 0: [mem 0x0000004ff8010000-0x0000004fffffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000004000000000-0x0000004fffffffff]
[ 0.000000] On node 0 totalpages: 1048517
[ 0.000000] DMA zone: 64 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 65478 pages, LIFO batch:1
[ 0.000000] Normal zone: 960 pages used for memmap
[ 0.000000] Normal zone: 983039 pages, LIFO batch:1
[ 0.000000] psci: is not implemented in ACPI.
[ 0.000000] percpu: Embedded 3 pages/cpu @fffffe0fffdd0000 s117248 r8192 d71168 u196608
[ 0.000000] pcpu-alloc: s117248 r8192 d71168 u196608 alloc=3*65536
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7
[ 0.000000] Detected PIPT I-cache on CPU0
[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 1047493
[ 0.000000] Policy zone: Normal
[ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-4.9.0-next-20161213.next20161213_jcm1 root=/dev/mapper/rhel_hp--moonshot--02--c08-root ro crashkernel=auto rd.lvm.lv=rhel_hp-moonshot-02-c08/root rd.lvm.lv=rhel_hp-moonshot-02-c08/swap LANG=en_US.UTF-8 acpi=on earlycon=uart8250,mmio32,0x1c021000 console=ttyS0,9600
[ 0.000000] PID hash table entries: 4096 (order: -1, 32768 bytes)
[ 0.000000] software IO TLB [mem 0x40dbff0000-0x40dfff0000] (64MB) mapped at [fffffe00dbff0000-fffffe00dffeffff]
[ 0.000000] Memory: 66377408K/67105088K available (8572K kernel code, 1626K rwdata, 3776K rodata, 1536K init, 7219K bss, 203392K reserved, 524288K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] modules : 0xfffffc0000000000 - 0xfffffc0008000000 ( 128 MB)
[ 0.000000] vmalloc : 0xfffffc0008000000 - 0xfffffdff5fff0000 ( 2045 GB)
[ 0.000000] .text : 0xfffffc0008080000 - 0xfffffc00088e0000 ( 8576 KB)
[ 0.000000] .rodata : 0xfffffc00088e0000 - 0xfffffc0008ca0000 ( 3840 KB)
[ 0.000000] .init : 0xfffffc0008ca0000 - 0xfffffc0008e20000 ( 1536 KB)
[ 0.000000] .data : 0xfffffc0008e20000 - 0xfffffc0008fb6a00 ( 1627 KB)
[ 0.000000] .bss : 0xfffffc0008fb6a00 - 0xfffffc00096c38d0 ( 7220 KB)
[ 0.000000] fixed : 0xfffffdff7e7d0000 - 0xfffffdff7ec00000 ( 4288 KB)
[ 0.000000] PCI I/O : 0xfffffdff7ee00000 - 0xfffffdff7fe00000 ( 16 MB)
[ 0.000000] vmemmap : 0xfffffdff80000000 - 0xfffffe0000000000 ( 2 GB maximum)
[ 0.000000] 0xfffffdff80000000 - 0xfffffdff84000000 ( 64 MB actual)
[ 0.000000] memory : 0xfffffe0000000000 - 0xfffffe1000000000 ( 65536 MB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 64.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4096 to nr_cpu_ids=8.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=8
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] arm_arch_timer: Architected cp15 timer(s) running at 50.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0xb8812736b, max_idle_ns: 440795202655 ns
[ 0.000002] sched_clock: 56 bits at 50MHz, resolution 20ns, wraps every 4398046511100ns
[ 0.095859] Console: colour dummy device 80x25
[ 0.149059] Calibrating delay loop (skipped), value calculated using timer frequency.. 100.00 BogoMIPS (lpj=50000)
[ 0.273029] pid_max: default: 32768 minimum: 301
[ 0.328350] ACPI: Core revision 20160930
[ 0.377378] ACPI: 3 ACPI AML tables successfully acquired and loaded
[ 0.453514] Security Framework initialized
[ 0.502501] Yama: becoming mindful.
[ 0.544208] SELinux: Initializing.
[ 0.586151] SELinux: Starting in permissive mode
[ 0.586902] Dentry cache hash table entries: 8388608 (order: 10, 67108864 bytes)
[ 0.686317] Inode-cache hash table entries: 4194304 (order: 9, 33554432 bytes)
[ 0.778042] Mount-cache hash table entries: 131072 (order: 4, 1048576 bytes)
[ 0.862396] Mountpoint-cache hash table entries: 131072 (order: 4, 1048576 bytes)
[ 0.952631] ftrace: allocating 31238 entries in 8 pages
[ 1.040528] ASID allocator initialised with 65536 entries
[ 1.105893] Remapping and enabling EFI services.
[ 1.161155] EFI remap 0x0000000010510000 => 0000000020000000
[ 1.230941] EFI remap 0x0000000010548000 => 0000000020018000
[ 1.300723] EFI remap 0x0000000017000000 => 0000000020020000
[ 1.370507] EFI remap 0x000000001c024000 => 0000000020034000
[ 1.440187] EFI remap 0x000000001f2a0000 => 0000000020040000
[ 1.509867] EFI remap 0x0000004002310000 => 0000000020050000
[ 1.579547] EFI remap 0x0000004ff7340000 => 00000000200b0000
[ 1.649331] EFI remap 0x0000004ff79d0000 => 0000000020540000
[ 1.719184] smp: Bringing up secondary CPUs ...
[ 1.773561] Detected PIPT I-cache on CPU1
[ 1.773591] CPU1: Booted secondary processor [500f0001]
[ 1.773810] Detected PIPT I-cache on CPU2
[ 1.773831] CPU2: Booted secondary processor [500f0001]
[ 1.774052] Detected PIPT I-cache on CPU3
[ 1.774065] CPU3: Booted secondary processor [500f0001]
[ 1.774263] Detected PIPT I-cache on CPU4
[ 1.774283] CPU4: Booted secondary processor [500f0001]
[ 1.774502] Detected PIPT I-cache on CPU5
[ 1.774516] CPU5: Booted secondary processor [500f0001]
[ 1.774715] Detected PIPT I-cache on CPU6
[ 1.774735] CPU6: Booted secondary processor [500f0001]
[ 1.774947] Detected PIPT I-cache on CPU7
[ 1.774960] CPU7: Booted secondary processor [500f0001]
[ 1.774998] smp: Brought up 1 node, 8 CPUs
[ 2.595763] SMP: Total of 8 processors activated.
[ 2.651925] CPU features: detected feature: 32-bit EL0 Support
[ 2.863045] CPU: All CPU(s) started at EL2
[ 2.912933] devtmpfs: initialized
[ 2.952981] SMBIOS 3.0.0 present.
[ 2.992611] DMI: HPE ProLiant m400 Server/ProLiant m400 Server, BIOS U02 06/25/2016
[ 3.084336] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
[ 3.201380] atomic64_test: passed
[ 3.241036] pinctrl core: initialized pinctrl subsystem
[ 3.303945] NET: Registered protocol family 16
[ 3.357675] cpuidle: using governor menu
[ 3.404583] PCCT header not found.
[ 3.445296] vdso: 2 pages (1 code @ fffffc0008900000, 1 data @ fffffc0008e40000)
[ 3.533818] hw-breakpoint: found 4 breakpoint and 4 watchpoint registers.
[ 3.615473] DMA: preallocated 256 KiB pool for atomic allocations
[ 3.688440] ACPI: bus type PCI registered
[ 3.736390] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[ 3.813544] Serial: AMBA PL011 UART driver
[ 3.865355] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 3.941388] HugeTLB registered 512 MB page size, pre-allocated 0 pages
[ 4.020035] ACPI: Added _OSI(Module Device)
[ 4.070067] ACPI: Added _OSI(Processor Device)
[ 4.123208] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 4.179473] ACPI: Added _OSI(Processor Aggregator Device)
[ 4.244129] ACPI: Executed 1 blocks of module-level executable AML code
[ 4.327259] ACPI: Interpreter enabled
[ 4.371051] ACPI: Using GIC for interrupt routing
[ 4.427339] ACPI: MCFG table detected, 1 entries
[ 4.485254] ACPI: Power Resource [SCVR] (off)
[ 4.540968] ACPI: PCI Root Bridge [PCI3] (domain 0000 [bus 00-ff])
[ 4.614943] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
[ 4.713012] acpi PNP0A08:00: _OSC: platform does not support [AER]
[ 4.787128] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME PCIeCapability]
[ 4.878780] acpi PNP0A08:00: MCFG quirk: ECAM at [mem 0xa0d0000000-0xa0dfffffff] for [bus 00-ff] with xgene_v1_pcie_ecam_ops
[ 5.013499] acpi PNP0A08:00: [Firmware Bug]: ECAM area [mem 0xa0d0000000-0xa0dfffffff] not reserved in ACPI namespace
[ 5.140522] acpi PNP0A08:00: ECAM at [mem 0xa0d0000000-0xa0dfffffff] for [bus 00-ff]
[ 5.233212] Remapped I/O 0x000000a100010000 to [io 0x0000-0xffff window]
[ 5.314538] PCI host bridge to bus 0000:00
[ 5.363532] pci_bus 0000:00: root bus resource [io 0x0000-0xffff window] (bus address [0x10000-0x1ffff])
[ 5.478041] pci_bus 0000:00: root bus resource [mem 0xa020000000-0xa03fffffff window] (bus address [0x20000000-0x3fffffff])
[ 5.611273] pci_bus 0000:00: root bus resource [mem 0xa060000000-0xa07fffffff window] (bus address [0x40000000-0x5fffffff])
[ 5.744502] pci_bus 0000:00: root bus resource [mem 0xa110000000-0xa14fffffff window]
[ 5.838210] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 5.903849] pci 0000:00:00.0: [10e8:e004] type 01 class 0x060400
[ 5.903922] pci 0000:00:00.0: supports D1 D2
[ 5.904276] pci 0000:01:00.0: [15b3:1007] type 00 class 0x020000
[ 5.904601] pci 0000:01:00.0: reg 0x10: [mem 0xa020000000-0xa0200fffff 64bit]
[ 5.904846] pci 0000:01:00.0: reg 0x18: [mem 0xa122000000-0xa123ffffff 64bit pref]
[ 5.905278] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x000fffff pref]
[ 5.907014] pci 0000:01:00.0: reg 0x134: [mem 0xa112000000-0xa113ffffff 64bit pref]
[ 5.907016] pci 0000:01:00.0: VF(n) BAR2 space: [mem 0xa112000000-0xa121ffffff 64bit pref] (contains BAR2 for 8 VFs)
[ 6.037078] pci_bus 0000:00: on NUMA node 0
[ 6.037098] pci 0000:00:00.0: BAR 15: assigned [mem 0xa110000000-0xa121ffffff 64bit pref]
[ 6.134970] pci 0000:00:00.0: BAR 14: assigned [mem 0xa020000000-0xa0201fffff]
[ 6.221401] pci 0000:01:00.0: BAR 2: assigned [mem 0xa110000000-0xa111ffffff 64bit pref]
[ 6.318379] pci 0000:01:00.0: BAR 9: assigned [mem 0xa112000000-0xa121ffffff 64bit pref]
[ 6.415273] pci 0000:01:00.0: BAR 0: assigned [mem 0xa020000000-0xa0200fffff 64bit]
[ 6.507043] pci 0000:01:00.0: BAR 6: assigned [mem 0xa020100000-0xa0201fffff pref]
[ 6.597633] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 6.657022] pci 0000:00:00.0: bridge window [mem 0xa020000000-0xa0201fffff]
[ 6.742414] pci 0000:00:00.0: bridge window [mem 0xa110000000-0xa121ffffff 64bit pref]
[ 6.839684] vgaarb: loaded
[ 6.872357] SCSI subsystem initialized
[ 6.917272] libata version 3.00 loaded.
[ 6.917319] ACPI: bus type USB registered
[ 6.965300] usbcore: registered new interface driver usbfs
[ 7.030944] usbcore: registered new interface driver hub
[ 7.094523] usbcore: registered new device driver usb
[ 7.154974] pps_core: LinuxPPS API ver. 1 registered
[ 7.214363] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 7.323672] PTP clock support registered
[ 7.370675] Registered efivars operations
[ 7.419358] NetLabel: Initializing
[ 7.460028] NetLabel: domain hash size = 128
[ 7.512133] NetLabel: protocols = UNLABELED CIPSOv4
[ 7.571547] NetLabel: unlabeled traffic allowed by default
[ 7.638361] clocksource: Switched to clocksource arch_sys_counter
[ 7.728243] VFS: Disk quotas dquot_6.6.0
[ 7.775223] VFS: Dquot-cache hash table entries: 8192 (order 0, 65536 bytes)
[ 7.859807] pnp: PnP ACPI init
[ 7.896705] pnp: PnP ACPI: found 0 devices
[ 8.091440] NET: Registered protocol family 2
[ 8.143915] TCP established hash table entries: 524288 (order: 6, 4194304 bytes)
[ 8.233776] TCP bind hash table entries: 65536 (order: 4, 1048576 bytes)
[ 8.314326] TCP: Hash tables configured (established 524288 bind 65536)
[ 8.393534] UDP hash table entries: 32768 (order: 4, 1048576 bytes)
[ 8.469053] UDP-Lite hash table entries: 32768 (order: 4, 1048576 bytes)
[ 8.549917] NET: Registered protocol family 1
[ 8.602063] PCI: CLS 64 bytes, default 128
[ 8.602177] Unpacking initramfs...
[ 9.396621] Freeing initrd memory: 35200K
[ 9.444989] kvm [1]: 8-bit VMID
[ 9.482540] kvm [1]: IDMAP page: 40008ce000
[ 9.532565] kvm [1]: HYP VA range: 20000000000:3ffffffffff
[ 9.598280] kvm [1]: Hyp mode initialized successfully
[ 9.659763] kvm [1]: GICV region size/alignment is unsafe, using trapping (reduced performance)
[ 9.763887] kvm [1]: vgic-v2 at 780cf000
[ 9.807757] kvm [1]: vgic interrupt IRQ1
[ 9.854665] kvm [1]: virtual timer IRQ4
[ 9.916744] futex hash table entries: 2048 (order: 2, 262144 bytes)
[ 9.991796] audit: initializing netlink subsys (disabled)
[ 10.056453] audit: type=2000 audit(6.770:1): initialized
[ 10.056630] Initialise system trusted keyrings
[ 10.056778] workingset: timestamp_bits=37 max_order=20 bucket_order=0
[ 10.059968] zbud: loaded
[ 10.061498] SELinux: Registering netfilter hooks
[ 10.135674] alg: acomp: Compression test 1 failed for lzo-scomp: output len = 27
[ 10.135777] alg: drbg: Test 0 failed for drbg_pr_ctr_aes128
[ 10.139874] alg: drbg: Test 0 failed for drbg_nopr_ctr_aes128
[ 10.139966] alg: drbg: Test 0 failed for drbg_nopr_ctr_aes192
[ 10.140039] alg: drbg: Test 0 failed for drbg_nopr_ctr_aes256
[ 10.141015] NET: Registered protocol family 38
[ 10.141020] Key type asymmetric registered
[ 10.141022] Asymmetric key parser 'x509' registered
[ 10.141066] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 248)
[ 10.141127] io scheduler noop registered
[ 10.141129] io scheduler deadline registered (default)
[ 10.141158] io scheduler cfq registered
[ 11.044288] xgene-gpio APMC0D14:00: X-Gene GPIO driver registered.
[ 11.118317] pcieport 0000:00:00.0: can't derive routing for PCI INT A
[ 11.195387] pcieport 0000:00:00.0: PCI INT A: no GSI
[ 11.254927] pcie_pme: probe of 0000:00:00.0:pcie001 failed with error -22
[ 11.336367] acpi ACPI0007:00: CPPC data invalid or not present
[ 11.406182] acpi ACPI0007:01: CPPC data invalid or not present
[ 11.475988] acpi ACPI0007:02: CPPC data invalid or not present
[ 11.545790] acpi ACPI0007:03: CPPC data invalid or not present
[ 11.615591] acpi ACPI0007:04: CPPC data invalid or not present
[ 11.685386] acpi ACPI0007:05: CPPC data invalid or not present
[ 11.755183] acpi ACPI0007:06: CPPC data invalid or not present
[ 11.824979] acpi ACPI0007:07: CPPC data invalid or not present
[ 11.895296] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
[ 11.985565] console [ttyS0] disabled
[ 12.048458] APMC0D08:00: ttyS0 at MMIO 0x1c021000 (irq = 23, base_baud = 3125000) is a U6_16550A
[ 12.153622] console [ttyS0] enabled
[ 12.237185] bootconsole [uart8250] disabled
[ 12.337600] msm_serial: driver initialized
[ 12.387004] cacheinfo: Unable to detect cache hierarchy for CPU 0
[ 12.460306] hisi_sas: driver version v1.6
[ 12.508614] xgene-ahci APMC0D0D:00: skip clock and PHY initialization
[ 12.585926] xgene-ahci APMC0D0D:00: controller can't do NCQ, turning off CAP_NCQ
[ 12.674726] xgene-ahci APMC0D0D:00: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl platform mode
[ 12.781242] xgene-ahci APMC0D0D:00: flags: 64bit sntf pm only pmp fbs pio slum part ccc
[ 12.878376] xgene-ahci APMC0D0D:00: port 0 is not capable of FBS
[ 12.950530] xgene-ahci APMC0D0D:00: port 1 is not capable of FBS
[ 13.023086] scsi host0: xgene-ahci
[ 13.064107] scsi host1: xgene-ahci
[ 13.104993] ata1: SATA max UDMA/133 mmio [mem 0x1a800000-0x1a800fff] port 0x100 irq 24
[ 13.200036] ata2: SATA max UDMA/133 mmio [mem 0x1a800000-0x1a800fff] port 0x180 irq 24
[ 13.295220] libphy: Fixed MDIO Bus: probed
[ 13.344622] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 13.423035] ehci-pci: EHCI PCI platform driver
[ 13.476382] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 13.550566] ohci-pci: OHCI PCI platform driver
[ 13.603485] ata2: SATA link down (SStatus 0 SControl 4300)
[ 13.669714] uhci_hcd: USB Universal Host Controller Interface driver
[ 13.746061] usbcore: registered new interface driver usbserial
[ 13.816074] usbcore: registered new interface driver usbserial_generic
[ 13.894431] usbserial: USB Serial support registered for generic
[ 13.918368] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 4300)
[ 13.918575] ata1.00: ATA-9: XR0120GEBLT, HPS4, max UDMA/133
[ 13.918577] ata1.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 0/32)
[ 13.918793] ata1.00: configured for UDMA/133
[ 13.919075] scsi 0:0:0:0: Direct-Access ATA XR0120GEBLT HPS4 PQ: 0 ANSI: 5
[ 14.337526] mousedev: PS/2 mouse device common for all mice
[ 14.337731] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 14.337813] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 14.337816] sd 0:0:0:0: [sda] 4096-byte physical blocks
[ 14.337844] sd 0:0:0:0: [sda] Write Protect is off
[ 14.337847] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 14.337878] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 14.340377] sda: sda1 sda2 sda3
[ 14.340976] sd 0:0:0:0: [sda] Attached SCSI disk
[ 14.882043] rtc-efi rtc-efi: rtc core: registered rtc-efi as rtc0
[ 14.955405] device-mapper: uevent: version 1.0.3
[ 15.010948] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel at redhat.com
[ 15.112879] EFI Variables Facility v0.08 2004-May-17
[ 15.173571] hidraw: raw HID events driver (C) Jiri Kosina
[ 15.238435] usbcore: registered new interface driver usbhid
[ 15.305312] usbhid: USB HID core driver
[ 15.351500] drop_monitor: Initializing network drop monitor service
[ 15.426836] ip_tables: (C) 2000-2006 Netfilter Core Team
[ 15.490607] Initializing XFRM netlink socket
[ 15.542068] NET: Registered protocol family 10
[ 15.595815] Segment Routing with IPv6
[ 15.639769] mip6: Mobile IPv6
[ 15.675345] NET: Registered protocol family 17
[ 15.728962] registered taskstats version 1
[ 15.778126] Loading compiled-in X.509 certificates
[ 15.838950] alg: No test for pkcs1pad(rsa,sha256) (pkcs1pad(rsa-generic,sha256))
[ 15.929166] Loaded X.509 cert 'Build time autogenerated kernel key: 1fab4053cdef4de1ccc5ce05e1cbfed5d5537af3'
[ 16.048260] zswap: loaded using pool lzo/zbud
[ 16.121521] Key type big_key registered
[ 16.167696] rtc-efi rtc-efi: setting system clock to 2016-12-13 21:36:35 UTC (1481664995)
[ 16.265895] PM: Hibernation image not present or could not be loaded.
[ 16.266097] Freeing unused kernel memory: 1536K
[ 16.326138] random: systemd: uninitialized urandom read (16 bytes read)
[ 16.406164] random: systemd: uninitialized urandom read (16 bytes read)
[ 16.487457] systemd[1]: systemd 219 running in system mode. (+PAM +AUDIT +SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID +ELFUTILS +KMOD +IDN)
[ 16.703839] systemd[1]: Detected architecture arm64.
[ 16.763425] systemd[1]: Running in initial RAM disk.
[ 16.933524] systemd[1]: Set hostname to <localhost.localdomain>.
[ 17.048780] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.128253] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.207713] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.287210] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.367813] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.447496] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.527253] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.607728] random: systemd: uninitialized urandom read (16 bytes read)
[ 17.742418] systemd[1]: Created slice Root Slice.
[ 17.798887] systemd[1]: Starting Root Slice.
[ 17.906399] systemd[1]: Listening on udev Kernel Socket.
[ 17.970171] systemd[1]: Starting udev Kernel Socket.
[ 18.086397] systemd[1]: Listening on udev Control Socket.
[ 18.151212] systemd[1]: Starting udev Control Socket.
[ 19.673565] mlx4_core: Mellanox ConnectX core driver v2.2-1 (Feb, 2014)
[ 19.789919] mlx4_core: Initializing 0000:01:00.0
[ 26.231135] mlx4_core 0000:01:00.0: PCIe BW is different than device's capability
[ 26.320967] mlx4_core 0000:01:00.0: PCIe link speed is 5.0GT/s, device supports 8.0GT/s
[ 26.417049] mlx4_core 0000:01:00.0: PCIe link width is x8, device supports x8
[ 26.564318] mlx4_en: Mellanox ConnectX HCA Ethernet driver v2.2-1 (Feb 2014)
[ 26.649193] mlx4_en 0000:01:00.0: Activating port:1
[ 26.711378] mlx4_en: 0000:01:00.0: Port 1: Using 64 TX rings
[ 26.779299] mlx4_en: 0000:01:00.0: Port 1: Using 4 RX rings
[ 26.846181] mlx4_en: 0000:01:00.0: Port 1: frag:0 - size:1522 prefix:0 stride:1536
[ 26.939499] mlx4_en: 0000:01:00.0: Port 1: Initializing port
[ 27.007785] mlx4_en 0000:01:00.0: registered PHC clock
[ 27.070877] mlx4_en 0000:01:00.0: Activating port:2
[ 27.133993] mlx4_en: 0000:01:00.0: Port 2: Using 64 TX rings
[ 27.201915] mlx4_en: 0000:01:00.0: Port 2: Using 4 RX rings
[ 27.268798] mlx4_en: 0000:01:00.0: Port 2: frag:0 - size:1522 prefix:0 stride:1536
[ 27.362021] mlx4_en: 0000:01:00.0: Port 2: Initializing port
[ 27.434754] mlx4_core 0000:01:00.0 eno1: renamed from eth0
[ 27.512496] mlx4_core 0000:01:00.0 eno1d1: renamed from eth1
[ 27.735069] random: fast init done
[ 28.250283] SGI XFS with ACLs, security attributes, no debug enabled
[ 28.329275] XFS (dm-0): Mounting V5 Filesystem
[ 28.425520] XFS (dm-0): Ending clean mount
[ 28.505469] mlx4_en: eno1d1: Link Up
[ 28.798515] systemd-journald[278]: Received SIGTERM from PID 1 (systemd).
[ 28.816777] systemd: 20 output lines suppressed due to ratelimiting
[ 28.843206] audit: type=1404 audit(1481665008.174:2): enforcing=1 old_enforcing=0 auid=4294967295 ses=4294967295
[ 29.275766] SELinux: 32768 avtab hash slots, 104865 rules.
[ 29.311159] SELinux: 32768 avtab hash slots, 104865 rules.
[ 29.396915] SELinux: 8 users, 14 roles, 4983 types, 301 bools, 1 sens, 1024 cats
[ 29.396921] SELinux: 91 classes, 104865 rules
[ 29.405995] SELinux: Permission validate_trans in class security not defined in policy.
[ 29.534735] SELinux: Permission module_load in class system not defined in policy.
[ 29.693475] SELinux: Class binder not defined in policy.
[ 29.824717] SELinux: Class cap_userns not defined in policy.
[ 29.960328] SELinux: Class cap2_userns not defined in policy.
[ 30.096987] SELinux: Class sctp_socket not defined in policy.
[ 30.233647] SELinux: Class icmp_socket not defined in policy.
[ 30.370305] SELinux: Class ax25_socket not defined in policy.
[ 30.506963] SELinux: Class ipx_socket not defined in policy.
[ 30.642581] SELinux: Class netrom_socket not defined in policy.
[ 30.781326] SELinux: Class bridge_socket not defined in policy.
[ 30.920071] SELinux: Class atmpvc_socket not defined in policy.
[ 31.058818] SELinux: Class x25_socket not defined in policy.
[ 31.194433] SELinux: Class rose_socket not defined in policy.
[ 31.331091] SELinux: Class decnet_socket not defined in policy.
[ 31.469842] SELinux: Class atmsvc_socket not defined in policy.
[ 31.608584] SELinux: Class rds_socket not defined in policy.
[ 31.744199] SELinux: Class irda_socket not defined in policy.
[ 31.880859] SELinux: Class pppox_socket not defined in policy.
[ 32.018561] SELinux: Class llc_socket not defined in policy.
[ 32.154176] SELinux: Class ib_socket not defined in policy.
[ 32.288749] SELinux: Class mpls_socket not defined in policy.
[ 32.425408] SELinux: Class can_socket not defined in policy.
[ 32.561024] SELinux: Class tipc_socket not defined in policy.
[ 32.697683] SELinux: Class bluetooth_socket not defined in policy.
[ 32.839559] SELinux: Class iucv_socket not defined in policy.
[ 32.976219] SELinux: Class rxrpc_socket not defined in policy.
[ 33.113920] SELinux: Class isdn_socket not defined in policy.
[ 33.250580] SELinux: Class phonet_socket not defined in policy.
[ 33.389325] SELinux: Class ieee802154_socket not defined in policy.
[ 33.532248] SELinux: Class caif_socket not defined in policy.
[ 33.656387] SELinux: Class alg_socket not defined in policy.
[ 33.725348] SELinux: Class nfc_socket not defined in policy.
[ 33.794301] SELinux: Class vsock_socket not defined in policy.
[ 33.865345] SELinux: Class kcm_socket not defined in policy.
[ 33.934298] SELinux: Class qipcrtr_socket not defined in policy.
[ 34.007429] SELinux: the above unknown classes and permissions will be allowed
[ 34.094131] SELinux: Completing initialization.
[ 34.094132] SELinux: Setting up existing superblocks.
[ 34.115577] audit: type=1403 audit(1481665013.447:3): policy loaded auid=4294967295 ses=4294967295
[ 34.119916] systemd[1]: Successfully loaded SELinux policy in 5.276847s.
[ 34.223152] systemd[1]: RTC configured in localtime, applying delta of -300 minutes to system time.
[ 34.274091] systemd[1]: Relabelled /dev and /run in 47.393ms.
[ 34.696398] systemd-journald[579]: Received request to flush runtime journal from PID 1
[ 34.824700] RPC: Registered named UNIX socket transport module.
[ 34.954590] RPC: Registered udp transport module.
[ 34.954592] RPC: Registered tcp transport module.
[ 34.954593] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 35.206778] Installing knfsd (copyright (C) 1996 okir at monad.swb.de).
[ 35.569775] input: Power Button as /devices/LNXSYSTM:00/PNP0C0C:00/input/input0
[ 35.572132] xgene-slimpro-mbox APMC0D01:00: APM X-Gene SLIMpro MailBox registered
[ 35.865673] ACPI: Power Button [PWRB]
[ 35.985733] xgene-gpio-sb APMC0D15:00: Support 22 gpios, 6 irqs start from pin 8
[ 36.132022] xgene-gpio-sb APMC0D15:00: X-Gene GPIO Standby driver registered
[ 36.282950] xgene-rng APMC0D18:00: Couldn't get the clock for RNG
[ 36.422797] xgene-slimpro-i2c APMC0D40:00: i2c mailbox channel request failed
[ 36.591693] Adding 11722688k swap on /dev/mapper/rhel_hp--moonshot--02--c08-swap. Priority:-1 extents:1 across:11722688k SSFS
[ 36.787069] XFS (sda2): Mounting V5 Filesystem
[ 36.868688] <mlx4_ib> mlx4_ib_add: mlx4_ib: Mellanox ConnectX InfiniBand driver v2.2-1 (Feb 2014)
[ 36.869195] <mlx4_ib> mlx4_ib_add: counter index 2 for port 1 allocated 1
[ 36.869196] <mlx4_ib> mlx4_ib_add: counter index 3 for port 2 allocated 1
[ 37.308253] Rounding down aligned max_sectors from 4294967295 to 4294967168
[ 37.350909] Loading iSCSI transport class v2.0-870.
[ 37.392750] iscsi: registered transport (iser)
[ 37.637247] RPC: Registered rdma transport module.
[ 37.637249] RPC: Registered rdma backchannel transport module.
[ 38.038304] XFS (dm-2): Mounting V5 Filesystem
[ 38.079284] XFS (sda2): Ending clean mount
[ 38.297433] XFS (dm-2): Ending clean mount
[ 43.639471] IPv6: ADDRCONF(NETDEV_UP): eno1: link is not ready
[ 43.710421] mlx4_en: eno1: frag:0 - size:1522 prefix:0 stride:1536
[ 43.838542] mlx4_en: eno1: Link Up
[ 43.838572] IPv6: ADDRCONF(NETDEV_UP): eno1: link is not ready
[ 43.908671] IPv6: ADDRCONF(NETDEV_CHANGE): eno1: link becomes ready
[ 43.991371] IPv6: ADDRCONF(NETDEV_UP): eno1d1: link is not ready
[ 44.064245] mlx4_en: eno1d1: frag:0 - size:1522 prefix:0 stride:1536
[ 90.846478] random: crng init done
^ permalink raw reply
* [PATCH 5/5] Documentation: fsl-quadspi: Add fsl, ls1012a-qspi compatible string
From: Rob Herring @ 2016-12-13 21:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR0402MB2902DADEB4E6D06418AD311F899B0@DB6PR0402MB2902.eurprd04.prod.outlook.com>
On Mon, Dec 12, 2016 at 8:47 PM, Yao Yuan <yao.yuan@nxp.com> wrote:
> On Thu, Dec 13, 2016 at 05:23:02PM +0800, Rob Herring wrote:
>> On Thu, Dec 08, 2016 at 05:23:04PM +0800, Yuan Yao wrote:
>> > From: Yuan Yao <yao.yuan@nxp.com>
>>
>> Same problem in this subject too.
>>
>> >
>> > new compatible string: "fsl,ls1012a-qspi".
>> >
>> > Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
>> > ---
>> > Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
>> > 1 file changed, 1 insertion(+)
>>
>> Acked-by: Rob Herring <robh@kernel.org>
>
> Thanks for your review.
> And do you have any suggestion for this subject?
The problem is you have a space in the compatible string: "fsl,
ls1012a-qspi" rather than "fsl,ls1012a-qspi"
Also, I prefer "dt/bindings: " as the beginning of binding patch subjects.
Rob
^ permalink raw reply
* [PATCH 2/4] dt-bindings: mfd: Remove TPS65217 interrupts
From: Rob Herring @ 2016-12-13 21:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <fe4985c0-d60a-2562-12a7-064404efd64c@gmail.com>
On Mon, Dec 12, 2016 at 5:24 PM, Milo Kim <woogyom.kim@gmail.com> wrote:
> On 12/13/2016 02:25 AM, Rob Herring wrote:
>>
>> On Fri, Dec 09, 2016 at 03:28:31PM +0900, Milo Kim wrote:
>>>
>>> Interrupt numbers are from the datasheet, so no need to keep them in
>>> the ABI. Use the number in the DT file.
>>
>> I don't see the purpose of ripping this out. The headers have always
>> been for convienence, not whether the values come from the datasheet or
>> not.
>
>
> My understanding is it's a same rule as other interrupt controllers.
Oh yes, that's true. We never use defines for interrupts. In that case:
Acked-by: Rob Herring <robh@kernel.org>
Rob
^ permalink raw reply
* [PATCH v6 1/8] MFD: add bindings for STM32 Timers driver
From: Rob Herring @ 2016-12-13 21:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+M3ks4ukP14YE5-6+gAzJBjEmjEyGyVbsVGOm8ehVm0EfzO-w@mail.gmail.com>
On Tue, Dec 13, 2016 at 3:29 AM, Benjamin Gaignard
<benjamin.gaignard@linaro.org> wrote:
> 2016-12-12 19:51 GMT+01:00 Rob Herring <robh@kernel.org>:
>> On Fri, Dec 09, 2016 at 03:15:12PM +0100, Benjamin Gaignard wrote:
>>> Add bindings information for STM32 Timers
>>>
>>> version 6:
>>> - rename stm32-gtimer to stm32-timers
>>> - change compatible
>>> - add description about the IPs
>>>
>>> version 2:
>>> - rename stm32-mfd-timer to stm32-gptimer
>>> - only keep one compatible string
>>>
>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>>> ---
>>> .../devicetree/bindings/mfd/stm32-timers.txt | 46 ++++++++++++++++++++++
>>> 1 file changed, 46 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
>>> new file mode 100644
>>> index 0000000..b30868e
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
>>> @@ -0,0 +1,46 @@
>>> +STM32 Timers driver bindings
>>> +
>>> +This IP provides 3 types of timer along with PWM functionality:
>>> +- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable
>>> + prescaler, break input feature, PWM outputs and complementary PWM ouputs channels.
>>> +- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a
>>> + programmable prescaler and PWM outputs.
>>> +- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
>>> +
>>> +Required parameters:
>>> +- compatible: must be "st,stm32-timers"
>>> +
>>> +- reg: Physical base address and length of the controller's
>>> + registers.
>>> +- clock-names: Set to "clk_int".
>>
>> 'clk' is redundant. Also, you don't really need -names when there is
>> only one of them.
>
> I use devm_regmap_init_mmio_clk() which get the clock by it name so
> I have to define it in DT.
Are you sure NULL is not allowed? I don't know, but at least clk_get()
allows NULL.
It's fine to keep, just drop the "clk_" part.
>
>>> +- clocks: Phandle to the clock used by the timer module.
>>> + For Clk properties, please refer to ../clock/clock-bindings.txt
>>> +
>>> +Optional parameters:
>>> +- resets: Phandle to the parent reset controller.
>>> + See ../reset/st,stm32-rcc.txt
>>> +
>>> +Optional subnodes:
>>> +- pwm: See ../pwm/pwm-stm32.txt
>>> +- timer: See ../iio/timer/stm32-timer-trigger.txt
>>> +
>>> +Example:
>>> + timers at 40010000 {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + compatible = "st,stm32-timers";
>>> + reg = <0x40010000 0x400>;
>>> + clocks = <&rcc 0 160>;
>>> + clock-names = "clk_int";
>>> +
>>> + pwm {
>>> + compatible = "st,stm32-pwm";
>>> + pinctrl-0 = <&pwm1_pins>;
>>> + pinctrl-names = "default";
>>> + };
>>> +
>>> + timer {
>>> + compatible = "st,stm32-timer-trigger";
>>> + reg = <0>;
>>
>> You don't need reg here as there is only one. In turn, you don't need
>> #address-cells or #size-cells.
>
> I use "reg" to set each timer configuration.
> From hardware point of view they are all the same except for which hardware
> signals they could consume and/or send.
This sounds okay, but...
> "reg" is used as index of the two tables in driver code.
this statement doesn't really sound like valid use of reg.
If you keep reg, then the node needs a unit address (timer at 0).
Rob
^ permalink raw reply
* [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33
From: Icenowy Zheng @ 2016-12-13 20:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161213154451.y4wcrqhtcc5sqli7@lukather>
13.12.2016, 23:44, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote:
>> ?The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
>> ?be changeable by changing the rate of PLL_CPUX.
>>
>> ?Add CLK_SET_RATE_PARENT flag to this clock.
>>
>> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Excuse me, have you merged this patch?
If merged, I won't contain it in my PATCH v2, thus the PATCH v2 will contain
only an updated OPP patch.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply
* [PATCH] i2c: designware: add reset interface
From: Wolfram Sang @ 2016-12-13 20:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479789700-19532-1-git-send-email-zhangfei.gao@linaro.org>
On Tue, Nov 22, 2016 at 12:41:40PM +0800, Zhangfei Gao wrote:
> Some platforms like hi3660 need do reset first to allow accessing registers
>
> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Adding designware maintainers to CC...
> ---
> drivers/i2c/busses/i2c-designware-core.h | 1 +
> drivers/i2c/busses/i2c-designware-platdrv.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
> index 0d44d2a..94b14fa 100644
> --- a/drivers/i2c/busses/i2c-designware-core.h
> +++ b/drivers/i2c/busses/i2c-designware-core.h
> @@ -80,6 +80,7 @@ struct dw_i2c_dev {
> void __iomem *base;
> struct completion cmd_complete;
> struct clk *clk;
> + struct reset_control *rst;
> u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
> struct dw_pci_controller *controller;
> int cmd_err;
> diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
> index 0b42a12..fd80e58 100644
> --- a/drivers/i2c/busses/i2c-designware-platdrv.c
> +++ b/drivers/i2c/busses/i2c-designware-platdrv.c
> @@ -38,6 +38,7 @@
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> #include <linux/io.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/acpi.h>
> #include <linux/platform_data/i2c-designware.h>
> @@ -176,6 +177,10 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
> dev->irq = irq;
> platform_set_drvdata(pdev, dev);
>
> + dev->rst = devm_reset_control_get(&pdev->dev, NULL);
> + if (!IS_ERR(dev->rst))
> + reset_control_reset(dev->rst);
> +
> /* fast mode by default because of legacy reasons */
> dev->clk_freq = 400000;
>
> --
> 2.7.4
>
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^ permalink raw reply
* [RFC v4 00/16] KVM PCIe/MSI passthrough on ARM/ARM64 and IOVA reserved regions
From: Eric Auger @ 2016-12-13 20:30 UTC (permalink / raw)
To: linux-arm-kernel
Following LPC discussions, we now report reserved regions through
iommu-group sysfs reserved_regions attribute file.
Reserved regions are populated through the IOMMU get_resv_region
callback (former get_dm_regions), now implemented by amd-iommu,
intel-iommu and arm-smmu:
- the amd-iommu reports device direct mapped regions.
- the intel-iommu reports the [0xfee00000 - 0xfeefffff] MSI window
as an IOMMU_RESV_NOMAP reserved region.
- the arm-smmu reports the MSI window (arbitrarily located at
0x8000000 and 1MB large).
Unsafe interrupt assignment is tested by enumerating all MSI irq
domains and checking they support MSI remapping. This check is done
in case we detect the iommu translates MSI (an IOMMU_RESV_MSI
window exists). Otherwise the IRQ remapping capability is checked
at IOMMU level. Obviously this is a defensive IRQ safety assessment.
Assuming there are several MSI controllers in the system and at
least one does not implement IRQ remapping, the assignment will be
considered as unsafe (even if this controller is not acessible from
the assigned devices).
The series integrates a not officially posted patch from Robin:
"iommu/dma: Allow MSI-only cookies".
Best Regards
Eric
Git: complete series available at
https://github.com/eauger/linux/tree/v4.9-reserved-v4
History:
RFCv3 -> RFCv4:
- arm-smmu driver does not register PCI host bridge windows as
reserved regions anymore
- Implement reserved region get/put callbacks also in arm-smmuv3
- take the iommu_group lock on iommu_get_group_resv_regions
- add a type field in iommu_resv_region instead of using prot
- init the region list_head in iommu_alloc_resv_region, also
add type parameter
- iommu_insert_resv_region manage overlaps and sort reserved
windows
- address IRQ safety assessment by enumerating all the MSI irq
domains and checking the MSI_REMAP flag
- update Documentation/ABI/testing/sysfs-kernel-iommu_groups
- Did not add T-b since the code has significantly changed
RFCv2 -> RFCv3:
- switch to an iommu-group sysfs API
- use new dummy allocator provided by Robin
- dummy allocator initialized by vfio-iommu-type1 after enumerating
the reserved regions
- at the moment ARM MSI base address/size is left unchanged compared
to v2
- we currently report reserved regions and not usable IOVA regions as
requested by Alex
RFC v1 -> v2:
- fix intel_add_reserved_regions
- add mutex lock/unlock in vfio_iommu_type1
Eric Auger (16):
iommu/dma: Allow MSI-only cookies
iommu: Rename iommu_dm_regions into iommu_resv_regions
iommu: Add a new type field in iommu_resv_region
iommu: iommu_alloc_resv_region
iommu: Only map direct mapped regions
iommu: iommu_get_group_resv_regions
iommu: Implement reserved_regions iommu-group sysfs file
iommu/vt-d: Implement reserved region get/put callbacks
iommu/arm-smmu: Implement reserved region get/put callbacks
iommu/arm-smmu-v3: Implement reserved region get/put callbacks
irqdomain: Add IRQ_DOMAIN_FLAG_MSI_REMAP value
irqdomain: irq_domain_check_msi_remap
irqchip/gicv3-its: Sets IRQ_DOMAIN_FLAG_MSI_REMAP
vfio/type1: Allow transparent MSI IOVA allocation
vfio/type1: Check MSI remapping at irq domain level
iommu/arm-smmu: Do not advertise IOMMU_CAP_INTR_REMAP anymore
.../ABI/testing/sysfs-kernel-iommu_groups | 9 ++
drivers/iommu/amd_iommu.c | 21 +--
drivers/iommu/arm-smmu-v3.c | 30 +++-
drivers/iommu/arm-smmu.c | 30 +++-
drivers/iommu/dma-iommu.c | 116 +++++++++++++---
drivers/iommu/intel-iommu.c | 50 +++++--
drivers/iommu/iommu.c | 152 +++++++++++++++++++--
drivers/irqchip/irq-gic-v3-its.c | 1 +
drivers/vfio/vfio_iommu_type1.c | 37 ++++-
include/linux/dma-iommu.h | 7 +
include/linux/iommu.h | 46 +++++--
include/linux/irqdomain.h | 8 ++
kernel/irq/irqdomain.c | 24 ++++
13 files changed, 455 insertions(+), 76 deletions(-)
--
1.9.1
^ permalink raw reply
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