* [PATCH v6 05/14] ACPI: platform-msi: retrieve dev id from IORT
From: Tomasz Nowicki @ 2017-01-03 9:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <13cb0c87-e1c0-c4d6-4793-a3edd20944dc@semihalf.com>
On 03.01.2017 09:43, Tomasz Nowicki wrote:
> On 02.01.2017 14:31, Hanjun Guo wrote:
>> For devices connecting to ITS, it needs dev id to identify
>> itself, and this dev id is represented in the IORT table in
>> named componant node [1] for platform devices, so in this
>> patch we will scan the IORT to retrieve device's dev id.
>>
>> Introduce iort_pmsi_get_dev_id() with pointer dev passed
>> in for that purpose.
>>
>> [1]:
>> https://static.docs.arm.com/den0049/b/DEN0049B_IO_Remapping_Table.pdf
>>
>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>> Tested-by: Sinan Kaya <okaya@codeaurora.org>
>> Tested-by: Majun <majun258@huawei.com>
>> Tested-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Cc: Tomasz Nowicki <tn@semihalf.com>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> ---
>> drivers/acpi/arm64/iort.c | 26
>> ++++++++++++++++++++++++++
>> drivers/irqchip/irq-gic-v3-its-platform-msi.c | 4 +++-
>> include/linux/acpi_iort.h | 8 ++++++++
>> 3 files changed, 37 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index 174e983..ab7bae7 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -444,6 +444,32 @@ u32 iort_msi_map_rid(struct device *dev, u32 req_id)
>> }
>>
>> /**
>> + * iort_pmsi_get_dev_id() - Get the device id for a device
>> + * @dev: The device for which the mapping is to be done.
>> + * @dev_id: The device ID found.
>> + *
>> + * Returns: 0 for successful find a dev id, errors otherwise
>> + */
>> +int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
>> +{
>> + struct acpi_iort_node *node;
>> +
>> + if (!iort_table)
>> + return -ENODEV;
>> +
>> + node = iort_find_dev_node(dev);
>> + if (!node) {
>> + dev_err(dev, "can't find related IORT node\n");
>> + return -ENODEV;
>> + }
>> +
>> + if(!iort_node_get_id(node, dev_id, IORT_MSI_TYPE, 0))
>> + return -ENODEV;
>> +
>> + return 0;
>> +}
>> +
>> +/**
> Giving that you are extending this to NC->
> SMMU->ITS case in later patch, we can use existing helpers from iort.c,
> like that:
>
> +/**
> + * iort_pmsi_get_dev_id() - Get the device id for a device
> + * @dev: The device for which the mapping is to be done.
> + * @dev_id: The device ID found.
> + *
> + * Returns: 0 for successful find a dev id, errors otherwise
> + */
> +int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
> +{
> + struct acpi_iort_node *node;
> +
> + node = iort_find_dev_node(dev);
> + if (!node)
> + return -ENODEV;
> +
> + if (!iort_node_map_rid(node, 0, dev_id, IORT_MSI_TYPE))
> + return -ENODEV;
> +
> + return 0;
> +}
>
> Correct me if I am wrong.
>
"0" as rid_in for iort_node_map_rid() isn't good idea, sorry...
Tomasz
^ permalink raw reply
* [PATCH v2 1/4] pinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433
From: Andi Shyti @ 2017-01-03 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161230150932.q7kadv4ouhdrkqea@kozik-lap>
Hi Linus and Krzysztof,
> > > From: Chanwoo Choi <cw00.choi@samsung.com>
> > >
> > > This patch fixes the wrong width of PINCFG_TYPE_DRV bitfields for Exynos5433
> > > because PINCFG_TYPE_DRV of Exynos5433 has 4bit fields in the *_DRV
> > > registers. Usually, other Exynos have 2bit field for PINCFG_TYPE_DRV.
> > >
> > > Fixes: 3c5ecc9ed353 ("pinctrl: exynos: Add support for Exynos5433")
> > > Cc: stable at vger.kernel.org
> > > Cc: Tomasz Figa <tomasz.figa@gmail.com>
> > > Cc: Krzysztof Kozlowski <krzk@kernel.org>
> > > Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> > > Cc: Linus Walleij <linus.walleij@linaro.org>
> > > Cc: Kukjin Kim <kgene@kernel.org>
> > > Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> > > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> >
> > Nominally I think you should sign this off too Andi, as you are in the delivery
> > path.
> >
> > Patch applied for fixes.
>
> That has to be signed by Andi... otherwise the chain is broken (and
> there could be changes added inside).
yes, sorry about this. If Linus wants and it's not too late, he
can add my signed off at the bottom.
Thanks,
Andi
^ permalink raw reply
* [PATCH 1/2] ARM: hyp-stub: improve ABI
From: Christoffer Dall @ 2017-01-03 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161215185717.GM14217@n2100.armlinux.org.uk>
Hi Russell,
On Thu, Dec 15, 2016 at 06:57:18PM +0000, Russell King - ARM Linux wrote:
> On Thu, Dec 15, 2016 at 03:37:15PM +0000, Marc Zyngier wrote:
> > On 15/12/16 15:15, Russell King - ARM Linux wrote:
> > > On Thu, Dec 15, 2016 at 11:46:41AM +0000, Marc Zyngier wrote:
> > >> On 15/12/16 11:35, Russell King - ARM Linux wrote:
> > >>> On Thu, Dec 15, 2016 at 11:18:48AM +0000, Marc Zyngier wrote:
> > >>>> On 14/12/16 10:46, Russell King wrote:
> > >>>>> @@ -231,10 +244,14 @@ ENDPROC(__hyp_stub_do_trap)
> > >>>>> * initialisation entry point.
> > >>>>> */
> > >>>>> ENTRY(__hyp_get_vectors)
> > >>>>> - mov r0, #-1
> > >>>>> + mov r0, #HVC_GET_VECTORS
> > >>>>
> > >>>> This breaks the KVM implementation of __hyp_get_vectors, easily fixed
> > >>>> with the following patchlet:
> > >>>
> > >>> Right, so what Mark said is wrong:
> > >>>
> > >>> "The hyp-stub is part of the kernel image, and the API is private to
> > >>> that particular image, so we can change things -- there's no ABI to
> > >>> worry about."
> > >>
> > >> I think Mark is right. The API *is* private to the kernel, and KVM being
> > >> the only in-kernel hypervisor on ARM, this is not an ABI.
> > >
> > > Again, that's wrong.
> > >
> > > We have two hypervisors in the kernel. One is KVM, the other is the
> > > stub. Sure, the stub isn't a full implementation of a hypervisor, but
> > > it is nevertheless, for the purposes of _this_ discussion, a hypervisor
> > > of sorts.
> > >
> > > The reason that both are included is because they both appear to share
> > > a common interface (although that's totally not documented anywhere.)
> >
> > And this interface exists for the sole purpose of enabling KVM. Call it
> > a hypervisor if you wish, but its usefulness is doubtful on its own.
> >
> > >>> So no, I'm going with my original patch (which TI has tested) which is
> > >>> the minimal change, and if we _then_ want to rework the HYP mode
> > >>> interfaces, that's the time to do the other changes when more people
> > >>> (such as KVM folk) are paying attention and we can come to a cross-
> > >>> hypervisor agreement on what the interface should be.
> > >>
> > >> Given that there is a single in-kernel hypervisor, I can't really see
> > >> who we're going to agree anything with...
> > >
> > > As far as I can see, the hyp-stub falls under ARM arch maintanence.
> > > KVM falls under KVM people. Two different groups, we need agreement
> > > between them what a sane API for both "hypervisors" should be.
> >
> > Well, I though we had the right level of discussion by reviewing your
> > patches and coming up with improvements. If you're after something else,
> > please let me know.
>
> What I'm after is a meaningful discussion between ARM arch maintainers
> and KVM maintainers - so far all I see are people on the ARM side of
> things.
I think your patches look fine, and I agree with your suggestions on
improving the hyp ABI and documenting it.
Marc found a small problem for KVM with your patch and offered a simple
fix. I don't really see a bigger problem here?
>
> I've also yet to have any response on some of the KVM questions I raised
> earlier in this thread - again, silence from KVM people.
Sorry about my silence, I was really busy leading up to Christmas and
was offline for most of the Christmas and new years days.
I've gone back over the thread and haven't been able to spot anything
that wasn't already answered by Marc (who also maintains KVM so would be
one of the KVM people). Could you let me know which questions remain
unanswered and I can try to help?
>
> What's also coming clear is that there's very few people who understand
> all the interactions here, and the whole thing seems to be an undocumented
> mess.
I think the hyp stub has just served a very limited purpose so far, and
therefore is a somewhat immature implementation. Now we've discovered a
need to clean it up, and we're all for that. Again, I don't think the
problem is any larger than that, we just need to fix it, and it seems to
me everyone is willing to work on that. Marc even offered to work on
your suggestion to support the general hyp ABI commands in KVM.
[...]
>
> So, I want KVM further changes to come through my tree once this merge
> window is over
I think we should try to separate the discussion of fixing an immediate
problem with the hyp code, and that of how to maintain things. I think
we're already on the right track to fix the former.
Before we start changing up maintainerships (which I personally think
work fine as it is) I would encourage you to just comment on patches
touching arch/arm that you are unhappy with.
We have been cc'ing all our changes to lakml and we've tried to cc you
specifically on anything touching arch/arm, and we will listen to any
suggestions you may have.
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH v4] arm64: Add DTS support for FSL's LS1012A SoC
From: Harninder Rai @ 2017-01-03 9:57 UTC (permalink / raw)
To: linux-arm-kernel
LS1012A features an advanced 64-bit ARM v8 CortexA53 processor
with 32 KB of parity protected L1-I cache, 32 KB of ECC protected
L1-D cache, as well as 256 KB of ECC protected L2 cache.
Features summary
One 64-bit ARM-v8 Cortex-A53 core with the following capabilities
- Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC
protection
- Speed up to 800 MHz
- Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache
- Neon SIMD engine
- ARM v8 cryptography extensions
One 16-bit DDR3L SDRAM memory controller
ARM core-link CCI-400 cache coherent interconnect
Cryptography acceleration (SEC)
One Configurable x3 SerDes
One PCI Express Gen2 controller, supporting x1 operation
One serial ATA (SATA Gen 3.0) controller
One USB 3.0/2.0 controller with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1012A
SoC family:
- fsl-ls1012a.dtsi:
DTS-Include file for FSL LS1012A SoC.
- fsl-ls1012a-frdm.dts:
DTS file for FSL LS1012A FRDM board.
- fsl-ls1012a-qds.dts:
DTS file for FSL LS1012A QDS board.
- fsl-ls1012a-rdb.dts:
DTS file for FSL LS1012A RDB board.
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
Changes in v4: Incorporated Shawn's comments
- Convert "regulator_3p3v: regulator" to "reg_3p3v: regulator-3p3v"
- Add "status = "disabled"" property in sata and duart nodes
Changes in v3: Incorporated Leo's comments
- Change PPI interrupts to IRQ_TYPE_LEVEL_LOW and
- SPI interrupts to IRQ_TYPE_LEVEL_HIGH
Changes in v2: Incorporated Shawn's comments
- Brief introduction of the SoC in commit message
- Alphabetic ordering of labeled nodes
- Better naming to be used for regulator node
- Make timer node's comments more readable
- Sort nodes with unit-address in order of the address
arch/arm64/boot/dts/freescale/Makefile | 3 +
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 115 ++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 128 +++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 59 +++++
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 247 +++++++++++++++++++++
5 files changed, 552 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 6602718..39db645 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,3 +1,6 @@
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
new file mode 100644
index 0000000..a619f64
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -0,0 +1,115 @@
+/*
+ * Device Tree file for Freescale LS1012A Freedom Board.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A Freedom Board";
+ compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ system-clock-frequency = <25000000>;
+ };
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ codec: sgtl5000 at a {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0xa>;
+ VDDA-supply = <®_1p8v>;
+ VDDIO-supply = <®_1p8v>;
+ clocks = <&sys_mclk>;
+ };
+};
+
+&sai2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
new file mode 100644
index 0000000..14a67f1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -0,0 +1,128 @@
+/*
+ * Device Tree file for Freescale LS1012A QDS Board.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A QDS Board";
+ compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ system-clock-frequency = <24576000>;
+ };
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ pca9547 at 77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ codec: sgtl5000 at a {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0xa>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ clocks = <&sys_mclk>;
+ };
+ };
+ };
+};
+
+&sai2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
new file mode 100644
index 0000000..62c5c71
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -0,0 +1,59 @@
+/*
+ * Device Tree file for Freescale LS1012A RDB Board.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A RDB Board";
+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
new file mode 100644
index 0000000..cffebb4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -0,0 +1,247 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "fsl,ls1012a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clocks = <&clockgen 1 0>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
+ <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
+ <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
+ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gic: interrupt-controller at 1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x2000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&dcfg>;
+ offset = <0xb0>;
+ mask = <0x02>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scfg: scfg at 1570000 {
+ compatible = "fsl,ls1012a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ };
+
+ dcfg: dcfg at 1ee0000 {
+ compatible = "fsl,ls1012a-dcfg",
+ "syscon";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ big-endian;
+ };
+
+ clockgen: clocking at 1ee1000 {
+ compatible = "fsl,ls1012a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ i2c0: i2c at 2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial at 21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart1: serial at 21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ gpio0: gpio at 2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio at 2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wdog0: wdog at 2ad0000 {
+ compatible = "fsl,ls1012a-wdt",
+ "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ big-endian;
+ };
+
+ sai1: sai at 2b50000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b50000 0x0 0x10000>;
+ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>,
+ <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 47>,
+ <&edma0 1 46>;
+ status = "disabled";
+ };
+
+ sai2: sai at 2b60000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0x2b60000 0x0 0x10000>;
+ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>,
+ <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 45>,
+ <&edma0 1 44>;
+ status = "disabled";
+ };
+
+ edma0: edma at 2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
+ <0 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen 4 3>,
+ <&clockgen 4 3>;
+ };
+
+ sata: sata at 3200000 {
+ compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Andi Shyti @ 2017-01-03 9:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJKOXPev9m07_dQWAvJ+=MKnbT0TFERKOtjWUDU+WXdGAiRyDA@mail.gmail.com>
Hi Krzysztof,
> > Currently tm2e dts includes tm2 but there are some differences
> > between the two boards and tm2 has some properties that tm2e
> > doesn't have.
> >
> > That's why it's important to keep the two dts files independent
> > and put all the commonalities in a tm2-common.dtsi file.
> >
> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> > ---
> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
> > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
> > 3 files changed, 1049 insertions(+), 1032 deletions(-)
> > create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>
> I would like to see here the rename and diff from it. Not entire delta
> (deletions and addons). It is not possible to compare it... I think
> git supports it by default with similarity of 50%.
I understand, it's indeed quite cryptic to understand. But all
the diff algorithms (patience, minimal, histogram, myers) give
the same result. I don't know how to make it better.
I could split this patch, but this also means breaking tm2's
functionality, which looks worse.
Please tell me if you know a better way for generating the patch.
Thanks,
Andi
^ permalink raw reply
* [PATCH v1] mtd: nand: tango: Reset pbus to raw mode in probe
From: Marc Gonzalez @ 2017-01-03 10:01 UTC (permalink / raw)
To: linux-arm-kernel
Linux should not expect the boot loader to properly configure the
peripheral bus "pad mode", so reset PBUS_PAD_MODE to raw.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
---
drivers/mtd/nand/tango_nand.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/tango_nand.c b/drivers/mtd/nand/tango_nand.c
index d370c0382808..2456640fe4d5 100644
--- a/drivers/mtd/nand/tango_nand.c
+++ b/drivers/mtd/nand/tango_nand.c
@@ -644,6 +644,8 @@ static int tango_nand_probe(struct platform_device *pdev)
if (IS_ERR(nfc->pbus_base))
return PTR_ERR(nfc->pbus_base);
+ writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
+
clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(clk))
return PTR_ERR(clk);
^ permalink raw reply related
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Krzysztof Kozlowski @ 2017-01-03 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103095842.h3hl64amje4qv4ts@gangnam.samsung>
On Tue, Jan 3, 2017 at 11:58 AM, Andi Shyti <andi.shyti@samsung.com> wrote:
> Hi Krzysztof,
>
>> > Currently tm2e dts includes tm2 but there are some differences
>> > between the two boards and tm2 has some properties that tm2e
>> > doesn't have.
>> >
>> > That's why it's important to keep the two dts files independent
>> > and put all the commonalities in a tm2-common.dtsi file.
>> >
>> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
>> > ---
>> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
>> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
>> > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
>> > 3 files changed, 1049 insertions(+), 1032 deletions(-)
>> > create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>>
>> I would like to see here the rename and diff from it. Not entire delta
>> (deletions and addons). It is not possible to compare it... I think
>> git supports it by default with similarity of 50%.
>
> I understand, it's indeed quite cryptic to understand. But all
> the diff algorithms (patience, minimal, histogram, myers) give
> the same result. I don't know how to make it better.
>
> I could split this patch, but this also means breaking tm2's
> functionality, which looks worse.
>
> Please tell me if you know a better way for generating the patch.
git format-patch -M95%?
Krzysztof
^ permalink raw reply
* [PATCH v5 0/6] arm64: arch_timer: Add workaround for hisilicon-161601 erratum
From: Hanjun Guo @ 2017-01-03 10:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482476669-15596-1-git-send-email-dingtianhong@huawei.com>
Hi Ding,
On 2016/12/23 15:04, Ding Tianhong wrote:
> Erratum Hisilicon-161601 says that the ARM generic timer counter "has the
> potential to contain an erroneous value when the timer value changes".
> Accesses to TVAL (both read and write) are also affected due to the implicit counter
> read. Accesses to CVAL are not affected.
>
> The workaround is to reread the system count registers until the value of the second
> read is larger than the first one by less than 32, the system counter can be guaranteed
> not to return wrong value twice by back-to-back read and the error value is always larger
> than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
>
> v2: Introducing a new generic erratum handling mechanism for fsl,a008585 and hisilicon,161601.
> Significant rework based on feedback, including seperate the fsl erratum a008585
> to another patch, update the erratum name and remove unwanted code.
>
> v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585
> and make the #define __fsl_a008585_read_reg to be private to the .c file instead of
> being globally visible. After discussion with Marc and Will, a consensus decision was
> made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum,
> and make some generic name more specific, export timer_unstable_counter_workaround
> for module access.
>
> Significant rework based on feedback, including fix some alignment problem, make the
> #define __hisi_161601_read_reg to be private to the .c file instead of being globally
> visible, add more accurate annotation and modify a bit of logical format to enable
> arch_timer_read_ool_enabled, remove the kernel commandline parameter
> clocksource.arm_arch_timer.hisilicon-161601.
>
> Introduce a generic aquick framework for erratum in ACPI mode.
>
> v4: rename the quirk handler parameter to make it more generic, and
> avoid break loop when handling the quirk becasue it need to
> support multi quirks handler.
>
> update some data structures for acpi mode.
>
> v5: Adapt the new kernel-parameters.txt for latest kernel version.
> Set the retries of reread system counter to 50, because it is possible
> that some interrupts may lead to more than twice read errors and break the loop,
> it will trigger the warning, so we set the number of retries far beyond the number of
> iterations the loop has been observed to take.
>
> Ding Tianhong (4):
> arm64: arch_timer: Add device tree binding for hisilicon-161601
> erratum
> arm64: arch_timer: Introduce a generic erratum handing mechanism for
> fsl-a008585
> arm64: arch_timer: Work around Erratum Hisilicon-161601
> arm64: arch timer: Add timer erratum property for Hip05-d02 and
> Hip06-d03
>
> Hanjun Guo (2):
> arm64: arch_timer: apci: Introduce a generic aquirk framework for
> erratum
> arm64: arch_timer: acpi: add hisi timer errata data
Since the ACPI code is conflict with Fuwei's GTDT patch set, let's split this patch
set into two parts, one is the DT based code, and the other is the ACPI part,
I will rebase ACPI code on top of Fuwei's patch set so please go upstream first.
Thanks
Hanjun
^ permalink raw reply
* [RFC PATCH] sched: Remove set_task_state()
From: Mark Rutland @ 2017-01-03 10:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483121873-21528-1-git-send-email-dave@stgolabs.net>
On Fri, Dec 30, 2016 at 10:17:53AM -0800, Davidlohr Bueso wrote:
> Secondly for a higher overview, an unlink microbenchmark was used,
> which pounds on a single file with open, close,unlink combos with
> increasing thread counts (up to 4x ncpus). While the workload is
> quite unrealistic, it does contend a lot on the inode mutex or now
> rwsem. With the archs I had access to, the differences are as follows:
>
> == 1. arm64 ==
>
> 0000000000002784 <set_task_state>:
> 2784: f9000c1f str xzr, [x0,#24]
>
> 0000000000002790 <set_current_state>:
> 2790: d5384100 mrs x0, sp_el0
> 2794: f9000c1f str xzr, [x0,#24]
>
> Avg runtime set_task_state(): 2648 msecs
> Avg runtime set_current_state(): 2686 msecs
> Unsurprisingly, the big looser is arm64, due to the masking of sp_el0.
> otoh, x86-64 (known to be fast for get_current()/this_cpu_read_stable()
> caching) and ppc64 (with paca) show similar improvements in the unlink
> microbenches. x86's write latencies delta is similar to the opposite of
> arm64: 50ms vs -40ms, respectively. The small delta for ppc64 (2ms), does
> not represent the gains on the unlink runs. In the case of x86, there was
> a decent amount of variation in the latency runs, but always within a 20
> to 50ms increase), ppc was more constant.
>
> So, do we want to get rid of the interface (and improve performance on
> other archs) at the expense of arm64? Can arm64 do better?
We can defineitely do better; the asm constraints in read_sysreg() are
overly pessimistic for get_current().
Does the below help?
Thanks,
Mark.
---->8----
diff --git a/arch/arm64/include/asm/current.h b/arch/arm64/include/asm/current.h
index f2bcbe2..c9ba5ac 100644
--- a/arch/arm64/include/asm/current.h
+++ b/arch/arm64/include/asm/current.h
@@ -11,7 +11,11 @@
static __always_inline struct task_struct *get_current(void)
{
- return (struct task_struct *)read_sysreg(sp_el0);
+ struct task_struct *tsk;
+
+ asm ("mrs %0, sp_el0" : "=r" (tsk));
+
+ return tsk;
}
#define current get_current()
^ permalink raw reply related
* [PATCH] mtd: nand: lpc32xx: fix invalid error handling of a requested irq
From: Vladimir Zapolskiy @ 2017-01-03 10:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103101259.0ec123df@bbrezillon>
Hi Boris,
On 01/03/2017 11:12 AM, Boris Brezillon wrote:
> Hi Vladimir
>
> On Mon, 5 Dec 2016 03:47:10 +0200
> Vladimir Zapolskiy <vz@mleia.com> wrote:
>
>> Semantics of NR_IRQS is different on machines with SPARSE_IRQ option
>> disabled or enabled, in the latter case IRQs are allocated starting
>> at least from the value specified by NR_IRQS and going upwards, so
>> the check of (irq >= NR_IRQ) to decide about an error code returned by
>> platform_get_irq() is completely invalid, don't attempt to overrule
>> irq subsystem in the driver.
>>
>> The change fixes LPC32xx NAND MLC driver initialization on boot.
>
> Do you need to backport this fix to stable releases? If that's the
> case, I'll add the Cc: stable tag when applying.
that will be great if you can add
Cc: stable at kernel.org # v4.7+
Please feel free to add also the tag
Fixes: 8cb17b5ed017 ("irqchip: Add LPC32xx interrupt controller driver")
--
With best wishes,
Vladimir
^ permalink raw reply
* [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
From: Richard Cochran @ 2017-01-03 10:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFcVECK1vt7Hu4tgSZ2+kKpMxoT-wpikMDq65HaxRv-EMgobHA@mail.gmail.com>
On Tue, Jan 03, 2017 at 10:36:11AM +0530, Harini Katakam wrote:
> I understand that it is not accurate - it is an initial version.
No, it is not inaccurate at all, it is WRONG.
This means that time stamps will be randomly associated with PTP
network packets. To the application, the protocol will appear to
work, but the time stamp information (and thus the synchronization)
will be wrong.
To me, this is unacceptable, and I will push back on this driver
getting merged.
[ In contrast, the descriptor based approach would be ok, afaict. ]
Thanks,
Richard
^ permalink raw reply
* [PATCH 3/4] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Andi Shyti @ 2017-01-03 10:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJKOXPeEE1VwAUSAOpfyX+t58zKeAT1fe3ybp0BoQiiDBb4Uqg@mail.gmail.com>
> >> > Currently tm2e dts includes tm2 but there are some differences
> >> > between the two boards and tm2 has some properties that tm2e
> >> > doesn't have.
> >> >
> >> > That's why it's important to keep the two dts files independent
> >> > and put all the commonalities in a tm2-common.dtsi file.
> >> >
> >> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> >> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> >> > ---
> >> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1046 ++++++++++++++++++++
> >> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1033 +------------------
> >> > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 2 +-
> >> > 3 files changed, 1049 insertions(+), 1032 deletions(-)
> >> > create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> >>
> >> I would like to see here the rename and diff from it. Not entire delta
> >> (deletions and addons). It is not possible to compare it... I think
> >> git supports it by default with similarity of 50%.
> >
> > I understand, it's indeed quite cryptic to understand. But all
> > the diff algorithms (patience, minimal, histogram, myers) give
> > the same result. I don't know how to make it better.
> >
> > I could split this patch, but this also means breaking tm2's
> > functionality, which looks worse.
> >
> > Please tell me if you know a better way for generating the patch.
>
> git format-patch -M95%?
Same thing with all M values.
Because exynos5433-tm2.dts results modified, while
exynos5433-tm2-common.dtsi is new. Even though I did:
1. mv exynos5433-tm2.dts exynos5433-tm2-common.dtsi
2. copied pieces from exynos5433-tm2-common.dtsi to a new
exynos5433-tm2.dts
Andi
^ permalink raw reply
* [GIT PULL] firmware: SCPI: fixes for v4.10
From: Sudeep Holla @ 2017-01-03 10:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi ARM SoC Team,
Please pull !
Regards,
Sudeep
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git
tags/scpi-fixes-4.10
for you to fetch changes up to a766347b15c01507db9bf01f9b7021be5a776691:
firmware: arm_scpi: fix reading sensor values on pre-1.0 SCPI
firmwares (2016-12-30 14:53:36 +0000)
----------------------------------------------------------------
SCPI fix for v4.10
A simple fix for reading only lower 32-bit sensor values on pre-1.0 SCPI
firmwares so that upper 32-bit (garbage) value is discarded properly.
----------------------------------------------------------------
Martin Blumenstingl (1):
firmware: arm_scpi: fix reading sensor values on pre-1.0 SCPI
firmwares
drivers/firmware/arm_scpi.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
^ permalink raw reply
* [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
From: Richard Cochran @ 2017-01-03 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFcVECK1vt7Hu4tgSZ2+kKpMxoT-wpikMDq65HaxRv-EMgobHA@mail.gmail.com>
On Tue, Jan 03, 2017 at 10:36:11AM +0530, Harini Katakam wrote:
> I understand that it is not accurate - it is an initial version.
Why do you say, "it is an initial version?"
The Atmel device has this IP core burned in. The core is hopelessly
broken, and it cannot be fixed in SW either, so what is your point?
Thanks,
Richard
^ permalink raw reply
* [GIT PULL] ARM: dts: vexpress: fixes for v4.10
From: Sudeep Holla @ 2017-01-03 10:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi ARM SoC Team,
Please pull !
Regards,
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git
tags/vexpress-fixes-4.10
for you to fetch changes up to 368400e242dc04963ca5ff0b70654f1470344a0a:
ARM: dts: vexpress: Support GICC_DIR operations (2016-12-30 14:54:30
+0000)
----------------------------------------------------------------
ARMv7 VExpress fixes for v4.10
A simple fix to extend GICv2 CPU interface registers from 4K to 8K
on VExpress TC1 and TC2 platforms in order to support split priority
drop and interrupt deactivation.
----------------------------------------------------------------
Christoffer Dall (1):
ARM: dts: vexpress: Support GICC_DIR operations
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
^ permalink raw reply
* [GIT PULL] arm64: dts: vexpress: fixes for v4.10
From: Sudeep Holla @ 2017-01-03 10:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi ARM SoC Team,
Please pull !
Regards,
Sudeep
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git
tags/juno-fixes-4.10
for you to fetch changes up to 1dff32d7df7ff5d80194ebce7ab5755b32564e13:
arm64: dts: vexpress: Support GICC_DIR operations (2016-12-30 15:31:24
+0000)
----------------------------------------------------------------
ARMv8 Juno/VExpress fixes for v4.10
A simple fix to extend GICv2 CPU interface registers from 4K to 8K
on AEMv8 FVP/RTSM models in order to support split priority drop and
interrupt deactivation.
----------------------------------------------------------------
Sudeep Holla (1):
arm64: dts: vexpress: Support GICC_DIR operations
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
^ permalink raw reply
* [PATCH v3 1/2] Doc: devicetree: bindings: Add vendor prefix entry - lwn
From: Lukasz Majewski @ 2017-01-03 10:46 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds entry for LWN - the Liebherr-Werk Nenzing GmbH company to
vendor-prefixes.txt file.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes for v3:
- Update to v4.10-rc2
Changes for v2:
- New patch
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 16d3b5e..8e2abcb 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -164,6 +164,7 @@ lg LG Corporation
linux Linux-specific binding
lltc Linear Technology Corporation
lsi LSI Corp. (LSI Logic)
+lwn Liebherr-Werk Nenzing GmbH
macnica Macnica Americas
marvell Marvell Technology Group Ltd.
maxim Maxim Integrated Products
--
2.1.4
^ permalink raw reply related
* [PATCH v3 2/2] ARM: dts: imx6q: Add mccmon6 board support
From: Lukasz Majewski @ 2017-01-03 10:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1483440381-24268-1-git-send-email-lukma@denx.de>
From: Lukasz Majewski <l.majewski@majess.pl>
This patch provides support for Liebherr's Monitor 6 board (abverrated as
mccmon6) to Linux kernel.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes for v3:
- Reorganize the dts file according to Shawn Guo's comments
Changes for v2:
- Reorganize the dts file according to Valdimir Zapolskiy's comments
---
MCCMON6 board support depends on following patches:
1. "video: backlight: pwm_bl: Initialize fb_bl_on[x] and use_count during pwm_backlight_probe()"
http://patchwork.ozlabs.org/patch/708844/
2. "pwm: imx: Provide atomic operation for IMX PWM driver"
http://patchwork.ozlabs.org/patch/708847/ - http://patchwork.ozlabs.org/patch/708843/
The patch applies to v4.10-rc2
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-mccmon6.dts | 473 ++++++++++++++++++++++++++++++++++++
2 files changed, 474 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-mccmon6.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cccdbcb..316c178 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -393,6 +393,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-marsboard.dtb \
+ imx6q-mccmon6.dtb \
imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \
imx6q-nitrogen6_som2.dtb \
diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts
new file mode 100644
index 0000000..eedbe73
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-mccmon6.dts
@@ -0,0 +1,473 @@
+/*
+ * Copyright 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Liebherr (LWN) monitor6 i.MX6 Quad Board";
+ compatible = "lwn,mccmon6", "fsl,imx6q";
+
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+
+ backlight_lvds: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>;
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100 101 102 103 104 105 106 107 108 109
+ 110 111 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127 128 129
+ 130 131 132 133 134 135 136 137 138 139
+ 140 141 142 143 144 145 146 147 148 149
+ 150 151 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167 168 169
+ 170 171 172 173 174 175 176 177 178 179
+ 180 181 182 183 184 185 186 187 188 189
+ 190 191 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207 208 209
+ 210 211 212 213 214 215 216 217 218 219
+ 220 221 222 223 224 225 226 227 228 229
+ 230 231 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247 248 249
+ 250 251 252 253 254 255>;
+ default-brightness-level = <50>;
+ enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_lvds: regulator-lvds {
+ compatible = "regulator-fixed";
+ regulator-name = "lvds_ppen";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_lvds>;
+ gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ panel-lvds0 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
+ status = "okay";
+
+ s25sl032p: flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pfuze100: pmic at 08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&ldb {
+ status = "okay";
+
+ lvds0: lvds-channel at 0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port at 4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+};
+
+&pwm2 {
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
+ ranges = <0 0 0x08000000 0x08000000>;
+ status = "okay";
+
+ nor at 0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x02000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ use-advanced-sector-protection;
+ fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+ 0x0000c000 0x1404a38e 0x00000000>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_backlight: dispgrp {
+ fsl,pins = <
+ /* BLEN_OUT */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi3_cs: ecspi3csgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000
+ >;
+ };
+
+ pinctrl_ecspi3_flwp: ecspi3flwpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_lvds: reqlvdsgrp {
+ fsl,pins = <
+ /* LVDS_PPEN_OUT */
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
+ >;
+ };
+
+ pinctrl_weim_cs0: weimcs0grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_nor: weimnorgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+ MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+ MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+ MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+ MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+ MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+ MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+ MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+ MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+ MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+ MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+ MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+ MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+ MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+ MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+ MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+ MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+ MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+ MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+ MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+ MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+ MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ >;
+ };
+};
--
2.1.4
^ permalink raw reply related
* [PATCH] mtd: nand: lpc32xx: fix invalid error handling of a requested irq
From: Boris Brezillon @ 2017-01-03 10:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <72ab91ec-a919-af42-8a82-f5d99b245edf@mleia.com>
On Tue, 3 Jan 2017 12:16:26 +0200
Vladimir Zapolskiy <vz@mleia.com> wrote:
> Hi Boris,
>
> On 01/03/2017 11:12 AM, Boris Brezillon wrote:
> > Hi Vladimir
> >
> > On Mon, 5 Dec 2016 03:47:10 +0200
> > Vladimir Zapolskiy <vz@mleia.com> wrote:
> >
> >> Semantics of NR_IRQS is different on machines with SPARSE_IRQ option
> >> disabled or enabled, in the latter case IRQs are allocated starting
> >> at least from the value specified by NR_IRQS and going upwards, so
> >> the check of (irq >= NR_IRQ) to decide about an error code returned by
> >> platform_get_irq() is completely invalid, don't attempt to overrule
> >> irq subsystem in the driver.
> >>
> >> The change fixes LPC32xx NAND MLC driver initialization on boot.
> >
> > Do you need to backport this fix to stable releases? If that's the
> > case, I'll add the Cc: stable tag when applying.
>
> that will be great if you can add
>
> Cc: stable at kernel.org # v4.7+
>
> Please feel free to add also the tag
>
> Fixes: 8cb17b5ed017 ("irqchip: Add LPC32xx interrupt controller driver")
Applied to nand/next (this patch will appear in 4.11).
Thanks,
Boris
>
> --
> With best wishes,
> Vladimir
>
^ permalink raw reply
* [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
From: Rafal Ozieblo @ 2017-01-03 10:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFcVECK1vt7Hu4tgSZ2+kKpMxoT-wpikMDq65HaxRv-EMgobHA@mail.gmail.com>
>From: Harini Katakam [mailto:harinikatakamlinux at gmail.com]
>Sent: 3 stycznia 2017 06:06
>Subject: Re: [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
>
>Hi Richard,
>
>On Mon, Jan 2, 2017 at 9:43 PM, Richard Cochran <richardcochran@gmail.com> wrote:
>> On Mon, Jan 02, 2017 at 03:47:07PM +0100, Nicolas Ferre wrote:
>>> Le 02/01/2017 ? 12:31, Richard Cochran a ?crit :
>>> > This Cadence IP core is a complete disaster.
>>>
>>> Well, it evolved and propose several options to different SoC
>>> integrators. This is not something unusual...
>>> I suspect as well that some other network adapters have the same
>>> weakness concerning PTP timestamp in single register as the early
>>> revisions of this IP.
>>
>> It appears that this core can neither latch the time on read or write,
>> or even latch time stamps. I have worked with many different PTP HW
>> implementations, even early ones like on the ixp4xx, and it is no
>> exaggeration to say that this one is uniquely broken.
>>
>>> I suspect that Rafal tend to jump too quickly to the latest IP
>>> revisions and add more options to this series: let's not try to pour
>>> too much things into this code right now.
>>
>> Why can't you check the IP version in the driver?
>
>There is an IP revision register but it would be probably be better to rely on "caps" from the compatibility strings - to cover SoC specific implementations. Also, when this extended BD is added (with timestamp), additional words will need to be added statically which will be consistent with Andrei's CONFIG_ checks.
We can distinguish IP cores with and without PTP support by reading Design Configuration Register. But to distinguish IP cores with timestamps in buffer descriptors and which support only event registers, we can only check IP version by reading the revision ID register and base on that.
I agree with Harini, compatibility strings could be better. But we might end up with many different configuration in the future.
We could use only descriptor approach but there are many Atmel's cores on the market which support only event registers.
^ permalink raw reply
* [PATCH 3/5] arm64: dts: sun50i: add MMC nodes
From: André Przywara @ 2017-01-03 10:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65GJFTnQZtWHCS7CAtA+Dry94o77aakPLr938BpQksLog@mail.gmail.com>
On 03/01/17 02:52, Chen-Yu Tsai wrote:
Hi,
> On Tue, Jan 3, 2017 at 7:03 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>
> A commit message explaining the mmc controllers would be nice.
OK.
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 67 +++++++++++++++++++++++++++
>> 1 file changed, 67 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> index e0dcab8..c680566 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> @@ -150,6 +150,32 @@
>> pins = "PB8", "PB9";
>> function = "uart0";
>> };
>> +
>> + mmc0_pins: mmc0 at 0 {
>> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
>> + function = "mmc0";
>> + drive-strength = <30>;
>> + };
>> +
>> + mmc0_default_cd_pin: mmc0_cd_pin at 0 {
>> + pins = "PF6";
>> + function = "gpio_in";
>> + bias-pull-up;
>> + };
>
> We are starting to drop pinmux nodes for gpio usage.
And replacing them with what?
Or do you mean they go in the individual board .dts files?
In this case I believe having a default pin defined here would help to
define it in every .dts.
>> +
>> + mmc1_pins: mmc1 at 0 {
>> + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
>> + function = "mmc1";
>> + drive-strength = <30>;
>> + };
>> +
>> + mmc2_pins: mmc2 at 0 {
>> + pins = "PC1", "PC5", "PC6", "PC8", "PC9",
>> + "PC10", "PC11", "PC12", "PC13", "PC14",
>> + "PC15", "PC16";
>> + function = "mmc2";
>> + drive-strength = <30>;
>> + };
>
> Moreover I think you should split out the pinmux nodes to a separate patch.
I can surely do, just wondering what's the rationale is behind that?
>
>> };
>>
>> uart0: serial at 1c28000 {
>> @@ -240,6 +266,47 @@
>> #size-cells = <0>;
>> };
>>
>> + mmc0: mmc at 1c0f000 {
>> + compatible = "allwinner,sun50i-a64-mmc",
>> + "allwinner,sun5i-a13-mmc";
>
> Given that sun5i doesn't support mmc delay timings, and the A64 has
> calibration and delay timings, I wouldn't call them compatible.
>
> Or are you claiming that for the A64 has a delay of 0 for the
> currently supported speeds, so the calibration doesn't really
> matter? If so this should be mentioned in the commit message.
Yes, that's my observation: Driving it with sun5-a13-mmc just works.
This sun5i driver version does not (and will never) support higher
transfer modes anyway, so for that subset they are compatible. This
opens up the door to other operating systems not having a particular
driver for the A64, for instance, also older Linux kernels.
I know that sunxi doesn't use this compatible feature much, but IMHO we
should really start thinking about the DT not just being Linux specific
- or even being specific to a certain Linux version. And this case here
is a good example: An A13 MMC driver can drive this device - if there is
no better driver (an A64 one) available.
>
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ccu 31>, <&ccu 75>;
>
> The clock / reset index macros are in the tree now.
> Please switch to them.
The include file is in the tree, but it isn't used in the current HEAD
(as in #included and the actual macros being used in the .dtsi).
So I was wondering if there is a patch pending for that?
Cheers,
Andre
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu 8>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc1: mmc at 1c10000 {
>> + compatible = "allwinner,sun50i-a64-mmc",
>> + "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&ccu 32>, <&ccu 76>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu 9>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc2: mmc at 1c11000 {
>> + compatible = "allwinner,sun50i-a64-emmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&ccu 33>, <&ccu 77>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu 10>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> gic: interrupt-controller at 1c81000 {
>> compatible = "arm,gic-400";
>> reg = <0x01c81000 0x1000>,
>> --
>> 2.8.2
>>
^ permalink raw reply
* [RFC PATCH net-next v4 1/2] macb: Add 1588 support in Cadence GEM.
From: Harini Katakam @ 2017-01-03 10:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170103102958.GC24780@localhost.localdomain>
Hi Richard,
On Tue, Jan 3, 2017 at 3:59 PM, Richard Cochran
<richardcochran@gmail.com> wrote:
> On Tue, Jan 03, 2017 at 10:36:11AM +0530, Harini Katakam wrote:
>> I understand that it is not accurate - it is an initial version.
>
> Why do you say, "it is an initial version?"
>
> The Atmel device has this IP core burned in. The core is hopelessly
> broken, and it cannot be fixed in SW either, so what is your point?
>
I'm sorry - I just meant that this was before many necessary
enhancements and fixes.
Newer SoCs including ZynqMP (for which the original series was sent)
have the descriptor based approach which is reliable.
Regards,
Harini
^ permalink raw reply
* [PATCH] mtd: nand: fsmc: remove stale non-DT probe path
From: Boris Brezillon @ 2017-01-03 10:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1482060895-26838-1-git-send-email-linus.walleij@linaro.org>
On Sun, 18 Dec 2016 12:34:55 +0100
Linus Walleij <linus.walleij@linaro.org> wrote:
> The FSMC driver has an execution path and a header file in
> <linux/mtd/fsmc.h> that serves to support passing in platform
> data through board files, albeit no upstream users of this
> mechanism exist.
>
> The header file also contains function headers for functions that
> do not exist in the kernel.
>
> Delete this and move the platform data struct, parsing and
> handling into the driver, assume we are using OF and make the
> driver depend on OF, remove the ifdefs making that optional.
Applied.
Thanks,
Boris
>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Vipin Kumar <vipin.kumar@st.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> drivers/mtd/nand/Kconfig | 1 +
> drivers/mtd/nand/fsmc_nand.c | 153 ++++++++++++++++++++++++++++++++++++------
> include/linux/mtd/fsmc.h | 156 -------------------------------------------
> 3 files changed, 133 insertions(+), 177 deletions(-)
> delete mode 100644 include/linux/mtd/fsmc.h
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 353a9ddf6b97..7d5a9cb4594d 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -534,6 +534,7 @@ config MTD_NAND_JZ4780
>
> config MTD_NAND_FSMC
> tristate "Support for NAND on ST Micros FSMC"
> + depends on OF
> depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300
> help
> Enables support for NAND Flash chips on the ST Microelectronics
> diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
> index 4924b43977ef..bda1e4667138 100644
> --- a/drivers/mtd/nand/fsmc_nand.c
> +++ b/drivers/mtd/nand/fsmc_nand.c
> @@ -35,10 +35,133 @@
> #include <linux/mtd/partitions.h>
> #include <linux/io.h>
> #include <linux/slab.h>
> -#include <linux/mtd/fsmc.h>
> #include <linux/amba/bus.h>
> #include <mtd/mtd-abi.h>
>
> +#define FSMC_NAND_BW8 1
> +#define FSMC_NAND_BW16 2
> +
> +#define FSMC_MAX_NOR_BANKS 4
> +#define FSMC_MAX_NAND_BANKS 4
> +
> +#define FSMC_FLASH_WIDTH8 1
> +#define FSMC_FLASH_WIDTH16 2
> +
> +/* fsmc controller registers for NOR flash */
> +#define CTRL 0x0
> + /* ctrl register definitions */
> + #define BANK_ENABLE (1 << 0)
> + #define MUXED (1 << 1)
> + #define NOR_DEV (2 << 2)
> + #define WIDTH_8 (0 << 4)
> + #define WIDTH_16 (1 << 4)
> + #define RSTPWRDWN (1 << 6)
> + #define WPROT (1 << 7)
> + #define WRT_ENABLE (1 << 12)
> + #define WAIT_ENB (1 << 13)
> +
> +#define CTRL_TIM 0x4
> + /* ctrl_tim register definitions */
> +
> +#define FSMC_NOR_BANK_SZ 0x8
> +#define FSMC_NOR_REG_SIZE 0x40
> +
> +#define FSMC_NOR_REG(base, bank, reg) (base + \
> + FSMC_NOR_BANK_SZ * (bank) + \
> + reg)
> +
> +/* fsmc controller registers for NAND flash */
> +#define PC 0x00
> + /* pc register definitions */
> + #define FSMC_RESET (1 << 0)
> + #define FSMC_WAITON (1 << 1)
> + #define FSMC_ENABLE (1 << 2)
> + #define FSMC_DEVTYPE_NAND (1 << 3)
> + #define FSMC_DEVWID_8 (0 << 4)
> + #define FSMC_DEVWID_16 (1 << 4)
> + #define FSMC_ECCEN (1 << 6)
> + #define FSMC_ECCPLEN_512 (0 << 7)
> + #define FSMC_ECCPLEN_256 (1 << 7)
> + #define FSMC_TCLR_1 (1)
> + #define FSMC_TCLR_SHIFT (9)
> + #define FSMC_TCLR_MASK (0xF)
> + #define FSMC_TAR_1 (1)
> + #define FSMC_TAR_SHIFT (13)
> + #define FSMC_TAR_MASK (0xF)
> +#define STS 0x04
> + /* sts register definitions */
> + #define FSMC_CODE_RDY (1 << 15)
> +#define COMM 0x08
> + /* comm register definitions */
> + #define FSMC_TSET_0 0
> + #define FSMC_TSET_SHIFT 0
> + #define FSMC_TSET_MASK 0xFF
> + #define FSMC_TWAIT_6 6
> + #define FSMC_TWAIT_SHIFT 8
> + #define FSMC_TWAIT_MASK 0xFF
> + #define FSMC_THOLD_4 4
> + #define FSMC_THOLD_SHIFT 16
> + #define FSMC_THOLD_MASK 0xFF
> + #define FSMC_THIZ_1 1
> + #define FSMC_THIZ_SHIFT 24
> + #define FSMC_THIZ_MASK 0xFF
> +#define ATTRIB 0x0C
> +#define IOATA 0x10
> +#define ECC1 0x14
> +#define ECC2 0x18
> +#define ECC3 0x1C
> +#define FSMC_NAND_BANK_SZ 0x20
> +
> +#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
> + (FSMC_NAND_BANK_SZ * (bank)) + \
> + reg)
> +
> +#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
> +
> +struct fsmc_nand_timings {
> + uint8_t tclr;
> + uint8_t tar;
> + uint8_t thiz;
> + uint8_t thold;
> + uint8_t twait;
> + uint8_t tset;
> +};
> +
> +enum access_mode {
> + USE_DMA_ACCESS = 1,
> + USE_WORD_ACCESS,
> +};
> +
> +/**
> + * fsmc_nand_platform_data - platform specific NAND controller config
> + * @nand_timings: timing setup for the physical NAND interface
> + * @partitions: partition table for the platform, use a default fallback
> + * if this is NULL
> + * @nr_partitions: the number of partitions in the previous entry
> + * @options: different options for the driver
> + * @width: bus width
> + * @bank: default bank
> + * @select_bank: callback to select a certain bank, this is
> + * platform-specific. If the controller only supports one bank
> + * this may be set to NULL
> + */
> +struct fsmc_nand_platform_data {
> + struct fsmc_nand_timings *nand_timings;
> + struct mtd_partition *partitions;
> + unsigned int nr_partitions;
> + unsigned int options;
> + unsigned int width;
> + unsigned int bank;
> +
> + enum access_mode mode;
> +
> + void (*select_bank)(uint32_t bank, uint32_t busw);
> +
> + /* priv structures for dma accesses */
> + void *read_dma_priv;
> + void *write_dma_priv;
> +};
> +
> static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
> struct mtd_oob_region *oobregion)
> {
> @@ -714,7 +837,6 @@ static bool filter(struct dma_chan *chan, void *slave)
> return true;
> }
>
> -#ifdef CONFIG_OF
> static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
> struct device_node *np)
> {
> @@ -757,13 +879,6 @@ static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
> }
> return 0;
> }
> -#else
> -static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
> - struct device_node *np)
> -{
> - return -ENOSYS;
> -}
> -#endif
>
> /*
> * fsmc_nand_probe - Probe function
> @@ -782,19 +897,15 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
> u32 pid;
> int i;
>
> - if (np) {
> - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> - pdev->dev.platform_data = pdata;
> - ret = fsmc_nand_probe_config_dt(pdev, np);
> - if (ret) {
> - dev_err(&pdev->dev, "no platform data\n");
> - return -ENODEV;
> - }
> - }
> + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> + if (!pdata)
> + return -ENOMEM;
>
> - if (!pdata) {
> - dev_err(&pdev->dev, "platform data is NULL\n");
> - return -EINVAL;
> + pdev->dev.platform_data = pdata;
> + ret = fsmc_nand_probe_config_dt(pdev, np);
> + if (ret) {
> + dev_err(&pdev->dev, "no platform data\n");
> + return -ENODEV;
> }
>
> /* Allocate memory for the device structure (and zero it) */
> diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
> deleted file mode 100644
> index ad3c3488073c..000000000000
> --- a/include/linux/mtd/fsmc.h
> +++ /dev/null
> @@ -1,156 +0,0 @@
> -/*
> - * incude/mtd/fsmc.h
> - *
> - * ST Microelectronics
> - * Flexible Static Memory Controller (FSMC)
> - * platform data interface and header file
> - *
> - * Copyright ? 2010 ST Microelectronics
> - * Vipin Kumar <vipin.kumar@st.com>
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __MTD_FSMC_H
> -#define __MTD_FSMC_H
> -
> -#include <linux/io.h>
> -#include <linux/platform_device.h>
> -#include <linux/mtd/physmap.h>
> -#include <linux/types.h>
> -#include <linux/mtd/partitions.h>
> -#include <asm/param.h>
> -
> -#define FSMC_NAND_BW8 1
> -#define FSMC_NAND_BW16 2
> -
> -#define FSMC_MAX_NOR_BANKS 4
> -#define FSMC_MAX_NAND_BANKS 4
> -
> -#define FSMC_FLASH_WIDTH8 1
> -#define FSMC_FLASH_WIDTH16 2
> -
> -/* fsmc controller registers for NOR flash */
> -#define CTRL 0x0
> - /* ctrl register definitions */
> - #define BANK_ENABLE (1 << 0)
> - #define MUXED (1 << 1)
> - #define NOR_DEV (2 << 2)
> - #define WIDTH_8 (0 << 4)
> - #define WIDTH_16 (1 << 4)
> - #define RSTPWRDWN (1 << 6)
> - #define WPROT (1 << 7)
> - #define WRT_ENABLE (1 << 12)
> - #define WAIT_ENB (1 << 13)
> -
> -#define CTRL_TIM 0x4
> - /* ctrl_tim register definitions */
> -
> -#define FSMC_NOR_BANK_SZ 0x8
> -#define FSMC_NOR_REG_SIZE 0x40
> -
> -#define FSMC_NOR_REG(base, bank, reg) (base + \
> - FSMC_NOR_BANK_SZ * (bank) + \
> - reg)
> -
> -/* fsmc controller registers for NAND flash */
> -#define PC 0x00
> - /* pc register definitions */
> - #define FSMC_RESET (1 << 0)
> - #define FSMC_WAITON (1 << 1)
> - #define FSMC_ENABLE (1 << 2)
> - #define FSMC_DEVTYPE_NAND (1 << 3)
> - #define FSMC_DEVWID_8 (0 << 4)
> - #define FSMC_DEVWID_16 (1 << 4)
> - #define FSMC_ECCEN (1 << 6)
> - #define FSMC_ECCPLEN_512 (0 << 7)
> - #define FSMC_ECCPLEN_256 (1 << 7)
> - #define FSMC_TCLR_1 (1)
> - #define FSMC_TCLR_SHIFT (9)
> - #define FSMC_TCLR_MASK (0xF)
> - #define FSMC_TAR_1 (1)
> - #define FSMC_TAR_SHIFT (13)
> - #define FSMC_TAR_MASK (0xF)
> -#define STS 0x04
> - /* sts register definitions */
> - #define FSMC_CODE_RDY (1 << 15)
> -#define COMM 0x08
> - /* comm register definitions */
> - #define FSMC_TSET_0 0
> - #define FSMC_TSET_SHIFT 0
> - #define FSMC_TSET_MASK 0xFF
> - #define FSMC_TWAIT_6 6
> - #define FSMC_TWAIT_SHIFT 8
> - #define FSMC_TWAIT_MASK 0xFF
> - #define FSMC_THOLD_4 4
> - #define FSMC_THOLD_SHIFT 16
> - #define FSMC_THOLD_MASK 0xFF
> - #define FSMC_THIZ_1 1
> - #define FSMC_THIZ_SHIFT 24
> - #define FSMC_THIZ_MASK 0xFF
> -#define ATTRIB 0x0C
> -#define IOATA 0x10
> -#define ECC1 0x14
> -#define ECC2 0x18
> -#define ECC3 0x1C
> -#define FSMC_NAND_BANK_SZ 0x20
> -
> -#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
> - (FSMC_NAND_BANK_SZ * (bank)) + \
> - reg)
> -
> -#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
> -
> -struct fsmc_nand_timings {
> - uint8_t tclr;
> - uint8_t tar;
> - uint8_t thiz;
> - uint8_t thold;
> - uint8_t twait;
> - uint8_t tset;
> -};
> -
> -enum access_mode {
> - USE_DMA_ACCESS = 1,
> - USE_WORD_ACCESS,
> -};
> -
> -/**
> - * fsmc_nand_platform_data - platform specific NAND controller config
> - * @nand_timings: timing setup for the physical NAND interface
> - * @partitions: partition table for the platform, use a default fallback
> - * if this is NULL
> - * @nr_partitions: the number of partitions in the previous entry
> - * @options: different options for the driver
> - * @width: bus width
> - * @bank: default bank
> - * @select_bank: callback to select a certain bank, this is
> - * platform-specific. If the controller only supports one bank
> - * this may be set to NULL
> - */
> -struct fsmc_nand_platform_data {
> - struct fsmc_nand_timings *nand_timings;
> - struct mtd_partition *partitions;
> - unsigned int nr_partitions;
> - unsigned int options;
> - unsigned int width;
> - unsigned int bank;
> -
> - enum access_mode mode;
> -
> - void (*select_bank)(uint32_t bank, uint32_t busw);
> -
> - /* priv structures for dma accesses */
> - void *read_dma_priv;
> - void *write_dma_priv;
> -};
> -
> -extern int __init fsmc_nor_init(struct platform_device *pdev,
> - unsigned long base, uint32_t bank, uint32_t width);
> -extern void __init fsmc_init_board_info(struct platform_device *pdev,
> - struct mtd_partition *partitions, unsigned int nr_partitions,
> - unsigned int width);
> -
> -#endif /* __MTD_FSMC_H */
^ permalink raw reply
* [PATCH v1] mtd: nand: tango: Reset pbus to raw mode in probe
From: Boris Brezillon @ 2017-01-03 10:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e73bf318-c715-af8c-3fdc-3c5c93a13472@sigmadesigns.com>
On Tue, 3 Jan 2017 11:01:14 +0100
Marc Gonzalez <marc_gonzalez@sigmadesigns.com> wrote:
> Linux should not expect the boot loader to properly configure the
> peripheral bus "pad mode", so reset PBUS_PAD_MODE to raw.
>
Applied to nand/fixes.
Thanks,
Boris
> Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
> ---
> drivers/mtd/nand/tango_nand.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/nand/tango_nand.c b/drivers/mtd/nand/tango_nand.c
> index d370c0382808..2456640fe4d5 100644
> --- a/drivers/mtd/nand/tango_nand.c
> +++ b/drivers/mtd/nand/tango_nand.c
> @@ -644,6 +644,8 @@ static int tango_nand_probe(struct platform_device *pdev)
> if (IS_ERR(nfc->pbus_base))
> return PTR_ERR(nfc->pbus_base);
>
> + writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
> +
> clk = clk_get(&pdev->dev, NULL);
> if (IS_ERR(clk))
> return PTR_ERR(clk);
>
^ permalink raw reply
* [arm-platforms:kvm-arm64/gicv4-wip 9/39] include/linux/irqchip/arm-gic-v3.h:245:32: warning: left shift count >= width of type
From: kbuild test robot @ 2017-01-03 11:02 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/gicv4-wip
head: ff003d7a3416337cc037320bfd175aaee79f05ae
commit: c02d4af9238775c4d1cfed01cf2072bc60d8c1ed [9/39] irqchip/gic-v3-its: Add probing for VLPI properties
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout c02d4af9238775c4d1cfed01cf2072bc60d8c1ed
# save the attached .config to linux build tree
make.cross ARCH=arm
All warnings (new ones prefixed by >>):
In file included from drivers/irqchip/irq-gic-v3-its.c:38:0:
drivers/irqchip/irq-gic-v3-its.c: In function 'its_probe_one':
>> include/linux/irqchip/arm-gic-v3.h:245:32: warning: left shift count >= width of type [-Wshift-count-overflow]
#define GITS_TYPER_VMOVP (1UL << 37)
^
>> drivers/irqchip/irq-gic-v3-its.c:1706:30: note: in expansion of macro 'GITS_TYPER_VMOVP'
if (its->is_v4 && !(typer & GITS_TYPER_VMOVP)) {
^~~~~~~~~~~~~~~~
vim +245 include/linux/irqchip/arm-gic-v3.h
229 #define GITS_CIDR3 0xfffc
230
231 #define GITS_TRANSLATER 0x10040
232
233 #define GITS_CTLR_ENABLE (1U << 0)
234 #define GITS_CTLR_ITS_NUMBER_SHIFT 4
235 #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT)
236 #define GITS_CTLR_QUIESCENT (1U << 31)
237
238 #define GITS_TYPER_PLPIS (1UL << 0)
239 #define GITS_TYPER_VLPIS (1UL << 1)
240 #define GITS_TYPER_IDBITS_SHIFT 8
241 #define GITS_TYPER_DEVBITS_SHIFT 13
242 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
243 #define GITS_TYPER_PTA (1UL << 19)
244 #define GITS_TYPER_HWCOLLCNT_SHIFT 24
> 245 #define GITS_TYPER_VMOVP (1UL << 37)
246
247 #define GITS_CBASER_VALID (1ULL << 63)
248 #define GITS_CBASER_SHAREABILITY_SHIFT (10)
249 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
250 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
251 #define GITS_CBASER_SHAREABILITY_MASK \
252 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
253 #define GITS_CBASER_INNER_CACHEABILITY_MASK \
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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