* [PATCH v2 03/10] dt-bindings: sound: Add new reset compatible for sun4i-i2s
From: Mylene Josserand @ 2017-01-18 8:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170117164636.qhkxvqcs7l732wxk@lukather>
Hi,
On 17/01/2017 17:46, Maxime Ripard wrote:
> On Tue, Jan 17, 2017 at 03:02:23PM +0100, Myl?ne Josserand wrote:
>> Add a new compatible for sun4i-i2s driver to handle some
>> SoCs that have a reset line that must be asserted/deasserted.
>>
>> This new compatible, "allwinner,sun6i-a31-i2s", requires two
>> properties:
>> - resets: phandle to the reset line
>> - reset-names: the name of the reset line ("rst").
>> Except these differences, the compatible is identical to previous one
>> which will not handle a reset line.
>>
>> Signed-off-by: Myl?ne Josserand <mylene.josserand@free-electrons.com>
>> ---
>> .../devicetree/bindings/sound/sun4i-i2s.txt | 23 ++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
>> index 7a2c0945fd22..f673206e309b 100644
>> --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
>> +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
>> @@ -7,6 +7,7 @@ Required properties:
>>
>> - compatible: should be one of the following:
>> - "allwinner,sun4i-a10-i2s"
>> + - "allwinner,sun6i-a31-i2s" for controller with reset lines
>
> That's not only for controllers with reset lines, but for the
> controllers found in the A31 (and later). I'd simply drop the last
> part of that line.
ACK
>
>> - reg: physical base address of the controller and length of memory mapped
>> region.
>> - interrupts: should contain the I2S interrupt.
>> @@ -19,7 +20,13 @@ Required properties:
>> - "mod" : module clock for the I2S controller
>> - #sound-dai-cells : Must be equal to 0
>>
>> +Required properties for the following compatibles:
>> + - "allwinner,sun6i-a31-i2s"
>> +- resets: phandle to the reset line for this codec
>> +- reset-names: Contains the reset signal name "rst"
>
> You don't need reset-names if there's a single reset line.
>
ACK
>> +
>> Example:
>> +For "allwinner,sun4i-a10-i2s":
>>
>> i2s0: i2s at 01c22400 {
>> #sound-dai-cells = <0>;
>> @@ -32,3 +39,19 @@ i2s0: i2s at 01c22400 {
>> <&dma SUN4I_DMA_NORMAL 3>;
>> dma-names = "rx", "tx";
>> };
>> +
>> +For "allwinner,sun6i-a31-i2s":
>> +
>> +dai: dai at 01c22c00 {
>> + #sound-dai-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-i2s";
>> + reg = <0x01c22c00 0x200>;
>> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
>> + clock-names = "apb", "mod";
>> + resets = <&ccu RST_BUS_CODEC>;
>> + reset-names = "rst";
>> + dmas = <&dma 15>, /* AUDIO_CODEC port */
>> + <&dma 15>; /* AUDIO_CODEC port */
>> + dma-names = "rx", "tx";
>> +};
>
> And we already have an example, so there's no need to add a new one
> either.
I will remove it on a V3.
Thank you the review!
--
Myl?ne Josserand, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts
From: Robert Jarzmik @ 2017-01-18 8:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4d97e416-4d32-3b9f-0695-de116a4b26bd@siemens.com>
Jan Kiszka <jan.kiszka@siemens.com> writes:
> On 2017-01-17 08:54, Robert Jarzmik wrote:
>> Jan Kiszka <jan.kiszka@siemens.com> writes:
>>
>>> When using the a device with edge-triggered interrupts, such as MSIs,
>>> the interrupt handler has to ensure that there is a point in time during
>>> its execution where all interrupts sources are silent so that a new
>>> event can trigger a new interrupt again.
>>>
>>> This is achieved here by looping over SSSR evaluation. We need to take
>>> into account that SSCR1 may be changed by the transfer handler, thus we
>>> need to redo the mask calculation, at least regarding the volatile
>>> interrupt enable bit (TIE).
>>>
>>> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
>> Hi Jan,
>>
>>> + while (1) {
>> This bit worries me a bit, as this can be either :
>> - hogging the SoC's CPU, endlessly running
>> - or even worse, blocking the CPU for ever
>>
>> The question behind is, should this be done in a top-half, or moved to a irq
>> thread ?
>
> Every device with a broken interrupt source can hog CPUs, nothing
> special with this one. If you don't close the loop in the handler
> itself, you close it over the hardware retriggering the interrupt over
> and over again.
I'm not speaking of a broken interrupt source, I'm speaking of a broken code,
such as in the handler, or broken status readback, or lack of understanding on
the status register which may imply the while(1) to loop forever.
> So, I don't see a point in offloading to a thread. The normal case is
> some TX done (FIFO available) event followed by an RX event, then the
> transfer is complete, isn't it?
The point is if you stay forever in the while(1) loop, you can at least have a
print a backtrace (LOCKUP_DETECTOR).
>> Imagine that on first iteration the handler returns IRQ_NONE, and on second
>> IRQ_HANDLED. This makes ret IRQ_HANDLED. Yet after the first iteration the
>> handler should have exited, especially if the interrupt is shared with another
>> driver.
>
> That would be a bug in transfer_handler, because we don't enter it
> without a reason (status != 0).
Sure, but can you be sure that all the people modifying the code after you will
see that also ? The other way will _force_ them to see it.
>> Another thing which is along what Andy already said : it would be better
>> practice to have this loop in the form :
>> do {
>> ...
>> } while (exit_condition_not_met);
>
> This implies code duplication in order to calculate the condition
> (mask...). I can do this if desired, I wouldn't do this to my own code,
> though.
Okay, that's acceptable.
Why not have something like this :
sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
if (!(sccr1_reg & SSCR1_TIE))
mask &= ~SSSR_TFS;
/* Ignore RX timeout interrupt if it is disabled */
if (!(sccr1_reg & SSCR1_TINTE))
mask &= ~SSSR_TINT;
status = pxa2xx_spi_read(drv_data, SSR);
while (status & mask) {
... handlers etc ...
status = pxa2xx_spi_read(drv_data, SSR);
};
There is a duplication of the status read, but that looks acceptable, and the
mask calculation is moved out of the loop (this should be checked more
thoroughly as it looked to me only probe() would change these values, yet I
might be wrong).
Cheers.
--
Robert
^ permalink raw reply
* [PATCH v4 3/3] USB3/DWC3: Enable undefined length INCR burst type
From: Changming Huang @ 2017-01-18 8:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484727138-3264-1-git-send-email-jerry.huang@nxp.com>
Enable the undefined length INCR burst type and set INCRx.
Different platform may has the different burst size type.
In order to get best performance, we need to tune the burst size to
one special value, instead of the default value.
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
Changes in v4:
- Modify the codes according to the definition of this property.
Changes in v3:
- add new property for INCR burst in usb node to reset GSBUSCFG0.
Changes in v2:
- split patch
- create one new function to handle soc bus configuration register.
drivers/usb/dwc3/core.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 7 ++++
2 files changed, 90 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 369bab1..446aec3 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -650,6 +650,87 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}
+/* set global soc bus configuration registers */
+static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
+{
+ struct device *dev = dwc->dev;
+ u32 *vals;
+ u32 cfg;
+ int ntype;
+ int ret;
+ int i;
+
+ cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+
+ /*
+ * Handle property "snps,incr-burst-type-adjustment".
+ * Get the number of value from this property:
+ * result <= 0, means this property is not supported.
+ * result = 1, means INCRx burst mode supported.
+ * result > 1, means undefined length burst mode supported.
+ */
+ ntype = device_property_read_u32_array(dev,
+ "snps,incr-burst-type-adjustment", NULL, 0);
+ if (ntype > 0) {
+ vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
+ if (!vals) {
+ dev_err(dev, "Error to get memory\n");
+ return;
+ }
+ /* Get INCR burst type, and parse it */
+ ret = device_property_read_u32_array(dev,
+ "snps,incr-burst-type-adjustment", vals, ntype);
+ if (ret) {
+ dev_err(dev, "Error to get property\n");
+ return;
+ }
+ *(dwc->incrx_type + 1) = vals[0];
+ if (ntype > 1) {
+ *dwc->incrx_type = 1;
+ for (i = 1; i < ntype; i++) {
+ if (vals[i] > *(dwc->incrx_type + 1))
+ *(dwc->incrx_type + 1) = vals[i];
+ }
+ } else
+ *dwc->incrx_type = 0;
+
+ /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
+ cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
+ if (*dwc->incrx_type)
+ cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
+ switch (*(dwc->incrx_type + 1)) {
+ case 256:
+ cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
+ break;
+ case 128:
+ cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
+ break;
+ case 64:
+ cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
+ break;
+ case 32:
+ cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
+ break;
+ case 16:
+ cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
+ break;
+ case 8:
+ cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
+ break;
+ case 4:
+ cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
+ break;
+ case 1:
+ break;
+ default:
+ dev_err(dev, "Invalid property\n");
+ break;
+ }
+ }
+
+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
+}
+
/**
* dwc3_core_init - Low-level initialization of DWC3 Core
* @dwc: Pointer to our controller context structure
@@ -698,6 +779,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
/* Adjust Frame Length */
dwc3_frame_length_adjustment(dwc);
+ dwc3_set_soc_bus_cfg(dwc);
+
usb_phy_set_suspend(dwc->usb2_phy, 0);
usb_phy_set_suspend(dwc->usb3_phy, 0);
ret = phy_power_on(dwc->usb2_generic_phy);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 065aa6f..9df6304 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -805,6 +805,7 @@ struct dwc3_scratchpad_array {
* @regs: base address for our registers
* @regs_size: address space size
* @fladj: frame length adjustment
+ * @incrx_type: INCR burst type adjustment
* @irq_gadget: peripheral controller's IRQ number
* @nr_scratch: number of scratch buffers
* @u1u2: only used on revisions <1.83a for workaround
@@ -928,6 +929,12 @@ struct dwc3 {
enum usb_phy_interface hsphy_mode;
u32 fladj;
+ /*
+ * For INCR burst type.
+ * First field: for undefined length INCR burst type enable.
+ * Second field: for INCRx burst type enable
+ */
+ u32 incrx_type[2];
u32 irq_gadget;
u32 nr_scratch;
u32 u1u2;
--
1.7.9.5
^ permalink raw reply related
* [PATCH v4 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type
From: Changming Huang @ 2017-01-18 8:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484727138-3264-1-git-send-email-jerry.huang@nxp.com>
Property "snps,incr-burst-type-adjustment = <x>, <y>..." for USB3.0 DWC3.
When Just one value means INCRx mode with fix burst type.
When more than one value, means undefined length burst mode, USB controller
can use the length less than or equal to the largest enabled burst length.
While enabling undefined length INCR burst type and INCR16 burst type,
get better write performance on NXP Layerscape platform:
around 3% improvement (from 364MB/s to 375MB/s).
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
---
Changes in v4:
- change definition for this property.
Changes in v3:
- add new property for INCR burst in usb node.
Documentation/devicetree/bindings/usb/dwc3.txt | 6 ++++++
arch/arm/boot/dts/ls1021a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 2 ++
4 files changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index e3e6983..a68dbfc 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -55,6 +55,11 @@ Optional properties:
fladj_30mhz_sdbnd signal is invalid or incorrect.
- <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
+ - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
+ register, undefined length INCR burst type enable and INCRx type.
+ When just one value, which means INCRX burst mode. When more than one
+ value, which means undefined length INCR burst type enabled.
+ The values can be 1, 4, 8, 16, 32, 64, 128 and 256.
This is usually a subnode to DWC3 glue to which it is connected.
@@ -63,4 +68,5 @@ dwc3 at 4a030000 {
reg = <0x4a030000 0xcfff>;
interrupts = <0 92 4>
usb-phy = <&usb2_phy>, <&usb3,phy>;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..6eee0d5 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -627,6 +627,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
pcie at 3400000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 97d331e..04ffd66 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -482,6 +482,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb1: usb3 at 3000000 {
@@ -491,6 +492,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb2: usb3 at 3100000 {
@@ -500,6 +502,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
sata: sata at 3200000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index d058e56..902cc93 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -710,6 +710,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb1: usb3 at 3110000 {
@@ -720,6 +721,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
ccn at 4000000 {
--
1.7.9.5
^ permalink raw reply related
* [PATCH v4 1/3] USB3/DWC3: Add definition for global soc bus configuration register
From: Changming Huang @ 2017-01-18 8:12 UTC (permalink / raw)
To: linux-arm-kernel
Add the macro definition for global soc bus configuration register 0/1
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
---
Changes in v4:
- no change
Changes in v3:
- no change
Changes in v2:
- split the patch
- add more macro definition for soc bus configuration register
drivers/usb/dwc3/core.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index de5a857..065aa6f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -161,6 +161,32 @@
/* Bit fields */
+/* Global SoC Bus Configuration Register 0 */
+#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */
+#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */
+#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */
+#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */
+#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
+#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
+#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
+#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
+#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000
+#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11)
+#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10)
+#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
+#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
+#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
+#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
+#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
+#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
+#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
+#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
+#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
+
+/* Global SoC Bus Configuration Register 1 */
+#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */
+#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00
+
/* Global Debug Queue/FIFO Space Available Register */
#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 02/10] clk: ccu-sun8i-a33: Add CLK_SET_RATE_PARENT to ac-dig
From: Mylene Josserand @ 2017-01-18 7:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170117164415.4qseqbqkdx3e6bvt@lukather>
Hi,
On 17/01/2017 17:44, Maxime Ripard wrote:
> Hi,
>
> On Tue, Jan 17, 2017 at 03:02:22PM +0100, Myl?ne Josserand wrote:
>> The audio DAI needs to set the clock rates of the ac-dig clock.
>> To make it possible, the parent PLL audio clock rates should
>> also be changed. This is possible via "CLK_SET_RATE_PARENT" flag.
>>
>> Signed-off-by: Myl?ne Josserand <mylene.josserand@free-electrons.com>
>
> Please make sure to look at the prefixes usually used in the commit
> titles of the area you're working on. In this case that would have
> been "clk: sunxi-ng:". I fixed it, and applied.
Okay, I will pay more attention to prefixes for commit titles for next
times.
Thank you !
--
Myl?ne Josserand, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v11 09/12] drm/mediatek: add dsi transfer function
From: CK Hu @ 2017-01-18 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484117473-46644-10-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> From: shaoming chen <shaoming.chen@mediatek.com>
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 168 ++++++++++++++++++++++++++++++++++++-
> 1 file changed, 166 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 474861a..b3c7fd8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -24,6 +24,7 @@
> #include <linux/of_graph.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <video/mipi_display.h>
> #include <video/videomode.h>
>
> #include "mtk_drm_ddp_comp.h"
> @@ -80,8 +81,16 @@
> #define DSI_HBP_WC 0x54
> #define DSI_HFP_WC 0x58
>
> +#define DSI_CMDQ_SIZE 0x60
> +#define CMDQ_SIZE 0x3f
> +
> #define DSI_HSTX_CKL_WC 0x64
>
> +#define DSI_RX_DATA0 0x74
> +#define DSI_RX_DATA1 0x78
> +#define DSI_RX_DATA2 0x7c
> +#define DSI_RX_DATA3 0x80
> +
> #define DSI_RACK 0x84
> #define RACK BIT(0)
>
> @@ -117,6 +126,15 @@
> #define CLK_HS_POST (0xff << 8)
> #define CLK_HS_EXIT (0xff << 16)
>
> +#define DSI_CMDQ0 0x180
> +#define CONFIG (0xff << 0)
> +#define SHORT_PACKET 0
> +#define LONG_PACKET 2
> +#define BTA BIT(2)
> +#define DATA_ID (0xff << 8)
> +#define DATA_0 (0xff << 16)
> +#define DATA_1 (0xff << 24)
> +
> #define T_LPX 5
> #define T_HS_PREP 6
> #define T_HS_TRAIL 8
> @@ -125,6 +143,12 @@
>
> #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
>
> +#define MTK_DSI_HOST_IS_READ(type) \
> + ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
> + (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
> + (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> + (type == MIPI_DSI_DCS_READ))
> +
> struct phy;
>
> struct mtk_dsi {
> @@ -497,12 +521,12 @@ static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
> dsi->irq_data |= irq_bit;
> }
>
> -static __maybe_unused void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
> +static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
> {
> dsi->irq_data &= ~irq_bit;
> }
>
> -static __maybe_unused s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
> +static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
> unsigned int timeout)
> {
> s32 ret = 0;
> @@ -832,9 +856,149 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
> return 0;
> }
>
> +static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
> +{
> + u32 timeout_ms = 500000; /* total 1s ~ 2s timeout */
> +
> + while (timeout_ms--) {
> + if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
> + break;
> +
> + usleep_range(2, 4);
> + }
> +
> + if (timeout_ms == 0) {
> + DRM_WARN("polling dsi wait not busy timeout!\n");
> +
> + mtk_dsi_enable(dsi);
> + mtk_dsi_reset_engine(dsi);
> + }
> +}
> +
> +static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
> +{
> + switch (type) {
> + case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
> + case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
> + return 1;
> + case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
> + case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
> + return 2;
> + case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
> + case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
> + return read_data[1] + read_data[2] * 16;
> + case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
> + DRM_INFO("type is 0x02, try again\n");
> + break;
> + default:
> + DRM_INFO("type(0x%x) cannot be non-recognite\n", type);
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
> +{
> + const char *tx_buf = msg->tx_buf;
> + u8 config, cmdq_size, cmdq_off, type = msg->type;
> + u32 reg_val, cmdq_mask, i;
> +
> + if (MTK_DSI_HOST_IS_READ(type))
> + config = BTA;
> + else
> + config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
> +
> + if (msg->tx_len > 2) {
> + cmdq_size = 1 + (msg->tx_len + 3) / 4;
> + cmdq_off = 4;
> + cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
> + reg_val = (msg->tx_len << 16) | (type << 8) | config;
> + } else {
> + cmdq_size = 1;
> + cmdq_off = 2;
> + cmdq_mask = CONFIG | DATA_ID;
> + reg_val = (type << 8) | config;
> + }
> +
> + for (i = 0; i < msg->tx_len; i++)
> + writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
> +
> + mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
> + mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
> +}
> +
> +static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
> + const struct mipi_dsi_msg *msg, u8 flag)
> +{
> + mtk_dsi_wait_for_idle(dsi);
> + mtk_dsi_irq_data_clear(dsi, flag);
> + mtk_dsi_cmdq(dsi, msg);
> + mtk_dsi_start(dsi);
> +
> + if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
> + return -ETIME;
> + else
> + return 0;
> +}
> +
> +static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
> + const struct mipi_dsi_msg *msg)
> +{
> + struct mtk_dsi *dsi = host_to_dsi(host);
> + u32 recv_cnt, i;
> + u8 read_data[16];
> + void *src_addr;
> + u8 irq_flag = CMD_DONE_INT_FLAG;
> +
> + if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
> + DRM_ERROR("dsi engine is not command mode\n");
> + return -EINVAL;
> + }
> +
> + if (MTK_DSI_HOST_IS_READ(msg->type))
> + irq_flag |= LPRX_RD_RDY_INT_FLAG;
> +
> + if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
> + return -ETIME;
> +
> + if (!MTK_DSI_HOST_IS_READ(msg->type))
> + return 0;
> +
> + if (!msg->rx_buf) {
> + DRM_ERROR("dsi receive buffer size may be NULL\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < 16; i++)
> + *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
> +
> + recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
> +
> + if (recv_cnt > 2)
> + src_addr = &read_data[4];
> + else
> + src_addr = &read_data[1];
> +
> + if (recv_cnt > 10)
> + recv_cnt = 10;
> +
> + if (recv_cnt > msg->rx_len)
> + recv_cnt = msg->rx_len;
> +
> + if (recv_cnt)
> + memcpy(msg->rx_buf, src_addr, recv_cnt);
> +
> + DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
> + recv_cnt, *((u8 *)(msg->tx_buf)));
> +
> + return recv_cnt;
> +}
> +
> static const struct mipi_dsi_host_ops mtk_dsi_ops = {
> .attach = mtk_dsi_host_attach,
> .detach = mtk_dsi_host_detach,
> + .transfer = mtk_dsi_host_transfer,
> };
>
> static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
^ permalink raw reply
* [PATCH V2 1/2] kexec: arm64: create identity page table to be used in purgatory
From: Pratyush Anand @ 2017-01-18 7:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <587E53A6.6020709@arm.com>
Hi James,
Thanks for your review.
On Tuesday 17 January 2017 10:55 PM, James Morse wrote:
> Hi Pratyush,
>
> On 19/12/16 07:13, Pratyush Anand wrote:
>> Purgatory sha verification is very slow when D-cache is not enabled there.
>> We need to enable MMU as well to enable D-Cache.Therefore,we need to an
>> identity mapped page table in purgatory.
>>
>> Since debugging is very difficult in purgatory therefore we prefer to do as
>> much work as possible in kexec.
>>
>> This patch prepares page table for purgatory in advance. We support only 4K
>> page table,because it will be available on most of the platform. This page
>> table is passed to the purgatory as a new segment.
>>
>> VA bit is fixed as 48, page table level is 3 where 3rd level page table
>> contains 2M block entries.
>
>> diff --git a/kexec/arch/arm64/kexec-arm64.c b/kexec/arch/arm64/kexec-arm64.c
>> index 04fd3968bb52..c2c8ff1b6940 100644
>> --- a/kexec/arch/arm64/kexec-arm64.c
>> +++ b/kexec/arch/arm64/kexec-arm64.c
>> @@ -24,6 +24,45 @@
>> #include "kexec-syscall.h"
>> #include "arch/options.h"
>>
>> +/*
>> + * kexec creates identity page table to be used in purgatory so that
>> + * dcache verification becomes faster.
>> + *
>> + * These are the definitions to be used by page table creation routine.
>> + *
>> + * Only 4K page table, 3 level, 2M block mapping, 48bit VA is supported
>> + */
>> +#define PGDIR_SHIFT 39
>> +#define PUD_SHIFT 30
>> +#define PMD_SHIFT 21
>> +#define PTRS_PER_PGD 0x1FF
>> +#define PTRS_PER_PUD 0x1FF
>> +#define PTRS_PER_PMD 0x1FF
>
> Aren't these 0x200 for 4K pages in the kernel? It looks like you use them as a
> mask instead.
>
will use definitions as in kernel.
>
>> +#define PMD_TYPE_TABLE (3UL << 0)
>> +#define PMD_TYPE_SECT (1UL << 0)
>> +#define PMD_SECT_AF (1UL << 10)
>> +#define PMD_ATTRINDX(t) ((unsigned long)(t) << 2)
>
>> +#define MT_NORMAL 4
>
> This needs to correspond to the part of MAIR that describes the memory type for
> 'normal'. You define MT_NORMAL again in the next patch, it would be better to
> share the definition so they can't be different. (I don't see why you can't use 0!)
Hummm...Had thought to share the definition, but inclusion of header
file into purgatory code looked like ugly. But I see
purgatory/purgatory.c is including "../kexec/kexec-sha256.h". So,
probably I can do that similarly.
Yes, can use 0 as well, as there is no other memory type now.
>
>
>> +#define PMD_FLAGS_NORMAL (PMD_TYPE_SECT | PMD_SECT_AF)
>> +#define MMU_FLAGS_NORMAL (PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS_NORMAL)
>
> The SH and AP bits are left as zero, which means non-shareable, read/writeable,
> (which I think is fine).
>
>
>> +#define SECTION_SIZE (2 * 1024 * 1024)
>> +#define PAGE_SIZE (4 * 1024)
>> +/* Since we are using 3 level of page tables, therefore minimum number of
>> + * table will be 3. Most likely we will never need more than 3. Each entry
>> + * in level 3 page table can map 2MB memory area. Thus a level 3 page table
>> + * indexed by bit 29:21 can map a total of 1G memory area. Therefore, if
>> + * any segment crosses 1G boundary, then we will need one more level 3
>> + * table. Similarly, level 2 page table indexed by bit 38:30 can map a
>> + * total of 512G memory area. If segment addresses are more than 512G apart
>> + * then we will need two more table for each such block. We do not expect
>> + * any memory segment to cross 512G boundary, however if we will ever wish
>> + * to support uart debugging in purgatory then that might cross the
>> + * boundary and therefore additional 2 more table space. Thus we will need
>> + * maximum of 6 table space.
>
> Surely we only need 6 page_size table entries if we support uart debugging,
> which your 'if we ever' suggests we don't. So surely we only need 3, and a
> comment that this needs expanding to 6 if we need to map two distinct areas.
>
OK, will use 3 now and write comments accordingly.
>
>> + */
>> +#define MAX_PGTBLE_SZ (6 * 4096)
>> +static int next_tbl_cnt = 1;
>> +
>> /* Global varables the core kexec routines expect. */
>>
>> unsigned char reuse_initrd;
>> @@ -316,6 +355,117 @@ unsigned long arm64_locate_kernel_segment(struct kexec_info *info)
>> return hole;
>> }
>>
>> +static unsigned long *create_table_entry(unsigned long *pgtbl_buf,
>> + unsigned long pgtbl_mem, unsigned long *tbl,
>> + unsigned long virt, int shift,
>> + unsigned long ptrs)
>> +{
>> + unsigned long index, desc, offset;
>> +
>> + index = (virt >> shift) & ptrs;
>> + /* check if we have allocated a table already for this index */
>> + if (tbl[index]) {
>> + /*
>> + * table index will have entry as per purgatory page table
>> + * memory. Find out corresponding buffer address of table.
>> + */
>> + desc = tbl[index] & ~3UL;
>> + offset = desc - pgtbl_mem;
>
> wait .. no .. pgtbl_mem is also a guest physical address, so this is fine... its
> not obvious at first glance! You could do with a typedef to make it clear which
> addresses are the guests (pgtable_mem) and which are the hosts (pgtable_buf).
> Something like phys_addr_t?
so may be host_addr_t and guest_addr_t??
>
>
>> + return &pgtbl_buf[offset >> 3];
>> + }
>> +
>> + /*
>> + * Always write page table content as per page table memory allocated
>> + * for purgaory area, but return corresponding buffer area alloced
>
> Nit: purgatory, allocated,
ok.
>
>> + * in kexec
>> + */
>> + if (next_tbl_cnt > 5)
>> + die("%s: No more memory for page table\n", __func__);
>
> die()? With a bit of juggling can't we return an error so we never try to enable
> the MMU+dcache instead?
>
OK. can do that.
>
>> +
>> + tbl[index] = (pgtbl_mem + PAGE_SIZE * next_tbl_cnt) | PMD_TYPE_TABLE;
>> +
>> + return &pgtbl_buf[(next_tbl_cnt++ * PAGE_SIZE) >> 3];
>> +}
>> +
>> +static void craete_block_entry(unsigned long *tbl, unsigned long flags,
>> + unsigned long phys, unsigned long virt)
>
> Why have separate phys and virt parameters if all this ever does is idmap?
Agreed.
>
>
>> +{
>> + unsigned long index;
>> + unsigned long desc;
>> +
>> + index = (virt >> PMD_SHIFT) & PTRS_PER_PMD;
>
> Copying the pmd_index() macro would make this clearer.
Right.
>
>
>> + desc = (phys >> PMD_SHIFT) << PMD_SHIFT;
>
> Looks like you wanted a PMD_MASK.
Right.
>
>
>> + desc |= flags;
>> + tbl[index] = desc;
>> +}
>> +
>> +static void create_identity_entry(unsigned long *pgtbl_buf,
>> + unsigned long pgtbl_mem, unsigned long virt,
>> + unsigned long flags)
>> +{
>> + unsigned long *tbl = pgtbl_buf;
>> +
>> + tbl = create_table_entry(pgtbl_buf, pgtbl_mem, tbl, virt,
>> + PGDIR_SHIFT, PTRS_PER_PGD);
>> + tbl = create_table_entry(pgtbl_buf, pgtbl_mem, tbl, virt,
>> + PUD_SHIFT, PTRS_PER_PUD);
>> + craete_block_entry(tbl, flags, virt, virt);
>
> Nit: create
Ok.
>
>> +}
>> +
>> +/**
>> + * arm64_create_pgtbl_segment - Create page table segments to be used by
>> + * purgatory. Page table will have entries to access memory area of all
>> + * those segments which becomes part of sha verification in purgatory.
>> + * Additionaly, we also create page table for purgatory segment as well.
>
> Nit: additionally,
Ok.
>
>> + */
>> +
>> +static int arm64_create_pgtbl_segment(struct kexec_info *info,
>> + unsigned long hole_min, unsigned long hole_max)
>> +{
>> + unsigned long *pgtbl_buf;
>> + int i;
>> + unsigned long mstart, mend, pgtbl_mem;
>> + unsigned long purgatory_base, purgatory_len;
>> +
>> + pgtbl_buf = xmalloc(MAX_PGTBLE_SZ);
>> + memset(pgtbl_buf, 0, MAX_PGTBLE_SZ);
>
>> + pgtbl_mem = add_buffer_phys_virt(info, pgtbl_buf, MAX_PGTBLE_SZ,
>> + MAX_PGTBLE_SZ, PAGE_SIZE, hole_min, hole_max, 1, 0);
>
> I want to check what this does, but this all looks like it is doing the right thing.
>
>
>> + for (i = 0; i < info->nr_segments; i++) {
>> + if (info->segment[i].mem == (void *)info->rhdr.rel_addr) {
>> + purgatory_base = (unsigned long)info->segment[i].mem;
>> + purgatory_len = info->segment[i].memsz;
>> + }
>> + mstart = (unsigned long)info->segment[i].mem;
>> + mend = mstart + info->segment[i].memsz;
>> + mstart &= ~(SECTION_SIZE - 1);
>> + while (mstart < mend) {
>> + create_identity_entry(pgtbl_buf, pgtbl_mem,
>> + mstart, MMU_FLAGS_NORMAL);
>> + mstart += SECTION_SIZE;
>> + }
>> + }
>
~Pratyush
^ permalink raw reply
* [PATCH v6 23/25] usb: chipidea: Pullup D+ in device mode via phy APIs
From: Peter Chen @ 2017-01-18 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <148467591341.23457.3638889856786813589@sboyd-linaro>
On Tue, Jan 17, 2017 at 09:58:33AM -0800, Stephen Boyd wrote:
> Quoting Peter Chen (2017-01-15 19:45:51)
> >
> > So, you need to call phy_set_mode when switching between host and device.
> > Besides, you also need to toggle VBUSVLDEXT when the external vbus
> > is on or off at device mode (doesn't need for host mode), is it correct?
>
> Correct.
>
> >
> > At include/linux/usb/phy.h, we have .set_vbus interface, maybe you need
> > to port it to generic phy framework.
> >
>
> Ok. I'll look into that. Can the other patches in this series be picked
> up? Otherwise I can resend them all again once I fix the phy_set_mode()
> call location and introduce a new phy op.
I can pick up chipidea patches after you test the patch I supplied at:
[PATCH v6 11/25] usb: chipidea: vbus event may exist before starting
gadget
You may ping other maintainers to pick up other patches.
--
Best Regards,
Peter Chen
^ permalink raw reply
* [PATCH] ARM: dts: sun6i: sina31s: Enable USB OTG controller in peripheral mode
From: Maxime Ripard @ 2017-01-18 7:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170118010105.20069-1-wens@csie.org>
On Wed, Jan 18, 2017 at 09:01:05AM +0800, Chen-Yu Tsai wrote:
> While the SinA31s does have a proper 5-pin mini USB OTG port, the ID
> pin does not seem to work. The pin used in the schematics is always low,
> regardless of the attached OTG cable or SoC internal pin bias settings.
>
> The v1.5 board is missing bias resistors shown in the schematics for
> earlier revisions, and the connections of the remaining one does not
> match the schematics either.
>
> In addition, VBUS for this port is disconnected from the board's 5V
> power rail. The board features a pad to solder jumper pins to connect
> VBUS to 5V manually.
>
> Given the above and the fact that the board has 5 more USB host ports,
> it makes more sense to have the OTG port work in peripheral mode.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v1] arm64: mm: avoid name clash in __page_to_voff()
From: Oleksandr Andrushchenko @ 2017-01-18 7:09 UTC (permalink / raw)
To: linux-arm-kernel
From: Oleksandr Andrushchenko <Oleksandr_Andrushchenko@epam.com>
The arm64 __page_to_voff() macro takes a parameter called 'page', and
also refers to 'struct page'. Thus, if the value passed in is not
called 'page', we'll refer to the wrong struct name (which might not
exist).
Fixes: 3fa72fe9c614 ("arm64: mm: fix __page_to_voff definition")
Acked-by: Mark Rutland <mark.rutland@arm.com>
Suggested-by: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
Signed-off-by: Oleksandr Andrushchenko <Oleksandr_Andrushchenko@epam.com>
---
Changes since initital:
* use better description.
arch/arm64/include/asm/memory.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index bfe632808d77..90c39a662379 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -222,7 +222,7 @@ static inline void *phys_to_virt(phys_addr_t x)
#define _virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
#else
#define __virt_to_pgoff(kaddr) (((u64)(kaddr) & ~PAGE_OFFSET) / PAGE_SIZE * sizeof(struct page))
-#define __page_to_voff(page) (((u64)(page) & ~VMEMMAP_START) * PAGE_SIZE / sizeof(struct page))
+#define __page_to_voff(kaddr) (((u64)(kaddr) & ~VMEMMAP_START) * PAGE_SIZE / sizeof(struct page))
#define page_to_virt(page) ((void *)((__page_to_voff(page)) | PAGE_OFFSET))
#define virt_to_page(vaddr) ((struct page *)((__virt_to_pgoff(vaddr)) | VMEMMAP_START))
--
2.7.4
^ permalink raw reply related
* [linux-sunxi] Re: [PATCH] ASoC: sunxi: Add bindings for sun8i to SPDIF
From: Code Kipper @ 2017-01-18 7:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170117181531.fdwc5vglpvxpx7su@sirena.org.uk>
On 17 January 2017 at 19:15, Mark Brown <broonie@kernel.org> wrote:
> On Thu, Jan 12, 2017 at 06:33:43PM +0100, codekipper at gmail.com wrote:
>> From: Marcus Cooper <codekipper@gmail.com>
>>
>> The H3 SoC uses the same SPDIF block as found in earlier SoCs, but the
>> transmit fifo is at a different address.
>>
>> Signed-off-by: Marcus Cooper <codekipper@gmail.com>
>> ---
>> Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt | 1 +
>> 1 file changed, 1 insertion(+)
>
> This is fine but it doesn't actually add the compatible string to the
> driver which I'd expect.
Hi Mark,
I missed the binding documentation on the patch for the driver so I
pushed it separately instead of pushing a new patch version.
You can find it under the subject heading 'ASoC: sun4i-spdif: Add
support for the H3 SoC' and Maxime has ACK it (on the condition that I
add the binding doc).
BR,
CK
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe at googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply
* [PATCH v5 3/4] dmaengine: pl330: Store pointer to slave device
From: Marek Szyprowski @ 2017-01-18 7:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170117172445.3itztktiay22as26@kozik-lap>
Hi Krzysztof,
On 2017-01-17 18:29, Krzysztof Kozlowski wrote:
> On Tue, Jan 17, 2017 at 01:48:57PM +0100, Marek Szyprowski wrote:
>> Store the pointer to slave device, which requested our channel. It will be
>> later used to implement runtime PM of PL330 DMA controller. Although
>> DMA channels might be requested many times, each DMA peripheral channel is
>> physically dedicated only for specific hardware, so there should be only
>> one slave device for each channel.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> Acked-by: Arnd Bergmann <arnd@arndb.de>
> Any particular reason for removing my Reviewed-by? Any changes here?
No changes here. I'm sorry, the tag got lost during rebase.
> Best regards,
> Krzysztof
>
>> ---
>> drivers/dma/pl330.c | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
>> index b6b2cc912380..c77a3494659c 100644
>> --- a/drivers/dma/pl330.c
>> +++ b/drivers/dma/pl330.c
>> @@ -450,6 +450,7 @@ struct dma_pl330_chan {
>>
>> /* for runtime pm tracking */
>> bool active;
>> + struct device *slave;
>> };
>>
>> struct pl330_dmac {
>> @@ -2093,6 +2094,14 @@ static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
>> if (chan_id >= pl330->num_peripherals)
>> return NULL;
>>
>> + if (!pl330->peripherals[chan_id].slave) {
>> + pl330->peripherals[chan_id].slave = slave;
>> + } else if (pl330->peripherals[chan_id].slave != slave) {
>> + dev_err(pl330->ddma.dev,
>> + "Can't use same channel with multiple slave devices!\n");
>> + return NULL;
>> + }
>> +
>> return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
>> }
>>
>> --
>> 1.9.1
>>
>
>
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply
* [PATCH net-next v4 05/10] drivers: base: Add device_find_in_class_name()
From: Greg Kroah-Hartman @ 2017-01-18 7:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170117232152.1661-6-f.fainelli@gmail.com>
On Tue, Jan 17, 2017 at 03:21:47PM -0800, Florian Fainelli wrote:
> Add a helper function to lookup a device reference given a class name.
> This is a preliminary patch to remove adhoc code from net/dsa/dsa.c and
> make it more generic.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> drivers/base/core.c | 31 +++++++++++++++++++++++++++++++
> include/linux/device.h | 2 ++
> 2 files changed, 33 insertions(+)
My NAK still stands here, please give me a day or so to respond to the
other thread about this...
thanks,
greg k-h
^ permalink raw reply
* [PATCH net-next v3 06/10] net: dsa: Migrate to device_find_class()
From: Greg KH @ 2017-01-18 7:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <912e6143-c67a-d909-2a6c-939de79efc5d@gmail.com>
On Mon, Jan 16, 2017 at 12:01:02PM -0800, Florian Fainelli wrote:
> On 01/15/2017 11:16 AM, Andrew Lunn wrote:
> >>> What exactly is the relationship between these devices (a ascii-art tree
> >>> or sysfs tree output might be nice) so I can try to understand what is
> >>> going on here.
> >
> > Hi Greg, Florian
> >
> > A few diagrams and trees which might help understand what is going on.
> >
> > The first diagram comes from the 2008 patch which added all this code:
> >
> > +-----------+ +-----------+
> > | | RGMII | |
> > | +-------+ +------ 1000baseT MDI ("WAN")
> > | | | 6-port +------ 1000baseT MDI ("LAN1")
> > | CPU | | ethernet +------ 1000baseT MDI ("LAN2")
> > | |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
> > | +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
> > | | | |
> > +-----------+ +-----------+
> >
> > We have an ethernet switch and a host CPU. The switch is connected to
> > the CPU in two different ways. RGMII allows us to get Ethernet frames
> > from the CPU into the switch. MIImgmt, is the management bus normally
> > used for Ethernet PHYs, but Marvell switches also use it for Managing
> > switches.
> >
> > The diagram above is the simplest setup. You can have multiple
> > Ethernet switches, connected together via switch ports. Each switch
> > has its own MIImgmt connect to the CPU, but there is only one RGMII
> > link.
> >
> > When this code was designed back in 2008, it was decided to represent
> > this is a platform device, and it has a platform_data, which i have
> > slightly edited to keep it simple:
> >
> > struct dsa_platform_data {
> > /*
> > * Reference to a Linux network interface that connects
> > * to the root switch chip of the tree.
> > */
> > struct device *netdev;
> >
> > /*
> > * Info structs describing each of the switch chips
> > * connected via this network interface.
> > */
> > int nr_chips;
> > struct dsa_chip_data *chip;
> > };
> >
> > This netdev is the CPU side of the RGMII interface.
> >
> > Each switch has a dsa_chip_data, again edited:
> >
> > struct dsa_chip_data {
> > /*
> > * How to access the switch configuration registers.
> > */
> > struct device *host_dev;
> > int sw_addr;
> > ...
> > }
> >
> > The host_dev is the CPU side of the MIImgmt, and we have the address
> > the switch is using on the bus.
> >
> > During probe of this platform device, we need to get from the
> > struct device *netdev to a struct net_device *dev.
> >
> > So the code looks in the device net class to find the device
> >
> > | | | |-- f1074000.ethernet
> > | | | | |-- deferred_probe
> > | | | | |-- driver -> ../../../../../bus/platform/drivers/mvneta
> > | | | | |-- driver_override
> > | | | | |-- modalias
> > | | | | |-- net
> > | | | | | `-- eth1
> > | | | | | |-- addr_assign_type
> > | | | | | |-- address
> > | | | | | |-- addr_len
> > | | | | | |-- broadcast
> > | | | | | |-- carrier
> > | | | | | |-- carrier_changes
> > | | | | | |-- deferred_probe
> > | | | | | |-- device -> ../../../f1074000.ethernet
> >
> > and then use container_of() to get the net_device.
> >
> > Similarly, the code needs to get from struct device *host_dev to a struct mii_bus *.
> >
> > | | | |-- f1072004.mdio
> > | | | | |-- deferred_probe
> > | | | | |-- driver -> ../../../../../bus/platform/drivers/orion-mdio
> > | | | | |-- driver_override
> > | | | | |-- mdio_bus
> > | | | | | `-- f1072004.mdio-mi
> > | | | | | |-- deferred_probe
> > | | | | | |-- device -> ../../../f1072004.mdio
> >
>
> Thanks Andrew! Greg, does that make it clearer how these devices
> references are used, do you still think the way this is done is wrong,
> too cautious, or valid?
I'm still not sold on it, I think there is something odd here with your
use/assumptions of the driver model. Give me a few days to catch up
with other stuff to respond back please...
thanks,
greg k-h
^ permalink raw reply
* [PATCH v3 2/2] arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
From: Pankaj Dubey @ 2017-01-18 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484721173-30474-1-git-send-email-pankaj.dubey@samsung.com>
From: Vivek Gautam <gautamvivek1987@gmail.com>
Adding fixed voltage regulators for Vbus and Vbus-boost required
by USB 3.0 DRD controller on Exynos7-espresso board.
Signed-off-by: Vivek Gautam <gautamvivek1987@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45 +++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 1b2db9f0..e4705fd 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -13,6 +13,7 @@
#include "exynos7.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Samsung Exynos7 Espresso board based on EXYNOS7";
@@ -32,6 +33,29 @@
device_type = "memory";
reg = <0x0 0x40000000 0x0 0xC0000000>;
};
+
+ usb30_vbus_reg: regulator-usb30 {
+ compatible = "regulator-fixed";
+ regulator-name = "VBUS_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gph1 1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_vbus_en>;
+ enable-active-high;
+ };
+
+ usb3drd_boost_5v: regulator-usb3drd-boost {
+ compatible = "regulator-fixed";
+ regulator-name = "VUSB_VBUS_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpf4 1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3drd_boost_en>;
+ enable-active-high;
+ };
+
};
&fin_pll {
@@ -365,3 +389,24 @@
vqmmc-supply = <&ldo2_reg>;
disable-wp;
};
+
+&usbdrd_phy {
+ vbus-supply = <&usb30_vbus_reg>;
+ vbus-boost-supply = <&usb3drd_boost_5v>;
+};
+
+&pinctrl_bus1 {
+ usb30_vbus_en: usb30-vbus-en {
+ samsung,pins = "gph1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ usb3drd_boost_en: usb3drd-boost-en {
+ samsung,pins = "gpf4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/2] arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
From: Pankaj Dubey @ 2017-01-18 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484721173-30474-1-git-send-email-pankaj.dubey@samsung.com>
From: Vivek Gautam <gautamvivek1987@gmail.com>
Add USB 3.0 DRD controller device node, with its clock
and phy information to enable the same on Exynos7.
Signed-off-by: Vivek Gautam <gautamvivek1987@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 34 +++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 80aa60e..9a3fbed 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -603,6 +603,40 @@
#include "exynos7-trip-points.dtsi"
};
};
+
+ usbdrd_phy: phy at 15500000 {
+ compatible = "samsung,exynos7-usbdrd-phy";
+ reg = <0x15500000 0x100>;
+ clocks = <&clock_fsys0 ACLK_USBDRD300>,
+ <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
+ <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
+ <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
+ <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
+ clock-names = "phy", "ref", "phy_pipe",
+ "phy_utmi", "itp";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <1>;
+ };
+
+ usbdrd3 {
+ compatible = "samsung,exynos7-dwusb3";
+ clocks = <&clock_fsys0 ACLK_USBDRD300>,
+ <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
+ <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
+ clock-names = "usbdrd30", "usbdrd30_susp_clk",
+ "usbdrd30_axius_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dwc3 at 15400000 {
+ compatible = "snps,dwc3";
+ reg = <0x15400000 0x10000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH v3 0/2] Add USB DRD 3.0 device node for Exynos7
From: Pankaj Dubey @ 2017-01-18 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CGME20170118063006epcas5p28e5430460e604e9c1017ea0a46c89baa@epcas5p2.samsung.com>
This patch series adds USB 3.0 DRD device node for Exynos7 and
required Vbus and Vbus-boost support for espresso dev boards.
These patches are part of patch series [1] earlier submitted by Vivek
While other patches in these series got merged, DTS related change were
left. I have prepared and tested these patches on top of krzk/for-next and
my patch series "Use macros for pinctrl configuration on Exynos7" [2].
[1]: https://lkml.org/lkml/2014/11/21/247
[2]: https://www.spinics.net/lists/arm-kernel/msg555333.html
Changes since v1:
- Updated S-o-B order and Authorship of patches.
- Added Javier's Reviewed-by.
- Replaced GPIO polarity values with appropriate macros.
Changes since v2:
- Changed order of S-o-B and R-o-B lines
- Removed address node from parent usb node
- Replaced pinctrl configuration values with macros
Vivek Gautam (2):
arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 45 +++++++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 34 +++++++++++++++++++
2 files changed, 79 insertions(+)
--
2.7.4
^ permalink raw reply
* [PATCH v11 08/12] drm/mediatek: add dsi interrupt control
From: CK Hu @ 2017-01-18 6:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484117473-46644-9-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> From: shaoming chen <shaoming.chen@mediatek.com>
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 92 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 6f4b3bb..474861a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -18,6 +18,7 @@
> #include <drm/drm_panel.h>
> #include <linux/clk.h>
> #include <linux/component.h>
> +#include <linux/irq.h>
> #include <linux/of.h>
> #include <linux/of_platform.h>
> #include <linux/of_graph.h>
> @@ -29,6 +30,16 @@
>
> #define DSI_START 0x00
>
> +#define DSI_INTEN 0x08
> +
> +#define DSI_INTSTA 0x0c
> +#define LPRX_RD_RDY_INT_FLAG BIT(0)
> +#define CMD_DONE_INT_FLAG BIT(1)
> +#define TE_RDY_INT_FLAG BIT(2)
> +#define VM_DONE_INT_FLAG BIT(3)
> +#define EXT_TE_RDY_INT_FLAG BIT(4)
> +#define DSI_BUSY BIT(31)
> +
> #define DSI_CON_CTRL 0x10
> #define DSI_RESET BIT(0)
> #define DSI_EN BIT(1)
> @@ -71,6 +82,9 @@
>
> #define DSI_HSTX_CKL_WC 0x64
>
> +#define DSI_RACK 0x84
> +#define RACK BIT(0)
> +
> #define DSI_PHY_LCCON 0x104
> #define LC_HS_TX_EN BIT(0)
> #define LC_ULPM_EN BIT(1)
> @@ -137,6 +151,8 @@ struct mtk_dsi {
> struct videomode vm;
> int refcount;
> bool enabled;
> + u32 irq_data;
> + wait_queue_head_t irq_wait_queue;
> };
>
> static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
> @@ -469,6 +485,64 @@ static void mtk_dsi_start(struct mtk_dsi *dsi)
> writel(1, dsi->regs + DSI_START);
> }
>
> +static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
> +{
> + u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
> +
> + writel(inten, dsi->regs + DSI_INTEN);
> +}
> +
> +static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
> +{
> + dsi->irq_data |= irq_bit;
> +}
> +
> +static __maybe_unused void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
> +{
> + dsi->irq_data &= ~irq_bit;
> +}
> +
> +static __maybe_unused s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
> + unsigned int timeout)
> +{
> + s32 ret = 0;
> + unsigned long jiffies = msecs_to_jiffies(timeout);
> +
> + ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
> + dsi->irq_data & irq_flag,
> + jiffies);
> + if (ret == 0) {
> + DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
> +
> + mtk_dsi_enable(dsi);
> + mtk_dsi_reset_engine(dsi);
> + }
> +
> + return ret;
> +}
> +
> +static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
> +{
> + struct mtk_dsi *dsi = dev_id;
> + u32 status, tmp;
> + u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
> +
> + status = readl(dsi->regs + DSI_INTSTA) & flag;
> +
> + if (status) {
> + do {
> + mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
> + tmp = readl(dsi->regs + DSI_INTSTA);
> + } while (tmp & DSI_BUSY);
> +
> + mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
> + mtk_dsi_irq_data_set(dsi, status);
> + wake_up_interruptible(&dsi->irq_wait_queue);
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
> {
> if (WARN_ON(dsi->refcount == 0))
> @@ -517,6 +591,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
>
> mtk_dsi_ps_control_vact(dsi);
> mtk_dsi_config_vdo_timing(dsi);
> + mtk_dsi_set_interrupt_enable(dsi);
>
> mtk_dsi_set_mode(dsi);
> mtk_dsi_clk_hs_mode(dsi, 1);
> @@ -818,6 +893,7 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> struct device_node *remote_node, *endpoint;
> struct resource *regs;
> + int irq_num;
> int comp_id;
> int ret;
>
> @@ -894,6 +970,22 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> return ret;
> }
>
> + irq_num = platform_get_irq(pdev, 0);
> + if (irq_num < 0) {
> + dev_err(&pdev->dev, "failed to request dsi irq resource\n");
> + return -EPROBE_DEFER;
> + }
> +
> + irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
> + ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
> + IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
> + return -EPROBE_DEFER;
> + }
> +
> + init_waitqueue_head(&dsi->irq_wait_queue);
> +
> platform_set_drvdata(pdev, dsi);
>
> return component_add(&pdev->dev, &mtk_dsi_component_ops);
^ permalink raw reply
* [PATCH 6/6] dt-bindings: mt8173-mtu3: add reference clock
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun@mediatek.com>
add a reference clock for compatibility
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/usb/mt8173-mtu3.txt | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
index e049d19..8c976cd 100644
--- a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
+++ b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
@@ -10,7 +10,7 @@ Required properties:
- vusb33-supply : regulator of USB avdd3.3v
- clocks : a list of phandle + clock-specifier pairs, one for each
entry in clock-names
- - clock-names : must contain "sys_ck" for clock of controller;
+ - clock-names : must contain "sys_ck" and "ref_ck" for clock of controller;
"wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are
depends on "mediatek,enable-wakeup"
- phys : a list of phandle + phy specifier pairs
@@ -56,10 +56,10 @@ ssusb: usb at 11271000 {
phys = <&phy_port0 PHY_TYPE_USB3>,
<&phy_port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
<&pericfg CLK_PERI_USB0>,
<&pericfg CLK_PERI_USB1>;
- clock-names = "sys_ck",
+ clock-names = "sys_ck", "ref_ck",
"wakeup_deb_p0",
"wakeup_deb_p1";
vusb33-supply = <&mt6397_vusb_reg>;
@@ -79,8 +79,8 @@ ssusb: usb at 11271000 {
reg-names = "mac";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>;
- clock-names = "sys_ck";
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+ clock-names = "sys_ck", "ref_ck";
vusb33-supply = <&mt6397_vusb_reg>;
status = "disabled";
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 5/6] dt-bindings: mt8173-xhci: add reference clock
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun@mediatek.com>
add a reference clock for compatibility
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/usb/mt8173-xhci.txt | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
index 2a930bd..ab8bb27 100644
--- a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
@@ -23,6 +23,7 @@ Required properties:
entry in clock-names
- clock-names : must contain
"sys_ck": for clock of xHCI MAC
+ "ref_ck": for reference clock of xHCI MAC
"wakeup_deb_p0": for USB wakeup debounce clock of port0
"wakeup_deb_p1": for USB wakeup debounce clock of port1
@@ -47,10 +48,10 @@ usb30: usb at 11270000 {
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
<&pericfg CLK_PERI_USB0>,
<&pericfg CLK_PERI_USB1>;
- clock-names = "sys_ck",
+ clock-names = "sys_ck", "ref_ck",
"wakeup_deb_p0",
"wakeup_deb_p1";
phys = <&phy_port0 PHY_TYPE_USB3>,
@@ -82,6 +83,7 @@ Required properties:
entry in clock-names
- clock-names : must be
"sys_ck": for clock of xHCI MAC
+ "ref_ck": for reference clock of xHCI MAC
Optional properties:
- vbus-supply : reference to the VBUS regulator;
@@ -94,8 +96,8 @@ usb30: usb at 11270000 {
reg-names = "mac";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>;
- clock-names = "sys_ck";
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+ clock-names = "sys_ck", "ref_ck";
vusb33-supply = <&mt6397_vusb_reg>;
usb3-lpm-capable;
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/6] arm64: dts: mt8173: add reference clock for usb
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun@mediatek.com>
add 26M reference clock for ssusb and xhci nodes
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 07fd2eb..e2862b6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -729,9 +729,11 @@
<&u2port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ <&clk26m>,
<&pericfg CLK_PERI_USB0>,
<&pericfg CLK_PERI_USB1>;
clock-names = "sys_ck",
+ "ref_ck",
"wakeup_deb_p0",
"wakeup_deb_p1";
mediatek,syscon-wakeup = <&pericfg>;
@@ -746,8 +748,8 @@
reg-names = "mac";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
- clocks = <&topckgen CLK_TOP_USB30_SEL>;
- clock-names = "sys_ck";
+ clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
+ clock-names = "sys_ck", "ref_ck";
status = "disabled";
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/6] usb: xhci-mtk: add reference clock
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun@mediatek.com>
usually, the reference clock comes from 26M oscillator directly,
but some SoCs are not, add it for compatibility.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/usb/host/xhci-mtk.c | 15 +++++++++++++++
drivers/usb/host/xhci-mtk.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 1094ebd..4d75ac5 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -212,6 +212,12 @@ static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
{
int ret;
+ ret = clk_prepare_enable(mtk->ref_clk);
+ if (ret) {
+ dev_err(mtk->dev, "failed to enable ref_clk\n");
+ goto ref_clk_err;
+ }
+
ret = clk_prepare_enable(mtk->sys_clk);
if (ret) {
dev_err(mtk->dev, "failed to enable sys_clk\n");
@@ -238,6 +244,8 @@ static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
usb_p0_err:
clk_disable_unprepare(mtk->sys_clk);
sys_clk_err:
+ clk_disable_unprepare(mtk->ref_clk);
+ref_clk_err:
return -EINVAL;
}
@@ -248,6 +256,7 @@ static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
clk_disable_unprepare(mtk->wk_deb_p0);
}
clk_disable_unprepare(mtk->sys_clk);
+ clk_disable_unprepare(mtk->ref_clk);
}
/* only clocks can be turn off for ip-sleep wakeup mode */
@@ -550,6 +559,12 @@ static int xhci_mtk_probe(struct platform_device *pdev)
return PTR_ERR(mtk->sys_clk);
}
+ mtk->ref_clk = devm_clk_get(dev, "ref_ck");
+ if (IS_ERR(mtk->ref_clk)) {
+ dev_err(dev, "fail to get ref_ck\n");
+ return PTR_ERR(mtk->ref_clk);
+ }
+
mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
ret = usb_wakeup_of_property_parse(mtk, node);
diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
index 2845c49..3aa5e1d 100644
--- a/drivers/usb/host/xhci-mtk.h
+++ b/drivers/usb/host/xhci-mtk.h
@@ -124,6 +124,7 @@ struct xhci_hcd_mtk {
struct regulator *vusb33;
struct regulator *vbus;
struct clk *sys_clk; /* sys and mac clock */
+ struct clk *ref_clk;
struct clk *wk_deb_p0; /* port0's wakeup debounce clock */
struct clk *wk_deb_p1;
struct regmap *pericfg;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/6] usb: mtu3: add reference clock
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484719707-12107-1-git-send-email-chunfeng.yun@mediatek.com>
usually, the reference clock comes from 26M oscillator directly,
but some SoCs are not, add it for compatibility.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/usb/mtu3/mtu3.h | 1 +
drivers/usb/mtu3/mtu3_plat.c | 21 +++++++++++++++++++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
index ba9df71..aa6fd6a 100644
--- a/drivers/usb/mtu3/mtu3.h
+++ b/drivers/usb/mtu3/mtu3.h
@@ -225,6 +225,7 @@ struct ssusb_mtk {
/* common power & clock */
struct regulator *vusb33;
struct clk *sys_clk;
+ struct clk *ref_clk;
/* otg */
struct otg_switch_mtk otg_switch;
enum usb_dr_mode dr_mode;
diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
index 6344859..19a345d 100644
--- a/drivers/usb/mtu3/mtu3_plat.c
+++ b/drivers/usb/mtu3/mtu3_plat.c
@@ -123,7 +123,13 @@ static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
ret = clk_prepare_enable(ssusb->sys_clk);
if (ret) {
dev_err(ssusb->dev, "failed to enable sys_clk\n");
- goto clk_err;
+ goto sys_clk_err;
+ }
+
+ ret = clk_prepare_enable(ssusb->ref_clk);
+ if (ret) {
+ dev_err(ssusb->dev, "failed to enable ref_clk\n");
+ goto ref_clk_err;
}
ret = ssusb_phy_init(ssusb);
@@ -143,8 +149,10 @@ static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
phy_err:
ssusb_phy_exit(ssusb);
phy_init_err:
+ clk_disable_unprepare(ssusb->ref_clk);
+ref_clk_err:
clk_disable_unprepare(ssusb->sys_clk);
-clk_err:
+sys_clk_err:
regulator_disable(ssusb->vusb33);
vusb33_err:
@@ -154,6 +162,7 @@ static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
{
clk_disable_unprepare(ssusb->sys_clk);
+ clk_disable_unprepare(ssusb->ref_clk);
regulator_disable(ssusb->vusb33);
ssusb_phy_power_off(ssusb);
ssusb_phy_exit(ssusb);
@@ -216,6 +225,12 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
return PTR_ERR(ssusb->sys_clk);
}
+ ssusb->ref_clk = devm_clk_get(dev, "ref_ck");
+ if (IS_ERR(ssusb->ref_clk)) {
+ dev_err(dev, "failed to get ref clock\n");
+ return PTR_ERR(ssusb->ref_clk);
+ }
+
ssusb->num_phys = of_count_phandle_with_args(node,
"phys", "#phy-cells");
if (ssusb->num_phys > 0) {
@@ -428,6 +443,7 @@ static int __maybe_unused mtu3_suspend(struct device *dev)
ssusb_host_disable(ssusb, true);
ssusb_phy_power_off(ssusb);
clk_disable_unprepare(ssusb->sys_clk);
+ clk_disable_unprepare(ssusb->ref_clk);
ssusb_wakeup_enable(ssusb);
return 0;
@@ -445,6 +461,7 @@ static int __maybe_unused mtu3_resume(struct device *dev)
ssusb_wakeup_disable(ssusb);
clk_prepare_enable(ssusb->sys_clk);
+ clk_prepare_enable(ssusb->ref_clk);
ssusb_phy_power_on(ssusb);
ssusb_host_enable(ssusb);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/6] usb: mtu3: get resources that cause deferred probe earlier
From: Chunfeng Yun @ 2017-01-18 6:08 UTC (permalink / raw)
To: linux-arm-kernel
Some resources such as regulator, clock usually cause deferred
probe, get them earlier to avoid more ineffective processing.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/usb/mtu3/mtu3_plat.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c
index 7833678..6344859 100644
--- a/drivers/usb/mtu3/mtu3_plat.c
+++ b/drivers/usb/mtu3/mtu3_plat.c
@@ -204,6 +204,18 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
int i;
int ret;
+ ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
+ if (IS_ERR(ssusb->vusb33)) {
+ dev_err(dev, "failed to get vusb33\n");
+ return PTR_ERR(ssusb->vusb33);
+ }
+
+ ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
+ if (IS_ERR(ssusb->sys_clk)) {
+ dev_err(dev, "failed to get sys clock\n");
+ return PTR_ERR(ssusb->sys_clk);
+ }
+
ssusb->num_phys = of_count_phandle_with_args(node,
"phys", "#phy-cells");
if (ssusb->num_phys > 0) {
@@ -230,18 +242,6 @@ static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
return PTR_ERR(ssusb->ippc_base);
}
- ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
- if (IS_ERR(ssusb->vusb33)) {
- dev_err(dev, "failed to get vusb33\n");
- return PTR_ERR(ssusb->vusb33);
- }
-
- ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
- if (IS_ERR(ssusb->sys_clk)) {
- dev_err(dev, "failed to get sys clock\n");
- return PTR_ERR(ssusb->sys_clk);
- }
-
ssusb->dr_mode = usb_get_dr_mode(dev);
if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
dev_err(dev, "dr_mode is error\n");
--
1.7.9.5
^ permalink raw reply related
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