* [PATCH RFC 0/4] crypto: engine - Permit to enqueue all async requests
From: Fabien DESSENNE @ 2017-12-06 10:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171129084121.9385-1-clabbe.montjoie@gmail.com>
Hi Corentin,
I am fine with this proposal: it is generic enough and I have been able
to test and run the crypto engine with aead_request without changing any
single line of code.
This is what I need to be able to send the AEAD extension of the
stm32-cryp driver (successfully tested with your engine upgrade proposal).
I have also tested the stm32-hash patch.
Note that stm32-cryp (new driver applied by Herbert recently
[https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git/commit/?id=9e054ec21ef8344345b28603fb272fe999f735db])
would also need to be converted to the new crypto engine API : this is a
trivial patch.
Thank you for your proposal, I hope that this proposal is fine for
Herbert too.
BR
Fabien
On 29/11/17 09:41, Corentin Labbe wrote:
> Hello
>
> The current crypto_engine support only ahash and ablkcipher.
> My first patch which try to add skcipher was Nacked, it will add too many functions
> and adding other algs(aead, asymetric_key) will make the situation worst.
>
> This patchset remove all algs specific stuff and now only process generic crypto_async_request.
>
> The requests handler function pointer are now moved out of struct engine and
> are now stored directly in a crypto_engine_reqctx.
>
> The original proposal of Herbert [1] cannot be done completly since the crypto_engine
> could only dequeue crypto_async_request and it is impossible to access any request_ctx
> without knowing the underlying request type.
>
> So I do something near that was requested: adding crypto_engine_reqctx in TFM context.
> Note that the current implementation expect that crypto_engine_reqctx
> is the first member of the context.
>
> The first patch convert the crypto engine with the new way,
> while the following patchs convert the 3 existing users of crypto_engine.
> Note that this split break bisection, so probably the final commit will be all merged.
>
> The 3 latest patch were compile tested only, but the first is tested successfully
> with my new sun8i-ce driver.
>
> Regards
>
> [1] https://www.mail-archive.com/linux-kernel at vger.kernel.org/msg1474434.html
>
> Corentin Labbe (4):
> crypto: engine - Permit to enqueue all async requests
> crypto: omap: convert to new crypto engine API
> crypto: virtio: convert to new crypto engine API
> crypto: stm32: convert to the new crypto engine API
>
> crypto/crypto_engine.c | 188 ++++++---------------------
> drivers/crypto/omap-aes.c | 21 ++-
> drivers/crypto/omap-aes.h | 3 +
> drivers/crypto/omap-des.c | 24 +++-
> drivers/crypto/stm32/stm32-hash.c | 22 +++-
> drivers/crypto/virtio/virtio_crypto_algs.c | 15 ++-
> drivers/crypto/virtio/virtio_crypto_common.h | 2 +-
> drivers/crypto/virtio/virtio_crypto_core.c | 3 -
> include/crypto/engine.h | 46 +++----
> 9 files changed, 122 insertions(+), 202 deletions(-)
>
^ permalink raw reply
* [PATCH v6 7/8] KVM: arm/arm64: Provide a get_input_level for the arch timer
From: Christoffer Dall @ 2017-12-06 10:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205152446.rcmkowdnuhkqbrdb@yury-thinkpad>
On Tue, Dec 05, 2017 at 06:24:46PM +0300, Yury Norov wrote:
> On Mon, Dec 04, 2017 at 09:05:05PM +0100, Christoffer Dall wrote:
> > From: Christoffer Dall <christoffer.dall@linaro.org>
> >
> > The VGIC can now support the life-cycle of mapped level-triggered
> > interrupts, and we no longer have to read back the timer state on every
> > exit from the VM if we had an asserted timer interrupt signal, because
> > the VGIC already knows if we hit the unlikely case where the guest
> > disables the timer without ACKing the virtual timer interrupt.
> >
> > This means we rework a bit of the code to factor out the functionality
> > to snapshot the timer state from vtimer_save_state(), and we can reuse
> > this functionality in the sync path when we have an irqchip in
> > userspace, and also to support our implementation of the
> > get_input_level() function for the timer.
> >
> > This change also means that we can no longer rely on the timer's view of
> > the interrupt line to set the active state, because we no longer
> > maintain this state for mapped interrupts when exiting from the guest.
> > Instead, we only set the active state if the virtual interrupt is
> > active, and otherwise we simply let the timer fire again and raise the
> > virtual interrupt from the ISR.
> >
> > Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> > ---
> > include/kvm/arm_arch_timer.h | 2 ++
> > virt/kvm/arm/arch_timer.c | 75 +++++++++++++++++++++-----------------------
> > 2 files changed, 38 insertions(+), 39 deletions(-)
> >
> > diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
> > index 01ee473517e2..f57f795d704c 100644
> > --- a/include/kvm/arm_arch_timer.h
> > +++ b/include/kvm/arm_arch_timer.h
> > @@ -90,6 +90,8 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu);
> >
> > void kvm_timer_init_vhe(void);
> >
> > +bool kvm_arch_timer_get_input_level(int vintid);
> > +
> > #define vcpu_vtimer(v) (&(v)->arch.timer_cpu.vtimer)
> > #define vcpu_ptimer(v) (&(v)->arch.timer_cpu.ptimer)
> >
>
> [...]
>
> > +bool kvm_arch_timer_get_input_level(int vintid)
> > +{
> > + struct kvm_vcpu *vcpu = kvm_arm_get_running_vcpu();
> > + struct arch_timer_context *timer;
> > +
> > + if (vintid == vcpu_vtimer(vcpu)->irq.irq)
> > + timer = vcpu_vtimer(vcpu);
> > + else
> > + BUG(); /* We only map the vtimer so far */
> > +
> > + if (timer->loaded)
> > + __timer_snapshot_state(timer);
> > +
> > + return kvm_timer_should_fire(timer);
> > +}
>
> I think it worth to reword to highlight your intention about BUG,
> and save 1 call to vcpu_vtimer()
>
> bool kvm_arch_timer_get_input_level(int vintid)
> {
> struct kvm_vcpu *vcpu = kvm_arm_get_running_vcpu();
> struct arch_timer_context *timer = vcpu_vtimer(vcpu);
>
> /* We only map the vtimer so far */
> BUG_ON(vintid != timer->irq.irq)
>
> if (timer->loaded)
> __timer_snapshot_state(timer);
>
> return kvm_timer_should_fire(timer);
> }
>
Besides the incredible bikesheding nature of your comments, I disagree.
The current code suggests where to add functionality once we move to
using the physical timer hardware to drive an EL1 physical timer on VHE
systems, and is purposely written this way.
I'm sure we have real bugs and real issues in the code, perhaps you
could spend your energy looking for those, and if you cannot find any,
then provide a reviewed-by instead of these pointless cosmetic
adjustments.
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH] arm64/mm: Do not write ASID generation to ttbr0
From: James Morse @ 2017-12-06 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4f4572cf-9ae1-24b9-ec46-d8bbc6179426@arm.com>
Hi Julien,
On 06/12/17 10:17, Julien Thierry wrote:
> On 05/12/17 19:33, James Morse wrote:
>> On 05/12/17 17:38, Julien Thierry wrote:
>>> When writing the user ASID to ttbr0, 16bit get copied to ttbr0, potentially
>>> including part of the ASID generation in the ttbr0.ASID. If the kernel is
>>> using less than 16bits ASIDs and the other ttbr0 bits aren't RES0, two
>>> tasks using the same mm context might end up running with different
>>> ttbr0.ASID values.
>>> This would be triggered by one of the threads being scheduled before a
>>> roll-over and the second one scheduled after a roll-over.
>>>
>>> Pad the generation out of the 16bits of the mm id that are written to
>>> ttbr0. Thus, what the hardware sees is what the kernel considers ASID.
>>
>> Is this to fix a system with a mix of 8/16 asid bits? Or someone being clever
>> and reducing asid_bits to stress rollover?
> So it was motivated by the later. But hopefully the fix, pushing the generation
> always over 16bits is also suitable for hardware that mixes 8/16bits asids. If
> it is not, do call it out.
(okay, wasn't clear from the commit message!)
>>> diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
>>> index 6f40170..a7c72d4 100644
>>> --- a/arch/arm64/mm/context.c
>>> +++ b/arch/arm64/mm/context.c
>>> @@ -180,6 +190,13 @@ static u64 new_context(struct mm_struct *mm, unsigned
>>> int cpu)
>>> /* We're out of ASIDs, so increment the global generation count */
>>> generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION,
>>> &asid_generation);
>>> +
>>> + /*
>>> + * It is unlikely the generation will ever overflow, but if this
>>> + * happens, let it be known strange things can occur.
>>> + */
>>> + WARN_ON(generation == ASID_FIRST_VERSION);
>>
>> Won't generation wrap to zero, not '1<<16'?
>
> Yes it will! Silly me...
>
>>
>> asid_generation-is-never-zero is one of the nasty things in this code.
>>
>> In check_and_switch_context() we switch to the 'fast path' where the current
>> asid is usable if: the generation matches and the active_asid isn't 0 (which
>> indicates a rollover has occurred).
>>
>> from mm/context.c::check_and_switch_context():
>>> if (!((asid ^ atomic64_read(&asid_generation)) >> asid_bits)
>>> && atomic64_xchg_relaxed(&per_cpu(active_asids, cpu), asid))
>>> goto switch_mm_fastpath;
>>
>>
>> If asid_generation is ever zero, (even briefly) multiple new tasks with
>> different pages-tables will pass the generation test, and run with asid=0.
>>
>> Short of xchg(ASID_MAX_VERSION, ASID_FIRST_VERSION), every time, just in case, I
>> don't think this is something we can handle.
>>
>> But, this thing is layers on layers of subtle behaviour, so I may have missed
>> something...
> I had not thought of that. However I believe we checked with 48bits and the case
> of the generation overflowing would take a human life span (or something on that
> scale) of a system running and spawning continuous processes before reaching
This scales with the number of CPUs, and how quickly they can fork().
(Not using all the counter bits makes me nervous.)
> this. Which is why we decided on having a WARN_ON for now. So I don't know if we
> want to change things for this corner case which really means "things are going
> bad" more than anything else.
But it fires the generation after the chaos started, so if we ever do see this
it gives us false-confidence that generation-overflow wasn't the issue.
WARN_ON(generation == ASID_MAX_VERSION) ?
>> Instead, do you think we can duplicate just the asid bits (asid & ASID_MASK)
>> into a new 16bit field in mm_context_t, which we then use instead of the ASID()
>> and mmid macros? (We only set a new asid in one place as returned by
>> new_context()).
>>
>
> I'm not sure I understand why this prevents running with asid = 0 when
> generation is 0.
Sorry, I was talking about two things. It doesn't, I don't think we can do
anything about that.
This was a suggestion for an alternative way of stopping generation bits getting
into the TTBR, which still lets use use all the counter bits. (and lets us mess
with asid_bits to stress rollover without re-inventing this bug).
>> This would let context.c's asid_bits be arbitrary, as the hardware only uses the
>> masked value it exposes in the new field.
>>
>> This doesn't solve the mixed 8/16 bit case. I think we should force those
>> systems to use 8bit asids via cpufeature to preserve as much of the generation
>> counter as possible.
> Hmmm right, I see that today we just panic the kernel when we have a smaller
> asid size than the boot cpu...
> So if we boot on a 8bit asid cpu it should work but not the other way around...
> I agree we probably should find a way to reduce the size of software asids
> system wide when we find a cpu has less bits available.
cpufeature has some stuff for 'LOWER_SAFE' that might help here..
Thanks,
James
^ permalink raw reply
* [PATCH v6 2/8] KVM: arm/arm64: Factor out functionality to get vgic mmio requester_vcpu
From: Christoffer Dall @ 2017-12-06 10:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205134608.msg6wvh7px273mud@yury-thinkpad>
On Tue, Dec 05, 2017 at 04:46:08PM +0300, Yury Norov wrote:
> On Mon, Dec 04, 2017 at 09:05:00PM +0100, Christoffer Dall wrote:
> > From: Christoffer Dall <christoffer.dall@linaro.org>
> >
> > We are about to distinguish between userspace accesses and mmio traps
> > for a number of the mmio handlers. When the requester vcpu is NULL, it
> > mens we are handling a userspace acccess.
>
> Typo: means?
>
yes
> > Factor out the functionality to get the request vcpu into its own
> > function, mostly so we have a common place to document the semantics of
> > the return value.
> >
> > Also take the chance to move the functionality outside of holding a
> > spinlock and instead explicitly disable and enable preemption. This
> > supports PREEMPT_RT kernels as well.
> >
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> > Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> > ---
> > virt/kvm/arm/vgic/vgic-mmio.c | 44 +++++++++++++++++++++++++++----------------
> > 1 file changed, 28 insertions(+), 16 deletions(-)
> >
> > diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
> > index deb51ee16a3d..747b0a3b4784 100644
> > --- a/virt/kvm/arm/vgic/vgic-mmio.c
> > +++ b/virt/kvm/arm/vgic/vgic-mmio.c
> > @@ -122,6 +122,27 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
> > return value;
> > }
> >
> > +/*
> > + * This function will return the VCPU that performed the MMIO access and
> > + * trapped from twithin the VM, and will return NULL if this is a userspace
>
> Typo: from within?
>
yes
> > + * access.
> > + *
> > + * We can disable preemption locally around accessing the per-CPU variable,
> > + * and use the resolved vcpu pointer after enabling preemption again, because
> > + * even if the current thread is migrated to another CPU, reading the per-CPU
> > + * value later will give us the same value as we update the per-CPU variable
> > + * in the preempt notifier handlers.
> > + */
> > +static struct kvm_vcpu *vgic_get_mmio_requester_vcpu(void)
> > +{
> > + struct kvm_vcpu *vcpu;
> > +
> > + preempt_disable();
> > + vcpu = kvm_arm_get_running_vcpu();
> > + preempt_enable();
> > + return vcpu;
> > +}
> > +
> > void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
> > gpa_t addr, unsigned int len,
> > unsigned long val)
> > @@ -184,24 +205,10 @@ unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
> > static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
> > bool new_active_state)
> > {
> > - struct kvm_vcpu *requester_vcpu;
> > unsigned long flags;
> > - spin_lock_irqsave(&irq->irq_lock, flags);
> > + struct kvm_vcpu *requester_vcpu = vgic_get_mmio_requester_vcpu();
> >
> > - /*
> > - * The vcpu parameter here can mean multiple things depending on how
> > - * this function is called; when handling a trap from the kernel it
> > - * depends on the GIC version, and these functions are also called as
> > - * part of save/restore from userspace.
> > - *
> > - * Therefore, we have to figure out the requester in a reliable way.
> > - *
> > - * When accessing VGIC state from user space, the requester_vcpu is
> > - * NULL, which is fine, because we guarantee that no VCPUs are running
> > - * when accessing VGIC state from user space so irq->vcpu->cpu is
> > - * always -1.
> > - */
> > - requester_vcpu = kvm_arm_get_running_vcpu();
> > + spin_lock_irqsave(&irq->irq_lock, flags);
> >
> > /*
> > * If this virtual IRQ was written into a list register, we
> > @@ -213,6 +220,11 @@ static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
> > * vgic_change_active_prepare) and still has to sync back this IRQ,
> > * so we release and re-acquire the spin_lock to let the other thread
> > * sync back the IRQ.
> > + *
> > + * When accessing VGIC state from user space, requester_vcpu is
> > + * NULL, which is fine, because we guarantee that no VCPUs are running
> > + * when accessing VGIC state from user space so irq->vcpu->cpu is
> > + * always -1.
> > */
> > while (irq->vcpu && /* IRQ may have state in an LR somewhere */
> > irq->vcpu != requester_vcpu && /* Current thread is not the VCPU thread */
> > --
> > 2.14.2
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH 1/3] arm64: KVM: Move CPU ID reg trap setup off the world switch path
From: Christoffer Dall @ 2017-12-06 10:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205123150.GX22781@e103592.cambridge.arm.com>
On Tue, Dec 05, 2017 at 12:31:51PM +0000, Dave Martin wrote:
> On Tue, Dec 05, 2017 at 10:09:15AM +0100, Christoffer Dall wrote:
> > On Fri, Dec 01, 2017 at 03:19:40PM +0000, Dave Martin wrote:
> > > The HCR_EL2.TID3 flag needs to be set when trapping guest access to
> > > the CPU ID registers is required. However, the decision about
> > > whether to set this bit does not need to be repeated at every
> > > switch to the guest.
> > >
> > > Instead, it's sufficient to make this decision once and record the
> > > outcome.
> > >
> > > This patch moves the decision to vcpu_reset_hcr() and records the
> > > choice made in vcpu->arch.hcr_el2. The world switch code can then
> > > load this directly when switching to the guest without the need for
> > > conditional logic on the critical path.
> > >
> > > Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> > > Suggested-by: Christoffer Dall <christoffer.dall@linaro.org>
> > > Cc: Marc Zyngier <marc.zyngier@arm.com>
> >
> > Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
> >
> > >
> > > ---
> > >
> > > Note to maintainers: this was discussed on-list [1] prior to the merge
> > > window, but this patch implementing the agreed decision hasn't been
> > > posted previously.
> > >
> > > This should be considered a fix for v4.15.
> >
> > It's actually easier for me to apply this for v4.16 and base my VHE
> > optimization patches on it.
>
> If you're happy for this optimisation to be missing for v4.15, I'm fine
> with that.
>
> Can I leave it you to pick this up then?
Yes, I applied it to our queue already.
>
> I'll repost the other stuff from this series separately for Will to
> take care of.
>
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core
From: Geert Uytterhoeven @ 2017-12-06 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170915110609.GL3924@verge.net.au>
Hi Simon,
On Fri, Sep 15, 2017 at 1:06 PM, Simon Horman <horms@verge.net.au> wrote:
> On Fri, Sep 15, 2017 at 08:57:53AM +0000, Fabrizio Castro wrote:
>> > -----Original Message-----
>> > From: linux-renesas-soc-owner at vger.kernel.org [mailto:linux-renesas-soc-owner at vger.kernel.org] On Behalf Of Geert
>> > Uytterhoeven
>> > Sent: 15 September 2017 09:05
>> > To: Simon Horman <horms@verge.net.au>; Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>> > Cc: Chris Paterson <Chris.Paterson2@renesas.com>; Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
>> > Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>; devicetree at vger.kernel.org; Linux-Renesas
>> > <linux-renesas-soc@vger.kernel.org>; linux-arm-kernel at lists.infradead.org; Geert Uytterhoeven <geert+renesas@glider.be>
>> > Subject: Re: [PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core
>> >
>> > Hi Simon, Fabrizio,
>> >
>> > On Fri, Sep 15, 2017 at 9:45 AM, Simon Horman <horms@verge.net.au> wrote:
>> > > On Wed, Sep 13, 2017 at 06:05:34PM +0100, Chris Paterson wrote:
>> > >> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>> > >>
>> > >> Add DT node for the Advanced Power Management Unit (APMU), add the
>> > >> second CPU core, and use "renesas,apmu" as "enable-method".
>> > >>
>> > >> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>> > >> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
>> > >> ---
>> > >> This patch is based on renesas-devel-20170913-v4.13.
>> > >
>> > > Hi,
>> > >
>> > > with reference to "[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2"
>> > > is the CNTVOFF initialised in the boot loader of boards (in upstream)
>> > > for this SoC? If not I expect you will have trouble with the arch timer
>> > > on secondary CPU cores.
>>
>> I can confirm that this patch relies on:
>> * "ARM: Add definition for monitor mode", and
>> * "ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15 "
>> as the bootloader doesn't initialize CNTVOFF.
>>
>> >
>> > Exactly my question.
>> >
>> > Fabrizio: Given your feedback on "[PATCH v3 0/3] ARM: renesas: Enable SMP on
>> > R-Car E2", I think SMP enablement on RZ/G1E has to be postponed until "ARM:
>> > shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15" has been
>> > accepted upstream.
>>
>> You are right, somehow we missed the comment made by Simon on Monday:
>>
>> " I would like to deffer the third and last patch until v4.16 to avoid
>> an awkward branch dependency on the above - the branches are different
>> even though the tree is the same. Please resubmit this patch once the
>> above dependencies are present in an rc release, which at this stage
>> I expect to be v4.15-rc1."
>>
>> Apologies for this, we will send this patch later on, once both patches have been
>> accepted upstream.
>
> No problem, I will mark this one as deferred.
As the dependency is in v4.15-rc1, it can be applied now.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] ARM: dts: colibri/apalis: use correct compatible for RTC
From: Stefan Agner @ 2017-12-06 10:29 UTC (permalink / raw)
To: linux-arm-kernel
All Toradex Carrier Boards use a st,m41t0 compatible RTC. Compared
to a st,m41t00 this RTC has also an oscillator fail bit which allows
to detect when the RTC lost track of time.
Cc: Sanchayan Maity <maitysanchayan@gmail.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 2 +-
arch/arm/boot/dts/imx6q-apalis-eval.dts | 2 +-
arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 2 +-
arch/arm/boot/dts/imx6q-apalis-ixora.dts | 2 +-
arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 2 +-
arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 5705ebee0595..dcf9206f3e0d 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -163,7 +163,7 @@
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc at 68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
index 8b56656e53da..aa0e631f3c0a 100644
--- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -158,7 +158,7 @@
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc at 68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
index 27dc0fc686a9..e8dccf552122 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -170,7 +170,7 @@
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc at 68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 40b2c67fe7af..6831dfd24cc1 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -174,7 +174,7 @@
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc at 68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index 3d6c282dd258..3cf9b077d4f3 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -133,7 +133,7 @@
/* M41T0M6 real time clock on carrier board */
rtc: m41t0m6 at 68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 091b738041a0..d8b2972527eb 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -140,7 +140,7 @@
/* M41T0M6 real time clock on carrier board */
rtc: m41t0m6 at 68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
--
2.15.1
^ permalink raw reply related
* [kernel-hardening][PATCH v4 3/3] arm: mm: dump: add checking for writable and executable pages
From: Jinbum Park @ 2017-12-06 10:26 UTC (permalink / raw)
To: linux-arm-kernel
Page mappings with full RWX permissions are a security risk.
x86, arm64 has an option to walk the page tables
and dump any bad pages.
(1404d6f13e47
("arm64: dump: Add checking for writable and exectuable pages"))
Add a similar implementation for arm.
Signed-off-by: Jinbum Park <jinb.park7@gmail.com>
---
v4: Add boolean for ro_bit, nx_bit into prot_bits
to point ro_bit, nx_bit in pg_level.
Remove unnecessary %p in WARN_ONCE().
---
arch/arm/Kconfig.debug | 27 ++++++++++++++++++++
arch/arm/include/asm/ptdump.h | 8 ++++++
arch/arm/mm/dump.c | 58 ++++++++++++++++++++++++++++++++++++++++++-
arch/arm/mm/init.c | 2 ++
4 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e7b94db..78a6470 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -20,6 +20,33 @@ config ARM_PTDUMP_DEBUGFS
kernel.
If in doubt, say "N"
+config DEBUG_WX
+ bool "Warn on W+X mappings at boot"
+ select ARM_PTDUMP_CORE
+ ---help---
+ Generate a warning if any W+X mappings are found at boot.
+
+ This is useful for discovering cases where the kernel is leaving
+ W+X mappings after applying NX, as such mappings are a security risk.
+
+ Look for a message in dmesg output like this:
+
+ arm/mm: Checked W+X mappings: passed, no W+X pages found.
+
+ or like this, if the check failed:
+
+ arm/mm: Checked W+X mappings: FAILED, <N> W+X pages found.
+
+ Note that even if the check fails, your kernel is possibly
+ still fine, as W+X mappings are not a security hole in
+ themselves, what they do is that they make the exploitation
+ of other unfixed kernel bugs easier.
+
+ There is no runtime or memory usage effect of this option
+ once the kernel has booted up - it's a one time check.
+
+ If in doubt, say "Y".
+
# RMK wants arm kernels compiled with frame pointers or stack unwinding.
# If you know what you are doing and are willing to live without stack
# traces, you can get a slightly smaller kernel by setting this option to
diff --git a/arch/arm/include/asm/ptdump.h b/arch/arm/include/asm/ptdump.h
index 3a6c0b7..b6a0162 100644
--- a/arch/arm/include/asm/ptdump.h
+++ b/arch/arm/include/asm/ptdump.h
@@ -43,6 +43,14 @@ static inline int ptdump_debugfs_register(struct ptdump_info *info,
}
#endif /* CONFIG_ARM_PTDUMP_DEBUGFS */
+void ptdump_check_wx(void);
+
#endif /* CONFIG_ARM_PTDUMP_CORE */
+#ifdef CONFIG_DEBUG_WX
+#define debug_checkwx() ptdump_check_wx()
+#else
+#define debug_checkwx() do { } while (0)
+#endif
+
#endif /* __ASM_PTDUMP_H */
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index 43a2bee..084779c 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -52,6 +52,8 @@ struct pg_state {
unsigned long start_address;
unsigned level;
u64 current_prot;
+ bool check_wx;
+ unsigned long wx_pages;
const char *current_domain;
};
@@ -60,6 +62,8 @@ struct prot_bits {
u64 val;
const char *set;
const char *clear;
+ bool ro_bit;
+ bool nx_bit;
};
static const struct prot_bits pte_bits[] = {
@@ -73,11 +77,13 @@ struct prot_bits {
.val = L_PTE_RDONLY,
.set = "ro",
.clear = "RW",
+ .ro_bit = true,
}, {
.mask = L_PTE_XN,
.val = L_PTE_XN,
.set = "NX",
.clear = "x ",
+ .nx_bit = true,
}, {
.mask = L_PTE_SHARED,
.val = L_PTE_SHARED,
@@ -141,11 +147,13 @@ struct prot_bits {
.val = L_PMD_SECT_RDONLY | PMD_SECT_AP2,
.set = "ro",
.clear = "RW",
+ .ro_bit = true,
#elif __LINUX_ARM_ARCH__ >= 6
{
.mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
.val = PMD_SECT_APX | PMD_SECT_AP_WRITE,
.set = " ro",
+ .ro_bit = true,
}, {
.mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
.val = PMD_SECT_AP_WRITE,
@@ -164,6 +172,7 @@ struct prot_bits {
.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
.val = 0,
.set = " ro",
+ .ro_bit = true,
}, {
.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
.val = PMD_SECT_AP_WRITE,
@@ -182,6 +191,7 @@ struct prot_bits {
.val = PMD_SECT_XN,
.set = "NX",
.clear = "x ",
+ .nx_bit = true,
}, {
.mask = PMD_SECT_S,
.val = PMD_SECT_S,
@@ -194,6 +204,8 @@ struct pg_level {
const struct prot_bits *bits;
size_t num;
u64 mask;
+ const struct prot_bits *ro_bit;
+ const struct prot_bits *nx_bit;
};
static struct pg_level pg_level[] = {
@@ -226,6 +238,23 @@ static void dump_prot(struct pg_state *st, const struct prot_bits *bits, size_t
}
}
+static void note_prot_wx(struct pg_state *st, unsigned long addr)
+{
+ if (!st->check_wx)
+ return;
+ if ((st->current_prot & pg_level[st->level].ro_bit->mask) ==
+ pg_level[st->level].ro_bit->val)
+ return;
+ if ((st->current_prot & pg_level[st->level].nx_bit->mask) ==
+ pg_level[st->level].nx_bit->val)
+ return;
+
+ WARN_ONCE(1, "arm/mm: Found insecure W+X mapping at address %pS\n",
+ (void *)st->start_address);
+
+ st->wx_pages += (addr - st->start_address) / PAGE_SIZE;
+}
+
static void note_page(struct pg_state *st, unsigned long addr,
unsigned int level, u64 val, const char *domain)
{
@@ -244,6 +273,7 @@ static void note_page(struct pg_state *st, unsigned long addr,
unsigned long delta;
if (st->current_prot) {
+ note_prot_wx(st, addr);
pt_dump_seq_printf(st->seq, "0x%08lx-0x%08lx ",
st->start_address, addr);
@@ -367,6 +397,7 @@ void ptdump_walk_pgd(struct seq_file *m, struct ptdump_info *info)
struct pg_state st = {
.seq = m,
.marker = info->markers,
+ .check_wx = false,
};
walk_pgd(&st, info->mm, info->base_addr);
@@ -379,8 +410,13 @@ static void ptdump_initialize(void)
for (i = 0; i < ARRAY_SIZE(pg_level); i++)
if (pg_level[i].bits)
- for (j = 0; j < pg_level[i].num; j++)
+ for (j = 0; j < pg_level[i].num; j++) {
pg_level[i].mask |= pg_level[i].bits[j].mask;
+ if (pg_level[i].bits[j].ro_bit)
+ pg_level[i].ro_bit = &pg_level[i].bits[j];
+ if (pg_level[i].bits[j].nx_bit)
+ pg_level[i].nx_bit = &pg_level[i].bits[j];
+ }
address_markers[2].start_address = VMALLOC_START;
}
@@ -391,6 +427,26 @@ static void ptdump_initialize(void)
.base_addr = 0,
};
+void ptdump_check_wx(void)
+{
+ struct pg_state st = {
+ .seq = NULL,
+ .marker = (struct addr_marker[]) {
+ { 0, NULL},
+ { -1, NULL},
+ },
+ .check_wx = true,
+ };
+
+ walk_pgd(&st, &init_mm, 0);
+ note_page(&st, 0, 0, 0, NULL);
+ if (st.wx_pages)
+ pr_warn("Checked W+X mappings: FAILED, %lu W+X pages found\n",
+ st.wx_pages);
+ else
+ pr_info("Checked W+X mappings: passed, no W+X pages found\n");
+}
+
static int ptdump_init(void)
{
ptdump_initialize();
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index a1f11a7..bd6f451 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -36,6 +36,7 @@
#include <asm/system_info.h>
#include <asm/tlb.h>
#include <asm/fixmap.h>
+#include <asm/ptdump.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -738,6 +739,7 @@ static int __mark_rodata_ro(void *unused)
void mark_rodata_ro(void)
{
stop_machine(__mark_rodata_ro, NULL, NULL);
+ debug_checkwx();
}
void set_kernel_text_rw(void)
--
1.9.1
^ permalink raw reply related
* [PATCH v8 7/7] arm64: kvm: handle SError Interrupt by categorization
From: gengdongjiu @ 2017-12-06 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5A0B1334.7060500@arm.com>
On 2017/11/15 0:00, James Morse wrote:
>> + * error has not been propagated
>> + */
>> + run->exit_reason = KVM_EXIT_EXCEPTION;
>> + run->ex.exception = ESR_ELx_EC_SERROR;
>> + run->ex.error_code = KVM_SEI_SEV_RECOVERABLE;
>> + return 0;
> We should not pass RAS notifications to user space. The kernel either handles
> them, or it panics(). User space shouldn't even know if the kernel supports RAS
> until it gets an MCEERR signal.
>
> You're making your firmware-first notification an EL3->EL0 signal, bypassing the OS.
>
> If we get a RAS SError and there are no CPER records or values in the ERR nodes,
> we should panic as it looks like the CPU/firmware is broken. (spurious RAS errors)
Hi james,
sorry to disturb you!
do you think whether we need to set the guest ESR by user space? if need, I need to
notify user space that there is a SError happen and need to set ESR for guest in some place of
KVM. so here I return a error code to user space. you mean we should not pass RAS notifications
to user space, so could you give some suggestion how to notify user space to set guest ESR.
Thanks a lot in advance.
>
>
^ permalink raw reply
* [PATCH v2 10/18] arm64: entry: Add exception trampoline page for exceptions from EL0
From: Ard Biesheuvel @ 2017-12-06 10:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512059986-21325-11-git-send-email-will.deacon@arm.com>
On 30 November 2017 at 16:39, Will Deacon <will.deacon@arm.com> wrote:
> To allow unmapping of the kernel whilst running at EL0, we need to
> point the exception vectors at an entry trampoline that can map/unmap
> the kernel on entry/exit respectively.
>
> This patch adds the trampoline page, although it is not yet plugged
> into the vector table and is therefore unused.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm64/kernel/entry.S | 86 +++++++++++++++++++++++++++++++++++++++++
> arch/arm64/kernel/vmlinux.lds.S | 17 ++++++++
> 2 files changed, 103 insertions(+)
>
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index d454d8ed45e4..dea196f287a0 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -28,6 +28,8 @@
> #include <asm/errno.h>
> #include <asm/esr.h>
> #include <asm/irq.h>
> +#include <asm/memory.h>
> +#include <asm/mmu.h>
> #include <asm/processor.h>
> #include <asm/ptrace.h>
> #include <asm/thread_info.h>
> @@ -943,6 +945,90 @@ __ni_sys_trace:
>
> .popsection // .entry.text
>
> +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
> +/*
> + * Exception vectors trampoline.
> + */
> + .pushsection ".entry.tramp.text", "ax"
> +
> + .macro tramp_map_kernel, tmp
> + mrs \tmp, ttbr1_el1
> + sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
> + bic \tmp, \tmp, #USER_ASID_FLAG
> + msr ttbr1_el1, \tmp
> + .endm
> +
> + .macro tramp_unmap_kernel, tmp
> + mrs \tmp, ttbr1_el1
> + add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
> + orr \tmp, \tmp, #USER_ASID_FLAG
> + msr ttbr1_el1, \tmp
> + /*
> + * We avoid running the post_ttbr_update_workaround here because the
> + * user and kernel ASIDs don't have conflicting mappings, so any
> + * "blessing" as described in:
> + *
> + * http://lkml.kernel.org/r/56BB848A.6060603 at caviumnetworks.com
> + *
> + * will not hurt correctness. Whilst this may partially defeat the
> + * point of using split ASIDs in the first place, it avoids
> + * the hit of invalidating the entire I-cache on every return to
> + * userspace.
> + */
> + .endm
> +
> + .macro tramp_ventry, regsize = 64
> + .align 7
> +1:
> + .if \regsize == 64
> + msr tpidrro_el0, x30
> + .endif
> + tramp_map_kernel x30
> + ldr x30, =vectors
Could we move this literal into the next page, and only map that in
the kernel page tables? It's the only piece of information in the
trampoline page that can reveal the true location of the kernel, and
moving it out is trivial to implement on top of the changes you are
already making to harden KASLR.
> + prfm plil1strm, [x30, #(1b - tramp_vectors)]
> + msr vbar_el1, x30
> + add x30, x30, #(1b - tramp_vectors)
> + isb
> + br x30
> + .endm
> +
> + .macro tramp_exit, regsize = 64
> + adr x30, tramp_vectors
> + msr vbar_el1, x30
> + tramp_unmap_kernel x30
> + .if \regsize == 64
> + mrs x30, far_el1
> + .endif
> + eret
> + .endm
> +
> + .align 11
> +ENTRY(tramp_vectors)
> + .space 0x400
> +
> + tramp_ventry
> + tramp_ventry
> + tramp_ventry
> + tramp_ventry
> +
> + tramp_ventry 32
> + tramp_ventry 32
> + tramp_ventry 32
> + tramp_ventry 32
> +END(tramp_vectors)
> +
> +ENTRY(tramp_exit_native)
> + tramp_exit
> +END(tramp_exit_native)
> +
> +ENTRY(tramp_exit_compat)
> + tramp_exit 32
> +END(tramp_exit_compat)
> +
> + .ltorg
> + .popsection // .entry.tramp.text
> +#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
> +
> /*
> * Special system call wrappers.
> */
> diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
> index 7da3e5c366a0..6b4260f22aab 100644
> --- a/arch/arm64/kernel/vmlinux.lds.S
> +++ b/arch/arm64/kernel/vmlinux.lds.S
> @@ -57,6 +57,17 @@ jiffies = jiffies_64;
> #define HIBERNATE_TEXT
> #endif
>
> +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
> +#define TRAMP_TEXT \
> + . = ALIGN(PAGE_SIZE); \
> + VMLINUX_SYMBOL(__entry_tramp_text_start) = .; \
> + *(.entry.tramp.text) \
> + . = ALIGN(PAGE_SIZE); \
> + VMLINUX_SYMBOL(__entry_tramp_text_end) = .;
> +#else
> +#define TRAMP_TEXT
> +#endif
> +
> /*
> * The size of the PE/COFF section that covers the kernel image, which
> * runs from stext to _edata, must be a round multiple of the PE/COFF
> @@ -113,6 +124,7 @@ SECTIONS
> HYPERVISOR_TEXT
> IDMAP_TEXT
> HIBERNATE_TEXT
> + TRAMP_TEXT
> *(.fixup)
> *(.gnu.warning)
> . = ALIGN(16);
> @@ -214,6 +226,11 @@ SECTIONS
> . += RESERVED_TTBR0_SIZE;
> #endif
>
> +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
> + tramp_pg_dir = .;
> + . += PAGE_SIZE;
> +#endif
> +
> __pecoff_data_size = ABSOLUTE(. - __initdata_begin);
> _end = .;
>
> --
> 2.1.4
>
^ permalink raw reply
* [kernel-hardening][PATCH v4 2/3] arm: mm: dump: make the page table dumping seq_file optional
From: Jinbum Park @ 2017-12-06 10:25 UTC (permalink / raw)
To: linux-arm-kernel
This patch makes the page table dumping seq_file optional.
It makes the page table dumping code usable for other cases.
This patch refers below commit of arm64.
(ae5d1cf358a5
("arm64: dump: Make the page table dumping seq_file optional"))
Acked-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Jinbum Park <jinb.park7@gmail.com>
---
v4: Add Acked-by from Kees Cook
---
arch/arm/mm/dump.c | 28 +++++++++++++++++++++-------
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index 8dfe7c3..43a2bee 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -34,6 +34,18 @@
{ -1, NULL },
};
+#define pt_dump_seq_printf(m, fmt, args...) \
+({ \
+ if (m) \
+ seq_printf(m, fmt, ##args); \
+})
+
+#define pt_dump_seq_puts(m, fmt) \
+({ \
+ if (m) \
+ seq_printf(m, fmt); \
+})
+
struct pg_state {
struct seq_file *seq;
const struct addr_marker *marker;
@@ -210,7 +222,7 @@ static void dump_prot(struct pg_state *st, const struct prot_bits *bits, size_t
s = bits->clear;
if (s)
- seq_printf(st->seq, " %s", s);
+ pt_dump_seq_printf(st->seq, " %s", s);
}
}
@@ -224,7 +236,7 @@ static void note_page(struct pg_state *st, unsigned long addr,
st->level = level;
st->current_prot = prot;
st->current_domain = domain;
- seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
+ pt_dump_seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
} else if (prot != st->current_prot || level != st->level ||
domain != st->current_domain ||
addr >= st->marker[1].start_address) {
@@ -232,7 +244,7 @@ static void note_page(struct pg_state *st, unsigned long addr,
unsigned long delta;
if (st->current_prot) {
- seq_printf(st->seq, "0x%08lx-0x%08lx ",
+ pt_dump_seq_printf(st->seq, "0x%08lx-0x%08lx ",
st->start_address, addr);
delta = (addr - st->start_address) >> 10;
@@ -240,17 +252,19 @@ static void note_page(struct pg_state *st, unsigned long addr,
delta >>= 10;
unit++;
}
- seq_printf(st->seq, "%9lu%c", delta, *unit);
+ pt_dump_seq_printf(st->seq, "%9lu%c", delta, *unit);
if (st->current_domain)
- seq_printf(st->seq, " %s", st->current_domain);
+ pt_dump_seq_printf(st->seq, " %s",
+ st->current_domain);
if (pg_level[st->level].bits)
dump_prot(st, pg_level[st->level].bits, pg_level[st->level].num);
- seq_printf(st->seq, "\n");
+ pt_dump_seq_printf(st->seq, "\n");
}
if (addr >= st->marker[1].start_address) {
st->marker++;
- seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
+ pt_dump_seq_printf(st->seq, "---[ %s ]---\n",
+ st->marker->name);
}
st->start_address = addr;
st->current_prot = prot;
--
1.9.1
^ permalink raw reply related
* [kernel-hardening][PATCH v4 1/3] arm: mm: dump: make page table dumping reusable
From: Jinbum Park @ 2017-12-06 10:24 UTC (permalink / raw)
To: linux-arm-kernel
This patch refactors the arm page table dumping code,
so multiple tables may be registered with the framework.
This patch refers below commits of arm64.
(4674fdb9f149 ("arm64: mm: dump: make page table dumping reusable"))
(4ddb9bf83349 ("arm64: dump: Make ptdump debugfs a separate option"))
Signed-off-by: Jinbum Park <jinb.park7@gmail.com>
---
v4: No changes
---
arch/arm/Kconfig.debug | 6 +++-
arch/arm/include/asm/ptdump.h | 48 ++++++++++++++++++++++++++++++++
arch/arm/mm/Makefile | 3 +-
arch/arm/mm/dump.c | 65 +++++++++++++++++++------------------------
arch/arm/mm/ptdump_debugfs.c | 34 ++++++++++++++++++++++
5 files changed, 117 insertions(+), 39 deletions(-)
create mode 100644 arch/arm/include/asm/ptdump.h
create mode 100644 arch/arm/mm/ptdump_debugfs.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 17685e1..e7b94db 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -3,10 +3,14 @@ menu "Kernel hacking"
source "lib/Kconfig.debug"
-config ARM_PTDUMP
+config ARM_PTDUMP_CORE
+ def_bool n
+
+config ARM_PTDUMP_DEBUGFS
bool "Export kernel pagetable layout to userspace via debugfs"
depends on DEBUG_KERNEL
depends on MMU
+ select ARM_PTDUMP_CORE
select DEBUG_FS
---help---
Say Y here if you want to show the kernel pagetable layout in a
diff --git a/arch/arm/include/asm/ptdump.h b/arch/arm/include/asm/ptdump.h
new file mode 100644
index 0000000..3a6c0b7
--- /dev/null
+++ b/arch/arm/include/asm/ptdump.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PTDUMP_H
+#define __ASM_PTDUMP_H
+
+#ifdef CONFIG_ARM_PTDUMP_CORE
+
+#include <linux/mm_types.h>
+#include <linux/seq_file.h>
+
+struct addr_marker {
+ unsigned long start_address;
+ char *name;
+};
+
+struct ptdump_info {
+ struct mm_struct *mm;
+ const struct addr_marker *markers;
+ unsigned long base_addr;
+};
+
+void ptdump_walk_pgd(struct seq_file *s, struct ptdump_info *info);
+#ifdef CONFIG_ARM_PTDUMP_DEBUGFS
+int ptdump_debugfs_register(struct ptdump_info *info, const char *name);
+#else
+static inline int ptdump_debugfs_register(struct ptdump_info *info,
+ const char *name)
+{
+ return 0;
+}
+#endif /* CONFIG_ARM_PTDUMP_DEBUGFS */
+
+#endif /* CONFIG_ARM_PTDUMP_CORE */
+
+#endif /* __ASM_PTDUMP_H */
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 01bcc33..28be5f4 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -13,7 +13,8 @@ obj-y += nommu.o
obj-$(CONFIG_ARM_MPU) += pmsa-v7.o
endif
-obj-$(CONFIG_ARM_PTDUMP) += dump.o
+obj-$(CONFIG_ARM_PTDUMP_CORE) += dump.o
+obj-$(CONFIG_ARM_PTDUMP_DEBUGFS) += ptdump_debugfs.o
obj-$(CONFIG_MODULES) += proc-syms.o
obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index fc3b440..8dfe7c3 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -21,11 +21,7 @@
#include <asm/fixmap.h>
#include <asm/memory.h>
#include <asm/pgtable.h>
-
-struct addr_marker {
- unsigned long start_address;
- const char *name;
-};
+#include <asm/ptdump.h>
static struct addr_marker address_markers[] = {
{ MODULES_VADDR, "Modules" },
@@ -335,50 +331,36 @@ static void walk_pud(struct pg_state *st, pgd_t *pgd, unsigned long start)
}
}
-static void walk_pgd(struct seq_file *m)
+static void walk_pgd(struct pg_state *st, struct mm_struct *mm,
+ unsigned long start)
{
- pgd_t *pgd = swapper_pg_dir;
- struct pg_state st;
- unsigned long addr;
+ pgd_t *pgd = pgd_offset(mm, 0UL);
unsigned i;
-
- memset(&st, 0, sizeof(st));
- st.seq = m;
- st.marker = address_markers;
+ unsigned long addr;
for (i = 0; i < PTRS_PER_PGD; i++, pgd++) {
- addr = i * PGDIR_SIZE;
+ addr = start + i * PGDIR_SIZE;
if (!pgd_none(*pgd)) {
- walk_pud(&st, pgd, addr);
+ walk_pud(st, pgd, addr);
} else {
- note_page(&st, addr, 1, pgd_val(*pgd), NULL);
+ note_page(st, addr, 1, pgd_val(*pgd), NULL);
}
}
-
- note_page(&st, 0, 0, 0, NULL);
}
-static int ptdump_show(struct seq_file *m, void *v)
+void ptdump_walk_pgd(struct seq_file *m, struct ptdump_info *info)
{
- walk_pgd(m);
- return 0;
-}
+ struct pg_state st = {
+ .seq = m,
+ .marker = info->markers,
+ };
-static int ptdump_open(struct inode *inode, struct file *file)
-{
- return single_open(file, ptdump_show, NULL);
+ walk_pgd(&st, info->mm, info->base_addr);
+ note_page(&st, 0, 0, 0, NULL);
}
-static const struct file_operations ptdump_fops = {
- .open = ptdump_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int ptdump_init(void)
+static void ptdump_initialize(void)
{
- struct dentry *pe;
unsigned i, j;
for (i = 0; i < ARRAY_SIZE(pg_level); i++)
@@ -387,9 +369,18 @@ static int ptdump_init(void)
pg_level[i].mask |= pg_level[i].bits[j].mask;
address_markers[2].start_address = VMALLOC_START;
+}
- pe = debugfs_create_file("kernel_page_tables", 0400, NULL, NULL,
- &ptdump_fops);
- return pe ? 0 : -ENOMEM;
+static struct ptdump_info kernel_ptdump_info = {
+ .mm = &init_mm,
+ .markers = address_markers,
+ .base_addr = 0,
+};
+
+static int ptdump_init(void)
+{
+ ptdump_initialize();
+ return ptdump_debugfs_register(&kernel_ptdump_info,
+ "kernel_page_tables");
}
__initcall(ptdump_init);
diff --git a/arch/arm/mm/ptdump_debugfs.c b/arch/arm/mm/ptdump_debugfs.c
new file mode 100644
index 0000000..be8d87b
--- /dev/null
+++ b/arch/arm/mm/ptdump_debugfs.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include <asm/ptdump.h>
+
+static int ptdump_show(struct seq_file *m, void *v)
+{
+ struct ptdump_info *info = m->private;
+
+ ptdump_walk_pgd(m, info);
+ return 0;
+}
+
+static int ptdump_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, ptdump_show, inode->i_private);
+}
+
+static const struct file_operations ptdump_fops = {
+ .open = ptdump_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+int ptdump_debugfs_register(struct ptdump_info *info, const char *name)
+{
+ struct dentry *pe;
+
+ pe = debugfs_create_file(name, 0400, NULL, info, &ptdump_fops);
+ return pe ? 0 : -ENOMEM;
+
+}
--
1.9.1
^ permalink raw reply related
* [kernel-hardening][PATCH v4 0/3] arm: Makes ptdump resuable and add WX page checking
From: Jinbum Park @ 2017-12-06 10:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Page table dumping code for arm64-x86 is reusable,
and they have function for WX page checking.
But arm doesn't have that.
This path series are to makes ptdump reusable,
and add WX page checking for arm.
This is heavily based on arm64 version.
v2 :
Fix a sender name of mail header, there was an mistake.
(from "jinb.park" to Jinbum Park)
Contents of patch-set are perfectly same.
v3 :
Take advantage of the existing pg_level and bits arrays
to check ro, nx prot.
v4 :
Add boolean for ro_bit, nx_bit into prot_bits
to point ro_bit, nx_bit in pg_level.
This change is suggested by Laura Abbott.
jinb.park (3):
arm: mm: dump: make page table dumping reusable
arm: mm: dump: make the page table dumping seq_file optional
arm: mm: dump: add checking for writable and executable pages
arch/arm/Kconfig.debug | 33 ++++++++-
arch/arm/include/asm/ptdump.h | 56 ++++++++++++++++
arch/arm/mm/Makefile | 3 +-
arch/arm/mm/dump.c | 151 +++++++++++++++++++++++++++++-------------
arch/arm/mm/init.c | 2 +
arch/arm/mm/ptdump_debugfs.c | 34 ++++++++++
6 files changed, 232 insertions(+), 47 deletions(-)
create mode 100644 arch/arm/include/asm/ptdump.h
create mode 100644 arch/arm/mm/ptdump_debugfs.c
--
1.9.1
^ permalink raw reply
* [PATCH 61/61] ARM: dts: alt: Convert to named i2c-gpio bindings
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
more error-prone unnamed variant.
Switch to the new bindings, and add the missing GPIO_OPEN_DRAIN I/O
flags, which were implicitly assumed before.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794-alt.dts | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index bd98790d964e..60c6515c4996 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -143,9 +143,8 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
- gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
- &gpio4 8 GPIO_ACTIVE_HIGH /* scl */
- >;
+ sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 60/61] ARM: dts: koelsch: Convert to named i2c-gpio bindings
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
more error-prone unnamed variant.
Switch to the new bindings, and add the missing GPIO_OPEN_DRAIN I/O
flags, which were implicitly assumed before.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791-koelsch.dts | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index fac9cdea4965..a50924d12b6f 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -312,9 +312,8 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
- gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
- &gpio7 15 GPIO_ACTIVE_HIGH /* scl */
- >;
+ sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 59/61] ARM: dts: lager: Convert to named i2c-gpio bindings
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
more error-prone unnamed variant.
Switch to the new bindings, and add the missing GPIO_OPEN_DRAIN I/O
flags, which were implicitly assumed before.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790-lager.dts | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index e3d27783b6b5..f2ea632381e7 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -272,9 +272,8 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
- gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
- &gpio1 16 GPIO_ACTIVE_HIGH /* scl */
- >;
+ sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 58/61] ARM: dts: armadillo800eva: Convert to named i2c-gpio bindings
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
more error-prone unnamed variant.
Switch to the new bindings, and add the missing GPIO_OPEN_DRAIN I/O
flags, which were implicitly assumed before.
The latter gets rid of the message:
gpio-208 (?): enforced open drain please flag it properly in DT/ACPI DSDT/board file
gpio-91 (?): enforced open drain please flag it properly in DT/ACPI DSDT/board file
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 1788e186a512..03b00d87b39b 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -131,9 +131,8 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
- gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
- &pfc 91 GPIO_ACTIVE_HIGH /* scl */
- >;
+ sda-gpios = <&pfc 208 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&pfc 91 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 57/61] ARM: dts: sh73a0: Remove CMT renesas,channels-mask
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Magnus Damm <damm+renesas@opensource.se>
Update the DTS to remove the now deprecated "renesas,channels-mask"
property.
The channel information is now kept in the device driver and can easily
be determined based on the compat string.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/sh73a0.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 88d7e5631d34..914a7c2a584f 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -100,9 +100,6 @@
clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
clock-names = "fck";
power-domains = <&pd_c5>;
-
- renesas,channels-mask = <0x3f>;
-
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH 56/61] ARM: dts: r8a7794: Remove CMT renesas,channels-mask
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Magnus Damm <damm+renesas@opensource.se>
Update the DTS to remove the now deprecated "renesas,channels-mask"
property.
The channel information is now kept in the device driver and can easily
be determined based on the compat string.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 67aa409b32bf..96e405e70d9a 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -197,8 +197,6 @@
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 124>;
- renesas,channels-mask = <0x60>;
-
status = "disabled";
};
@@ -218,8 +216,6 @@
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 329>;
- renesas,channels-mask = <0xff>;
-
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH 55/61] ARM: dts: r8a7793: Remove CMT renesas,channels-mask
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Magnus Damm <damm+renesas@opensource.se>
Update the DTS to remove the now deprecated "renesas,channels-mask"
property.
The channel information is now kept in the device driver and can easily
be determined based on the compat string.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7793.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 4a79da3ddbef..a83c2e9c5723 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -257,8 +257,6 @@
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 124>;
- renesas,channels-mask = <0x60>;
-
status = "disabled";
};
@@ -278,8 +276,6 @@
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 329>;
- renesas,channels-mask = <0xff>;
-
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH 54/61] ARM: dts: r8a7791: Remove CMT renesas,channels-mask
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Magnus Damm <damm+renesas@opensource.se>
Update the DTS to remove the now deprecated "renesas,channels-mask"
property.
The channel information is now kept in the device driver and can easily
be determined based on the compat string.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index a69d6f883b34..dfc1c406179f 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -266,8 +266,6 @@
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 124>;
- renesas,channels-mask = <0x60>;
-
status = "disabled";
};
@@ -287,8 +285,6 @@
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 329>;
- renesas,channels-mask = <0xff>;
-
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH 53/61] ARM: dts: r8a7790: Remove CMT renesas,channels-mask
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Magnus Damm <damm+renesas@opensource.se>
Update the DTS to remove the now deprecated "renesas,channels-mask"
property.
The channel information is now kept in the device driver and can easily
be determined based on the compat string.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index d3c6ab806616..e2c530c330a8 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -320,8 +320,6 @@
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 124>;
- renesas,channels-mask = <0x60>;
-
status = "disabled";
};
@@ -341,8 +339,6 @@
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 329>;
- renesas,channels-mask = <0xff>;
-
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH 52/61] ARM: dts: r8a7740: Remove CMT renesas,channels-mask
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Magnus Damm <damm+renesas@opensource.se>
Update the DTS to remove the now deprecated "renesas,channels-mask"
property.
The channel information is now kept in the device driver and can easily
be determined based on the compat string.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7740.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index d37d22682a63..95c408b11991 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -74,9 +74,6 @@
clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
clock-names = "fck";
power-domains = <&pd_c5>;
-
- renesas,channels-mask = <0x3f>;
-
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH 51/61] ARM: dts: r8a73a4: Remove CMT renesas,channels-mask
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Magnus Damm <damm+renesas@opensource.se>
Update the DTS to remove the now deprecated "renesas,channels-mask"
property.
The channel information is now kept in the device driver and can easily
be determined based on the compat string.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a73a4.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 805b0fd70f53..8e48090e4fdc 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -138,9 +138,6 @@
clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
clock-names = "fck";
power-domains = <&pd_c5>;
-
- renesas,channels-mask = <0xff>;
-
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH 50/61] ARM: dts: r8a7794: Update CMT compat strings
From: Simon Horman @ 2017-12-06 10:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1512555546.git.horms+renesas@verge.net.au>
From: Magnus Damm <damm+renesas@opensource.se>
Use recently updated R-Car Gen2 CMT0 and CMT1 compat strings.
With this change in place we can keep device-specific configuration in
the driver and the driver can be able to support CMT1 specific features.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 90050565114c..67aa409b32bf 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -188,7 +188,7 @@
};
cmt0: timer at ffca0000 {
- compatible = "renesas,cmt-48-gen2";
+ compatible = "renesas,r8a7794-cmt0", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -203,7 +203,7 @@
};
cmt1: timer at e6130000 {
- compatible = "renesas,cmt-48-gen2";
+ compatible = "renesas,r8a7794-cmt1", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
--
2.11.0
^ permalink raw reply related
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