* [PATCH 10/12] ARM: dts: pxa: use reworked NAND controller driver
From: Miquel Raynal @ 2017-12-07 20:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207201814.30411-1-miquel.raynal@free-electrons.com>
Use the new bindings of the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
---
arch/arm/boot/dts/pxa3xx.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
index 55c75b67351c..982d1a62661d 100644
--- a/arch/arm/boot/dts/pxa3xx.dtsi
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -117,15 +117,15 @@
status = "disabled";
};
- nand0: nand at 43100000 {
- compatible = "marvell,pxa3xx-nand";
+ nand_controller: nand-controller at 43100000 {
+ compatible = "marvell,pxa3xx-nand-controller";
reg = <0x43100000 90>;
interrupts = <45>;
clocks = <&clks CLK_NAND>;
dmas = <&pdma 97 3>;
dma-names = "data";
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH 11/12] ARM64: dts: marvell: use reworked NAND controller driver on Armada 7K
From: Miquel Raynal @ 2017-12-07 20:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207201814.30411-1-miquel.raynal@free-electrons.com>
Use the new bindings of the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as
the driver activates the arbiter by default for all boards (either
needed or harmless).
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 52 +++++++++++++---------
.../boot/dts/marvell/armada-cp110-master.dtsi | 8 ++--
2 files changed, 36 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 52b5341cb270..758452c10612 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -156,36 +156,48 @@
};
};
-&cpm_nand {
+&cpm_nand_controller {
/*
* SPI on CPM and NAND have common pins on this board. We can
- * use only one at a time. To enable the NAND (whihch will
+ * use only one at a time. To enable the NAND (which will
* disable the SPI), the "status = "okay";" line have to be
* added here.
*/
- num-cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
-
- partition at 0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition at 200000 {
- label = "Linux";
- reg = <0x200000 0xe00000>;
- };
- partition at 1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
+
+ nand at 0 {
+ reg = <0>;
+ label = "pxa3xx_nand-0";
+ marvell,rb = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+
+ partition at 200000 {
+ label = "Linux";
+ reg = <0x200000 0xe00000>;
+ };
+
+ partition at 1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+
+ };
};
};
-
&cpm_spi1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index e3b64d03fbd8..8a3cff9a7343 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -309,17 +309,17 @@
status = "disabled";
};
- cpm_nand: nand at 720000 {
+ cpm_nand_controller: nand at 720000 {
/*
* Due to the limiation of the pin available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
- compatible = "marvell,armada-8k-nand",
- "marvell,armada370-nand";
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 2>;
marvell,system-controller = <&cpm_syscon0>;
--
2.11.0
^ permalink raw reply related
* [PATCH 12/12] ARM64: dts: marvell: use reworked NAND controller driver on Armada 8K
From: Miquel Raynal @ 2017-12-07 20:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207201814.30411-1-miquel.raynal@free-electrons.com>
Use the new bindings of the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as
the driver activates the arbiter by default for all boards (either
needed or harmless).
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 46 +++++++++++++---------
.../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 10 ++---
2 files changed, 32 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index b1f6cccc5081..c25ac3fa9aec 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -272,27 +272,35 @@
* Proper NAND usage will require DPR-76 to be in position 1-2, which disables
* MDIO signal of CP1.
*/
-&cps_nand {
- num-cs = <1>;
+&cps_nand_controller {
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- marvell,nand-enable-arbiter;
- marvell,system-controller = <&cps_syscon0>;
- nand-on-flash-bbt;
-
- partition at 0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition at 200000 {
- label = "Linux";
- reg = <0x200000 0xe00000>;
- };
- partition at 1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
+
+ nand at 0 {
+ reg = <0>;
+ marvell,rb = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition at 200000 {
+ label = "Linux";
+ reg = <0x200000 0xe00000>;
+ };
+ partition at 1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index cb1fb49ccf81..8610163bb1a4 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -310,20 +310,20 @@
status = "disabled";
};
- cps_nand: nand at 720000 {
+ cps_nand_controller: nand at 720000 {
/*
* Due to the limiation of the pin available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
- compatible = "marvell,armada370-nand",
- "marvell,armada-8k-nand";
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 2>;
- marvell,system-controller = <&cpm_syscon0>;
+ marvell,system-controller = <&cps_syscon0>;
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH] clk: meson: make the spinlock naming more specific
From: Kevin Hilman @ 2017-12-07 20:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204052739.10747-1-yixun.lan@amlogic.com>
Yixun Lan <yixun.lan@amlogic.com> writes:
> Make the spinlock more specific, so better for lockdep
> debugging and ctags/grep.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>
> ---
>
> this patch try to address the issue which bring up by Stephen at [1]
> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005534.html
FYI... for future reference, it's common to use a Suggested-by tag to
give credit for these kinds of things. e.g.:
Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Kevin
^ permalink raw reply
* [PATCH v8 4/6] clocksource: stm32: only use 32 bits timers
From: Benjamin Gaignard @ 2017-12-07 20:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2afa343b-3a23-3352-33b3-2133678a4122@linaro.org>
2017-12-07 17:49 GMT+01:00 Daniel Lezcano <daniel.lezcano@linaro.org>:
> On 07/12/2017 17:33, Benjamin Gaignard wrote:
>> 2017-12-07 16:27 GMT+01:00 Daniel Lezcano <daniel.lezcano@linaro.org>:
>>> On 14/11/2017 09:52, Benjamin Gaignard wrote:
>>>> The clock driving counters is at 90MHz so the maximum period
>>>> for 16 bis counters is around 750 ms which is a short period
>>>> for a clocksource.
>>>
>>> Isn't it 728us ?
>>
>> yes it is: 2^16 / 90.000.000 => 728us
>
> Ok, now I can do the connection with the previous patch.
>
> So, the real issue of all this is the 16bits clocksource is wrapping up
> every 728us, hence the clockevent periodically expires every ~728us to
> keep the timekeeping consistent. Unfortunately, the kernel has a too
> high overhead for this as the system is consistently processing this
> timer leading to a CPU time resource starvation.
>
> Is that correct ?
Yes that is correct
>
>
>>>> For 32 bits counters this period is close
>>>> 47 secondes which is more acceptable.
>>>>
>>>> This patch remove 16 bits counters support and makes sure that
>>>> they won't be probed anymore.
>>>>
>>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
>>>> ---
>>>> drivers/clocksource/timer-stm32.c | 26 ++++++++++++--------------
>>>> 1 file changed, 12 insertions(+), 14 deletions(-)
>>>>
>>>> diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c
>>>> index ae41a19..8173bcf 100644
>>>> --- a/drivers/clocksource/timer-stm32.c
>>>> +++ b/drivers/clocksource/timer-stm32.c
>>>> @@ -83,9 +83,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
>>>> static int __init stm32_clockevent_init(struct device_node *node)
>>>> {
>>>> struct reset_control *rstc;
>>>> - unsigned long max_delta;
>>>> - int ret, bits, prescaler = 1;
>>>> + unsigned long max_arr;
>>>> struct timer_of *to;
>>>> + int ret;
>>>>
>>>> to = kzalloc(sizeof(*to), GFP_KERNEL);
>>>> if (!to)
>>>> @@ -115,29 +115,27 @@ static int __init stm32_clockevent_init(struct device_node *node)
>>>>
>>>> /* Detect whether the timer is 16 or 32 bits */
>>>> writel_relaxed(~0U, timer_of_base(to) + TIM_ARR);
>>>> - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR);
>>>> - if (max_delta == ~0U) {
>>>> - prescaler = 1;
>>>> - bits = 32;
>>>> - } else {
>>>> - prescaler = 1024;
>>>> - bits = 16;
>>>> + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR);
>>>> + if (max_arr != ~0U) {
>>>> + pr_err("32 bits timer is needed\n");
>>>> + ret = -EINVAL;
>>>> + goto deinit;
>>>> }
>>>> +
>>>> writel_relaxed(0, timer_of_base(to) + TIM_ARR);
>>>>
>>>> - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
>>>> + writel_relaxed(0, timer_of_base(to) + TIM_PSC);
>>>> writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
>>>> writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER);
>>>> writel_relaxed(0, timer_of_base(to) + TIM_SR);
>>>>
>>>> clockevents_config_and_register(&to->clkevt,
>>>> - timer_of_period(to), MIN_DELTA, max_delta);
>>>> -
>>>> - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
>>>> - node, bits);
>>>> + timer_of_period(to), MIN_DELTA, ~0U);
>>>>
>>>> return 0;
>>>>
>>>> +deinit:
>>>> + timer_of_exit(to);
>>>> err:
>>>> kfree(to);
>>>> return ret;
>>>>
>>>
>>>
>>> --
>>> <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
>>>
>>> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
>>> <http://twitter.com/#!/linaroorg> Twitter |
>>> <http://www.linaro.org/linaro-blog/> Blog
>>>
>>
>>
>>
>
>
> --
> <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
>
> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>
--
Benjamin Gaignard
Graphic Study Group
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v8 1/3] arm: npcm: add basic support for Nuvoton BMCs
From: Brendan Higgins @ 2017-12-07 20:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171117190747.21642-2-brendanhiggins@google.com>
Any update on this?
On Fri, Nov 17, 2017 at 11:07 AM, Brendan Higgins
<brendanhiggins@google.com> wrote:
> Adds basic support for the Nuvoton NPCM750 BMC.
>
> Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com>
> Reviewed-by: Avi Fishman <avifishman70@gmail.com>
> Tested-by: Tomer Maimon <tmaimon77@gmail.com>
> Tested-by: Avi Fishman <avifishman70@gmail.com>
> ---
> Changes since v7:
> - Fixed useless parameter in print statement
> - Added/cleaned up some comments
> - Fixed typo in DT_MACHINE_START
> - Got rid of L2C aux value
> - Dropped unnecessary memory barriers
> - Renamed CPU_NPCM750 to ARCH_NPCM750
> - Fixed some other minor issues
> ---
> arch/arm/Kconfig | 2 ++
> arch/arm/Makefile | 1 +
> arch/arm/mach-npcm/Kconfig | 48 +++++++++++++++++++++++++
> arch/arm/mach-npcm/Makefile | 3 ++
> arch/arm/mach-npcm/headsmp.S | 21 +++++++++++
> arch/arm/mach-npcm/npcm7xx.c | 25 +++++++++++++
> arch/arm/mach-npcm/platsmp.c | 85 ++++++++++++++++++++++++++++++++++++++++++++
> 7 files changed, 185 insertions(+)
> create mode 100644 arch/arm/mach-npcm/Kconfig
> create mode 100644 arch/arm/mach-npcm/Makefile
> create mode 100644 arch/arm/mach-npcm/headsmp.S
> create mode 100644 arch/arm/mach-npcm/npcm7xx.c
> create mode 100644 arch/arm/mach-npcm/platsmp.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 61a0cb15067e..05543f1cfbde 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig"
>
> source "arch/arm/mach-nomadik/Kconfig"
>
> +source "arch/arm/mach-npcm/Kconfig"
> +
> source "arch/arm/mach-nspire/Kconfig"
>
> source "arch/arm/plat-omap/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 47d3a1ab08d2..60ca50c7d762 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
> machine-$(CONFIG_ARCH_MXS) += mxs
> machine-$(CONFIG_ARCH_NETX) += netx
> machine-$(CONFIG_ARCH_NOMADIK) += nomadik
> +machine-$(CONFIG_ARCH_NPCM) += npcm
> machine-$(CONFIG_ARCH_NSPIRE) += nspire
> machine-$(CONFIG_ARCH_OXNAS) += oxnas
> machine-$(CONFIG_ARCH_OMAP1) += omap1
> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
> new file mode 100644
> index 000000000000..6ff9df2636be
> --- /dev/null
> +++ b/arch/arm/mach-npcm/Kconfig
> @@ -0,0 +1,48 @@
> +menuconfig ARCH_NPCM
> + bool "Nuvoton NPCM Architecture"
> + select ARCH_REQUIRE_GPIOLIB
> + select USE_OF
> + select PINCTRL
> + select PINCTRL_NPCM7XX
> +
> +if ARCH_NPCM
> +
> +comment "NPCM7XX CPU type"
> +
> +config ARCH_NPCM750
> + depends on ARCH_NPCM && ARCH_MULTI_V7
> + bool "Support for NPCM750 BMC CPU (Poleg)"
> + select CACHE_L2X0
> + select CPU_V7
> + select ARM_GIC
> + select HAVE_SMP
> + select SMP
> + select SMP_ON_UP
> + select HAVE_ARM_SCU
> + select HAVE_ARM_TWD if SMP
> + select ARM_ERRATA_720789
> + select ARM_ERRATA_754322
> + select ARM_ERRATA_764369
> + select ARM_ERRATA_794072
> + select PL310_ERRATA_588369
> + select PL310_ERRATA_727915
> + select USB_EHCI_ROOT_HUB_TT
> + select USB_ARCH_HAS_HCD
> + select USB_ARCH_HAS_EHCI
> + select USB_EHCI_HCD
> + select USB_ARCH_HAS_OHCI
> + select USB_OHCI_HCD
> + select USB
> + select FIQ
> + select CPU_USE_DOMAINS
> + select GENERIC_CLOCKEVENTS
> + select CLKDEV_LOOKUP
> + select COMMON_CLK if OF
> + select NPCM750_TIMER
> + select MFD_SYSCON
> + help
> + Support for NPCM750 BMC CPU (Poleg).
> +
> + Nuvoton NPCM750 BMC based on the Cortex A9.
> +
> +endif
> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
> new file mode 100644
> index 000000000000..c7a1316d27c1
> --- /dev/null
> +++ b/arch/arm/mach-npcm/Makefile
> @@ -0,0 +1,3 @@
> +AFLAGS_headsmp.o += -march=armv7-a
> +
> +obj-$(CONFIG_ARCH_NPCM750) += npcm7xx.o platsmp.o headsmp.o
> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S
> new file mode 100644
> index 000000000000..2d0d8880634b
> --- /dev/null
> +++ b/arch/arm/mach-npcm/headsmp.S
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright 2017 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/linkage.h>
> +#include <linux/init.h>
> +#include <asm/assembler.h>
> +
> +/*
> + * The boot ROM does not start secondary CPUs in SVC mode, so we need to do that
> + * here.
> + */
> +ENTRY(npcm7xx_secondary_startup)
> + safe_svcmode_maskall r0
> +
> + b secondary_startup
> +ENDPROC(npcm7xx_secondary_startup)
> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
> new file mode 100644
> index 000000000000..500bdd0a9ebb
> --- /dev/null
> +++ b/arch/arm/mach-npcm/npcm7xx.c
> @@ -0,0 +1,25 @@
> +/*
> + * Copyright (c) 2017 Nuvoton Technology corporation.
> + * Copyright 2017 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/map.h>
> +#include <asm/hardware/cache-l2x0.h>
> +
> +static const char *const npcm7xx_dt_match[] = {
> + "nuvoton,npcm750",
> + NULL
> +};
> +
> +DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
> + .atag_offset = 0x100,
> + .dt_compat = npcm7xx_dt_match,
> +MACHINE_END
> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c
> new file mode 100644
> index 000000000000..959af7bd741f
> --- /dev/null
> +++ b/arch/arm/mach-npcm/platsmp.c
> @@ -0,0 +1,85 @@
> +/*
> + * Copyright 2017 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
> +
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/smp.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <asm/cacheflush.h>
> +#include <asm/smp.h>
> +#include <asm/smp_plat.h>
> +#include <asm/smp_scu.h>
> +
> +#define NPCM7XX_SCRPAD_REG 0x13c
> +
> +extern void npcm7xx_secondary_startup(void);
> +
> +static int npcm7xx_smp_boot_secondary(unsigned int cpu,
> + struct task_struct *idle)
> +{
> + struct device_node *gcr_np;
> + void __iomem *gcr_base;
> + int ret = 0;
> +
> + gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
> + if (!gcr_np) {
> + pr_err("no gcr device node\n");
> + ret = -ENODEV;
> + goto out;
> + }
> + gcr_base = of_iomap(gcr_np, 0);
> + if (!gcr_base) {
> + pr_err("could not iomap gcr");
> + ret = -ENOMEM;
> + goto out;
> + }
> +
> + /* give boot ROM kernel start address. */
> + iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
> + NPCM7XX_SCRPAD_REG);
> + /* make sure the previous write is seen by all observers. */
> + dsb_sev();
> +
> + iounmap(gcr_base);
> +out:
> + return ret;
> +}
> +
> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
> +{
> + struct device_node *scu_np;
> + void __iomem *scu_base;
> +
> + scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
> + if (!scu_np) {
> + pr_err("no scu device node\n");
> + return;
> + }
> + scu_base = of_iomap(scu_np, 0);
> + if (!scu_base) {
> + pr_err("could not iomap scu");
> + return;
> + }
> +
> + scu_enable(scu_base);
> +
> + iounmap(scu_base);
> +}
> +
> +static struct smp_operations npcm7xx_smp_ops __initdata = {
> + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
> + .smp_boot_secondary = npcm7xx_smp_boot_secondary,
> +};
> +
> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm7xx-smp", &npcm7xx_smp_ops);
> --
> 2.15.0.448.gf294e3d99a-goog
>
^ permalink raw reply
* [PATCH V7 0/7] dmaengine: qcom_hidma: add support for bugfixed HW
From: Sinan Kaya @ 2017-12-07 21:10 UTC (permalink / raw)
To: linux-arm-kernel
Introduce new ACPI and OF device ids for thw HW along with the helper
functions.
Changes from v6:
* add const to the device callback parameter in fwnode.
* reorganize the callbacks in the code
* rename get_match_data() as device_get_match_data()
* place pointer checks into acpi_get_match_data()
Sinan Kaya (7):
Documentation: DT: qcom_hidma: Bump HW revision for the bugfixed HW
ACPI / bus: Introduce acpi_get_match_data() function
device property: Introduce a common API to fetch device match data
OF: properties: Implement get_match_data() callback
ACPI: properties: Implement get_match_data() callback
dmaengine: qcom_hidma: Add support for the new revision
dmaengine: qcom_hidma: Add identity register support
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt | 4 +--
drivers/acpi/bus.c | 18 ++++++++++
drivers/acpi/property.c | 8 +++++
drivers/base/property.c | 7 ++++
drivers/dma/qcom/hidma.c | 41 ++++++++++------------
drivers/of/property.c | 8 +++++
include/linux/acpi.h | 6 ++++
include/linux/fwnode.h | 4 +++
include/linux/property.h | 2 ++
9 files changed, 74 insertions(+), 24 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH V7 1/7] Documentation: DT: qcom_hidma: Bump HW revision for the bugfixed HW
From: Sinan Kaya @ 2017-12-07 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512681031-11343-1-git-send-email-okaya@codeaurora.org>
A new version of the HIDMA IP has been released with bug fixes. Bumping the
hardware version to differentiate from others.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
index 55492c2..5d93d6d 100644
--- a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
@@ -47,8 +47,8 @@ When the OS is not in control of the management interface (i.e. it's a guest),
the channel nodes appear on their own, not under a management node.
Required properties:
-- compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1"
-for MSI capable HW.
+- compatible: must contain "qcom,hidma-1.0" for initial HW or
+ "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.
- reg: Addresses for the transfer and event channel
- interrupts: Should contain the event interrupt
- desc-count: Number of asynchronous requests this channel can handle
--
1.9.1
^ permalink raw reply related
* [PATCH V7 2/7] ACPI / bus: Introduce acpi_get_match_data() function
From: Sinan Kaya @ 2017-12-07 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512681031-11343-1-git-send-email-okaya@codeaurora.org>
OF has of_device_get_match_data() function to extract driver specific data
structure. Add a similar function for ACPI.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/acpi/bus.c | 18 ++++++++++++++++++
include/linux/acpi.h | 6 ++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 4d0979e..f87ed3b 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -785,6 +785,24 @@ const struct acpi_device_id *acpi_match_device(const struct acpi_device_id *ids,
}
EXPORT_SYMBOL_GPL(acpi_match_device);
+void *acpi_get_match_data(const struct device *dev)
+{
+ const struct acpi_device_id *match;
+
+ if (!dev->driver)
+ return NULL;
+
+ if (!dev->driver->acpi_match_table)
+ return NULL;
+
+ match = acpi_match_device(dev->driver->acpi_match_table, dev);
+ if (!match)
+ return NULL;
+
+ return (void *)match->driver_data;
+}
+EXPORT_SYMBOL_GPL(acpi_get_match_data);
+
int acpi_match_device_ids(struct acpi_device *device,
const struct acpi_device_id *ids)
{
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 502af53..a927260 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -584,6 +584,7 @@ extern int acpi_nvs_for_each_region(int (*func)(__u64, __u64, void *),
const struct acpi_device_id *acpi_match_device(const struct acpi_device_id *ids,
const struct device *dev);
+void *acpi_get_match_data(const struct device *dev);
extern bool acpi_driver_match_device(struct device *dev,
const struct device_driver *drv);
int acpi_device_uevent_modalias(struct device *, struct kobj_uevent_env *);
@@ -755,6 +756,11 @@ static inline const struct acpi_device_id *acpi_match_device(
return NULL;
}
+static inline void *acpi_get_match_data(const struct device *dev)
+{
+ return NULL;
+}
+
static inline bool acpi_driver_match_device(struct device *dev,
const struct device_driver *drv)
{
--
1.9.1
^ permalink raw reply related
* [PATCH V7 3/7] device property: Introduce a common API to fetch device match data
From: Sinan Kaya @ 2017-12-07 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512681031-11343-1-git-send-email-okaya@codeaurora.org>
There is an OF/ACPI function to obtain the driver data. We want to hide
OF/ACPI details from the device drivers and abstract following the device
family of functions.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/base/property.c | 7 +++++++
include/linux/fwnode.h | 4 ++++
include/linux/property.h | 2 ++
3 files changed, 13 insertions(+)
diff --git a/drivers/base/property.c b/drivers/base/property.c
index 7ed99c1..ee704a8 100644
--- a/drivers/base/property.c
+++ b/drivers/base/property.c
@@ -1335,3 +1335,10 @@ int fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode,
return fwnode_call_int_op(fwnode, graph_parse_endpoint, endpoint);
}
EXPORT_SYMBOL(fwnode_graph_parse_endpoint);
+
+void *device_get_match_data(struct device *dev)
+{
+ return fwnode_call_ptr_op(dev_fwnode(dev), device_get_match_data,
+ dev);
+}
+EXPORT_SYMBOL_GPL(device_get_match_data);
diff --git a/include/linux/fwnode.h b/include/linux/fwnode.h
index 0c35b6c..e2b4b22 100644
--- a/include/linux/fwnode.h
+++ b/include/linux/fwnode.h
@@ -15,6 +15,7 @@
#include <linux/types.h>
struct fwnode_operations;
+struct device;
struct fwnode_handle {
struct fwnode_handle *secondary;
@@ -51,6 +52,7 @@ struct fwnode_reference_args {
* struct fwnode_operations - Operations for fwnode interface
* @get: Get a reference to an fwnode.
* @put: Put a reference to an fwnode.
+ * @device_get_match_data: Return the device driver match data.
* @property_present: Return true if a property is present.
* @property_read_integer_array: Read an array of integer properties. Return
* zero on success, a negative error code
@@ -71,6 +73,8 @@ struct fwnode_operations {
void (*get)(struct fwnode_handle *fwnode);
void (*put)(struct fwnode_handle *fwnode);
bool (*device_is_available)(const struct fwnode_handle *fwnode);
+ void *(*device_get_match_data)(const struct fwnode_handle *fwnode,
+ const struct device *dev);
bool (*property_present)(const struct fwnode_handle *fwnode,
const char *propname);
int (*property_read_int_array)(const struct fwnode_handle *fwnode,
diff --git a/include/linux/property.h b/include/linux/property.h
index 6bebee1..01fa55b 100644
--- a/include/linux/property.h
+++ b/include/linux/property.h
@@ -275,6 +275,8 @@ int device_add_properties(struct device *dev,
enum dev_dma_attr device_get_dma_attr(struct device *dev);
+void *device_get_match_data(struct device *dev);
+
int device_get_phy_mode(struct device *dev);
void *device_get_mac_address(struct device *dev, char *addr, int alen);
--
1.9.1
^ permalink raw reply related
* [PATCH V7 4/7] OF: properties: Implement get_match_data() callback
From: Sinan Kaya @ 2017-12-07 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512681031-11343-1-git-send-email-okaya@codeaurora.org>
Now that we have a get_match_data() callback as part of the firmware node,
implement the OF specific piece for it.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/of/property.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/of/property.c b/drivers/of/property.c
index 264c355..543e059 100644
--- a/drivers/of/property.c
+++ b/drivers/of/property.c
@@ -981,10 +981,18 @@ static int of_fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode,
return 0;
}
+static void *
+of_fwnode_device_get_match_data(const struct fwnode_handle *fwnode,
+ const struct device *dev)
+{
+ return (void *)of_device_get_match_data(dev);
+}
+
const struct fwnode_operations of_fwnode_ops = {
.get = of_fwnode_get,
.put = of_fwnode_put,
.device_is_available = of_fwnode_device_is_available,
+ .device_get_match_data = of_fwnode_device_get_match_data,
.property_present = of_fwnode_property_present,
.property_read_int_array = of_fwnode_property_read_int_array,
.property_read_string_array = of_fwnode_property_read_string_array,
--
1.9.1
^ permalink raw reply related
* [PATCH V7 5/7] ACPI: properties: Implement get_match_data() callback
From: Sinan Kaya @ 2017-12-07 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512681031-11343-1-git-send-email-okaya@codeaurora.org>
Now that we have a get_match_data() callback as part of the firmware node,
implement the ACPI specific piece for it.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/acpi/property.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c
index e26ea20..466d150 100644
--- a/drivers/acpi/property.c
+++ b/drivers/acpi/property.c
@@ -1271,9 +1271,17 @@ static int acpi_fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode,
return 0;
}
+static void *
+acpi_fwnode_device_get_match_data(const struct fwnode_handle *fwnode,
+ const struct device *dev)
+{
+ return acpi_get_match_data(dev);
+}
+
#define DECLARE_ACPI_FWNODE_OPS(ops) \
const struct fwnode_operations ops = { \
.device_is_available = acpi_fwnode_device_is_available, \
+ .device_get_match_data = acpi_fwnode_device_get_match_data, \
.property_present = acpi_fwnode_property_present, \
.property_read_int_array = \
acpi_fwnode_property_read_int_array, \
--
1.9.1
^ permalink raw reply related
* [PATCH V7 6/7] dmaengine: qcom_hidma: Add support for the new revision
From: Sinan Kaya @ 2017-12-07 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512681031-11343-1-git-send-email-okaya@codeaurora.org>
Add support for probing the newer HW and also organize MSI capable hardware
into an array for maintenance reasons.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma.c | 34 +++++++++++++---------------------
1 file changed, 13 insertions(+), 21 deletions(-)
diff --git a/drivers/dma/qcom/hidma.c b/drivers/dma/qcom/hidma.c
index e366985..c146c6d 100644
--- a/drivers/dma/qcom/hidma.c
+++ b/drivers/dma/qcom/hidma.c
@@ -50,6 +50,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/of_dma.h>
+#include <linux/of_device.h>
#include <linux/property.h>
#include <linux/delay.h>
#include <linux/acpi.h>
@@ -104,6 +105,9 @@ static void hidma_free(struct hidma_dev *dmadev)
module_param(nr_desc_prm, uint, 0644);
MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)");
+enum hidma_cap {
+ HIDMA_MSI_CAP = 1,
+};
/* process completed descriptors */
static void hidma_process_completed(struct hidma_chan *mchan)
@@ -736,25 +740,12 @@ static int hidma_request_msi(struct hidma_dev *dmadev,
#endif
}
-static bool hidma_msi_capable(struct device *dev)
+static bool hidma_test_capability(struct device *dev, enum hidma_cap test_cap)
{
- struct acpi_device *adev = ACPI_COMPANION(dev);
- const char *of_compat;
- int ret = -EINVAL;
-
- if (!adev || acpi_disabled) {
- ret = device_property_read_string(dev, "compatible",
- &of_compat);
- if (ret)
- return false;
+ enum hidma_cap cap;
- ret = strcmp(of_compat, "qcom,hidma-1.1");
- } else {
-#ifdef CONFIG_ACPI
- ret = strcmp(acpi_device_hid(adev), "QCOM8062");
-#endif
- }
- return ret == 0;
+ cap = (enum hidma_cap) device_get_match_data(dev);
+ return cap ? ((cap & test_cap) > 0) : 0;
}
static int hidma_probe(struct platform_device *pdev)
@@ -834,8 +825,7 @@ static int hidma_probe(struct platform_device *pdev)
* Determine the MSI capability of the platform. Old HW doesn't
* support MSI.
*/
- msi = hidma_msi_capable(&pdev->dev);
-
+ msi = hidma_test_capability(&pdev->dev, HIDMA_MSI_CAP);
device_property_read_u32(&pdev->dev, "desc-count",
&dmadev->nr_descriptors);
@@ -953,7 +943,8 @@ static int hidma_remove(struct platform_device *pdev)
#if IS_ENABLED(CONFIG_ACPI)
static const struct acpi_device_id hidma_acpi_ids[] = {
{"QCOM8061"},
- {"QCOM8062"},
+ {"QCOM8062", HIDMA_MSI_CAP},
+ {"QCOM8063", HIDMA_MSI_CAP},
{},
};
MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids);
@@ -961,7 +952,8 @@ static int hidma_remove(struct platform_device *pdev)
static const struct of_device_id hidma_match[] = {
{.compatible = "qcom,hidma-1.0",},
- {.compatible = "qcom,hidma-1.1",},
+ {.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),},
+ {.compatible = "qcom,hidma-1.2", .data = (void *)(HIDMA_MSI_CAP),},
{},
};
MODULE_DEVICE_TABLE(of, hidma_match);
--
1.9.1
^ permalink raw reply related
* [PATCH V7 7/7] dmaengine: qcom_hidma: Add identity register support
From: Sinan Kaya @ 2017-12-07 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512681031-11343-1-git-send-email-okaya@codeaurora.org>
The location for destination event channel register has been relocated from
offset 0x28 to 0x40. Update the code accordingly.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/qcom/hidma.c b/drivers/dma/qcom/hidma.c
index c146c6d..963cc52 100644
--- a/drivers/dma/qcom/hidma.c
+++ b/drivers/dma/qcom/hidma.c
@@ -107,6 +107,7 @@ static void hidma_free(struct hidma_dev *dmadev)
enum hidma_cap {
HIDMA_MSI_CAP = 1,
+ HIDMA_IDENTITY_CAP,
};
/* process completed descriptors */
@@ -838,7 +839,10 @@ static int hidma_probe(struct platform_device *pdev)
if (!dmadev->nr_descriptors)
dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC;
- dmadev->chidx = readl(dmadev->dev_trca + 0x28);
+ if (hidma_test_capability(&pdev->dev, HIDMA_IDENTITY_CAP))
+ dmadev->chidx = readl(dmadev->dev_trca + 0x40);
+ else
+ dmadev->chidx = readl(dmadev->dev_trca + 0x28);
/* Set DMA mask to 64 bits. */
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
@@ -944,7 +948,7 @@ static int hidma_remove(struct platform_device *pdev)
static const struct acpi_device_id hidma_acpi_ids[] = {
{"QCOM8061"},
{"QCOM8062", HIDMA_MSI_CAP},
- {"QCOM8063", HIDMA_MSI_CAP},
+ {"QCOM8063", (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP)},
{},
};
MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids);
@@ -953,7 +957,8 @@ static int hidma_remove(struct platform_device *pdev)
static const struct of_device_id hidma_match[] = {
{.compatible = "qcom,hidma-1.0",},
{.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),},
- {.compatible = "qcom,hidma-1.2", .data = (void *)(HIDMA_MSI_CAP),},
+ {.compatible = "qcom,hidma-1.2",
+ .data = (void *)(HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP),},
{},
};
MODULE_DEVICE_TABLE(of, hidma_match);
--
1.9.1
^ permalink raw reply related
* [PATCH v2 0/7] Add CPU Frequency scaling support on Armada 37xx
From: Rafael J. Wysocki @ 2017-12-07 21:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87r2s6s9mj.fsf@free-electrons.com>
On Thu, Dec 7, 2017 at 6:58 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:
> Hi Rafael,
>
> On jeu., d?c. 07 2017, "Rafael J. Wysocki" <rjw@rjwysocki.net> wrote:
>
>> On Thursday, December 7, 2017 2:56:09 PM CET Gregory CLEMENT wrote:
>>> Hi,
>>>
>>> This is the second version of a series adding the CPU Frequency
>>> support on Armada 37xx using DVFS. It is based on the initial work of
>>> Evan Wang and Victor Gu.
>>>
>>> The main change since the first version was a bug fixed in the
>>> "cpufreq: Add DVFS support for Armada 37xx" patch which was preventing
>>> to register the opp. An other noticeable change is the 4th patch which
>>> is new adding the use of dev_pm_opp_remove and removing an comment
>>> became wrong. The other changes are described in the change log.
>>>
>>> DVFS control is done by a set of registers from the North Bridge Power
>>> Management block. The binding for this block is documented in patch 1.
>>>
>>> While adding a new cpufreq driver I found that the Kconfig and
>>> Makefile were no more in order, so it is fixed by patch 2 and 3.
>>>
>>> The 5th patch is just about updating the MAINTAINERS file with the new
>>> driver.
>>>
>>> The next patch is the real purpose of the series. The main goal of
>>> this driver is to setup the CPU load level in the hardware to
>>> associate them to CPU frequencies and register a standard cpufreq
>>> driver. Note that the hardware also capable of doing AVS (Adaptive
>>> Voltage Scaling), by associating a voltage on each level beside the
>>> CPU frequency. However, this support is not yet ready, so it is not
>>> part of this series.
>>>
>>> Finally, the last patch is for arm-soc the arm-soc subsystem through
>>> mvebu and update the device tree to support the CPU frequency scaling.
>>>
>>> An update on the CPU clock driver is needed in order to take into
>>> account the DVFS setting. It's the purpose of an other series already
>>> sent, but is no dependencies between the series (for building or at
>>> runtime).
>>>
>>> Thanks,
>>>
>>> Gregory
>>>
>>> Changelog:
>>>
>>> v1 -> v2:
>>>
>>> - using syscon instead of nb_pm for the binding of the North bridge
>>> power management unit: reported by Rob Herring
>>>
>>> - fix sorting inside the big LITTLE section for the Kconfig: reported
>>> by Viresh Kumar
>>>
>>> - fix the bogus freq calculation in armada37xx_cpufreq_driver_init,
>>> bug reported by Andre Heider
>>>
>>> - use dev_pm_opp_remove() on the previous opp if dev_pm_opp_add()
>>> failed, reported by Viresh Kumar
>>>
>>> - add the Tested-by flag from Andre Heider on "cpufreq: Add DVFS
>>> support for Armada 37xx" patch
>>>
>>> Gregory CLEMENT (7):
>>> dt-bindings: marvell: Add documentation for the North Bridge PM on
>>> Armada 37xx
>>> cpufreq: ARM: sort the Kconfig menu
>>> cpufreq: sort the drivers in ARM part
>>> cpufreq: mvebu: Use dev_pm_opp_remove()
>>> MAINTAINERS: add new entries for Armada 37xx cpufreq driver
>>> cpufreq: Add DVFS support for Armada 37xx
>>> arm64: dts: marvell: armada-37xx: add nodes allowing cpufreq support
>>>
>>> .../bindings/arm/marvell/armada-37xx.txt | 19 ++
>>> MAINTAINERS | 1 +
>>> arch/arm64/boot/dts/marvell/armada-372x.dtsi | 1 +
>>> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 7 +
>>> drivers/cpufreq/Kconfig.arm | 89 ++++----
>>> drivers/cpufreq/Makefile | 9 +-
>>> drivers/cpufreq/armada-37xx-cpufreq.c | 241 +++++++++++++++++++++
>>> drivers/cpufreq/mvebu-cpufreq.c | 11 +-
>>> 8 files changed, 327 insertions(+), 51 deletions(-)
>>> create mode 100644 drivers/cpufreq/armada-37xx-cpufreq.c
>>
>> I'd like you to split patches [2-3/7] off this series as they aren't
>> exactly related to the other changes in it.
>
> Actually the patch 6 depend on patch 2 and 3. To be more precise they
> modify the same area inside the files drivers/cpufreq/Kconfig.arm and
> drivers/cpufreq/Makefile.
>
> So if I move them in an other series then there could be some merge
> conflicts.
That's fine. Merge conflicts are not a big issue to me.
^ permalink raw reply
* [PATCH v8 1/3] arm: npcm: add basic support for Nuvoton BMCs
From: Philippe Ombredanne @ 2017-12-07 21:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFd5g45+dNuayw=s08iwAj2wrUYNXnGd5SbA+OVvsL_J6APHGA@mail.gmail.com>
Brendan,
On Thu, Dec 7, 2017 at 9:37 PM, Brendan Higgins
<brendanhiggins@google.com> wrote:
> Any update on this?
>
> On Fri, Nov 17, 2017 at 11:07 AM, Brendan Higgins
> <brendanhiggins@google.com> wrote:
>> Adds basic support for the Nuvoton NPCM750 BMC.
>>
>> Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
>> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com>
>> Reviewed-by: Avi Fishman <avifishman70@gmail.com>
>> Tested-by: Tomer Maimon <tmaimon77@gmail.com>
>> Tested-by: Avi Fishman <avifishman70@gmail.com>
<snip>
>> --- /dev/null
>> +++ b/arch/arm/mach-npcm/npcm7xx.c
>> @@ -0,0 +1,25 @@
>> +/*
>> + * Copyright (c) 2017 Nuvoton Technology corporation.
>> + * Copyright 2017 Google, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
Have you considered using the new SPDX ids here instead of the
traditional license boilerplate?
This could come out this way:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017 Nuvoton Technology corporation.
// Copyright 2017 Google, Inc.
It is shorter and simpler, with a better code/comments ratio.
And if you wonder about why using C++ style comment, please check
Linus posts on the topic, as well as Thomas doc patches.
Thank you for your kind consideration!
--
Cordially
Philippe Ombredanne
^ permalink raw reply
* [GIT PULL] two dts compiler warning fixes for v4.15-rc cycle
From: Tony Lindgren @ 2017-12-07 21:19 UTC (permalink / raw)
To: linux-arm-kernel
From: "Tony Lindgren" <tony@atomide.com>
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v4.15/fixes-dt-warnings
for you to fetch changes up to c22fe696157dc94a25cc5396b43b29b6d6f4a189:
ARM: dts: Fix dm814x missing phy-cells property (2017-12-05 08:29:04 -0800)
----------------------------------------------------------------
Two fixes for dts compiler warnings
These recently started showing up with better dtc checks being
introduced.
----------------------------------------------------------------
Tony Lindgren (2):
ARM: dts: Fix elm interrupt compiler warning
ARM: dts: Fix dm814x missing phy-cells property
arch/arm/boot/dts/dm814x.dtsi | 1 +
arch/arm/boot/dts/omap4.dtsi | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
^ permalink raw reply
* [PATCH V6 3/7] device property: Introduce a common API to fetch device match data
From: Sakari Ailus @ 2017-12-07 22:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c2b38889-888a-3518-bf59-c2377f64a8ce@codeaurora.org>
On Thu, Dec 07, 2017 at 03:17:52PM -0500, Sinan Kaya wrote:
> On 12/7/2017 7:40 AM, Sakari Ailus wrote:
> > On Tue, Dec 05, 2017 at 12:04:48PM -0500, Sinan Kaya wrote:
> >> @@ -101,6 +103,8 @@ struct fwnode_operations {
> >> (*graph_get_port_parent)(struct fwnode_handle *fwnode);
> >> int (*graph_parse_endpoint)(const struct fwnode_handle *fwnode,
> >> struct fwnode_endpoint *endpoint);
> >> + void *(*get_match_data)(const struct fwnode_handle *fwnode,
> >> + struct device *dev);
> >
> > You can make dev const, too.
> >
>
> done, I couldn't change device_get_match_data() parameter const due to
> dev_fwnode() function.
>
> from /local/mnt/workspace/projects/caf/kernel/drivers/base/property.c:13:
>
> /local/mnt/workspace/projects/caf/kernel/drivers/base/property.c:1341:39: warning: passing argument 1 of 'dev_fwnode' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
> return fwnode_call_ptr_op(dev_fwnode(dev), device_get_match_data,
Right. Makes sense.
I guess it's not perhaps worth it introducing dev_fwnode_const just for
this. devices are seldom if ever const anyway.
--
Sakari Ailus
e-mail: sakari.ailus at iki.fi
^ permalink raw reply
* [PATCH v5 2/4] clk: meson-axg: add clocks dt-bindings required header
From: Rob Herring @ 2017-12-07 22:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207095300.15384-3-yixun.lan@amlogic.com>
On Thu, Dec 07, 2017 at 05:52:58PM +0800, Yixun Lan wrote:
> From: Qiufang Dai <qiufang.dai@amlogic.com>
>
> Add the required header for the clocks ID dt-bindings
> exported from various subsystem in the Meson-AXG SoC.
>
> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> include/dt-bindings/clock/axg-clkc.h | 71 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 71 insertions(+)
> create mode 100644 include/dt-bindings/clock/axg-clkc.h
Please add acks when posting new versions.
Rob
^ permalink raw reply
* [RFC v2 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
From: Rob Herring @ 2017-12-07 22:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512368735-27147-3-git-send-email-jliang@xilinx.com>
On Sun, Dec 03, 2017 at 10:25:35PM -0800, Wendy Liang wrote:
> Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
> in ZynqMP SoC used for the communication between various processor
> systems.
>
> Signed-off-by: Wendy Liang <jliang@xilinx.com>
> ---
> .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 104 +++++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH V6 3/7] device property: Introduce a common API to fetch device match data
From: Rafael J. Wysocki @ 2017-12-07 22:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207220642.qqiwf4vvk2gf42uf@valkosipuli.retiisi.org.uk>
On Thu, Dec 7, 2017 at 11:06 PM, Sakari Ailus <sakari.ailus@iki.fi> wrote:
> On Thu, Dec 07, 2017 at 03:17:52PM -0500, Sinan Kaya wrote:
>> On 12/7/2017 7:40 AM, Sakari Ailus wrote:
>> > On Tue, Dec 05, 2017 at 12:04:48PM -0500, Sinan Kaya wrote:
>> >> @@ -101,6 +103,8 @@ struct fwnode_operations {
>> >> (*graph_get_port_parent)(struct fwnode_handle *fwnode);
>> >> int (*graph_parse_endpoint)(const struct fwnode_handle *fwnode,
>> >> struct fwnode_endpoint *endpoint);
>> >> + void *(*get_match_data)(const struct fwnode_handle *fwnode,
>> >> + struct device *dev);
>> >
>> > You can make dev const, too.
>> >
>>
>> done, I couldn't change device_get_match_data() parameter const due to
>> dev_fwnode() function.
>>
>> from /local/mnt/workspace/projects/caf/kernel/drivers/base/property.c:13:
>>
>> /local/mnt/workspace/projects/caf/kernel/drivers/base/property.c:1341:39: warning: passing argument 1 of 'dev_fwnode' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
>> return fwnode_call_ptr_op(dev_fwnode(dev), device_get_match_data,
>
> Right. Makes sense.
>
> I guess it's not perhaps worth it introducing dev_fwnode_const just for
> this. devices are seldom if ever const anyway.
They cannot be const. Had they been const, it wouldn't have been
possible to register them even. :-)
^ permalink raw reply
* [PATCH 2/9] ASoC: sun4i-i2s: Add compatibility with A64 codec I2S
From: Vasily Khoruzhick @ 2017-12-07 22:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAEKpxBnWYiSq-Xrzj9MET61kGyVSJZPNnWpDh8jwnmdtw=GKtA@mail.gmail.com>
On Thu, Dec 7, 2017 at 1:21 AM, Code Kipper <codekipper@gmail.com> wrote:
> On 4 December 2017 at 08:34, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>> I'd keep it sun50i_a64_acodec_i2s, since other 3 I2S modules aren't
>> compatible with this one, but similar to H3.
>
> Well I wouldn't and the description of it is usage is clearly stated
> in the devicetree
> for the dai.
OK, how would you name 3 other I2S modules that are present in A64?
>> On Sun, Dec 3, 2017 at 10:42 PM, Code Kipper <codekipper@gmail.com> wrote:
>>> On 3 December 2017 at 21:41, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>>>> From: Marcus Cooper <codekipper@gmail.com>
>>>>
>>>> The I2S block used for the audio codec in the A64 is very similar
>>>> to what is used by the A10(sun4i) devices. However, its TX FIFO is
>>>> located at a different address.
>>>>
>>>> [vasilykh: - added fixed_wss and wss_value to A64 quirks,
>>>> - changed compatible to 'allwinner,sun50i-a64-acodec-i2s,
>>>> since A64 has 3 more I2S blocks that are not compatible
>>>> with audio codec I2S]
> This needs to be investigated more...I'm suspicious of the
> SUN8I_I2S_FMT0_LRCK_PERIOD value which is hardcoded to 0x1f.
> I've made this following change
> https://github.com/codekipper/linux-sunxi/commit/4c5fe5f5576cfbb2e1e94a99cd19dfdc9403ea50
> which seems to work for me but I would like to look at it with a logic
> analyser and test other sample depths.
> CK
I'm afraid it's not possible to get inside of SoC, since internal I2S
pins do not go out. And other 3 I2S modules are different from one for
internal codec.
>>>>
>>>> Signed-off-by: Marcus Cooper <codekipper@gmail.com>
>>>> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>>>> ---
>>>> .../devicetree/bindings/sound/sun4i-i2s.txt | 2 ++
>>>> sound/soc/sunxi/sun4i-i2s.c | 23 ++++++++++++++++++++++
>>>> 2 files changed, 25 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
>>>> index 05d7135a8d2f..ab86f266962a 100644
>>>> --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
>>>> +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
>>>> @@ -9,6 +9,7 @@ Required properties:
>>>> - "allwinner,sun4i-a10-i2s"
>>>> - "allwinner,sun6i-a31-i2s"
>>>> - "allwinner,sun8i-h3-i2s"
>>>> + - "allwinner,sun50i-a64-acodec-i2s"
>>>> - reg: physical base address of the controller and length of memory mapped
>>>> region.
>>>> - interrupts: should contain the I2S interrupt.
>>>> @@ -24,6 +25,7 @@ Required properties:
>>>> Required properties for the following compatibles:
>>>> - "allwinner,sun6i-a31-i2s"
>>>> - "allwinner,sun8i-h3-i2s"
>>>> + - "allwinner,sun50i-a64-acodec-i2s"
>>> I would keep the compatible format the same. ie.
>>> allwinner,sun50i-a64-i2s. The A33 for example uses the sun6i-a31-i2s
>>> for it's dai.
>>>
>>>> - resets: phandle to the reset line for this codec
>>>>
>>>> Example:
>>>> diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
>>>> index 54c16eb64713..2c060e015725 100644
>>>> --- a/sound/soc/sunxi/sun4i-i2s.c
>>>> +++ b/sound/soc/sunxi/sun4i-i2s.c
>>>> @@ -942,6 +942,25 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
>>>> .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
>>>> };
>>>>
>>>> +static const struct sun4i_i2s_quirks sun50i_a64_acodec_i2s_quirks = {
>>> ditto
>>>> + .has_reset = true,
>>>> + .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
>>>> + .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
>>>> + .has_slave_select_bit = true,
>>>> + .fixed_wss = true,
>>>> + .wss_value = 3,
>>>> + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
>>>> + .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
>>>> + .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
>>>> + .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
>>>> + .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
>>>> + .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
>>>> + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
>>>> + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
>>>> + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
>>>> + .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
>>>> +};
>>>> +
>>>> static int sun4i_i2s_init_regmap_fields(struct device *dev,
>>>> struct sun4i_i2s *i2s)
>>>> {
>>>> @@ -1146,6 +1165,10 @@ static const struct of_device_id sun4i_i2s_match[] = {
>>>> .compatible = "allwinner,sun8i-h3-i2s",
>>>> .data = &sun8i_h3_i2s_quirks,
>>>> },
>>>> + {
>>>> + .compatible = "allwinner,sun50i-a64-acodec-i2s",
>>>> + .data = &sun50i_a64_acodec_i2s_quirks,
>>> ditto
>>> BR,
>>> CK
>>>> + },
>>>> {}
>>>> };
>>>> MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
>>>> --
>>>> 2.15.0
>>>>
^ permalink raw reply
* [PATCH v3 06/12] dt-bindings: Document the Rockchip ISP1 bindings
From: Rob Herring @ 2017-12-07 23:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171206111939.1153-7-jacob-chen@iotwrt.com>
On Wed, Dec 06, 2017 at 07:19:33PM +0800, Jacob Chen wrote:
> From: Jacob Chen <jacob2.chen@rock-chips.com>
>
> Add DT bindings documentation for Rockchip ISP1
>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
> .../devicetree/bindings/media/rockchip-isp1.txt | 57 ++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp1.txt
>
> diff --git a/Documentation/devicetree/bindings/media/rockchip-isp1.txt b/Documentation/devicetree/bindings/media/rockchip-isp1.txt
> new file mode 100644
> index 000000000000..0971ed94ed69
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/rockchip-isp1.txt
> @@ -0,0 +1,57 @@
> +Rockchip SoC Image Signal Processing unit v1
> +----------------------------------------------
> +
> +Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
> +which contains image processing, scaling, and compression funcitons.
> +
> +Required properties:
> + - compatible: value should be one of the following
> + "rockchip,rk3288-cif-isp";
> + "rockchip,rk3399-cif-isp";
> + - reg : offset and length of the register set for the device.
> + - interrupts: should contain ISP interrupt.
> + - clocks: phandle to the required clocks.
> + - clock-names: required clock name.
> + - iommus: required a iommu node.
> +
> +The device node should contain one 'port' child node with child 'endpoint'
> +nodes, according to the bindings defined in Documentation/devicetree/bindings/
> +media/video-interfaces.txt.
> +
> +For sensor with a parallel video bus, it could be linked directly to the isp.
> +For sensor with a MIPI CSI-2 video bus, it should be linked through the
> +MIPI-DPHY, which is defined in rockchip-mipi-dphy.txt.
As I mentioned on the last version, you need to list that there are 2
endpoints for the port and what their assignment is.
Rob
^ permalink raw reply
* [PATCH v3 07/12] dt-bindings: Document the Rockchip MIPI RX D-PHY bindings
From: Rob Herring @ 2017-12-07 23:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171206111939.1153-8-jacob-chen@iotwrt.com>
On Wed, Dec 06, 2017 at 07:19:34PM +0800, Jacob Chen wrote:
> From: Jacob Chen <jacob2.chen@rock-chips.com>
>
> Add DT bindings documentation for Rockchip MIPI D-PHY RX
>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
> .../bindings/media/rockchip-mipi-dphy.txt | 71 ++++++++++++++++++++++
> 1 file changed, 71 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
>
> diff --git a/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt b/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
> new file mode 100644
> index 000000000000..cef9450db051
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
> @@ -0,0 +1,71 @@
> +Rockchip SoC MIPI RX D-PHY
> +-------------------------------------------------------------
> +
> +Required properties:
> +
> +- compatible: value should be one of the following
> + "rockchip,rk3288-mipi-dphy";
> + "rockchip,rk3399-mipi-dphy";
Drop the ';'
> +- rockchip,grf: GRF regs.
> +- bus-width : maximum number of data lanes supported (SoC specific);
> +- clocks : list of clock specifiers, corresponding to entries in
> + clock-names property;
> +- clock-names: required clock name.
> +
> +The device node should contain two 'port' child node, according to the bindings
> +defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
> +The first port should be connected to sensor nodes, and the second port should be
> +connected to isp node. The following are properties specific to those nodes.
Need to list how many endpoints if there are more than 1.
> +
> +endpoint node
> +-------------
> +
> +- data-lanes : (required) an array specifying active physical MIPI-CSI2
> + data input lanes and their mapping to logical lanes; the
> + array's content is unused, only its length is meaningful;
> +
> +Device node example
> +-------------------
> +
> + mipi_dphy_rx0: mipi-dphy-rx0 {
> + compatible = "rockchip,rk3399-mipi-dphy";
> + clocks = <&cru SCLK_MIPIDPHY_REF>,
> + <&cru SCLK_DPHY_RX0_CFG>,
> + <&cru PCLK_VIO_GRF>;
> + clock-names = "dphy-ref", "dphy-cfg", "grf";
> + power-domains = <&power RK3399_PD_VIO>;
> + bus-width = <4>;
rockchip,grf?
No other registers? Can you just make this a child of the grf block with
a proper reg property for the range of dphy registers?
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mipi_in_wcam: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint = <&wcam_out>;
> + data-lanes = <1 2>;
> + };
> + mipi_in_ucam: endpoint at 1 {
> + reg = <1>;
> + remote-endpoint = <&ucam_out>;
> + data-lanes = <1>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dphy_rx0_out: endpoint at 0 {
> + reg = <0>;
Don't need reg and everything associated with it if there's only 1
endpoint.
> + remote-endpoint = <&isp0_mipi_in>;
> + };
> + };
> + };
> + };
> \ No newline at end of file
Please fix.
Rob
^ permalink raw reply
* [PATCH v6 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs
From: Rob Herring @ 2017-12-07 23:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207102026.14977-3-liwei213@huawei.com>
On Thu, Dec 07, 2017 at 06:20:23PM +0800, Li Wei wrote:
> add ufs node document for Hisilicon.
>
> Signed-off-by: Li Wei <liwei213@huawei.com>
> ---
Version history?
> Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 38 ++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
>
> diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
> new file mode 100644
> index 000000000000..73e10698960e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
> @@ -0,0 +1,38 @@
> +* Hisilicon Universal Flash Storage (UFS) Host Controller
> +
> +UFS nodes are defined to describe on-chip UFS hardware macro.
> +Each UFS Host Controller should have its own node.
> +
> +Required properties:
> +- compatible : compatible list, contains one of the following -
> + "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
> + host controller present on Hi36xx chipset.
> +- reg : should contain UFS register address space & UFS SYS CTRL register address,
> +- interrupt-parent : interrupt device
> +- interrupts : interrupt number
> +- clocks : List of phandle and clock specifier pairs
> +- clock-names : List of clock input name strings sorted in the same
> + order as the clocks property. "ref_clk", "phy_clk" is optional
> +- resets : reset node register, one reset the clk and the other reset the controller
> +- reset-names : describe reset node register
> +
> +Example:
> +
> + ufs: ufs at ff3b0000 {
> + compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
> + /* 0: HCI standard */
> + /* 1: UFS SYS CTRL */
> + reg = <0x0 0xff3b0000 0x0 0x1000>,
> + <0x0 0xff3b1000 0x0 0x1000>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
> + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
> + clock-names = "ref_clk", "phy_clk";
> + freq-table-hz = <0 0>, <0 0>;
? Not documented.
> + /* offset: 0x84; bit: 12 */
> + /* offset: 0x84; bit: 7 */
> + resets = <&crg_rst 0x84 12>,
> + <&crg_rst 0x84 7>;
> + reset-names = "rst", "assert";
> + };
> --
> 2.15.0
>
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