* [PATCH v3 4/9] ARM: dts: imx7-colibri: use NAND_CE1 as GPIO
From: Stefan Agner @ 2017-12-19 18:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219181038.1369-1-stefan@agner.ch>
All Colibri iMX7 SKUs use either single-die NAND or eMMC, hence
NAND_CE1 is not used on the module and can be used as a GPIO by
carrier boards.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx7-colibri.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index e4e32aa786f4..f61041af026a 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -329,6 +329,7 @@
MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
+ MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
@@ -439,7 +440,6 @@
MX7D_PAD_SD3_CLK__NAND_CLE 0x71
MX7D_PAD_SD3_CMD__NAND_ALE 0x71
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
- MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
--
2.15.1
^ permalink raw reply related
* [PATCH v3 3/9] ARM: dts: imx7-colibri: mux pull-ups where appropriate
From: Stefan Agner @ 2017-12-19 18:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219181038.1369-1-stefan@agner.ch>
Use pull-ups instead of pull-downs for the pins which are already
pulled-up externally.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx7-colibri.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index dae6b561145b..e4e32aa786f4 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -307,17 +307,17 @@
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
- MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
- MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
+ MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
+ MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x74 /* SODIMM 63 */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
- MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0X14 /* SODIMM 77 */
+ MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
- MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x14 /* SODIMM 91 */
+ MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
- MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x14 /* SODIMM 105 */
- MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x14 /* SODIMM 107 */
+ MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
+ MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */
MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
@@ -333,7 +333,7 @@
MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 */
+ MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
@@ -357,7 +357,7 @@
pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
fsl,pins = <
MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x14 /* SODIMM 69 */
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
@@ -378,8 +378,8 @@
MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
- MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x14 /* SODIMM 146 */
- MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x14 /* SODIMM 148 */
+ MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
+ MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
>;
};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 2/9] ARM: dts: imx7-colibri: make sure multiplexed pins are not active
From: Stefan Agner @ 2017-12-19 18:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219181038.1369-1-stefan@agner.ch>
The Colibri pins PWM<A> and <D> are multiplexed on the module, make
sure the secondary SoC pin is not active.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx7-colibri.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index 60ea7557d8c9..dae6b561145b 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -507,6 +507,7 @@
pinctrl_pwm1: pwm1-grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79
+ MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4
>;
};
@@ -525,6 +526,7 @@
pinctrl_pwm4: pwm4-grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79
+ MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4
>;
};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 1/9] ARM: dts: imx7-colibri: move and rename USB Host power regulator
From: Stefan Agner @ 2017-12-19 18:10 UTC (permalink / raw)
To: linux-arm-kernel
The Colibri default which enables USB Host power is not necessarily
tied to the OTG2 controller, some carrier board use the pin to
control USB power for both controllers. Hence name the pinctrl
group more generic.
Also move the regulator to the generic eval-v3 device tree since
the regulator is always on the carrier board. In the Colibri iMX7S
case the regulator is just not used. This allows to reuse the
regulator in a upcoming SKU Colibri iMX7D 1GB with eMMC.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 11 +++++++++++
arch/arm/boot/dts/imx7-colibri.dtsi | 2 +-
arch/arm/boot/dts/imx7d-colibri-eval-v3.dts | 13 +------------
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index 18bebd6d8d47..5ecb3a858c5a 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -70,6 +70,17 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ vin-supply = <®_5v0>;
+ };
};
&bl {
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index bb5bf94f1a32..60ea7557d8c9 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -559,7 +559,7 @@
>;
};
- pinctrl_usbotg2_reg: gpio-usbotg2-vbus {
+ pinctrl_usbh_reg: gpio-usbh-vbus {
fsl,pins = <
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
>;
diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
index a608a14d8c85..136e11ab4893 100644
--- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
@@ -48,20 +48,9 @@
model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d",
"fsl,imx7d";
-
- reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg2_reg>;
- regulator-name = "VCC_USB[1-4]";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
- vin-supply = <®_5v0>;
- };
};
&usbotg2 {
- vbus-supply = <®_usb_otg2_vbus>;
+ vbus-supply = <®_usbh_vbus>;
status = "okay";
};
--
2.15.1
^ permalink raw reply related
* [PATCH 00/10] arm64: 52-bit physical address support
From: Bob Picco @ 2017-12-19 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ec1d1613-0005-3a5d-f623-837c743e683d@arm.com>
Kristina Martsenko wrote: [Tue Dec 19 2017, 12:15:46PM EST]
> On 14/12/17 17:52, Bob Picco wrote:
> > Kristina Martsenko wrote: [Wed Dec 13 2017, 12:07:15PM EST]
> >> Hi,
> >>
> >> This series adds 52-bit physical address space support to arm64, up from
> >> the current 48 bits. This is an ARMv8.2 feature (ARMv8.2-LPA).
> >>
> >> The series is based on 4.15-rc3. It has been lightly tested on an ARM
> >> Fast Model. There's still some cases and areas to think through, as well
> >> as more testing to do.
> >>
> >> Patches for SMMU 52-bit PA support have been sent separately [1]. A GIC
> >> ITS patch has already been merged [2]. ARMv8.2 also allows 52-bit IPA,
> >> but support for that is not part of this series.
> >>
> >> This version mostly addresses various review comments received.
> >>
> >> Changes from RFC:
> >> - Split kconfig symbol into two patches, to enable 52-bit PA at the end
> >> - Patch #3: Changed phys_to_ttbr to use a macro, added an #include
> >> - Patch #4: Changed phys_to_pte to use a macro
> >> - Patch #6: Replaced __phys_to_pte with __phys_to_pte_val (same for
> >> pmd/pud/pgd)
> >> - Patch #6: Changed __phys_to_pte_val, __pte_to_phys, and
> >> pgtable-hwdef.h macros
> >> - Patches #5, #6: Removed kvm_extended_idmap_pgd, inlined its code,
> >> moved the comment
> >> - Patch #5: Added pfn_pud definition (to make the kernel build on that
> >> commit)
> >>
> >> Thanks,
> >> Kristina
> >>
> >> [1] https://www.spinics.net/lists/arm-kernel/msg619040.html
> >> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=30ae9610d275f8f03f5bf7612ce71d8af6fc400b
> >>
> >>
> >> Kristina Martsenko (10):
> >> arm64: add kconfig symbol to configure physical address size
> >> arm64: limit PA size to supported range
> >> arm64: handle 52-bit addresses in TTBR
> >> arm64: head.S: handle 52-bit PAs in PTEs in early page table setup
> >> arm64: don't open code page table entry creation
> >> arm64: handle 52-bit physical addresses in page table entries
> >> arm64: increase PHYS_MASK to 52 bits
> >> arm64: increase sparsemem MAX_PHYSMEM_BITS to 52
> >> arm64: allow ID map to be extended to 52 bits
> >> arm64: enable 52-bit physical address support
> >>
> >> arch/arm/include/asm/kvm_mmu.h | 7 ++
> >> arch/arm64/Kconfig | 29 ++++++++
> >> arch/arm64/include/asm/assembler.h | 31 ++++++++-
> >> arch/arm64/include/asm/kvm_mmu.h | 21 +++++-
> >> arch/arm64/include/asm/mmu_context.h | 16 ++++-
> >> arch/arm64/include/asm/pgalloc.h | 6 +-
> >> arch/arm64/include/asm/pgtable-hwdef.h | 19 +++++-
> >> arch/arm64/include/asm/pgtable.h | 53 ++++++++++++---
> >> arch/arm64/include/asm/sparsemem.h | 2 +-
> >> arch/arm64/include/asm/sysreg.h | 8 +++
> >> arch/arm64/kernel/head.S | 118 +++++++++++++++++++++------------
> >> arch/arm64/kernel/hibernate-asm.S | 12 ++--
> >> arch/arm64/kernel/hibernate.c | 5 +-
> >> arch/arm64/kvm/hyp-init.S | 26 ++++----
> >> arch/arm64/kvm/hyp/s2-setup.c | 2 +
> >> arch/arm64/mm/mmu.c | 15 +++--
> >> arch/arm64/mm/pgd.c | 8 +++
> >> arch/arm64/mm/proc.S | 19 +++---
> >> virt/kvm/arm/arm.c | 2 +-
> >> virt/kvm/arm/mmu.c | 12 ++--
> >> 20 files changed, 302 insertions(+), 109 deletions(-)
> >>
> >> --
> >> 2.1.4
> > Hi Kristina,
> >
> > I boot tested but on VM and had a couple issues. I will examine and share
> > should the issues be of value.
> > Tested-by: Bob Picco <bob.picco@oracle.com>
>
> Thanks for testing! I assume it was on a VM with less than 52 bits of
> PA? In any case, let me know if you find any issues.
Hi Kristina,
Yes it was substantially less than 52b PA. I was surprised we booted.
>
> > I reviewed and thank you. Your effort caused me to return to some code
> > examined/learned during the last few months.
> > Reviewed-by: Bob Picco <bob.picco@oracle.com>
>
> Thanks for reviewing! Hope it was useful.
You are welcome. Well I had to commence at some point. I happened to review
most of boot up two months ago. Your effort caused me to return and review
more... A few more iterations before being reasonably solid.
bob
>
> Kristina
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 6/6] ARM: imx_v6_v7_defconfig: Enable Dialog Semicondocter DA9062 driver
From: Fabio Estevam @ 2017-12-19 17:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5CyMoY+24ub09Lp4VHFn=O6FqFELfQzH-WDv1H9OweoHw@mail.gmail.com>
On Tue, Dec 19, 2017 at 3:16 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
> <s.riedmueller@phytec.de> wrote:
>> The phyCORE-i.MX 6 uses the DA9062/63 PMIC, RTC and Watchdog driver.
>>
>> Enable this option by default.
>
> "these options"
>
>>
>> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
>
> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
There is a typo in "Semiconductor" in the Subject.
^ permalink raw reply
* [PATCH 1/2] usb: musb: un-break davinci glue layer
From: Bin Liu @ 2017-12-19 17:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171208192355.32735-1-amery@hanoverdisplays.com>
Hi Alejandro,
On Fri, Dec 08, 2017 at 07:23:54PM +0000, Alejandro Mery wrote:
> MUSB's davinci glue was made to depend on BROKEN by Felipe Balbi back in
> 2013 because of lack of active development. needed changes were actually trivial
>
> Fixes: 787f5627bec8 (usb: musb: make davinci and da8xx glues depend on BROKEN)
> Signed-off-by: Alejandro Mery <amery@hanoverdisplays.com>
Thanks for the effort to re-enable this driver. But due to lack of
development, other than the phy and fifo mode which you try to fix with
these two patches, the driver still doesn't fit in the current driver
framework, for example,
- the driver depends on mach/ header for CPU and board type;
- clk control is not separated;
- gpio control vbus should use extcon driver;
So I feel it is not ready to un-broken it yet, unless others have
different opinion.
But I could take these two patches if not remove BROKEN from Kconfig.
Regards,
-Bin.
^ permalink raw reply
* [PATCH 2/6] ARM: dts: imx6: Add initial support for phyBOARD-Mira
From: Christoph Fritz @ 2017-12-19 17:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5CSQSpPXTnR69HqHfKZiUpi+eqonqjuEu9mgBECsWG_5g@mail.gmail.com>
On Tue, 2017-12-19 at 15:10 -0200, Fabio Estevam wrote:
> On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
> <s.riedmueller@phytec.de> wrote:
>
> > + reg_pcie: regulator-pcie {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pcie_reg>;
> > + compatible = "regulator-fixed";
> > + regulator-name = "mPCIe_1V5";
> > + regulator-min-microvolt = <1500000>;
> > + regulator-max-microvolt = <1500000>;
> > + gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> > + regulator-always-on;
>
> Instead of using 'regulator-always-on' here, you could use:
>
> vpcie-supply = <®_pcie>;
>
> under the &pcie node
>
> > + panel {
> > + compatible = "auo,g104sn02";
>
> I could not find this compatible in linux-next.
FYI: I've sent this a few days ago:
https://www.spinics.net/lists/devicetree/msg206590.html
^ permalink raw reply
* [PATCH 6/6] ARM: imx_v6_v7_defconfig: Enable Dialog Semicondocter DA9062 driver
From: Fabio Estevam @ 2017-12-19 17:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-7-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> The phyCORE-i.MX 6 uses the DA9062/63 PMIC, RTC and Watchdog driver.
>
> Enable this option by default.
"these options"
>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH] ARM: dts: add minimal device tree for compute model 3
From: Stefan Wahren @ 2017-12-19 17:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171124121813.11318-1-kernel@martin.sperl.org>
Hi Martin,
> kernel at martin.sperl.org hat am 24. November 2017 um 13:18 geschrieben:
>
>
> From: Martin Sperl <kernel@martin.sperl.org>
>
> Add a minimal working device tree for the compute model 3
> for both arm and arm64.
>
just a note before you send a V2. Recently i looked at the CM datasheet (revision 1.0) and noticed on the block diagram (page 8) that the CM3 eMMC I/O voltage is fixed at 1.8 Volt (doesn't apply to CM3 lite). Providing a fixed regulator for vmmc/vqmmc-supply [1] would give the MMC core the chance to figure out the right voltage.
[1] - http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mmc/mmc.txt
^ permalink raw reply
* [PATCH 00/10] arm64: 52-bit physical address support
From: Kristina Martsenko @ 2017-12-19 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214175259.GA4219@zareason>
On 14/12/17 17:52, Bob Picco wrote:
> Kristina Martsenko wrote: [Wed Dec 13 2017, 12:07:15PM EST]
>> Hi,
>>
>> This series adds 52-bit physical address space support to arm64, up from
>> the current 48 bits. This is an ARMv8.2 feature (ARMv8.2-LPA).
>>
>> The series is based on 4.15-rc3. It has been lightly tested on an ARM
>> Fast Model. There's still some cases and areas to think through, as well
>> as more testing to do.
>>
>> Patches for SMMU 52-bit PA support have been sent separately [1]. A GIC
>> ITS patch has already been merged [2]. ARMv8.2 also allows 52-bit IPA,
>> but support for that is not part of this series.
>>
>> This version mostly addresses various review comments received.
>>
>> Changes from RFC:
>> - Split kconfig symbol into two patches, to enable 52-bit PA at the end
>> - Patch #3: Changed phys_to_ttbr to use a macro, added an #include
>> - Patch #4: Changed phys_to_pte to use a macro
>> - Patch #6: Replaced __phys_to_pte with __phys_to_pte_val (same for
>> pmd/pud/pgd)
>> - Patch #6: Changed __phys_to_pte_val, __pte_to_phys, and
>> pgtable-hwdef.h macros
>> - Patches #5, #6: Removed kvm_extended_idmap_pgd, inlined its code,
>> moved the comment
>> - Patch #5: Added pfn_pud definition (to make the kernel build on that
>> commit)
>>
>> Thanks,
>> Kristina
>>
>> [1] https://www.spinics.net/lists/arm-kernel/msg619040.html
>> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=30ae9610d275f8f03f5bf7612ce71d8af6fc400b
>>
>>
>> Kristina Martsenko (10):
>> arm64: add kconfig symbol to configure physical address size
>> arm64: limit PA size to supported range
>> arm64: handle 52-bit addresses in TTBR
>> arm64: head.S: handle 52-bit PAs in PTEs in early page table setup
>> arm64: don't open code page table entry creation
>> arm64: handle 52-bit physical addresses in page table entries
>> arm64: increase PHYS_MASK to 52 bits
>> arm64: increase sparsemem MAX_PHYSMEM_BITS to 52
>> arm64: allow ID map to be extended to 52 bits
>> arm64: enable 52-bit physical address support
>>
>> arch/arm/include/asm/kvm_mmu.h | 7 ++
>> arch/arm64/Kconfig | 29 ++++++++
>> arch/arm64/include/asm/assembler.h | 31 ++++++++-
>> arch/arm64/include/asm/kvm_mmu.h | 21 +++++-
>> arch/arm64/include/asm/mmu_context.h | 16 ++++-
>> arch/arm64/include/asm/pgalloc.h | 6 +-
>> arch/arm64/include/asm/pgtable-hwdef.h | 19 +++++-
>> arch/arm64/include/asm/pgtable.h | 53 ++++++++++++---
>> arch/arm64/include/asm/sparsemem.h | 2 +-
>> arch/arm64/include/asm/sysreg.h | 8 +++
>> arch/arm64/kernel/head.S | 118 +++++++++++++++++++++------------
>> arch/arm64/kernel/hibernate-asm.S | 12 ++--
>> arch/arm64/kernel/hibernate.c | 5 +-
>> arch/arm64/kvm/hyp-init.S | 26 ++++----
>> arch/arm64/kvm/hyp/s2-setup.c | 2 +
>> arch/arm64/mm/mmu.c | 15 +++--
>> arch/arm64/mm/pgd.c | 8 +++
>> arch/arm64/mm/proc.S | 19 +++---
>> virt/kvm/arm/arm.c | 2 +-
>> virt/kvm/arm/mmu.c | 12 ++--
>> 20 files changed, 302 insertions(+), 109 deletions(-)
>>
>> --
>> 2.1.4
> Hi Kristina,
>
> I boot tested but on VM and had a couple issues. I will examine and share
> should the issues be of value.
> Tested-by: Bob Picco <bob.picco@oracle.com>
Thanks for testing! I assume it was on a VM with less than 52 bits of
PA? In any case, let me know if you find any issues.
> I reviewed and thank you. Your effort caused me to return to some code
> examined/learned during the last few months.
> Reviewed-by: Bob Picco <bob.picco@oracle.com>
Thanks for reviewing! Hope it was useful.
Kristina
^ permalink raw reply
* [PATCH 5/6] ARM: dts: imx6: Add support for phyBOARD-Mira with i.MX 6QuadPlus
From: Fabio Estevam @ 2017-12-19 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-6-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> +/ {
> + model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
> + compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06",
> + "phytec,imx6qdl-pcm058", "fsl,imx6qp";
> +
> + aliases {
> + ipu1 = &ipu2;
> + };
Same comment as previous patch. You can drop this alias.
^ permalink raw reply
* [PATCH 4/6] ARM: dts: imx6: Add support for phxBOARD-Mira i.MX 6 DualLight/Solo RDK
From: Fabio Estevam @ 2017-12-19 17:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-5-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> From: Christian Hemp <c.hemp@phytec.de>
>
> Add support for the PHYTEC phyBOARD-Mira Low-Cost Rapid Development Kit
> with i.MX 6DualLight/Solo with NAND.
>
> Following interfaces are supported:
> - 100 MBit Ethernet
> - USB Host
> - RS232
> - HDMI
>
> Signed-off-by: Christian Hemp <c.hemp@phytec.de>
> Signed-off-by: Stefan Christ <s.christ@phytec.de>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH 3/6] ARM: dts: imx6: Add support for phyBOARD-Mira i.MX 6Quad/Dual RDK
From: Fabio Estevam @ 2017-12-19 17:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-4-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> +/ {
> + model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
> + compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06",
> + "phytec,imx6qdl-pcm058", "fsl,imx6q";
> +
> + aliases {
> + ipu1 = &ipu2;
> + };
This alias is not needed as it is part of imx6q.dtsi.
> +/ {
> + model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
> + compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06",
> + "phytec,imx6qdl-pcm058", "fsl,imx6q";
> +
> + aliases {
> + ipu1 = &ipu2;
> + };
Ditto.
^ permalink raw reply
* pwm: atmel-tcb: Delete an error message for a failed memory allocation in atmel_tcb_pwm_probe()
From: SF Markus Elfring @ 2017-12-19 17:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6d607786-4c1b-0949-0768-1bc0a4749fd5@microchip.com>
>> Omit an extra message for a memory allocation failure in this function.
>>
>> This issue was detected by using the Coccinelle software.
>
> Can you point which coccinelle script highlited this issue?
Not directly (so far).
I constructed an approach for the semantic patch language based on
information from the script ?checkpatch.pl?.
Would you like to improve it any ways?
Regards,
Markus
^ permalink raw reply
* [PATCH 2/6] ARM: dts: imx6: Add initial support for phyBOARD-Mira
From: Fabio Estevam @ 2017-12-19 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-3-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> + reg_pcie: regulator-pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie_reg>;
> + compatible = "regulator-fixed";
> + regulator-name = "mPCIe_1V5";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> + regulator-always-on;
Instead of using 'regulator-always-on' here, you could use:
vpcie-supply = <®_pcie>;
under the &pcie node
> + panel {
> + compatible = "auo,g104sn02";
I could not find this compatible in linux-next.
> + i2c_rtc: rtc at 68 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rtc_int>;
> + compatible = "mc,rv4162";
I could not find this compatible in linux-next.
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
The imx driver ignores the polarity and it is active high only when
'reset-gpio-active-high' property is present.
The correct here would be: reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + fsl,uart-has-rtscts;
uart-has-rtscts, please.
^ permalink raw reply
* [PATCH 1/6] ARM: dts: imx6: Add initial support for phyCORE-i.MX 6 SOM
From: Fabio Estevam @ 2017-12-19 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-2-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> +
> +/ {
> + model = "PHYTEC phyCORE-i.MX 6";
> + compatible = "phytec,imx6qdl-pcm058", "fsl,imx6qdl";
> +
> + aliases {
> + ipu0 = &ipu1;
Is this alias needed?
> + rtc1 = &da9062_rtc;
> + rtc2 = &snvs_rtc;
> + };
> +
> + /*
> + * Set the minimum memory size here and
> + * let the bootloader set the real size.
> + */
> + memory {
memory at 10000000 so that you don't get warnings when building with W=1.
Also, please build W=1 and make sure to not introduce any build
warning in this series.
> +&i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + eeprom: eeprom at 50 {
> + compatible = "cat,24c32";
This compatible is not documented.
^ permalink raw reply
* [PATCH net 3/3] net: mvneta: eliminate wrong call to handle rx descriptor error
From: Gregory CLEMENT @ 2017-12-19 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219165947.28516-1-gregory.clement@free-electrons.com>
From: Yelena Krivosheev <yelena@marvell.com>
There are few reasons in mvneta_rx_swbm() function when received packet
is dropped. mvneta_rx_error() should be called only if error bit [16]
is set in rx descriptor.
[gregory.clement at free-electrons.com: add fixes tag]
Cc: stable at vger.kernel.org
Fixes: dc35a10f68d3 ("net: mvneta: bm: add support for hardware buffer management")
Signed-off-by: Yelena Krivosheev <yelena@marvell.com>
Tested-by: Dmitri Epshtein <dima@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 1e0835655c93..a539263cd79c 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -1962,9 +1962,9 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo,
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
(rx_status & MVNETA_RXD_ERR_SUMMARY)) {
+ mvneta_rx_error(pp, rx_desc);
err_drop_frame:
dev->stats.rx_errors++;
- mvneta_rx_error(pp, rx_desc);
/* leave the descriptor untouched */
continue;
}
--
2.15.1
^ permalink raw reply related
* [PATCH net 2/3] net: mvneta: use proper rxq_number in loop on rx queues
From: Gregory CLEMENT @ 2017-12-19 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219165947.28516-1-gregory.clement@free-electrons.com>
From: Yelena Krivosheev <yelena@marvell.com>
When adding the RX queue association with each CPU, a typo was made in
the mvneta_cleanup_rxqs() function. This patch fixes it.
[gregory.clement at free-electrons.com: add commit log and fixes tag]
Cc: stable at vger.kernel.org
Fixes: 2dcf75e2793c ("net: mvneta: Associate RX queues with each CPU")
Signed-off-by: Yelena Krivosheev <yelena@marvell.com>
Tested-by: Dmitri Epshtein <dima@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 16b2bfb2cf51..1e0835655c93 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3015,7 +3015,7 @@ static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
{
int queue;
- for (queue = 0; queue < txq_number; queue++)
+ for (queue = 0; queue < rxq_number; queue++)
mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
}
--
2.15.1
^ permalink raw reply related
* [PATCH net 1/3] net: mvneta: clear interface link status on port disable
From: Gregory CLEMENT @ 2017-12-19 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219165947.28516-1-gregory.clement@free-electrons.com>
From: Yelena Krivosheev <yelena@marvell.com>
When port connect to PHY in polling mode (with poll interval 1 sec),
port and phy link status must be synchronize in order don't loss link
change event.
[gregory.clement at free-electrons.com: add fixes tag]
Cc: <stable@vger.kernel.org>
Fixes: c5aff18204da ("net: mvneta: driver for Marvell Armada 370/XP network unit")
Signed-off-by: Yelena Krivosheev <yelena@marvell.com>
Tested-by: Dmitri Epshtein <dima@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index bc93b69cfd1e..16b2bfb2cf51 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -1214,6 +1214,10 @@ static void mvneta_port_disable(struct mvneta_port *pp)
val &= ~MVNETA_GMAC0_PORT_ENABLE;
mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
+ pp->link = 0;
+ pp->duplex = -1;
+ pp->speed = 0;
+
udelay(200);
}
--
2.15.1
^ permalink raw reply related
* [PATCH net 0/3] Few mvneta fixes
From: Gregory CLEMENT @ 2017-12-19 16:59 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
here it is a small series of fixes found on the mvneta driver. They
had been already used in the vendor kernel and are now ported to
mainline.
Thanks,
Gregory
Yelena Krivosheev (3):
net: mvneta: clear interface link status on port disable
net: mvneta: use proper rxq_number in loop on rx queues
net: mvneta: eliminate wrong call to handle rx descriptor error
drivers/net/ethernet/marvell/mvneta.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
--
2.15.1
^ permalink raw reply
* [PATCH V1 1/1] iommu: Make sure device's ID array elements are unique
From: Alex Williamson @ 2017-12-19 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513696821-32291-1-git-send-email-tomasz.nowicki@caviumnetworks.com>
On Tue, 19 Dec 2017 16:20:21 +0100
Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> wrote:
> While iterating over DMA aliases for a PCI device, for some rare cases
> (i.e. PCIe-to-PCI/X bridges) we may get exactly the same ID as initial child
> device. In turn, the same ID may get registered for a device multiple times.
> Eventually IOMMU driver may try to configure the same ID within domain
> multiple times too which for some IOMMU drivers is illegal and causes kernel
> panic.
>
> Rule out ID duplication prior to device ID array registration.
>
> CC: stable at vger.kernel.org # v4.14+
You've identified a release, is there a specific commit this fixes?
> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com>
> ---
> drivers/iommu/iommu.c | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
> index 3de5c0b..9b2c138 100644
> --- a/drivers/iommu/iommu.c
> +++ b/drivers/iommu/iommu.c
> @@ -1945,6 +1945,31 @@ void iommu_fwspec_free(struct device *dev)
> }
> EXPORT_SYMBOL_GPL(iommu_fwspec_free);
>
> +static void iommu_fwspec_remove_ids_dup(struct device *dev, u32 *ids,
> + int *num_ids)
> +{
> + struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> + int i, j, k, valid_ids = *num_ids;
> +
> + for (i = 0; i < valid_ids; i++) {
> + for (j = 0; j < fwspec->num_ids; j++) {
> + if (ids[i] != fwspec->ids[j])
> + continue;
> +
> + dev_info(dev, "found 0x%x ID duplication, skipped\n",
> + ids[i]);
> +
> + for (k = i + 1; k < valid_ids; k++)
> + ids[k - 1] = ids[k];
Use memmove()?
> +
> + valid_ids--;
> + break;
At this point ids[i] is not the ids[i] that we tested for dupes, it's
what was ids[i + 1], but we're going to i++ on the next iteration and
we therefore never test that entry.
> + }
> + }
> +
> + *num_ids = valid_ids;
> +}
> +
> int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids)
> {
> struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> @@ -1954,6 +1979,9 @@ int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids)
> if (!fwspec)
> return -EINVAL;
>
> + /* Rule out IDs already registered */
> + iommu_fwspec_remove_ids_dup(dev, ids, &num_ids);
> +
> size = offsetof(struct iommu_fwspec, ids[fwspec->num_ids + num_ids]);
> if (size > sizeof(*fwspec)) {
> fwspec = krealloc(dev->iommu_fwspec, size, GFP_KERNEL);
^ permalink raw reply
* [PATCH 0/3] irqchip: irq-bcm2836: add support for DT interrupt polarity
From: Marc Zyngier @ 2017-12-19 16:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d0c81267-8379-d4a1-ec56-fec3492c1df6@i2se.com>
On 19/12/17 07:02, Stefan Wahren wrote:
> Hi Marc,
>
> Am 11.12.2017 um 21:39 schrieb Stefan Wahren:
>> This patch series implements DT polarity support for the 1st level interrupt
>> controller.
>>
>> Stefan Wahren (3):
>> dt-bindings: bcm2836-l1-intc: add interrupt polarity support
>> irqchip: irq-bcm2836: add support for DT interrupt polarity
>> ARM: dts: bcm283x: Define polarity of per-cpu interrupts
>>
>> .../interrupt-controller/brcm,bcm2836-l1-intc.txt | 4 +-
>> arch/arm/boot/dts/bcm2836.dtsi | 14 +++----
>> arch/arm/boot/dts/bcm2837.dtsi | 12 +++---
>> arch/arm/boot/dts/bcm283x.dtsi | 1 +
>> drivers/irqchip/irq-bcm2836.c | 46 +++++++++++++---------
>> 5 files changed, 44 insertions(+), 33 deletions(-)
>>
>
> is this series okay?
Yes, it does look good. I'll queue that for 4.16.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH V1 0/1] Fix kernel panic caused by device ID duplication presented to the IOMMU
From: Robin Murphy @ 2017-12-19 16:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513696436-31834-1-git-send-email-tomasz.nowicki@caviumnetworks.com>
Hi Tomasz,
On 19/12/17 15:13, Tomasz Nowicki wrote:
> Here is my lspci output of ThunderX2 for which I am observing kernel panic coming from
> SMMUv3 driver -> arm_smmu_write_strtab_ent() -> BUG_ON(ste_live):
>
> # lspci -vt
> -[0000:00]-+-00.0-[01-1f]--+ [...]
> + [...]
> \-00.0-[1e-1f]----00.0-[1f]----00.0 ASPEED Technology, Inc. ASPEED Graphics Family
>
> ASP device -> 1f:00.0 VGA compatible controller: ASPEED Technology, Inc. ASPEED Graphics Family
> PCI-Express to PCI/PCI-X Bridge -> 1e:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
>
> While setting up ASP device SID in IORT dirver:
> iort_iommu_configure() -> pci_for_each_dma_alias()
> we need to walk up and iterate over each device which alias transaction from
> downstream devices.
>
> AST device (1f:00.0) gets BDF=0x1f00 and corresponding SID=0x1f00 from IORT.
> Bridge (1e:00.0) is the first alias. Following PCI Express to PCI/PCI-X Bridge
> spec: PCIe-to-PCI/X bridges alias transactions from downstream devices using
> the subordinate bus number. For bridge (1e:00.0), the subordinate is equal
> to 0x1f. This gives BDF=0x1f00 and SID=1f00 which is the same as downstream
> device. So it is possible to have two identical SIDs. The question is what we
> should do about such case. Presented patch prevents from registering the same
> ID so that SMMUv3 is not complaining later on.
Ooh, subtle :( There is logic in arm_smmu_attach_device() to tolerate
grouped devices aliasing to the same ID, but I guess I overlooked the
distinction of a device sharing an alias ID with itself. I'm not sure
I really like trying to work around this in generic code, since
fwspec->ids is essentially opaque data in a driver-specific format - in
theory a driver is free to encode a single logical ID into multiple
fwspec elements (I think I did that in an early draft of SMMUv2 SMR
support), at which point this approach might corrupt things massively.
Does the (untested) diff below suffice?
Robin.
----->8-----diff --git a/drivers/iommu/arm-smmu-v3.c
b/drivers/iommu/arm-smmu-v3.c
index f122071688fd..d8a730d83401 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -1731,7 +1731,7 @@ static __le64 *arm_smmu_get_step_for_sid(struct
arm_smmu_device *smmu, u32 sid)
static void arm_smmu_install_ste_for_dev(struct iommu_fwspec *fwspec)
{
- int i;
+ int i, j;
struct arm_smmu_master_data *master = fwspec->iommu_priv;
struct arm_smmu_device *smmu = master->smmu;
@@ -1739,6 +1739,13 @@ static void arm_smmu_install_ste_for_dev(struct
iommu_fwspec *fwspec)
u32 sid = fwspec->ids[i];
__le64 *step = arm_smmu_get_step_for_sid(smmu, sid);
+ /* Bridged PCI devices may end up with duplicated IDs */
+ for (j = 0; j < i; j++)
+ if (fwspec->ids[j] == sid)
+ break;
+ if (j < i)
+ continue;
+
arm_smmu_write_strtab_ent(smmu, sid, step, &master->ste);
}
}
^ permalink raw reply related
* [PATCH 1/4] pci: dwc: pci-dra7xx: Enable errata i870 for both EP and RC mode
From: Lorenzo Pieralisi @ 2017-12-19 16:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201061311.16691-2-vigneshr@ti.com>
On Fri, Dec 01, 2017 at 11:43:08AM +0530, Vignesh R wrote:
> Errata i870 is applicable in both EP and RC mode. Therefore rename
> function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata
> workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a
> common place. So, that errata workaround is applied for both modes of
> operation.
>
> Reported-by: Chris Welch <Chris.Welch@viavisolutions.com>
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
> drivers/pci/dwc/pci-dra7xx.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
I need Kishon's ACK to apply it, thanks.
Lorenzo
> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
> index e77a4ceed74c..53f721d1cc40 100644
> --- a/drivers/pci/dwc/pci-dra7xx.c
> +++ b/drivers/pci/dwc/pci-dra7xx.c
> @@ -546,7 +546,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
> };
>
> /*
> - * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
> + * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
> * @dra7xx: the dra7xx device where the workaround should be applied
> *
> * Access to the PCIe slave port that are not 32-bit aligned will result
> @@ -556,7 +556,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
> *
> * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
> */
> -static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
> +static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
> {
> int ret;
> struct device_node *np = dev->of_node;
> @@ -703,6 +703,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
> if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
> dra7xx->link_gen = 2;
>
> + ret = dra7xx_pcie_unaligned_memaccess(dev);
> + if (ret)
> + goto err_gpio;
> +
> switch (mode) {
> case DW_PCIE_RC_TYPE:
> dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
> @@ -715,10 +719,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
> dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
> DEVICE_TYPE_EP);
>
> - ret = dra7xx_pcie_ep_unaligned_memaccess(dev);
> - if (ret)
> - goto err_gpio;
> -
> ret = dra7xx_add_pcie_ep(dra7xx, pdev);
> if (ret < 0)
> goto err_gpio;
> --
> 2.15.0
>
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