* [PATCH v5 0/4] ARM: ep93xx: ts72xx: Add support for BK3 board
From: Arnd Bergmann @ 2017-12-20 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219223612.1a67ba5b@jawa>
On Tue, Dec 19, 2017 at 10:36 PM, Lukasz Majewski <lukma@denx.de> wrote:
> Hi Arnd,
>
>> Hi!
>>
>> On Mon Dec 18 12:55:40 2017 Arnd Bergmann <arnd@arndb.de> wrote:
>> > > GCC 7.2 is working
>> >
>> > Ah wait, this is still for ep93xx, which is always at least armv4t,
>> > right? So it won't have a problem with the armv4 deprecation
>> > anyway, even
>>
>> Correct.
>
> Maybe a bit off topic :-)
>
> Are there any more comments regarding this patch series? Are those
> patches eligible for applying them to -next?
Alexander already sent a pull request, I just haven't pulled them. If there
are any other comments or additional patches, they should be done
on top of the first pull request, unless there is a major regression in
the original pull (which is unlikely).
Arnd
^ permalink raw reply
* [PATCH 42/45] ARM: dts: at91: vinco: use TCB2 as timers
From: Gregory CLEMENT @ 2017-12-20 8:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219213209.13823-43-alexandre.belloni@free-electrons.com>
Hi Alexandre,
On mar., d?c. 19 2017, Alexandre Belloni <alexandre.belloni@free-electrons.com> wrote:
> As TCB2 doesn't have any output pins, use it for timers
>
> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thanks,
Gregory
> ---
> arch/arm/boot/dts/at91-vinco.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts
> index 9f6005708ea8..1be9889a2b3a 100644
> --- a/arch/arm/boot/dts/at91-vinco.dts
> +++ b/arch/arm/boot/dts/at91-vinco.dts
> @@ -151,6 +151,18 @@
> status = "okay";
> };
>
> + tcb2: timer at fc024000 {
> + timer at 0 {
> + compatible = "atmel,tcb-timer";
> + reg = <0>;
> + };
> +
> + timer at 1 {
> + compatible = "atmel,tcb-timer";
> + reg = <1>;
> + };
> + };
> +
> macb1: ethernet at fc028000 {
> phy-mode = "rmii";
> status = "okay";
> --
> 2.15.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 00/45] Migrate TCB bindings
From: Nicolas Ferre @ 2017-12-20 8:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219213209.13823-1-alexandre.belloni@free-electrons.com>
On 19/12/2017 at 22:31, Alexandre Belloni wrote:
> Hi,
>
> As the bindings were acked by Rob a while ago [1] and I think there is
> consensus on what they look like, I'm planning to apply that series for
> 4.16 so we get a smoother transition for the TCB driver rework.
>
> I've simply removed the PWM binding change that I will submit with the
> driver change itself.
> There is also a small fix in the at91sam9261ek patch.
>
> [1] https://patchwork.kernel.org/patch/9755341/
>
> Cc: Antoine Aubert <a.aubert@overkiz.com>
> Cc: devicetree at vger.kernel.org
> Cc: Douglas Gilbert <dgilbert@interlog.com>
> Cc: Fabio Porcedda <fabio.porcedda@gmail.com>
> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Cc: Joachim Eastwood <manabian@gmail.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Martin Reimann <martin.reimann@egnite.de>
> Cc: Peter Rosin <peda@axentia.se>
> Cc: Raashid Muhammed <raashidmuhammed@zilogic.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Rodolfo Giometti <giometti@linux.it>
> Cc: Sergio Tanzilli <tanzilli@acmesystems.it>
> Cc: Tim Schendekehl <tim.schendekehl@egnite.de>
>
> Alexandre Belloni (45):
> ARM: at91: Document new TCB bindings
> ARM: dts: at91: at91rm9200: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: at91rm9200ek: use TCB0 for timers
> ARM: dts: at91: mpa1600: use TCB0 as timers
> ARM: dts: at91: at91sam9260: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: at91sam9260ek: use TCB0 as timers
> ARM: dts: at91: sam9_l9260: use TCB0 as timers
> ARM: dts: at91: ethernut5: use TCB0 as timers
> ARM: dts: at91: foxg20: use TCB0 as timers
> ARM: dts: at91: animeo_ip: use TCB0 as timers
> ARM: dts: at91: kizbox: use TCB0 as timers
> ARM: dts: at91: at91sam9g20ek: use TCB0 as timers
> ARM: dts: at91: ge863-pro3: use TCB0 as timers
> ARM: dts: at91: at91sam9261: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: at91sam9261ek: use TCB0 as timers
> ARM: dts: at91: at91sam9263: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: at91sam9263ek: use TCB0 as timers
> ARM: dts: at91: calao: use TCB0 as timers
> ARM: dts: at91: at91sam9g45: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: at91sam9m10g45ek: use TCB0 as timers
> ARM: dts: at91: pm9g45: use TCB0 as timers
> ARM: dts: at91: at91sam9rl: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: at91sam9rlek: use TCB0 as timers
> ARM: dts: at91: at91sam9n12: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: at91sam9n12ek: use TCB0 as timers
> ARM: dts: at91: at91sam9x5: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: at91sam9x5cm: use TCB0 as timers
> ARM: dts: at91: acme/g25: use TCB0 as timers
> ARM: dts: at91: cosino: use TCB0 as timers
> ARM: dts: at91: kizboxmini: use TCB0 as timers
> ARM: dts: at91: sama5d3: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: sama5d3xek: use TCB0 as timers
> ARM: dts: at91: sama5d3 Xplained: use TCB0 as timers
> ARM: dts: at91: kizbox2: use TCB0 as timers
> ARM: dts: at91: sama5d3xek_cmp: use TCB0 as timers
> ARM: dts: at91: linea/tse850-3: use TCB0 as timers
> ARM: dts: at91: sama5d4: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: sama5d4: Add TCB2
> ARM: dts: at91: sama5d4ek: use TCB2 as timers
> ARM: dts: at91: sama5d4 Xplained: use TCB2 as timers
> ARM: dts: at91: ma5d4: use TCB2 as timers
> ARM: dts: at91: vinco: use TCB2 as timers
> ARM: dts: at91: sama5d2: TC blocks are also simple-mfd and syscon
> devices
> ARM: dts: at91: sama5d2 Xplained: use TCB0 as timers
> ARM: dts: at91: sama5d27_som1_ek: use TCB0 as timers
For the whole series:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Thanks, best regards,
Nicolas
> .../devicetree/bindings/arm/atmel-at91.txt | 32 -------------
> .../devicetree/bindings/mfd/atmel-tcb.txt | 56 ++++++++++++++++++++++
> arch/arm/boot/dts/animeo_ip.dts | 12 +++++
> arch/arm/boot/dts/at91-ariag25.dts | 12 +++++
> arch/arm/boot/dts/at91-ariettag25.dts | 12 +++++
> arch/arm/boot/dts/at91-cosino.dtsi | 12 +++++
> arch/arm/boot/dts/at91-foxg20.dts | 12 +++++
> arch/arm/boot/dts/at91-kizbox.dts | 12 +++++
> arch/arm/boot/dts/at91-kizbox2.dts | 12 +++++
> arch/arm/boot/dts/at91-kizboxmini.dts | 12 +++++
> arch/arm/boot/dts/at91-linea.dtsi | 12 +++++
> arch/arm/boot/dts/at91-qil_a9260.dts | 12 +++++
> arch/arm/boot/dts/at91-sam9_l9260.dts | 12 +++++
> arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 12 +++++
> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 12 +++++
> arch/arm/boot/dts/at91-sama5d3_xplained.dts | 12 +++++
> arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi | 12 +++++
> arch/arm/boot/dts/at91-sama5d4_xplained.dts | 12 +++++
> arch/arm/boot/dts/at91-sama5d4ek.dts | 12 +++++
> arch/arm/boot/dts/at91-vinco.dts | 12 +++++
> arch/arm/boot/dts/at91rm9200.dtsi | 8 +++-
> arch/arm/boot/dts/at91rm9200ek.dts | 12 +++++
> arch/arm/boot/dts/at91sam9260.dtsi | 8 +++-
> arch/arm/boot/dts/at91sam9260ek.dts | 12 +++++
> arch/arm/boot/dts/at91sam9261.dtsi | 4 +-
> arch/arm/boot/dts/at91sam9261ek.dts | 20 ++++++++
> arch/arm/boot/dts/at91sam9263.dtsi | 4 +-
> arch/arm/boot/dts/at91sam9263ek.dts | 12 +++++
> arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 12 +++++
> arch/arm/boot/dts/at91sam9g45.dtsi | 8 +++-
> arch/arm/boot/dts/at91sam9m10g45ek.dts | 12 +++++
> arch/arm/boot/dts/at91sam9n12.dtsi | 8 +++-
> arch/arm/boot/dts/at91sam9n12ek.dts | 12 +++++
> arch/arm/boot/dts/at91sam9rl.dtsi | 4 +-
> arch/arm/boot/dts/at91sam9rlek.dts | 12 +++++
> arch/arm/boot/dts/at91sam9x5.dtsi | 8 +++-
> arch/arm/boot/dts/at91sam9x5cm.dtsi | 12 +++++
> arch/arm/boot/dts/ethernut5.dts | 12 +++++
> arch/arm/boot/dts/ge863-pro3.dtsi | 12 +++++
> arch/arm/boot/dts/mpa1600.dts | 12 +++++
> arch/arm/boot/dts/pm9g45.dts | 12 +++++
> arch/arm/boot/dts/sama5d2.dtsi | 8 +++-
> arch/arm/boot/dts/sama5d3.dtsi | 4 +-
> arch/arm/boot/dts/sama5d3_tcb1.dtsi | 4 +-
> arch/arm/boot/dts/sama5d3xcm.dtsi | 12 +++++
> arch/arm/boot/dts/sama5d3xcm_cmp.dtsi | 12 +++++
> arch/arm/boot/dts/sama5d4.dtsi | 18 ++++++-
> arch/arm/boot/dts/tny_a9260_common.dtsi | 12 +++++
> arch/arm/boot/dts/tny_a9263.dts | 12 +++++
> arch/arm/boot/dts/usb_a9260_common.dtsi | 12 +++++
> arch/arm/boot/dts/usb_a9263.dts | 12 +++++
> 51 files changed, 575 insertions(+), 51 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mfd/atmel-tcb.txt
>
--
Nicolas Ferre
^ permalink raw reply
* [PATCH 3/3] [v6] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002
From: Stephen Boyd @ 2017-12-20 8:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d511f096-bad4-c7b3-d7d4-11b1fa3b1cce@codeaurora.org>
On 12/19, Timur Tabi wrote:
> Frankly, I thought I had everything resolved already, and it sounds
> like you want me to start over from scratch anyway.
>
Here's the patch. I get a hang when dumping debugfs, but at least
sysfs expose fails when trying to request blocked gpios. I need
to check if we need to say "yes" to pins that are above the gpio
max for pinctrl. I'll do that tomorrow.
---
drivers/gpio/gpiolib.c | 4 +-
drivers/pinctrl/qcom/pinctrl-msm.c | 98 ++++++++++++++++++++++++++++++++++++--
include/linux/gpio/driver.h | 3 ++
3 files changed, 99 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 8db2680bf872..5f118f044caa 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1475,8 +1475,8 @@ static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
gpiochip->irq_valid_mask = NULL;
}
-static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
- unsigned int offset)
+bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
+ unsigned int offset)
{
/* No mask means all valid */
if (likely(!gpiochip->irq_valid_mask))
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd92561..4c2ce1f7d449 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -105,6 +105,17 @@ static const struct pinctrl_ops msm_pinctrl_ops = {
.dt_free_map = pinctrl_utils_free_map,
};
+static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
+{
+ struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+ struct gpio_chip *chip = &pctrl->chip;
+
+ if (gpiochip_irqchip_irq_valid(chip, offset))
+ return 0;
+
+ return -EINVAL;
+}
+
static int msm_get_functions_count(struct pinctrl_dev *pctldev)
{
struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
@@ -166,6 +177,7 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
}
static const struct pinmux_ops msm_pinmux_ops = {
+ .request = msm_pinmux_request,
.get_functions_count = msm_get_functions_count,
.get_function_name = msm_get_function_name,
.get_function_groups = msm_get_function_groups,
@@ -493,6 +505,9 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
"pull up"
};
+ if (!gpiochip_irqchip_irq_valid(chip, offset))
+ return;
+
g = &pctrl->soc->groups[offset];
ctl_reg = readl(pctrl->regs + g->ctl_reg);
@@ -503,7 +518,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
seq_printf(s, " %dmA", msm_regval_to_drive(drive));
- seq_printf(s, " %s", pulls[pull]);
+ seq_printf(s, " %s\n", pulls[pull]);
}
static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,10 +526,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
unsigned gpio = chip->base;
unsigned i;
- for (i = 0; i < chip->ngpio; i++, gpio++) {
+ for (i = 0; i < chip->ngpio; i++, gpio++)
msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
- seq_puts(s, "\n");
- }
}
#else
@@ -795,6 +808,76 @@ static void msm_gpio_irq_handler(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
+static int msm_gpio_init_irq_valid_mask(struct gpio_chip *chip,
+ struct msm_pinctrl *pctrl)
+{
+ int ret;
+ unsigned int len, i;
+ unsigned int max_gpios = pctrl->soc->ngpios;
+ struct device_node *np = pctrl->dev->of_node;
+
+ /* The number of GPIOs in the ACPI tables */
+ ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0);
+ if (ret > 0 && ret < max_gpios) {
+ u16 *tmp;
+
+ len = ret;
+ tmp = kmalloc_array(len, sizeof(tmp[0]), GFP_KERNEL);
+ if (!tmp)
+ return -ENOMEM;
+
+ ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp,
+ len);
+ if (ret < 0) {
+ dev_err(pctrl->dev, "could not read list of GPIOs\n");
+ kfree(tmp);
+ return ret;
+ }
+
+ bitmap_zero(chip->irq_valid_mask, max_gpios);
+ for (i = 0; i < len; i++)
+ set_bit(tmp[i], chip->irq_valid_mask);
+
+ return 0;
+ }
+
+ /* If there's a DT ngpios-ranges property then add those ranges */
+ ret = of_property_count_u32_elems(np, "ngpios-ranges");
+ if (ret > 0 && ret % 2 == 0 && ret / 2 < max_gpios) {
+ u32 start;
+ u32 count;
+
+ len = ret / 2;
+ bitmap_zero(chip->irq_valid_mask, max_gpios);
+
+ for (i = 0; i < len; i++) {
+ of_property_read_u32_index(np, "ngpios-ranges",
+ i * 2, &start);
+ of_property_read_u32_index(np, "ngpios-ranges",
+ i * 2 + 1, &count);
+ bitmap_set(chip->irq_valid_mask, start, count);
+ }
+ }
+
+ return 0;
+}
+
+static bool msm_gpio_needs_irq_valid_mask(struct msm_pinctrl *pctrl)
+{
+ int ret;
+ struct device_node *np = pctrl->dev->of_node;
+
+ ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0);
+ if (ret > 0)
+ return true;
+
+ ret = of_property_count_u32_elems(np, "ngpios-ranges");
+ if (ret > 0 && ret % 2 == 0)
+ return true;
+
+ return false;
+}
+
static int msm_gpio_init(struct msm_pinctrl *pctrl)
{
struct gpio_chip *chip;
@@ -811,6 +894,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
chip->parent = pctrl->dev;
chip->owner = THIS_MODULE;
chip->of_node = pctrl->dev->of_node;
+ chip->irq_need_valid_mask = msm_gpio_needs_irq_valid_mask(pctrl);
ret = gpiochip_add_data(&pctrl->chip, pctrl);
if (ret) {
@@ -818,6 +902,12 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
return ret;
}
+ ret = msm_gpio_init_irq_valid_mask(chip, pctrl);
+ if (ret) {
+ dev_err(pctrl->dev, "Failed to setup irq valid bits\n");
+ return ret;
+ }
+
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
if (ret) {
dev_err(pctrl->dev, "Failed to add pin range\n");
diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
index af20369ec8e7..be977c1c7498 100644
--- a/include/linux/gpio/driver.h
+++ b/include/linux/gpio/driver.h
@@ -262,6 +262,9 @@ int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
bool nested,
struct lock_class_key *lock_key);
+bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
+ unsigned int offset);
+
#ifdef CONFIG_LOCKDEP
/*
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v3 00/19] ARM: dts: aspeed: updates and new machines
From: Arnd Bergmann @ 2017-12-20 8:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACPK8Xdf3__yuMEvD0NiZXihU-8F1R15aEwwJueHLZ6Jfs82oQ@mail.gmail.com>
On Wed, Dec 20, 2017 at 4:37 AM, Joel Stanley <joel@jms.id.au> wrote:
> On Wed, Dec 20, 2017 at 1:53 PM, Joel Stanley <joel@jms.id.au> wrote:
>> This series of device tree patches for the ASPEED BMC machines
>> moves all systems to use the soon to be merged clk driver, and
>> updates machines to use all of the drivers we have upstream.
>>
>> v3: Address review from Rob and Cedric
>> - Move aspeed-gpio.h usage out into the patches where use of the GPIO
>> is added
>> - Clarify that the aspeed-clock.h patch will be merged as part of
>> the device tree tree. This is to ensure we don't depend on the clk
>> tree for building.
>
> Arnd, Michael, Stephen; how do we resolve this? We need the
> dt-bindings header to be present for both the clk driver and the
> device tree to build.
>
> The clk driver is not (yet - soon I hope?) merged by Michael and
> Stephen. I am about to commit the device tree changes that will go
> through the ARM SoC tree.
There are several options:
- avoid the use of the header and redefine the binding to have a
clear mapping between hardware clock lines and the numeric
representation. This works better for some SoCs than others,
YMMV.
- Don't use the constants in the dts files for now, but use the
numbers directly, and update the dts files for the next merge window
- merge only one side for 4.16, either the driver or the dts files,
and follow up with the other one in 4.17
- make one shared git branch that contains only the headers
and base both the driver and the dts files on that branch so you
get a single shared commit ID.
I'm fine with any of the above, please pick whatever suits you best.
Arnd
^ permalink raw reply
* [PATCH] ARM: multi_v7_defconfig: Select PWM_RCAR as module
From: Simon Horman @ 2017-12-20 8:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513691837-16192-1-git-send-email-fabrizio.castro@bp.renesas.com>
On Tue, Dec 19, 2017 at 01:57:17PM +0000, Fabrizio Castro wrote:
> Enable PWM support for R-Car and friends by default.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Thanks, applied.
^ permalink raw reply
* [PATCH] soc: renesas: rcar-sysc: Mark rcar_sysc_matches[] __initconst
From: Simon Horman @ 2017-12-20 8:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698884-26663-1-git-send-email-geert+renesas@glider.be>
On Tue, Dec 19, 2017 at 04:54:44PM +0100, Geert Uytterhoeven wrote:
> rcar_sysc_matches[] is used only by rcar_sysc_pd_init(), which is
> __init. Hence mark rcar_sysc_matches[] __initconst.
>
> This frees another 1764 bytes (arm32/shmobile_defconfig) or 1000 bytes
> (arm64/renesas_defconfig) of memory after kernel init.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <simon.horman@netronome.com>
^ permalink raw reply
* [PATCH v3 1/5] ARM: shmobile: defconfig: Enable PWM
From: Simon Horman @ 2017-12-20 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513690500-12165-2-git-send-email-fabrizio.castro@bp.renesas.com>
On Tue, Dec 19, 2017 at 01:34:56PM +0000, Fabrizio Castro wrote:
> RZ/G1 and R-Car platforms have PWM timers. This patch enables PWM support
> by default.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Thanks, applied.
^ permalink raw reply
* [PATCH v3 3/5] ARM: dts: r8a7743: Add PWM SoC support
From: Simon Horman @ 2017-12-20 8:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513690500-12165-4-git-send-email-fabrizio.castro@bp.renesas.com>
On Tue, Dec 19, 2017 at 01:34:58PM +0000, Fabrizio Castro wrote:
> Add the definitions for pwm[0123456] to the SoC .dtsi.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v2->v3:
> * pwm[0123456] compatible definitions don't wrap anymore
Thanks, applied.
^ permalink raw reply
* [PATCH v3 5/5] ARM: dts: r8a7743: Add TPU support
From: Simon Horman @ 2017-12-20 8:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513690500-12165-6-git-send-email-fabrizio.castro@bp.renesas.com>
On Tue, Dec 19, 2017 at 01:35:00PM +0000, Fabrizio Castro wrote:
> Add TPU support to SoC DT.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v2->v3:
> * No change
Thanks, applied.
^ permalink raw reply
* [PATCH v5 0/4] ARM: ep93xx: ts72xx: Add support for BK3 board
From: Lukasz Majewski @ 2017-12-20 8:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a1W+jU79GriKLZ1SXoVLaxC+przqQUTyHH6zz8+9dw2jg@mail.gmail.com>
Hi Arnd,
> On Tue, Dec 19, 2017 at 10:36 PM, Lukasz Majewski <lukma@denx.de>
> wrote:
> > Hi Arnd,
> >
> >> Hi!
> >>
> >> On Mon Dec 18 12:55:40 2017 Arnd Bergmann <arnd@arndb.de> wrote:
> >> > > GCC 7.2 is working
> >> >
> >> > Ah wait, this is still for ep93xx, which is always at least
> >> > armv4t, right? So it won't have a problem with the armv4
> >> > deprecation anyway, even
> >>
> >> Correct.
> >
> > Maybe a bit off topic :-)
> >
> > Are there any more comments regarding this patch series? Are those
> > patches eligible for applying them to -next?
>
> Alexander already sent a pull request, I just haven't pulled them. If
> there are any other comments or additional patches, they should be
> done on top of the first pull request, unless there is a major
> regression in the original pull (which is unlikely).
Thanks for reply.
>
> Arnd
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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^ permalink raw reply
* [PATCH] ARM: dts: at91: sama5d2_ptc_ek: use TCB0 as timers
From: Nicolas Ferre @ 2017-12-20 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219213209.13823-1-alexandre.belloni@free-electrons.com>
Use tcb0 for timers as selected in sama5_defconfig.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
Hi Alex,
Adding the newly added sama5d2_ptc_ek to the series.
Not tested though.
Regards,
Nicolas
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index 186cb03e2672..e603a267bdf1 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -149,6 +149,18 @@
};
};
+ tcb0: timer at f800c000 {
+ timer0: timer at 0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer at 1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+ };
+
uart0: serial at f801c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
--
2.9.0
^ permalink raw reply related
* [PATCH v2 2/4] ARM: dts: r8a7745: Add PWM SoC support
From: Simon Horman @ 2017-12-20 9:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdUi953N1J+vfJWJo0GMKO4tBZV9HnX7haG0fvyNHfOvOA@mail.gmail.com>
On Tue, Dec 19, 2017 at 12:25:54PM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 7:06 PM, Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add the definitions for pwm[0123456] to the SoC .dtsi.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- a/arch/arm/boot/dts/r8a7745.dtsi
> > +++ b/arch/arm/boot/dts/r8a7745.dtsi
> > @@ -968,6 +968,83 @@
> > status = "disabled";
> > };
> >
> > + pwm0: pwm at e6e30000 {
> > + compatible = "renesas,pwm-r8a7745",
> > + "renesas,pwm-rcar";
>
> I think this can fit on one line.
No need. I have fixed this when applying the patch.
^ permalink raw reply
* [PATCH v2 4/4] ARM: dts: r8a7745: Add TPU support
From: Simon Horman @ 2017-12-20 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513620411-17478-5-git-send-email-fabrizio.castro@bp.renesas.com>
On Mon, Dec 18, 2017 at 06:06:51PM +0000, Fabrizio Castro wrote:
> Add TPU support to SoC DT.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>
> ---
> v1->v2:
> * No change
Thanks, applied.
^ permalink raw reply
* [PATCH v2 2/3] ARM: dts: r8a7743: Add CMT SoC specific support
From: Simon Horman @ 2017-12-20 9:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdWPufohN+g=gFwi2V6vsGvhO7kTh8kj9AKCkraGKWGZBg@mail.gmail.com>
On Tue, Dec 19, 2017 at 12:20:45PM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 6:39 PM, Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add CMT[01] support to SoC DT.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied.
^ permalink raw reply
* [PATCH] clk: samsung: s3c: Remove unneeded enumeration
From: Chanwoo Choi @ 2017-12-20 9:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1511749908-29777-1-git-send-email-cw00.choi@samsung.com>
Dear Sylwester,
Gently Ping.
Regards,
Chanwoo Choi
On 2017? 11? 27? 11:31, Chanwoo Choi wrote:
> This patch just removes the unneeded enumeration for PLL index.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> drivers/clk/samsung/clk-s3c2412.c | 11 ++---------
> drivers/clk/samsung/clk-s3c2443.c | 17 ++++-------------
> drivers/clk/samsung/clk-s3c64xx.c | 17 ++++++-----------
> 3 files changed, 12 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c
> index b8340a49921b..1555e407529e 100644
> --- a/drivers/clk/samsung/clk-s3c2412.c
> +++ b/drivers/clk/samsung/clk-s3c2412.c
> @@ -27,11 +27,6 @@
> #define CLKSRC 0x1c
> #define SWRST 0x30
>
> -/* list of PLLs to be registered */
> -enum s3c2412_plls {
> - mpll, upll,
> -};
> -
> static void __iomem *reg_base;
>
> #ifdef CONFIG_PM_SLEEP
> @@ -144,10 +139,8 @@ struct samsung_mux_clock s3c2412_muxes[] __initdata = {
> };
>
> static struct samsung_pll_clock s3c2412_plls[] __initdata = {
> - [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
> - LOCKTIME, MPLLCON, NULL),
> - [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk",
> - LOCKTIME, UPLLCON, NULL),
> + PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
> + PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
> };
>
> struct samsung_gate_clock s3c2412_gates[] __initdata = {
> diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
> index d94b85a42356..9580a6baf4d7 100644
> --- a/drivers/clk/samsung/clk-s3c2443.c
> +++ b/drivers/clk/samsung/clk-s3c2443.c
> @@ -41,11 +41,6 @@ enum supported_socs {
> S3C2450,
> };
>
> -/* list of PLLs to be registered */
> -enum s3c2443_plls {
> - mpll, epll,
> -};
> -
> static void __iomem *reg_base;
>
> #ifdef CONFIG_PM_SLEEP
> @@ -225,10 +220,8 @@ struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
> /* S3C2416 specific clocks */
>
> static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
> - [mpll] = PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref",
> - LOCKCON0, MPLLCON, NULL),
> - [epll] = PLL(pll_6553, EPLL, "epll", "epllref",
> - LOCKCON1, EPLLCON, NULL),
> + PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
> + PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
> };
>
> PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
> @@ -279,10 +272,8 @@ struct samsung_clock_alias s3c2416_aliases[] __initdata = {
> /* S3C2443 specific clocks */
>
> static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
> - [mpll] = PLL(pll_3000, MPLL, "mpll", "mpllref",
> - LOCKCON0, MPLLCON, NULL),
> - [epll] = PLL(pll_2126, EPLL, "epll", "epllref",
> - LOCKCON1, EPLLCON, NULL),
> + PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
> + PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
> };
>
> static struct clk_div_table armdiv_s3c2443_d[] = {
> diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
> index 7306867a0ab8..6db01cf5ab83 100644
> --- a/drivers/clk/samsung/clk-s3c64xx.c
> +++ b/drivers/clk/samsung/clk-s3c64xx.c
> @@ -56,11 +56,6 @@
> #define GATE_ON(_id, cname, pname, o, b) \
> GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
>
> -/* list of PLLs to be registered */
> -enum s3c64xx_plls {
> - apll, mpll, epll,
> -};
> -
> static void __iomem *reg_base;
> static bool is_s3c6400;
>
> @@ -364,12 +359,12 @@ static void __init s3c64xx_clk_sleep_init(void) {}
>
> /* List of PLL clocks. */
> static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
> - [apll] = PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
> - APLL_LOCK, APLL_CON, NULL),
> - [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
> - MPLL_LOCK, MPLL_CON, NULL),
> - [epll] = PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
> - EPLL_LOCK, EPLL_CON0, NULL),
> + PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
> + APLL_LOCK, APLL_CON, NULL),
> + PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
> + MPLL_LOCK, MPLL_CON, NULL),
> + PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
> + EPLL_LOCK, EPLL_CON0, NULL),
> };
>
> /* Aliases for common s3c64xx clocks. */
>
^ permalink raw reply
* [PATCH] irqchip/gic-v3-its: Flush GICR caching for a cross node collection move of an irq
From: Ganapatrao Kulkarni @ 2017-12-20 9:15 UTC (permalink / raw)
To: linux-arm-kernel
When an interrupt is moved, it is possible that an implementation that
supports caching might still have cached data for a previous
(no longer valid) mapping of the interrupt. In particular, in a distributed
GIC implementation like multi-socket SoC platfroms. Hence it is necessary
to flush cached entries after cross node collection migration.
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
drivers/irqchip/irq-gic-v3-its.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 4039e64..ea849a1 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1119,6 +1119,12 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
if (cpu != its_dev->event_map.col_map[id]) {
target_col = &its_dev->its->collections[cpu];
its_send_movi(its_dev, target_col, id);
+ /* Issue INV for cross node collection move on
+ * multi socket systems.
+ */
+ if (cpu_to_node(cpu) !=
+ cpu_to_node(its_dev->event_map.col_map[id]))
+ its_send_inv(its_dev, id);
its_dev->event_map.col_map[id] = cpu;
irq_data_update_effective_affinity(d, cpumask_of(cpu));
}
--
2.9.4
^ permalink raw reply related
* [PATCH V2 9/9] ARM: dts: stm32: add initial support of stm32mp157c eval board
From: Alexandre Torgue @ 2017-12-20 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZaEjdGB2k6HdPt1_E0jRXEimEUxT9NmMwMw7OiyeqGLA@mail.gmail.com>
Hi Linus
On 12/20/2017 08:44 AM, Linus Walleij wrote:
> On Mon, Dec 18, 2017 at 4:17 PM, Ludovic Barre <ludovic.Barre@st.com> wrote:
>
>> From: Ludovic Barre <ludovic.barre@st.com>
>>
>> Add support of stm32mp157c evaluation board (part number: STM32MP157C-EV1)
>> split in 2 elements:
>> -Daughter board (part number: STM32MP157C-ED1)
>> which includes CPU, memory and power supply
>> -Mother board (part number: STM32MP157C-EM1)
>> which includes external peripherals (like display, camera,...)
>> and extension connectors.
>>
>> The daughter board can run alone, this is why the device tree files
>> are split in two layers, for the complete evaluation board (ev1)
>> and for the daughter board alone (ed1).
>>
>> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
> (...)
>> diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
>
> Evaluation boards are important because they set a pattern that customers
> will use.
>
> Please consider to include nodes for all GPIO blocks used in this
> evaluation board, and add:
>
> gpio-line-names = "foo", "bar" ...;
>
> See for example
> arch/arm/boot/dts/bcm2835-rpi-a.dts
> arch/arm/boot/dts/ste-snowball.dts
>
> It's good to have because probably you guys have proper schematics and
> know rail names of the stuff connected to those GPIO lines and so on,
> so you can give the lines proper names.
It looks like useful for pins used as gpio line. Are you saying that we
also have to describe pins used as Alternate Function ? Currently for
stm32 MCU we add (for each pins in a group) a comment in
stm32xxx-pinctrl.dtsi file to describe the pinmux (to help developers).
On driver side for each stm32 pinctrl driver (ex:
drivers/pinctrl/stm32/pinctrl-stm32f429.c) we add for each possible
muxing a name:
STM32_PIN(
PINCTRL_PIN(0, "PA0"),
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
To be honest, currently there is a an issue to printout the name :) but
I have a patch to send for that.
regards
Alex
>
> It will be helpful for people using the reference design, especially with the
> new character device, and also sets a pattern for people doing devices
> based on the reference design and we really want to do that.
>
> Yours,
> Linus Walleij
>
^ permalink raw reply
* [PATCH v2 3/3] ARM: dts: r8a7745: Add CMT SoC specific support
From: Simon Horman @ 2017-12-20 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdV-sM833JqN-UD8sBYc-bVS-3zWanaQTL-OUgpvKh_uXA@mail.gmail.com>
On Tue, Dec 19, 2017 at 12:21:12PM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 6:39 PM, Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add CMT[01] support to SoC DT.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied.
^ permalink raw reply
* [PATCH] irqchip/gic-v3-its: Flush GICR caching for a cross node collection move of an irq
From: Marc Zyngier @ 2017-12-20 9:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220091544.4467-1-ganapatrao.kulkarni@cavium.com>
On 20/12/17 09:15, Ganapatrao Kulkarni wrote:
> When an interrupt is moved, it is possible that an implementation that
> supports caching might still have cached data for a previous
> (no longer valid) mapping of the interrupt. In particular, in a distributed
> GIC implementation like multi-socket SoC platfroms. Hence it is necessary
> to flush cached entries after cross node collection migration.
>
> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 4039e64..ea849a1 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1119,6 +1119,12 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
> if (cpu != its_dev->event_map.col_map[id]) {
> target_col = &its_dev->its->collections[cpu];
> its_send_movi(its_dev, target_col, id);
> + /* Issue INV for cross node collection move on
> + * multi socket systems.
> + */
> + if (cpu_to_node(cpu) !=
> + cpu_to_node(its_dev->event_map.col_map[id]))
> + its_send_inv(its_dev, id);
> its_dev->event_map.col_map[id] = cpu;
> irq_data_update_effective_affinity(d, cpumask_of(cpu));
> }
>
The MOVI command doesn't have any such requirement (it only mandates
synchronization), and doesn't say anything about distributed vs monolithic.
What am I missing?
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH 1/2] ARM: dts: r8a7745: sort root sub-nodes alphabetically
From: Simon Horman @ 2017-12-20 9:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdWunJqU2b4e6XDc8MwnDc6WzxJPJumREM=X=MPSMN3e6A@mail.gmail.com>
On Tue, Dec 19, 2017 at 09:44:38AM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 10:50 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Sort root sub-nodes alphabetically for allow for easier maintenance
>
> to allow for
>
> > of this file.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied with the changelog fix.
^ permalink raw reply
* [PATCH 2/2] ARM: dts: r8a7745: move timer node out of bus
From: Simon Horman @ 2017-12-20 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdUELsg=qPrho-SmekY_d24q9waUwGS90HFEKQsSV1w7=w@mail.gmail.com>
On Tue, Dec 19, 2017 at 09:45:05AM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 10:50 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > The timer node does not have any register properties and thus shouldn't be
> > placed on the bus.
> >
> > This problem is flagged by the compiler as follows:
> > $ make dtbs W=1
> > ...
> > arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > DTC arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb
> > arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied.
^ permalink raw reply
* [PATCH] irqchip/gic-v3-its: Flush GICR caching for a cross node collection move of an irq
From: Ganapatrao Kulkarni @ 2017-12-20 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a2754c68-0a6b-e23d-1ed7-693ce4f7f89c@arm.com>
Hi Marc,
On Wed, Dec 20, 2017 at 2:56 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On 20/12/17 09:15, Ganapatrao Kulkarni wrote:
>> When an interrupt is moved, it is possible that an implementation that
>> supports caching might still have cached data for a previous
>> (no longer valid) mapping of the interrupt. In particular, in a distributed
>> GIC implementation like multi-socket SoC platfroms. Hence it is necessary
>> to flush cached entries after cross node collection migration.
>>
>> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>> ---
>> drivers/irqchip/irq-gic-v3-its.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
>> index 4039e64..ea849a1 100644
>> --- a/drivers/irqchip/irq-gic-v3-its.c
>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>> @@ -1119,6 +1119,12 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
>> if (cpu != its_dev->event_map.col_map[id]) {
>> target_col = &its_dev->its->collections[cpu];
>> its_send_movi(its_dev, target_col, id);
>> + /* Issue INV for cross node collection move on
>> + * multi socket systems.
>> + */
>> + if (cpu_to_node(cpu) !=
>> + cpu_to_node(its_dev->event_map.col_map[id]))
>> + its_send_inv(its_dev, id);
>> its_dev->event_map.col_map[id] = cpu;
>> irq_data_update_effective_affinity(d, cpumask_of(cpu));
>> }
>>
>
> The MOVI command doesn't have any such requirement (it only mandates
> synchronization), and doesn't say anything about distributed vs monolithic.
GIC-v3 spec do mention to issue ITS INV command or a write to GICR_INVLPIR.
pasting below snippet of MOVI command description.
"When an interrupt is moved to a collection, it is possible that an
implementation that supports speculative caching
might still have cached data for a previous (no longer valid) mapping
of the interrupt. Hence, implementations
must take care to invalidate any data associated with an interrupt
when it is moved. In particular, in a distributed
implementation, the ITS must write to the appropriate GICR_* register
to perform the invalidation in the redistributor."
>
> What am I missing?
>
> M.
> --
> Jazz is not dead. It just smells funny...
thanks
Ganapat
^ permalink raw reply
* [PATCH 1/2] ARM: dts: r8a7792: sort root sub-nodes alphabetically
From: Simon Horman @ 2017-12-20 9:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <14c60234-3755-3b06-64fc-e3943d8b5293@cogentembedded.com>
On Tue, Dec 19, 2017 at 12:27:48PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 12/19/2017 12:32 AM, Simon Horman wrote:
>
> > Sort root sub-nodes alphabetically for allow for easier maintenance
>
> s/for/to/?
>
> > of this file.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> > arch/arm/boot/dts/r8a7792.dtsi | 48 +++++++++++++++++++++---------------------
> > 1 file changed, 24 insertions(+), 24 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
> > index ac05fdb91798..d31258958c36 100644
> > --- a/arch/arm/boot/dts/r8a7792.dtsi
> > +++ b/arch/arm/boot/dts/r8a7792.dtsi
> > @@ -36,6 +36,22 @@
> > vin5 = &vin5;
> > };
> > + /* External root clock */
> > + extal_clk: extal {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board. */
> > + clock-frequency = <0>;
> > + };
> > +
> > + /* External CAN clock */
> > + can_clk: can {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board. */
> > + clock-frequency = <0>;
> > + };
> > +
>
> C predates E in my alphabet. :-)
Thanks, I have applied the following:
From: Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH] ARM: dts: r8a7792: sort root sub-nodes alphabetically
Sort root sub-nodes alphabetically to allow for easier maintenance
of this file.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7792.dtsi | 48 +++++++++++++++++++++---------------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 7b394273031e..b0013e5fcf47 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -36,6 +36,14 @@
vin5 = &vin5;
};
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -69,6 +77,22 @@
};
};
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -832,28 +856,4 @@
#power-domain-cells = <0>;
};
};
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
};
--
2.11.0
^ permalink raw reply related
* [-next PATCH 0/4] sysfs and DEVICE_ATTR_<foo>
From: Felipe Balbi @ 2017-12-20 9:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513706701.git.joe@perches.com>
Hi,
Joe Perches <joe@perches.com> writes:
> drivers/usb/phy/phy-tahvo.c | 2 +-
Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
--
balbi
^ permalink raw reply
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