* [kernel-hardening] [PATCH] arm: Always use REFCOUNT_FULL
From: Jinbum Park @ 2018-01-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
arm prefers to use REFCOUNT_FULL by default.
This enables it for arm.
Signed-off-by: Jinbum Park <jinb.park7@gmail.com>
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3d349b4..ec80270 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -100,6 +100,7 @@ config ARM
select OLD_SIGACTION
select OLD_SIGSUSPEND3
select PERF_USE_VMALLOC
+ select REFCOUNT_FULL
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
# Above selects are sorted alphabetically; please add new ones
--
1.9.1
^ permalink raw reply related
* [PATCH V4 08/26] drm/gma500: deprecate pci_get_bus_and_slot()
From: Sinan Kaya @ 2018-01-04 12:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513661883-28662-9-git-send-email-okaya@codeaurora.org>
On 12/19/2017 12:37 AM, Sinan Kaya wrote:
> pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as
> where a PCI device is present. This restricts the device drivers to be
> reused for other domain numbers.
>
> Getting ready to remove pci_get_bus_and_slot() function in favor of
> pci_get_domain_bus_and_slot().
>
> Add domain parameter to CDV_MSG_READ32, CDV_MSG_WRITE32, MRST_MSG_READ32,
> MRST_MSG_WRITE32, MDFLD_MSG_READ32, MDFLD_MSG_WRITE32.
>
> Extract pci_dev from struct drm_device and use pdev to find the domain
> number while calling pci_get_domain_bus_and_slot().
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> ---
> drivers/gpu/drm/gma500/cdv_device.c | 16 +++++++++-------
> drivers/gpu/drm/gma500/gma_device.c | 4 +++-
> drivers/gpu/drm/gma500/mid_bios.c | 12 +++++++++---
> drivers/gpu/drm/gma500/psb_drv.c | 10 ++++++++--
> drivers/gpu/drm/gma500/psb_drv.h | 18 ++++++++++--------
> 5 files changed, 39 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c
> index 8745971..3a3bf75 100644
> --- a/drivers/gpu/drm/gma500/cdv_device.c
> +++ b/drivers/gpu/drm/gma500/cdv_device.c
> @@ -185,21 +185,22 @@ static int cdv_backlight_init(struct drm_device *dev)
> * for this and the MID devices.
> */
>
> -static inline u32 CDV_MSG_READ32(uint port, uint offset)
> +static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset)
> {
> int mcr = (0x10<<24) | (port << 16) | (offset << 8);
> uint32_t ret_val = 0;
> - struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
> + struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
> pci_write_config_dword(pci_root, 0xD0, mcr);
> pci_read_config_dword(pci_root, 0xD4, &ret_val);
> pci_dev_put(pci_root);
> return ret_val;
> }
>
> -static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
> +static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset,
> + u32 value)
> {
> int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
> - struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
> + struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
> pci_write_config_dword(pci_root, 0xD4, value);
> pci_write_config_dword(pci_root, 0xD0, mcr);
> pci_dev_put(pci_root);
> @@ -216,11 +217,12 @@ static void cdv_init_pm(struct drm_device *dev)
> {
> struct drm_psb_private *dev_priv = dev->dev_private;
> u32 pwr_cnt;
> + int domain = pci_domain_nr(dev->pdev->bus);
> int i;
>
> - dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
> + dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
> PSB_APMBA) & 0xFFFF;
> - dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
> + dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
> PSB_OSPMBA) & 0xFFFF;
>
> /* Power status */
> @@ -251,7 +253,7 @@ static void cdv_errata(struct drm_device *dev)
> * Bonus Launch to work around the issue, by degrading
> * performance.
> */
> - CDV_MSG_WRITE32(3, 0x30, 0x08027108);
> + CDV_MSG_WRITE32(pci_domain_nr(dev->pdev->bus), 3, 0x30, 0x08027108);
> }
>
> /**
> diff --git a/drivers/gpu/drm/gma500/gma_device.c b/drivers/gpu/drm/gma500/gma_device.c
> index 4a295f9..a7fb6de 100644
> --- a/drivers/gpu/drm/gma500/gma_device.c
> +++ b/drivers/gpu/drm/gma500/gma_device.c
> @@ -19,7 +19,9 @@
> void gma_get_core_freq(struct drm_device *dev)
> {
> uint32_t clock;
> - struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
> + struct pci_dev *pci_root =
> + pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
> + 0, 0);
> struct drm_psb_private *dev_priv = dev->dev_private;
>
> /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
> diff --git a/drivers/gpu/drm/gma500/mid_bios.c b/drivers/gpu/drm/gma500/mid_bios.c
> index 1fa1633..7171b74 100644
> --- a/drivers/gpu/drm/gma500/mid_bios.c
> +++ b/drivers/gpu/drm/gma500/mid_bios.c
> @@ -32,7 +32,9 @@
> static void mid_get_fuse_settings(struct drm_device *dev)
> {
> struct drm_psb_private *dev_priv = dev->dev_private;
> - struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
> + struct pci_dev *pci_root =
> + pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
> + 0, 0);
> uint32_t fuse_value = 0;
> uint32_t fuse_value_tmp = 0;
>
> @@ -104,7 +106,9 @@ static void mid_get_fuse_settings(struct drm_device *dev)
> static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
> {
> uint32_t platform_rev_id = 0;
> - struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
> + int domain = pci_domain_nr(dev_priv->dev->pdev->bus);
> + struct pci_dev *pci_gfx_root =
> + pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
>
> if (pci_gfx_root == NULL) {
> WARN_ON(1);
> @@ -281,7 +285,9 @@ static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
> u32 addr;
> u8 __iomem *vbt_virtual;
> struct mid_vbt_header vbt_header;
> - struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
> + struct pci_dev *pci_gfx_root =
> + pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
> + 0, PCI_DEVFN(2, 0));
> int ret = -1;
>
> /* Get the address of the platform config vbt */
> diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c
> index 38d09d4..ac32ab5 100644
> --- a/drivers/gpu/drm/gma500/psb_drv.c
> +++ b/drivers/gpu/drm/gma500/psb_drv.c
> @@ -248,7 +248,11 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
> goto out_err;
>
> if (IS_MRST(dev)) {
> - dev_priv->aux_pdev = pci_get_bus_and_slot(0, PCI_DEVFN(3, 0));
> + int domain = pci_domain_nr(dev->pdev->bus);
> +
> + dev_priv->aux_pdev =
> + pci_get_domain_bus_and_slot(domain, 0,
> + PCI_DEVFN(3, 0));
>
> if (dev_priv->aux_pdev) {
> resource_start = pci_resource_start(dev_priv->aux_pdev,
> @@ -268,7 +272,9 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
> }
> dev_priv->gmbus_reg = dev_priv->aux_reg;
>
> - dev_priv->lpc_pdev = pci_get_bus_and_slot(0, PCI_DEVFN(31, 0));
> + dev_priv->lpc_pdev =
> + pci_get_domain_bus_and_slot(domain, 0,
> + PCI_DEVFN(31, 0));
> if (dev_priv->lpc_pdev) {
> pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA,
> &dev_priv->lpc_gpio_base);
> diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
> index 4918efc..e8300f5 100644
> --- a/drivers/gpu/drm/gma500/psb_drv.h
> +++ b/drivers/gpu/drm/gma500/psb_drv.h
> @@ -780,38 +780,40 @@ extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
> extern int drm_idle_check_interval;
>
> /* Utilities */
> -static inline u32 MRST_MSG_READ32(uint port, uint offset)
> +static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset)
> {
> int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
> uint32_t ret_val = 0;
> - struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
> + struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
> pci_write_config_dword(pci_root, 0xD0, mcr);
> pci_read_config_dword(pci_root, 0xD4, &ret_val);
> pci_dev_put(pci_root);
> return ret_val;
> }
> -static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
> +static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset,
> + u32 value)
> {
> int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
> - struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
> + struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
> pci_write_config_dword(pci_root, 0xD4, value);
> pci_write_config_dword(pci_root, 0xD0, mcr);
> pci_dev_put(pci_root);
> }
> -static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
> +static inline u32 MDFLD_MSG_READ32(int domain, uint port, uint offset)
> {
> int mcr = (0x10<<24) | (port << 16) | (offset << 8);
> uint32_t ret_val = 0;
> - struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
> + struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
> pci_write_config_dword(pci_root, 0xD0, mcr);
> pci_read_config_dword(pci_root, 0xD4, &ret_val);
> pci_dev_put(pci_root);
> return ret_val;
> }
> -static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
> +static inline void MDFLD_MSG_WRITE32(int domain, uint port, uint offset,
> + u32 value)
> {
> int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
> - struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
> + struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
> pci_write_config_dword(pci_root, 0xD4, value);
> pci_write_config_dword(pci_root, 0xD0, mcr);
> pci_dev_put(pci_root);
>
Any feedback here? I don't have any hardware to test the changes. I just did a compile test.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH V4 09/26] drm/nouveau: deprecate pci_get_bus_and_slot()
From: Sinan Kaya @ 2018-01-04 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513661883-28662-10-git-send-email-okaya@codeaurora.org>
On 12/19/2017 12:37 AM, Sinan Kaya wrote:
> pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as
> where a PCI device is present. This restricts the device drivers to be
> reused for other domain numbers.
>
> Getting ready to remove pci_get_bus_and_slot() function in favor of
> pci_get_domain_bus_and_slot().
>
> Replace pci_get_bus_and_slot() with pci_get_domain_bus_and_slot()
> and extract the domain number from
> 1. struct pci_dev
> 2. struct pci_dev through drm_device->pdev
> 3. struct pci_dev through fb->subdev->drm_device->pdev
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> ---
> drivers/gpu/drm/nouveau/dispnv04/arb.c | 4 +++-
> drivers/gpu/drm/nouveau/dispnv04/hw.c | 10 +++++++---
> drivers/gpu/drm/nouveau/nouveau_drm.c | 3 ++-
> drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c | 10 +++++++++-
> 4 files changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c b/drivers/gpu/drm/nouveau/dispnv04/arb.c
> index 90075b6..c79160c 100644
> --- a/drivers/gpu/drm/nouveau/dispnv04/arb.c
> +++ b/drivers/gpu/drm/nouveau/dispnv04/arb.c
> @@ -213,8 +213,10 @@ struct nv_sim_state {
> if ((dev->pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
> (dev->pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
> uint32_t type;
> + int domain = pci_domain_nr(dev->pdev->bus);
>
> - pci_read_config_dword(pci_get_bus_and_slot(0, 1), 0x7c, &type);
> + pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
> + 0x7c, &type);
>
> sim_data.memory_type = (type >> 12) & 1;
> sim_data.memory_width = 64;
> diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
> index b985990..0c9bdf0 100644
> --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
> +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
> @@ -216,12 +216,15 @@
> {
> struct nvkm_pll_vals pllvals;
> int ret;
> + int domain;
> +
> + domain = pci_domain_nr(dev->pdev->bus);
>
> if (plltype == PLL_MEMORY &&
> (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
> uint32_t mpllP;
> -
> - pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
> + pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
> + 0x6c, &mpllP);
> mpllP = (mpllP >> 8) & 0xf;
> if (!mpllP)
> mpllP = 4;
> @@ -232,7 +235,8 @@
> (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) {
> uint32_t clock;
>
> - pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
> + pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5),
> + 0x4c, &clock);
> return clock / 1000;
> }
>
> diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
> index 8d4a5be..33b6139 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_drm.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
> @@ -524,7 +524,8 @@ static int nouveau_drm_probe(struct pci_dev *pdev,
> }
>
> /* subfunction one is a hdmi audio device? */
> - drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
> + drm->hdmi_device = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
> + (unsigned int)pdev->bus->number,
> PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
>
> if (!drm->hdmi_device) {
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
> index 4c07d10..18241c6 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
> @@ -28,8 +28,16 @@
> {
> struct pci_dev *bridge;
> u32 mem, mib;
> + int domain = 0;
> + struct pci_dev *pdev = NULL;
>
> - bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
> + if (dev_is_pci(fb->subdev.device->dev))
> + pdev = to_pci_dev(fb->subdev.device->dev);
> +
> + if (pdev)
> + domain = pci_domain_nr(pdev->bus);
> +
> + bridge = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 1));
> if (!bridge) {
> nvkm_error(&fb->subdev, "no bridge device\n");
> return -ENODEV;
>
Any feedback here? I don't have any hardware to test the changes. I just did a compile test.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH V4] ARM: imx_v6_v7_defconfig: select the CONFIG_CPUFREQ_DT
From: Fabio Estevam @ 2018-01-04 12:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515095504-4570-1-git-send-email-Anson.Huang@nxp.com>
On Thu, Jan 4, 2018 at 5:51 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> Select CONFIG_CPUFREQ_DT by default to enable
> cpu-freq driver for i.MX7D.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH V4 11/26] iommu/amd: deprecate pci_get_bus_and_slot()
From: Sinan Kaya @ 2018-01-04 12:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513661883-28662-12-git-send-email-okaya@codeaurora.org>
On 12/19/2017 12:37 AM, Sinan Kaya wrote:
> pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as
> where a PCI device is present. This restricts the device drivers to be
> reused for other domain numbers.
>
> Getting ready to remove pci_get_bus_and_slot() function in favor of
> pci_get_domain_bus_and_slot().
>
> Hard-code the domain number as 0 for the AMD IOMMU driver.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> ---
> drivers/iommu/amd_iommu.c | 3 ++-
> drivers/iommu/amd_iommu_init.c | 9 +++++----
> drivers/iommu/amd_iommu_v2.c | 3 ++-
> 3 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
> index 7d5eb00..821547b 100644
> --- a/drivers/iommu/amd_iommu.c
> +++ b/drivers/iommu/amd_iommu.c
> @@ -527,7 +527,8 @@ static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
> struct iommu_dev_data *dev_data = NULL;
> struct pci_dev *pdev;
>
> - pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
> + pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
> + devid & 0xff);
> if (pdev)
> dev_data = get_dev_data(&pdev->dev);
>
> diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
> index 6fe2d03..4e4a615 100644
> --- a/drivers/iommu/amd_iommu_init.c
> +++ b/drivers/iommu/amd_iommu_init.c
> @@ -1697,8 +1697,8 @@ static int iommu_init_pci(struct amd_iommu *iommu)
> u32 range, misc, low, high;
> int ret;
>
> - iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
> - iommu->devid & 0xff);
> + iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
> + iommu->devid & 0xff);
> if (!iommu->dev)
> return -ENODEV;
>
> @@ -1764,8 +1764,9 @@ static int iommu_init_pci(struct amd_iommu *iommu)
> if (is_rd890_iommu(iommu->dev)) {
> int i, j;
>
> - iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
> - PCI_DEVFN(0, 0));
> + iommu->root_pdev =
> + pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
> + PCI_DEVFN(0, 0));
>
> /*
> * Some rd890 systems may not be fully reconfigured by the
> diff --git a/drivers/iommu/amd_iommu_v2.c b/drivers/iommu/amd_iommu_v2.c
> index 7d94e1d..8696382 100644
> --- a/drivers/iommu/amd_iommu_v2.c
> +++ b/drivers/iommu/amd_iommu_v2.c
> @@ -564,7 +564,8 @@ static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data)
> finish = (iommu_fault->tag >> 9) & 1;
>
> devid = iommu_fault->device_id;
> - pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
> + pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
> + devid & 0xff);
> if (!pdev)
> return -ENODEV;
> dev_data = get_dev_data(&pdev->dev);
>
Any comments from the IOMMU people?
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH V2] ARM: imx_v6_v7_defconfig: select the CONFIG_CPUFREQ_DT
From: Anson Huang @ 2018-01-04 12:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5DnSVKvteBtNB5RqXg3v0kV889w9eDOw=rjx90SiiPx1A@mail.gmail.com>
Best Regards!
Anson Huang
> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: 2018-01-04 7:37 PM
> To: Anson Huang <anson.huang@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Sascha Hauer
> <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>; Russell
> King - ARM Linux <linux@armlinux.org.uk>; linux-kernel <linux-
> kernel at vger.kernel.org>; moderated list:ARM/FREESCALE IMX / MXC ARM
> ARCHITECTURE <linux-arm-kernel@lists.infradead.org>
> Subject: Re: [PATCH V2] ARM: imx_v6_v7_defconfig: select the
> CONFIG_CPUFREQ_DT
>
> On Thu, Jan 4, 2018 at 4:39 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
>
> > diff --git a/arch/arm/configs/imx_v6_v7_defconfig
> > b/arch/arm/configs/imx_v6_v7_defconfig
> > index 29cd1ac..885db90 100644
> > --- a/arch/arm/configs/imx_v6_v7_defconfig
> > +++ b/arch/arm/configs/imx_v6_v7_defconfig
> > @@ -58,6 +58,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
> > CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> > CONFIG_CPU_FREQ_GOV_USERSPACE=y
> > CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
> > +CONFIG_CPUFREQ_DT=y
> > CONFIG_ARM_IMX6Q_CPUFREQ=y
> > CONFIG_CPU_IDLE=y
> > CONFIG_VFP=y
> > @@ -318,14 +319,6 @@ CONFIG_USB_CONFIGFS_F_MIDI=y
> > CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_UVC=y
> > CONFIG_USB_CONFIGFS_F_PRINTER=y -CONFIG_USB_ZERO=m -
> CONFIG_USB_AUDIO=m
> > -CONFIG_USB_ETH=m -CONFIG_USB_G_NCM=m -
> CONFIG_USB_GADGETFS=m
> > -CONFIG_USB_FUNCTIONFS=m -CONFIG_USB_MASS_STORAGE=m
> > -CONFIG_USB_G_SERIAL=m
>
> Not sure why these are getting removed automatically.
>
> > CONFIG_MMC=y
> > CONFIG_MMC_SDHCI=y
> > CONFIG_MMC_SDHCI_PLTFM=y
> > @@ -350,7 +343,6 @@ CONFIG_RTC_DRV_PCF8563=y
> CONFIG_RTC_DRV_M41T80=y
> > CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y
> > -CONFIG_RTC_DRV_MXC_V2=y
>
> This is the rtc driver for mx53.
>
> This driver will land in 4.16, so that's the reason it got removed automatically by
> savedefconfig.
>
> It would be safer if your patch could only add a single line:
> 'CONFIG_CPUFREQ_DT=y'.
Thanks Fabio, I send a V3 patch with the only change.
Anson.
^ permalink raw reply
* [RESEND PATCH v2 14/15] ASoC: qcom: apq8096: Add db820c machine driver
From: Mark Brown @ 2018-01-04 12:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f72f32dd-e248-47c3-23cc-eabe1b85d9ae@codeaurora.org>
On Wed, Jan 03, 2018 at 09:20:45AM -0800, Stephen Boyd wrote:
> On 12/14/2017 09:34 AM, srinivas.kandagatla at linaro.org wrote:
> > uThis patch adds support to DB820c machine driver.
> > + ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
> Why do we need to do this? Can you add some sort of comment in the code
> about why?
And why are we applying DMA restrictions in a machine driver?
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^ permalink raw reply
* Tegra baseline test results for v4.15-rc6
From: Jon Hunter @ 2018-01-04 11:51 UTC (permalink / raw)
To: linux-arm-kernel
Here are some basic Tegra test results for Linux v4.15-rc6.
Logs and other details at:
https://nvtb.github.io//linux/test_v4.15-rc6/20180102073103/
Test summary - 84% Success
--------------------------
Build: zImage:
Pass: ( 3/ 3): multi_v7_defconfig, tegra_defconfig,
tegra_defconfig%tegra-fw
Build: Image:
Pass: ( 3/ 3): defconfig, defconfig%jetson-tx2,
defconfig%jetson-tx1
Boot to userspace: defconfig:
Pass: ( 4/ 4): qemu-vexpress64, tegra132-norrin,
tegra210-p2371-0000, tegra210-smaug
Boot to userspace: defconfig%jetson-tx1:
Pass: ( 2/ 2): tegra210-p2371-0000, tegra210-p2371-2180
Boot to userspace: defconfig%jetson-tx2:
Pass: ( 1/ 1): tegra186-p2771-0000
Boot to userspace: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
PM: System suspend: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
vmlinux object size
(delta in bytes from test_v4.15-rc5 (464e1d5f23cca236b930ef068c328a64cab78fb1)):
text data bss total kernel
+3476 +1932 0 +5408 defconfig
+2748 +408 0 +3156 multi_v7_defconfig
+2368 +152 0 +2520 tegra_defconfig
Boot-time memory difference
(delta in bytes from test_v4.15-rc5 (464e1d5f23cca236b930ef068c328a64cab78fb1))
avail rsrvd high freed board kconfig dtb
. . . . qemu-vexpress64 defconfig __internal
. . . . tegra114-dalmore-a04 multi_v7_defconfig tegra114-dalmore
. . . . tegra114-dalmore-a04 tegra_defconfig tegra114-dalmore
. . . . tegra124-jetson-tk1 multi_v7_defconfig tegra124-jetson-tk1
. . . . tegra124-jetson-tk1 tegra_defconfig%tegr tegra124-jetson-tk1
. . . . tegra124-jetson-tk1 tegra_defconfig tegra124-jetson-tk1
. . . . tegra124-nyan-big multi_v7_defconfig tegra124-nyan-big
. . . . tegra124-nyan-big tegra_defconfig%tegr tegra124-nyan-big
. . . . tegra124-nyan-big tegra_defconfig tegra124-nyan-big
. . . . tegra132-norrin defconfig tegra132-norrin
. . . . tegra186-p2771-0000 defconfig%jetson-tx2 tegra186-p2771-0000
. . . . tegra20-trimslice multi_v7_defconfig tegra20-trimslice
. . . . tegra20-trimslice tegra_defconfig tegra20-trimslice
. . . . tegra210-p2371-0000 defconfig%jetson-tx1 tegra210-p2371-0000
. . . . tegra210-p2371-0000 defconfig tegra210-p2371-0000
. . . . tegra210-p2371-2180 defconfig%jetson-tx1 tegra210-p2371-2180
. . . . tegra210-smaug defconfig tegra210-smaug
. . . . tegra30-beaver multi_v7_defconfig tegra30-beaver
. . . . tegra30-beaver tegra_defconfig tegra30-beaver
--
nvpublic
^ permalink raw reply
* Tegra baseline test results for v4.15-rc5
From: Jon Hunter @ 2018-01-04 11:51 UTC (permalink / raw)
To: linux-arm-kernel
Here are some basic Tegra test results for Linux v4.15-rc5.
Logs and other details at:
https://nvtb.github.io//linux/test_v4.15-rc5/20171223210103/
Test summary - 84% Success
--------------------------
Build: zImage:
Pass: ( 3/ 3): multi_v7_defconfig, tegra_defconfig,
tegra_defconfig%tegra-fw
Build: Image:
Pass: ( 3/ 3): defconfig, defconfig%jetson-tx2,
defconfig%jetson-tx1
Boot to userspace: defconfig:
Pass: ( 4/ 4): qemu-vexpress64, tegra132-norrin,
tegra210-p2371-0000, tegra210-smaug
Boot to userspace: defconfig%jetson-tx1:
Pass: ( 2/ 2): tegra210-p2371-0000, tegra210-p2371-2180
Boot to userspace: defconfig%jetson-tx2:
Pass: ( 1/ 1): tegra186-p2771-0000
Boot to userspace: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
PM: System suspend: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
vmlinux object size
(delta in bytes from test_v4.15-rc4 (1291a0d5049dbc06baaaf66a9ff3f53db493b19b)):
text data bss total kernel
+48 -48 0 0 defconfig
+1232 0 0 +1232 multi_v7_defconfig
+1140 +64 0 +1204 tegra_defconfig
Boot-time memory difference
(delta in bytes from test_v4.15-rc4 (1291a0d5049dbc06baaaf66a9ff3f53db493b19b))
avail rsrvd high freed board kconfig dtb
. . . . qemu-vexpress64 defconfig __internal
. . . . tegra114-dalmore-a04 multi_v7_defconfig tegra114-dalmore
. . . . tegra114-dalmore-a04 tegra_defconfig tegra114-dalmore
. . . . tegra124-jetson-tk1 multi_v7_defconfig tegra124-jetson-tk1
. . . . tegra124-jetson-tk1 tegra_defconfig%tegr tegra124-jetson-tk1
. . . . tegra124-jetson-tk1 tegra_defconfig tegra124-jetson-tk1
. . . . tegra124-nyan-big multi_v7_defconfig tegra124-nyan-big
. . . . tegra124-nyan-big tegra_defconfig%tegr tegra124-nyan-big
. . . . tegra124-nyan-big tegra_defconfig tegra124-nyan-big
. . . . tegra132-norrin defconfig tegra132-norrin
. . . . tegra186-p2771-0000 defconfig%jetson-tx2 tegra186-p2771-0000
. . . . tegra20-trimslice multi_v7_defconfig tegra20-trimslice
. . . . tegra20-trimslice tegra_defconfig tegra20-trimslice
. . . . tegra210-p2371-0000 defconfig%jetson-tx1 tegra210-p2371-0000
. . . . tegra210-p2371-0000 defconfig tegra210-p2371-0000
. . . . tegra210-p2371-2180 defconfig%jetson-tx1 tegra210-p2371-2180
. . . . tegra210-smaug defconfig tegra210-smaug
. . . . tegra30-beaver multi_v7_defconfig tegra30-beaver
. . . . tegra30-beaver tegra_defconfig tegra30-beaver
--
nvpublic
^ permalink raw reply
* Tegra baseline test results for v4.15-rc4
From: Jon Hunter @ 2018-01-04 11:51 UTC (permalink / raw)
To: linux-arm-kernel
Here are some basic Tegra test results for Linux v4.15-rc4.
Logs and other details at:
https://nvtb.github.io//linux/test_v4.15-rc4/20171217193104/
Test summary - 84% Success
--------------------------
Build: zImage:
Pass: ( 3/ 3): multi_v7_defconfig, tegra_defconfig,
tegra_defconfig%tegra-fw
Build: Image:
Pass: ( 3/ 3): defconfig, defconfig%jetson-tx2,
defconfig%jetson-tx1
Boot to userspace: defconfig:
Pass: ( 4/ 4): qemu-vexpress64, tegra132-norrin,
tegra210-p2371-0000, tegra210-smaug
Boot to userspace: defconfig%jetson-tx1:
Pass: ( 2/ 2): tegra210-p2371-0000, tegra210-p2371-2180
Boot to userspace: defconfig%jetson-tx2:
Pass: ( 1/ 1): tegra186-p2771-0000
Boot to userspace: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
PM: System suspend: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
vmlinux object size
(delta in bytes from test_v4.15-rc3 (50c4c4e268a2d7a3e58ebb698ac74da0de40ae36)):
text data bss total kernel
-571 +732 0 +161 defconfig
+1189 +12 0 +1201 multi_v7_defconfig
+1069 +76 0 +1145 tegra_defconfig
Boot-time memory difference
(delta in bytes from test_v4.15-rc3 (50c4c4e268a2d7a3e58ebb698ac74da0de40ae36))
avail rsrvd high freed board kconfig dtb
. . . . qemu-vexpress64 defconfig __internal
. . . . tegra114-dalmore-a04 multi_v7_defconfig tegra114-dalmore
. . . . tegra114-dalmore-a04 tegra_defconfig tegra114-dalmore
. . . . tegra124-jetson-tk1 multi_v7_defconfig tegra124-jetson-tk1
. . . . tegra124-jetson-tk1 tegra_defconfig%tegr tegra124-jetson-tk1
. . . . tegra124-jetson-tk1 tegra_defconfig tegra124-jetson-tk1
. . . . tegra124-nyan-big multi_v7_defconfig tegra124-nyan-big
. . . . tegra124-nyan-big tegra_defconfig%tegr tegra124-nyan-big
. . . . tegra124-nyan-big tegra_defconfig tegra124-nyan-big
. . . . tegra132-norrin defconfig tegra132-norrin
. . . . tegra186-p2771-0000 defconfig%jetson-tx2 tegra186-p2771-0000
. . . . tegra20-trimslice multi_v7_defconfig tegra20-trimslice
. . . . tegra20-trimslice tegra_defconfig tegra20-trimslice
-64k 64k . . tegra210-p2371-0000 defconfig%jetson-tx1 tegra210-p2371-0000
. . . . tegra210-p2371-0000 defconfig tegra210-p2371-0000
. . . . tegra210-p2371-2180 defconfig%jetson-tx1 tegra210-p2371-2180
. . . . tegra210-smaug defconfig tegra210-smaug
. . . . tegra30-beaver multi_v7_defconfig tegra30-beaver
. . . . tegra30-beaver tegra_defconfig tegra30-beaver
--
nvpublic
^ permalink raw reply
* [PATCH v5 4/9] drivers: base cacheinfo: Add support for ACPI based firmware tables
From: Sudeep Holla @ 2018-01-04 11:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3c3bf8a4-a13a-ce71-4bd2-71dd11b45521@arm.com>
On 03/01/18 14:21, Sudeep Holla wrote:
> On 12/12/17 23:37, Jeremy Linton wrote:
>> On 12/12/2017 05:02 PM, Rafael J. Wysocki wrote:
>
> [...]
>
>>>
>>> So call this field "token" or similar.? Don't call it "of_node" and
>>> don't introduce another "firmware_node" thing in addition to that.
>>> That just is a mess, sorry.
>
> I completely agree. Both me and Lorenzo pointed that out in previous
> revisions and fair enough you have a valid concern it's use with PPTT.
>
>>
>> I sort of agree, I think I can just change the whole of_node to a
>> generic 'void *firmware_unique' which works fine for the PPTT code, it
>> should also work for the DT code in cache_leaves_are_shared().
>>
>
> Should be fine.
>
Just to let you know, I don't have much to add. I will wait for the
patches that replace of_node with firmware cookie or something similar.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH] [v2] s3mci: mark debug_regs[] as static
From: Ulf Hansson @ 2018-01-04 11:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180103224939.4104207-1-arnd@arndb.de>
On 3 January 2018 at 23:49, Arnd Bergmann <arnd@arndb.de> wrote:
> The global array clashes with a newly added symbol of the same name:
>
> drivers/staging/ccree/cc_debugfs.o:(.data+0x0): multiple definition of `debug_regs'
> drivers/mmc/host/s3cmci.o:(.data+0x70): first defined here
>
> We should fix both, this one addresses the s3cmci driver by removing
> the symbol from the global namespace. While at it, this separates
> the declaration from the type definition and makes the variable const.
>
> Fixes: 9bdd203b4dc8 ("s3cmci: add debugfs support for examining driver and hardware state")
> Fixes: b3ec9a6736f2 ("staging: ccree: staging: ccree: replace sysfs by debugfs interface")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Thanks, applied for fixes!
Kind regards
Uffe
> ---
> drivers/mmc/host/s3cmci.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
> index 36daee1e6588..f77493604312 100644
> --- a/drivers/mmc/host/s3cmci.c
> +++ b/drivers/mmc/host/s3cmci.c
> @@ -1424,7 +1424,9 @@ static const struct file_operations s3cmci_fops_state = {
> struct s3cmci_reg {
> unsigned short addr;
> unsigned char *name;
> -} debug_regs[] = {
> +};
> +
> +static const struct s3cmci_reg debug_regs[] = {
> DBG_REG(CON),
> DBG_REG(PRE),
> DBG_REG(CMDARG),
> @@ -1446,7 +1448,7 @@ struct s3cmci_reg {
> static int s3cmci_regs_show(struct seq_file *seq, void *v)
> {
> struct s3cmci_host *host = seq->private;
> - struct s3cmci_reg *rptr = debug_regs;
> + const struct s3cmci_reg *rptr = debug_regs;
>
> for (; rptr->name; rptr++)
> seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
> --
> 2.9.0
>
^ permalink raw reply
* [PATCH] arm64: asid: Do not replace active_asids if already 0
From: Will Deacon @ 2018-01-04 11:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104111721.33834-1-catalin.marinas@arm.com>
Hi Catalin,
This is really awesome work!
On Thu, Jan 04, 2018 at 11:17:21AM +0000, Catalin Marinas wrote:
> Under some uncommon timing conditions, a generation check and
> xchg(active_asids, A1) in check_and_switch_context() on P1 can race with
> an ASID roll-over on P2. If P2 has not seen the update to
> active_asids[P1], it can re-allocate A1 to a new task T2 on P2. P1 ends
> up waiting on the spinlock since the xchg() returned 0 while P2 can go
> through a second ASID roll-over with (T2,A1,G2) active on P2. This
> roll-over copies active_asids[P1] == A1,G1 into reserved_asids[P1] and
> active_asids[P2] == A1,G2 into reserved_asids[P2]. A subsequent
> scheduling of T1 on P1 and T2 on P2 would match reserved_asids and get
> their generation bumped to G3:
>
> P1 P2
> -- --
> TTBR0.BADDR = T0
> TTBR0.ASID = A0
> asid_generation = G1
> check_and_switch_context(T1,A1,G1)
> generation match
> check_and_switch_context(T2,A0,G0)
> new_context()
> ASID roll-over
> asid_generation = G2
> flush_context()
> active_asids[P1] = 0
> asid_map[A1] = 0
> reserved_asids[P1] = A0,G0
> xchg(active_asids, A1)
> active_asids[P1] = A1,G1
> xchg returns 0
> spin_lock_irqsave()
> allocated ASID (T2,A1,G2)
> asid_map[A1] = 1
> active_asids[P2] = A1,G2
> ...
> check_and_switch_context(T3,A0,G0)
> new_context()
> ASID roll-over
> asid_generation = G3
> flush_context()
> active_asids[P1] = 0
> asid_map[A1] = 1
> reserved_asids[P1] = A1,G1
> reserved_asids[P2] = A1,G2
> allocated ASID (T3,A2,G3)
> asid_map[A2] = 1
> active_asids[P2] = A2,G3
> new_context()
> check_update_reserved_asid(A1,G1)
> matches reserved_asid[P1]
> reserved_asid[P1] = A1,G3
> updated T1 ASID to (T1,A1,G3)
> check_and_switch_context(T2,A1,G2)
> new_context()
> check_and_switch_context(A1,G2)
> matches reserved_asids[P2]
> reserved_asids[P2] = A1,G3
> updated T2 ASID to (T2,A1,G3)
>
> At this point, we have two tasks, T1 and T2 both using ASID A1 with the
> latest generation G3. Any of them is allowed to be scheduled on the
> other CPU leading to two different tasks with the same ASID on the same
> CPU.
>
> This patch changes the xchg to cmpxchg so that the active_asids is only
> updated if non-zero to avoid a race with an ASID roll-over on a
> different CPU.
>
> Cc: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
>
> We could add a cc stable as the patch is not invasive but I doubt one
> could trigger this under normal circumstances. I would say the (still
> small) probability is slightly increased under virtualisation when a
> vCPU could be scheduled out for a longer time allowing other vCPUs to go
> through a new roll-over.
>
> An arm32 patch will follow as well.
>
> (and we now have a formally verified ASID allocator ;))
It would be cool to mention the verifier in the commit message; potentially
even including the code somewhere so that it can be used to test future
changes. For example, I did something similar for the qrwlock and pushed
the changes here:
https://git.kernel.org/pub/scm/linux/kernel/git/will/qrwlock-rmem.git/
Anyway, for the patch:
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
I don't see the need for stable; this race isn't going to occur in
practice.
Will
^ permalink raw reply
* [PATCH V2] ARM: imx_v6_v7_defconfig: select the CONFIG_CPUFREQ_DT
From: Fabio Estevam @ 2018-01-04 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515091174-30944-1-git-send-email-Anson.Huang@nxp.com>
On Thu, Jan 4, 2018 at 4:39 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index 29cd1ac..885db90 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -58,6 +58,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
> CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> CONFIG_CPU_FREQ_GOV_USERSPACE=y
> CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
> +CONFIG_CPUFREQ_DT=y
> CONFIG_ARM_IMX6Q_CPUFREQ=y
> CONFIG_CPU_IDLE=y
> CONFIG_VFP=y
> @@ -318,14 +319,6 @@ CONFIG_USB_CONFIGFS_F_MIDI=y
> CONFIG_USB_CONFIGFS_F_HID=y
> CONFIG_USB_CONFIGFS_F_UVC=y
> CONFIG_USB_CONFIGFS_F_PRINTER=y
> -CONFIG_USB_ZERO=m
> -CONFIG_USB_AUDIO=m
> -CONFIG_USB_ETH=m
> -CONFIG_USB_G_NCM=m
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FUNCTIONFS=m
> -CONFIG_USB_MASS_STORAGE=m
> -CONFIG_USB_G_SERIAL=m
Not sure why these are getting removed automatically.
> CONFIG_MMC=y
> CONFIG_MMC_SDHCI=y
> CONFIG_MMC_SDHCI_PLTFM=y
> @@ -350,7 +343,6 @@ CONFIG_RTC_DRV_PCF8563=y
> CONFIG_RTC_DRV_M41T80=y
> CONFIG_RTC_DRV_MC13XXX=y
> CONFIG_RTC_DRV_MXC=y
> -CONFIG_RTC_DRV_MXC_V2=y
This is the rtc driver for mx53.
This driver will land in 4.16, so that's the reason it got removed
automatically by savedefconfig.
It would be safer if your patch could only add a single line:
'CONFIG_CPUFREQ_DT=y'.
^ permalink raw reply
* [PATCH] arm64: asid: Do not replace active_asids if already 0
From: Catalin Marinas @ 2018-01-04 11:17 UTC (permalink / raw)
To: linux-arm-kernel
Under some uncommon timing conditions, a generation check and
xchg(active_asids, A1) in check_and_switch_context() on P1 can race with
an ASID roll-over on P2. If P2 has not seen the update to
active_asids[P1], it can re-allocate A1 to a new task T2 on P2. P1 ends
up waiting on the spinlock since the xchg() returned 0 while P2 can go
through a second ASID roll-over with (T2,A1,G2) active on P2. This
roll-over copies active_asids[P1] == A1,G1 into reserved_asids[P1] and
active_asids[P2] == A1,G2 into reserved_asids[P2]. A subsequent
scheduling of T1 on P1 and T2 on P2 would match reserved_asids and get
their generation bumped to G3:
P1 P2
-- --
TTBR0.BADDR = T0
TTBR0.ASID = A0
asid_generation = G1
check_and_switch_context(T1,A1,G1)
generation match
check_and_switch_context(T2,A0,G0)
new_context()
ASID roll-over
asid_generation = G2
flush_context()
active_asids[P1] = 0
asid_map[A1] = 0
reserved_asids[P1] = A0,G0
xchg(active_asids, A1)
active_asids[P1] = A1,G1
xchg returns 0
spin_lock_irqsave()
allocated ASID (T2,A1,G2)
asid_map[A1] = 1
active_asids[P2] = A1,G2
...
check_and_switch_context(T3,A0,G0)
new_context()
ASID roll-over
asid_generation = G3
flush_context()
active_asids[P1] = 0
asid_map[A1] = 1
reserved_asids[P1] = A1,G1
reserved_asids[P2] = A1,G2
allocated ASID (T3,A2,G3)
asid_map[A2] = 1
active_asids[P2] = A2,G3
new_context()
check_update_reserved_asid(A1,G1)
matches reserved_asid[P1]
reserved_asid[P1] = A1,G3
updated T1 ASID to (T1,A1,G3)
check_and_switch_context(T2,A1,G2)
new_context()
check_and_switch_context(A1,G2)
matches reserved_asids[P2]
reserved_asids[P2] = A1,G3
updated T2 ASID to (T2,A1,G3)
At this point, we have two tasks, T1 and T2 both using ASID A1 with the
latest generation G3. Any of them is allowed to be scheduled on the
other CPU leading to two different tasks with the same ASID on the same
CPU.
This patch changes the xchg to cmpxchg so that the active_asids is only
updated if non-zero to avoid a race with an ASID roll-over on a
different CPU.
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
We could add a cc stable as the patch is not invasive but I doubt one
could trigger this under normal circumstances. I would say the (still
small) probability is slightly increased under virtualisation when a
vCPU could be scheduled out for a longer time allowing other vCPUs to go
through a new roll-over.
An arm32 patch will follow as well.
(and we now have a formally verified ASID allocator ;))
arch/arm64/mm/context.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index 1cb3bc92ae5c..1fe71b9fcf35 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -194,26 +194,29 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu)
void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
{
unsigned long flags;
- u64 asid;
+ u64 asid, old_active_asid;
asid = atomic64_read(&mm->context.id);
/*
* The memory ordering here is subtle.
- * If our ASID matches the current generation, then we update
- * our active_asids entry with a relaxed xchg. Racing with a
- * concurrent rollover means that either:
+ * If our active_asids is non-zero and the ASID matches the current
+ * generation, then we update the active_asids entry with a relaxed
+ * cmpxchg. Racing with a concurrent rollover means that either:
*
- * - We get a zero back from the xchg and end up waiting on the
+ * - We get a zero back from the cmpxchg and end up waiting on the
* lock. Taking the lock synchronises with the rollover and so
* we are forced to see the updated generation.
*
- * - We get a valid ASID back from the xchg, which means the
+ * - We get a valid ASID back from the cmpxchg, which means the
* relaxed xchg in flush_context will treat us as reserved
* because atomic RmWs are totally ordered for a given location.
*/
- if (!((asid ^ atomic64_read(&asid_generation)) >> asid_bits)
- && atomic64_xchg_relaxed(&per_cpu(active_asids, cpu), asid))
+ old_active_asid = atomic64_read(&per_cpu(active_asids, cpu));
+ if (old_active_asid &&
+ !((asid ^ atomic64_read(&asid_generation)) >> asid_bits) &&
+ atomic64_cmpxchg_relaxed(&per_cpu(active_asids, cpu),
+ old_active_asid, asid))
goto switch_mm_fastpath;
raw_spin_lock_irqsave(&cpu_asid_lock, flags);
^ permalink raw reply related
* [PATCH 01/10] soc: qcom: Separate kryo l2 accessors from PMU driver
From: ilialin at codeaurora.org @ 2018-01-04 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222020636.GG7997@codeaurora.org>
Tested COMPILE_TEST and found OK.
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd at codeaurora.org]
> Sent: Friday, December 22, 2017 4:07 AM
> To: Mark Rutland <mark.rutland@arm.com>
> Cc: Ilia Lin <ilialin@codeaurora.org>; linux-clk at vger.kernel.org;
linux-arm-
> kernel at lists.infradead.org; linux-arm-msm at vger.kernel.org;
> devicetree at vger.kernel.org; will.deacon at arm.com;
> rnayak at codeaurora.org; qualcomm-lt at lists.linaro.org;
> celster at codeaurora.org; tfinkel at codeaurora.org
> Subject: Re: [PATCH 01/10] soc: qcom: Separate kryo l2 accessors from PMU
> driver
>
> On 12/12, Mark Rutland wrote:
> > On Tue, Dec 12, 2017 at 02:31:28PM +0200, Ilia Lin wrote:
> > > + * accesses, and system registers with respect to device memory */
> > > +void set_l2_indirect_reg(u64 reg, u64 val) {
> > > + unsigned long flags;
> > > + mb();
> >
> > We didn't need this for the PMU driver, so it's unfortuante that it
> > now has to pay the cost.
> >
> > Can we please factor this mb() into the callers that need it?
>
> +1
>
> >
> > > + raw_spin_lock_irqsave(&l2_access_lock, flags);
> > > + write_sysreg_s(reg, L2CPUSRSELR_EL1);
> > > + isb();
> > > + write_sysreg_s(val, L2CPUSRDR_EL1);
> > > + isb();
> > > + raw_spin_unlock_irqrestore(&l2_access_lock, flags); }
> > > +EXPORT_SYMBOL(set_l2_indirect_reg);
> >
> > [...]
> >
> > > +#ifdef CONFIG_ARCH_QCOM
> > > +void set_l2_indirect_reg(u64 reg_addr, u64 val);
> > > +u64 get_l2_indirect_reg(u64 reg_addr); #else static inline void
> > > +set_l2_indirect_reg(u32 reg_addr, u32 val) {} static inline u32
> > > +get_l2_indirect_reg(u32 reg_addr) {
> > > + return 0;
> > > +}
> > > +#endif
> > > +#endif
> >
> > Are there any drivers that will bne built for !CONFIG_ARCH_QCOM that
> > reference this?
> >
> > It might be better to not have the stub versions, so that we get a
> > build-error if they are erroneously used.
> >
>
> Does that approach make COMPILE_TEST break?
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
> Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 04/10] clk: qcom: Add CPU clock driver for msm8996
From: ilialin at codeaurora.org @ 2018-01-04 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215223525.tzcycllxsl72hway@rob-hp-laptop>
This is address in the V2: https://patchwork.kernel.org/patch/10144489/
> -----Original Message-----
> From: Rob Herring [mailto:robh at kernel.org]
> Sent: Saturday, December 16, 2017 12:35 AM
> To: Ilia Lin <ilialin@codeaurora.org>
> Cc: linux-clk at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
linux-
> arm-msm at vger.kernel.org; sboyd at codeaurora.org;
> devicetree at vger.kernel.org; mark.rutland at arm.com;
> will.deacon at arm.com; rnayak at codeaurora.org; qualcomm-
> lt at lists.linaro.org; celster at codeaurora.org; tfinkel at codeaurora.org
> Subject: Re: [PATCH 04/10] clk: qcom: Add CPU clock driver for msm8996
>
> On Tue, Dec 12, 2017 at 02:31:31PM +0200, Ilia Lin wrote:
> > From: Rajendra Nayak <rnayak@codeaurora.org>
> >
> > Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2
> > PLLs, a primary and alternate. There are also
> > 2 Mux'es, a primary and secondary all connected together as shown
> > below
> >
> > +-------+
> > XO | |
> > +------------------>0 |
> > | |
> > PLL/2 | SMUX +----+
> > +------->1 | |
> > | | | |
> > | +-------+ | +-------+
> > | +---->0 |
> > | | |
> > +---------------+ | +----------->1 | CPU clk
> > |Primary PLL +----+ PLL_EARLY | | +------>
> > | +------+-----------+ +------>2 PMUX |
> > +---------------+ | | | |
> > | +------+ | +-->3 |
> > +--^+ ACD +-----+ | +-------+
> > +---------------+ +------+ |
> > |Alt PLL | |
> > | +---------------------------+
> > +---------------+ PLL_EARLY
> >
> > The primary PLL is what drives the CPU clk, except for times when we
> > are reprogramming the PLL itself (for rate changes) when we
> > temporarily switch to an alternate PLL. A subsequent patch adds
> > support to switch between primary and alternate PLL during rate
> > changes.
> >
> > The primary PLL operates on a single VCO range, between 600Mhz and
> > 3Ghz. However the CPUs do support OPPs with frequencies between
> 300Mhz
> > and 600Mhz. In order to support running the CPUs at those frequencies
> > we end up having to lock the PLL at twice the rate and drive the CPU
> > clk via the PLL/2 output and SMUX.
> >
> > So for frequencies above 600Mhz we follow the following path Primary
> > PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between
> > 300Mhz and 600Mhz we follow Primary PLL --> PLL/2 --> SMUX(1) -->
> > PMUX(0) --> CPU clk Support for this is added in a subsequent patch as
> > well.
> >
> > ACD stands for Adaptive Clock Distribution and is used to detect
> > voltage droops. We do not add support for ACD as yet.
> > This can be added at a later point as needed.
> >
> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> > Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> > ---
> > .../devicetree/bindings/clock/qcom,kryocc.txt | 17 +
>
> If you respin, please make bindings a separate patch. In any case,
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> > drivers/clk/qcom/Kconfig | 8 +
> > drivers/clk/qcom/Makefile | 1 +
> > drivers/clk/qcom/clk-cpu-8996.c | 388
> +++++++++++++++++++++
> > 4 files changed, 414 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/clock/qcom,kryocc.txt
> > create mode 100644 drivers/clk/qcom/clk-cpu-8996.c
^ permalink raw reply
* [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update
From: ilialin at codeaurora.org @ 2018-01-04 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ee78b47f-4fdb-01eb-ba04-c1172b7b7b00@arm.com>
This is address in the V2: https://patchwork.kernel.org/patch/10144477/
> -----Original Message-----
> From: Julien Thierry [mailto:julien.thierry at arm.com]
> Sent: Tuesday, December 12, 2017 5:06 PM
> To: Ilia Lin <ilialin@codeaurora.org>; linux-clk at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; linux-arm-msm at vger.kernel.org;
> sboyd at codeaurora.org
> Cc: mark.rutland at arm.com; devicetree at vger.kernel.org;
> rnayak at codeaurora.org; will.deacon at arm.com; tfinkel at codeaurora.org;
> qualcomm-lt at lists.linaro.org; celster at codeaurora.org; Taniya Das
> <tdas@codeaurora.org>
> Subject: Re: [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs
> w/wo dynamic update
>
> Hi,
>
> On 12/12/17 12:31, Ilia Lin wrote:
> > From: Taniya Das <tdas@codeaurora.org>
> >
> > From: Taniya Das <tdas@codeaurora.org>
> >
> > Alpha PLLs which do not support dynamic update feature need to be
> > explicitly disabled before a rate change.
> > The ones which do support dynamic update do so within a single vco
> > range, so add a min/max freq check for such PLLs so they fall in the
> > vco range.
> >
> > Signed-off-by: Taniya Das <tdas@codeaurora.org>
> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> > Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> > ---
> > drivers/clk/qcom/clk-alpha-pll.c | 71
> +++++++++++++++++++++++++++++++++-------
> > drivers/clk/qcom/clk-alpha-pll.h | 5 +++
> > 2 files changed, 65 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/clk-alpha-pll.c
> > b/drivers/clk/qcom/clk-alpha-pll.c
> > index 47a1da3..ecb9e7f 100644
> > --- a/drivers/clk/qcom/clk-alpha-pll.c
> > +++ b/drivers/clk/qcom/clk-alpha-pll.c
> > @@ -376,19 +376,46 @@ static unsigned long alpha_pll_calc_rate(u64
> prate, u32 l, u32 a)
> > return alpha_pll_calc_rate(prate, l, a);
> > }
> >
> > -static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > - unsigned long prate)
> > +static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long prate,
> > + int (*enable)(struct clk_hw *hw),
> > + void (*disable)(struct clk_hw *hw))
> > {
> > + bool enabled;
>
> Some remarks about this.
>
> > struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> > const struct pll_vco *vco;
> > u32 l, off = pll->offset;
> > u64 a;
> >
> > rate = alpha_pll_round_rate(rate, prate, &l, &a);
> > - vco = alpha_pll_find_vco(pll, rate);
> > - if (!vco) {
> > - pr_err("alpha pll not in a valid vco range\n");
> > - return -EINVAL;
> > + enabled = clk_hw_is_enabled(hw);
>
> This is not needed unless we go through the 'else' branch.
>
> > +
> > + if (pll->flags & SUPPORTS_DYNAMIC_UPDATE) {
> > + /*
> > + * PLLs which support dynamic updates support one single
> > + * vco range, between min_rate and max_rate supported
> > + */
> > + if (rate < pll->min_rate || rate > pll->max_rate) {
> > + pr_err("alpha pll rate outside supported min/max
> range\n");
> > + return -EINVAL;
> > + }
> > + } else {
> > + /*
> > + * All alpha PLLs which do not support dynamic update,
> > + * should be disabled before a vco update.
> > + */
> > + if (enabled)
> > + disable(hw);
> > +
> > + vco = alpha_pll_find_vco(pll, rate);
> > + if (!vco) {
> > + pr_err("alpha pll not in a valid vco range\n");
> > + return -EINVAL;
> > + }
> > +
> > + regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
> > + PLL_VCO_MASK << PLL_VCO_SHIFT,
> > + vco->val << PLL_VCO_SHIFT);
> > }
> >
> > regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l); @@ -401,16
> > +428,29 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned
> long rate,
> > regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a
> >> 32);
> > }
> >
> > - regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
> > - PLL_VCO_MASK << PLL_VCO_SHIFT,
> > - vco->val << PLL_VCO_SHIFT);
> > -
> > regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
> PLL_ALPHA_EN,
> > PLL_ALPHA_EN);
> >
> > + if (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled)
> > + enable(hw);
> > +
>
> This condition is only "did we disable the clock and need to reenable it?".
>
> To make it clearer, I'd suggest renaming 'enabled' to something like
> 'need_reenabling' and the code look like this:
>
> static int alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> unsigned long prate,
> int (*enable)(struct clk_hw *hw),
> void (*disable)(struct clk_hw *hw)) {
> bool need_reenabling = false;
>
> [...]
>
> if(pll->flags & SUPPORTS_DYNAMIC_UPDATE) {
> [...]
> } else {
> if (clk_hw_is_enabled(hw)) {
> disable(hw);
> need_reenabling = true;
> }
> [...]
> }
>
> [...]
>
> if (need_reenabling)
> enable(hw);
>
> }
>
>
> Cheers,
>
> --
> Julien Thierry
^ permalink raw reply
* [PATCH 01/10] soc: qcom: Separate kryo l2 accessors from PMU driver
From: ilialin at codeaurora.org @ 2018-01-04 11:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171212140302.au4wart4uhwm7lfq@lakrids.cambridge.arm.com>
This is address in the V2: https://patchwork.kernel.org/patch/10144473/
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland at arm.com]
> Sent: Tuesday, December 12, 2017 4:03 PM
> To: Ilia Lin <ilialin@codeaurora.org>
> Cc: linux-clk at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
linux-
> arm-msm at vger.kernel.org; sboyd at codeaurora.org;
> devicetree at vger.kernel.org; will.deacon at arm.com;
> rnayak at codeaurora.org; qualcomm-lt at lists.linaro.org;
> celster at codeaurora.org; tfinkel at codeaurora.org
> Subject: Re: [PATCH 01/10] soc: qcom: Separate kryo l2 accessors from PMU
> driver
>
> Hi,
>
> On Tue, Dec 12, 2017 at 02:31:28PM +0200, Ilia Lin wrote:
> > The driver provides kernel level API for other drivers to access the
> > MSM8996 L2 cache registers.
> > Separating the L2 access code from the PMU driver and making it public
> > to allow other drivers use it.
> > The accesses must be separated with a single spinlock, maintained in
> > this driver.
>
> > -static void set_l2_indirect_reg(u64 reg, u64 val) -{
> > - unsigned long flags;
> > -
> > - raw_spin_lock_irqsave(&l2_access_lock, flags);
> > - write_sysreg_s(reg, L2CPUSRSELR_EL1);
> > - isb();
> > - write_sysreg_s(val, L2CPUSRDR_EL1);
> > - isb();
> > - raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> > -}
>
> > +/**
> > + * set_l2_indirect_reg: write value to an L2 register
> > + * @reg: Address of L2 register.
> > + * @value: Value to be written to register.
> > + *
> > + * Use architecturally required barriers for ordering between system
> > +register
> > + * accesses, and system registers with respect to device memory */
> > +void set_l2_indirect_reg(u64 reg, u64 val) {
> > + unsigned long flags;
> > + mb();
>
> We didn't need this for the PMU driver, so it's unfortuante that it now
has to
> pay the cost.
>
> Can we please factor this mb() into the callers that need it?
>
> > + raw_spin_lock_irqsave(&l2_access_lock, flags);
> > + write_sysreg_s(reg, L2CPUSRSELR_EL1);
> > + isb();
> > + write_sysreg_s(val, L2CPUSRDR_EL1);
> > + isb();
> > + raw_spin_unlock_irqrestore(&l2_access_lock, flags); }
> > +EXPORT_SYMBOL(set_l2_indirect_reg);
>
> [...]
>
> > +#ifdef CONFIG_ARCH_QCOM
> > +void set_l2_indirect_reg(u64 reg_addr, u64 val);
> > +u64 get_l2_indirect_reg(u64 reg_addr); #else static inline void
> > +set_l2_indirect_reg(u32 reg_addr, u32 val) {} static inline u32
> > +get_l2_indirect_reg(u32 reg_addr) {
> > + return 0;
> > +}
> > +#endif
> > +#endif
>
> Are there any drivers that will bne built for !CONFIG_ARCH_QCOM that
> reference this?
>
> It might be better to not have the stub versions, so that we get a
build-error
> if they are erroneously used.
>
> Thannks,
> Mark.
^ permalink raw reply
* [PATCH v4 3/7] ARM: davinci: fix duplicate clocks
From: Sekhar Nori @ 2018-01-04 11:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-4-git-send-email-david@lechnology.com>
On Monday 01 January 2018 05:09 AM, David Lechner wrote:
> There are a number of clocks that were duplicated because they are used by
> more than one device. It is no longer necessary to do this since we are
> explicitly calling clk_register_clkdev() for each clock. In da830.c, some
> clocks were using the same LPSC, which would cause problems with reference
> counting, so these are combinded into one clock each. In da850.c the
> duplicate clocks had already been fixed by creating dummy child clocks, so
> these clocks are removed.
>
> Signed-off-by: David Lechner <david@lechnology.com>
If we do end up keeping 2/7, this should be done before that - to avoid
retouching code that was just introduced.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v4 2/7] ARM: davinci: don't use static clk_lookup
From: Sekhar Nori @ 2018-01-04 11:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-3-git-send-email-david@lechnology.com>
Hi David,
On Monday 01 January 2018 05:09 AM, David Lechner wrote:
> In preparation of moving to the common clock framework, usage of static
> struct clk_lookup is removed. The common clock framework uses an opaque
> struct clk, so we won't be able to use static tables as was previously
> done.
>
> davinci_clk_init() is changed to init a single clock instead of a table
> and an individual clk_register_clkdev() is added for each clock.
>
> Signed-off-by: David Lechner <david@lechnology.com>
Is there a need for this considering in 6/7 you end up modifying quite a
bit of this patch again?
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v2 11/11] DT: QCOM: Add thermal mitigation to msm8996
From: Ilia Lin @ 2018-01-04 11:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515064215-22202-1-git-send-email-ilialin@codeaurora.org>
Add thermal mitigation configuration to msm8996.
With the cpufreq-dt OPP table the CPU frequency may be
scaled and therefore throttled by the thermal config.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 98 +++++++++++++++++++++++++++++++----
1 file changed, 87 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 8beea7e..6fa061f 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8996";
@@ -88,6 +89,10 @@
enable-method = "psci";
clocks = <&kryocc 0>;
operating-points-v2 = <&cluster0_opp>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -102,6 +107,10 @@
enable-method = "psci";
clocks = <&kryocc 0>;
operating-points-v2 = <&cluster0_opp>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
@@ -112,6 +121,10 @@
enable-method = "psci";
clocks = <&kryocc 1>;
operating-points-v2 = <&cluster1_opp>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@@ -126,6 +139,10 @@
enable-method = "psci";
clocks = <&kryocc 1>;
operating-points-v2 = <&cluster1_opp>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
@@ -336,18 +353,33 @@
thermal-sensors = <&tsens0 3>;
trips {
- cpu_alert0: trip0 {
+ cpu_alert0: cpu_alert0 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn0: cpu_warn0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
-
- cpu_crit0: trip1 {
+ cpu_crit0: cpu_crit0 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn0>;
+ cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal1 {
@@ -357,18 +389,33 @@
thermal-sensors = <&tsens0 5>;
trips {
- cpu_alert1: trip0 {
+ cpu_alert1: cpu_alert1 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn1: cpu_warn1 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
-
- cpu_crit1: trip1 {
+ cpu_crit1: cpu_crit1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn1>;
+ cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal2 {
@@ -378,18 +425,32 @@
thermal-sensors = <&tsens0 8>;
trips {
- cpu_alert2: trip0 {
+ cpu_alert2: cpu_alert2 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn2: cpu_warn2 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
-
- cpu_crit2: trip1 {
+ cpu_crit2: cpu_crit2 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert2>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn2>;
+ cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal3 {
@@ -399,18 +460,33 @@
thermal-sensors = <&tsens0 10>;
trips {
- cpu_alert3: trip0 {
+ cpu_alert3: cpu_alert3 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn3: cpu_warn3 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
-
cpu_crit3: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert3>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn3>;
+ cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH v2 10/11] DT: QCOM: Add cpufreq-dt to msm8996
From: Ilia Lin @ 2018-01-04 11:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515064215-22202-1-git-send-email-ilialin@codeaurora.org>
Add device tree frequency table for the MSM8996 to be
used by the upstream cpufreq-dt driver with the clk-cpu-8996
driver as infrastructure.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 184 ++++++++++++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 3 +
3 files changed, 188 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
index 230e9c8..da23bda 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
@@ -17,5 +17,5 @@
/ {
model = "Qualcomm Technologies, Inc. DB820c";
- compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
+ compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 4b2afcc..8beea7e 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -86,6 +86,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -98,6 +100,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x1>;
enable-method = "psci";
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
next-level-cache = <&L2_0>;
};
@@ -106,6 +110,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@@ -118,6 +124,8 @@
compatible = "qcom,kryo";
reg = <0x0 0x101>;
enable-method = "psci";
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
next-level-cache = <&L2_1>;
};
@@ -144,6 +152,182 @@
};
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp at 307200000 {
+ opp-hz = /bits/ 64 < 307200000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 422400000 {
+ opp-hz = /bits/ 64 < 422400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 480000000 {
+ opp-hz = /bits/ 64 < 480000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 556800000 {
+ opp-hz = /bits/ 64 < 556800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 652800000 {
+ opp-hz = /bits/ 64 < 652800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 729600000 {
+ opp-hz = /bits/ 64 < 729600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 844800000 {
+ opp-hz = /bits/ 64 < 844800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 960000000 {
+ opp-hz = /bits/ 64 < 960000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1036800000 {
+ opp-hz = /bits/ 64 < 1036800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1113600000 {
+ opp-hz = /bits/ 64 < 1113600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1190400000 {
+ opp-hz = /bits/ 64 < 1190400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1228800000 {
+ opp-hz = /bits/ 64 < 1228800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1324800000 {
+ opp-hz = /bits/ 64 < 1324800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1401600000 {
+ opp-hz = /bits/ 64 < 1401600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1478400000 {
+ opp-hz = /bits/ 64 < 1478400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1593600000 {
+ opp-hz = /bits/ 64 < 1593600000 >;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp at 307200000 {
+ opp-hz = /bits/ 64 < 307200000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 403200000 {
+ opp-hz = /bits/ 64 < 403200000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 480000000 {
+ opp-hz = /bits/ 64 < 480000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 556800000 {
+ opp-hz = /bits/ 64 < 556800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 652800000 {
+ opp-hz = /bits/ 64 < 652800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 729600000 {
+ opp-hz = /bits/ 64 < 729600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 806400000 {
+ opp-hz = /bits/ 64 < 806400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 883200000 {
+ opp-hz = /bits/ 64 < 883200000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 940800000 {
+ opp-hz = /bits/ 64 < 940800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1036800000 {
+ opp-hz = /bits/ 64 < 1036800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1113600000 {
+ opp-hz = /bits/ 64 < 1113600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1190400000 {
+ opp-hz = /bits/ 64 < 1190400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1248000000 {
+ opp-hz = /bits/ 64 < 1248000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1324800000 {
+ opp-hz = /bits/ 64 < 1324800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1401600000 {
+ opp-hz = /bits/ 64 < 1401600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1478400000 {
+ opp-hz = /bits/ 64 < 1478400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1552000000 {
+ opp-hz = /bits/ 64 < 1552000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1632000000 {
+ opp-hz = /bits/ 64 < 1632000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1708800000 {
+ opp-hz = /bits/ 64 < 1708800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1785600000 {
+ opp-hz = /bits/ 64 < 1785600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1824000000 {
+ opp-hz = /bits/ 64 < 1824000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1920000000 {
+ opp-hz = /bits/ 64 < 1920000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 1996800000 {
+ opp-hz = /bits/ 64 < 1996800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 2073600000 {
+ opp-hz = /bits/ 64 < 2073600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp at 2150400000 {
+ opp-hz = /bits/ 64 < 2150400000 >;
+ clock-latency-ns = <200000>;
+ };
+
+ };
thermal-zones {
cpu-thermal0 {
polling-delay-passive = <250>;
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index ecc56e2..0feca0e 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -95,6 +95,9 @@
{ .compatible = "xlnx,zynq-7000", },
{ .compatible = "xlnx,zynqmp", },
+ { .compatible = "qcom,msm8996", },
+ { .compatible = "qcom,apq8096", },
+
{ }
};
--
1.9.1
^ permalink raw reply related
* [PATCH v2 09/11] clk: qcom: Add ACD path to CPU clock driver for msm8996
From: Ilia Lin @ 2018-01-04 11:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515064215-22202-1-git-send-email-ilialin@codeaurora.org>
The PMUX for each duplex allows for selection of ACD clock source.
The DVM (Dynamic Variation Monitor) will flag an error
when a voltage droop event is detected. This flagged error
enables ACD to provide a div-by-2 clock, sourced from the primary PLL.
The duplex will be provided the divided clock
until a pre-programmed delay has expired.
This change configures ACD during the probe and switches
the PMUXes to the ACD clock source.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
---
drivers/clk/qcom/clk-cpu-8996.c | 122 ++++++++++++++++++++++++++++++++++------
1 file changed, 106 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index f1bfd13..d38ff6d 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -17,6 +17,7 @@
#include <linux/regmap.h>
#include <linux/clk-provider.h>
#include "clk-alpha-pll.h"
+#include <soc/qcom/kryo-l2-accessors.h>
#define VCO(a, b, c) { \
.val = a,\
@@ -29,6 +30,27 @@
#define ACD_INDEX 2
#define ALT_INDEX 3
#define DIV_2_THRESHOLD 600000000
+#define PWRCL_REG_OFFSET 0x0
+#define PERFCL_REG_OFFSET 0x80000
+#define MUX_OFFSET 0x40
+#define ALT_PLL_OFFSET 0x100
+#define SSSCTL_OFFSET 0x160
+/*
+APCy_QLL_SSSCTL value:
+SACDRCLEN=1
+SSWEN=1
+SSTRTEN=1
+SSTPAPMSWEN=1
+*/
+#define SSSCTL_VAL 0xF
+
+enum {
+ APC_BASE,
+ EFUSE_BASE,
+ NUM_BASES
+};
+
+static void __iomem *vbases[NUM_BASES];
/* PLLs */
@@ -44,7 +66,7 @@
};
static struct clk_alpha_pll perfcl_pll = {
- .offset = 0x80000,
+ .offset = PERFCL_REG_OFFSET,
.min_rate = 600000000,
.max_rate = 3000000000,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_16BIT_ALPHA
@@ -58,7 +80,7 @@
};
static struct clk_alpha_pll pwrcl_pll = {
- .offset = 0x0,
+ .offset = PWRCL_REG_OFFSET,
.min_rate = 600000000,
.max_rate = 3000000000,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_16BIT_ALPHA
@@ -90,7 +112,7 @@
};
static struct clk_alpha_pll perfcl_alt_pll = {
- .offset = 0x80100,
+ .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
@@ -103,7 +125,7 @@
};
static struct clk_alpha_pll pwrcl_alt_pll = {
- .offset = 0x100,
+ .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
@@ -114,6 +136,7 @@
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
+static void qcom_cpu_clk_msm8996_acd_init(void);
/* Mux'es */
@@ -197,6 +220,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
switch (event) {
case PRE_RATE_CHANGE:
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
+ qcom_cpu_clk_msm8996_acd_init();
break;
case POST_RATE_CHANGE:
if (cnd->new_rate < DIV_2_THRESHOLD)
@@ -204,7 +228,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
DIV_2_INDEX);
else
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
- PLL_INDEX);
+ ACD_INDEX);
break;
default:
ret = 0;
@@ -221,7 +245,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
};
static struct clk_cpu_8996_mux pwrcl_smux = {
- .reg = 0x40,
+ .reg = PWRCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
@@ -237,7 +261,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
};
static struct clk_cpu_8996_mux perfcl_smux = {
- .reg = 0x80040,
+ .reg = PERFCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
@@ -253,7 +277,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
};
static struct clk_cpu_8996_mux pwrcl_pmux = {
- .reg = 0x40,
+ .reg = PWRCL_REG_OFFSET + MUX_OFFSET,
.shift = 0,
.width = 2,
.pll = &pwrcl_pll.clkr.hw,
@@ -274,7 +298,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
};
static struct clk_cpu_8996_mux perfcl_pmux = {
- .reg = 0x80040,
+ .reg = PERFCL_REG_OFFSET + MUX_OFFSET,
.shift = 0,
.width = 2,
.pll = &perfcl_pll.clkr.hw,
@@ -342,7 +366,17 @@ struct clk_hw_clks {
CLK_SET_RATE_PARENT, 1, 2);
pwrcl_smux.pll = hws->hws[1];
- hws->num = 2;
+ hws->hws[2] = clk_hw_register_fixed_factor(dev, "perfcl_pll_acd",
+ "perfcl_pll",
+ CLK_SET_RATE_PARENT, 1, 1);
+ perfcl_pmux.pll = hws->hws[2];
+
+ hws->hws[3] = clk_hw_register_fixed_factor(dev, "pwrcl_pll_acd",
+ "pwrcl_pll",
+ CLK_SET_RATE_PARENT, 1, 1);
+ pwrcl_pmux.pll = hws->hws[3];
+
+ hws->num = 4;
for (i = 0; i < ARRAY_SIZE(clks); i++) {
ret = devm_clk_register_regmap(dev, clks[i]);
@@ -378,10 +412,65 @@ struct clk_hw_clks {
return ret;
}
+#define CPU_AFINITY_MASK 0xFFF
+#define PWRCL_CPU_REG_MASK 0x3
+#define PERFCL_CPU_REG_MASK 0x103
+
+/* ACD static settings (HMSS HPG 7.2.2) */
+#define L2ACDCR_REG 0x580ULL
+#define L2ACDTD_REG 0x581ULL
+#define L2ACDDVMRC_REG 0x584ULL
+#define L2ACDSSCR_REG 0x589ULL
+#define ACDTD_VAL 0x00006A11
+#define ACDCR_VAL 0x002C5FFD
+#define ACDSSCR_VAL 0x00000601
+#define ACDDVMRC_VAL 0x000E0F0F
+
+static DEFINE_SPINLOCK(acd_lock);
+
+static void qcom_cpu_clk_msm8996_acd_init(void)
+{
+ u64 hwid;
+ unsigned long flags;
+
+ spin_lock_irqsave(&acd_lock, flags);
+
+ hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK;
+
+ /* Program ACD Tunable-Length Delay (TLD) */
+ set_l2_indirect_reg(L2ACDTD_REG, ACDTD_VAL);
+ /* Initial ACD for *this* cluster */
+ set_l2_indirect_reg(L2ACDDVMRC_REG, ACDDVMRC_VAL);
+ /* Program ACD soft start control bits. */
+ set_l2_indirect_reg(L2ACDSSCR_REG, ACDSSCR_VAL);
+
+ if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) {
+ /* Enable Soft Stop/Start */
+ if (vbases[APC_BASE])
+ writel_relaxed(SSSCTL_VAL, vbases[APC_BASE] +
+ PWRCL_REG_OFFSET + SSSCTL_OFFSET);
+ /* Ensure SSSCTL config goes through before enabling ACD. */
+ mb();
+ /* Program ACD control bits */
+ set_l2_indirect_reg(L2ACDCR_REG, ACDCR_VAL);
+ }
+ if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) { //else {
+ /* Program ACD control bits */
+ set_l2_indirect_reg(L2ACDCR_REG, ACDCR_VAL);
+ /* Enable Soft Stop/Start */
+ if (vbases[APC_BASE])
+ writel_relaxed(SSSCTL_VAL, vbases[APC_BASE] +
+ PERFCL_REG_OFFSET + SSSCTL_OFFSET);
+ /* Ensure SSSCTL config goes through before enabling ACD. */
+ mb();
+ }
+
+ spin_unlock_irqrestore(&acd_lock, flags);
+}
+
static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
{
int ret;
- void __iomem *base;
struct resource *res;
struct regmap *regmap_cpu;
struct clk_hw_clks *hws;
@@ -394,17 +483,17 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
- hws = devm_kzalloc(dev, sizeof(*hws) + 2 * sizeof(struct clk_hw *),
+ hws = devm_kzalloc(dev, sizeof(*hws) + 4 * sizeof(struct clk_hw *),
GFP_KERNEL);
if (!hws)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(dev, res);
- if (IS_ERR(base))
- return PTR_ERR(base);
+ vbases[APC_BASE] = devm_ioremap_resource(dev, res);
+ if (IS_ERR(vbases[APC_BASE]))
+ return PTR_ERR(vbases[APC_BASE]);
- regmap_cpu = devm_regmap_init_mmio(dev, base,
+ regmap_cpu = devm_regmap_init_mmio(dev, vbases[APC_BASE],
&cpu_msm8996_regmap_config);
if (IS_ERR(regmap_cpu))
return PTR_ERR(regmap_cpu);
@@ -412,6 +501,7 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
ret = qcom_cpu_clk_msm8996_register_clks(dev, hws, regmap_cpu);
if (ret)
return ret;
+ qcom_cpu_clk_msm8996_acd_init();
data->hws[0] = &pwrcl_pmux.clkr.hw;
data->hws[1] = &perfcl_pmux.clkr.hw;
--
1.9.1
^ permalink raw reply related
* [PATCH v2 08/11] clk: qcom: clk-cpu-8996: Prepare PLLs on probe
From: Ilia Lin @ 2018-01-04 11:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515064215-22202-1-git-send-email-ilialin@codeaurora.org>
The PLLs must be prepared enabled during the probe to be
accessible by the OPPs. Otherwise an OPP may switch
to non-enabled clock.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
---
drivers/clk/qcom/clk-cpu-8996.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index 81cf466..f1bfd13 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -15,7 +15,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
-
+#include <linux/clk-provider.h>
#include "clk-alpha-pll.h"
#define VCO(a, b, c) { \
@@ -160,7 +160,7 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
cpuclk->shift);
val = index;
- val = cpuclk->shift;
+ val <<= cpuclk->shift;
return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
}
@@ -269,7 +269,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
},
.num_parents = 4,
.ops = &clk_cpu_8996_mux_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
},
};
@@ -285,12 +285,12 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
.parent_names = (const char *[]){
"perfcl_smux",
"perfcl_pll",
- "pwrcl_pll_acd",
+ "perfcl_pll_acd",
"perfcl_alt_pll",
},
.num_parents = 4,
.ops = &clk_cpu_8996_mux_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
},
};
@@ -355,6 +355,18 @@ struct clk_hw_clks {
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
+ /* Enable all PLLs and alt PLLs */
+ clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);
+ clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);
+ clk_prepare_enable(pwrcl_pll.clkr.hw.clk);
+ clk_prepare_enable(perfcl_pll.clkr.hw.clk);
+
+ /* Set initial boot frequencies for power/perf PLLs */
+ clk_set_rate(pwrcl_alt_pll.clkr.hw.clk, 652800000);
+ clk_set_rate(perfcl_alt_pll.clkr.hw.clk, 652800000);
+ clk_set_rate(pwrcl_pll.clkr.hw.clk, 652800000);
+ clk_set_rate(perfcl_pll.clkr.hw.clk, 652800000);
+
ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
if (ret)
return ret;
--
1.9.1
^ permalink raw reply related
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