* [RFC PATCH 4/9] soc: samsung: Add generic power-management driver for Exynos
From: Chanwoo Choi @ 2018-01-09 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515484746-10656-1-git-send-email-cw00.choi@samsung.com>
To enter suspend, Exynos SoC requires the some machine dependent procedures.
This patch introduces the generic power-management driver to support
those requirements and generic interface for power state management.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/mach-exynos/common.h | 1 -
arch/arm/mach-exynos/exynos.c | 23 +----
drivers/soc/samsung/Makefile | 2 +-
drivers/soc/samsung/exynos-pm.c | 176 ++++++++++++++++++++++++++++++++++
include/linux/soc/samsung/exynos-pm.h | 21 ++++
5 files changed, 199 insertions(+), 24 deletions(-)
create mode 100644 drivers/soc/samsung/exynos-pm.c
create mode 100644 include/linux/soc/samsung/exynos-pm.h
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index afbc143a3d5d..ad482c0fc131 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -119,7 +119,6 @@ enum {
* Magic values for bootloader indicating chosen low power mode.
* See also Documentation/arm/Samsung/Bootloader-interface.txt
*/
-#define EXYNOS_SLEEP_MAGIC 0x00000bad
#define EXYNOS_AFTR_MAGIC 0xfcba0d10
void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index fbd108ce8745..0d5265d175c4 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -12,6 +12,7 @@
#include <linux/of_fdt.h>
#include <linux/platform_device.h>
#include <linux/irqchip.h>
+#include <linux/soc/samsung/exynos-pm.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <asm/cacheflush.h>
@@ -41,28 +42,6 @@
.id = -1,
};
-void __iomem *sysram_base_addr __ro_after_init;
-void __iomem *sysram_ns_base_addr __ro_after_init;
-
-void __init exynos_sysram_init(void)
-{
- struct device_node *node;
-
- for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
- if (!of_device_is_available(node))
- continue;
- sysram_base_addr = of_iomap(node, 0);
- break;
- }
-
- for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
- if (!of_device_is_available(node))
- continue;
- sysram_ns_base_addr = of_iomap(node, 0);
- break;
- }
-}
-
static void __init exynos_init_late(void)
{
if (of_machine_is_compatible("samsung,exynos5440"))
diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
index d2e637339a45..58ca5bdabf1f 100644
--- a/drivers/soc/samsung/Makefile
+++ b/drivers/soc/samsung/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
+obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o exynos-pm.o
obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \
exynos5250-pmu.o exynos5420-pmu.o \
diff --git a/drivers/soc/samsung/exynos-pm.c b/drivers/soc/samsung/exynos-pm.c
new file mode 100644
index 000000000000..45d84bbe5e61
--- /dev/null
+++ b/drivers/soc/samsung/exynos-pm.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// based on arch/arm/mach-exynos/suspend.c
+// Copyright (c) 2018 Samsung Electronics Co., Ltd.
+//
+// Exynos Power Management support driver
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/kernel.h>
+#include <linux/regulator/machine.h>
+#include <linux/syscore_ops.h>
+#include <linux/suspend.h>
+
+#include <asm/cpuidle.h>
+#include <asm/io.h>
+#include <asm/suspend.h>
+
+#include <linux/soc/samsung/exynos-pm.h>
+#include <linux/soc/samsung/exynos-pmu.h>
+
+/*
+ * The struct exynos_pm_data contains the callbacks of
+ * both struct platform_suspend_ops and syscore_ops.
+ * This structure is listed according to the call order,
+ * because the callback call order for the two structures is mixed.
+ */
+struct exynos_pm_data {
+ int (*prepare)(void); /* for platform_suspend_ops */
+ int (*suspend)(void); /* for syscore_ops */
+ int (*enter)(suspend_state_t state); /* for platform_suspend_ops */
+ void (*resume)(void); /* for syscore_ops */
+ void (*finish)(void); /* for platform_suspend_ops */
+};
+
+static struct platform_suspend_ops exynos_pm_suspend_ops;
+static struct syscore_ops exynos_pm_syscore_ops;
+static const struct exynos_pm_data *pm_data __ro_after_init;
+
+void __iomem *sysram_base_addr __ro_after_init;
+void __iomem *sysram_ns_base_addr __ro_after_init;
+
+static int exynos_pm_prepare(void)
+{
+ int ret;
+
+ /*
+ * REVISIT: It would be better if struct platform_suspend_ops
+ * .prepare handler get the suspend_state_t as a parameter to
+ * avoid hard-coding the suspend to mem state. It's safe to do
+ * it now only because the suspend_valid_only_mem function is
+ * used as the .valid callback used to check if a given state
+ * is supported by the platform anyways.
+ */
+ ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
+ if (ret) {
+ pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
+ return ret;
+ }
+
+ if (pm_data->prepare) {
+ ret = pm_data->prepare();
+ if (ret) {
+ pr_err("Failed to prepare for suspend (%d)\n", ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int exynos_pm_suspend(void)
+{
+ if (pm_data->suspend)
+ return pm_data->suspend();
+
+ return 0;
+}
+
+static int exynos_pm_enter(suspend_state_t state)
+{
+ int ret;
+
+ exynos_sys_powerdown_conf(SYS_SLEEP);
+
+ ret = pm_data->enter(state);
+ if (ret) {
+ pr_err("Failed to enter sleep\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void exynos_pm_resume(void)
+{
+ exynos_sys_powerup_conf(SYS_SLEEP);
+
+ if (pm_data->resume)
+ pm_data->resume();
+}
+
+static void exynos_pm_finish(void)
+{
+ int ret;
+
+ ret = regulator_suspend_finish();
+ if (ret)
+ pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
+
+ if (pm_data->finish)
+ pm_data->finish();
+}
+
+/*
+ * Split the data between ARM architectures because it is relatively big
+ * and useless on other arch.
+ */
+#ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS
+#define exynos_pm_data_arm_ptr(data) (&data)
+#else
+#define exynos_pm_data_arm_ptr(data) NULL
+#endif
+
+static const struct of_device_id exynos_pm_of_device_ids[] = {
+ { /*sentinel*/ },
+};
+
+void __init exynos_sysram_init(void)
+{
+ struct device_node *np;
+
+ for_each_compatible_node(np, NULL, "samsung,exynos4210-sysram") {
+ if (!of_device_is_available(np))
+ continue;
+ sysram_base_addr = of_iomap(np, 0);
+ break;
+ }
+
+ for_each_compatible_node(np, NULL, "samsung,exynos4210-sysram-ns") {
+ if (!of_device_is_available(np))
+ continue;
+ sysram_ns_base_addr = of_iomap(np, 0);
+ break;
+ }
+}
+
+static int __init exynos_pm_init(void)
+{
+ const struct of_device_id *match;
+ struct device_node *np;
+
+ np = of_find_matching_node_and_match(NULL,
+ exynos_pm_of_device_ids, &match);
+ if (!np) {
+ pr_err("Failed to find PMU node for Exynos Power-Management\n");
+ return -ENODEV;
+ }
+ pm_data = (const struct exynos_pm_data *) match->data;
+
+ exynos_sysram_init();
+
+ exynos_pm_suspend_ops.valid = suspend_valid_only_mem;
+ exynos_pm_suspend_ops.prepare = exynos_pm_prepare;
+ exynos_pm_syscore_ops.suspend = exynos_pm_suspend;
+ exynos_pm_suspend_ops.enter = exynos_pm_enter;
+ exynos_pm_syscore_ops.resume = exynos_pm_resume;
+ exynos_pm_suspend_ops.finish = exynos_pm_finish;
+
+ register_syscore_ops(&exynos_pm_syscore_ops);
+ suspend_set_ops(&exynos_pm_suspend_ops);
+
+ return 0;
+}
+postcore_initcall(exynos_pm_init);
diff --git a/include/linux/soc/samsung/exynos-pm.h b/include/linux/soc/samsung/exynos-pm.h
new file mode 100644
index 000000000000..b1afe95ed10c
--- /dev/null
+++ b/include/linux/soc/samsung/exynos-pm.h
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 Samsung Electronics Co., Ltd.
+//
+// Header for Exynos Power-Management support driver
+
+#ifndef __LINUX_SOC_EXYNOS_PM_H
+#define __LINUX_SOC_EXYNOS_PM_H
+
+/*
+ * Magic values for bootloader indicating chosen low power mode.
+ * See also Documentation/arm/Samsung/Bootloader-interface.txt
+ */
+#define EXYNOS_SLEEP_MAGIC 0x00000bad
+
+extern void __iomem *sysram_base_addr;
+extern void __iomem *sysram_ns_base_addr;
+
+extern void exynos_sysram_init(void);
+
+#endif /* __LINUX_SOC_EXYNOS_PMU_H */
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 5/9] soc: samsung: pm: Add support for suspend-to-ram of Exynos5433
From: Chanwoo Choi @ 2018-01-09 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515484746-10656-1-git-send-email-cw00.choi@samsung.com>
This patch adds the specific exynos_pm_data instance for Exynos5433
in order to support the suspend-to-ram. Exynos5433 SoC need to write
the 'cpu_resume' poiter address and the specific magic number
for suspend mode.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/soc/samsung/exynos-pm.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/soc/samsung/exynos-pm.c b/drivers/soc/samsung/exynos-pm.c
index 45d84bbe5e61..70d949ba5cab 100644
--- a/drivers/soc/samsung/exynos-pm.c
+++ b/drivers/soc/samsung/exynos-pm.c
@@ -12,6 +12,7 @@
#include <linux/regulator/machine.h>
#include <linux/syscore_ops.h>
#include <linux/suspend.h>
+#include <linux/psci.h>
#include <asm/cpuidle.h>
#include <asm/io.h>
@@ -123,7 +124,44 @@ static void exynos_pm_finish(void)
#define exynos_pm_data_arm_ptr(data) NULL
#endif
+static int exynos5433_pm_suspend(unsigned long unused)
+{
+ /*
+ * Exynos5433 uses PSCI v0.1 which provides the only one
+ * entry point (psci_ops.cpu_suspend) for both cpuidle and
+ * suspend-to-RAM. Also, PSCI v0.1 needs the specific 'power_state'
+ * parameter for the suspend mode. In order to enter suspend mode,
+ * Exynos5433 calls the 'psci_ops.cpu_suspend' with '0x3010000'
+ * power_state parameter.
+ *
+ * '0x3010000' means that both cluster and system are going to enter
+ * the power-down state as following:
+ * - [25:24] 0x3 : Indicate the cluster and system.
+ * - [16] 0x1 : Indicate power-down state.
+ */
+ return psci_ops.cpu_suspend(0x3010000, __pa_symbol(cpu_resume));
+}
+
+static int exynos5433_pm_suspend_enter(suspend_state_t state)
+{
+ if (!sysram_ns_base_addr)
+ return -EINVAL;
+
+ __raw_writel(virt_to_phys(cpu_resume), sysram_ns_base_addr + 0x8);
+ __raw_writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + 0xc);
+
+ return cpu_suspend(0, exynos5433_pm_suspend);
+}
+
+const struct exynos_pm_data exynos5433_pm_data = {
+ .enter = exynos5433_pm_suspend_enter,
+};
+
static const struct of_device_id exynos_pm_of_device_ids[] = {
+ {
+ .compatible = "samsung,exynos5433-pmu",
+ .data = exynos_pm_data_arm_ptr(exynos5433_pm_data),
+ },
{ /*sentinel*/ },
};
--
1.9.1
^ permalink raw reply related
* [PATCH 6/9] arm64: dts: exynos: Add iRAM device-tree node for Exynos5433
From: Chanwoo Choi @ 2018-01-09 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515484746-10656-1-git-send-email-cw00.choi@samsung.com>
This patch adds the iRAM device-tree node of Exynos5433 which
defines the memory map of iRAM as following and it is used for suspend.
- address: 0x0202_0000 ~ 0x3000_0000
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 62f276970174..77f4321b247c 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -262,6 +262,20 @@
interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
+ sysram at 02020000 {
+ compatible = "mmio-sram";
+ reg = <0x02020000 0x5c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x02020000 0x5c000>;
+ status = "okay";
+
+ smp-sysram at 5b000 {
+ compatible = "samsung,exynos4210-sysram-ns";
+ reg = <0x5b000 0x1000>;
+ };
+ };
+
chipid at 10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
--
1.9.1
^ permalink raw reply related
* [PATCH 7/9] arm64: dts: exynos: Use power key as a wakeup source on TM2/TM2E board
From: Chanwoo Choi @ 2018-01-09 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515484746-10656-1-git-send-email-cw00.choi@samsung.com>
This patch uses the power-key as a wakeup source from suspend/freeze state.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index a77462da4a36..26de0add1254 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -60,6 +60,7 @@
linux,code = <KEY_POWER>;
label = "power key";
debounce-interval = <10>;
+ wakeup-source;
};
volume-up-key {
--
1.9.1
^ permalink raw reply related
* [PATCH 8/9] arm64: dts: exynos: Add cpu_suspend property of PSCI for exynos5433
From: Chanwoo Choi @ 2018-01-09 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515484746-10656-1-git-send-email-cw00.choi@samsung.com>
The ARM64 Exynos5433 supports PSCI(Power State Coordinate Interface)[1] v0.1.
When PSCI v0.1 is used, the device-tree should contain the specific entry
point such as cpu_suspend. This patch adds the 'cpu_suspend' property
in order to support the cpuidle and suspend execution on Exynos5433 SoC.
The 'cpu_suspend' of psci is originally intended for use in idle subsystems.
Although the cpuidle and suspend-to-RAM framework have separate routine
in order to enter the low-power state, PSCI v0.1 doesn't support
the separate the entry point such as 'system_suspend' on PSCI v1.0.
So, the 'cpu_suspend' of PSCI v0.1 on Exynos5433 is used for both
cpuidle and suspend-to-RAM.
[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 77f4321b247c..0d99ded21202 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -227,6 +227,7 @@
psci {
compatible = "arm,psci";
method = "smc";
+ cpu_suspend = <0xc4000001>;
cpu_off = <0x84000002>;
cpu_on = <0xC4000003>;
};
--
1.9.1
^ permalink raw reply related
* [PATCH 9/9] arm64: dts: exynos: Add cpu topology information for Exynos5433 SoC
From: Chanwoo Choi @ 2018-01-09 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515484746-10656-1-git-send-email-cw00.choi@samsung.com>
This patch adds the 'cpu-map' for the cpu topology information
of Exynos5433 which has the following two clusters.
- cluster0 contains the four LITTLE cores (cpu0-3).
- cluster1 contains the four big cores (cpu4-7).
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 32 ++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0d99ded21202..ea54022f4f44 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -27,6 +27,38 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
cpu0: cpu at 100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
--
1.9.1
^ permalink raw reply related
* [PATCH v3 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
From: Jassi Brar @ 2018-01-09 8:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515109891-17133-3-git-send-email-jliang@xilinx.com>
On Fri, Jan 5, 2018 at 5:21 AM, Wendy Liang <wendy.liang@xilinx.com> wrote:
> Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
> in ZynqMP SoC used for the communication between various processor
> systems.
>
> Signed-off-by: Wendy Liang <jliang@xilinx.com>
> ---
> .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 104 +++++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
>
> diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
> new file mode 100644
> index 0000000..5e270a3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
> @@ -0,0 +1,104 @@
> +Xilinx IPI Mailbox Controller
> +========================================
> +
> +The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
> +messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
> +agent owns registers used for notification and buffers for message.
> +
> + +-------------------------------------+
> + | Xilinx ZynqMP IPI Controller |
> + +-------------------------------------+
> + +--------------------------------------------------+
> +ATF | |
> + | |
> + | |
> + +--------------------------+ |
> + | |
> + | |
> + +--------------------------------------------------+
> + +------------------------------------------+
> + | +----------------+ +----------------+ |
> +Hardware | | IPI Agent | | IPI Buffers | |
> + | | Registers | | | |
> + | | | | | |
> + | +----------------+ +----------------+ |
> + | |
> + | Xilinx IPI Agent Block |
> + +------------------------------------------+
> +
> +
> +Controller Device Node:
> +===========================
> +Required properties:
> +--------------------
> +- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
> +- reg: IPI buffers address ranges
> +- reg-names: Names of the reg resources. It should have:
> + * local_request_region
> + - IPI request msg buffer written by local and read
> + by remote
> + * local_response_region
> + - IPI response msg buffer written by local and read
> + by remote
> + * remote_request_region
> + - IPI request msg buffer written by remote and read
> + by local
> + * remote_response_region
> + - IPI response msg buffer written by remote and read
> + by local
>
shmem is option and external to the controller. It should be passed
via client's binding.
Please have a look at Sudeep's proposed patch
https://www.spinics.net/lists/arm-kernel/msg626120.html
> +- #mbox-cells: Shall be 1. It contains:
> + * tx(0) or rx(1) channel
> +- xlnx,ipi-ids: Xilinx IPI agent IDs of the two peers of the
> + Xilinx IPI communication channel.
> +- interrupt-parent: Phandle for the interrupt controller
> +- interrupts: Interrupt information corresponding to the
> + interrupt-names property.
> +
> +Optional properties:
> +--------------------
> +- method: The method of accessing the IPI agent registers.
> + Permitted values are: "smc" and "hvc". Default is
> + "smc".
> +
Andre almost implemented the generic driver. Can you please have a
look at https://www.spinics.net/lists/arm-kernel/msg595416.html
and see if you can just finish it off?
Thanks
^ permalink raw reply
* [PATCH v3 0/6] arm: sunxi: IR support for A83T
From: Philipp Rossak @ 2018-01-09 8:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180105145913.ddb5l5dyt7yn3kwc@flea.lan>
On 05.01.2018 15:59, Maxime Ripard wrote:
> Hi,
>
> On Fri, Jan 05, 2018 at 12:02:53PM +0000, Sean Young wrote:
>> On Tue, Dec 19, 2017 at 09:07:41AM +0100, Philipp Rossak wrote:
>>> This patch series adds support for the sunxi A83T ir module and enhances
>>> the sunxi-ir driver. Right now the base clock frequency for the ir driver
>>> is a hard coded define and is set to 8 MHz.
>>> This works for the most common ir receivers. On the Sinovoip Bananapi M3
>>> the ir receiver needs, a 3 MHz base clock frequency to work without
>>> problems with this driver.
>>>
>>> This patch series adds support for an optinal property that makes it able
>>> to override the default base clock frequency and enables the ir interface
>>> on the a83t and the Bananapi M3.
>>>
>>> changes since v2:
>>> * reorder cir pin (alphabetical)
>>> * fix typo in documentation
>>>
>>> changes since v1:
>>> * fix typos, reword Documentation
>>> * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement
>>> * change dev_info() to dev_dbg()
>>> * change naming to cir* in dts/dtsi
>>> * Added acked Ackedi-by to related patch
>>> * use whole memory block instead of registers needed + fix for h3/h5
>>>
>>> changes since rfc:
>>> * The property is now optinal. If the property is not available in
>>> the dtb the driver uses the default base clock frequency.
>>> * the driver prints out the the selected base clock frequency.
>>> * changed devicetree property from base-clk-frequency to clock-frequency
>>>
>>> Regards,
>>> Philipp
>>>
>>>
>>> Philipp Rossak (6):
>>> media: rc: update sunxi-ir driver to get base clock frequency from
>>> devicetree
>>> media: dt: bindings: Update binding documentation for sunxi IR
>>> controller
>>> arm: dts: sun8i: a83t: Add the cir pin for the A83T
>>> arm: dts: sun8i: a83t: Add support for the cir interface
>>> arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
>>> arm: dts: sun8i: h3-h8: ir register size should be the whole memory
>>> block
>>
>> I can take this series (through rc-core, i.e. linux-media), but I need an
>> maintainer Acked-by: for the sun[x8]i dts changes (all four patches).
>
> We'll merge them through our tree. We usually have a rather big number
> of patches around, so we'd be better off avoiding conflicts :)
>
> Philipp, can you resubmit the DTs as soon as -rc1 is out?
>
> Thanks!
> Maxime
>
Yes, I can do this!
Regards,
Philipp
^ permalink raw reply
* [PATCH v2 2/2] arm64: Implement branch predictor hardening for Falkor
From: Ard Biesheuvel @ 2018-01-09 8:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515447068-20977-2-git-send-email-shankerd@codeaurora.org>
On 8 January 2018 at 21:31, Shanker Donthineni <shankerd@codeaurora.org> wrote:
> Falkor is susceptible to branch predictor aliasing and can
> theoretically be attacked by malicious code. This patch
> implements a mitigation for these attacks, preventing any
> malicious entries from affecting other victim contexts.
>
> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> ---
> Changes since v1:
> Corrected typo to fix the compilation errors if HARDEN_BRANCH_PREDICTOR=n
>
> This patch requires FALKOR MIDR which is available in upstream v4.15-rc7
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm64?h=v4.15-rc7&id=c622cc013cece073722592cff1ac6643a33b1622 ans also
> attached this v2 patch series.
>
> arch/arm64/include/asm/cpucaps.h | 3 ++-
> arch/arm64/include/asm/kvm_asm.h | 2 ++
> arch/arm64/kernel/bpi.S | 8 +++++++
> arch/arm64/kernel/cpu_errata.c | 49 ++++++++++++++++++++++++++++++++++++++--
> arch/arm64/kvm/hyp/entry.S | 12 ++++++++++
> arch/arm64/kvm/hyp/switch.c | 10 ++++++++
> 6 files changed, 81 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
> index 51616e7..7049b48 100644
> --- a/arch/arm64/include/asm/cpucaps.h
> +++ b/arch/arm64/include/asm/cpucaps.h
> @@ -43,7 +43,8 @@
> #define ARM64_SVE 22
> #define ARM64_UNMAP_KERNEL_AT_EL0 23
> #define ARM64_HARDEN_BRANCH_PREDICTOR 24
> +#define ARM64_HARDEN_BP_POST_GUEST_EXIT 25
>
> -#define ARM64_NCAPS 25
> +#define ARM64_NCAPS 26
>
> #endif /* __ASM_CPUCAPS_H */
> diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
> index ab4d0a9..24961b7 100644
> --- a/arch/arm64/include/asm/kvm_asm.h
> +++ b/arch/arm64/include/asm/kvm_asm.h
> @@ -68,6 +68,8 @@
>
> extern u32 __init_stage2_translation(void);
>
> +extern void __qcom_hyp_sanitize_btac_predictors(void);
> +
> #endif
>
> #endif /* __ARM_KVM_ASM_H__ */
> diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S
> index 2b10d52..44ffcda 100644
> --- a/arch/arm64/kernel/bpi.S
> +++ b/arch/arm64/kernel/bpi.S
> @@ -77,3 +77,11 @@ ENTRY(__psci_hyp_bp_inval_start)
> ldp x2, x3, [sp], #16
> ldp x0, x1, [sp], #16
> ENTRY(__psci_hyp_bp_inval_end)
> +
> +ENTRY(__qcom_hyp_sanitize_link_stack_start)
> + stp x29, x30, [sp, #-16]!
> + .rept 16
> + bl . + 4
> + .endr
> + ldp x29, x30, [sp], #16
> +ENTRY(__qcom_hyp_sanitize_link_stack_end)
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index cb0fb37..9ee9d2e 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -54,6 +54,8 @@ static int cpu_enable_trap_ctr_access(void *__unused)
>
> #ifdef CONFIG_KVM
> extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[];
> +extern char __qcom_hyp_sanitize_link_stack_start[];
> +extern char __qcom_hyp_sanitize_link_stack_end[];
>
> static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
> const char *hyp_vecs_end)
> @@ -96,8 +98,10 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
> spin_unlock(&bp_lock);
> }
> #else
> -#define __psci_hyp_bp_inval_start NULL
> -#define __psci_hyp_bp_inval_end NULL
> +#define __psci_hyp_bp_inval_start NULL
> +#define __psci_hyp_bp_inval_end NULL
> +#define __qcom_hyp_sanitize_link_stack_start NULL
> +#define __qcom_hyp_sanitize_link_stack_end NULL
>
> static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
> const char *hyp_vecs_start,
> @@ -138,6 +142,29 @@ static int enable_psci_bp_hardening(void *data)
>
> return 0;
> }
> +
> +static void qcom_link_stack_sanitization(void)
> +{
> + u64 tmp;
> +
> + asm volatile("mov %0, x30 \n"
> + ".rept 16 \n"
> + "bl . + 4 \n"
> + ".endr \n"
> + "mov x30, %0 \n"
> + : "=&r" (tmp));
> +}
> +
Couldn't you just add x30 to the clobber list here?
> +static int qcom_enable_link_stack_sanitization(void *data)
> +{
> + const struct arm64_cpu_capabilities *entry = data;
> +
> + install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
> + __qcom_hyp_sanitize_link_stack_start,
> + __qcom_hyp_sanitize_link_stack_end);
> +
> + return 0;
> +}
> #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
>
> #define MIDR_RANGE(model, min, max) \
> @@ -302,6 +329,24 @@ static int enable_psci_bp_hardening(void *data)
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
> .enable = enable_psci_bp_hardening,
> },
> + {
> + .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
> + MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
> + .enable = qcom_enable_link_stack_sanitization,
> + },
> + {
> + .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
> + MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
> + .enable = qcom_enable_link_stack_sanitization,
> + },
> + {
> + .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
> + MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
> + },
> + {
> + .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
> + MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
> + },
> #endif
> {
> }
> diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S
> index 12ee62d..9c45c6a 100644
> --- a/arch/arm64/kvm/hyp/entry.S
> +++ b/arch/arm64/kvm/hyp/entry.S
> @@ -196,3 +196,15 @@ alternative_endif
>
> eret
> ENDPROC(__fpsimd_guest_restore)
> +
> +ENTRY(__qcom_hyp_sanitize_btac_predictors)
> + /**
> + * Call SMC64 with Silicon provider serviceID 23<<8 (0xc2001700)
> + * 0xC2000000-0xC200FFFF: assigned to SiP Service Calls
> + * b15-b0: contains SiP functionID
> + */
> + movz x0, #0x1700
> + movk x0, #0xc200, lsl #16
> + smc #0
> + ret
> +ENDPROC(__qcom_hyp_sanitize_btac_predictors)
> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> index 4d273f6..7e37379 100644
> --- a/arch/arm64/kvm/hyp/switch.c
> +++ b/arch/arm64/kvm/hyp/switch.c
> @@ -406,6 +406,16 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
> /* 0 falls through to be handled out of EL2 */
> }
>
> + if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT)) {
> + u32 midr = read_cpuid_id();
> +
> + /* Apply BTAC predictors mitigation to all Falkor chips */
> + if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
> + ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) {
> + __qcom_hyp_sanitize_btac_predictors();
> + }
> + }
> +
> fp_enabled = __fpsimd_enabled();
>
> __sysreg_save_guest_state(guest_ctxt);
> --
> Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
> Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] ARM: imx: Improve the soc revision calculation flow
From: Bai Ping @ 2018-01-09 8:30 UTC (permalink / raw)
To: linux-arm-kernel
On our i.MX6 SOC, the DIGPROG register is used for representing the
SOC ID and silicon revision. The revision has two part: MAJOR and
MINOR. each is represented in 8 bits in the register.
bits [15:8]: reflect the MAJOR part of the revision;
bits [7:0]: reflect the MINOR part of the revision;
In our linux kernel, the soc revision is represented in 8 bits.
MAJOR part and MINOR each occupy 4 bits.
previous method does NOT take care about the MAJOR part in DIGPROG
register. So reformat the revision read from the HW to be compatible
with the revision format used in kernel.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
arch/arm/mach-imx/anatop.c | 58 +++++++++++++++++-----------------------------
1 file changed, 21 insertions(+), 37 deletions(-)
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 649a84c..170cb30 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright NXP 2017.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@@ -116,6 +117,8 @@ void __init imx_init_revision_from_anatop(void)
unsigned int revision;
u32 digprog;
u16 offset = ANADIG_DIGPROG;
+ u16 major_part, minor_part;
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
anatop_base = of_iomap(np, 0);
@@ -127,45 +130,26 @@ void __init imx_init_revision_from_anatop(void)
digprog = readl_relaxed(anatop_base + offset);
iounmap(anatop_base);
- switch (digprog & 0xff) {
- case 0:
- /*
- * For i.MX6QP, most of the code for i.MX6Q can be resued,
- * so internally, we identify it as i.MX6Q Rev 2.0
- */
- if (digprog >> 8 & 0x01)
- revision = IMX_CHIP_REVISION_2_0;
- else
- revision = IMX_CHIP_REVISION_1_0;
- break;
- case 1:
- revision = IMX_CHIP_REVISION_1_1;
- break;
- case 2:
- revision = IMX_CHIP_REVISION_1_2;
- break;
- case 3:
- revision = IMX_CHIP_REVISION_1_3;
- break;
- case 4:
- revision = IMX_CHIP_REVISION_1_4;
- break;
- case 5:
- /*
- * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
- * as 'D' in Part Number last character.
- */
- revision = IMX_CHIP_REVISION_1_5;
- break;
- default:
- /*
- * Fail back to return raw register value instead of 0xff.
- * It will be easy to know version information in SOC if it
- * can't be recognized by known version. And some chip's (i.MX7D)
- * digprog value match linux version format, so it needn't map
- * again and we can use register value directly.
+ /*
+ * On i.MX7D digprog value match linux version format, so
+ * it needn't map again and we can use register value directly.
+ */
+ if (of_device_is_compatible(np, "fsl,imx7d-anatop")) {
+ revision = digprog & 0xff;
+ } else {
+
+ /* MAJOR: [15:8], the major silicon revison;
+ * MINOR: [7: 0], the minor silicon revison;
+ *
+ * please refer to the i.MX RM for the detailed
+ * silicon revison bit define.
+ * format the major part and minor part to match the
+ * linux kernel soc version format.
*/
revision = digprog & 0xff;
+ major_part = (digprog >> 8) & 0xf;
+ minor_part = digprog & 0xf;
+ revision = ((major_part + 1) << 4) | minor_part;
}
mxc_set_cpu_type(digprog >> 16 & 0xff);
--
1.9.1
^ permalink raw reply related
* Hang loading omap_rng on MacchiatoBin with 4.15-rc7
From: Riku Voipio @ 2018-01-09 8:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Loading omap_rng module on McBin causes hangup (in about 9/10 times).
Looking at /proc/interrupts it seems the interrupt starts running like
crazy, and after a while the whole system is unresponsive. This with
Debian kernel (everything possible as modules) and EFI as bootloader.
The EFI firmware appears[1] to use the rng unit to provide a seed for
KASRL, I wonder if the driver needs to depend less on the state left
by firmware, or the firmware needs to de-initialize the RNG before
booting.
root at debian:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
1: 0 0 0 0 GICv2 25 Level vgic
3: 1268 1983 1175 1139 GICv2 30 Level
arch_timer
4: 0 0 0 0 GICv2 27 Level
kvm guest timer
7: 1956 0 0 0 GICv2 51 Level ttyS0
9: 4472 0 307 0 GICv2 48 Level mmc0
18: 0 0 0 0 pMSI 4096 Edge
f0400000.xor
19: 0 0 0 0 pMSI 6144 Edge
f0420000.xor
20: 0 0 0 0 pMSI 8192 Edge
f0440000.xor
21: 0 0 0 0 pMSI 10240 Edge
f0460000.xor
22: 0 0 0 0 pMSI 12288 Edge
f26a0000.xor
23: 0 0 0 0 pMSI 14336 Edge
f26c0000.xor
24: 0 0 0 0 pMSI 16384 Edge
f46a0000.xor
25: 0 0 0 0 pMSI 18432 Edge
f46c0000.xor
26: 0 0 0 0
f03f0100.interrupt-controller 17 Level arm-pmu
27: 0 0 0 0 ICU.f21e0000 22
Level armada8k-pcie, PCIe PME, aerdrv
72: 13 0 0 0 ICU.f41e0000 40
Level eth2
73: 0 10 0 0 ICU.f41e0000 44
Level eth2
74: 0 0 29 0 ICU.f41e0000 48
Level eth2
75: 0 0 0 45 ICU.f41e0000 52
Level eth2
76: 36 0 0 55 ICU.f41e0000 56
Level eth2
78: 440 0 42 0 ICU.f21e0000 27
Level mmc1
79: 0 0 0 0 ICU.f41e0000 77
Level f4284000.rtc
80: 0 0 0 0 ICU.f21e0000 120
Level mv64xxx_i2c
81: 0 0 0 0 ICU.f21e0000 121
Level mv64xxx_i2c
82: 0 0 0 0 ICU.f21e0000 106
Level xhci-hcd:usb1
83: 0 0 0 0 ICU.f21e0000 105
Level xhci-hcd:usb3
84: 0 0 0 0 ICU.f41e0000 106
Level xhci-hcd:usb5
85: 0 0 0 0 ICU.f21e0000 107
Level ahci[f2540000.sata]
86: 268 0 0 0 ICU.f41e0000 107
Level ahci[f4540000.sata]
IPI0: 2254 2458 1876 1844 Rescheduling interrupts
IPI1: 110 107 299 165 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 0 0 0 0 CPU stop (for
crash dump) interrupts
IPI4: 0 0 0 0 Timer broadcast
interrupts
IPI5: 1 0 0 0 IRQ work interrupts
IPI6: 0 0 0 0 CPU wake-up interrupts
Err: 0
root at debian:~# modprobe omap_rng
root at debian:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
1: 0 0 0 0 GICv2 25 Level vgic
3: 1795 2736 1663 1620 GICv2 30 Level
arch_timer
4: 0 0 0 0 GICv2 27 Level
kvm guest timer
7: 2183 0 0 0 GICv2 51 Level ttyS0
9: 4472 0 1759 0 GICv2 48 Level mmc0
18: 0 0 0 0 pMSI 4096 Edge
f0400000.xor
19: 0 0 0 0 pMSI 6144 Edge
f0420000.xor
20: 0 0 0 0 pMSI 8192 Edge
f0440000.xor
21: 0 0 0 0 pMSI 10240 Edge
f0460000.xor
22: 0 0 0 0 pMSI 12288 Edge
f26a0000.xor
23: 0 0 0 0 pMSI 14336 Edge
f26c0000.xor
24: 0 0 0 0 pMSI 16384 Edge
f46a0000.xor
25: 0 0 0 0 pMSI 18432 Edge
f46c0000.xor
26: 0 0 0 0
f03f0100.interrupt-controller 17 Level arm-pmu
27: 0 0 0 0 ICU.f21e0000 22
Level armada8k-pcie, PCIe PME, aerdrv
72: 15 0 0 0 ICU.f41e0000 40
Level eth2
73: 0 11 0 0 ICU.f41e0000 44
Level eth2
74: 0 0 37 0 ICU.f41e0000 48
Level eth2
75: 0 0 0 68 ICU.f41e0000 52
Level eth2
76: 36 0 0 118 ICU.f41e0000 56
Level eth2
78: 440 0 68 0 ICU.f21e0000 27
Level mmc1
79: 0 0 0 0 ICU.f41e0000 77
Level f4284000.rtc
80: 0 0 0 0 ICU.f21e0000 120
Level mv64xxx_i2c
81: 0 0 0 0 ICU.f21e0000 121
Level mv64xxx_i2c
82: 0 0 0 0 ICU.f21e0000 106
Level xhci-hcd:usb1
83: 0 0 0 0 ICU.f21e0000 105
Level xhci-hcd:usb3
84: 0 0 0 0 ICU.f41e0000 106
Level xhci-hcd:usb5
85: 0 0 0 0 ICU.f21e0000 107
Level ahci[f2540000.sata]
86: 268 0 0 0 ICU.f41e0000 107
Level ahci[f4540000.sata]
87: 0 0 0 0 ICU.f21e0000 95
Level f2760000.trng
88: 889660 0 0 0 ICU.f41e0000 95
Level f4760000.trng
IPI0: 2964 2559 2607 1957 Rescheduling interrupts
IPI1: 110 107 299 165 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 0 0 0 0 CPU stop (for
crash dump) interrupts
IPI4: 0 0 0 0 Timer broadcast
interrupts
IPI5: 1 0 0 0 IRQ work interrupts
IPI6: 0 0 0 0 CPU wake-up interrupts
Err: 0
root at debian:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
1: 0 0 0 0 GICv2 25 Level vgic
3: 2538 3498 2407 2364 GICv2 30 Level
arch_timer
4: 0 0 0 0 GICv2 27 Level
kvm guest timer
7: 2625 0 0 0 GICv2 51 Level ttyS0
9: 4472 0 1768 0 GICv2 48 Level mmc0
18: 0 0 0 0 pMSI 4096 Edge
f0400000.xor
19: 0 0 0 0 pMSI 6144 Edge
f0420000.xor
20: 0 0 0 0 pMSI 8192 Edge
f0440000.xor
21: 0 0 0 0 pMSI 10240 Edge
f0460000.xor
22: 0 0 0 0 pMSI 12288 Edge
f26a0000.xor
23: 0 0 0 0 pMSI 14336 Edge
f26c0000.xor
24: 0 0 0 0 pMSI 16384 Edge
f46a0000.xor
25: 0 0 0 0 pMSI 18432 Edge
f46c0000.xor
26: 0 0 0 0
f03f0100.interrupt-controller 17 Level arm-pmu
27: 0 0 0 0 ICU.f21e0000 22
Level armada8k-pcie, PCIe PME, aerdrv
72: 15 0 0 0 ICU.f41e0000 40
Level eth2
73: 0 11 0 0 ICU.f41e0000 44
Level eth2
74: 0 0 37 0 ICU.f41e0000 48
Level eth2
75: 0 0 0 68 ICU.f41e0000 52
Level eth2
76: 36 0 0 118 ICU.f41e0000 56
Level eth2
78: 440 0 71 0 ICU.f21e0000 27
Level mmc1
79: 0 0 0 0 ICU.f41e0000 77
Level f4284000.rtc
80: 0 0 0 0 ICU.f21e0000 120
Level mv64xxx_i2c
81: 0 0 0 0 ICU.f21e0000 121
Level mv64xxx_i2c
82: 0 0 0 0 ICU.f21e0000 106
Level xhci-hcd:usb1
83: 0 0 0 0 ICU.f21e0000 105
Level xhci-hcd:usb3
84: 0 0 0 0 ICU.f41e0000 106
Level xhci-hcd:usb5
85: 0 0 0 0 ICU.f21e0000 107
Level ahci[f2540000.sata]
86: 268 0 0 0 ICU.f41e0000 107
Level ahci[f4540000.sata]
87: 0 0 0 0 ICU.f21e0000 95
Level f2760000.trng
88: 2532580 0 0 0 ICU.f41e0000 95
Level f4760000.trng
IPI0: 2964 2562 2640 2001 Rescheduling interrupts
IPI1: 110 107 299 165 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 0 0 0 0 CPU stop (for
crash dump) interrupts
IPI4: 0 0 0 0 Timer broadcast
interrupts
IPI5: 1 0 0 0 IRQ work interrupts
IPI6: 0 0 0 0 CPU wake-up interrupts
[1] https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commit/4a0d8a37247b0da45baf37e1f207ae8737c7254b
Full kernel log:
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd081]
[ 0.000000] Linux version 4.15.0-rc7-arm64
(debian-kernel at lists.debian.org) (gcc version 7.2.0 (Debian 7.2.0-11))
#1 SMP Debian 4.15~rc7-1~exp1 (2018-01-08)
[ 0.000000] Machine model: Marvell 8040 MACHIATOBin
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: EFI v2.60 by EDK II
[ 0.000000] efi: SMBIOS 3.0=0xbfd00000 ACPI 2.0=0xb6760000
MEMATTR=0xb8862018 RNG=0xbffdbf98
[ 0.000000] random: fast init done
[ 0.000000] efi: seeding entropy pool
[ 0.000000] cma: Reserved 64 MiB at 0x00000000bb800000
[ 0.000000] NUMA: No NUMA configuration found
[ 0.000000] NUMA: Faking a node at [mem
0x0000000000000000-0x000000013fffffff]
[ 0.000000] NUMA: NODE_DATA [mem 0x13ffd3980-0x13ffd547f]
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000000000000-0x00000000ffffffff]
[ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000000000-0x0000000003ffffff]
[ 0.000000] node 0: [mem 0x0000000004200000-0x00000000bf80ffff]
[ 0.000000] node 0: [mem 0x00000000bf810000-0x00000000bfbeffff]
[ 0.000000] node 0: [mem 0x00000000bfbf0000-0x00000000bfc8ffff]
[ 0.000000] node 0: [mem 0x00000000bfc90000-0x00000000bffdffff]
[ 0.000000] node 0: [mem 0x00000000bffe0000-0x00000000bfffffff]
[ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000013fffffff]
[ 0.000000] On node 0 totalpages: 1048064
[ 0.000000] DMA zone: 12280 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 785920 pages, LIFO batch:31
[ 0.000000] Normal zone: 4096 pages used for memmap
[ 0.000000] Normal zone: 262144 pages, LIFO batch:31
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.0 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] percpu: Embedded 24 pages/cpu @ (ptrval) s58904
r8192 d31208 u98304
[ 0.000000] pcpu-alloc: s58904 r8192 d31208 u98304 alloc=24*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[ 0.000000] Detected PIPT I-cache on CPU0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031688
[ 0.000000] Policy zone: Normal
[ 0.000000] Kernel command line:
BOOT_IMAGE=/boot/vmlinuz-4.15.0-rc7-arm64
root=UUID=eac7cb10-f190-4ade-bf79-d1a979e18e8b ro quiet
[ 0.000000] software IO TLB [mem 0xb2700000-0xb6700000] (64MB)
mapped at [ (ptrval)- (ptrval)]
[ 0.000000] Memory: 3948596K/4192256K available (8316K kernel code,
1436K rwdata, 2748K rodata, 4480K init, 600K bss, 178124K reserved,
6553
6K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] modules : 0xffff000000000000 - 0xffff000008000000
( 128 MB)
[ 0.000000] vmalloc : 0xffff000008000000 - 0xffff7dffbfff0000
(129022 GB)
[ 0.000000] .text : 0x (ptrval) - 0x (ptrval)
( 8320 KB)
[ 0.000000] .rodata : 0x (ptrval) - 0x (ptrval)
( 2816 KB)
[ 0.000000] .init : 0x (ptrval) - 0x (ptrval)
( 4480 KB)
[ 0.000000] .data : 0x (ptrval) - 0x (ptrval)
( 1437 KB)
[ 0.000000] .bss : 0x (ptrval) - 0x (ptrval)
( 601 KB)
[ 0.000000] fixed : 0xffff7dfffe7fd000 - 0xffff7dfffec00000
( 4108 KB)
[ 0.000000] PCI I/O : 0xffff7dfffee00000 - 0xffff7dffffe00000
( 16 MB)
[ 0.000000] vmemmap : 0xffff7e0000000000 - 0xffff800000000000
( 2048 GB maximum)
[ 0.000000] 0xffff7f7ac9000000 - 0xffff7f7ace000000
( 80 MB actual)
[ 0.000000] memory : 0xffffdeb240000000 - 0xffffdeb380000000
( 5120 MB)
[ 0.000000] ftrace: allocating 31174 entries in 122 pages
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f022f000
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] GICv2m: DT overriding V2M MSI_TYPER (base:160, num:32)
[ 0.000000] GICv2m: range[mem 0xf0280000-0xf0280fff], SPI[160:191]
[ 0.000000] GICv2m: DT overriding V2M MSI_TYPER (base:192, num:32)
[ 0.000000] GICv2m: range[mem 0xf0290000-0xf0290fff], SPI[192:223]
[ 0.000000] GICv2m: DT overriding V2M MSI_TYPER (base:224, num:32)
[ 0.000000] GICv2m: range[mem 0xf02a0000-0xf02a0fff], SPI[224:255]
[ 0.000000] GICv2m: DT overriding V2M MSI_TYPER (base:256, num:32)
[ 0.000000] GICv2m: range[mem 0xf02b0000-0xf02b0fff], SPI[256:287]
[ 0.000000] arch_timer: cp15 timer(s) running at 25.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff
max_cycles: 0x5c40939b5, max_idle_ns: 440795202646 ns
[ 0.000002] sched_clock: 56 bits at 25MHz, resolution 40ns, wraps
every 4398046511100ns
[ 0.000320] Console: colour dummy device 80x25
[ 0.000329] console [tty0] enabled
[ 0.000367] Calibrating delay loop (skipped), value calculated
using timer frequency.. 50.00 BogoMIPS (lpj=100000)
[ 0.000373] pid_max: default: 32768 minimum: 301
[ 0.000455] Security Framework initialized
[ 0.000460] Yama: disabled by default; enable with sysctl kernel.yama.*
[ 0.000502] AppArmor: AppArmor initialized
[ 0.001673] Dentry cache hash table entries: 524288 (order: 10,
4194304 bytes)
[ 0.002270] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.002318] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.002341] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.003051] ASID allocator initialised with 65536 entries
[ 0.003095] Hierarchical SRCU implementation.
[ 0.004111] Remapping and enabling EFI services.
[ 0.004215] EFI remap 0x00000000bf810000 => (ptrval)
[ 0.004292] EFI remap 0x00000000bfc90000 => (ptrval)
[ 0.004296] EFI remap 0x00000000f4284000 => (ptrval)
[ 0.004299] EFI remap 0x00000000f4700000 => (ptrval)
[ 0.004306] EFI remap 0x00000000f93c0000 => (ptrval)
[ 0.004610] smp: Bringing up secondary CPUs ...
[ 0.005038] Detected PIPT I-cache on CPU1
[ 0.005078] CPU1: Booted secondary processor 0x0000000001 [0x410fd081]
[ 0.005532] Detected PIPT I-cache on CPU2
[ 0.005562] CPU2: Booted secondary processor 0x0000000100 [0x410fd081]
[ 0.006013] Detected PIPT I-cache on CPU3
[ 0.006033] CPU3: Booted secondary processor 0x0000000101 [0x410fd081]
[ 0.006084] smp: Brought up 1 node, 4 CPUs
[ 0.006088] SMP: Total of 4 processors activated.
[ 0.006092] CPU features: detected feature: 32-bit EL0 Support
[ 0.006378] CPU: All CPU(s) started at EL2
[ 0.007024] devtmpfs: initialized
[ 0.009286] Registered cp15_barrier emulation handler
[ 0.009294] Registered setend emulation handler
[ 0.009408] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.009435] futex hash table entries: 1024 (order: 5, 131072 bytes)
[ 0.010231] pinctrl core: initialized pinctrl subsystem
[ 0.010660] SMBIOS 3.0.0 present.
[ 0.010671] DMI: Marvell Armada 8040 MacchiatoBin/Armada 8040
MacchiatoBin, BIOS EDK II Dec 12 2017
[ 0.010837] NET: Registered protocol family 16
[ 0.010997] audit: initializing netlink subsys (disabled)
[ 0.011098] audit: type=2000 audit(0.008:1): state=initialized
audit_enabled=0 res=1
[ 0.011559] cpuidle: using governor ladder
[ 0.011633] cpuidle: using governor menu
[ 0.011803] vdso: 2 pages (1 code @ 0000000000e7c779, 1 data @
000000009a994fe8)
[ 0.011812] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.012428] DMA: preallocated 256 KiB pool for atomic allocations
[ 0.012528] Serial: AMBA PL011 UART driver
[ 0.019355] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.019916] ACPI: Interpreter disabled.
[ 0.020101] vgaarb: loaded
[ 0.020268] EDAC MC: Ver: 3.0.0
[ 0.020437] Registered efivars operations
[ 0.023923] clocksource: Switched to clocksource arch_sys_counter
[ 0.048986] VFS: Disk quotas dquot_6.6.0
[ 0.049027] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 0.049295] AppArmor: AppArmor Filesystem Enabled
[ 0.049454] pnp: PnP ACPI: disabled
[ 0.053211] NET: Registered protocol family 2
[ 0.053536] TCP established hash table entries: 32768 (order: 6,
262144 bytes)
[ 0.053685] TCP bind hash table entries: 32768 (order: 7, 524288 bytes)
[ 0.053910] TCP: Hash tables configured (established 32768 bind 32768)
[ 0.053982] UDP hash table entries: 2048 (order: 4, 65536 bytes)
[ 0.054008] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
[ 0.054127] NET: Registered protocol family 1
[ 0.054142] PCI: CLS 0 bytes, default 128
[ 0.054241] Unpacking initramfs...
[ 0.677482] Freeing initrd memory: 18500K
[ 0.677789] hw perfevents: unable to count PMU IRQs
[ 0.677803] hw perfevents: /ap806/config-space at f0000000/pmu: failed
to register PMU devices!
[ 0.677970] kvm [1]: 8-bit VMID
[ 0.677973] kvm [1]: IDMAP page: 51c54000
[ 0.677975] kvm [1]: HYP VA range: 800000000000:ffffffffffff
[ 0.678466] kvm [1]: vgic-v2 at f0240000
[ 0.678537] kvm [1]: vgic interrupt IRQ1
[ 0.678546] kvm [1]: virtual timer IRQ4
[ 0.678607] kvm [1]: Hyp mode initialized successfully
[ 0.679727] Initialise system trusted keyrings
[ 0.679801] workingset: timestamp_bits=44 max_order=20 bucket_order=0
[ 0.679880] zbud: loaded
[ 1.334003] Key type asymmetric registered
[ 1.334007] Asymmetric key parser 'x509' registered
[ 1.334050] Block layer SCSI generic (bsg) driver version 0.4
loaded (major 246)
[ 1.334123] io scheduler noop registered
[ 1.334125] io scheduler deadline registered
[ 1.334154] io scheduler cfq registered (default)
[ 1.334156] io scheduler mq-deadline registered
[ 1.335649] armada-ap806-pinctrl
f06f4000.system-controller:pinctrl: registered pinctrl driver
[ 1.336054] armada-cp110-pinctrl
f2440000.system-controller:pinctrl: registered pinctrl driver
[ 1.336335] armada-cp110-pinctrl
f4440000.system-controller:pinctrl: registered pinctrl driver
[ 1.340941] mv_xor_v2 f0400000.xor: Marvell Version 2 XOR driver
[ 1.341186] mv_xor_v2 f0420000.xor: Marvell Version 2 XOR driver
[ 1.341461] mv_xor_v2 f0440000.xor: Marvell Version 2 XOR driver
[ 1.341702] mv_xor_v2 f0460000.xor: Marvell Version 2 XOR driver
[ 1.342010] mv_xor_v2 f26a0000.xor: Marvell Version 2 XOR driver
[ 1.342263] mv_xor_v2 f26c0000.xor: Marvell Version 2 XOR driver
[ 1.342652] mv_xor_v2 f46a0000.xor: Marvell Version 2 XOR driver
[ 1.342914] mv_xor_v2 f46c0000.xor: Marvell Version 2 XOR driver
[ 1.343757] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 1.364902] f0512000.serial: ttyS0 at MMIO 0xf0512000 (irq = 7,
base_baud = 12500000) is a 16550A
[ 1.369854] console [ttyS0] enabled
[ 1.370155] Serial: AMBA driver
[ 1.370306] msm_serial: driver initialized
[ 1.370630] cacheinfo: Unable to detect cache hierarchy for CPU 0
[ 1.370882] mousedev: PS/2 mouse device common for all mice
[ 1.371155] rtc-efi rtc-efi: rtc core: registered rtc-efi as rtc0
[ 1.371854] ledtrig-cpu: registered to indicate activity on CPUs
[ 1.372409] NET: Registered protocol family 10
[ 1.372782] Segment Routing with IPv6
[ 1.372812] mip6: Mobile IPv6
[ 1.372817] NET: Registered protocol family 17
[ 1.372822] mpls_gso: MPLS GSO support
[ 1.373117] registered taskstats version 1
[ 1.373120] Loading compiled-in X.509 certificates
[ 1.456522] Loaded X.509 cert 'Debian Project: Ben Hutchings:
008a018dca80932630'
[ 1.456573] zswap: loaded using pool lzo/zbud
[ 1.456649] AppArmor: AppArmor sha1 policy hashing enabled
[ 1.456655] ima: No TPM chip found, activating TPM-bypass! (rc=-19)
[ 1.458339] hw perfevents: enabled with armv8_cortex_a72 PMU
driver, 7 counters available
[ 1.458570] OF: PCI: host bridge /cp110-master/pcie at f2600000 ranges:
[ 1.458584] OF: PCI: IO 0xf9000000..0xf900ffff -> 0xf9000000
[ 1.458592] OF: PCI: MEM 0xf6000000..0xf6efffff -> 0xf6000000
[ 2.459125] armada8k-pcie f2600000.pcie: phy link never came up
[ 2.465091] armada8k-pcie f2600000.pcie: Link not up after reconfiguration
[ 2.472079] armada8k-pcie f2600000.pcie: PCI host bridge to bus 0000:00
[ 2.472085] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 2.472090] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
(bus address [0xf9000000-0xf900ffff])
[ 2.472094] pci_bus 0000:00: root bus resource [mem 0xf6000000-0xf6efffff]
[ 2.472113] pci 0000:00:00.0: [11ab:0110] type 01 class 0x060400
[ 2.472138] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit]
[ 2.472192] pci 0000:00:00.0: supports D1 D2
[ 2.472195] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[ 2.472307] pci 0000:00:00.0: bridge configuration invalid ([bus
00-00]), reconfiguring
[ 2.472365] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 2.472383] pci 0000:00:00.0: BAR 0: assigned [mem
0xf6000000-0xf60fffff 64bit]
[ 2.472393] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 2.779832] pcieport 0000:00:00.0: Signaling PME with IRQ 27
[ 2.779895] pcieport 0000:00:00.0: AER enabled with IRQ 27
[ 2.780028] rtc-efi rtc-efi: setting system clock to 2018-05-19
00:53:40 UTC (1526691220)
[ 2.787233] Freeing unused kernel memory: 4480K
[ 2.910988] libphy: Fixed MDIO Bus: probed
[ 2.915788] sdhci: Secure Digital Host Controller Interface driver
[ 2.915792] sdhci: Copyright(c) Pierre Ossman
[ 2.916452] sdhci-pltfm: SDHCI platform and OF driver helper
[ 2.927389] usbcore: registered new interface driver usbfs
[ 2.927421] usbcore: registered new interface driver hub
[ 2.929827] usbcore: registered new device driver usb
[ 2.930648] mvpp2 f2000000.ethernet eth0: Using random mac address
ce:c0:57:1c:27:7c
[ 2.935964] SCSI subsystem initialized
[ 2.936159] libphy: orion_mdio_bus: probed
[ 2.940813] libphy: orion_mdio_bus: probed
[ 2.948693] libata version 3.00 loaded.
[ 2.949269] mmc0: Switching to 3.3V signalling voltage failed
[ 2.951977] mvpp2 f4000000.ethernet eth1: Using random mac address
aa:6b:ec:75:56:b1
[ 2.963178] mvpp2 f4000000.ethernet eth2: Using random mac address
16:4c:90:91:ba:0a
[ 2.964356] armada38x-rtc f4284000.rtc: rtc core: registered
f4284000.rtc as rtc1
[ 2.988065] mmc0: SDHCI controller on f06e0000.sdhci
[f06e0000.sdhci] using ADMA 64-bit
[ 3.011934] mmc1: SDHCI controller on f2780000.sdhci
[f2780000.sdhci] using ADMA 64-bit
[ 3.012770] xhci-hcd f2500000.usb3: xHCI Host Controller
[ 3.012786] xhci-hcd f2500000.usb3: new USB bus registered,
assigned bus number 1
[ 3.013294] xhci-hcd f2500000.usb3: hcc params 0x0a000990 hci
version 0x100 quirks 0x00010010
[ 3.013326] xhci-hcd f2500000.usb3: irq 82, io mem 0xf2500000
[ 3.013525] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 3.013529] usb usb1: New USB device strings: Mfr=3, Product=2,
SerialNumber=1
[ 3.013533] usb usb1: Product: xHCI Host Controller
[ 3.013536] usb usb1: Manufacturer: Linux 4.15.0-rc7-arm64 xhci-hcd
[ 3.013539] usb usb1: SerialNumber: f2500000.usb3
[ 3.013879] hub 1-0:1.0: USB hub found
[ 3.014944] hub 1-0:1.0: 1 port detected
[ 3.015169] xhci-hcd f2500000.usb3: xHCI Host Controller
[ 3.015177] xhci-hcd f2500000.usb3: new USB bus registered,
assigned bus number 2
[ 3.015238] usb usb2: We don't know the algorithms for LPM for this
host, disabling LPM.
[ 3.015309] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
[ 3.015314] usb usb2: New USB device strings: Mfr=3, Product=2,
SerialNumber=1
[ 3.015317] usb usb2: Product: xHCI Host Controller
[ 3.015321] usb usb2: Manufacturer: Linux 4.15.0-rc7-arm64 xhci-hcd
[ 3.015324] usb usb2: SerialNumber: f2500000.usb3
[ 3.016118] hub 2-0:1.0: USB hub found
[ 3.016136] hub 2-0:1.0: 1 port detected
[ 3.016465] xhci-hcd f2510000.usb3: xHCI Host Controller
[ 3.016475] xhci-hcd f2510000.usb3: new USB bus registered,
assigned bus number 3
[ 3.016965] xhci-hcd f2510000.usb3: hcc params 0x0a000990 hci
version 0x100 quirks 0x00010010
[ 3.016991] xhci-hcd f2510000.usb3: irq 83, io mem 0xf2510000
[ 3.017155] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002
[ 3.017159] usb usb3: New USB device strings: Mfr=3, Product=2,
SerialNumber=1
[ 3.017162] usb usb3: Product: xHCI Host Controller
[ 3.017165] usb usb3: Manufacturer: Linux 4.15.0-rc7-arm64 xhci-hcd
[ 3.017168] usb usb3: SerialNumber: f2510000.usb3
[ 3.017420] hub 3-0:1.0: USB hub found
[ 3.017443] hub 3-0:1.0: 1 port detected
[ 3.017622] xhci-hcd f2510000.usb3: xHCI Host Controller
[ 3.017629] xhci-hcd f2510000.usb3: new USB bus registered,
assigned bus number 4
[ 3.017675] usb usb4: We don't know the algorithms for LPM for this
host, disabling LPM.
[ 3.017733] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003
[ 3.017737] usb usb4: New USB device strings: Mfr=3, Product=2,
SerialNumber=1
[ 3.017740] usb usb4: Product: xHCI Host Controller
[ 3.017743] usb usb4: Manufacturer: Linux 4.15.0-rc7-arm64 xhci-hcd
[ 3.017746] usb usb4: SerialNumber: f2510000.usb3
[ 3.017970] hub 4-0:1.0: USB hub found
[ 3.017986] hub 4-0:1.0: 1 port detected
[ 3.018421] ahci f2540000.sata: AHCI 0001.0000 32 slots 2 ports 6
Gbps 0x3 impl platform mode
[ 3.018426] ahci f2540000.sata: flags: 64bit ncq sntf led only pmp
fbs pio slum part sxs
[ 3.018492] xhci-hcd f4500000.usb3: xHCI Host Controller
[ 3.018503] xhci-hcd f4500000.usb3: new USB bus registered,
assigned bus number 5
[ 3.019059] xhci-hcd f4500000.usb3: hcc params 0x0a000990 hci
version 0x100 quirks 0x00010010
[ 3.019080] xhci-hcd f4500000.usb3: irq 84, io mem 0xf4500000
[ 3.019263] scsi host0: ahci
[ 3.019312] usb usb5: New USB device found, idVendor=1d6b, idProduct=0002
[ 3.019316] usb usb5: New USB device strings: Mfr=3, Product=2,
SerialNumber=1
[ 3.019319] usb usb5: Product: xHCI Host Controller
[ 3.019323] usb usb5: Manufacturer: Linux 4.15.0-rc7-arm64 xhci-hcd
[ 3.019326] usb usb5: SerialNumber: f4500000.usb3
[ 3.019491] scsi host1: ahci
[ 3.019629] ata1: SATA max UDMA/133 mmio [mem
0xf2540000-0xf256ffff] port 0x100 irq 85
[ 3.019633] ata2: SATA max UDMA/133 mmio [mem
0xf2540000-0xf256ffff] port 0x180 irq 85
[ 3.019642] hub 5-0:1.0: USB hub found
[ 3.019673] hub 5-0:1.0: 1 port detected
[ 3.019858] xhci-hcd f4500000.usb3: xHCI Host Controller
[ 3.019865] xhci-hcd f4500000.usb3: new USB bus registered,
assigned bus number 6
[ 3.019947] usb usb6: We don't know the algorithms for LPM for this
host, disabling LPM.
[ 3.020035] usb usb6: New USB device found, idVendor=1d6b, idProduct=0003
[ 3.020039] usb usb6: New USB device strings: Mfr=3, Product=2,
SerialNumber=1
[ 3.020042] usb usb6: Product: xHCI Host Controller
[ 3.020045] usb usb6: Manufacturer: Linux 4.15.0-rc7-arm64 xhci-hcd
[ 3.020048] usb usb6: SerialNumber: f4500000.usb3
[ 3.020332] hub 6-0:1.0: USB hub found
[ 3.020353] hub 6-0:1.0: 1 port detected
[ 3.020752] ahci f4540000.sata: AHCI 0001.0000 32 slots 2 ports 6
Gbps 0x3 impl platform mode
[ 3.020758] ahci f4540000.sata: flags: 64bit ncq sntf led only pmp
fbs pio slum part sxs
[ 3.026127] scsi host2: ahci
[ 3.026428] scsi host3: ahci
[ 3.026547] ata3: SATA max UDMA/133 mmio [mem
0xf4540000-0xf456ffff] port 0x100 irq 86
[ 3.026551] ata4: SATA max UDMA/133 mmio [mem
0xf4540000-0xf456ffff] port 0x180 irq 86
[ 3.030874] mmc0: new high speed MMC card at address 0001
[ 3.031191] mmcblk0: mmc0:0001 8GME4R 7.28 GiB
[ 3.031331] mmcblk0boot0: mmc0:0001 8GME4R partition 1 4.00 MiB
[ 3.031470] mmcblk0boot1: mmc0:0001 8GME4R partition 2 4.00 MiB
[ 3.031557] mmcblk0rpmb: mmc0:0001 8GME4R partition 3 512 KiB,
chardev (242:0)
[ 3.034350] mmcblk0: p1 p2 p3
[ 3.053903] mmc1: new high speed SDHC card at address 1234
[ 3.054238] mmcblk1: mmc1:1234 SA08G 7.41 GiB
[ 3.055423] mmcblk1: p1 p2
[ 3.334142] ata2: SATA link down (SStatus 0 SControl 300)
[ 3.334175] ata1: SATA link down (SStatus 0 SControl 300)
[ 3.503937] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 3.503958] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 3.504175] ata4.00: supports DRM functions and may not be fully accessible
[ 3.504181] ata4.00: ATA-9: Samsung SSD 850 EVO 500GB, EMT02B6Q, max UDMA/133
[ 3.504185] ata4.00: 976773168 sectors, multi 1: LBA48 NCQ (depth 31/32)
[ 3.505757] ata4.00: supports DRM functions and may not be fully accessible
[ 3.507050] ata4.00: configured for UDMA/133
[ 3.511148] ata3.00: ATA-8: WDC WD20EARS-00J99B0, 80.00A80, max UDMA/133
[ 3.511151] ata3.00: 3907029168 sectors, multi 0: LBA48 NCQ (depth 31/32)
[ 3.518179] ata3.00: configured for UDMA/133
[ 3.518433] scsi 2:0:0:0: Direct-Access ATA WDC
WD20EARS-00J 0A80 PQ: 0 ANSI: 5
[ 3.518999] scsi 3:0:0:0: Direct-Access ATA Samsung SSD
850 2B6Q PQ: 0 ANSI: 5
[ 3.524036] sd 2:0:0:0: [sda] 3907029168 512-byte logical blocks:
(2.00 TB/1.82 TiB)
[ 3.524042] sd 2:0:0:0: [sda] 4096-byte physical blocks
[ 3.524084] sd 2:0:0:0: [sda] Write Protect is off
[ 3.524088] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.524133] sd 2:0:0:0: [sda] Write cache: enabled, read cache:
enabled, doesn't support DPO or FUA
[ 3.524326] sd 3:0:0:0: [sdb] 976773168 512-byte logical blocks:
(500 GB/466 GiB)
[ 3.524355] sd 3:0:0:0: [sdb] Write Protect is off
[ 3.524360] sd 3:0:0:0: [sdb] Mode Sense: 00 3a 00 00
[ 3.524410] sd 3:0:0:0: [sdb] Write cache: enabled, read cache:
enabled, doesn't support DPO or FUA
[ 3.525680] sd 3:0:0:0: [sdb] Attached SCSI removable disk
[ 3.540619] sda: sda1 sda2
[ 3.541248] sd 2:0:0:0: [sda] Attached SCSI removable disk
[ 3.815843] mmc0: Switching to 3.3V signalling voltage failed
[ 3.822247] PM: Starting manual resume from disk
[ 3.822515] PM: Image not found (code -22)
[ 3.937618] EXT4-fs (mmcblk0p2): mounted filesystem with ordered
data mode. Opts: (null)
[ 4.308264] ip_tables: (C) 2000-2006 Netfilter Core Team
[ 4.335334] systemd[1]: systemd 236 running in system mode. (+PAM
+AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP
+GCRY
PT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN
default-hierarchy=hybrid)
[ 4.335635] systemd[1]: Detected architecture arm64.
[ 4.339813] systemd[1]: Set hostname to <debian>.
[ 4.475258] systemd-gpt-auto-generator[205]: Failed to dissect:
Input/output error
[ 4.483749] systemd[200]:
/lib/systemd/system-generators/systemd-gpt-auto-generator failed with
error code 1.
[ 4.494976] systemd[1]: File
/lib/systemd/system/systemd-journald.service:35 configures an IP
firewall (IPAddressDeny=any), but the local sy
stem does not support BPF/cgroup based firewalling.
[ 4.494983] systemd[1]: Proceeding WITHOUT firewalling in effect!
(This warning is only shown for the first loaded unit using IP
firewalling
.)
[ 4.561763] systemd[1]: Reached target Remote File Systems.
[ 4.561976] systemd[1]: Started Forward Password Requests to Wall
Directory Watch.
[ 4.562075] systemd[1]: Started Dispatch Password Requests to
Console Directory Watch.
[ 4.562094] systemd[1]: Reached target Paths.
[ 4.624825] EXT4-fs (mmcblk0p2): re-mounted. Opts: errors=remount-ro
[ 4.693929] systemd-journald[217]: Received request to flush
runtime journal from PID 1
[ 4.796241] sbsa-gwdt f0610000.watchdog: Initialized with 10s
timeout @ 25000000 Hz, action=0.
[ 4.811412] EFI Variables Facility v0.08 2004-May-17
[ 4.834118] pstore: using zlib compression
[ 4.837066] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[ 4.844672] pstore: Registered efi as persistent store backend
[ 4.896049] sd 2:0:0:0: Attached scsi generic sg0 type 0
[ 4.896176] sd 3:0:0:0: Attached scsi generic sg1 type 0
[ 4.990475] Adding 3942396k swap on /dev/mmcblk0p3. Priority:-2
extents:1 across:3942396k SSFS
[ 5.284816] audit: type=1400 audit(1526691223.000:2):
apparmor="STATUS" operation="profile_load" profile="unconfined"
name="/usr/bin/man" pi
d=370 comm="apparmor_parser"
[ 5.284825] audit: type=1400 audit(1526691223.000:3):
apparmor="STATUS" operation="profile_load" profile="unconfined"
name="/usr/bin/man//fi
lter" pid=370 comm="apparmor_parser"
[ 5.284831] audit: type=1400 audit(1526691223.000:4):
apparmor="STATUS" operation="profile_load" profile="unconfined"
name="/usr/bin/man//gr
off" pid=370 comm="apparmor_parser"
[ 5.618325] IPv6: ADDRCONF(NETDEV_UP): eth2: link is not ready
[ 5.710874] mmc0: Switching to 3.3V signalling voltage failed
[ 9.796332] mvpp2 f4000000.ethernet eth2: Link is Up - 1Gbps/Full -
flow control off
[ 9.796350] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready
[ 9.800076] mmc0: Switching to 3.3V signalling voltage failed
[ 14.052137] mmc0: Switching to 3.3V signalling voltage failed
[ 15.844178] mmc0: Switching to 3.3V signalling voltage failed
[ 21.988130] mmc0: Switching to 3.3V signalling voltage failed
[ 22.050680] mmc0: Switching to 3.3V signalling voltage failed
[ 22.155246] mmc0: Switching to 3.3V signalling voltage failed
[ 22.845074] mmc0: Switching to 3.3V signalling voltage failed
[ 22.917350] mmc0: Switching to 3.3V signalling voltage failed
[ 24.834819] mmc0: Switching to 3.3V signalling voltage failed
[ 26.195699] mmc0: Switching to 3.3V signalling voltage failed
[ 27.876102] mmc0: Switching to 3.3V signalling voltage failed
[ 29.170275] mmc0: Switching to 3.3V signalling voltage failed
[ 34.020058] mmc0: Switching to 3.3V signalling voltage failed
[ 36.570406] mmc0: Switching to 3.3V signalling voltage failed
[ 39.139512] mmc0: Switching to 3.3V signalling voltage failed
[ 40.652720] mmc0: Switching to 3.3V signalling voltage failed
[ 44.772152] mmc0: Switching to 3.3V signalling voltage failed
[ 49.892041] mmc0: Switching to 3.3V signalling voltage failed
[ 50.420898] mmc0: Switching to 3.3V signalling voltage failed
[ 51.938299] random: crng init done
[ 55.012204] mmc0: Switching to 3.3V signalling voltage failed
[ 60.900100] mmc0: Switching to 3.3V signalling voltage failed
[ 67.044040] mmc0: Switching to 3.3V signalling voltage failed
[ 67.231406] mmc0: Switching to 3.3V signalling voltage failed
[ 72.931749] mmc0: Switching to 3.3V signalling voltage failed
[ 75.491437] mmc0: Switching to 3.3V signalling voltage failed
[ 78.819241] mmc0: Switching to 3.3V signalling voltage failed
[ 80.611246] mmc0: Switching to 3.3V signalling voltage failed
[ 84.962989] mmc0: Switching to 3.3V signalling voltage failed
[ 90.330158] mmc0: Switching to 3.3V signalling voltage failed
[ 93.332842] mmc0: Switching to 3.3V signalling voltage failed
[ 93.336740] omap_rng f2760000.trng: Random Number Generator ver. 203b34c
[ 95.970664] mmc0: Switching to 3.3V signalling voltage failed
[ 101.862573] mmc0: Switching to 3.3V signalling voltage failed
[ 106.210610] mmc0: Switching to 3.3V signalling voltage failed
[ 108.002491] mmc0: Switching to 3.3V signalling voltage failed
[ 111.334419] mmc0: Switching to 3.3V signalling voltage failed
[ 113.894416] mmc0: Switching to 3.3V signalling voltage failed
[ 114.330328] INFO: rcu_sched self-detected stall on CPU
[ 114.335500] 0-....: (5249 ticks this GP)
idle=3b6/140000000000002/0 softirq=2065/2065 fqs=1944
[ 114.344325]
[ 114.344327] INFO: rcu_sched detected stalls on CPUs/tasks:
[ 114.344336] 0-....: (5249 ticks this GP)
idle=3b6/140000000000002/0 softirq=2065/2065 fqs=1945
[ 114.344337] (detected by 3, t=5252 jiffies, g=375, c=374, q=836)
[ 114.330328] INFO: rcu_sched self-detected stall on CPU
[ 114.335500] 0-....: (5249 ticks this GP)
idle=3b6/140000000000002/0 softirq=2065/2065 fqs=1944
[ 114.344325]
[ 114.344327] INFO: rcu_sched detected stalls on CPUs/tasks:
[ 114.344336] 0-....: (5249 ticks this GP)
idle=3b6/140000000000002/0 softirq=2065/2065 fqs=1945
[ 114.344337] (detected by 3, t=5252 jiffies, g=375, c=374, q=836)
[ 114.344342] Task dump for CPU 0:
[ 114.344344] modprobe R running task 0 543 486 0x00000022
[ 114.344350] Call trace:
[ 114.344361] __switch_to+0x98/0xb0
[ 114.344367] __setup_irq+0x798/0x7f8
[ 114.366360] (t=5259 jiffies g=375 c=374 q=836)
[ 114.366362] Task dump for CPU 0:
[ 114.366365] modprobe R running task 0 543 486 0x00000022
[ 114.366372] Call trace:
[ 114.366381] dump_backtrace+0x0/0x200
[ 114.366386] show_stack+0x24/0x30
[ 114.366391] sched_show_task+0x174/0x198
[ 114.366394] dump_cpu_task+0x48/0x58
[ 114.366399] rcu_dump_cpu_stacks+0x9c/0xe0
[ 114.366403] rcu_check_callbacks+0x6cc/0x908
[ 114.366406] update_process_times+0x34/0x60
[ 114.366412] tick_sched_handle.isra.5+0x34/0x70
[ 114.366415] tick_sched_timer+0x48/0x98
[ 114.366419] __hrtimer_run_queues+0xdc/0x2b8
[ 114.366422] hrtimer_interrupt+0xa8/0x228
[ 114.366427] arch_timer_handler_phys+0x38/0x58
[ 114.366431] handle_percpu_devid_irq+0x90/0x268
[ 114.366436] generic_handle_irq+0x34/0x50
[ 114.366439] __handle_domain_irq+0x68/0xc0
[ 114.366442] gic_handle_irq+0x60/0xb0
[ 114.366444] el1_irq+0xb0/0x140
[ 114.366447] __do_softirq+0xb0/0x334
[ 114.366451] irq_exit+0xc0/0xf0
[ 114.366454] __handle_domain_irq+0x6c/0xc0
[ 114.366456] gic_handle_irq+0x60/0xb0
[ 114.366459] el1_irq+0xb0/0x140
[ 114.366464] _raw_spin_unlock_irqrestore+0x2c/0x38
[ 114.366467] __setup_irq+0x548/0x7f8
[ 114.366470] request_threaded_irq+0xf0/0x1b0
[ 114.366474] devm_request_threaded_irq+0x80/0xf8
[ 114.366486] omap_rng_probe+0x1f4/0x418 [omap_rng]
[ 114.366491] platform_drv_probe+0x60/0xc0
[ 114.366496] driver_probe_device+0x33c/0x4a0
[ 114.366499] __driver_attach+0xdc/0x128
[ 114.366503] bus_for_each_dev+0x78/0xd8
[ 114.366506] driver_attach+0x30/0x40
[ 114.366510] bus_add_driver+0x218/0x2b8
[ 114.366513] driver_register+0x6c/0x118
[ 114.366516] __platform_driver_register+0x54/0x60
[ 114.366522] omap_rng_driver_init+0x20/0x1000 [omap_rng]
[ 114.366525] do_one_initcall+0x58/0x168
[ 114.366529] do_init_module+0x64/0x1d8
[ 114.366533] load_module.isra.36+0x20e0/0x26a8
[ 114.366537] SyS_finit_module+0x100/0x120
[ 114.366540] el0_svc_naked+0x20/0x24
[ 116.454456] mmc0: Switching to 3.3V signalling voltage failed
[ 120.038421] mmc0: Switching to 3.3V signalling voltage failed
[ 125.922372] mmc0: Switching to 3.3V signalling voltage failed
[ 126.690483] mmc0: Switching to 3.3V signalling voltage failed
[ 131.810396] mmc0: Switching to 3.3V signalling voltage failed
[ 136.934029] mmc0: Switching to 3.3V signalling voltage failed
[ 140.005535] watchdog: BUG: soft lockup - CPU#0 stuck for 22s! [modprobe:543]
[ 140.005535] watchdog: BUG: soft lockup - CPU#0 stuck for 22s! [modprobe:543]
[ 140.012617] Modules linked in: omap_rng(+) rng_core nls_ascii
nls_cp437 vfat fat aes_ce_blk crypto_simd cryptd sg aes_ce_cipher
ghash_ce gf1
28mul sha2_ce shpchp efi_pstore efivars sha256_arm64 sbsa_gwdt sha1_ce
efivarfs ip_tables x_tables autofs4 ext4 crc16 mbcache jbd2
crc32c_gener
ic fscrypto ecb aes_arm64 sd_mod phy_generic ahci_platform
libahci_platform libahci libata marvell rtc_armada38x xhci_plat_hcd
xhci_hcd scsi_mo
d fixed usbcore i2c_mv64xxx sdhci_xenon_driver sdhci_pltfm sdhci
mvmdio mvpp2 of_mdio fixed_phy phy_mvebu_cp110_comphy libphy
[ 140.012715] CPU: 0 PID: 543 Comm: modprobe Not tainted
4.15.0-rc7-arm64 #1 Debian 4.15~rc7-1~exp1
[ 140.012717] Hardware name: Marvell Armada 8040 MacchiatoBin/Armada
8040 MacchiatoBin, BIOS EDK II Dec 12 2017
[ 140.012721] pstate: 40000005 (nZcv daif -PAN -UAO)
[ 140.012725] pc : __do_softirq+0xb0/0x334
[ 140.012729] lr : irq_exit+0xc0/0xf0
[ 140.012731] sp : ffff000008003ed0
[ 140.012733] x29: ffff000008003ed0 x28: 0000000000000282
[ 140.012739] x27: 0000000000000000 x26: ffff000008004000
[ 140.012744] x25: ffff000008000000 x24: ffff3d049fa31000
[ 140.012749] x23: ffff000009e93770 x22: 0000000000000000
[ 140.012754] x21: 0000000000000000 x20: 0000000000000003
Message from syslogd at debian at Jan 9 09:58:21 ...
kernel:[ 140.005535] watchdog: BUG: soft lockup - CPU#0 stuck for
22s! [modprobe:543]
[ 140.012759] x19: ffff3d049fa31000 x18: 0000000000000014
[ 140.012764] x17: 000000000000000e x16: 0000000000000007
[ 140.012769] x15: 0000000000000001 x14: 0000000000000000
[ 140.012774] x13: 0000000000000033 x12: 0000000000000000
[ 140.012779] x11: ffff3d049f672150 x10: 0000000000000177
[ 140.012784] x9 : ffff3d049f672158 x8 : 0000000000000000
[ 140.012789] x7 : 0000000000000004 x6 : 00000000a6e967d8
[ 140.012794] x5 : 00ffffffffffffff x4 : 00000000ffff362f
[ 140.012799] x3 : ffff3d049fef9980 x2 : 0000a1aee0539000
[ 140.012804] x1 : ffff3d049fef9980 x0 : 0000000000000000
[ 140.012809] Call trace:
[ 140.012813] __do_softirq+0xb0/0x334
[ 140.012816] irq_exit+0xc0/0xf0
[ 140.012819] __handle_domain_irq+0x6c/0xc0
[ 140.012822] gic_handle_irq+0x60/0xb0
[ 140.012824] el1_irq+0xb0/0x140
[ 140.012828] _raw_spin_unlock_irqrestore+0x2c/0x38
[ 140.012831] __setup_irq+0x548/0x7f8
[ 140.012834] request_threaded_irq+0xf0/0x1b0
[ 140.012838] devm_request_threaded_irq+0x80/0xf8
[ 140.012846] omap_rng_probe+0x1f4/0x418 [omap_rng]
[ 140.012849] platform_drv_probe+0x60/0xc0
[ 140.012853] driver_probe_device+0x33c/0x4a0
[ 140.012857] __driver_attach+0xdc/0x128
[ 140.012860] bus_for_each_dev+0x78/0xd8
[ 140.012864] driver_attach+0x30/0x40
[ 140.012867] bus_add_driver+0x218/0x2b8
[ 140.012871] driver_register+0x6c/0x118
[ 140.012874] __platform_driver_register+0x54/0x60
[ 140.012879] omap_rng_driver_init+0x20/0x1000 [omap_rng]
[ 140.012882] do_one_initcall+0x58/0x168
[ 140.012886] do_init_module+0x64/0x1d8
[ 140.012890] load_module.isra.36+0x20e0/0x26a8
[ 140.012894] SyS_finit_module+0x100/0x120
[ 140.012896] el0_svc_naked+0x20/0x24
[ 142.049544] mmc0: Switching to 3.3V signalling voltage failed
^ permalink raw reply
* [PATCH] media: mtk-vcodec: Always signal source change event on format change
From: Tomasz Figa @ 2018-01-09 8:42 UTC (permalink / raw)
To: linux-arm-kernel
Currently the driver signals the source change event only in case of
a midstream resolution change, however the initial format detection
is also defined as a source change by the V4L2 codec API specification.
Fix this by signaling the event after the initial header is parsed as
well.
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
index 843510979ad8..86f0a7134365 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
@@ -1224,6 +1224,8 @@ static void vb2ops_vdec_buf_queue(struct vb2_buffer *vb)
ctx->dpb_size = dpbsize;
ctx->state = MTK_STATE_HEADER;
mtk_v4l2_debug(1, "[%d] dpbsize=%d", ctx->id, ctx->dpb_size);
+
+ mtk_vdec_queue_res_chg_event(ctx);
}
static void vb2ops_vdec_buf_finish(struct vb2_buffer *vb)
--
2.16.0.rc0.223.g4a4ac83678-goog
^ permalink raw reply related
* [PATCH] media: mtk-vcodec: Always signal source change event on format change
From: Wu-Cheng Li (李務誠) @ 2018-01-09 8:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109084247.104601-1-tfiga@chromium.org>
Reviewed-by: Wu-Cheng Li <wuchengli@chromium.org>
On Tue, Jan 9, 2018 at 4:42 PM, Tomasz Figa <tfiga@chromium.org> wrote:
> Currently the driver signals the source change event only in case of
> a midstream resolution change, however the initial format detection
> is also defined as a source change by the V4L2 codec API specification.
> Fix this by signaling the event after the initial header is parsed as
> well.
>
> Signed-off-by: Tomasz Figa <tfiga@chromium.org>
> ---
> drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
> index 843510979ad8..86f0a7134365 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c
> @@ -1224,6 +1224,8 @@ static void vb2ops_vdec_buf_queue(struct vb2_buffer *vb)
> ctx->dpb_size = dpbsize;
> ctx->state = MTK_STATE_HEADER;
> mtk_v4l2_debug(1, "[%d] dpbsize=%d", ctx->id, ctx->dpb_size);
> +
> + mtk_vdec_queue_res_chg_event(ctx);
> }
>
> static void vb2ops_vdec_buf_finish(struct vb2_buffer *vb)
> --
> 2.16.0.rc0.223.g4a4ac83678-goog
>
^ permalink raw reply
* [PATCH net-next v3 0/4] net: mvpp2: 1000BaseX and 2500BaseX support
From: Antoine Tenart @ 2018-01-09 8:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This series adds 1000BaseX and 2500BaseX support to the Marvell PPv2
driver. In order to use it, the 2.5 SGMII mode is added in the Marvell
common PHY driver (cp110-comphy).
This was tested on a mcbin.
All patches should probably go through net-next as patch 4/4 depends on
patch 1/4 to build and work.
Please note the two mvpp2 patches do not conflict with the ACPI series
v2 Marcin sent a few days ago, and the two series can be processed in
parallel. (Marcin is aware of me sending this series).
Thanks!
Antoine
Since v2:
- Added a comment before mvpp22_comphy_init() about the different PHY modes
used and why they differ between the PPv2 driver and the COMPHY one.
Since v1:
- s/PHY_MODE_SGMII_2_5G/PHY_MODE_2500SGMII/
- Fixed a build error in 'net: mvpp2: 1000baseX support' (which was solved in
the 2500baseX support one, but the bisection was broken).
- Removed the dt patches, as the fourth network interface on the mcbin also
needs PHYLINK support in the PPv2 driver to be correctly supported.
Antoine Tenart (4):
phy: add 2.5G SGMII mode to the phy_mode enum
phy: cp110-comphy: 2.5G SGMII mode
net: mvpp2: 1000baseX support
net: mvpp2: 2500baseX support
drivers/net/ethernet/marvell/mvpp2.c | 77 ++++++++++++++++++++++++----
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 17 ++++--
include/linux/phy/phy.h | 1 +
3 files changed, 82 insertions(+), 13 deletions(-)
--
2.14.3
^ permalink raw reply
* [PATCH net-next v3 1/4] phy: add 2.5G SGMII mode to the phy_mode enum
From: Antoine Tenart @ 2018-01-09 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109085945.11916-1-antoine.tenart@free-electrons.com>
This patch adds one more generic PHY mode to the phy_mode enum, to allow
configuring generic PHYs to the 2.5G SGMII mode by using the set_mode
callback.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
include/linux/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 4f8423a948d5..5a80e9de3686 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -28,6 +28,7 @@ enum phy_mode {
PHY_MODE_USB_DEVICE,
PHY_MODE_USB_OTG,
PHY_MODE_SGMII,
+ PHY_MODE_2500SGMII,
PHY_MODE_10GKR,
PHY_MODE_UFS_HS_A,
PHY_MODE_UFS_HS_B,
--
2.14.3
^ permalink raw reply related
* [PATCH net-next v3 2/4] phy: cp110-comphy: 2.5G SGMII mode
From: Antoine Tenart @ 2018-01-09 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109085945.11916-1-antoine.tenart@free-electrons.com>
This patch allow the CP100 comphy to configure some lanes in the
2.5G SGMII mode. This mode is quite close to SGMII and uses nearly the
same code path.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index a0d522154cdf..4ef429250d7b 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -135,19 +135,25 @@ struct mvebu_comhy_conf {
static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(0, 1, PHY_MODE_2500SGMII, 0x1),
/* lane 1 */
MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(1, 2, PHY_MODE_2500SGMII, 0x1),
/* lane 2 */
MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(2, 0, PHY_MODE_2500SGMII, 0x1),
MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR, 0x1),
/* lane 3 */
MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII, 0x2),
+ MVEBU_COMPHY_CONF(3, 1, PHY_MODE_2500SGMII, 0x2),
/* lane 4 */
MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII, 0x2),
+ MVEBU_COMPHY_CONF(4, 0, PHY_MODE_2500SGMII, 0x2),
MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR, 0x2),
MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII, 0x1),
/* lane 5 */
MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(5, 2, PHY_MODE_2500SGMII, 0x1),
};
struct mvebu_comphy_priv {
@@ -206,6 +212,10 @@ static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane,
if (mode == PHY_MODE_10GKR)
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
+ else if (mode == PHY_MODE_2500SGMII)
+ val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) |
+ MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x8) |
+ MVEBU_COMPHY_SERDES_CFG0_HALF_BUS;
else if (mode == PHY_MODE_SGMII)
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) |
@@ -296,13 +306,13 @@ static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane,
return 0;
}
-static int mvebu_comphy_set_mode_sgmii(struct phy *phy)
+static int mvebu_comphy_set_mode_sgmii(struct phy *phy, enum phy_mode mode)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
u32 val;
- mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_SGMII);
+ mvebu_comphy_ethernet_init_reset(lane, mode);
val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
@@ -487,7 +497,8 @@ static int mvebu_comphy_power_on(struct phy *phy)
switch (lane->mode) {
case PHY_MODE_SGMII:
- ret = mvebu_comphy_set_mode_sgmii(phy);
+ case PHY_MODE_2500SGMII:
+ ret = mvebu_comphy_set_mode_sgmii(phy, lane->mode);
break;
case PHY_MODE_10GKR:
ret = mvebu_comphy_set_mode_10gkr(phy);
--
2.14.3
^ permalink raw reply related
* [PATCH net-next v3 3/4] net: mvpp2: 1000baseX support
From: Antoine Tenart @ 2018-01-09 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109085945.11916-1-antoine.tenart@free-electrons.com>
This patch adds the 1000Base-X PHY mode support in the Marvell PPv2
driver. 1000Base-X is quite close the SGMII and uses nearly the same
code path.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 45 ++++++++++++++++++++++++++++--------
1 file changed, 35 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index a19760736b71..257a6b99b4ca 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -4501,6 +4501,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
mvpp22_gop_init_rgmii(port);
break;
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
mvpp22_gop_init_sgmii(port);
break;
case PHY_INTERFACE_MODE_10GKR:
@@ -4538,7 +4539,8 @@ static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
u32 val;
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
/* Enable the GMAC link status irq for this port */
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
@@ -4568,7 +4570,8 @@ static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
}
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
@@ -4580,7 +4583,8 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
u32 val;
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_MASK);
val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_MASK);
@@ -4605,6 +4609,7 @@ static int mvpp22_comphy_init(struct mvpp2_port *port)
switch (port->phy_interface) {
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
mode = PHY_MODE_SGMII;
break;
case PHY_INTERFACE_MODE_10GKR:
@@ -4625,7 +4630,8 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
{
u32 val;
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL |
MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
@@ -4640,9 +4646,11 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
}
- /* The port is connected to a copper PHY */
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
- val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
+ if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ val |= MVPP2_GMAC_PORT_TYPE_MASK;
+ else
+ val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
@@ -4651,6 +4659,19 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
MVPP2_GMAC_AN_DUPLEX_EN;
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
val |= MVPP2_GMAC_IN_BAND_AUTONEG;
+
+ if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ /* 1000BaseX port cannot negotiate speed nor can it
+ * negotiate duplex: they are always operating with a
+ * fixed speed of 1000Mbps in full duplex, so force
+ * 1000 speed and full duplex here.
+ */
+ val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_CONFIG_FULL_DUPLEX;
+ else
+ val |= MVPP2_GMAC_AN_SPEED_EN |
+ MVPP2_GMAC_AN_DUPLEX_EN;
+
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
}
@@ -4671,7 +4692,8 @@ static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port)
/* Configure the PCS and in-band AN */
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
} else if (phy_interface_mode_is_rgmii(port->phy_interface)) {
val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
@@ -4733,7 +4755,8 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
mvpp22_port_mii_set(port);
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
mvpp2_port_mii_gmac_configure(port);
else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
mvpp2_port_mii_xlg_configure(port);
@@ -4810,7 +4833,8 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port)
else
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
else
val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -6023,7 +6047,8 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
link = true;
}
} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_STAT);
if (val & MVPP22_GMAC_INT_STAT_LINK) {
event = true;
--
2.14.3
^ permalink raw reply related
* [PATCH net-next v3 4/4] net: mvpp2: 2500baseX support
From: Antoine Tenart @ 2018-01-09 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109085945.11916-1-antoine.tenart@free-electrons.com>
This patch adds the 2500Base-X PHY mode support in the Marvell PPv2
driver. 2500Base-X is quite close to 1000Base-X and SGMII modes and uses
nearly the same code path.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 50 +++++++++++++++++++++++++++++-------
1 file changed, 41 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 257a6b99b4ca..290f891421d1 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -4502,6 +4502,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
mvpp22_gop_init_sgmii(port);
break;
case PHY_INTERFACE_MODE_10GKR:
@@ -4540,7 +4541,8 @@ static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
/* Enable the GMAC link status irq for this port */
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
@@ -4571,7 +4573,8 @@ static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
@@ -4584,7 +4587,8 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_MASK);
val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_MASK);
@@ -4599,6 +4603,16 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
mvpp22_gop_unmask_irq(port);
}
+/* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
+ *
+ * The PHY mode used by the PPv2 driver comes from the network subsystem, while
+ * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
+ * differ.
+ *
+ * The COMPHY configures the serdes lanes regardless of the actual use of the
+ * lanes by the physical layer. This is why configurations like
+ * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
+ */
static int mvpp22_comphy_init(struct mvpp2_port *port)
{
enum phy_mode mode;
@@ -4612,6 +4626,9 @@ static int mvpp22_comphy_init(struct mvpp2_port *port)
case PHY_INTERFACE_MODE_1000BASEX:
mode = PHY_MODE_SGMII;
break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ mode = PHY_MODE_2500SGMII;
+ break;
case PHY_INTERFACE_MODE_10GKR:
mode = PHY_MODE_10GKR;
break;
@@ -4631,7 +4648,8 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
u32 val;
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL |
MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
@@ -4647,7 +4665,8 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
}
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
- if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
val |= MVPP2_GMAC_PORT_TYPE_MASK;
else
val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
@@ -4660,6 +4679,11 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
val |= MVPP2_GMAC_IN_BAND_AUTONEG;
+ /* Clear all fields we may want to explicitly set below */
+ val &= ~(MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_AN_SPEED_EN |
+ MVPP2_GMAC_AN_DUPLEX_EN);
+
if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
/* 1000BaseX port cannot negotiate speed nor can it
* negotiate duplex: they are always operating with a
@@ -4668,6 +4692,10 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
*/
val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
MVPP2_GMAC_CONFIG_FULL_DUPLEX;
+ else if (port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
+ val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_CONFIG_MII_SPEED |
+ MVPP2_GMAC_CONFIG_FULL_DUPLEX;
else
val |= MVPP2_GMAC_AN_SPEED_EN |
MVPP2_GMAC_AN_DUPLEX_EN;
@@ -4693,7 +4721,8 @@ static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port)
/* Configure the PCS and in-band AN */
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
} else if (phy_interface_mode_is_rgmii(port->phy_interface)) {
val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
@@ -4756,7 +4785,8 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
mvpp2_port_mii_gmac_configure(port);
else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
mvpp2_port_mii_xlg_configure(port);
@@ -4834,7 +4864,8 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port)
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
else
val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -6048,7 +6079,8 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
}
} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_STAT);
if (val & MVPP22_GMAC_INT_STAT_LINK) {
event = true;
--
2.14.3
^ permalink raw reply related
* [Intel-wired-lan] [PATCH 01/27] timecounter: Make cyclecounter struct part of timecounter struct
From: Sagar Arun Kamble @ 2018-01-09 9:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <309B89C4C689E141A5FF6A0C5FB2118B8C734DF8@ORSMSX101.amr.corp.intel.com>
Thanks Aaron.
Regards,
Sagar
On 1/9/2018 3:50 AM, Brown, Aaron F wrote:
>> From: Intel-wired-lan [mailto:intel-wired-lan-bounces at osuosl.org] On
>> Behalf Of Sagar Arun Kamble
>> Sent: Thursday, December 14, 2017 11:38 PM
>> To: linux-kernel at vger.kernel.org
>> Cc: alsa-devel at alsa-project.org; linux-rdma at vger.kernel.org;
>> netdev at vger.kernel.org; Richard Cochran <richardcochran@gmail.com>;
>> Stephen Boyd <sboyd@codeaurora.org>; Chris Wilson <chris@chris-
>> wilson.co.uk>; John Stultz <john.stultz@linaro.org>; intel-wired-
>> lan at lists.osuosl.org; Thomas Gleixner <tglx@linutronix.de>; Kamble, Sagar A
>> <sagar.a.kamble@intel.com>; kvmarm at lists.cs.columbia.edu; linux-arm-
>> kernel at lists.infradead.org
>> Subject: [Intel-wired-lan] [PATCH 01/27] timecounter: Make cyclecounter
>> struct part of timecounter struct
>>
>> There is no real need for the users of timecounters to define cyclecounter
>> and timecounter variables separately. Since timecounter will always be
>> based on cyclecounter, have cyclecounter struct as member of timecounter
>> struct.
>>
>> v2: Rebase.
>>
>> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Richard Cochran <richardcochran@gmail.com>
>> Cc: John Stultz <john.stultz@linaro.org>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: Stephen Boyd <sboyd@codeaurora.org>
>> Cc: linux-kernel at vger.kernel.org
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: netdev at vger.kernel.org
>> Cc: intel-wired-lan at lists.osuosl.org
>> Cc: linux-rdma at vger.kernel.org
>> Cc: alsa-devel at alsa-project.org
>> Cc: kvmarm at lists.cs.columbia.edu
>> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> (Intel drivers)
>> ---
>> arch/microblaze/kernel/timer.c | 20 ++++++------
>> drivers/clocksource/arm_arch_timer.c | 19 ++++++------
>> drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 3 +-
>> drivers/net/ethernet/amd/xgbe/xgbe-ptp.c | 9 +++---
>> drivers/net/ethernet/amd/xgbe/xgbe.h | 1 -
>> drivers/net/ethernet/broadcom/bnx2x/bnx2x.h | 1 -
>> drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 20 ++++++------
>> drivers/net/ethernet/freescale/fec.h | 1 -
>> drivers/net/ethernet/freescale/fec_ptp.c | 30 +++++++++---------
>> drivers/net/ethernet/intel/e1000e/e1000.h | 1 -
>> drivers/net/ethernet/intel/e1000e/netdev.c | 27 ++++++++--------
>> drivers/net/ethernet/intel/e1000e/ptp.c | 2 +-
>> drivers/net/ethernet/intel/igb/igb.h | 1 -
>> drivers/net/ethernet/intel/igb/igb_ptp.c | 25 ++++++++-------
>> drivers/net/ethernet/intel/ixgbe/ixgbe.h | 1 -
>> drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | 17 +++++-----
>> drivers/net/ethernet/mellanox/mlx4/en_clock.c | 28 ++++++++---------
>> drivers/net/ethernet/mellanox/mlx4/mlx4_en.h | 1 -
>> .../net/ethernet/mellanox/mlx5/core/lib/clock.c | 34 ++++++++++----------
>> drivers/net/ethernet/qlogic/qede/qede_ptp.c | 20 ++++++------
>> drivers/net/ethernet/ti/cpts.c | 36 ++++++++++++----------
>> drivers/net/ethernet/ti/cpts.h | 1 -
>> include/linux/mlx5/driver.h | 1 -
>> include/linux/timecounter.h | 4 +--
>> include/sound/hdaudio.h | 1 -
>> kernel/time/timecounter.c | 28 ++++++++---------
>> sound/hda/hdac_stream.c | 7 +++--
>> virt/kvm/arm/arch_timer.c | 6 ++--
>> 28 files changed, 163 insertions(+), 182 deletions(-)
>>
> For Intel e1000e and igb drivers:
> Tested-by: Aaron Brown <aaron.f.brown@intel.com>
^ permalink raw reply
* [GIT PULL] Mediatek: 32-bit DT update for v4.15
From: Ryder Lee @ 2018-01-09 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1509846112.26038.22.camel@mtkswgap22>
On Fri, 2017-11-03 at 16:21 +0100, Arnd Bergmann wrote:
> On Fri, Nov 3, 2017 at 12:52 PM, Ryder Lee <ryder.lee@mediatek.com> wrote:
> > On Fri, 2017-11-03 at 10:40 +0100, Arnd Bergmann wrote:
> >> On Fri, Nov 3, 2017 at 2:37 AM, Ryder Lee <ryder.lee@mediatek.com> wrote:
>
> >> This should have the exact same effect as what you have in your tree,
> >> but if that works,
> >> we can merge that version and try to figure out why the kernel thinks
> >> they are different.
> >
> > I've tried this approach by using the 4-ports network card and got the
> > result:
> > pcieport 0000:00:01.0: assign IRQ: got 220
> > pcieport 0000:00:01.0: assigning IRQ 220
> > pcieport 0000:00:01.0: enabling device (0140 -> 0142)
> > pcieport 0000:00:01.0: enabling bus mastering
> > pcieport 0000:00:01.0: Signaling PME with IRQ 220
> > ....
> > igb 0000:01:00.0: assign IRQ: got 221
> > igb 0000:01:00.0: assigning IRQ 221
> > igb 0000:01:00.1: assign IRQ: got 221
> > igb 0000:01:00.1: assigning IRQ 221
> > igb 0000:01:00.2: assign IRQ: got 221
> > igb 0000:01:00.2: assigning IRQ 221
> > igb 0000:01:00.3: assign IRQ: got 221
> > igb 0000:01:00.3: assigning IRQ 221
> >
> > I think slot 1 should share its IRQ (220) with every device in the
> > hierarchy below this root port.
>
> Agreed, that is what I expected, too. I've looked at the of_pci_irq.c
> in more detail but couldn't come up with what happened. Can you
> try running with this patch or something like that to figure out where
> it takes the wrong turn?
>
> https://pastebin.com/MrMzwcmw
>
Hi Arnd,
I guess the problem is the first device attached to downstream side of a
link must be device 0 - it means that the 'slot' portion of pdev->devfn
should be 0 when PCIe enumeration. That's why we always mismatch to
interrupt-map = <0x0000 0 0 ... GIC_SPI 193 ...>
However, if we want to list all four interrupts for each slot, that
could work if fallback to device tree parsing:
https://elixir.free-electrons.com/linux/v4.15-rc7/source/drivers/of/of_pci_irq.c#L89
Then replace 'pdev->devfn' with 'of_pci_get_devfn(out_irq->np)'
But I still not sure the proper way to solve it.
Ryder.
^ permalink raw reply
* [PATCH v3 7/7] EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC
From: Jan Lübbe @ 2018-01-09 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2d257134ee344f128a80e5b17ca5c76f@svr-chch-ex1.atlnz.lc>
Hi Chris,
On Mon, 2018-01-08 at 22:00 +0000, Chris Packham wrote:
> Hi Jan,
>
> On 10/11/17 22:03, Jan Luebbe wrote:
> > Add support for the ECC functionality as found in the DDR RAM and
> > L2 cache controllers on the MV78230/MV78x60 SoCs. This driver has
> > been tested on the MV78460 (on a custom board with a DDR3 ECC
> > DIMM).
> >
> > Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
>
> What is the current state of this? I see there were some comments
> from Borislav that need addressing.
>
> I've got my patches for Armada-380 and 98dx3236 ready. They're
> fairly minor so I might send them anyway just to get any feedback.
> They probably could be incorporated into a v4 series if you are
> willing to carry them.
This series is still on my todo list, but I currently don't have the
time to work on it (and probably also not in the next weeks). If you
have some spare time to pick it up and address Borislav's comments, I
wouldn't mind at all. ;)
Thanks,
Jan
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v7 2/9] arm: omap: timer: Wrap the inline functions under OMAP2PLUS define
From: Sebastian Reichel @ 2018-01-09 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515478987-5786-3-git-send-email-j-keerthy@ti.com>
Hi,
On Tue, Jan 09, 2018 at 11:53:00AM +0530, Keerthy wrote:
> Wrap the inline functions under OMAP2PLUS/OMAP1 defines.
>
> Signed-off-by: Keerthy <j-keerthy@ti.com>
> Tested-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
-- Sebastian
> ---
> arch/arm/plat-omap/include/plat/dmtimer.h | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
> index dd79f30..862ad62 100644
> --- a/arch/arm/plat-omap/include/plat/dmtimer.h
> +++ b/arch/arm/plat-omap/include/plat/dmtimer.h
> @@ -276,6 +276,12 @@ struct omap_dm_timer {
> #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
> (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
>
> +/*
> + * The below are inlined to optimize code size for system timers. Other code
> + * should not need these at all, see
> + * include/linux/platform_data/pwm_omap_dmtimer.h
> + */
> +#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2PLUS)
> static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
> int posted)
> {
> @@ -414,5 +420,5 @@ static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
> {
> writel_relaxed(value, timer->irq_stat);
> }
> -
> +#endif /* CONFIG_ARCH_OMAP1 || CONFIG_ARCH_OMAP2PLUS */
> #endif /* __ASM_ARCH_DMTIMER_H */
> --
> 1.9.1
>
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* [PATCH v7 7/9] clocksource: timer-dm: Hook device platform data if not already assigned
From: Sebastian Reichel @ 2018-01-09 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515478987-5786-8-git-send-email-j-keerthy@ti.com>
Hi,
On Tue, Jan 09, 2018 at 11:53:05AM +0530, Keerthy wrote:
> From: Ladislav Michl <ladis@linux-mips.org>
>
> In the case of device tree boot the device platform data is usually
> NULL so hook the platform data obtained from the match.
> As part of un-constify the platform_data pointer.
>
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
-- Sebastian
> ---
> drivers/clocksource/timer-dm.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clocksource/timer-dm.c b/drivers/clocksource/timer-dm.c
> index 1cbd954..60db173 100644
> --- a/drivers/clocksource/timer-dm.c
> +++ b/drivers/clocksource/timer-dm.c
> @@ -806,14 +806,16 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
> struct omap_dm_timer *timer;
> struct resource *mem, *irq;
> struct device *dev = &pdev->dev;
> - const struct of_device_id *match;
> const struct dmtimer_platform_data *pdata;
> int ret;
>
> - match = of_match_device(of_match_ptr(omap_timer_match), dev);
> - pdata = match ? match->data : dev->platform_data;
> + pdata = of_device_get_match_data(dev);
> + if (!pdata)
> + pdata = dev_get_platdata(dev);
> + else
> + dev->platform_data = (void *)pdata;
>
> - if (!pdata && !dev->of_node) {
> + if (!pdata) {
> dev_err(dev, "%s: no platform data.\n", __func__);
> return -ENODEV;
> }
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
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* [PATCH V3 1/2] clk: imx: imx7d: add the snvs clock
From: Anson Huang @ 2018-01-09 9:20 UTC (permalink / raw)
To: linux-arm-kernel
According to the i.MX7D Reference Manual,
SNVS block has a clock gate, accessing SNVS block
would need this clock gate to be enabled, add it
into clock tree so that SNVS module driver can
operate this clock gate.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 1 +
include/dt-bindings/clock/imx7d-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 80dc211..f34f1ec 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -795,6 +795,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0);
clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
+ clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index e2f99ae..dc51904 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -452,5 +452,6 @@
#define IMX7D_OCOTP_CLK 439
#define IMX7D_NAND_RAWNAND_CLK 440
#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
-#define IMX7D_CLK_END 442
+#define IMX7D_SNVS_CLK 442
+#define IMX7D_CLK_END 443
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
--
1.9.1
^ permalink raw reply related
* [PATCH V3 2/2] ARM: dts: imx7s: add snvs rtc clock
From: Anson Huang @ 2018-01-09 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515489651-13488-1-git-send-email-Anson.Huang@nxp.com>
Add i.MX7 SNVS RTC clock.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
changes since v2:
improve the binding doc statement about clocks.
Documentation/devicetree/bindings/crypto/fsl-sec4.txt | 15 +++++++++++++++
arch/arm/boot/dts/imx7s.dtsi | 2 ++
2 files changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
index 76aec8a..7329f29 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
@@ -415,12 +415,25 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
value type: <u32>
Definition: LP register offset. default it is 0x34.
+ - clocks
+ Usage: required if SNVS LP RTC requires explicit enablement of clocks
+ Value type: <prop_encoded-array>
+ Definition: a clock specifier describing the clock required for
+ enabling and disabling SNVS LP RTC.
+
+ - clock-names
+ Usage: required if SNVS LP RTC requires explicit enablement of clocks
+ Value type: <string>
+ Definition: clock name string should be "snvs-rtc".
+
EXAMPLE
sec_mon_rtc_lp at 1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
interrupts = <93 2>;
regmap = <&snvs>;
offset = <0x34>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
=====================================================================
@@ -543,6 +556,8 @@ FULL EXAMPLE
regmap = <&sec_mon>;
offset = <0x34>;
interrupts = <93 2>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
snvs-pwrkey at 020cc000 {
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 9aa2bb9..02baf42 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -551,6 +551,8 @@
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
snvs_poweroff: snvs-poweroff {
--
1.9.1
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