* [PATCH v3] arm: exynos/s3c: dts: Remove leading 0x and 0s from bindings notation
From: Mathieu Malaterre @ 2018-05-03 18:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180502201153.7459-1-malat@debian.org>
Improve the DTS files by removing all the leading "0x" and zeros to fix the
following dtc warnings:
Warning (unit_address_format): Node /XXX unit name should not have leading "0x"
and
Warning (unit_address_format): Node /XXX unit name should not have leading 0s
Converted using the following command:
find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]\+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0\+\(.*\) {/@\1 {/g" {} +
For simplicity, two sed expressions were used to solve each warnings separately.
To make the regex expression more robust a few other issues were resolved,
namely setting unit-address to lower case, and adding a whitespace before the
the opening curly brace:
https://elinux.org/Device_Tree_Linux#Linux_conventions
This will solve as a side effect warning:
Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format error, expected "<lower>"
This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation")
Reported-by: David Daney <ddaney@caviumnetworks.com>
Suggested-by: Rob Herring <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Mathieu Malaterre <malat@debian.org>
---
v3: remove extra 0 preventing correct fixup
v2: intermediate patch contained unrelated changes. restrict to S3 and Exynos*
arch/arm/boot/dts/exynos5420.dtsi | 36 +++++++++++++--------------
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +-
arch/arm/boot/dts/s3c2416.dtsi | 8 +++---
3 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 2f3cb2a97f71..633952a96427 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -761,7 +761,7 @@
#include "exynos5420-tmu-sensor-conf.dtsi"
};
- sysmmu_g2dr: sysmmu at 0x10A60000 {
+ sysmmu_g2dr: sysmmu at 10a60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A60000 0x1000>;
interrupt-parent = <&combiner>;
@@ -771,7 +771,7 @@
#iommu-cells = <0>;
};
- sysmmu_g2dw: sysmmu at 0x10A70000 {
+ sysmmu_g2dw: sysmmu at 10a70000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A70000 0x1000>;
interrupt-parent = <&combiner>;
@@ -781,7 +781,7 @@
#iommu-cells = <0>;
};
- sysmmu_tv: sysmmu at 0x14650000 {
+ sysmmu_tv: sysmmu at 14650000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14650000 0x1000>;
interrupt-parent = <&combiner>;
@@ -792,7 +792,7 @@
#iommu-cells = <0>;
};
- sysmmu_gscl0: sysmmu at 0x13E80000 {
+ sysmmu_gscl0: sysmmu at 13e80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E80000 0x1000>;
interrupt-parent = <&combiner>;
@@ -803,7 +803,7 @@
#iommu-cells = <0>;
};
- sysmmu_gscl1: sysmmu at 0x13E90000 {
+ sysmmu_gscl1: sysmmu at 13e90000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E90000 0x1000>;
interrupt-parent = <&combiner>;
@@ -814,7 +814,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler0r: sysmmu at 0x12880000 {
+ sysmmu_scaler0r: sysmmu at 12880000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12880000 0x1000>;
interrupt-parent = <&combiner>;
@@ -824,7 +824,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler1r: sysmmu at 0x12890000 {
+ sysmmu_scaler1r: sysmmu at 12890000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12890000 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
@@ -833,7 +833,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler2r: sysmmu at 0x128A0000 {
+ sysmmu_scaler2r: sysmmu at 128a0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128A0000 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
@@ -842,7 +842,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler0w: sysmmu at 0x128C0000 {
+ sysmmu_scaler0w: sysmmu at 128c0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128C0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -852,7 +852,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler1w: sysmmu at 0x128D0000 {
+ sysmmu_scaler1w: sysmmu at 128d0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128D0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -862,7 +862,7 @@
#iommu-cells = <0>;
};
- sysmmu_scaler2w: sysmmu at 0x128E0000 {
+ sysmmu_scaler2w: sysmmu at 128e0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128E0000 0x1000>;
interrupt-parent = <&combiner>;
@@ -872,7 +872,7 @@
#iommu-cells = <0>;
};
- sysmmu_rotator: sysmmu at 0x11D40000 {
+ sysmmu_rotator: sysmmu at 11d40000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11D40000 0x1000>;
interrupt-parent = <&combiner>;
@@ -882,7 +882,7 @@
#iommu-cells = <0>;
};
- sysmmu_jpeg0: sysmmu at 0x11F10000 {
+ sysmmu_jpeg0: sysmmu at 11f10000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F10000 0x1000>;
interrupt-parent = <&combiner>;
@@ -892,7 +892,7 @@
#iommu-cells = <0>;
};
- sysmmu_jpeg1: sysmmu at 0x11F20000 {
+ sysmmu_jpeg1: sysmmu at 11f20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
@@ -901,7 +901,7 @@
#iommu-cells = <0>;
};
- sysmmu_mfc_l: sysmmu at 0x11200000 {
+ sysmmu_mfc_l: sysmmu at 11200000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11200000 0x1000>;
interrupt-parent = <&combiner>;
@@ -912,7 +912,7 @@
#iommu-cells = <0>;
};
- sysmmu_mfc_r: sysmmu at 0x11210000 {
+ sysmmu_mfc_r: sysmmu at 11210000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11210000 0x1000>;
interrupt-parent = <&combiner>;
@@ -923,7 +923,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimd1_0: sysmmu at 0x14640000 {
+ sysmmu_fimd1_0: sysmmu at 14640000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14640000 0x1000>;
interrupt-parent = <&combiner>;
@@ -934,7 +934,7 @@
#iommu-cells = <0>;
};
- sysmmu_fimd1_1: sysmmu at 0x14680000 {
+ sysmmu_fimd1_1: sysmmu at 14680000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14680000 0x1000>;
interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index d31249f25ccf..2f4f40882dab 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -23,7 +23,7 @@
stdout-path = "serial2:115200n8";
};
- firmware at 02073000 {
+ firmware at 2073000 {
compatible = "samsung,secure-firmware";
reg = <0x02073000 0x1000>;
};
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index 3c7385cab248..46cf85f3c18b 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -30,7 +30,7 @@
compatible = "samsung,s3c2416-irq";
};
- clocks: clock-controller at 0x4c000000 {
+ clocks: clock-controller at 4c000000 {
compatible = "samsung,s3c2416-clock";
reg = <0x4c000000 0x40>;
#clock-cells = <1>;
@@ -69,7 +69,7 @@
<&clocks SCLK_UART>;
};
- uart_3: serial at 5000C000 {
+ uart_3: serial at 5000c000 {
compatible = "samsung,s3c2440-uart";
reg = <0x5000C000 0x4000>;
interrupts = <1 18 24 4>, <1 18 25 4>;
@@ -80,7 +80,7 @@
status = "disabled";
};
- sdhci_1: sdhci at 4AC00000 {
+ sdhci_1: sdhci at 4ac00000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x4AC00000 0x100>;
interrupts = <0 0 21 3>;
@@ -91,7 +91,7 @@
status = "disabled";
};
- sdhci_0: sdhci at 4A800000 {
+ sdhci_0: sdhci at 4a800000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x4A800000 0x100>;
interrupts = <0 0 20 3>;
--
2.11.0
^ permalink raw reply related
* [PATCH net-next v2 00/15] ARM: sun8i: r40: Add Ethernet support
From: David Miller @ 2018-05-03 18:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503131257.rlqxetafejikmnji@flea>
From: Maxime Ripard <maxime.ripard@bootlin.com>
Date: Thu, 3 May 2018 15:12:57 +0200
> Hi Dave,
>
> On Wed, May 02, 2018 at 11:06:17AM -0400, David Miller wrote:
>> From: Chen-Yu Tsai <wens@csie.org>
>> Date: Wed, 2 May 2018 00:33:45 +0800
>>
>> > I should've mentioned that patches 3 ~ 10, and only these, should go
>> > through net-next. sunxi will handle the remaining clk, device tree, and
>> > soc driver patches.
>>
>> Ok, I just noticed this.
>>
>> Why don't you just post those patches separately as a series on their
>> own then, in order to avoid confusion?
>>
>> Then you can adjust the patch series header posting to explain the
>> non-net-next changes, where they got merged, and what they provide
>> in order to faciliate the net-next changes.
>
> I now that we usually have some feedback from non-net maintainers that
> they actually prefer seeing the full picture (and I also tend to
> prefer that as well) and having all the patches relevant to enable a
> particular feature, even if it means getting multiple maintainers
> involved.
>
> Just to make sure we understood you fully, do you want Chen-Yu to
> resend his serie following your comments, or was that just a general
> remark for next time?
Yeah, good questions.
I think it can be argued either way. For review having the complete
context is important.
But from a maintainer's standpoint, when there is any ambiguity
whatsoever about what patches go into this tree or that, it is really
frowned upon and is quite error prone.
Also, that header posting is _SO_ important. It explains the series.
But for these 'partial apply' situations the header posting refers
to patches not in the series.
This looks terrible in the logs, when, as I do, the header posting
text is added to a marge commit for the series. People will read it
and say "where are all of these other changes mentioned in the text?
was this series misapplied?"
That's why, maybe after the review is successful, I want the actual
patch series standalone with appropriately updated header posting
text.
^ permalink raw reply
* [PATCH 7/7] arm64: allwinner: h6: add PCF8563 RTC on Pine H64 board
From: Icenowy Zheng @ 2018-05-03 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503183847.11046-1-icenowy@aosc.io>
Pine H64 board has a PCF8563 dedicated RTC connected to its R_I2C bus.
Enable the R_I2C bus and add the RTC to the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index d36de5eb81f3..b6f2d6b2ecae 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -22,6 +22,16 @@
};
};
+&r_i2c {
+ status = "okay";
+
+ pcf8563: rtc at 51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
--
2.15.1
^ permalink raw reply related
* [PATCH 6/7] arm64: allwinner: h6: add R_I2C controller
From: Icenowy Zheng @ 2018-05-03 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503183847.11046-1-icenowy@aosc.io>
Allwinner H6 SoC has a R_I2C controller wired to the PL0/PL1 pins, which
are used in the reference design to connect AXP805 PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index b0b342c8c189..37c2e11fca2e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -5,7 +5,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -204,6 +206,24 @@
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+
+ r_i2c_pins: r-i2c {
+ pins = "PL0", "PL1";
+ function = "s_i2c";
+ };
+ };
+
+ r_i2c: i2c at 7081400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x07081400 0x400>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB2_I2C>;
+ resets = <&r_ccu RST_R_APB2_I2C>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
--
2.15.1
^ permalink raw reply related
* [PATCH 5/7] arm64: allwinner: h6: add R_INTC interrupt controller
From: Icenowy Zheng @ 2018-05-03 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503183847.11046-1-icenowy@aosc.io>
Allwinner H6 SoC has also a R_INTC interrupt controller like Allwinner
A64 SoC, but has its base address changed due to the memory map change
in H6.
Add it into the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index a18b78fb4850..b0b342c8c189 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -184,6 +184,15 @@
#reset-cells = <1>;
};
+ r_intc: interrupt-controller at 7021000 {
+ compatible = "allwinner,sun50i-h6-r-intc",
+ "allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x07021000 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
r_pio: pinctrl at 7022000 {
compatible = "allwinner,sun50i-h6-r-pinctrl";
reg = <0x07022000 0x400>;
--
2.15.1
^ permalink raw reply related
* [PATCH 4/7] arm64: allwinner: h6: add node for R_PIO pin controller
From: Icenowy Zheng @ 2018-05-03 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503183847.11046-1-icenowy@aosc.io>
Allwinner H6 SoC has a R_PIO pin controller which controls PL and PM
GPIO banks.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index db9da343ba46..a18b78fb4850 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -183,5 +183,18 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ r_pio: pinctrl at 7022000 {
+ compatible = "allwinner,sun50i-h6-r-pinctrl";
+ reg = <0x07022000 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.15.1
^ permalink raw reply related
* [PATCH 3/7] pinctrl: sunxi: add support for H6 R_PIO pin controller
From: Icenowy Zheng @ 2018-05-03 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503183847.11046-1-icenowy@aosc.io>
Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 128 +++++++++++++++++++++
4 files changed, 134 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 64bc5c2a76da..258a4648ab81 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -28,6 +28,7 @@ Required properties:
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
"allwinner,sun50i-h6-pinctrl"
+ "allwinner,sun50i-h6-r-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 5de1f63b07bb..95282cda6cee 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -81,4 +81,8 @@ config PINCTRL_SUN50I_H6
def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H6_R
+ def_bool ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 3c4aec6611e9..adb8443aa55c 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o
+obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
new file mode 100644
index 000000000000..4557e18d5989
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H6 R_PIO pin controller driver
+ *
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on pinctrl-sun6i-a31-r.c, which is:
+ * Copyright (C) 2014 Boris Brezillon
+ * Boris Brezillon <boris.brezillon@free-electrons.com>
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_h6_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_pwm"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_cir_rx"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_w1"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2), /* PM_EINT2 */
+ SUNXI_FUNCTION(0x3, "1wire")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = {
+ .pins = sun50i_h6_r_pins,
+ .npins = ARRAY_SIZE(sun50i_h6_r_pins),
+ .pin_base = PL_BASE,
+ .irq_banks = 2,
+};
+
+static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun50i_h6_r_pinctrl_data);
+}
+
+static const struct of_device_id sun50i_h6_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-h6-r-pinctrl", },
+ {}
+};
+
+static struct platform_driver sun50i_h6_r_pinctrl_driver = {
+ .probe = sun50i_h6_r_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-h6-r-pinctrl",
+ .of_match_table = sun50i_h6_r_pinctrl_match,
+ },
+};
+builtin_platform_driver(sun50i_h6_r_pinctrl_driver);
--
2.15.1
^ permalink raw reply related
* [PATCH 2/7] arm64: allwinner: h6: add PRCM CCU device node
From: Icenowy Zheng @ 2018-05-03 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503183847.11046-1-icenowy@aosc.io>
Allwinner H6 has also a PRCM CCU.
Add its device node into the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 4debc3962830..db9da343ba46 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -173,5 +173,15 @@
resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
+
+ r_ccu: clock at 7010000 {
+ compatible = "allwinner,sun50i-h6-r-ccu";
+ reg = <0x07010000 0x400>;
+ clocks = <&osc24M>, <&osc32k>, <&iosc>,
+ <&ccu CLK_PLL_PERIPH0>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
--
2.15.1
^ permalink raw reply related
* [PATCH 1/7] clk: sunxi-ng: add support for H6 PRCM CCU
From: Icenowy Zheng @ 2018-05-03 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503183847.11046-1-icenowy@aosc.io>
The H6 has clock/reset controls in PRCM part, like old SoCs such as H3
and A64. However, the PRCM CCU is rearranged; the register arragement
is now similar to the main CCU of H6, and the PRCM now has two APB
buses to control -- one is clocked from AHB clock derivde from AR100
clock, the other is clocked from the same mux with AR100 clock.
Therefore a new driver is written for it.
As there's no official document about the PRCM in H6, all the information
are indirectly collected from BSP and parts of the document, and the
information source is noted as comments in the driver's source code. If
reliable information is provided furtherly, the driver needs to be
rechecked.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../devicetree/bindings/clock/sunxi-ccu.txt | 3 +-
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 207 +++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 19 ++
include/dt-bindings/clock/sun50i-h6-r-ccu.h | 24 +++
include/dt-bindings/reset/sun50i-h6-r-ccu.h | 17 ++
7 files changed, 275 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
create mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 460ef27b1008..47d2e902ced4 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -21,6 +21,7 @@ Required properties :
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
+ - "allwinner,sun50i-h6-r-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
@@ -35,7 +36,7 @@ Required properties :
For the main CCU on H6, one more clock is needed:
- "iosc": the SoC's internal frequency oscillator
-For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
+For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 79dfd296c3d1..826674d090fd 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -16,6 +16,11 @@ config SUN50I_H6_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+config SUN50I_H6_R_CCU
+ bool "Support for the Allwinner H6 PRCM CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
config SUN4I_A10_CCU
bool "Support for the Allwinner A10/A20 CCU"
default MACH_SUN4I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 9ac0fb948101..49454700f2e5 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,6 +23,7 @@ obj-y += ccu_mp.o
# SoC support
obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
+obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
new file mode 100644
index 000000000000..27554eaf6929
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-h6-r.h"
+
+/*
+ * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
+ * clock definitions in the BSP source code.
+ */
+
+static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
+ "pll-periph0", "iosc" };
+static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
+ { .index = 2, .shift = 0, .width = 5 },
+};
+
+static struct ccu_div ar100_clk = {
+ .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .mux = {
+ .shift = 24,
+ .width = 2,
+
+ .var_predivs = ar100_r_apb2_predivs,
+ .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
+ },
+
+ .common = {
+ .reg = 0x000,
+ .features = CCU_FEATURE_VARIABLE_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS("ar100",
+ ar100_r_apb2_parents,
+ &ccu_div_ops,
+ 0),
+ },
+};
+
+static CLK_FIXED_FACTOR(r_ahb_clk, "r-ahb", "ar100", 1, 1, 0);
+
+static struct ccu_div r_apb1_clk = {
+ .div = _SUNXI_CCU_DIV(0, 2),
+
+ .common = {
+ .reg = 0x00c,
+ .hw.init = CLK_HW_INIT("r-apb1",
+ "r-ahb",
+ &ccu_div_ops,
+ 0),
+ },
+};
+
+static struct ccu_div r_apb2_clk = {
+ .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .mux = {
+ .shift = 24,
+ .width = 2,
+
+ .var_predivs = ar100_r_apb2_predivs,
+ .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
+ },
+
+ .common = {
+ .reg = 0x010,
+ .features = CCU_FEATURE_VARIABLE_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
+ ar100_r_apb2_parents,
+ &ccu_div_ops,
+ 0),
+ },
+};
+
+/*
+ * Information about the gate/resets are gathered from the clock header file
+ * in the BSP source code, although most of them are unused. The existence
+ * of the hardware block is verified with "3.1 Memory Mapping" chapter in
+ * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
+ * with "3.3.2.1 System Bus Tree" chapter inthe same document.
+ */
+static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
+ 0x11c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
+ 0x12c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb1_pwm_clk, "r-apb1-pwm", "r-apb1",
+ 0x13c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2",
+ 0x18c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
+ 0x19c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
+ 0x1cc, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
+ 0x1cc, BIT(0), 0);
+
+/* Information of IR(RX) mod clock is gathered from BSP source code */
+static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
+ r_mod0_default_parents, 0x1c0,
+ 0, 5, /* M */
+ 8, 2, /* P */
+ 24, 1, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+/*
+ * BSP didn't use the 1-wire function at all now, and the information about
+ * this mod clock is guessed from the IR mod clock above. The existence of
+ * this mod clock is proven by BSP clock header, and the dividers are verified
+ * by contents in the 1-wire related chapter of the User Manual.
+ */
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
+ r_mod0_default_parents, 0x1e0,
+ 0, 5, /* M */
+ 8, 2, /* P */
+ 24, 1, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
+ &ar100_clk.common,
+ &r_apb1_clk.common,
+ &r_apb2_clk.common,
+ &r_apb1_timer_clk.common,
+ &r_apb1_twd_clk.common,
+ &r_apb1_pwm_clk.common,
+ &r_apb2_uart_clk.common,
+ &r_apb2_i2c_clk.common,
+ &r_apb1_ir_clk.common,
+ &r_apb1_w1_clk.common,
+ &ir_clk.common,
+ &w1_clk.common,
+};
+
+static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
+ .hws = {
+ [CLK_AR100] = &ar100_clk.common.hw,
+ [CLK_R_AHB] = &r_ahb_clk.hw,
+ [CLK_R_APB1] = &r_apb1_clk.common.hw,
+ [CLK_R_APB2] = &r_apb2_clk.common.hw,
+ [CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
+ [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
+ [CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
+ [CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
+ [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
+ [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
+ [CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw,
+ [CLK_IR] = &ir_clk.common.hw,
+ [CLK_W1] = &w1_clk.common.hw,
+ },
+ .num = CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
+ [RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
+ [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
+ [RST_R_APB1_PWM] = { 0x13c, BIT(16) },
+ [RST_R_APB2_UART] = { 0x18c, BIT(16) },
+ [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
+ [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
+ [RST_R_APB1_W1] = { 0x1ec, BIT(16) },
+};
+
+static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
+ .ccu_clks = sun50i_h6_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
+
+ .hw_clks = &sun50i_h6_r_hw_clks,
+
+ .resets = sun50i_h6_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
+};
+
+static void __init sunxi_r_ccu_init(struct device_node *node,
+ const struct sunxi_ccu_desc *desc)
+{
+ void __iomem *reg;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg)) {
+ pr_err("%pOF: Could not map the clock registers\n", node);
+ return;
+ }
+
+ sunxi_ccu_probe(node, reg, desc);
+}
+
+static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
+{
+ sunxi_r_ccu_init(node, &sun50i_h6_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
+ sun50i_h6_r_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
new file mode 100644
index 000000000000..782117dc0b28
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _CCU_SUN50I_H6_R_H
+#define _CCU_SUN50I_H6_R_H
+
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+
+/* AHB/APB bus clocks are not exported except APB1 for R_PIO */
+#define CLK_R_AHB 1
+
+#define CLK_R_APB2 3
+
+#define CLK_NUMBER (CLK_W1 + 1)
+
+#endif /* _CCU_SUN50I_H6_R_H */
diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
new file mode 100644
index 000000000000..76136132a13e
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+
+#define CLK_AR100 0
+
+#define CLK_R_APB1 2
+
+#define CLK_R_APB1_TIMER 4
+#define CLK_R_APB1_TWD 5
+#define CLK_R_APB1_PWM 6
+#define CLK_R_APB2_UART 7
+#define CLK_R_APB2_I2C 8
+#define CLK_R_APB1_IR 9
+#define CLK_R_APB1_W1 10
+
+#define CLK_IR 11
+#define CLK_W1 12
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
new file mode 100644
index 000000000000..01c84dba49a4
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+
+#define RST_R_APB1_TIMER 0
+#define RST_R_APB1_TWD 1
+#define RST_R_APB1_PWM 2
+#define RST_R_APB2_UART 3
+#define RST_R_APB2_I2C 4
+#define RST_R_APB1_IR 5
+#define RST_R_APB1_W1 6
+
+#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */
--
2.15.1
^ permalink raw reply related
* [PATCH 0/7] Allwinner H6 R_{PIO,INTC,I2C} support
From: Icenowy Zheng @ 2018-05-03 18:38 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds support for Allwinner H6's R_{PIO,INTC,I2C}
peripherals. They are in the "CPUS" power domain, powered by VDD-CPUS
rather than VDD-SYS.
R_PIO controls the PL/PM GPIO banks, R_INTC controls NMI, and R_I2C
controls the I2C at PL0/1.
A PCF8563 RTC is attached on R_I2C on Pine H64, which is added to the
device tree. An AXP805 (a variation of AXP806 with different default
value customization) is attached on the bus too, however as its driver
currently lacks self-work mode support, it will be activated in another
patchset.
In order to support R_{PIO,I2C}, a PRCM CCU driver is introduced. As the
PRCM clock part is totally different with older SoCs (from A31 to H5),
the driver for H6 is a new one, not reusing the old code.
Icenowy Zheng (7):
clk: sunxi-ng: add support for H6 PRCM CCU
arm64: allwinner: h6: add PRCM CCU device node
pinctrl: sunxi: add support for H6 R_PIO pin controller
arm64: allwinner: h6: add node for R_PIO pin controller
arm64: allwinner: h6: add R_INTC interrupt controller
arm64: allwinner: h6: add R_I2C controller
arm64: allwinner: h6: add PCF8563 RTC on Pine H64 board
.../devicetree/bindings/clock/sunxi-ccu.txt | 3 +-
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 +
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 52 ++++++
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 207 +++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 19 ++
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 128 +++++++++++++
include/dt-bindings/clock/sun50i-h6-r-ccu.h | 24 +++
include/dt-bindings/reset/sun50i-h6-r-ccu.h | 17 ++
13 files changed, 471 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
create mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h
--
2.15.1
^ permalink raw reply
* [PATCH] spi: bcm2835aux: ensure interrupts are enabled for shared handler
From: Stefan Wahren @ 2018-05-03 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503180945.3502-1-robh@kernel.org>
Hi,
[added Martin, Noralf and Phil]
> Rob Herring <robh@kernel.org> hat am 3. Mai 2018 um 20:09 geschrieben:
>
>
> The BCM2835 AUX SPI has a shared interrupt line (with AUX UART).
> Downstream fixes this with an AUX irqchip to demux the IRQ sources and a
> DT change which breaks compatibility with older kernels. The AUX irqchip
> was already rejected for upstream[1] and the DT change would break
> working systems if the DTB is updated to a newer one. The latter issue
> was brought to my attention by Alex Graf.
>
> The root cause however is a bug in the shared handler. Shared handlers
> must check that interrupts are actually enabled before servicing the
> interrupt. Add a check that the TXEMPTY or IDLE interrupts are enabled.
>
> [1] https://patchwork.kernel.org/patch/9781221/
>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Eric Anholt <eric@anholt.net>
> Cc: Stefan Wahren <stefan.wahren@i2se.com>
> Cc: Florian Fainelli <f.fainelli@gmail.com>
> Cc: Ray Jui <rjui@broadcom.com>
> Cc: Scott Branden <sbranden@broadcom.com>
> Cc: bcm-kernel-feedback-list at broadcom.com
> Cc: linux-spi at vger.kernel.org
> Cc: linux-rpi-kernel at lists.infradead.org
> Cc: linux-arm-kernel at lists.infradead.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> Compile tested only. I'll add something to the related github issue on
> this and hopefully someone can test and confirm.
>
> I'm assuming the 8250 driver can handle shared irqs correctly.
>
> Rob
>
> drivers/spi/spi-bcm2835aux.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/spi/spi-bcm2835aux.c b/drivers/spi/spi-bcm2835aux.c
> index 1431cb98fe40..3094d818cf06 100644
> --- a/drivers/spi/spi-bcm2835aux.c
> +++ b/drivers/spi/spi-bcm2835aux.c
> @@ -184,6 +184,11 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
> struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
> irqreturn_t ret = IRQ_NONE;
>
> + /* IRQ may be shared, so return if our interrupts are disabled */
> + if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
> + (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
> + return ret;
> +
> /* check if we have data to read */
> while (bs->rx_len &&
> (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
> --
> 2.17.0
does anyone have a setup to test this patch (i assume it requires a compute module)?
@Rob: Thank you very much for this patch
^ permalink raw reply
* [PATCH 1/2] ARM: dts: am335x: Replace numeric pinmux address with macro defines
From: Grygorii Strashko @ 2018-05-03 18:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503161916.GS98604@atomide.com>
On 05/03/2018 11:19 AM, Tony Lindgren wrote:
> * Grygorii Strashko <grygorii.strashko@ti.com> [180503 15:54]:
>>
>>
>> On 04/30/2018 12:31 PM, Tony Lindgren wrote:
>>> Hi,
>>>
>>> * Christina Quast <cquast@baylibre.com> [180430 11:23]:
>>>> The values are extraced from the "AM335x SitaraTM Processors Technical
>>>> Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the
>>>> file autogenerated by TI PinMux.
>>>
>>> This certainly makes things easier to mux :)
>>>
>>> Have you verified that the registers are the same across all am335x
>>> models and different revisions?
>>>
>>> It used to be that different SoC revisions could have different
>>> amount of registers and also different options in some cases.
>>>
>>>> +#define AM335X_CONTROL_REVISION 0x0
>>>> +#define AM335X_CONTROL_HWINFO 0x4
>>>> +#define AM335X_CONTROL_SYSCONFIG 0x10
>>>> +#define AM335X_CONTROL_STATUS 0x40
>>>
>>> You should only list the padconf mux registers here, no need to
>>> list any of the controller registers.
>>>
>>
>> To be honest, I do think it's right thing to do - DT by itself is
>> documentation and previously DT maintainers were not very happy regarding
>> introducing more defines instead of const.
>
> Sounds like you mean "I don't think" above instead of "I do think"?
> Care to clarify..
i don't.. sry
>
>> Adding such defines will introduce big headers in Linux common or
>> platform folders again which we've just got rid of.
>>
>> If smth is unclear - comments can be used in DT.
>>
>> Just my 5c.
>
> The problem earlier was that we had just too many variants as
> the padconf registers got changed even between SoC revisions.
> Not always and not for many registers but still. The padconf
> register range seems to stay the same for a SoC though.
>
> I do see value at being able to mux the registers easier though.
--
regards,
-grygorii
^ permalink raw reply
* [PATCH] spi: bcm2835aux: ensure interrupts are enabled for shared handler
From: Rob Herring @ 2018-05-03 18:09 UTC (permalink / raw)
To: linux-arm-kernel
The BCM2835 AUX SPI has a shared interrupt line (with AUX UART).
Downstream fixes this with an AUX irqchip to demux the IRQ sources and a
DT change which breaks compatibility with older kernels. The AUX irqchip
was already rejected for upstream[1] and the DT change would break
working systems if the DTB is updated to a newer one. The latter issue
was brought to my attention by Alex Graf.
The root cause however is a bug in the shared handler. Shared handlers
must check that interrupts are actually enabled before servicing the
interrupt. Add a check that the TXEMPTY or IDLE interrupts are enabled.
[1] https://patchwork.kernel.org/patch/9781221/
Cc: Alexander Graf <agraf@suse.de>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Eric Anholt <eric@anholt.net>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list at broadcom.com
Cc: linux-spi at vger.kernel.org
Cc: linux-rpi-kernel at lists.infradead.org
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
Compile tested only. I'll add something to the related github issue on
this and hopefully someone can test and confirm.
I'm assuming the 8250 driver can handle shared irqs correctly.
Rob
drivers/spi/spi-bcm2835aux.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/spi/spi-bcm2835aux.c b/drivers/spi/spi-bcm2835aux.c
index 1431cb98fe40..3094d818cf06 100644
--- a/drivers/spi/spi-bcm2835aux.c
+++ b/drivers/spi/spi-bcm2835aux.c
@@ -184,6 +184,11 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
irqreturn_t ret = IRQ_NONE;
+ /* IRQ may be shared, so return if our interrupts are disabled */
+ if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
+ (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
+ return ret;
+
/* check if we have data to read */
while (bs->rx_len &&
(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
--
2.17.0
^ permalink raw reply related
* [linux-sunxi] [PATCH 3/3] arm64: allwinner: h6: enable MMC0/2 on Pine H64
From: Maxime Ripard @ 2018-05-03 18:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <aa2d6072-87a5-cd52-d3a5-17df889e6bc9@arm.com>
On Wed, May 02, 2018 at 12:01:53PM +0100, Andre Przywara wrote:
> >>>> It looks like there are more users of those power rails, so we could
> >>>> keep those supplies connected to these fixed regulators here, even with
> >>>> AXP-805 support in the kernel.
> >>>
> >>> It's not a good choice.
> >>>
> >>>>
> >>>> Or we keep this back until we get proper AXP support in the kernel? I
> >>>> guess it's quite close to the existing PMICs, so it might be more a
> >>>> copy&paste exercise to support the AXP-805?
> >>>
> >>> It's not a reason to keep it back.
> >>
> >> So I compared the manuals of the AXP806 and the AXP805, the register
> >> interface looks identical to me. I only have a (somewhat) Chinese
> >> version of the AXP806 manual, so couldn't really find the difference
> >> between the two. Do you know more about it? Is it just maybe the
> >> packaging and the electrical properties (like max current supported)?
> >>
> >> If the I2C register interface is really the same, we could just add the
> >> DT nodes for the regulator and be done.
> >
> > And that argument is only valid if you 100% trust the fact that both
> > datasheet are complete and accurate.
> >
> > And experience show that you can't.
>
> Well, but I wonder how paranoid we are going to be? And in this case we
> have confirmation from Wink that they are the same.
Paranoid enough so that we don't blindly trust that the reviewer had a
coffee, no interruptions or moment of distraction, or that the
datasheet is correct.
But not so paranoid that having the driver running on a kernel is
enough.
> So I think we can go with just a DT addition, given that we test it
> and confirm that it works for our use case. Should we discover
> something odd or undocumented later, I'd consider this a bug fix,
> which we then (and only then!) could fix by adding the compatible
> string to the driver. Any DT would be fine already, because we list
> both compatible strings in there.
In this particular case, yeah, it seems reasonable.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v2] pinctrl: msm: fix gpio-hog related boot issues
From: Christian Lamparter @ 2018-05-03 17:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdaEYFerKQa4QRCFEg2TOrdbnF6SfVZ9chLpmCxSUNcZBw@mail.gmail.com>
On Mittwoch, 2. Mai 2018 14:14:39 CEST Linus Walleij wrote:
> On Thu, Apr 26, 2018 at 11:47 PM, Christian Lamparter
> <chunkeey@gmail.com> wrote:
> > On Thu, Apr 26, 2018 11:12:21 CEST Linus Walleij wrote:
>
> >> I think I replied in some other mail that I think we need to
> >> be backwards compatible and it's not too hard to do
> >> both. (Correct me if I'm wrong.)
> >
> > I think so too, I looked around and found that the nvidia pinctrl was
> > doing something similar with of_find_property():
> > <https://elixir.bootlin.com/linux/v4.17-rc2/source/drivers/pinctrl/tegra/pinctrl-tegra.c#L652>
> > | has_prop = of_find_property(np, "gpio-ranges", NULL);
> >
> > However this looks kinda funny, since "has_prob" is declared as a bool
> > and of_find_property() returns a pointer to a "struct property"....
> > Tell you what: If nobody beats me to it, I'll sent a patch for this after
> > the pinctrl-msm's gpio-hog has been dealt with. :)
>
> Yeah the nVidia driver is one of the oldest and also at the time
> DT was kind of new. I haven't heard from Stephen for a while
> but I bet he will pop up, else check with Laxman, he's got
> a good grip on nVidia pinctrl+GPIO as well.
All in good time.
But first @Bjorn and @Andy or @David can you please look and
review v4 "pinctrl: msm: fix gpio-hog related boot issues"
<https://patchwork.kernel.org/patch/10339129/>
Thanks.
> > The MR24 craze is mostly over by now. You can still find a few. However
> > some listings are now selling them with OpenWrt/LEDE for ~$40.
> >
> > And obviously, this cycle will continue on, but now with the old wave1
> > 802.11ac gear that gets replaced. In fact this business has spawned
> > companies that are actively working on supporting "old" enterprise gear
> > via their own OpenWrt/LEDE derivatives.
>
> Haha that is just awesome :D
> I hope they salvage a lot of them.
Yes, I'm aware of that some of them where put to good use in the
Personal Telco Projec (501(c)(3) non-profit organization in Portland, Oregon):
<https://personaltelco.net/wiki/PersonalTelco>
And they have been somewhat vocal about it too:
<https://groups.google.com/forum/#!msg/ptp-general/RZ-VjKFonVo/cQgnGn2wAgAJ>
"The MR24 is a dual-band 802.11n 3x3 MIMO access point with a single
ethernet port. They are "last-gen" devices, and are starting to show up
on ebay at reasonable prices as Meraki's deep-pocket cloud-management
enterprise users are beginning to "upgrade" to 802.11ac gear. Note that
802.11n in this case means a fully-open-source driver (ath9k). 802.11ac
drivers involve firmware blobs across the board. You don't get
super-wide 5GHz channels, but you get freedom. "
;)
By the way, it gets even weirder. In the past (and to this day) Meraki has
given away their current crop of enterprise APs via their
"Free AP for IT Professionals" <https://meraki.cisco.com/tc/freeap> program.
Of course, the main idea probably was to get them all "hooked/sold" on their
cloud-management firmware. Because of course that "Free AP" is intended to be
only good for the lifespan of included the 3-year license. However,
"IT Professionals" do have their own mind and that's why there is some
continued interest in making alternative firmwares for these devices.
Best Regards,
Christian
^ permalink raw reply
* [PATCH v2 05/27] dts: bindings: Document device tree binding for CATU
From: Mathieu Poirier @ 2018-05-03 17:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180501131057.GA15706@rob-hp-laptop>
On 1 May 2018 at 07:10, Rob Herring <robh@kernel.org> wrote:
> On Tue, May 01, 2018 at 10:10:35AM +0100, Suzuki K Poulose wrote:
>> Document CATU device-tree bindings. CATU augments the TMC-ETR
>> by providing an improved Scatter Gather mechanism for streaming
>> trace data to non-contiguous system RAM pages.
>>
>> Cc: devicetree at vger.kernel.org
>> Cc: frowand.list at gmail.com
>> Cc: Rob Herring <robh@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Mathieu Poirier <mathieu.poirier@arm.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> .../devicetree/bindings/arm/coresight.txt | 52 ++++++++++++++++++++++
>> 1 file changed, 52 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
>> index 15ac8e8..cdd84d0 100644
>> --- a/Documentation/devicetree/bindings/arm/coresight.txt
>> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
>> @@ -39,6 +39,8 @@ its hardware characteristcs.
>>
>> - System Trace Macrocell:
>> "arm,coresight-stm", "arm,primecell"; [1]
>> + - Coresight Address Translation Unit (CATU)
>> + "arm, coresight-catu", "arm,primecell";
>
> spurious space ^
>
>>
>> * reg: physical base address and length of the register
>> set(s) of the component.
>> @@ -86,6 +88,9 @@ its hardware characteristcs.
>> * arm,buffer-size: size of contiguous buffer space for TMC ETR
>> (embedded trace router)
>>
>> +* Optional property for CATU :
>> + * interrupts : Exactly one SPI may be listed for reporting the address
>> + error
>
> Somewhere you need to define the ports for the CATU.
>
>>
>> Example:
>>
>> @@ -118,6 +123,35 @@ Example:
>> };
>> };
>>
>> + etr at 20070000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0 0x20070000 0 0x1000>;
>> +
>> + clocks = <&oscclk6a>;
>> + clock-names = "apb_pclk";
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* input port */
>> + port at 0 {
>> + reg = <0>;
>> + etr_in_port: endpoint {
>> + slave-mode;
>> + remote-endpoint = <&replicator2_out_port0>;
>> + };
>> + };
>> +
>> + /* CATU link represented by output port */
>> + port at 1 {
>> + reg = <0>;
>
> While common in the Coresight bindings, having unit-address and reg not
> match is an error. Mathieu and I discussed this a bit as dtc now warns
> on these.
>
> Either reg should be 1 here, or 'ports' needs to be split into input and
> output ports. My preference would be the former, but Mathieu objected to
> this not reflecting the the h/w numbering.
Suzuki, as we discuss this is related to your work on revamping CS
bindings for ACPI. Until that gets done and to move forward with this
set I suggest you abide to Rob's request.
>
> Rob
^ permalink raw reply
* [PATCH 2/2] arm64: Clear the stack
From: Alexander Popov @ 2018-05-03 17:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503071917.xm2xvgagvzkworay@salmiak>
Hello Mark and Laura,
Let me join the discussion. Mark, thanks for your feedback!
On 03.05.2018 10:19, Mark Rutland wrote:
> Hi Laura,
>
> On Wed, May 02, 2018 at 01:33:26PM -0700, Laura Abbott wrote:
>>
>> Implementation of stackleak based heavily on the x86 version
>>
>> Signed-off-by: Laura Abbott <labbott@redhat.com>
>> ---
>> Now written in C instead of a bunch of assembly.
>
> This looks neat!
>
> I have a few minor comments below.
>
>> diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
>> index bf825f38d206..0ceea613c65b 100644
>> --- a/arch/arm64/kernel/Makefile
>> +++ b/arch/arm64/kernel/Makefile
>> @@ -55,6 +55,9 @@ arm64-reloc-test-y := reloc_test_core.o reloc_test_syms.o
>> arm64-obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
>> arm64-obj-$(CONFIG_ARM_SDE_INTERFACE) += sdei.o
>>
>> +arm64-obj-$(CONFIG_GCC_PLUGIN_STACKLEAK) += erase.o
>> +KASAN_SANITIZE_erase.o := n
>
> I suspect we want to avoid the full set of instrumentation suspects here, e.g.
> GKOV, KASAN, UBSAN, and KCOV.
I've disabled KASAN instrumentation for that file on x86 because erase_kstack()
intentionally writes to the stack and causes KASAN false positive reports.
But I didn't see any conflicts with other types of instrumentation that you
mentioned.
>> +
>> obj-y += $(arm64-obj-y) vdso/ probes/
>> obj-m += $(arm64-obj-m)
>> head-y := head.o
>> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
>> index ec2ee720e33e..3144f1ebdc18 100644
>> --- a/arch/arm64/kernel/entry.S
>> +++ b/arch/arm64/kernel/entry.S
>> @@ -401,6 +401,11 @@ tsk .req x28 // current thread_info
>>
>> .text
>>
>> + .macro ERASE_KSTACK
>> +#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
>> + bl erase_kstack
>> +#endif
>> + .endm
>
> Nit: The rest of our asm macros are lower-case -- can we stick to that here?
>
>> /*
>> * Exception vectors.
>> */
>> @@ -906,6 +911,7 @@ ret_to_user:
>> cbnz x2, work_pending
>> finish_ret_to_user:
>> enable_step_tsk x1, x2
>> + ERASE_KSTACK
>> kernel_exit 0
>> ENDPROC(ret_to_user)
>
> I believe we also need this in ret_fast_syscall.
>
> [...]
>
>> +asmlinkage void erase_kstack(void)
>> +{
>> + unsigned long p = current->thread.lowest_stack;
>> + unsigned long boundary = p & ~(THREAD_SIZE - 1);
>> + unsigned long poison = 0;
>> + const unsigned long check_depth = STACKLEAK_POISON_CHECK_DEPTH /
>> + sizeof(unsigned long);
>> +
>> + /*
>> + * Let's search for the poison value in the stack.
>> + * Start from the lowest_stack and go to the bottom.
>> + */
>> + while (p > boundary && poison <= check_depth) {
>> + if (*(unsigned long *)p == STACKLEAK_POISON)
>> + poison++;
>> + else
>> + poison = 0;
>> +
>> + p -= sizeof(unsigned long);
>> + }
>> +
>> + /*
>> + * One long int at the bottom of the thread stack is reserved and
>> + * should not be poisoned (see CONFIG_SCHED_STACK_END_CHECK).
>> + */
>> + if (p == boundary)
>> + p += sizeof(unsigned long);
>
> I wonder if end_of_stack() should be taught about CONFIG_SCHED_STACK_END_CHECK,
> given that's supposed to return the last *usable* long on the stack, and we
> don't account for this elsewhere.
I would be afraid to change the meaning of end_of_stack()... Currently it
considers that magic long as usable (include/linux/sched/task_stack.h):
#define task_stack_end_corrupted(task) \
(*(end_of_stack(task)) != STACK_END_MAGIC)
> If we did, then IIUC we could do:
>
> unsigned long boundary = (unsigned long)end_of_stack(current);
>
> ... at the start of the function, and not have to worry about this explicitly.
I should mention that erase_kstack() can be called from x86 trampoline stack.
That's why the boundary is calculated from the lowest_stack.
>> +
>> +#ifdef CONFIG_STACKLEAK_METRICS
>> + current->thread.prev_lowest_stack = p;
>> +#endif
>> +
>> + /*
>> + * So let's write the poison value to the kernel stack.
>> + * Start from the address in p and move up till the new boundary.
>> + */
>> + boundary = current_stack_pointer;
>
> I worry a little that the compiler can move the SP during a function's
> lifetime, but maybe that's only the case when there are VLAs, or something like
> that?
Oh, I don't know.
However, erase_kstack() doesn't call anything except simple inline functions.
And as I see from its disasm on x86, the local variables reside in registers.
>> +
>> + BUG_ON(boundary - p >= THREAD_SIZE);
>> +
>> + while (p < boundary) {
>> + *(unsigned long *)p = STACKLEAK_POISON;
>> + p += sizeof(unsigned long);
>> + }
>> +
>> + /* Reset the lowest_stack value for the next syscall */
>> + current->thread.lowest_stack = current_stack_pointer;
Laura, that might be wrong and introduce huge performance impact.
I think, lowest_stack should be reset similarly to the original version.
>> +}
>
> Once this function returns, its data is left on the stack. Is that not a problem?
>
> No strong feelings either way, but it might be worth mentioning in the commit
> message.
I managed to bypass that with "register" specifier. Although it doesn't give an
absolute guarantee.
>> diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
>> index f08a2ed9db0d..156fa0a0da19 100644
>> --- a/arch/arm64/kernel/process.c
>> +++ b/arch/arm64/kernel/process.c
>> @@ -364,6 +364,9 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
>> p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
>> p->thread.cpu_context.sp = (unsigned long)childregs;
>>
>> +#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
>> + p->thread.lowest_stack = (unsigned long)task_stack_page(p);
>
> Nit: end_of_stack(p) would be slightly better semantically, even though
> currently equivalent to task_stack_page(p).
Thanks, I agree, I'll fix it in v12.
> [...]
>
>> +#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
>> +void __used check_alloca(unsigned long size)
>> +{
>> + unsigned long sp, stack_left;
>> +
>> + sp = current_stack_pointer;
>> +
>> + stack_left = sp & (THREAD_SIZE - 1);
>> + BUG_ON(stack_left < 256 || size >= stack_left - 256);
>> +}
>
> Is this arbitrary, or is there something special about 256?
>
> Even if this is arbitrary, can we give it some mnemonic?
It's just a reasonable number. We can introduce a macro for it.
>> +EXPORT_SYMBOL(check_alloca);
>> +#endif
>> diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile
>> index a34e9290a699..25dd2a14560d 100644
>> --- a/drivers/firmware/efi/libstub/Makefile
>> +++ b/drivers/firmware/efi/libstub/Makefile
>> @@ -20,7 +20,8 @@ cflags-$(CONFIG_EFI_ARMSTUB) += -I$(srctree)/scripts/dtc/libfdt
>> KBUILD_CFLAGS := $(cflags-y) -DDISABLE_BRANCH_PROFILING \
>> -D__NO_FORTIFY \
>> $(call cc-option,-ffreestanding) \
>> - $(call cc-option,-fno-stack-protector)
>> + $(call cc-option,-fno-stack-protector) \
>> + $(DISABLE_STACKLEAK_PLUGIN)
>>
>> GCOV_PROFILE := n
>> KASAN_SANITIZE := n
>
> I believe we'll also need to do this for the KVM hyp code in arch/arm64/kvm/hyp/.
Could you please give more details on that? Why STACKLEAK breaks it?
Thanks a lot!
Best regards,
Alexander
^ permalink raw reply
* [PATCH v2 04/27] coresight: Introduce support for Coresight Addrss Translation Unit
From: Mathieu Poirier @ 2018-05-03 17:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525165857-11096-5-git-send-email-suzuki.poulose@arm.com>
On Tue, May 01, 2018 at 10:10:34AM +0100, Suzuki K Poulose wrote:
> Add the initial support for Coresight Address Translation Unit, which
> augments the TMC in Coresight SoC-600 by providing an improved Scatter
> Gather mechanism. CATU is always connected to a single TMC-ETR and
> converts the AXI address with a translated address (from a given SG
> table with specific format). The CATU should be programmed in pass
> through mode and enabled if the ETR doesn't translation by CATU.
>
> This patch provides mechanism to enable/disable the CATU always in the
> pass through mode.
>
> We reuse the existing ports mechanism to link the TMC-ETR to the
> connected CATU.
>
> i.e, TMC-ETR:output_port0 -> CATU:input_port0
>
> Reference manual for CATU component is avilable in version r2p0 of :
> "Arm Coresight System-on-Chip SoC-600 Technical Reference Manual",
> under Section 4.9.
Please remove the part about the TRM as it is bound to change.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/Kconfig | 10 ++
> drivers/hwtracing/coresight/Makefile | 1 +
> drivers/hwtracing/coresight/coresight-catu.c | 195 ++++++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-catu.h | 89 +++++++++++
> drivers/hwtracing/coresight/coresight-tmc-etr.c | 26 ++++
> drivers/hwtracing/coresight/coresight-tmc.h | 27 ++++
> include/linux/coresight.h | 1 +
> 7 files changed, 349 insertions(+)
> create mode 100644 drivers/hwtracing/coresight/coresight-catu.c
> create mode 100644 drivers/hwtracing/coresight/coresight-catu.h
>
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index ef9cb3c..21f638f 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -31,6 +31,16 @@ config CORESIGHT_LINK_AND_SINK_TMC
> complies with the generic implementation of the component without
> special enhancement or added features.
>
> +config CORESIGHT_CATU
> + bool "Coresight Address Translation Unit (CATU) driver"
> + depends on CORESIGHT_LINK_AND_SINK_TMC
> + help
> + Enable support for the Coresight Address Translation Unit (CATU).
> + CATU supports a scatter gather table of 4K pages, with forward/backward
> + lookup. CATU helps TMC ETR to use large physically non-contiguous trace
> + buffer by translating the addersses used by ETR to the corresponding
> + physical adderss by looking up the table.
There is a couple of typos in the last sentence.
> +
> config CORESIGHT_SINK_TPIU
> bool "Coresight generic TPIU driver"
> depends on CORESIGHT_LINKS_AND_SINKS
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index 61db9dd..41870de 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -18,3 +18,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
> obj-$(CONFIG_CORESIGHT_DYNAMIC_REPLICATOR) += coresight-dynamic-replicator.o
> obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
> obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> +obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
> diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c
> new file mode 100644
> index 0000000..2cd69a6
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-catu.c
> @@ -0,0 +1,195 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
Extra line
> +/*
> + * Copyright (C) 2017 ARM Limited. All rights reserved.
You sure you don't want to bump this to 2018?
> + *
> + * Coresight Address Translation Unit support
> + *
> + * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/device.h>
> +#include <linux/amba/bus.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
List in alphabetical order is possible.
> +
> +#include "coresight-catu.h"
> +#include "coresight-priv.h"
> +
> +#define csdev_to_catu_drvdata(csdev) \
> + dev_get_drvdata(csdev->dev.parent)
> +
> +coresight_simple_reg32(struct catu_drvdata, control, CATU_CONTROL);
> +coresight_simple_reg32(struct catu_drvdata, status, CATU_STATUS);
> +coresight_simple_reg32(struct catu_drvdata, mode, CATU_MODE);
> +coresight_simple_reg32(struct catu_drvdata, axictrl, CATU_AXICTRL);
> +coresight_simple_reg32(struct catu_drvdata, irqen, CATU_IRQEN);
> +coresight_simple_reg64(struct catu_drvdata, sladdr,
> + CATU_SLADDRLO, CATU_SLADDRHI);
> +coresight_simple_reg64(struct catu_drvdata, inaddr,
> + CATU_INADDRLO, CATU_INADDRHI);
> +
> +static struct attribute *catu_mgmt_attrs[] = {
> + &dev_attr_control.attr,
> + &dev_attr_status.attr,
> + &dev_attr_mode.attr,
> + &dev_attr_axictrl.attr,
> + &dev_attr_irqen.attr,
> + &dev_attr_sladdr.attr,
> + &dev_attr_inaddr.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group catu_mgmt_group = {
> + .attrs = catu_mgmt_attrs,
> + .name = "mgmt",
> +};
> +
> +static const struct attribute_group *catu_groups[] = {
> + &catu_mgmt_group,
> + NULL,
> +};
> +
> +
> +static inline int catu_wait_for_ready(struct catu_drvdata *drvdata)
> +{
> + return coresight_timeout(drvdata->base,
> + CATU_STATUS, CATU_STATUS_READY, 1);
> +}
> +
> +static int catu_enable_hw(struct catu_drvdata *drvdata, void *__unused)
> +{
> + u32 control;
> +
> + if (catu_wait_for_ready(drvdata))
> + dev_warn(drvdata->dev, "Timeout while waiting for READY\n");
> +
> + control = catu_read_control(drvdata);
> + if (control & BIT(CATU_CONTROL_ENABLE)) {
> + dev_warn(drvdata->dev, "CATU is already enabled\n");
> + return -EBUSY;
> + }
> +
> + control |= BIT(CATU_CONTROL_ENABLE);
> + catu_write_mode(drvdata, CATU_MODE_PASS_THROUGH);
> + catu_write_control(drvdata, control);
> + dev_dbg(drvdata->dev, "Enabled in Pass through mode\n");
> + return 0;
> +}
> +
> +static int catu_enable(struct coresight_device *csdev, void *data)
> +{
> + int rc;
> + struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);
> +
> + CS_UNLOCK(catu_drvdata->base);
> + rc = catu_enable_hw(catu_drvdata, data);
> + CS_LOCK(catu_drvdata->base);
> + return rc;
> +}
> +
> +static int catu_disable_hw(struct catu_drvdata *drvdata)
> +{
> + int rc = 0;
> +
> + if (catu_wait_for_ready(drvdata)) {
> + dev_info(drvdata->dev, "Timeout while waiting for READY\n");
> + rc = -EAGAIN;
> + }
> +
> + catu_write_control(drvdata, 0);
> + dev_dbg(drvdata->dev, "Disabled\n");
> + return rc;
> +}
> +
> +static int catu_disable(struct coresight_device *csdev, void *__unused)
> +{
> + int rc;
> + struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);
> +
> + CS_UNLOCK(catu_drvdata->base);
> + rc = catu_disable_hw(catu_drvdata);
> + CS_LOCK(catu_drvdata->base);
> +
I suppose you can remove the extra line as catu_enable() doesn't have one.
> + return rc;
> +}
> +
> +const struct coresight_ops_helper catu_helper_ops = {
> + .enable = catu_enable,
> + .disable = catu_disable,
> +};
> +
> +const struct coresight_ops catu_ops = {
> + .helper_ops = &catu_helper_ops,
> +};
> +
> +static int catu_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> + int ret = 0;
> + struct catu_drvdata *drvdata;
> + struct coresight_desc catu_desc;
> + struct coresight_platform_data *pdata = NULL;
> + struct device *dev = &adev->dev;
> + struct device_node *np = dev->of_node;
> + void __iomem *base;
> +
> + if (np) {
> + pdata = of_get_coresight_platform_data(dev, np);
> + if (IS_ERR(pdata)) {
> + ret = PTR_ERR(pdata);
> + goto out;
> + }
> + dev->platform_data = pdata;
> + }
> +
> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata) {
> + ret = -ENOMEM;
> + goto out;
> + }
> +
> + drvdata->dev = dev;
> + dev_set_drvdata(dev, drvdata);
> + base = devm_ioremap_resource(dev, &adev->res);
> + if (IS_ERR(base)) {
> + ret = PTR_ERR(base);
> + goto out;
> + }
> +
> + drvdata->base = base;
> + catu_desc.pdata = pdata;
> + catu_desc.dev = dev;
> + catu_desc.groups = catu_groups;
> + catu_desc.type = CORESIGHT_DEV_TYPE_HELPER;
> + catu_desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CATU;
> + catu_desc.ops = &catu_ops;
> + drvdata->csdev = coresight_register(&catu_desc);
> + if (IS_ERR(drvdata->csdev))
> + ret = PTR_ERR(drvdata->csdev);
> + if (!ret)
> + dev_info(drvdata->dev, "initialized\n");
Please remove as it 1) doesn't convey HW related information and 2) the TMC
doesn't out put anything.
> +out:
> + pm_runtime_put(&adev->dev);
> + return ret;
> +}
> +
> +static struct amba_id catu_ids[] = {
> + {
> + .id = 0x000bb9ee,
> + .mask = 0x000fffff,
> + },
> + {},
> +};
> +
> +static struct amba_driver catu_driver = {
> + .drv = {
> + .name = "coresight-catu",
> + .owner = THIS_MODULE,
> + .suppress_bind_attrs = true,
> + },
> + .probe = catu_probe,
> + .id_table = catu_ids,
> +};
> +
> +builtin_amba_driver(catu_driver);
> diff --git a/drivers/hwtracing/coresight/coresight-catu.h b/drivers/hwtracing/coresight/coresight-catu.h
> new file mode 100644
> index 0000000..cd58d6f
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-catu.h
> @@ -0,0 +1,89 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
Extra line
> +/*
> + * Copyright (C) 2017 ARM Limited. All rights reserved.
> + *
> + * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
> + *
Extra line. In coresight-catu.c there isn't one.
> + */
> +
> +#ifndef _CORESIGHT_CATU_H
> +#define _CORESIGHT_CATU_H
> +
> +#include "coresight-priv.h"
> +
> +/* Register offset from base */
> +#define CATU_CONTROL 0x000
> +#define CATU_MODE 0x004
> +#define CATU_AXICTRL 0x008
> +#define CATU_IRQEN 0x00c
> +#define CATU_SLADDRLO 0x020
> +#define CATU_SLADDRHI 0x024
> +#define CATU_INADDRLO 0x028
> +#define CATU_INADDRHI 0x02c
> +#define CATU_STATUS 0x100
> +#define CATU_DEVARCH 0xfbc
> +
> +#define CATU_CONTROL_ENABLE 0
> +
> +#define CATU_MODE_PASS_THROUGH 0U
> +#define CATU_MODE_TRANSLATE 1U
> +
> +#define CATU_STATUS_READY 8
> +#define CATU_STATUS_ADRERR 0
> +#define CATU_STATUS_AXIERR 4
> +
> +
Extra line.
> +#define CATU_IRQEN_ON 0x1
> +#define CATU_IRQEN_OFF 0x0
> +
> +
Extra line.
> +struct catu_drvdata {
> + struct device *dev;
> + void __iomem *base;
> + struct coresight_device *csdev;
> + int irq;
> +};
> +
> +#define CATU_REG32(name, offset) \
> +static inline u32 \
> +catu_read_##name(struct catu_drvdata *drvdata) \
> +{ \
> + return coresight_read_reg_pair(drvdata->base, offset, -1); \
> +} \
> +static inline void \
> +catu_write_##name(struct catu_drvdata *drvdata, u32 val) \
> +{ \
> + coresight_write_reg_pair(drvdata->base, val, offset, -1); \
> +}
> +
> +#define CATU_REG_PAIR(name, lo_off, hi_off) \
> +static inline u64 \
> +catu_read_##name(struct catu_drvdata *drvdata) \
> +{ \
> + return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \
> +} \
> +static inline void \
> +catu_write_##name(struct catu_drvdata *drvdata, u64 val) \
> +{ \
> + coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \
> +}
> +
> +CATU_REG32(control, CATU_CONTROL);
> +CATU_REG32(mode, CATU_MODE);
> +CATU_REG_PAIR(sladdr, CATU_SLADDRLO, CATU_SLADDRHI)
> +CATU_REG_PAIR(inaddr, CATU_INADDRLO, CATU_INADDRHI)
> +
> +static inline bool coresight_is_catu_device(struct coresight_device *csdev)
> +{
> + enum coresight_dev_subtype_helper subtype;
> +
> + /* Make the checkpatch happy */
> + subtype = csdev->subtype.helper_subtype;
> +
> + return IS_ENABLED(CONFIG_CORESIGHT_CATU) &&
> + csdev->type == CORESIGHT_DEV_TYPE_HELPER &&
> + subtype == CORESIGHT_DEV_SUBTYPE_HELPER_CATU;
> +}
> +
> +#endif
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 68fbc8f..9b0c620 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -17,9 +17,26 @@
>
> #include <linux/coresight.h>
> #include <linux/dma-mapping.h>
> +#include "coresight-catu.h"
> #include "coresight-priv.h"
> #include "coresight-tmc.h"
>
> +static inline void tmc_etr_enable_catu(struct tmc_drvdata *drvdata)
> +{
> + struct coresight_device *catu = tmc_etr_get_catu_device(drvdata);
> +
> + if (catu && helper_ops(catu)->enable)
> + helper_ops(catu)->enable(catu, NULL);
> +}
> +
> +static inline void tmc_etr_disable_catu(struct tmc_drvdata *drvdata)
> +{
> + struct coresight_device *catu = tmc_etr_get_catu_device(drvdata);
> +
> + if (catu && helper_ops(catu)->disable)
> + helper_ops(catu)->disable(catu, NULL);
> +}
> +
> static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> {
> u32 axictl, sts;
> @@ -27,6 +44,12 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> /* Zero out the memory to help with debug */
> memset(drvdata->vaddr, 0, drvdata->size);
>
> + /*
> + * If this ETR is connected to a CATU, enable it before we turn
> + * this on
> + */
> + tmc_etr_enable_catu(drvdata);
> +
> CS_UNLOCK(drvdata->base);
>
> /* Wait for TMCSReady bit to be set */
> @@ -116,6 +139,9 @@ static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> tmc_disable_hw(drvdata);
>
> CS_LOCK(drvdata->base);
> +
> + /* Disable CATU device if this ETR is connected to one */
> + tmc_etr_disable_catu(drvdata);
> }
>
> static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 8df7a81..cdff853 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -19,6 +19,7 @@
> #define _CORESIGHT_TMC_H
>
> #include <linux/miscdevice.h>
> +#include "coresight-catu.h"
>
> #define TMC_RSZ 0x004
> #define TMC_STS 0x00c
> @@ -222,4 +223,30 @@ static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap)
> return !!(drvdata->etr_caps & cap);
> }
>
> +/*
> + * TMC ETR could be connected to a CATU device, which can provide address
> + * translation service. This is represented by the Output port of the TMC
> + * (ETR) connected to the input port of the CATU.
> + *
> + * Returns : coresight_device ptr for the CATU device if a CATU is found.
> + * : NULL otherwise.
> + */
> +static inline struct coresight_device *
> +tmc_etr_get_catu_device(struct tmc_drvdata *drvdata)
> +{
> + int i;
> + struct coresight_device *tmp, *etr = drvdata->csdev;
> +
> + if (!IS_ENABLED(CONFIG_CORESIGHT_CATU))
> + return NULL;
> +
> + for (i = 0; i < etr->nr_outport; i++) {
> + tmp = etr->conns[0].child_dev;
> + if (tmp && coresight_is_catu_device(tmp))
> + return tmp;
> + }
> +
> + return NULL;
> +}
> +
> #endif
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 5e926f7..c0e1568 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -72,6 +72,7 @@ enum coresight_dev_subtype_source {
>
> enum coresight_dev_subtype_helper {
> CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
> + CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
> };
>
> /**
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v1] pinctrl: armada-37xx: Convert to use match_string() helper
From: Andy Shevchenko @ 2018-05-03 17:26 UTC (permalink / raw)
To: linux-arm-kernel
The new helper returns index of the matching string in an array.
We are going to use it here.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 29 ++++++---------------
1 file changed, 8 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5b63248c8209..0f1eafba0ded 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -214,18 +214,6 @@ static inline void armada_37xx_update_reg(unsigned int *reg,
}
}
-static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
- const char *func)
-{
- int f;
-
- for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
- if (!strcmp(grp->funcs[f], func))
- return f;
-
- return -ENOTSUPP;
-}
-
static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
struct armada_37xx_pinctrl *info, int pin, int *grp)
{
@@ -344,10 +332,9 @@ static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
dev_dbg(info->dev, "enable function %s group %s\n",
name, grp->name);
- func = armada_37xx_get_func_reg(grp, name);
-
+ func = match_string(grp->funcs, NB_FUNCS, name);
if (func < 0)
- return func;
+ return -ENOTSUPP;
val = grp->val[func];
@@ -932,12 +919,12 @@ static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
struct armada_37xx_pin_group *gp = &info->groups[g];
int f;
- for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
- if (strcmp(gp->funcs[f], name) == 0) {
- *groups = gp->name;
- groups++;
- }
- }
+ f = match_string(gp->funcs, NB_FUNCS, name);
+ if (f < 0)
+ continue;
+
+ *groups = gp->name;
+ groups++;
}
}
return 0;
--
2.17.0
^ permalink raw reply related
* [PATCH v9 0/2] Initial Allwinner V3s CSI Support
From: Maxime Ripard @ 2018-05-03 17:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1520301070-48769-1-git-send-email-yong.deng@magewell.com>
Hi Yong,
On Tue, Mar 06, 2018 at 09:51:10AM +0800, Yong Deng wrote:
> This patchset add initial support for Allwinner V3s CSI.
>
> Allwinner V3s SoC features two CSI module. CSI0 is used for MIPI CSI-2
> interface and CSI1 is used for parallel interface. This is not
> documented in datasheet but by test and guess.
>
> This patchset implement a v4l2 framework driver and add a binding
> documentation for it.
>
> Currently, the driver only support the parallel interface. And has been
> tested with a BT1120 signal which generating from FPGA. The following
> fetures are not support with this patchset:
> - ISP
> - MIPI-CSI2
> - Master clock for camera sensor
> - Power regulator for the front end IC
Do you plan on sending another version some time soon? It would be
awesome to have this in 4.18.
Thanks!
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH] arm: omap1: ams-delta: fix deferred_fiq handler
From: Tony Lindgren @ 2018-05-03 17:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180502183203.16034-1-jmkrzyszt@gmail.com>
* Janusz Krzysztofik <jmkrzyszt@gmail.com> [180502 11:34]:
> The deferred_fiq handler used to limit hardware operations to IRQ
> unmask only, relying on gpio-omap assigned handler performing the ACKs.
> Since commit 80ac93c27441 ("gpio: omap: Fix lost edge interrupts") this
> is no longer the case as handle_edge_irq() has been replaced with
> handle_simmple_irq() which doesn't touch the hardware.
>
> Add single ACK operation per each active IRQ pin to the handler. While
> being at it, move unmask operation out of irq_counter loop so it is
> also called only once for each active IRQ pin.
Good to hear the fiq handler is confirmed working, applying
into omap-for-v4.17/fixes thanks.
Tony
^ permalink raw reply
* [PATCH 4/4] firmware: arm_sdei: use common SMCCC_CONDUIT_*
From: Mark Rutland @ 2018-05-03 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503170330.5591-1-mark.rutland@arm.com>
Now that we have common definitions for SMCCC conduits, move the SDEI
code over to them, and remove the SDEI-specific definitions.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
---
arch/arm64/kernel/sdei.c | 3 ++-
drivers/firmware/arm_sdei.c | 12 ++++++------
include/linux/arm_sdei.h | 6 ------
3 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/kernel/sdei.c b/arch/arm64/kernel/sdei.c
index 6b8d90d5ceae..a3be67ae8a88 100644
--- a/arch/arm64/kernel/sdei.c
+++ b/arch/arm64/kernel/sdei.c
@@ -2,6 +2,7 @@
// Copyright (C) 2017 Arm Ltd.
#define pr_fmt(fmt) "sdei: " fmt
+#include <linux/arm-smccc.h>
#include <linux/arm_sdei.h>
#include <linux/hardirq.h>
#include <linux/irqflags.h>
@@ -125,7 +126,7 @@ unsigned long sdei_arch_get_entry_point(int conduit)
return 0;
}
- sdei_exit_mode = (conduit == CONDUIT_HVC) ? SDEI_EXIT_HVC : SDEI_EXIT_SMC;
+ sdei_exit_mode = (conduit == SMCCC_CONDUIT_HVC) ? SDEI_EXIT_HVC : SDEI_EXIT_SMC;
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
if (arm64_kernel_unmapped_at_el0()) {
diff --git a/drivers/firmware/arm_sdei.c b/drivers/firmware/arm_sdei.c
index 1ea71640fdc2..1357dbd7c7fc 100644
--- a/drivers/firmware/arm_sdei.c
+++ b/drivers/firmware/arm_sdei.c
@@ -896,29 +896,29 @@ static int sdei_get_conduit(struct platform_device *pdev)
if (np) {
if (of_property_read_string(np, "method", &method)) {
pr_warn("missing \"method\" property\n");
- return CONDUIT_INVALID;
+ return SMCCC_CONDUIT_NONE;
}
if (!strcmp("hvc", method)) {
sdei_firmware_call = &sdei_smccc_hvc;
- return CONDUIT_HVC;
+ return SMCCC_CONDUIT_HVC;
} else if (!strcmp("smc", method)) {
sdei_firmware_call = &sdei_smccc_smc;
- return CONDUIT_SMC;
+ return SMCCC_CONDUIT_SMC;
}
pr_warn("invalid \"method\" property: %s\n", method);
} else if (IS_ENABLED(CONFIG_ACPI) && !acpi_disabled) {
if (acpi_psci_use_hvc()) {
sdei_firmware_call = &sdei_smccc_hvc;
- return CONDUIT_HVC;
+ return SMCCC_CONDUIT_HVC;
} else {
sdei_firmware_call = &sdei_smccc_smc;
- return CONDUIT_SMC;
+ return SMCCC_CONDUIT_SMC;
}
}
- return CONDUIT_INVALID;
+ return SMCCC_CONDUIT_NONE;
}
static int sdei_probe(struct platform_device *pdev)
diff --git a/include/linux/arm_sdei.h b/include/linux/arm_sdei.h
index 942afbd544b7..21e337d99fa6 100644
--- a/include/linux/arm_sdei.h
+++ b/include/linux/arm_sdei.h
@@ -5,12 +5,6 @@
#include <uapi/linux/arm_sdei.h>
-enum sdei_conduit_types {
- CONDUIT_INVALID = 0,
- CONDUIT_SMC,
- CONDUIT_HVC,
-};
-
#include <asm/sdei.h>
/* Arch code should override this to set the entry point from firmware... */
--
2.11.0
^ permalink raw reply related
* [PATCH 3/4] firmware/psci: use common SMCCC_CONDUIT_*
From: Mark Rutland @ 2018-05-03 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503170330.5591-1-mark.rutland@arm.com>
Now that we have common SMCCC_CONDUIT_* definitions, migrate the PSCI
code over to them, and kill off the old PSCI_CONDUIT_* definitions.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
drivers/firmware/psci.c | 25 +++++++++----------------
include/linux/psci.h | 9 ++-------
2 files changed, 11 insertions(+), 23 deletions(-)
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index 310882185ca4..05792699e6b5 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -60,7 +60,7 @@ bool psci_tos_resident_on(int cpu)
}
struct psci_operations psci_ops = {
- .conduit = PSCI_CONDUIT_NONE,
+ .conduit = SMCCC_CONDUIT_NONE,
.smccc_version = SMCCC_VERSION_1_0,
};
@@ -69,14 +69,7 @@ enum arm_smccc_conduit arm_smccc_get_conduit(void)
if (psci_ops.smccc_version < SMCCC_VERSION_1_1)
return SMCCC_CONDUIT_NONE;
- switch (psci_ops.conduit) {
- case PSCI_CONDUIT_SMC:
- return SMCCC_CONDUIT_SMC;
- case PSCI_CONDUIT_HVC:
- return SMCCC_CONDUIT_HVC;
- default:
- return SMCCC_CONDUIT_NONE;
- }
+ return psci_ops.conduit;
}
typedef unsigned long (psci_fn)(unsigned long, unsigned long,
@@ -228,13 +221,13 @@ static unsigned long psci_migrate_info_up_cpu(void)
0, 0, 0);
}
-static void set_conduit(enum psci_conduit conduit)
+static void set_conduit(enum arm_smccc_conduit conduit)
{
switch (conduit) {
- case PSCI_CONDUIT_HVC:
+ case SMCCC_CONDUIT_HVC:
invoke_psci_fn = __invoke_psci_fn_hvc;
break;
- case PSCI_CONDUIT_SMC:
+ case SMCCC_CONDUIT_SMC:
invoke_psci_fn = __invoke_psci_fn_smc;
break;
default:
@@ -256,9 +249,9 @@ static int get_set_conduit_method(struct device_node *np)
}
if (!strcmp("hvc", method)) {
- set_conduit(PSCI_CONDUIT_HVC);
+ set_conduit(SMCCC_CONDUIT_HVC);
} else if (!strcmp("smc", method)) {
- set_conduit(PSCI_CONDUIT_SMC);
+ set_conduit(SMCCC_CONDUIT_SMC);
} else {
pr_warn("invalid \"method\" property: %s\n", method);
return -EINVAL;
@@ -714,9 +707,9 @@ int __init psci_acpi_init(void)
pr_info("probing for conduit method from ACPI.\n");
if (acpi_psci_use_hvc())
- set_conduit(PSCI_CONDUIT_HVC);
+ set_conduit(SMCCC_CONDUIT_HVC);
else
- set_conduit(PSCI_CONDUIT_SMC);
+ set_conduit(SMCCC_CONDUIT_SMC);
return psci_probe();
}
diff --git a/include/linux/psci.h b/include/linux/psci.h
index 8b1b3b5935ab..affcd2128df8 100644
--- a/include/linux/psci.h
+++ b/include/linux/psci.h
@@ -14,6 +14,7 @@
#ifndef __LINUX_PSCI_H
#define __LINUX_PSCI_H
+#include <linux/arm-smccc.h>
#include <linux/init.h>
#include <linux/types.h>
@@ -25,12 +26,6 @@ bool psci_tos_resident_on(int cpu);
int psci_cpu_init_idle(unsigned int cpu);
int psci_cpu_suspend_enter(unsigned long index);
-enum psci_conduit {
- PSCI_CONDUIT_NONE,
- PSCI_CONDUIT_SMC,
- PSCI_CONDUIT_HVC,
-};
-
enum smccc_version {
SMCCC_VERSION_1_0,
SMCCC_VERSION_1_1,
@@ -45,7 +40,7 @@ struct psci_operations {
int (*affinity_info)(unsigned long target_affinity,
unsigned long lowest_affinity_level);
int (*migrate_info_type)(void);
- enum psci_conduit conduit;
+ enum arm_smccc_conduit conduit;
enum smccc_version smccc_version;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 2/4] arm64: errata: use arm_smccc_get_conduit()
From: Mark Rutland @ 2018-05-03 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503170330.5591-1-mark.rutland@arm.com>
Now that we have arm_smccc_get_conduit(), we can hide the PSCI
implementation details from the arm64 cpu errata code, so let's do so.
As arm_smccc_get_conduit() implicitly checks that the SMCCC version is
at least SMCCC_VERSION_1_1, we no longer need to check this explicitly,
as the switch statement's default case is a return.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
---
arch/arm64/kernel/cpu_errata.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index a900befadfe8..afd5e66f52f1 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -156,9 +156,7 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
}
-#include <uapi/linux/psci.h>
#include <linux/arm-smccc.h>
-#include <linux/psci.h>
static void call_smc_arch_workaround_1(void)
{
@@ -193,11 +191,8 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
if (!entry->matches(entry, SCOPE_LOCAL_CPU))
return;
- if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
- return;
-
- switch (psci_ops.conduit) {
- case PSCI_CONDUIT_HVC:
+ switch (arm_smccc_get_conduit()) {
+ case SMCCC_CONDUIT_HVC:
arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_1, &res);
if ((int)res.a0 < 0)
@@ -208,7 +203,7 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
smccc_end = NULL;
break;
- case PSCI_CONDUIT_SMC:
+ case SMCCC_CONDUIT_SMC:
arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_1, &res);
if ((int)res.a0 < 0)
--
2.11.0
^ permalink raw reply related
* [PATCH 1/4] arm/arm64: smccc/psci: add arm_smccc_get_conduit()
From: Mark Rutland @ 2018-05-03 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503170330.5591-1-mark.rutland@arm.com>
SMCCC callers are currently amassing a collection of enums for the SMCCC
conduit, and are having to dig into the PSCI driver's internals in order
to figure out what to do.
Let's clean this up, with common SMCCC_CONDUIT_* definitions, and an
arm_smccc_get_conduit() helper that abstracts the PSCI driver's internal
state.
We can kill off the PSCI_CONDUIT_* definitions once we've migrated users
over to the nerw interface.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
drivers/firmware/psci.c | 15 +++++++++++++++
include/linux/arm-smccc.h | 16 ++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index c80ec1d03274..310882185ca4 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -64,6 +64,21 @@ struct psci_operations psci_ops = {
.smccc_version = SMCCC_VERSION_1_0,
};
+enum arm_smccc_conduit arm_smccc_get_conduit(void)
+{
+ if (psci_ops.smccc_version < SMCCC_VERSION_1_1)
+ return SMCCC_CONDUIT_NONE;
+
+ switch (psci_ops.conduit) {
+ case PSCI_CONDUIT_SMC:
+ return SMCCC_CONDUIT_SMC;
+ case PSCI_CONDUIT_HVC:
+ return SMCCC_CONDUIT_HVC;
+ default:
+ return SMCCC_CONDUIT_NONE;
+ }
+}
+
typedef unsigned long (psci_fn)(unsigned long, unsigned long,
unsigned long, unsigned long);
static psci_fn *invoke_psci_fn;
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index a031897fca76..193e9d8a1ac2 100644
--- a/include/linux/arm-smccc.h
+++ b/include/linux/arm-smccc.h
@@ -84,6 +84,22 @@
#include <linux/linkage.h>
#include <linux/types.h>
+
+enum arm_smccc_conduit {
+ SMCCC_CONDUIT_NONE,
+ SMCCC_CONDUIT_SMC,
+ SMCCC_CONDUIT_HVC,
+};
+
+/**
+ * arm_smccc_get_conduit()
+ *
+ * Returns the conduit to be used for SMCCCv1.1 or later.
+ *
+ * When SMCCCv1.1 is not present, returns SMCCC_CONDUIT_NONE.
+ */
+enum arm_smccc_conduit arm_smccc_get_conduit(void);
+
/**
* struct arm_smccc_res - Result from SMC/HVC call
* @a0-a3 result values from registers 0 to 3
--
2.11.0
^ permalink raw reply related
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