* [PATCH] arm64: defconfig: enable rockchip efuse
From: Heiko Stuebner @ 2018-05-09 14:32 UTC (permalink / raw)
To: linux-arm-kernel
The efuses on Rockchip socs often contain informations
about specifics of the chip its running on (leakage currents etc)
which components might want to read to adjust settings accordingly.
So enable the efuse early for that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 34037d24fbf4..74abf140e332 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -612,6 +612,7 @@ CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
CONFIG_MESON_EFUSE=m
CONFIG_QCOM_QFPROM=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_UNIPHIER_EFUSE=y
CONFIG_TEE=y
CONFIG_OPTEE=y
--
2.16.2
^ permalink raw reply related
* [PATCH]irqchip/irq-gic-v3:Avoid a waste of LPI resource
From: Mark Langsdorf @ 2018-05-09 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8898674D84E3B24BA3A2D289B872026A69EF9AF9@G01JPEXMBKW03>
On 04/30/2018 02:53 AM, Zhang, Lei wrote:
> Hi Marc
>
> thanks for your opinions.
>
>> How many is many? Are they PCI? Or something else?
>
>> As it is, this patch will break Multi-MSI and some other platforms that
>> do require a higher allocation granule.
>>
>> Depending on whether you're using PCI or some other bus, we can probably
>> come up with a solution that works for everyone. But I need more
>> information on this.
>
> Actually it is our original interconnect device not on PCI but on our original bus.
> This device has many sub devices around one thousand, and each sub device requires only a few LPIs.
>
> As I explained in point1, each Device ID can still allocate enough LPIs more than IRQS_PER_CHUNK by increasing chunks.
> So I couldn't understand why this patch will break Multi-MSI.
>
> By the way, 32 seems a good default value for IRQS_PER_CHUNK.
> So, I want to write another patch to make IRQ_PER_CHUNK a variable which can be changed by kernel parameter.
> What do you think of this idea?
If you intend your devices to be supported by server distributions,
instead of embedded kernels, having IRQ_PER_CHUNK as a kernel parameter
is not a good idea. The server distributions are going to compile, test,
and support a single kernel for all server systems, and are not going to
have a special kernel to support one vendor's systems that has a
different IRQ_PER_CHUNK parameter.
So even if you wrote that patch and it was accepted into the kernel, the
server distribution kernels are still going to set IRQ_PER_CHUNK to 32.
Marc's suggestion of implementing a glue layer, and then changing the
glue layer interface to pass the allocation requirements up to this
driver is the best solution that can be supported for server products.
--Mark Langsdorf
^ permalink raw reply
* [PATCH] mtd: nxp-spifi: decrement flash_np refcnt on error paths
From: Alexey Khoroshilov @ 2018-05-09 14:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180509114250.120eb299@bbrezillon>
On 09.05.2018 12:42, Boris Brezillon wrote:
> On Tue, 8 May 2018 23:47:36 +0300
> Alexey Khoroshilov <khoroshilov@ispras.ru> wrote:
>
>> nxp_spifi_probe() increments refcnt of SPI flash device node by
>> of_get_next_available_child() and then it passes the node
>> to mtd device in nxp_spifi_setup_flash().
>> But if a failure happens before mtd_device_register() succeed,
>> the refcnt is left undecremented.
>
> Why not doing that in the error path of the probe function? Also, you
> probably want to call of_node_put() in the ->remove() function.
>
You are right.
I believed that after successful mtd_device_register()
the node is managed by mtd device. I missed that it calls of_node_get()
in add_mtd_device() by itself.
I will prepare v2.
But I guess there is no need to have of_node_put() in ->remove(), since
probe() finishes its own usage of flash_np, while mtd_device incremented
refcnt by itself and will decrement it in ->remove() in
mtd_device_unregister(&spifi->nor.mtd). So, I would propose
of_node_put() on both successful and error path.
Thank you,
Alexey
^ permalink raw reply
* [PATCH 0/8] ARM: dts: renesas: Add PMU device nodes
From: Geert Uytterhoeven @ 2018-05-09 14:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525701427-12914-1-git-send-email-geert+renesas@glider.be>
On Mon, May 7, 2018 at 3:56 PM, Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> This patch series enables support for the ARM Performance Monitor Units
> in Cortex-A7, Cortex-A9, and Cortex-A15 CPU cores on Renesas RZ/A1,
> R-Car Gen2, and RZ/G1 SoCs. This allows for better performance analysis
> using the "perf" tool.
[...]
> This has been tested on r8a7791/koelsch, and boot-tested on
> r7s72100/genmai, r8a7790/lager, r8a7792/blanche, and r8a7794/silk.
... and r8a7793/gose and r8a7794/alt.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] mtd: nxp-spifi: decrement flash_np refcnt on error paths
From: Boris Brezillon @ 2018-05-09 14:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <04eca940-cf53-d365-9899-336eb213e089@ispras.ru>
On Wed, 9 May 2018 17:35:41 +0300
Alexey Khoroshilov <khoroshilov@ispras.ru> wrote:
> On 09.05.2018 12:42, Boris Brezillon wrote:
> > On Tue, 8 May 2018 23:47:36 +0300
> > Alexey Khoroshilov <khoroshilov@ispras.ru> wrote:
> >
> >> nxp_spifi_probe() increments refcnt of SPI flash device node by
> >> of_get_next_available_child() and then it passes the node
> >> to mtd device in nxp_spifi_setup_flash().
> >> But if a failure happens before mtd_device_register() succeed,
> >> the refcnt is left undecremented.
> >
> > Why not doing that in the error path of the probe function? Also, you
> > probably want to call of_node_put() in the ->remove() function.
> >
>
>
> You are right.
>
> I believed that after successful mtd_device_register()
> the node is managed by mtd device. I missed that it calls of_node_get()
> in add_mtd_device() by itself.
>
> I will prepare v2.
> But I guess there is no need to have of_node_put() in ->remove(), since
> probe() finishes its own usage of flash_np, while mtd_device incremented
> refcnt by itself and will decrement it in ->remove() in
> mtd_device_unregister(&spifi->nor.mtd). So, I would propose
> of_node_put() on both successful and error path.
Sounds good.
^ permalink raw reply
* [PATCH v2] mtd: nxp-spifi: release flash_np in nxp_spifi_probe()
From: Alexey Khoroshilov @ 2018-05-09 14:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180509163920.67a5f203@bbrezillon>
nxp_spifi_probe() increments refcnt of SPI flash device node by
of_get_next_available_child() and leaves it undecremented on both
successful and error paths.
Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
---
drivers/mtd/spi-nor/nxp-spifi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/nxp-spifi.c b/drivers/mtd/spi-nor/nxp-spifi.c
index 15374216d4d9..7b047951d0a2 100644
--- a/drivers/mtd/spi-nor/nxp-spifi.c
+++ b/drivers/mtd/spi-nor/nxp-spifi.c
@@ -438,11 +438,15 @@ static int nxp_spifi_probe(struct platform_device *pdev)
ret = nxp_spifi_setup_flash(spifi, flash_np);
if (ret) {
dev_err(&pdev->dev, "unable to setup flash chip\n");
- goto dis_clks;
+ goto put_np;
}
+ of_node_put(flash_np);
+
return 0;
+put_np:
+ of_node_put(flash_np);
dis_clks:
clk_disable_unprepare(spifi->clk_spifi);
dis_clk_reg:
--
2.7.4
^ permalink raw reply related
* [PATCH v2] mtd: nxp-spifi: release flash_np in nxp_spifi_probe()
From: Boris Brezillon @ 2018-05-09 15:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525877806-21148-1-git-send-email-khoroshilov@ispras.ru>
On Wed, 9 May 2018 17:56:46 +0300
Alexey Khoroshilov <khoroshilov@ispras.ru> wrote:
> nxp_spifi_probe() increments refcnt of SPI flash device node by
> of_get_next_available_child() and leaves it undecremented on both
> successful and error paths.
>
> Found by Linux Driver Verification project (linuxtesting.org).
>
> Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
> ---
> drivers/mtd/spi-nor/nxp-spifi.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/nxp-spifi.c b/drivers/mtd/spi-nor/nxp-spifi.c
> index 15374216d4d9..7b047951d0a2 100644
> --- a/drivers/mtd/spi-nor/nxp-spifi.c
> +++ b/drivers/mtd/spi-nor/nxp-spifi.c
> @@ -438,11 +438,15 @@ static int nxp_spifi_probe(struct platform_device *pdev)
> ret = nxp_spifi_setup_flash(spifi, flash_np);
Just put the of_node_put() here and that's the only change you'll need.
> if (ret) {
> dev_err(&pdev->dev, "unable to setup flash chip\n");
> - goto dis_clks;
> + goto put_np;
> }
>
> + of_node_put(flash_np);
> +
> return 0;
>
> +put_np:
> + of_node_put(flash_np);
> dis_clks:
> clk_disable_unprepare(spifi->clk_spifi);
> dis_clk_reg:
^ permalink raw reply
* [PATCH v2 01/26] drm/bridge: allow optionally specifying an owner .odev device
From: Andrzej Hajda @ 2018-05-09 15:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180504135212.26977-2-peda@axentia.se>
On 04.05.2018 15:51, Peter Rosin wrote:
> Bridge drivers can now (temporarily, in a transition phase) select if
> they want to provide a full owner device or keep just providing an
> of_node.
>
> By providing a full owner device, the bridge drivers no longer need
> to provide an of_node since that node is available via the owner
> device.
>
> When all bridge drivers provide an owner device, that will become
> mandatory and the .of_node member will be removed.
>
> Signed-off-by: Peter Rosin <peda@axentia.se>
> ---
> drivers/gpu/drm/drm_bridge.c | 3 ++-
> drivers/gpu/drm/rockchip/rockchip_lvds.c | 4 +++-
What is the reason to put rockchip here? Shouldn't be in separate patch?
> include/drm/drm_bridge.h | 2 ++
> 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
> index 1638bfe9627c..3872f5379998 100644
> --- a/drivers/gpu/drm/drm_bridge.c
> +++ b/drivers/gpu/drm/drm_bridge.c
> @@ -365,7 +365,8 @@ struct drm_bridge *of_drm_find_bridge(struct device_node *np)
> mutex_lock(&bridge_lock);
>
> list_for_each_entry(bridge, &bridge_list, list) {
> - if (bridge->of_node == np) {
> + if ((bridge->odev && bridge->odev->of_node == np) ||
> + bridge->of_node == np) {
> mutex_unlock(&bridge_lock);
> return bridge;
> }
> diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c
> index 4bd94b167d2c..557e0079c98d 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
> @@ -377,8 +377,10 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master,
> }
> if (lvds->panel)
> remote = lvds->panel->dev->of_node;
> - else
> + else if (lvds->bridge->of_node)
> remote = lvds->bridge->of_node;
> + else
> + remote = lvds->bridge->odev->of_node;
I guess odev should be NULL here, or have I missed something.
Regards
Andrzej
> if (of_property_read_string(dev->of_node, "rockchip,output", &name))
> /* default set it as output rgb */
> lvds->output = DISPLAY_OUTPUT_RGB;
> diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
> index 3270fec46979..7c17977c3537 100644
> --- a/include/drm/drm_bridge.h
> +++ b/include/drm/drm_bridge.h
> @@ -254,6 +254,7 @@ struct drm_bridge_timings {
>
> /**
> * struct drm_bridge - central DRM bridge control structure
> + * @odev: device that owns the bridge
> * @dev: DRM device this bridge belongs to
> * @encoder: encoder to which this bridge is connected
> * @next: the next bridge in the encoder chain
> @@ -265,6 +266,7 @@ struct drm_bridge_timings {
> * @driver_private: pointer to the bridge driver's internal context
> */
> struct drm_bridge {
> + struct device *odev;
> struct drm_device *dev;
> struct drm_encoder *encoder;
> struct drm_bridge *next;
^ permalink raw reply
* [PATCH v3] mtd: nxp-spifi: release flash_np in nxp_spifi_probe()
From: Alexey Khoroshilov @ 2018-05-09 15:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180509170310.65d19c49@bbrezillon>
nxp_spifi_probe() increments refcnt of SPI flash device node by
of_get_next_available_child() and leaves it undecremented on both
successful and error paths.
Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
---
v3: Move of_node_put() before return value check as Boris Brezillon suggested.
drivers/mtd/spi-nor/nxp-spifi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/nxp-spifi.c b/drivers/mtd/spi-nor/nxp-spifi.c
index 15374216d4d9..0c9094ec5966 100644
--- a/drivers/mtd/spi-nor/nxp-spifi.c
+++ b/drivers/mtd/spi-nor/nxp-spifi.c
@@ -436,6 +436,7 @@ static int nxp_spifi_probe(struct platform_device *pdev)
}
ret = nxp_spifi_setup_flash(spifi, flash_np);
+ of_node_put(flash_np);
if (ret) {
dev_err(&pdev->dev, "unable to setup flash chip\n");
goto dis_clks;
--
2.7.4
^ permalink raw reply related
* [PATCH 0/2] ARM: dts: stm32: update rtc st,syscfg
From: Amelie Delaunay @ 2018-05-09 15:18 UTC (permalink / raw)
To: linux-arm-kernel
With the lastest STM32 RTC driver updates, it is mandatory to define
pwrcfg control register and DBP (Disable Backup Protection) bit through
st,syscfg property. This patchset updates RTC nodes on stm32f429 and
stm32f746 accordingly.
Amelie Delaunay (2):
ARM: dts: stm32: update rtc st,syscfg property on stm32f429
ARM: dts: stm32: update rtc st,syscfg property on stm32f746
arch/arm/boot/dts/stm32f429.dtsi | 2 +-
arch/arm/boot/dts/stm32f746.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH 1/2] ARM: dts: stm32: update rtc st, syscfg property on stm32f429
From: Amelie Delaunay @ 2018-05-09 15:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525879094-19562-1-git-send-email-amelie.delaunay@st.com>
To fit with latest rtc driver updates, rtc st,syscfg property must contain
the control register offset of pwrcfg and the mask corresponding to the
DBP (Disable Backup Protection) bit.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index ede77e0..309e7e3 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -302,7 +302,7 @@
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
- st,syscfg = <&pwrcfg>;
+ st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: stm32: update rtc st, syscfg property on stm32f746
From: Amelie Delaunay @ 2018-05-09 15:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525879094-19562-1-git-send-email-amelie.delaunay@st.com>
To fit with latest rtc driver updates, rtc st,syscfg property must contain
the control register offset of pwrcfg and the mask corresponding to the
DBP (Disable Backup Protection) bit.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
arch/arm/boot/dts/stm32f746.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 1479e3e..f48d06a 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -297,7 +297,7 @@
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
- st,syscfg = <&pwrcfg>;
+ st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 0/2] arm64: dts: renesas: r8a77970: Add SMP Support
From: Geert Uytterhoeven @ 2018-05-09 15:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon, Magnus,
This patch series enables SMP support on the R-Car V3M SoC, by adding
the second Cortex-A53 CPU core. It also adds the performance monitor
unit, and links it to both CPU cores.
Changes compared to v1:
- Adjust GIC_CPU_MASK_SIMPLE(),
- Use symbolic core clock and power domain indices,
- Move the pmu node from the soc subnode to the root node, as it
doesn't have registers.
Note that the PSCI implementation on Eagle may be a preliminary version
with some familiar quirks:
- SMP bringup works, and both CPUs can be used,
- Offlining CPU0 crashes the system,
- CPU1 can be offlined, but trying to bring it online again crashes
the system, too.
I'm confident these will be fixed in future firmware versions, just like
on H3/Salvator-X. Note that
git at github.com:renesas-rcar/arm-trusted-firmware.git does not have
support for R-Car V3M, V3H, and D3.
Thanks!
Geert Uytterhoeven (2):
arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.7.4
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v2 1/2] arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
From: Geert Uytterhoeven @ 2018-05-09 15:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525879403-12207-1-git-send-email-geert+renesas@glider.be>
Add a device node for the second Cortex-A53 CPU core on the Renesas
R-Car V3M (r8a77970) SoC, and adjust the interrupt delivery masks for
ARM Generic Interrupt Controller and Architectured Timer.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
- Adjust GIC_CPU_MASK_SIMPLE(),
- Use symbolic core clock and power domain indices.
---
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 6ed2e95eb53dbb15..ccc955e89cea4d32 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -41,6 +41,16 @@
enable-method = "psci";
};
+ a53_1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <1>;
+ clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
+ power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
L2_CA53: cache-controller {
compatible = "cache";
power-domains = <&sysc R8A77970_PD_CA53_SCU>;
@@ -603,7 +613,7 @@
<0 0xf1020000 0 0x20000>,
<0 0xf1040000 0 0x20000>,
<0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
@@ -694,9 +704,9 @@
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/2] arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node
From: Geert Uytterhoeven @ 2018-05-09 15:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525879403-12207-1-git-send-email-geert+renesas@glider.be>
Enable the performance monitor unit for the Cortex-A53 cores on the
R-Car V3M (r8a77970) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
- Move the pmu node from the soc subnode to the root node, as it
doesn't have registers.
---
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index ccc955e89cea4d32..71157ad893910a97 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -73,6 +73,13 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
--
2.7.4
^ permalink raw reply related
* [PATCH 2/4] pid: Export find_task_by_vpid for use in external modules
From: Mathieu Poirier @ 2018-05-09 15:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87d0y5toed.fsf@xmission.com>
On Tue, May 08, 2018 at 11:59:38PM -0500, Eric W. Biederman wrote:
> Kim Phillips <kim.phillips@arm.com> writes:
>
> > This patch is in the context of allowing the Coresight h/w
> > trace driver suite to be loaded as modules. Coresight uses
> > find_task_by_vpid when running in direct capture mode (via sysfs)
> > when getting/setting the context ID comparator to trigger on
> > (/sys/bus/coresight/devices/<x>.etm/ctxid_pid).
>
> Aside from my objection about how bad an interface a pid in sysfs is.
> The implementation of coresight_vpid_to_pid is horrible.
>
> The code should be just:
>
> static inline pid_t coresight_vpid_to_pid(pid_t vpid)
> {
> rcu_read_lock();
> pid = pid_nr(find_vpid(vpid));
> rcu_read_unlock();
>
> return pid;
> }
> Which takes find_task_by_vpid out of the picture.
Many thanks for pointing out the right way to do this. When Chunyan added
this feature she broadly published her work and find_task_by_vpid() is the
function she was asked to used.
>
> But reading further I am seeing code writing a pid to hardware. That is
> broken. That is a layering violation of the first order. Giving
> implementation details like that to hardware.
This is how the feature works - as Robin pointed out tracers are designed to
match pid values with the CPU's contextID register. The input value has no
other effect than triggering trace collection, which has absolutely no baring on
the CPU.
>
> Any chance while you are working on this you can modify this code so
> that it does something sensible and defensible instead of every line of
> code I read be wrong in at least one detail?
>
> Thank you,
> Eric
>
^ permalink raw reply
* [PATCH] ARM: DTS: imx53: Add support for imx53 HSC/DDC boards from K+P
From: Lukasz Majewski @ 2018-05-09 15:34 UTC (permalink / raw)
To: linux-arm-kernel
This commit provides support for HSC and DDC boards from
Kieback&Peter GmbH vendor.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx53-kp-ddc.dts | 146 ++++++++++++++++++++++++++++
arch/arm/boot/dts/imx53-kp-hsc.dts | 53 ++++++++++
arch/arm/boot/dts/imx53-kp.dtsi | 191 +++++++++++++++++++++++++++++++++++++
4 files changed, 392 insertions(+)
create mode 100644 arch/arm/boot/dts/imx53-kp-ddc.dts
create mode 100644 arch/arm/boot/dts/imx53-kp-hsc.dts
create mode 100644 arch/arm/boot/dts/imx53-kp.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fbc04b0db781..00854a5b6ac4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -360,6 +360,8 @@ dtb-$(CONFIG_SOC_IMX51) += \
dtb-$(CONFIG_SOC_IMX53) += \
imx53-ard.dtb \
imx53-cx9020.dtb \
+ imx53-kp-ddc.dtb \
+ imx53-kp-hsc.dtb \
imx53-m53evk.dtb \
imx53-mba53.dtb \
imx53-ppd.dtb \
diff --git a/arch/arm/boot/dts/imx53-kp-ddc.dts b/arch/arm/boot/dts/imx53-kp-ddc.dts
new file mode 100644
index 000000000000..acaf477a52c5
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-kp-ddc.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ */
+
+/dts-v1/;
+#include "imx53-kp.dtsi"
+
+/ {
+ model = "K+P imx53 DDC";
+ compatible = "kiebackpeter,imx53-ddc", "fsl,imx53";
+
+ backlight_lcd: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 50000>;
+ power-supply = <®_backlight>;
+ brightness-levels = <0 24 28 32 36
+ 40 44 48 52 56
+ 60 64 68 72 76
+ 80 84 88 92 96 100>;
+ default-brightness-level = <20>;
+ };
+
+ lcd_display: disp1 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_disp>;
+
+ port at 0 {
+ reg = <0>;
+
+ display1_in: endpoint {
+ remote-endpoint = <&ipu_di1_disp1>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ lcd_panel: lcd-panel {
+ compatible = "koe,tx14d24vm1bpa";
+ backlight = <&backlight_lcd>;
+ power-supply = <®_3v3>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ reg_backlight: regulator-backlight {
+ compatible = "regulator-fixed";
+ regulator-name = "backlight-supply";
+ regulator-min-microvolt = <15000000>;
+ regulator-max-microvolt = <15000000>;
+ regulator-always-on;
+ };
+};
+
+&i2c3 {
+ adc at 48 {
+ compatible = "ti,ads1015";
+ reg = <0x48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel at 4 {
+ reg = <4>;
+ ti,gain = <2>;
+ ti,datarate = <4>;
+ };
+
+ channel at 6 {
+ reg = <6>;
+ ti,gain = <2>;
+ ti,datarate = <4>;
+ };
+ };
+
+ gpio_expander2 at 21 {
+ compatible = "nxp,pcf8574";
+ reg = <0x21>;
+ interrupts = <109>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};
+
+&iomuxc {
+ imx53-kp-ddc {
+ pinctrl_disp: dispgrp {
+ fsl,pins = <
+ MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4
+ MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4
+ MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4
+ MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4
+ MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4
+ MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4
+ MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4
+ MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4
+ MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4
+ MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4
+ MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4
+ MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4
+ MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4
+ MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4
+ MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4
+ MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4
+ MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4
+ MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4
+ MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4
+ MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4
+ MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4
+ MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4
+ MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4
+ MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4
+ MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4
+ MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4
+ MX53_PAD_GPIO_1__PWM2_PWMO 0x4
+ >;
+ };
+ };
+};
+
+&ipu_di1_disp1 {
+ remote-endpoint = <&display1_in>;
+};
+
+&fec {
+ status = "okay";
+};
+
+&pmic {
+ fsl,mc13xxx-uses-touch;
+};
diff --git a/arch/arm/boot/dts/imx53-kp-hsc.dts b/arch/arm/boot/dts/imx53-kp-hsc.dts
new file mode 100644
index 000000000000..fff358395c9d
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-kp-hsc.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ */
+
+/dts-v1/;
+#include "imx53-kp.dtsi"
+
+/ {
+ model = "K+P imx53 HSC";
+ compatible = "kiebackpeter,imx53-hsc", "fsl,imx53";
+
+};
+
+&fec {
+ status = "okay";
+
+ fixed-link { /* RMII fixed link to LAN9303 */
+ speed = <100>;
+ full-duplex;
+ };
+};
+
+&i2c3 {
+ switch: switch at a {
+ compatible = "smsc,lan9303-i2c";
+ reg = <0xa>;
+ reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ reset-duration = <400>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 { /* RMII fixed link to master */
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&fec>;
+ };
+
+ port at 1 { /* external port 1 */
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port at 2 { /* external port 2 */
+ reg = <2>;
+ label = "lan2";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/imx53-kp.dtsi
new file mode 100644
index 000000000000..86bea3217f18
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-kp.dtsi
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
+ */
+
+/dts-v1/;
+#include "imx53-tqma53.dtsi"
+
+/ {
+ buzzer {
+ compatible = "pwm-beeper";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_buzzer>;
+
+ pwms = <&pwm1 0 500000>;
+ };
+
+ gpio_buttons {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiobuttons>;
+
+ button at 1 {
+ label = "Kaltstart";
+ linux,code = <64>; /* KEY_F6 */
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ };
+ button at 2 {
+ label = "PowerFailInterrupt";
+ linux,code = <65>; /* KEY_F7 */
+ gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ led_bus {
+ label = "bus";
+ gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "off";
+ };
+
+ led_error {
+ label = "error";
+ gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "off";
+ };
+
+ led_flash {
+ label = "flash";
+ gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ gpio_expander1 at 22 {
+ compatible = "nxp,pcf8574";
+ reg = <0x22>;
+ interrupts = <109>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ rtc at 51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_kp_common>;
+
+ imx53-kp-common {
+ pinctrl_buzzer: buzzergrp {
+ fsl,pins = <
+ MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4
+ >;
+ };
+
+ pinctrl_gpiobuttons: gpiobuttonsgrp {
+ fsl,pins = <
+ MX53_PAD_EIM_RW__GPIO2_26 0x1e4
+ MX53_PAD_EIM_D22__GPIO3_22 0x1e4
+ >;
+ };
+
+ pinctrl_kp_common: kpcommongrp {
+ fsl,pins = <
+ MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
+ MX53_PAD_GPIO_19__GPIO4_5 0x1e4
+ MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4
+ MX53_PAD_PATA_DATA7__GPIO2_7 0xe0
+ MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4
+ MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4
+ MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4
+ MX53_PAD_EIM_D17__GPIO3_17 0x1e4
+ MX53_PAD_EIM_D18__GPIO3_18 0x1e4
+ MX53_PAD_EIM_D21__GPIO3_21 0x1e4
+ MX53_PAD_EIM_D29__GPIO3_29 0x1e4
+ MX53_PAD_EIM_DA11__GPIO3_11 0x1e4
+ MX53_PAD_EIM_DA13__GPIO3_13 0x1e4
+ MX53_PAD_EIM_DA14__GPIO3_14 0x1e4
+ MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4
+ MX53_PAD_SD1_CMD__GPIO1_18 0x1e4
+ MX53_PAD_SD1_CLK__GPIO1_20 0x1e4
+ >;
+ };
+
+ pinctrl_leds: ledgrp {
+ fsl,pins = <
+ MX53_PAD_EIM_EB2__GPIO2_30 0x1d4
+ MX53_PAD_EIM_D28__GPIO3_28 0x1d4
+ MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4
+ MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4
+ >;
+ };
+ };
+};
+
+&pinctrl_uart1 {
+ fsl,pins = <
+ MX53_PAD_EIM_D23__GPIO3_23 0x1e4
+ MX53_PAD_EIM_EB3__GPIO2_31 0x1e4
+ MX53_PAD_EIM_D24__GPIO3_24 0x1e4
+ MX53_PAD_EIM_D25__GPIO3_25 0x1e4
+ MX53_PAD_EIM_D19__GPIO3_19 0x1e4
+ MX53_PAD_EIM_D20__GPIO3_20 0x1e4
+ >;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "disabled";
+};
--
2.11.0
^ permalink raw reply related
* [PATCH v3 0/2] clk: davinci: pll-dm355: fix SYSCLKn parent names
From: David Lechner @ 2018-05-09 15:36 UTC (permalink / raw)
To: linux-arm-kernel
v3 changes:
* swap order of patches
v2 changes:
* add new patch to remove non-existent PLL2 SYSCLK2
David Lechner (2):
clk: davinci: pll-dm355: drop pll2_sysclk2
clk: davinci: pll-dm355: fix SYSCLKn parent names
drivers/clk/davinci/pll-dm355.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
--
2.17.0
^ permalink raw reply
* [PATCH v3 1/2] clk: davinci: pll-dm355: drop pll2_sysclk2
From: David Lechner @ 2018-05-09 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180509153642.22399-1-david@lechnology.com>
This removes pll2_sysclk2 from the TI DM355 clock driver. This SoC
doesn't have such a clock. Also, SYSCLK_ALWAYS_ENABLED is transferred
to pll2_sysclk1 since it drives the DDR and doesn't have another
mechanism to keep it on.
Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/pll-dm355.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/clk/davinci/pll-dm355.c b/drivers/clk/davinci/pll-dm355.c
index 5345f8286c50..718d9bbbf30d 100644
--- a/drivers/clk/davinci/pll-dm355.c
+++ b/drivers/clk/davinci/pll-dm355.c
@@ -62,8 +62,7 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
};
-SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
-SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
int dm355_pll2_init(struct device *dev, void __iomem *base)
{
@@ -71,8 +70,6 @@ int dm355_pll2_init(struct device *dev, void __iomem *base)
davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
- davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
-
davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
return 0;
--
2.17.0
^ permalink raw reply related
* [PATCH v3 2/2] clk: davinci: pll-dm355: fix SYSCLKn parent names
From: David Lechner @ 2018-05-09 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180509153642.22399-1-david@lechnology.com>
This fixes the parent clock names of the SYSCLKn clocks for the DM355
SoC in the TI DaVinici PLL clock driver.
It appears that this name just didn't get updated to the correct name
like the other SoCs during the driver's development.
Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/pll-dm355.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/davinci/pll-dm355.c b/drivers/clk/davinci/pll-dm355.c
index 718d9bbbf30d..93f4a53d6b44 100644
--- a/drivers/clk/davinci/pll-dm355.c
+++ b/drivers/clk/davinci/pll-dm355.c
@@ -22,10 +22,10 @@ static const struct davinci_pll_clk_info dm355_pll1_info = {
PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
};
-SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
int dm355_pll1_init(struct device *dev, void __iomem *base)
{
@@ -62,7 +62,7 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
};
-SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
int dm355_pll2_init(struct device *dev, void __iomem *base)
{
--
2.17.0
^ permalink raw reply related
* [PATCH 1/4] amba: Export amba_bustype
From: Mathieu Poirier @ 2018-05-09 15:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8c2648ec-1379-fb2a-35d2-b3fa8fc9f063@arm.com>
On Wed, May 09, 2018 at 02:38:32PM +0100, Robin Murphy wrote:
> Hi Kim,
>
> On 08/05/18 20:06, Kim Phillips wrote:
> >This patch is provided in the context of allowing the Coresight driver
> >subsystem to be loaded as modules. Coresight uses amba_bus in its call
> >to bus_find_device() in of_coresight_get_endpoint_device() when
> >searching for a configurable endpoint device. This patch allows
> >Coresight to reference amba_bustype when built as a module.
> >
> >Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> >Cc: Alex Williamson <alex.williamson@redhat.com>
> >Cc: Eric Auger <eric.auger@redhat.com>
> >Cc: Russell King <linux@armlinux.org.uk>
> >Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> >Cc: Todd Kjos <tkjos@google.com>
> >Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> >Cc: Thierry Reding <treding@nvidia.com>
> >Cc: Robin Murphy <robin.murphy@arm.com>
> >Signed-off-by: Kim Phillips <kim.phillips@arm.com>
> >---
> >There was a prior patch submitted by Alex W. here:
> >
> >https://lkml.org/lkml/2017/6/19/811
> >
> >But I can't tell its fate - presume simply delayed?
> >
> >Coresight uses amba_bus in its call to bus_find_device() here:
> >
> >https://lxr.missinglinkelectronics.com/linux/drivers/hwtracing/coresight/of_coresight.c#L51
> >
> >Grepping for bus_type and EXPORT shows other busses exporting their
> >type, so I don't think this is the wrong approach. If, OTOH, Coresight
> >needs to do something differently, please comment.
>
> Exposing raw bus_types is pretty ugly, but it is indeed the status quo, so
> this probably is the reasonable thing to do. I suppose an amba_bus
> equivalent of of_find_device_by_node() could be implemented, but for only a
> single potential user that doesn't seem particularly worthwhile, since
> unless some massive shake-up of how buses work comes along the bus_type will
> inevitably end up being exported for other reasons anyway. So, in the
> context of this series;
>
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
>
> However, as a wild idea for sidestepping the issue completely (or at least
> keeping it within the CoreSight framework), at first glance it appears
> something like the below might be feasible, although I may well be missing
> some obvious reason why not.
>
> Thanks,
> Robin.
>
> ----->8-----
> diff --git a/drivers/hwtracing/coresight/of_coresight.c
> b/drivers/hwtracing/coresight/of_coresight.c
> index 7c375443ede6..2c3fdc9b63e6 100644
> --- a/drivers/hwtracing/coresight/of_coresight.c
> +++ b/drivers/hwtracing/coresight/of_coresight.c
> @@ -27,28 +27,13 @@
>
> static int of_dev_node_match(struct device *dev, void *data)
> {
> - return dev->of_node == data;
> + return dev->parent->of_node == data;
> }
>
> static struct device *
> of_coresight_get_endpoint_device(struct device_node *endpoint)
> {
> - struct device *dev = NULL;
> -
> - /*
> - * If we have a non-configurable replicator, it will be found on the
> - * platform bus.
> - */
> - dev = bus_find_device(&platform_bus_type, NULL,
> - endpoint, of_dev_node_match);
> - if (dev)
> - return dev;
> -
> - /*
> - * We have a configurable component - circle through the AMBA bus
> - * looking for the device that matches the endpoint node.
> - */
> - return bus_find_device(&amba_bustype, NULL,
> + return bus_find_device(&coresight_bustype, NULL,
> endpoint, of_dev_node_match);
> }
Hi Robin and thanks for the input.
Your approach would work if all CS devices would be on the CS bus, which is not
the case at discovery time when of_coresight_get_endpoint_device() is called.
Mathieu
>
^ permalink raw reply
* [PATCH v2 0/3] Introduce STM32MP1 RTC
From: Amelie Delaunay @ 2018-05-09 15:46 UTC (permalink / raw)
To: linux-arm-kernel
This series introduces STM32MP1 RTC.
On STM32MP1:
- two clocks are needed, plck and rtc_ck;
- to wakeup the system, a wakeup alarm interrupt is needed;
- some registers or bits have moved, but the operation is the same;
- the Backup Domain Protection (DBP) is not managed by RTC driver.
---
Changes in v2:
* One compatible per line in bindings file
* Remove unnecessary comment under rtc_ck as this clock is required for all
* Remove interrupts-extended and add stm32mp1 rtc alarm wakeup interrupt in
interrupts property description
Amelie Delaunay (3):
rtc: stm32: rework register management to prepare other version of RTC
dt-bindings: rtc: update stm32-rtc documentation for stm32mp1 rtc
rtc: stm32: add stm32mp1 rtc support
.../devicetree/bindings/rtc/st,stm32-rtc.txt | 27 +-
drivers/rtc/rtc-stm32.c | 272 ++++++++++++++++-----
2 files changed, 228 insertions(+), 71 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v2 1/3] rtc: stm32: rework register management to prepare other version of RTC
From: Amelie Delaunay @ 2018-05-09 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525880770-22263-1-git-send-email-amelie.delaunay@st.com>
This patch reworks register/bits management because next version of RTC
uses the same way of working but with different register's offset or bits
moved in new registers.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
drivers/rtc/rtc-stm32.c | 188 +++++++++++++++++++++++++++++++++---------------
1 file changed, 129 insertions(+), 59 deletions(-)
diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c
index de49b5b..52ee027 100644
--- a/drivers/rtc/rtc-stm32.c
+++ b/drivers/rtc/rtc-stm32.c
@@ -16,15 +16,6 @@
#define DRIVER_NAME "stm32_rtc"
-/* STM32 RTC registers */
-#define STM32_RTC_TR 0x00
-#define STM32_RTC_DR 0x04
-#define STM32_RTC_CR 0x08
-#define STM32_RTC_ISR 0x0C
-#define STM32_RTC_PRER 0x10
-#define STM32_RTC_ALRMAR 0x1C
-#define STM32_RTC_WPR 0x24
-
/* STM32_RTC_TR bit fields */
#define STM32_RTC_TR_SEC_SHIFT 0
#define STM32_RTC_TR_SEC GENMASK(6, 0)
@@ -85,7 +76,26 @@
#define RTC_WPR_2ND_KEY 0x53
#define RTC_WPR_WRONG_KEY 0xFF
+struct stm32_rtc;
+
+struct stm32_rtc_registers {
+ u8 tr;
+ u8 dr;
+ u8 cr;
+ u8 isr;
+ u8 prer;
+ u8 alrmar;
+ u8 wpr;
+};
+
+struct stm32_rtc_events {
+ u32 alra;
+};
+
struct stm32_rtc_data {
+ const struct stm32_rtc_registers regs;
+ const struct stm32_rtc_events events;
+ void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
bool has_pclk;
bool need_dbp;
};
@@ -96,30 +106,35 @@ struct stm32_rtc {
struct regmap *dbp;
unsigned int dbp_reg;
unsigned int dbp_mask;
- struct stm32_rtc_data *data;
struct clk *pclk;
struct clk *rtc_ck;
+ const struct stm32_rtc_data *data;
int irq_alarm;
};
static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
{
- writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + STM32_RTC_WPR);
- writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + STM32_RTC_WPR);
+ struct stm32_rtc_registers regs = rtc->data->regs;
+
+ writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs.wpr);
+ writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs.wpr);
}
static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
{
- writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + STM32_RTC_WPR);
+ struct stm32_rtc_registers regs = rtc->data->regs;
+
+ writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs.wpr);
}
static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
{
- unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
+ struct stm32_rtc_registers regs = rtc->data->regs;
+ unsigned int isr = readl_relaxed(rtc->base + regs.isr);
if (!(isr & STM32_RTC_ISR_INITF)) {
isr |= STM32_RTC_ISR_INIT;
- writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
+ writel_relaxed(isr, rtc->base + regs.isr);
/*
* It takes around 2 rtc_ck clock cycles to enter in
@@ -128,7 +143,7 @@ static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
* 1MHz, we poll every 10 us with a timeout of 100ms.
*/
return readl_relaxed_poll_timeout_atomic(
- rtc->base + STM32_RTC_ISR,
+ rtc->base + regs.isr,
isr, (isr & STM32_RTC_ISR_INITF),
10, 100000);
}
@@ -138,40 +153,50 @@ static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
{
- unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
+ struct stm32_rtc_registers regs = rtc->data->regs;
+ unsigned int isr = readl_relaxed(rtc->base + regs.isr);
isr &= ~STM32_RTC_ISR_INIT;
- writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
+ writel_relaxed(isr, rtc->base + regs.isr);
}
static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
{
- unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
+ struct stm32_rtc_registers regs = rtc->data->regs;
+ unsigned int isr = readl_relaxed(rtc->base + regs.isr);
isr &= ~STM32_RTC_ISR_RSF;
- writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
+ writel_relaxed(isr, rtc->base + regs.isr);
/*
* Wait for RSF to be set to ensure the calendar registers are
* synchronised, it takes around 2 rtc_ck clock cycles
*/
- return readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
+ return readl_relaxed_poll_timeout_atomic(rtc->base + regs.isr,
isr,
(isr & STM32_RTC_ISR_RSF),
10, 100000);
}
+static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
+ unsigned int flags)
+{
+ rtc->data->clear_events(rtc, flags);
+}
+
static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
{
struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
- unsigned int isr, cr;
+ struct stm32_rtc_registers regs = rtc->data->regs;
+ struct stm32_rtc_events evts = rtc->data->events;
+ unsigned int status, cr;
mutex_lock(&rtc->rtc_dev->ops_lock);
- isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
- cr = readl_relaxed(rtc->base + STM32_RTC_CR);
+ status = readl_relaxed(rtc->base + regs.isr);
+ cr = readl_relaxed(rtc->base + regs.cr);
- if ((isr & STM32_RTC_ISR_ALRAF) &&
+ if ((status & evts.alra) &&
(cr & STM32_RTC_CR_ALRAIE)) {
/* Alarm A flag - Alarm interrupt */
dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
@@ -179,9 +204,8 @@ static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
/* Pass event to the kernel */
rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
- /* Clear event flag, otherwise new events won't be received */
- writel_relaxed(isr & ~STM32_RTC_ISR_ALRAF,
- rtc->base + STM32_RTC_ISR);
+ /* Clear event flags, otherwise new events won't be received */
+ stm32_rtc_clear_event_flags(rtc, evts.alra);
}
mutex_unlock(&rtc->rtc_dev->ops_lock);
@@ -228,11 +252,12 @@ static void bcd2tm(struct rtc_time *tm)
static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
+ struct stm32_rtc_registers regs = rtc->data->regs;
unsigned int tr, dr;
/* Time and Date in BCD format */
- tr = readl_relaxed(rtc->base + STM32_RTC_TR);
- dr = readl_relaxed(rtc->base + STM32_RTC_DR);
+ tr = readl_relaxed(rtc->base + regs.tr);
+ dr = readl_relaxed(rtc->base + regs.dr);
tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
@@ -253,6 +278,7 @@ static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
+ struct stm32_rtc_registers regs = rtc->data->regs;
unsigned int tr, dr;
int ret = 0;
@@ -277,8 +303,8 @@ static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
goto end;
}
- writel_relaxed(tr, rtc->base + STM32_RTC_TR);
- writel_relaxed(dr, rtc->base + STM32_RTC_DR);
+ writel_relaxed(tr, rtc->base + regs.tr);
+ writel_relaxed(dr, rtc->base + regs.dr);
stm32_rtc_exit_init_mode(rtc);
@@ -292,12 +318,14 @@ static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
+ struct stm32_rtc_registers regs = rtc->data->regs;
+ struct stm32_rtc_events evts = rtc->data->events;
struct rtc_time *tm = &alrm->time;
- unsigned int alrmar, cr, isr;
+ unsigned int alrmar, cr, status;
- alrmar = readl_relaxed(rtc->base + STM32_RTC_ALRMAR);
- cr = readl_relaxed(rtc->base + STM32_RTC_CR);
- isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
+ alrmar = readl_relaxed(rtc->base + regs.alrmar);
+ cr = readl_relaxed(rtc->base + regs.cr);
+ status = readl_relaxed(rtc->base + regs.isr);
if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
/*
@@ -350,7 +378,7 @@ static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
bcd2tm(tm);
alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
- alrm->pending = (isr & STM32_RTC_ISR_ALRAF) ? 1 : 0;
+ alrm->pending = (status & evts.alra) ? 1 : 0;
return 0;
}
@@ -358,9 +386,11 @@ static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
- unsigned int isr, cr;
+ struct stm32_rtc_registers regs = rtc->data->regs;
+ struct stm32_rtc_events evts = rtc->data->events;
+ unsigned int cr;
- cr = readl_relaxed(rtc->base + STM32_RTC_CR);
+ cr = readl_relaxed(rtc->base + regs.cr);
stm32_rtc_wpr_unlock(rtc);
@@ -369,12 +399,10 @@ static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
else
cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
- writel_relaxed(cr, rtc->base + STM32_RTC_CR);
+ writel_relaxed(cr, rtc->base + regs.cr);
- /* Clear event flag, otherwise new events won't be received */
- isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
- isr &= ~STM32_RTC_ISR_ALRAF;
- writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
+ /* Clear event flags, otherwise new events won't be received */
+ stm32_rtc_clear_event_flags(rtc, evts.alra);
stm32_rtc_wpr_lock(rtc);
@@ -383,9 +411,10 @@ static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
{
+ struct stm32_rtc_registers regs = rtc->data->regs;
int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec;
- unsigned int dr = readl_relaxed(rtc->base + STM32_RTC_DR);
- unsigned int tr = readl_relaxed(rtc->base + STM32_RTC_TR);
+ unsigned int dr = readl_relaxed(rtc->base + regs.dr);
+ unsigned int tr = readl_relaxed(rtc->base + regs.tr);
cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
@@ -419,6 +448,7 @@ static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
+ struct stm32_rtc_registers regs = rtc->data->regs;
struct rtc_time *tm = &alrm->time;
unsigned int cr, isr, alrmar;
int ret = 0;
@@ -450,15 +480,15 @@ static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
stm32_rtc_wpr_unlock(rtc);
/* Disable Alarm */
- cr = readl_relaxed(rtc->base + STM32_RTC_CR);
+ cr = readl_relaxed(rtc->base + regs.cr);
cr &= ~STM32_RTC_CR_ALRAE;
- writel_relaxed(cr, rtc->base + STM32_RTC_CR);
+ writel_relaxed(cr, rtc->base + regs.cr);
/*
* Poll Alarm write flag to be sure that Alarm update is allowed: it
* takes around 2 rtc_ck clock cycles
*/
- ret = readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
+ ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs.isr,
isr,
(isr & STM32_RTC_ISR_ALRAWF),
10, 100000);
@@ -469,7 +499,7 @@ static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
}
/* Write to Alarm register */
- writel_relaxed(alrmar, rtc->base + STM32_RTC_ALRMAR);
+ writel_relaxed(alrmar, rtc->base + regs.alrmar);
if (alrm->enabled)
stm32_rtc_alarm_irq_enable(dev, 1);
@@ -490,14 +520,50 @@ static const struct rtc_class_ops stm32_rtc_ops = {
.alarm_irq_enable = stm32_rtc_alarm_irq_enable,
};
+static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
+ unsigned int flags)
+{
+ struct stm32_rtc_registers regs = rtc->data->regs;
+
+ /* Flags are cleared by writing 0 in RTC_ISR */
+ writel_relaxed(readl_relaxed(rtc->base + regs.isr) & ~flags,
+ rtc->base + regs.isr);
+}
+
static const struct stm32_rtc_data stm32_rtc_data = {
.has_pclk = false,
.need_dbp = true,
+ .regs = {
+ .tr = 0x00,
+ .dr = 0x04,
+ .cr = 0x08,
+ .isr = 0x0C,
+ .prer = 0x10,
+ .alrmar = 0x1C,
+ .wpr = 0x24,
+ },
+ .events = {
+ .alra = STM32_RTC_ISR_ALRAF,
+ },
+ .clear_events = stm32_rtc_clear_events,
};
static const struct stm32_rtc_data stm32h7_rtc_data = {
.has_pclk = true,
.need_dbp = true,
+ .regs = {
+ .tr = 0x00,
+ .dr = 0x04,
+ .cr = 0x08,
+ .isr = 0x0C,
+ .prer = 0x10,
+ .alrmar = 0x1C,
+ .wpr = 0x24,
+ },
+ .events = {
+ .alra = STM32_RTC_ISR_ALRAF,
+ },
+ .clear_events = stm32_rtc_clear_events,
};
static const struct of_device_id stm32_rtc_of_match[] = {
@@ -510,6 +576,7 @@ MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
static int stm32_rtc_init(struct platform_device *pdev,
struct stm32_rtc *rtc)
{
+ struct stm32_rtc_registers regs = rtc->data->regs;
unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
unsigned int rate;
int ret = 0;
@@ -550,14 +617,14 @@ static int stm32_rtc_init(struct platform_device *pdev,
}
prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
- writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
+ writel_relaxed(prer, rtc->base + regs.prer);
prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
- writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
+ writel_relaxed(prer, rtc->base + regs.prer);
/* Force 24h time format */
- cr = readl_relaxed(rtc->base + STM32_RTC_CR);
+ cr = readl_relaxed(rtc->base + regs.cr);
cr &= ~STM32_RTC_CR_FMT;
- writel_relaxed(cr, rtc->base + STM32_RTC_CR);
+ writel_relaxed(cr, rtc->base + regs.cr);
stm32_rtc_exit_init_mode(rtc);
@@ -571,6 +638,7 @@ static int stm32_rtc_init(struct platform_device *pdev,
static int stm32_rtc_probe(struct platform_device *pdev)
{
struct stm32_rtc *rtc;
+ struct stm32_rtc_registers regs;
struct resource *res;
int ret;
@@ -585,6 +653,7 @@ static int stm32_rtc_probe(struct platform_device *pdev)
rtc->data = (struct stm32_rtc_data *)
of_device_get_match_data(&pdev->dev);
+ regs = rtc->data->regs;
if (rtc->data->need_dbp) {
rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
@@ -641,7 +710,7 @@ static int stm32_rtc_probe(struct platform_device *pdev)
/*
* After a system reset, RTC_ISR.INITS flag can be read to check if
- * the calendar has been initalized or not. INITS flag is reset by a
+ * the calendar has been initialized or not. INITS flag is reset by a
* power-on reset (no vbat, no power-supply). It is not reset if
* rtc_ck parent clock has changed (so RTC prescalers need to be
* changed). That's why we cannot rely on this flag to know if RTC
@@ -666,7 +735,7 @@ static int stm32_rtc_probe(struct platform_device *pdev)
"alarm won't be able to wake up the system");
rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
- &stm32_rtc_ops, THIS_MODULE);
+ &stm32_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc->rtc_dev)) {
ret = PTR_ERR(rtc->rtc_dev);
dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
@@ -688,7 +757,7 @@ static int stm32_rtc_probe(struct platform_device *pdev)
* If INITS flag is reset (calendar year field set to 0x00), calendar
* must be initialized
*/
- if (!(readl_relaxed(rtc->base + STM32_RTC_ISR) & STM32_RTC_ISR_INITS))
+ if (!(readl_relaxed(rtc->base + regs.isr) & STM32_RTC_ISR_INITS))
dev_warn(&pdev->dev, "Date/Time must be initialized\n");
return 0;
@@ -708,13 +777,14 @@ static int stm32_rtc_probe(struct platform_device *pdev)
static int stm32_rtc_remove(struct platform_device *pdev)
{
struct stm32_rtc *rtc = platform_get_drvdata(pdev);
+ struct stm32_rtc_registers regs = rtc->data->regs;
unsigned int cr;
/* Disable interrupts */
stm32_rtc_wpr_unlock(rtc);
- cr = readl_relaxed(rtc->base + STM32_RTC_CR);
+ cr = readl_relaxed(rtc->base + regs.cr);
cr &= ~STM32_RTC_CR_ALRAIE;
- writel_relaxed(cr, rtc->base + STM32_RTC_CR);
+ writel_relaxed(cr, rtc->base + regs.cr);
stm32_rtc_wpr_lock(rtc);
clk_disable_unprepare(rtc->rtc_ck);
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/3] dt-bindings: rtc: update stm32-rtc documentation for stm32mp1 rtc
From: Amelie Delaunay @ 2018-05-09 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525880770-22263-1-git-send-email-amelie.delaunay@st.com>
RTC embedded in stm32mp1 SoC is slightly different from stm32h7 one, it
doesn't require to disable backup domain write protection, and rtc_ck
parent clock assignment isn't allowed.
To sum up, stm32mp1 RTC requires 2 clocks, pclk and rtc_ck, and an RTC
alarm interrupt.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
.../devicetree/bindings/rtc/st,stm32-rtc.txt | 27 ++++++++++++++++------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt
index 00f8b5d..c920e27 100644
--- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt
@@ -1,25 +1,29 @@
STM32 Real Time Clock
Required properties:
-- compatible: can be either "st,stm32-rtc" or "st,stm32h7-rtc", depending on
- the device is compatible with stm32(f4/f7) or stm32h7.
+- compatible: can be one of the following:
+ - "st,stm32-rtc" for devices compatible with stm32(f4/f7).
+ - "st,stm32h7-rtc" for devices compatible with stm32h7.
+ - "st,stm32mp1-rtc" for devices compatible with stm32mp1.
- reg: address range of rtc register set.
- clocks: can use up to two clocks, depending on part used:
- "rtc_ck": RTC clock source.
- It is required on stm32(f4/f7) and stm32h7.
- "pclk": RTC APB interface clock.
It is not present on stm32(f4/f7).
- It is required on stm32h7.
+ It is required on stm32(h7/mp1).
- clock-names: must be "rtc_ck" and "pclk".
- It is required only on stm32h7.
+ It is required on stm32(h7/mp1).
- interrupt-parent: phandle for the interrupt controller.
-- interrupts: rtc alarm interrupt.
+ It is required on stm32(f4/f7/h7).
+- interrupts: rtc alarm interrupt. On stm32mp1, a second interrupt is required
+ for rtc alarm wakeup interrupt.
- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to
access control register at offset, and change the dbp (Disable Backup
Protection) bit represented by the mask, mandatory to disable/enable backup
domain (RTC registers) write protection.
+ It is required on stm32(f4/f7/h7).
-Optional properties (to override default rtc_ck parent clock):
+Optional properties (to override default rtc_ck parent clock on stm32(f4/f7/h7):
- assigned-clocks: reference to the rtc_ck clock entry.
- assigned-clock-parents: phandle of the new parent clock of rtc_ck.
@@ -48,3 +52,12 @@ Example:
interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
};
+
+ rtc: rtc at 5c004000 {
+ compatible = "st,stm32mp1-rtc";
+ reg = <0x5c004000 0x400>;
+ clocks = <&rcc RTCAPB>, <&rcc RTC>;
+ clock-names = "pclk", "rtc_ck";
+ interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_NONE>,
+ <&exti 19 1>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v2 3/3] rtc: stm32: add stm32mp1 rtc support
From: Amelie Delaunay @ 2018-05-09 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525880770-22263-1-git-send-email-amelie.delaunay@st.com>
This patch adds support for stm32mp1 RTC.
Some common registers with previous RTC version have a different offset.
It is the case for Control Register (CR) and ALaRMA Register (ALRMAR).
There are also new registers regarding event flags: now, Alarm event flag
is in Status Register (SR) and write 1 in Status Clear Register (SCR) is
required to clear the event.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
drivers/rtc/rtc-stm32.c | 88 +++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 81 insertions(+), 7 deletions(-)
diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c
index 52ee027..45e0175 100644
--- a/drivers/rtc/rtc-stm32.c
+++ b/drivers/rtc/rtc-stm32.c
@@ -11,6 +11,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
@@ -39,7 +40,7 @@
#define STM32_RTC_CR_ALRAE BIT(8)
#define STM32_RTC_CR_ALRAIE BIT(12)
-/* STM32_RTC_ISR bit fields */
+/* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
#define STM32_RTC_ISR_ALRAWF BIT(0)
#define STM32_RTC_ISR_INITS BIT(4)
#define STM32_RTC_ISR_RSF BIT(5)
@@ -71,11 +72,22 @@
#define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)
#define STM32_RTC_ALRMXR_DATE_MASK BIT(31)
+/* STM32_RTC_SR/_SCR bit fields */
+#define STM32_RTC_SR_ALRA BIT(0)
+
+/* STM32_RTC_VERR bit fields */
+#define STM32_RTC_VERR_MINREV_SHIFT 0
+#define STM32_RTC_VERR_MINREV GENMASK(3, 0)
+#define STM32_RTC_VERR_MAJREV_SHIFT 4
+#define STM32_RTC_VERR_MAJREV GENMASK(7, 4)
+
/* STM32_RTC_WPR key constants */
#define RTC_WPR_1ST_KEY 0xCA
#define RTC_WPR_2ND_KEY 0x53
#define RTC_WPR_WRONG_KEY 0xFF
+#define UNDEF_REG ~0
+
struct stm32_rtc;
struct stm32_rtc_registers {
@@ -86,6 +98,9 @@ struct stm32_rtc_registers {
u8 prer;
u8 alrmar;
u8 wpr;
+ u8 sr;
+ u8 scr;
+ u16 verr;
};
struct stm32_rtc_events {
@@ -98,6 +113,7 @@ struct stm32_rtc_data {
void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
bool has_pclk;
bool need_dbp;
+ bool has_wakeirq;
};
struct stm32_rtc {
@@ -110,6 +126,7 @@ struct stm32_rtc {
struct clk *rtc_ck;
const struct stm32_rtc_data *data;
int irq_alarm;
+ int wakeirq_alarm;
};
static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
@@ -193,7 +210,7 @@ static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
mutex_lock(&rtc->rtc_dev->ops_lock);
- status = readl_relaxed(rtc->base + regs.isr);
+ status = readl_relaxed(rtc->base + regs.sr);
cr = readl_relaxed(rtc->base + regs.cr);
if ((status & evts.alra) &&
@@ -325,7 +342,7 @@ static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
alrmar = readl_relaxed(rtc->base + regs.alrmar);
cr = readl_relaxed(rtc->base + regs.cr);
- status = readl_relaxed(rtc->base + regs.isr);
+ status = readl_relaxed(rtc->base + regs.sr);
if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
/*
@@ -533,6 +550,7 @@ static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
static const struct stm32_rtc_data stm32_rtc_data = {
.has_pclk = false,
.need_dbp = true,
+ .has_wakeirq = false,
.regs = {
.tr = 0x00,
.dr = 0x04,
@@ -541,6 +559,9 @@ static const struct stm32_rtc_data stm32_rtc_data = {
.prer = 0x10,
.alrmar = 0x1C,
.wpr = 0x24,
+ .sr = 0x0C, /* set to ISR offset to ease alarm management */
+ .scr = UNDEF_REG,
+ .verr = UNDEF_REG,
},
.events = {
.alra = STM32_RTC_ISR_ALRAF,
@@ -551,6 +572,7 @@ static const struct stm32_rtc_data stm32_rtc_data = {
static const struct stm32_rtc_data stm32h7_rtc_data = {
.has_pclk = true,
.need_dbp = true,
+ .has_wakeirq = false,
.regs = {
.tr = 0x00,
.dr = 0x04,
@@ -559,6 +581,9 @@ static const struct stm32_rtc_data stm32h7_rtc_data = {
.prer = 0x10,
.alrmar = 0x1C,
.wpr = 0x24,
+ .sr = 0x0C, /* set to ISR offset to ease alarm management */
+ .scr = UNDEF_REG,
+ .verr = UNDEF_REG,
},
.events = {
.alra = STM32_RTC_ISR_ALRAF,
@@ -566,9 +591,41 @@ static const struct stm32_rtc_data stm32h7_rtc_data = {
.clear_events = stm32_rtc_clear_events,
};
+static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
+ unsigned int flags)
+{
+ struct stm32_rtc_registers regs = rtc->data->regs;
+
+ /* Flags are cleared by writing 1 in RTC_SCR */
+ writel_relaxed(flags, rtc->base + regs.scr);
+}
+
+static const struct stm32_rtc_data stm32mp1_data = {
+ .has_pclk = true,
+ .need_dbp = false,
+ .has_wakeirq = true,
+ .regs = {
+ .tr = 0x00,
+ .dr = 0x04,
+ .cr = 0x18,
+ .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
+ .prer = 0x10,
+ .alrmar = 0x40,
+ .wpr = 0x24,
+ .sr = 0x50,
+ .scr = 0x5C,
+ .verr = 0x3F4,
+ },
+ .events = {
+ .alra = STM32_RTC_SR_ALRA,
+ },
+ .clear_events = stm32mp1_rtc_clear_events,
+};
+
static const struct of_device_id stm32_rtc_of_match[] = {
{ .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
{ .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
+ { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
{}
};
MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
@@ -727,12 +784,19 @@ static int stm32_rtc_probe(struct platform_device *pdev)
goto err;
}
- platform_set_drvdata(pdev, rtc);
-
ret = device_init_wakeup(&pdev->dev, true);
+ if (rtc->data->has_wakeirq) {
+ rtc->wakeirq_alarm = platform_get_irq(pdev, 1);
+ if (rtc->wakeirq_alarm <= 0)
+ ret = rtc->wakeirq_alarm;
+ else
+ ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
+ rtc->wakeirq_alarm);
+ }
if (ret)
- dev_warn(&pdev->dev,
- "alarm won't be able to wake up the system");
+ dev_warn(&pdev->dev, "alarm can't wake up the system: %d", ret);
+
+ platform_set_drvdata(pdev, rtc);
rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
&stm32_rtc_ops, THIS_MODULE);
@@ -760,6 +824,14 @@ static int stm32_rtc_probe(struct platform_device *pdev)
if (!(readl_relaxed(rtc->base + regs.isr) & STM32_RTC_ISR_INITS))
dev_warn(&pdev->dev, "Date/Time must be initialized\n");
+ if (regs.verr != UNDEF_REG) {
+ u32 ver = readl_relaxed(rtc->base + regs.verr);
+
+ dev_info(&pdev->dev, "registered rev:%d.%d\n",
+ (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF,
+ (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF);
+ }
+
return 0;
err:
if (rtc->data->has_pclk)
@@ -769,6 +841,7 @@ static int stm32_rtc_probe(struct platform_device *pdev)
if (rtc->data->need_dbp)
regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
+ dev_pm_clear_wake_irq(&pdev->dev);
device_init_wakeup(&pdev->dev, false);
return ret;
@@ -795,6 +868,7 @@ static int stm32_rtc_remove(struct platform_device *pdev)
if (rtc->data->need_dbp)
regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
+ dev_pm_clear_wake_irq(&pdev->dev);
device_init_wakeup(&pdev->dev, false);
return 0;
--
2.7.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox