* Applied "ASoC: cirrus: i2s: Stop enabling I2S2 and I2S3 FIFOs" to the asoc tree
From: Mark Brown @ 2018-05-11 2:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180428205142.31921-4-alexander.sverdlin@gmail.com>
The patch
ASoC: cirrus: i2s: Stop enabling I2S2 and I2S3 FIFOs
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From cc27062b3eee3beb2e3830641b23ba9a52a8a04a Mon Sep 17 00:00:00 2001
From: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Date: Sat, 28 Apr 2018 22:51:40 +0200
Subject: [PATCH] ASoC: cirrus: i2s: Stop enabling I2S2 and I2S3 FIFOs
The driver never supported more than 2 channels because of
ep93xx_i2s_dma_data[] supporting only 1 DMA channel in each
direction.
Stop enabling two unused I2S controller FIFOs, this will simplify
future interrupt support.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/cirrus/ep93xx-i2s.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/sound/soc/cirrus/ep93xx-i2s.c b/sound/soc/cirrus/ep93xx-i2s.c
index 0dc3852c4621..42cc6d22baac 100644
--- a/sound/soc/cirrus/ep93xx-i2s.c
+++ b/sound/soc/cirrus/ep93xx-i2s.c
@@ -98,7 +98,6 @@ static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
{
unsigned base_reg;
- int i;
if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
(ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
@@ -111,27 +110,24 @@ static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
}
- /* Enable fifos */
+ /* Enable fifo */
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
base_reg = EP93XX_I2S_TX0EN;
else
base_reg = EP93XX_I2S_RX0EN;
- for (i = 0; i < 3; i++)
- ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
+ ep93xx_i2s_write_reg(info, base_reg, 1);
}
static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
{
unsigned base_reg;
- int i;
- /* Disable fifos */
+ /* Disable fifo */
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
base_reg = EP93XX_I2S_TX0EN;
else
base_reg = EP93XX_I2S_RX0EN;
- for (i = 0; i < 3; i++)
- ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
+ ep93xx_i2s_write_reg(info, base_reg, 0);
if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
(ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
--
2.17.0
^ permalink raw reply related
* Applied "ARM: ep93xx: i2s: Add IRQ to platform device resources" to the asoc tree
From: Mark Brown @ 2018-05-11 2:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180428205142.31921-5-alexander.sverdlin@gmail.com>
The patch
ARM: ep93xx: i2s: Add IRQ to platform device resources
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 6ea8a84806ac91809e1759a200bf3c272b12aeb9 Mon Sep 17 00:00:00 2001
From: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Date: Sat, 28 Apr 2018 22:51:41 +0200
Subject: [PATCH] ARM: ep93xx: i2s: Add IRQ to platform device resources
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
According to "EP93xx User???s Guide" it's called I2SINTR and has number 60.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm/mach-ep93xx/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index e70feec6fad5..48d6a9e01dc8 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -635,6 +635,7 @@ EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
*************************************************************************/
static struct resource ep93xx_i2s_resource[] = {
DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
+ DEFINE_RES_IRQ(IRQ_EP93XX_SAI),
};
static struct platform_device ep93xx_i2s_device = {
--
2.17.0
^ permalink raw reply related
* Applied "ASoC: cirrus: i2s: IRQ-based stream watchdog" to the asoc tree
From: Mark Brown @ 2018-05-11 2:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180428205142.31921-6-alexander.sverdlin@gmail.com>
The patch
ASoC: cirrus: i2s: IRQ-based stream watchdog
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 98e1241c357b82e070294f486cef91a1263874fa Mon Sep 17 00:00:00 2001
From: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Date: Sat, 28 Apr 2018 22:51:42 +0200
Subject: [PATCH] ASoC: cirrus: i2s: IRQ-based stream watchdog
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
I2S controller on EP93xx seems to have undocumented HW issue. According to
"EP93xx User???s Guide", controller can handle underflow and either transmit
last sample or zeroes in such case until FIFO is filled again. In reality
undeflow conditions seem to confuse internal state machine from time to
time and the whole stream gets shifted by one byte (as captured by logic
analyser on the I2S outputs). One could only hear noise instead of original
stream and this continues until the FIFO is disabled and enabled again.
Work this around by watching underflow interrupt and resetting I2S TX
channel + fill FIFO with zero samples until DMA catches up again. This is
a nasty workaround, but it works. Hence, Kconfig option to disable it in
case of problems.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/cirrus/Kconfig | 17 +++++++++
sound/soc/cirrus/ep93xx-i2s.c | 68 +++++++++++++++++++++++++++++++++++
2 files changed, 85 insertions(+)
diff --git a/sound/soc/cirrus/Kconfig b/sound/soc/cirrus/Kconfig
index c7cd60f009e9..e09199124c36 100644
--- a/sound/soc/cirrus/Kconfig
+++ b/sound/soc/cirrus/Kconfig
@@ -9,6 +9,23 @@ config SND_EP93XX_SOC
config SND_EP93XX_SOC_I2S
tristate
+if SND_EP93XX_SOC_I2S
+
+config SND_EP93XX_SOC_I2S_WATCHDOG
+ bool "IRQ based underflow watchdog workaround"
+ default y
+ help
+ I2S controller on EP93xx seems to have undocumented HW issue.
+ Underflow of internal I2S controller FIFO could confuse the
+ state machine and the whole stream can be shifted by one byte
+ until I2S is disabled. This option enables IRQ based watchdog
+ which disables and re-enables I2S in case of underflow and
+ fills FIFO with zeroes.
+
+ If you are unsure how to answer this question, answer Y.
+
+endif # if SND_EP93XX_SOC_I2S
+
config SND_EP93XX_SOC_AC97
tristate
select AC97_BUS
diff --git a/sound/soc/cirrus/ep93xx-i2s.c b/sound/soc/cirrus/ep93xx-i2s.c
index 42cc6d22baac..0918c5da575a 100644
--- a/sound/soc/cirrus/ep93xx-i2s.c
+++ b/sound/soc/cirrus/ep93xx-i2s.c
@@ -35,8 +35,12 @@
#define EP93XX_I2S_TXCLKCFG 0x00
#define EP93XX_I2S_RXCLKCFG 0x04
+#define EP93XX_I2S_GLSTS 0x08
#define EP93XX_I2S_GLCTRL 0x0C
+#define EP93XX_I2S_I2STX0LFT 0x10
+#define EP93XX_I2S_I2STX0RT 0x14
+
#define EP93XX_I2S_TXLINCTRLDATA 0x28
#define EP93XX_I2S_TXCTRL 0x2C
#define EP93XX_I2S_TXWRDLEN 0x30
@@ -55,12 +59,22 @@
#define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */
+/*
+ * Transmit empty interrupt level select:
+ * 0 - Generate interrupt when FIFO is half empty
+ * 1 - Generate interrupt when FIFO is empty
+ */
+#define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0)
+#define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */
+
#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
#define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
#define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
#define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
+#define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12)
+
struct ep93xx_i2s_info {
struct clk *mclk;
struct clk *sclk;
@@ -116,12 +130,24 @@ static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
else
base_reg = EP93XX_I2S_RX0EN;
ep93xx_i2s_write_reg(info, base_reg, 1);
+
+ /* Enable TX IRQs (FIFO empty or underflow) */
+ if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
+ stream == SNDRV_PCM_STREAM_PLAYBACK)
+ ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL,
+ EP93XX_I2S_TXCTRL_TXEMPTY_LVL |
+ EP93XX_I2S_TXCTRL_TXUFIE);
}
static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
{
unsigned base_reg;
+ /* Disable IRQs */
+ if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
+ stream == SNDRV_PCM_STREAM_PLAYBACK)
+ ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0);
+
/* Disable fifo */
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
base_reg = EP93XX_I2S_TX0EN;
@@ -141,6 +167,37 @@ static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
}
}
+/*
+ * According to documentation I2S controller can handle underflow conditions
+ * just fine, but in reality the state machine is sometimes confused so that
+ * the whole stream is shifted by one byte. The watchdog below disables the TX
+ * FIFO, fills the buffer with zeroes and re-enables the FIFO. State machine
+ * is being reset and by filling the buffer we get some time before next
+ * underflow happens.
+ */
+static irqreturn_t ep93xx_i2s_interrupt(int irq, void *dev_id)
+{
+ struct ep93xx_i2s_info *info = dev_id;
+
+ /* Disable FIFO */
+ ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0);
+ /*
+ * Fill TX FIFO with zeroes, this way we can defer next IRQs as much as
+ * possible and get more time for DMA to catch up. Actually there are
+ * only 8 samples in this FIFO, so even on 8kHz maximum deferral here is
+ * 1ms.
+ */
+ while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) &
+ EP93XX_I2S_GLSTS_TX0_FIFO_FULL)) {
+ ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0);
+ ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0);
+ }
+ /* Re-enable FIFO */
+ ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1);
+
+ return IRQ_HANDLED;
+}
+
static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
@@ -390,6 +447,17 @@ static int ep93xx_i2s_probe(struct platform_device *pdev)
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
+ if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG)) {
+ int irq = platform_get_irq(pdev, 0);
+ if (irq <= 0)
+ return irq < 0 ? irq : -ENODEV;
+
+ err = devm_request_irq(&pdev->dev, irq, ep93xx_i2s_interrupt, 0,
+ pdev->name, info);
+ if (err)
+ return err;
+ }
+
info->mclk = clk_get(&pdev->dev, "mclk");
if (IS_ERR(info->mclk)) {
err = PTR_ERR(info->mclk);
--
2.17.0
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: allwinner: a64: Enable A64 timer workaround
From: Samuel Holland @ 2018-05-11 2:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511022751.9096-1-samuel@sholland.org>
As instability in the architectural timer has been observed on multiple
devices using this SoC, inluding the Pine64 and the Orange Pi Win,
enable the workaround in the SoC's device tree.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1b2ef28c42bd..5202b76e9684 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -152,6 +152,7 @@
timer {
compatible = "arm,armv8-timer";
+ allwinner,sun50i-a64-unstable-timer;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
--
2.16.1
^ permalink raw reply related
* [PATCH 1/2] arm64: arch_timer: Workaround for Allwinner A64 timer instability
From: Samuel Holland @ 2018-05-11 2:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511022751.9096-1-samuel@sholland.org>
The Allwinner A64 SoC is known [1] to have an unstable architectural
timer, which manifests itself most obviously in the time jumping forward
a multiple of 95 years [2][3]. This coincides with 2^56 cycles at a
timer frequency of 24 MHz, implying that the time went slightly backward
(and this was interpreted by the kernel as it jumping forward and
wrapping around past the epoch).
Further investigation revealed instability in the low bits of CNTVCT at
the point a high bit rolls over. This leads to power-of-two cycle
forward and backward jumps. (Testing shows that forward jumps are about
twice as likely as backward jumps.)
Without trapping reads to CNTVCT, a userspace program is able to read it
in a loop faster than it changes. A test program running on all 4 CPU
cores that reported jumps larger than 100 ms was run for 13.6 hours and
reported the following:
Count | Event
-------+---------------------------
9940 | jumped backward 699ms
268 | jumped backward 1398ms
1 | jumped backward 2097ms
16020 | jumped forward 175ms
6443 | jumped forward 699ms
2976 | jumped forward 1398ms
9 | jumped forward 356516ms
9 | jumped forward 357215ms
4 | jumped forward 714430ms
1 | jumped forward 3578440ms
This works out to a jump larger than 100 ms about every 5.5 seconds on
each CPU core.
The largest jump (almost an hour!) was the following sequence of reads:
0x0000007fffffffff ? 0x00000093feffffff ? 0x0000008000000000
Note that the middle bits don't necessarily all read as all zeroes or
all ones during the anomalous behavior; however the low 11 bits checked
by the function in this patch have never been observed with any other
value.
Also note that smaller jumps are much more common, with the smallest
backward jumps of 2048 cycles observed over 400 times per second on each
core. (Of course, this is partially due to lower bits rolling over more
frequently.) Any one of these could have caused the 95 year time skip.
Similar anomalies were observed while reading CNTPCT (after patching the
kernel to allow reads from userspace). However, the jumps are much less
frequent, and only small jumps were observed. The same program as before
(except now reading CNTPCT) observed after 72 hours:
Count | Event
-------+---------------------------
17 | jumped backward 699ms
52 | jumped forward 175ms
2831 | jumped forward 699ms
5 | jumped forward 1398ms
========================================================================
Because the CPU can read the CNTPCT/CNTVCT registers faster than they
change, performing two reads of the register and comparing the high bits
(like other workarounds) is not a workable solution. And because the
timer can jump both forward and backward, no pair of reads can
distinguish a good value from a bad one. The only way to guarantee a
good value from consecutive reads would be to read _three_ times, and
take the middle value iff the three values are 1) individually unique
and 2) increasing. This takes at minimum 3 cycles (125 ns), or more if
an anomaly is detected.
However, since there is a distinct pattern to the bad values, we can
optimize the common case (2046/2048 of the time) to a single read by
simply ignoring values that match the pattern. This still takes no more
than 3 cycles in the worst case, and requires much less code.
[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clocksource/Kconfig | 11 ++++++++++
drivers/clocksource/arm_arch_timer.c | 39 ++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8e8a09755d10..7a5d434dd30b 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -364,6 +364,17 @@ config ARM64_ERRATUM_858921
The workaround will be dynamically enabled when an affected
core is detected.
+config SUN50I_A64_UNSTABLE_TIMER
+ bool "Workaround for Allwinner A64 timer instability"
+ default y
+ depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
+ select ARM_ARCH_TIMER_OOL_WORKAROUND
+ help
+ This option enables a workaround for instability in the timer on
+ the Allwinner A64 SoC. The workaround will only be active if the
+ allwinner,sun50i-a64-unstable-timer property is found in the
+ timer node.
+
config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST
select TIMER_OF if OF
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 57cb2f00fc07..66ce13578c52 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -319,6 +319,36 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
}
#endif
+#ifdef CONFIG_SUN50I_A64_UNSTABLE_TIMER
+/*
+ * The low bits of each register can transiently read as all ones or all zeroes
+ * when bit 11 or greater rolls over. Since the value can jump both backward
+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), it is simplest to just
+ * ignore register values with all ones or zeros in the low bits.
+ */
+static u64 notrace sun50i_a64_read_cntpct_el0(void)
+{
+ u64 val;
+
+ do {
+ val = read_sysreg(cntpct_el0);
+ } while (((val + 1) & GENMASK(10, 0)) <= 1);
+
+ return val;
+}
+
+static u64 notrace sun50i_a64_read_cntvct_el0(void)
+{
+ u64 val;
+
+ do {
+ val = read_sysreg(cntvct_el0);
+ } while (((val + 1) & GENMASK(10, 0)) <= 1);
+
+ return val;
+}
+#endif
+
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
@@ -408,6 +438,15 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
.read_cntvct_el0 = arm64_858921_read_cntvct_el0,
},
#endif
+#ifdef CONFIG_SUN50I_A64_UNSTABLE_TIMER
+ {
+ .match_type = ate_match_dt,
+ .id = "allwinner,sun50i-a64-unstable-timer",
+ .desc = "Allwinner A64 timer instability",
+ .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
+ .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
+ },
+#endif
};
typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
--
2.16.1
^ permalink raw reply related
* [PATCH 0/2] Allwinner A64 timer workaround
From: Samuel Holland @ 2018-05-11 2:27 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
Several people (including me) have experienced extremely large system
clock jumps on their A64-based devices, apparently due to the
architectural timer going backward, which is interpreted by Linux as
the timer wrapping around after 2^56 cycles.
Investigation led to discovery of some obvious problems with this SoC's
architectural timer, and this patch series introduces what I believe is
the simplest workaround. More details are in the commit message for
patch 1. Patch 2 simply enables the workaround in the device tree.
Thanks,
Samuel
Samuel Holland (2):
arm64: arch_timer: Workaround for Allwinner A64 timer instability
arm64: dts: allwinner: a64: Enable A64 timer workaround
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
drivers/clocksource/Kconfig | 11 ++++++++
drivers/clocksource/arm_arch_timer.c | 39 +++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
--
2.16.1
^ permalink raw reply
* [PATCH v1 2/5] gpio: syscon: Add gpio-syscon for rockchip
From: Levin Du @ 2018-05-11 2:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c0f520d1-42e3-e8b5-128e-3ff3d532ec4c@arm.com>
On 2018-05-10 10:56 PM, Robin Murphy wrote:
>
>> diff --git
>> a/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
>> b/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
>> new file mode 100644
>> index 0000000..e4c1650
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
>> @@ -0,0 +1,41 @@
>> +* Rockchip GPIO support for GRF_SOC_CON registers
>> +
>> +Required properties:
>> +- compatible: Should contain "rockchip,gpio-syscon".
>> +- gpio-controller: Marks the device node as a gpio controller.
>> +- #gpio-cells: Should be two. The first cell is the pin number and
>
> I would suggest s/pin number/bit number in the associated GRF
> register/ here. At least in this RK3328 case there's only one pin,
> which isn't numbered, and if you naively considered it pin 0 of this
> 'bank' you'd already have the wrong number. Since we're dealing with
> the "random SoC-specific controls" region of the GRF as opposed to the
> relatively-consistent and organised pinmux parts, I don't think we
> should rely on any assumptions about how things are laid out.
>
> I was initially going to suggest a more specific compatible string as
> well, but on reflection I think the generic "rockchip,gpio-syscon" for
> basic "flip this single GRF bit" functionality actually is the right
> way to go. In the specific RK3328 GPIO_MUTE case, there look to be 4
> bits in total related to this pin - the enable, value, and some pull
> controls (which I assume apply when the output is disabled) - if at
> some point in future we *did* want to start explicitly controlling the
> rest of them too, then would be a good time to define a separate
> "rockchip,rk3328-gpio-mute" binding (and probably a dedicated driver)
> for that specialised functionality, independently of this basic one.
>
Good point! I'll fix the doc.
>> ? +static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int
>> offset,
>> +????????????????? int val)
>> +{
>> +??? struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
>> +??? unsigned int offs;
>> +??? u8 bit;
>> +??? u32 data;
>> +??? int ret;
>> +
>> +??? offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
>
> data->dat_bit_offset is always 0 here, but given that wrapping large
> offsets to successive GRF registers doesn't make sense (and wouldn't
> work anyway with this arithmetic) I don't think you even need this
> calculation of offs at all...
>
>> +??? bit = offs % SYSCON_REG_BITS;
>
> ... since it would suffice to use offset here...
>
>> +??? data = (val ? BIT(bit) : 0) | BIT(bit + 16);
>> +??? ret = regmap_write(priv->syscon,
>> +?????????????? (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
>
> ... and priv->dreg_offset here.
>
rockchip_gpio_set() follows the conventional offset handling in the
gpio-syscon driver.
dreg_offset will get multiplied by 8 (dreg_offset <<= 3) in
syscon_gpio_probe().
I'm not sure if this needs to simplify, or stay the same as others.
Thanks
Levin
^ permalink raw reply
* [PATCH 3/3] arm64: dts: hi3798cv200: enable emmc support for poplar board
From: Shawn Guo @ 2018-05-11 2:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526004220-17030-1-git-send-email-shawn.guo@linaro.org>
It adds pinctrl device pinconf at 8a21000, gpio-ranges for GPIO devices,
and then enables eMMC support for Hi3798CV200 Poplar board.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
.../boot/dts/hisilicon/hi3798cv200-poplar.dts | 15 ++++
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 74 +++++++++++++++-
arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi | 98 ++++++++++++++++++++++
3 files changed, 184 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
index b0b790a5aa8d..d30f6eb8a5ee 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/gpio/gpio.h>
#include "hi3798cv200.dtsi"
+#include "poplar-pinctrl.dtsi"
/ {
model = "HiSilicon Poplar Development Board";
@@ -76,6 +77,20 @@
status = "okay";
};
+&emmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
+ &emmc_pins_3 &emmc_pins_4>;
+ fifo-depth = <256>;
+ clock-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ bus-width = <8>;
+ status = "okay";
+};
+
&gmac1 {
status = "okay";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index c1723ef01cac..7c0fddd7c8cf 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -175,6 +175,46 @@
};
};
+ pmx0: pinconf at 8a21000 {
+ compatible = "pinconf-single";
+ reg = <0x8a21000 0x180>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+ pinctrl-single,gpio-range = <
+ &range 0 8 2 /* GPIO 0 */
+ &range 8 1 0 /* GPIO 1 */
+ &range 9 4 2
+ &range 13 1 0
+ &range 14 1 1
+ &range 15 1 0
+ &range 16 5 0 /* GPIO 2 */
+ &range 21 3 1
+ &range 24 4 1 /* GPIO 3 */
+ &range 28 2 2
+ &range 86 1 1
+ &range 87 1 0
+ &range 30 4 2 /* GPIO 4 */
+ &range 34 3 0
+ &range 37 1 2
+ &range 38 3 2 /* GPIO 6 */
+ &range 41 5 0
+ &range 46 8 1 /* GPIO 7 */
+ &range 54 8 1 /* GPIO 8 */
+ &range 64 7 1 /* GPIO 9 */
+ &range 71 1 0
+ &range 72 6 1 /* GPIO 10 */
+ &range 78 1 0
+ &range 79 1 1
+ &range 80 6 1 /* GPIO 11 */
+ &range 70 2 1
+ &range 88 8 0 /* GPIO 12 */
+ >;
+
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+
uart0: serial at 8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
@@ -274,12 +314,17 @@
};
emmc: mmc at 9830000 {
- compatible = "snps,dw-mshc";
+ compatible = "hisilicon,hi3798cv200-dw-mshc";
reg = <0x9830000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_MMC_CIU_CLK>,
- <&crg HISTB_MMC_BIU_CLK>;
- clock-names = "ciu", "biu";
+ <&crg HISTB_MMC_BIU_CLK>,
+ <&crg HISTB_MMC_SAMPLE_CLK>,
+ <&crg HISTB_MMC_DRV_CLK>;
+ clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
+ resets = <&crg 0xa0 4>;
+ reset-names = "reset";
+ status = "disabled";
};
gpio0: gpio at 8b20000 {
@@ -290,6 +335,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 0 8>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -303,6 +349,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <
+ &pmx0 0 8 1
+ &pmx0 1 9 4
+ &pmx0 5 13 1
+ &pmx0 6 14 1
+ &pmx0 7 15 1
+ >;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -316,6 +369,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -329,6 +383,12 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <
+ &pmx0 0 24 4
+ &pmx0 4 28 2
+ &pmx0 6 86 1
+ &pmx0 7 87 1
+ >;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -342,6 +402,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -368,6 +429,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -381,6 +443,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 46 8>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -394,6 +457,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 54 8>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -407,6 +471,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -420,6 +485,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -433,6 +499,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
@@ -446,6 +513,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&pmx0 0 88 8>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
diff --git a/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi
new file mode 100644
index 000000000000..7bb19e4b084a
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl dts file for HiSilicon Poplar board
+ *
+ * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/hisi.h>
+
+/* value, enable bits, disable bits, mask */
+#define PINCTRL_PULLDOWN(value, enable, disable, mask) \
+ (value << 13) (enable << 13) (disable << 13) (mask << 13)
+#define PINCTRL_PULLUP(value, enable, disable, mask) \
+ (value << 12) (enable << 12) (disable << 12) (mask << 12)
+#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8)
+#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4)
+
+&pmx0 {
+ emmc_pins_1: emmc-pins-1 {
+ pinctrl-single,pins = <
+ 0x000 MUX_M2
+ 0x004 MUX_M2
+ 0x008 MUX_M2
+ 0x00c MUX_M2
+ 0x010 MUX_M2
+ 0x014 MUX_M2
+ 0x018 MUX_M2
+ 0x01c MUX_M2
+ 0x024 MUX_M2
+ >;
+ pinctrl-single,bias-pulldown = <
+ PINCTRL_PULLDOWN(0, 1, 0, 1)
+ >;
+ pinctrl-single,bias-pullup = <
+ PINCTRL_PULLUP(0, 1, 0, 1)
+ >;
+ pinctrl-single,slew-rate = <
+ PINCTRL_SLEW_RATE(1, 1)
+ >;
+ pinctrl-single,drive-strength = <
+ PINCTRL_DRV_STRENGTH(0xb, 0xf)
+ >;
+ };
+
+ emmc_pins_2: emmc-pins-2 {
+ pinctrl-single,pins = <
+ 0x028 MUX_M2
+ >;
+ pinctrl-single,bias-pulldown = <
+ PINCTRL_PULLDOWN(0, 1, 0, 1)
+ >;
+ pinctrl-single,bias-pullup = <
+ PINCTRL_PULLUP(0, 1, 0, 1)
+ >;
+ pinctrl-single,slew-rate = <
+ PINCTRL_SLEW_RATE(1, 1)
+ >;
+ pinctrl-single,drive-strength = <
+ PINCTRL_DRV_STRENGTH(0x9, 0xf)
+ >;
+ };
+
+ emmc_pins_3: emmc-pins-3 {
+ pinctrl-single,pins = <
+ 0x02c MUX_M2
+ >;
+ pinctrl-single,bias-pulldown = <
+ PINCTRL_PULLDOWN(0, 1, 0, 1)
+ >;
+ pinctrl-single,bias-pullup = <
+ PINCTRL_PULLUP(0, 1, 0, 1)
+ >;
+ pinctrl-single,slew-rate = <
+ PINCTRL_SLEW_RATE(1, 1)
+ >;
+ pinctrl-single,drive-strength = <
+ PINCTRL_DRV_STRENGTH(3, 3)
+ >;
+ };
+
+ emmc_pins_4: emmc-pins-4 {
+ pinctrl-single,pins = <
+ 0x030 MUX_M2
+ >;
+ pinctrl-single,bias-pulldown = <
+ PINCTRL_PULLDOWN(1, 1, 0, 1)
+ >;
+ pinctrl-single,bias-pullup = <
+ PINCTRL_PULLUP(0, 1, 0, 1)
+ >;
+ pinctrl-single,slew-rate = <
+ PINCTRL_SLEW_RATE(1, 1)
+ >;
+ pinctrl-single,drive-strength = <
+ PINCTRL_DRV_STRENGTH(3, 3)
+ >;
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: hi3798cv200: enable usb2 support for poplar board
From: Shawn Guo @ 2018-05-11 2:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526004220-17030-1-git-send-email-shawn.guo@linaro.org>
It adds usb2 phy devices, and enables ehci/ohci support for Hi3798CV200
Poplar board.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
.../boot/dts/hisilicon/hi3798cv200-poplar.dts | 8 +++
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 68 ++++++++++++++++++++++
2 files changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
index c4382e1f3c92..b0b790a5aa8d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
@@ -72,6 +72,10 @@
};
};
+&ehci {
+ status = "okay";
+};
+
&gmac1 {
status = "okay";
#address-cells = <1>;
@@ -155,6 +159,10 @@
status = "okay";
};
+&ohci {
+ status = "okay";
+};
+
&pcie {
reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
vpcie-supply = <®_pcie>;
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 5b73403551e6..c1723ef01cac 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -116,6 +116,42 @@
#size-cells = <1>;
ranges = <0x0 0x8a20000 0x1000>;
+ usb2_phy1: usb2-phy at 120 {
+ compatible = "hisilicon,hi3798cv200-usb2-phy";
+ reg = <0x120 0x4>;
+ clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+ resets = <&crg 0xbc 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_phy1_port0: phy at 0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ resets = <&crg 0xbc 8>;
+ };
+
+ usb2_phy1_port1: phy at 1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ resets = <&crg 0xbc 9>;
+ };
+ };
+
+ usb2_phy2: usb2-phy at 124 {
+ compatible = "hisilicon,hi3798cv200-usb2-phy";
+ reg = <0x124 0x4>;
+ clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
+ resets = <&crg 0xbc 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_phy2_port0: phy at 0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ resets = <&crg 0xbc 10>;
+ };
+ };
+
combphy0: phy at 850 {
compatible = "hisilicon,hi3798cv200-combphy";
reg = <0x850 0x8>;
@@ -482,5 +518,37 @@
phy-names = "phy";
status = "disabled";
};
+
+ ohci: ohci at 9880000 {
+ compatible = "generic-ohci";
+ reg = <0x9880000 0x10000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_USB2_BUS_CLK>,
+ <&crg HISTB_USB2_12M_CLK>,
+ <&crg HISTB_USB2_48M_CLK>;
+ clock-names = "bus", "clk12", "clk48";
+ resets = <&crg 0xb8 12>;
+ reset-names = "bus";
+ phys = <&usb2_phy1_port0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci: ehci at 9890000 {
+ compatible = "generic-ehci";
+ reg = <0x9890000 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_USB2_BUS_CLK>,
+ <&crg HISTB_USB2_PHY_CLK>,
+ <&crg HISTB_USB2_UTMI_CLK>;
+ clock-names = "bus", "phy", "utmi";
+ resets = <&crg 0xb8 12>,
+ <&crg 0xb8 16>,
+ <&crg 0xb8 13>;
+ reset-names = "bus", "phy", "utmi";
+ phys = <&usb2_phy1_port0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH 1/3] arm64: dts: hi3798cv200: enable PCIe support for poplar board
From: Shawn Guo @ 2018-05-11 2:03 UTC (permalink / raw)
To: linux-arm-kernel
It adds combophy devices under peripheral controller and enables PCIe
support for Hi3798CV200 Poplar board.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
.../boot/dts/hisilicon/hi3798cv200-poplar.dts | 15 ++++++
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 63 ++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
index 4d5d644abb12..c4382e1f3c92 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
@@ -61,6 +61,15 @@
default-state = "off";
};
};
+
+ reg_pcie: regulator-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3_PCIE0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio6 7 0>;
+ enable-active-high;
+ };
};
&gmac1 {
@@ -146,6 +155,12 @@
status = "okay";
};
+&pcie {
+ reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+ vpcie-supply = <®_pcie>;
+ status = "okay";
+};
+
&sd0 {
bus-width = <4>;
cap-sd-highspeed;
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 962bd79139e4..5b73403551e6 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -8,7 +8,9 @@
*/
#include <dt-bindings/clock/histb-clock.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
@@ -106,6 +108,37 @@
#reset-cells = <2>;
};
+ perictrl: peripheral-controller at 8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+ "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8a20000 0x1000>;
+
+ combphy0: phy at 850 {
+ compatible = "hisilicon,hi3798cv200-combphy";
+ reg = <0x850 0x8>;
+ #phy-cells = <1>;
+ clocks = <&crg HISTB_COMBPHY0_CLK>;
+ resets = <&crg 0x188 4>;
+ assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
+ assigned-clock-rates = <100000000>;
+ hisilicon,fixed-mode = <PHY_TYPE_USB3>;
+ };
+
+ combphy1: phy at 858 {
+ compatible = "hisilicon,hi3798cv200-combphy";
+ reg = <0x858 0x8>;
+ #phy-cells = <1>;
+ clocks = <&crg HISTB_COMBPHY1_CLK>;
+ resets = <&crg 0x188 12>;
+ assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
+ assigned-clock-rates = <100000000>;
+ hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
+ };
+ };
+
uart0: serial at 8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
@@ -419,5 +452,35 @@
clocks = <&sysctrl HISTB_IR_CLK>;
status = "disabled";
};
+
+ pcie: pcie at 9860000 {
+ compatible = "hisilicon,hi3798cv200-pcie";
+ reg = <0x9860000 0x1000>,
+ <0x0 0x2000>,
+ <0x2000000 0x01000000>;
+ reg-names = "control", "rc-dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0 15>;
+ num-lanes = <1>;
+ ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
+ 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_PCIE_AUX_CLK>,
+ <&crg HISTB_PCIE_PIPE_CLK>,
+ <&crg HISTB_PCIE_SYS_CLK>,
+ <&crg HISTB_PCIE_BUS_CLK>;
+ clock-names = "aux", "pipe", "sys", "bus";
+ resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
+ reset-names = "soft", "sys", "bus";
+ phys = <&combphy1 PHY_TYPE_PCIE>;
+ phy-names = "phy";
+ status = "disabled";
+ };
};
};
--
1.9.1
^ permalink raw reply related
* [arm:to-build 2/13] WARNING: vmlinux.o(.text+0x18ff0): Section mismatch in reference from the function check_bugs() to the function .init.text:check_writebuffer_bugs()
From: kbuild test robot @ 2018-05-11 1:11 UTC (permalink / raw)
To: linux-arm-kernel
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git to-build
head: 7eac243a530d849d5e2502ff3015dd68d1b27de3
commit: cc591a392bd5a56d60f3955c9c8bd15e14477ffa [2/13] ARM: bugs: prepare processor bug infrastructure
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout cc591a392bd5a56d60f3955c9c8bd15e14477ffa
# save the attached .config to linux build tree
make.cross ARCH=arm
All warnings (new ones prefixed by >>):
>> WARNING: vmlinux.o(.text+0x18ff0): Section mismatch in reference from the function check_bugs() to the function .init.text:check_writebuffer_bugs()
The function check_bugs() references
the function __init check_writebuffer_bugs().
This is often because check_bugs lacks a __init
annotation or the annotation of check_writebuffer_bugs is wrong.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
-------------- next part --------------
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^ permalink raw reply
* [PATCH 2/3] ARM: dts: imx28: Remove unit-address from pinctrl
From: Stefan Wahren @ 2018-05-11 0:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525997810-10964-2-git-send-email-festevam@gmail.com>
Hi Fabio,
> Fabio Estevam <festevam@gmail.com> hat am 11. Mai 2018 um 02:16 geschrieben:
>
>
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> Remove unit-address and reg property from pinctrl subnodes to fix
> the following DTC warnings with W=1:
>
> arch/arm/boot/dts/imx28-apf28dev.dtb: Warning (unique_unit_address): /apb at 80000000/apbh at 80000000/pinctrl at 80018000/hog at 0: duplicate unit-address (also used in node /apb at 80000000/apbh at 80000000
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
> ---
> arch/arm/boot/dts/imx28-apf28dev.dts | 9 +-
> arch/arm/boot/dts/imx28-apx4devkit.dts | 12 +-
> arch/arm/boot/dts/imx28-cfa10036.dts | 12 +-
> arch/arm/boot/dts/imx28-cfa10037.dts | 6 +-
> arch/arm/boot/dts/imx28-cfa10049.dts | 36 ++---
> arch/arm/boot/dts/imx28-cfa10055.dts | 12 +-
> arch/arm/boot/dts/imx28-cfa10056.dts | 9 +-
> arch/arm/boot/dts/imx28-cfa10057.dts | 9 +-
> arch/arm/boot/dts/imx28-cfa10058.dts | 6 +-
> arch/arm/boot/dts/imx28-duckbill-2-485.dts | 12 +-
> arch/arm/boot/dts/imx28-duckbill-2-enocean.dts | 15 +-
> arch/arm/boot/dts/imx28-duckbill-2-spi.dts | 15 +-
> arch/arm/boot/dts/imx28-duckbill-2.dts | 12 +-
> arch/arm/boot/dts/imx28-duckbill.dts | 9 +-
> arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts | 3 +-
> arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts | 3 +-
> arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi | 24 ++--
> arch/arm/boot/dts/imx28-evk.dts | 12 +-
> arch/arm/boot/dts/imx28-m28cu3.dts | 9 +-
> arch/arm/boot/dts/imx28-m28evk.dts | 6 +-
> arch/arm/boot/dts/imx28-sps1.dts | 3 +-
> arch/arm/boot/dts/imx28-ts4600.dts | 3 +-
> arch/arm/boot/dts/imx28-tx28.dts | 33 ++---
> arch/arm/boot/dts/imx28.dtsi | 191 ++++++++-----------------
> 24 files changed, 153 insertions(+), 308 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
> index c4fadbc..53ed2e2 100644
> ...
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 9ad8d35..8f46b1f 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -169,14 +169,11 @@
> };
>
> pinctrl: pinctrl at 80018000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> compatible = "fsl,imx28-pinctrl", "simple-bus";
> reg = <0x80018000 0x2000>;
>
> - gpio0: gpio at 0 {
> + gpio0: gpio0 {
> compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
> - reg = <0>;
> interrupts = <127>;
> gpio-controller;
> #gpio-cells = <2>;
> @@ -184,9 +181,8 @@
> #interrupt-cells = <2>;
> };
i'm not sure, but it looked to me like a proper way to address the gpio banks before.
Regards
Stefan
>
> - gpio1: gpio at 1 {
> + gpio1: gpio1 {
> compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
> - reg = <1>;
> interrupts = <126>;
> gpio-controller;
> #gpio-cells = <2>;
> @@ -194,9 +190,8 @@
> #interrupt-cells = <2>;
> };
>
^ permalink raw reply
* [PATCH 2/3] ARM: dts: imx28: Remove unit-address from pinctrl
From: Fabio Estevam @ 2018-05-11 0:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525997810-10964-2-git-send-email-festevam@gmail.com>
Hi Shawn,
On Thu, May 10, 2018 at 9:16 PM, Fabio Estevam <festevam@gmail.com> wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> Remove unit-address and reg property from pinctrl subnodes to fix
> the following DTC warnings with W=1:
>
> arch/arm/boot/dts/imx28-apf28dev.dtb: Warning (unique_unit_address): /apb at 80000000/apbh at 80000000/pinctrl at 80018000/hog at 0: duplicate unit-address (also used in node /apb at 80000000/apbh at 80000000
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Please discard this one and 3/3 for now.
I noticed that audio is no longer functional after this change. I will debug it.
^ permalink raw reply
* [PATCH 3/3] ARM: dts: imx23: Remove unit-address from pinctrl
From: Fabio Estevam @ 2018-05-11 0:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525997810-10964-1-git-send-email-festevam@gmail.com>
From: Fabio Estevam <fabio.estevam@nxp.com>
Remove unit-address and reg property from pinctrl subnodes to fix
the following DTC warnings with W=1:
arch/arm/boot/dts/imx23-olinuxino.dtb: Warning (unique_unit_address): /apb at 80000000/apbh at 80000000/pinctrl at 80018000/hog at 0: duplicate unit-address (also used in node /apb at 80000000/apbh at 80000000
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx23-evk.dts | 3 +-
arch/arm/boot/dts/imx23-olinuxino.dts | 6 +--
arch/arm/boot/dts/imx23-sansa.dts | 3 +-
arch/arm/boot/dts/imx23-stmp378x_devb.dts | 3 +-
arch/arm/boot/dts/imx23-xfi3.dts | 6 +--
arch/arm/boot/dts/imx23.dtsi | 62 ++++++++++---------------------
6 files changed, 27 insertions(+), 56 deletions(-)
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 9d92ece82..278a446 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -42,8 +42,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX23_PAD_LCD_RESET__GPIO_1_18
MX23_PAD_PWM3__GPIO_1_29
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index e935177..bc154b3 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -38,8 +38,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX23_PAD_GPMI_ALE__GPIO_0_17
>;
@@ -48,8 +47,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_pin_gpio2_1: led_gpio2_1 at 0 {
- reg = <0>;
+ led_pin_gpio2_1: led_gpio2_1 {
fsl,pinmux-ids = <
MX23_PAD_SSP1_DETECT__GPIO_2_1
>;
diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts
index 67de786..62514e4 100644
--- a/arch/arm/boot/dts/imx23-sansa.dts
+++ b/arch/arm/boot/dts/imx23-sansa.dts
@@ -79,8 +79,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX23_PAD_GPMI_D08__GPIO_0_8
MX23_PAD_PWM3__GPIO_1_29
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 95c7b91..dd61bfa 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -36,8 +36,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX23_PAD_PWM3__GPIO_1_29
MX23_PAD_PWM4__GPIO_1_30
diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts
index 9616e50..0c38b7e 100644
--- a/arch/arm/boot/dts/imx23-xfi3.dts
+++ b/arch/arm/boot/dts/imx23-xfi3.dts
@@ -77,8 +77,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX23_PAD_GPMI_D07__GPIO_0_7
>;
@@ -87,8 +86,7 @@
fsl,pull-up = <0>;
};
- key_pins_a: keys at 0 {
- reg = <0>;
+ key_pins_a: keys {
fsl,pinmux-ids = <
MX23_PAD_ROTARYA__GPIO_2_7
MX23_PAD_ROTARYB__GPIO_2_8
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index cb0a3fe..8d2019f 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -115,14 +115,11 @@
};
pinctrl@80018000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "fsl,imx23-pinctrl", "simple-bus";
reg = <0x80018000 0x2000>;
- gpio0: gpio at 0 {
+ gpio0: gpio0 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
- reg = <0>;
interrupts = <16>;
gpio-controller;
#gpio-cells = <2>;
@@ -130,9 +127,8 @@
#interrupt-cells = <2>;
};
- gpio1: gpio at 1 {
+ gpio1: gpio1 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
- reg = <1>;
interrupts = <17>;
gpio-controller;
#gpio-cells = <2>;
@@ -140,9 +136,8 @@
#interrupt-cells = <2>;
};
- gpio2: gpio at 2 {
+ gpio2: gpio2 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
- reg = <2>;
interrupts = <18>;
gpio-controller;
#gpio-cells = <2>;
@@ -150,8 +145,7 @@
#interrupt-cells = <2>;
};
- duart_pins_a: duart at 0 {
- reg = <0>;
+ duart_pins_a: duart {
fsl,pinmux-ids = <
MX23_PAD_PWM0__DUART_RX
MX23_PAD_PWM1__DUART_TX
@@ -161,8 +155,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart0_pins_a: auart0 at 0 {
- reg = <0>;
+ auart0_pins_a: auart0 {
fsl,pinmux-ids = <
MX23_PAD_AUART1_RX__AUART1_RX
MX23_PAD_AUART1_TX__AUART1_TX
@@ -174,8 +167,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart0_2pins_a: auart0-2pins at 0 {
- reg = <0>;
+ auart0_2pins_a: auart0-2pins {
fsl,pinmux-ids = <
MX23_PAD_I2C_SCL__AUART1_TX
MX23_PAD_I2C_SDA__AUART1_RX
@@ -185,8 +177,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart1_2pins_a: auart1-2pins at 0 {
- reg = <0>;
+ auart1_2pins_a: auart1-2pins {
fsl,pinmux-ids = <
MX23_PAD_GPMI_D14__AUART2_RX
MX23_PAD_GPMI_D15__AUART2_TX
@@ -196,8 +187,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- gpmi_pins_a: gpmi-nand at 0 {
- reg = <0>;
+ gpmi_pins_a: gpmi-nand {
fsl,pinmux-ids = <
MX23_PAD_GPMI_D00__GPMI_D00
MX23_PAD_GPMI_D01__GPMI_D01
@@ -222,8 +212,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- gpmi_pins_fixup: gpmi-pins-fixup at 0 {
- reg = <0>;
+ gpmi_pins_fixup: gpmi-pins-fixup {
fsl,pinmux-ids = <
MX23_PAD_GPMI_WPN__GPMI_WPN
MX23_PAD_GPMI_WRN__GPMI_WRN
@@ -232,8 +221,7 @@
fsl,drive-strength = <MXS_DRIVE_12mA>;
};
- mmc0_4bit_pins_a: mmc0-4bit at 0 {
- reg = <0>;
+ mmc0_4bit_pins_a: mmc0-4bit {
fsl,pinmux-ids = <
MX23_PAD_SSP1_DATA0__SSP1_DATA0
MX23_PAD_SSP1_DATA1__SSP1_DATA1
@@ -247,8 +235,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc0_8bit_pins_a: mmc0-8bit at 0 {
- reg = <0>;
+ mmc0_8bit_pins_a: mmc0-8bit {
fsl,pinmux-ids = <
MX23_PAD_SSP1_DATA0__SSP1_DATA0
MX23_PAD_SSP1_DATA1__SSP1_DATA1
@@ -267,8 +254,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc0_pins_fixup: mmc0-pins-fixup at 0 {
- reg = <0>;
+ mmc0_pins_fixup: mmc0-pins-fixup {
fsl,pinmux-ids = <
MX23_PAD_SSP1_DETECT__SSP1_DETECT
MX23_PAD_SSP1_SCK__SSP1_SCK
@@ -276,8 +262,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc1_4bit_pins_a: mmc1-4bit at 0 {
- reg = <0>;
+ mmc1_4bit_pins_a: mmc1-4bit {
fsl,pinmux-ids = <
MX23_PAD_GPMI_D00__SSP2_DATA0
MX23_PAD_GPMI_D01__SSP2_DATA1
@@ -291,8 +276,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc1_8bit_pins_a: mmc1-8bit at 0 {
- reg = <0>;
+ mmc1_8bit_pins_a: mmc1-8bit {
fsl,pinmux-ids = <
MX23_PAD_GPMI_D00__SSP2_DATA0
MX23_PAD_GPMI_D01__SSP2_DATA1
@@ -310,8 +294,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- pwm2_pins_a: pwm2 at 0 {
- reg = <0>;
+ pwm2_pins_a: pwm2 {
fsl,pinmux-ids = <
MX23_PAD_PWM2__PWM2
>;
@@ -320,8 +303,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_24bit_pins_a: lcdif-24bit at 0 {
- reg = <0>;
+ lcdif_24bit_pins_a: lcdif-24bit {
fsl,pinmux-ids = <
MX23_PAD_LCD_D00__LCD_D00
MX23_PAD_LCD_D01__LCD_D01
@@ -357,8 +339,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- spi2_pins_a: spi2 at 0 {
- reg = <0>;
+ spi2_pins_a: spi2 {
fsl,pinmux-ids = <
MX23_PAD_GPMI_WRN__SSP2_SCK
MX23_PAD_GPMI_RDY1__SSP2_CMD
@@ -370,8 +351,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- i2c_pins_a: i2c at 0 {
- reg = <0>;
+ i2c_pins_a: i2c {
fsl,pinmux-ids = <
MX23_PAD_I2C_SCL__I2C_SCL
MX23_PAD_I2C_SDA__I2C_SDA
@@ -381,8 +361,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- i2c_pins_b: i2c at 1 {
- reg = <1>;
+ i2c_pins_b: i2cb {
fsl,pinmux-ids = <
MX23_PAD_LCD_ENABLE__I2C_SCL
MX23_PAD_LCD_HSYNC__I2C_SDA
@@ -392,8 +371,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- i2c_pins_c: i2c at 2 {
- reg = <2>;
+ i2c_pins_c: i2cc {
fsl,pinmux-ids = <
MX23_PAD_SSP1_DATA1__I2C_SCL
MX23_PAD_SSP1_DATA2__I2C_SDA
--
2.7.4
^ permalink raw reply related
* [PATCH 2/3] ARM: dts: imx28: Remove unit-address from pinctrl
From: Fabio Estevam @ 2018-05-11 0:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525997810-10964-1-git-send-email-festevam@gmail.com>
From: Fabio Estevam <fabio.estevam@nxp.com>
Remove unit-address and reg property from pinctrl subnodes to fix
the following DTC warnings with W=1:
arch/arm/boot/dts/imx28-apf28dev.dtb: Warning (unique_unit_address): /apb at 80000000/apbh at 80000000/pinctrl at 80018000/hog at 0: duplicate unit-address (also used in node /apb at 80000000/apbh at 80000000
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx28-apf28dev.dts | 9 +-
arch/arm/boot/dts/imx28-apx4devkit.dts | 12 +-
arch/arm/boot/dts/imx28-cfa10036.dts | 12 +-
arch/arm/boot/dts/imx28-cfa10037.dts | 6 +-
arch/arm/boot/dts/imx28-cfa10049.dts | 36 ++---
arch/arm/boot/dts/imx28-cfa10055.dts | 12 +-
arch/arm/boot/dts/imx28-cfa10056.dts | 9 +-
arch/arm/boot/dts/imx28-cfa10057.dts | 9 +-
arch/arm/boot/dts/imx28-cfa10058.dts | 6 +-
arch/arm/boot/dts/imx28-duckbill-2-485.dts | 12 +-
arch/arm/boot/dts/imx28-duckbill-2-enocean.dts | 15 +-
arch/arm/boot/dts/imx28-duckbill-2-spi.dts | 15 +-
arch/arm/boot/dts/imx28-duckbill-2.dts | 12 +-
arch/arm/boot/dts/imx28-duckbill.dts | 9 +-
arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts | 3 +-
arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts | 3 +-
arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi | 24 ++--
arch/arm/boot/dts/imx28-evk.dts | 12 +-
arch/arm/boot/dts/imx28-m28cu3.dts | 9 +-
arch/arm/boot/dts/imx28-m28evk.dts | 6 +-
arch/arm/boot/dts/imx28-sps1.dts | 3 +-
arch/arm/boot/dts/imx28-ts4600.dts | 3 +-
arch/arm/boot/dts/imx28-tx28.dts | 33 ++---
arch/arm/boot/dts/imx28.dtsi | 191 ++++++++-----------------
24 files changed, 153 insertions(+), 308 deletions(-)
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index c4fadbc..53ed2e2 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -38,8 +38,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_apf28dev>;
- hog_pins_apf28dev: hog at 0 {
- reg = <0>;
+ hog_pins_apf28dev: hog {
fsl,pinmux-ids = <
MX28_PAD_LCD_D16__GPIO_1_16
MX28_PAD_LCD_D17__GPIO_1_17
@@ -55,8 +54,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_apf28dev: lcdif-apf28dev at 0 {
- reg = <0>;
+ lcdif_pins_apf28dev: lcdif-apf28dev {
fsl,pinmux-ids = <
MX28_PAD_LCD_RD_E__LCD_VSYNC
MX28_PAD_LCD_WR_RWN__LCD_HSYNC
@@ -68,8 +66,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- usb0_otg_apf28dev: otg-apf28dev at 0 {
- reg = <0>;
+ usb0_otg_apf28dev: otg-apf28dev {
fsl,pinmux-ids = <
MX28_PAD_LCD_D23__GPIO_1_23
>;
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index 96faa53..e8447af 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -38,8 +38,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_GPMI_CE1N__GPIO_0_17
MX28_PAD_GPMI_RDY1__GPIO_0_21
@@ -54,8 +53,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_apx4: lcdif-apx4 at 0 {
- reg = <0>;
+ lcdif_pins_apx4: lcdif-apx4 {
fsl,pinmux-ids = <
MX28_PAD_LCD_RD_E__LCD_VSYNC
MX28_PAD_LCD_WR_RWN__LCD_HSYNC
@@ -67,8 +65,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc2_4bit_pins_apx4: mmc2-4bit-apx4 at 0 {
- reg = <0>;
+ mmc2_4bit_pins_apx4: mmc2-4bit-apx4 {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA4__SSP2_D0
MX28_PAD_SSP0_DATA5__SSP2_D3
@@ -82,8 +79,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 at 0 {
- reg = <0>;
+ mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA7__SSP2_SCK
>;
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index e54f5ab..cc0205b 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -23,8 +23,7 @@
apb at 80000000 {
apbh at 80000000 {
pinctrl at 80018000 {
- ssd1306_cfa10036: ssd1306-10036 at 0 {
- reg = <0>;
+ ssd1306_cfa10036: ssd1306-10036 {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA7__GPIO_2_7
>;
@@ -33,8 +32,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_pins_cfa10036: leds-10036 at 0 {
- reg = <0>;
+ led_pins_cfa10036: leds-10036 {
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__GPIO_3_4
>;
@@ -43,8 +41,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- usb0_otg_cfa10036: otg-10036 at 0 {
- reg = <0>;
+ usb0_otg_cfa10036: otg-10036 {
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY0__USB0_ID
>;
@@ -53,8 +50,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc_pwr_cfa10036: mmc_pwr_cfa10036 at 0 {
- reg = <0>;
+ mmc_pwr_cfa10036: mmc_pwr_cfa10036 {
fsl,pinmux-ids = <
0x31c3 /*
MX28_PAD_PWM3__GPIO_3_28 */
diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts
index 3d13b32..e373aee 100644
--- a/arch/arm/boot/dts/imx28-cfa10037.dts
+++ b/arch/arm/boot/dts/imx28-cfa10037.dts
@@ -22,8 +22,7 @@
apb at 80000000 {
apbh at 80000000 {
pinctrl at 80018000 {
- usb_pins_cfa10037: usb-10037@0 {
- reg = <0>;
+ usb_pins_cfa10037: usb-10037 {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D07__GPIO_0_7
>;
@@ -32,8 +31,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_pins_cfa10037: mac0-10037 at 0 {
- reg = <0>;
+ mac0_pins_cfa10037: mac0-10037 {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SS2__GPIO_2_21
>;
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 60e5c7f..fbc4cb4 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -87,8 +87,7 @@
apb at 80000000 {
apbh at 80000000 {
pinctrl at 80018000 {
- usb_pins_cfa10049: usb-10049 at 0 {
- reg = <0>;
+ usb_pins_cfa10049: usb-10049 {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D07__GPIO_0_7
>;
@@ -97,8 +96,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- i2cmux_pins_cfa10049: i2cmux-10049 at 0 {
- reg = <0>;
+ i2cmux_pins_cfa10049: i2cmux-10049 {
fsl,pinmux-ids = <
MX28_PAD_LCD_D22__GPIO_1_22
MX28_PAD_LCD_D23__GPIO_1_23
@@ -108,8 +106,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_pins_cfa10049: mac0-10049 at 0 {
- reg = <0>;
+ mac0_pins_cfa10049: mac0-10049 {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SS2__GPIO_2_21
>;
@@ -118,8 +115,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- pca_pins_cfa10049: pca-10049 at 0 {
- reg = <0>;
+ pca_pins_cfa10049: pca-10049 {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SS0__GPIO_2_19
>;
@@ -128,8 +124,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- rotary_pins_cfa10049: rotary-10049 at 0 {
- reg = <0>;
+ rotary_pins_cfa10049: rotary-10049 {
fsl,pinmux-ids = <
MX28_PAD_I2C0_SCL__GPIO_3_24
MX28_PAD_I2C0_SDA__GPIO_3_25
@@ -139,8 +134,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- rotary_btn_pins_cfa10049: rotary-btn-10049 at 0 {
- reg = <0>;
+ rotary_btn_pins_cfa10049: rotary-btn-10049 {
fsl,pinmux-ids = <
MX28_PAD_SAIF1_SDATA0__GPIO_3_26
>;
@@ -149,8 +143,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- spi2_pins_cfa10049: spi2-cfa10049 at 0 {
- reg = <0>;
+ spi2_pins_cfa10049: spi2-cfa10049 {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__GPIO_2_16
MX28_PAD_SSP2_MOSI__GPIO_2_17
@@ -162,8 +155,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- spi3_pins_cfa10049: spi3-cfa10049 at 0 {
- reg = <0>;
+ spi3_pins_cfa10049: spi3-cfa10049 {
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDN__GPIO_0_24
MX28_PAD_GPMI_RESETN__GPIO_0_28
@@ -176,8 +168,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- lcdif_18bit_pins_cfa10049: lcdif-18bit at 0 {
- reg = <0>;
+ lcdif_18bit_pins_cfa10049: lcdif-18bit {
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
@@ -203,8 +194,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_cfa10049: lcdif-evk at 0 {
- reg = <0>;
+ lcdif_pins_cfa10049: lcdif-evk {
fsl,pinmux-ids = <
MX28_PAD_LCD_RD_E__LCD_VSYNC
MX28_PAD_LCD_WR_RWN__LCD_HSYNC
@@ -216,8 +206,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_cfa10049_pullup: lcdif-10049-pullup at 0 {
- reg = <0>;
+ lcdif_pins_cfa10049_pullup: lcdif-10049-pullup {
fsl,pinmux-ids = <
MX28_PAD_LCD_RESET__GPIO_3_30
>;
@@ -226,8 +215,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- w1_gpio_pins: w1-gpio at 0 {
- reg = <0>;
+ w1_gpio_pins: w1-gpio {
fsl,pinmux-ids = <
MX28_PAD_LCD_D21__GPIO_1_21
>;
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
index 6a34114..1edcc49 100644
--- a/arch/arm/boot/dts/imx28-cfa10055.dts
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -23,8 +23,7 @@
apb at 80000000 {
apbh at 80000000 {
pinctrl at 80018000 {
- spi2_pins_cfa10055: spi2-cfa10055 at 0 {
- reg = <0>;
+ spi2_pins_cfa10055: spi2-cfa10055 {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__GPIO_2_16
MX28_PAD_SSP2_MOSI__GPIO_2_17
@@ -36,8 +35,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- lcdif_18bit_pins_cfa10055: lcdif-18bit at 0 {
- reg = <0>;
+ lcdif_18bit_pins_cfa10055: lcdif-18bit {
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
@@ -63,8 +61,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_cfa10055: lcdif-evk at 0 {
- reg = <0>;
+ lcdif_pins_cfa10055: lcdif-evk {
fsl,pinmux-ids = <
MX28_PAD_LCD_RD_E__LCD_VSYNC
MX28_PAD_LCD_WR_RWN__LCD_HSYNC
@@ -76,8 +73,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_cfa10055_pullup: lcdif-10055-pullup at 0 {
- reg = <0>;
+ lcdif_pins_cfa10055_pullup: lcdif-10055-pullup {
fsl,pinmux-ids = <
MX28_PAD_LCD_RESET__GPIO_3_30
>;
diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts
index ba6495c..5ac3a12 100644
--- a/arch/arm/boot/dts/imx28-cfa10056.dts
+++ b/arch/arm/boot/dts/imx28-cfa10056.dts
@@ -22,8 +22,7 @@
apb at 80000000 {
apbh at 80000000 {
pinctrl at 80018000 {
- spi2_pins_cfa10056: spi2-cfa10056 at 0 {
- reg = <0>;
+ spi2_pins_cfa10056: spi2-cfa10056 {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__GPIO_2_16
MX28_PAD_SSP2_MOSI__GPIO_2_17
@@ -35,8 +34,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- lcdif_pins_cfa10056: lcdif-10056 at 0 {
- reg = <0>;
+ lcdif_pins_cfa10056: lcdif-10056 {
fsl,pinmux-ids = <
MX28_PAD_LCD_RD_E__LCD_VSYNC
MX28_PAD_LCD_WR_RWN__LCD_HSYNC
@@ -48,8 +46,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_cfa10056_pullup: lcdif-10056-pullup at 0 {
- reg = <0>;
+ lcdif_pins_cfa10056_pullup: lcdif-10056-pullup {
fsl,pinmux-ids = <
MX28_PAD_LCD_RESET__GPIO_3_30
>;
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
index c606791..de48936 100644
--- a/arch/arm/boot/dts/imx28-cfa10057.dts
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -23,8 +23,7 @@
apb at 80000000 {
apbh at 80000000 {
pinctrl at 80018000 {
- usb_pins_cfa10057: usb-10057 at 0 {
- reg = <0>;
+ usb_pins_cfa10057: usb-10057 {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D07__GPIO_0_7
>;
@@ -33,8 +32,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_18bit_pins_cfa10057: lcdif-18bit at 0 {
- reg = <0>;
+ lcdif_18bit_pins_cfa10057: lcdif-18bit {
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
@@ -60,8 +58,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_cfa10057: lcdif-evk at 0 {
- reg = <0>;
+ lcdif_pins_cfa10057: lcdif-evk {
fsl,pinmux-ids = <
MX28_PAD_LCD_RD_E__LCD_VSYNC
MX28_PAD_LCD_WR_RWN__LCD_HSYNC
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts
index 70c7bb4..26c3a0e 100644
--- a/arch/arm/boot/dts/imx28-cfa10058.dts
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -23,8 +23,7 @@
apb at 80000000 {
apbh at 80000000 {
pinctrl at 80018000 {
- usb_pins_cfa10058: usb-10058@0 {
- reg = <0>;
+ usb_pins_cfa10058: usb-10058 {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D07__GPIO_0_7
>;
@@ -33,8 +32,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_cfa10058: lcdif-10058 at 0 {
- reg = <0>;
+ lcdif_pins_cfa10058: lcdif-10058 {
fsl,pinmux-ids = <
MX28_PAD_LCD_RD_E__LCD_VSYNC
MX28_PAD_LCD_WR_RWN__LCD_HSYNC
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
index 97084e4..0fd07fe 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
@@ -50,8 +50,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
>;
@@ -60,8 +59,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_phy_reset_pin: mac0-phy-reset at 0 {
- reg = <0>;
+ mac0_phy_reset_pin: mac0-phy-reset {
fsl,pinmux-ids = <
MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
>;
@@ -70,8 +68,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_phy_int_pin: mac0-phy-int at 0 {
- reg = <0>;
+ mac0_phy_int_pin: mac0-phy-int {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
>;
@@ -80,8 +77,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_pins: leds at 0 {
- reg = <0>;
+ led_pins: leds {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20
MX28_PAD_SAIF0_LRCLK__GPIO_3_21
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
index 7f8d40a..c241546 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
@@ -51,8 +51,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
>;
@@ -61,8 +60,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_phy_reset_pin: mac0-phy-reset at 0 {
- reg = <0>;
+ mac0_phy_reset_pin: mac0-phy-reset {
fsl,pinmux-ids = <
MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
>;
@@ -71,8 +69,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_phy_int_pin: mac0-phy-int at 0 {
- reg = <0>;
+ mac0_phy_int_pin: mac0-phy-int {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
>;
@@ -81,8 +78,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_pins: leds at 0 {
- reg = <0>;
+ led_pins: leds {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20
MX28_PAD_SAIF0_LRCLK__GPIO_3_21
@@ -95,8 +91,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- enocean_button: enocean-button at 0 {
- reg = <0>;
+ enocean_button: enocean-button {
fsl,pinmux-ids = <
MX28_PAD_AUART0_RTS__GPIO_3_3
>;
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
index 13e7b13..e5c92f3 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
@@ -63,8 +63,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
>;
@@ -73,8 +72,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_phy_reset_pin: mac0-phy-reset at 0 {
- reg = <0>;
+ mac0_phy_reset_pin: mac0-phy-reset {
fsl,pinmux-ids = <
MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
>;
@@ -83,8 +81,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_phy_int_pin: mac0-phy-int at 0 {
- reg = <0>;
+ mac0_phy_int_pin: mac0-phy-int {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
>;
@@ -93,8 +90,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_pins: led at 0 {
- reg = <0>;
+ led_pins: led {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20
MX28_PAD_SAIF0_LRCLK__GPIO_3_21
@@ -104,8 +100,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- qca7000_pins: qca7000 at 0 {
- reg = <0>;
+ qca7000_pins: qca7000 {
fsl,pinmux-ids = <
MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */
MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */
diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts
index 88556c9..0a9128b 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2.dts
@@ -50,8 +50,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
>;
@@ -60,8 +59,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_phy_reset_pin: mac0-phy-reset at 0 {
- reg = <0>;
+ mac0_phy_reset_pin: mac0-phy-reset {
fsl,pinmux-ids = <
MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
>;
@@ -70,8 +68,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_phy_int_pin: mac0-phy-int at 0 {
- reg = <0>;
+ mac0_phy_int_pin: mac0-phy-int {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
>;
@@ -80,8 +77,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_pins: leds at 0 {
- reg = <0>;
+ led_pins: leds {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20
MX28_PAD_SAIF0_LRCLK__GPIO_3_21
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index f286bfe..6113bdc 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -45,8 +45,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
>;
@@ -55,8 +54,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_phy_reset_pin: mac0-phy-reset at 0 {
- reg = <0>;
+ mac0_phy_reset_pin: mac0-phy-reset {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */
>;
@@ -65,8 +63,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_pins: leds at 0 {
- reg = <0>;
+ led_pins: leds {
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__GPIO_3_4
MX28_PAD_AUART1_TX__GPIO_3_5
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
index b70f334..8773575 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
@@ -58,8 +58,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_cpuimx283>;
- hog_pins_cpuimx283: hog-cpuimx283 at 0 {
- reg = <0>;
+ hog_pins_cpuimx283: hog-cpuimx283 {
fsl,pinmux-ids = <
MX28_PAD_ENET0_RX_CLK__GPIO_4_13
MX28_PAD_ENET0_TX_CLK__GPIO_4_5
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
index 65efb78..cfd92c3 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
@@ -38,8 +38,7 @@
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>;
- hog_pins_cpuimx287: hog-cpuimx287 at 0 {
- reg = <0>;
+ hog_pins_cpuimx287: hog-cpuimx287 {
fsl,pinmux-ids = <
MX28_PAD_SPDIF__GPIO_3_27
>;
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
index ff1328c..11f3426 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
@@ -197,8 +197,7 @@
};
&pinctrl {
- gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc at 0 {
- reg = <0>;
+ gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc {
fsl,pinmux-ids = <
MX28_PAD_LCD_D21__GPIO_1_21
>;
@@ -207,8 +206,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc at 0 {
- reg = <0>;
+ gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc {
fsl,pinmux-ids = <
MX28_PAD_LCD_D20__GPIO_1_20
>;
@@ -217,8 +215,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_mbmx28lc: lcdif-mbmx28lc at 0 {
- reg = <0>;
+ lcdif_pins_mbmx28lc: lcdif-mbmx28lc {
fsl,pinmux-ids = <
MX28_PAD_LCD_VSYNC__LCD_VSYNC
MX28_PAD_LCD_HSYNC__LCD_HSYNC
@@ -230,8 +227,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_d6_pins_mbmx28lc: led-d6-mbmx28lc at 0 {
- reg = <0>;
+ led_d6_pins_mbmx28lc: led-d6-mbmx28lc {
fsl,pinmux-ids = <
MX28_PAD_LCD_D23__GPIO_1_23
>;
@@ -240,8 +236,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_d7_pins_mbmx28lc: led-d7-mbmx28lc at 0 {
- reg = <0>;
+ led_d7_pins_mbmx28lc: led-d7-mbmx28lc {
fsl,pinmux-ids = <
MX28_PAD_LCD_D22__GPIO_1_22
>;
@@ -250,8 +245,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc at 0 {
- reg = <0>;
+ reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc {
fsl,pinmux-ids = <
MX28_PAD_LCD_RESET__GPIO_3_30
>;
@@ -260,8 +254,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc at 0 {
- reg = <0>;
+ reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc {
fsl,pinmux-ids = <
MX28_PAD_LCD_D18__GPIO_1_18
>;
@@ -270,8 +263,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc at 0 {
- reg = <0>;
+ reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc {
fsl,pinmux-ids = <
MX28_PAD_LCD_D19__GPIO_1_19
>;
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index b0d3965..7f849de 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -67,8 +67,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_SSP1_CMD__GPIO_2_13
MX28_PAD_SSP1_DATA3__GPIO_2_15
@@ -84,8 +83,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_pin_gpio3_5: led_gpio3_5 at 0 {
- reg = <0>;
+ led_pin_gpio3_5: led_gpio3_5 {
fsl,pinmux-ids = <
MX28_PAD_AUART1_TX__GPIO_3_5
>;
@@ -94,8 +92,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- gpmi_pins_evk: gpmi-nand-evk at 0 {
- reg = <0>;
+ gpmi_pins_evk: gpmi-nand-evk {
fsl,pinmux-ids = <
MX28_PAD_GPMI_CE1N__GPMI_CE1N
MX28_PAD_GPMI_RDY1__GPMI_READY1
@@ -105,8 +102,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_evk: lcdif-evk at 0 {
- reg = <0>;
+ lcdif_pins_evk: lcdif-evk {
fsl,pinmux-ids = <
MX28_PAD_LCD_RD_E__LCD_VSYNC
MX28_PAD_LCD_WR_RWN__LCD_HSYNC
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 3bb5ffc..8af939c 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -67,8 +67,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SS0__GPIO_2_19
MX28_PAD_PWM4__GPIO_3_29
@@ -80,8 +79,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_m28: lcdif-m28 at 0 {
- reg = <0>;
+ lcdif_pins_m28: lcdif-m28 {
fsl,pinmux-ids = <
MX28_PAD_LCD_VSYNC__LCD_VSYNC
MX28_PAD_LCD_HSYNC__LCD_HSYNC
@@ -95,8 +93,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- led_pins_gpio: leds-m28 at 0 {
- reg = <0>;
+ led_pins_gpio: leds-m28 {
fsl,pinmux-ids = <
MX28_PAD_SSP3_MISO__GPIO_2_26
MX28_PAD_SSP3_SCK__GPIO_2_24
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 7d97a0c..639e1b3 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -51,8 +51,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_PWM3__GPIO_3_28
MX28_PAD_AUART2_CTS__GPIO_3_10
@@ -65,8 +64,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_pins_m28: lcdif-m28 at 0 {
- reg = <0>;
+ lcdif_pins_m28: lcdif-m28 {
fsl,pinmux-ids = <
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
MX28_PAD_LCD_ENABLE__LCD_ENABLE
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 2393e839..13d2bba 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -26,8 +26,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog-gpios at 0 {
- reg = <0>;
+ hog_pins_a: hog-gpios {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D00__GPIO_0_0
MX28_PAD_GPMI_D03__GPIO_0_3
diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts
index f8a09a8..758e70d 100644
--- a/arch/arm/boot/dts/imx28-ts4600.dts
+++ b/arch/arm/boot/dts/imx28-ts4600.dts
@@ -39,8 +39,7 @@
pinctrl at 80018000 {
- en_sd_pwr: en-sd-pwr@0 {
- reg = <0>;
+ en_sd_pwr: en-sd-pwr {
fsl,pinmux-ids = <
MX28_PAD_PWM3__GPIO_3_28
>;
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index e4f19f9b..32794e9 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -516,8 +516,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
- hog_pins_a: hog at 0 {
- reg = <0>;
+ hog_pins_a: hog {
fsl,pinmux-ids = <
MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */
>;
@@ -526,8 +525,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins at 0 {
- reg = <0>;
+ tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */
MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */
@@ -538,8 +536,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins at 0 {
- reg = <0>;
+ tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins {
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__GPIO_1_0
>;
@@ -548,8 +545,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_lcdif_23bit_pins: tx28-lcdif-23bit at 0 {
- reg = <0>;
+ tx28_lcdif_23bit_pins: tx28-lcdif-23bit {
fsl,pinmux-ids = <
/* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */
MX28_PAD_LCD_D01__LCD_D1
@@ -581,8 +577,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl at 0 {
- reg = <0>;
+ tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl {
fsl,pinmux-ids = <
MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */
MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */
@@ -592,8 +587,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_mac0_pins_gpio: tx28-mac0-gpio-pins at 0 {
- reg = <0>;
+ tx28_mac0_pins_gpio: tx28-mac0-gpio-pins {
fsl,pinmux-ids = <
MX28_PAD_ENET0_MDC__GPIO_4_0
MX28_PAD_ENET0_MDIO__GPIO_4_1
@@ -610,8 +604,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_pca9554_pins: tx28-pca9554-pins at 0 {
- reg = <0>;
+ tx28_pca9554_pins: tx28-pca9554-pins {
fsl,pinmux-ids = <
MX28_PAD_PWM3__GPIO_3_28
>;
@@ -620,8 +613,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_spi_gpio_pins: spi-gpiogrp at 0 {
- reg = <0>;
+ tx28_spi_gpio_pins: spi-gpiogrp {
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__GPIO_3_8
MX28_PAD_AUART2_TX__GPIO_3_9
@@ -635,8 +627,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_tsc2007_pins: tx28-tsc2007-pins at 0 {
- reg = <0>;
+ tx28_tsc2007_pins: tx28-tsc2007-pins {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
>;
@@ -646,8 +637,7 @@
};
- tx28_usbphy0_pins: tx28-usbphy0-pins at 0 {
- reg = <0>;
+ tx28_usbphy0_pins: tx28-usbphy0-pins {
fsl,pinmux-ids = <
MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */
MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */
@@ -657,8 +647,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- tx28_usbphy1_pins: tx28-usbphy1-pins at 0 {
- reg = <0>;
+ tx28_usbphy1_pins: tx28-usbphy1-pins {
fsl,pinmux-ids = <
MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */
MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 9ad8d35..8f46b1f 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -169,14 +169,11 @@
};
pinctrl: pinctrl@80018000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "fsl,imx28-pinctrl", "simple-bus";
reg = <0x80018000 0x2000>;
- gpio0: gpio at 0 {
+ gpio0: gpio0 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
- reg = <0>;
interrupts = <127>;
gpio-controller;
#gpio-cells = <2>;
@@ -184,9 +181,8 @@
#interrupt-cells = <2>;
};
- gpio1: gpio at 1 {
+ gpio1: gpio1 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
- reg = <1>;
interrupts = <126>;
gpio-controller;
#gpio-cells = <2>;
@@ -194,9 +190,8 @@
#interrupt-cells = <2>;
};
- gpio2: gpio at 2 {
+ gpio2: gpio2 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
- reg = <2>;
interrupts = <125>;
gpio-controller;
#gpio-cells = <2>;
@@ -204,9 +199,8 @@
#interrupt-cells = <2>;
};
- gpio3: gpio at 3 {
+ gpio3: gpio3 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
- reg = <3>;
interrupts = <124>;
gpio-controller;
#gpio-cells = <2>;
@@ -214,9 +208,8 @@
#interrupt-cells = <2>;
};
- gpio4: gpio at 4 {
+ gpio4: gpio4 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
- reg = <4>;
interrupts = <123>;
gpio-controller;
#gpio-cells = <2>;
@@ -224,8 +217,7 @@
#interrupt-cells = <2>;
};
- duart_pins_a: duart at 0 {
- reg = <0>;
+ duart_pins_a: duart0 {
fsl,pinmux-ids = <
MX28_PAD_PWM0__DUART_RX
MX28_PAD_PWM1__DUART_TX
@@ -235,8 +227,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- duart_pins_b: duart at 1 {
- reg = <1>;
+ duart_pins_b: duart1 {
fsl,pinmux-ids = <
MX28_PAD_AUART0_CTS__DUART_RX
MX28_PAD_AUART0_RTS__DUART_TX
@@ -246,8 +237,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- duart_4pins_a: duart-4pins at 0 {
- reg = <0>;
+ duart_4pins_a: duart-4pins {
fsl,pinmux-ids = <
MX28_PAD_AUART0_CTS__DUART_RX
MX28_PAD_AUART0_RTS__DUART_TX
@@ -259,8 +249,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- gpmi_pins_a: gpmi-nand at 0 {
- reg = <0>;
+ gpmi_pins_a: gpmi-nand {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D00__GPMI_D0
MX28_PAD_GPMI_D01__GPMI_D1
@@ -283,8 +272,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- gpmi_status_cfg: gpmi-status-cfg at 0 {
- reg = <0>;
+ gpmi_status_cfg: gpmi-status-cfg {
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDN__GPMI_RDN
MX28_PAD_GPMI_WRN__GPMI_WRN
@@ -293,8 +281,7 @@
fsl,drive-strength = <MXS_DRIVE_12mA>;
};
- auart0_pins_a: auart0 at 0 {
- reg = <0>;
+ auart0_pins_a: auart0 {
fsl,pinmux-ids = <
MX28_PAD_AUART0_RX__AUART0_RX
MX28_PAD_AUART0_TX__AUART0_TX
@@ -306,8 +293,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart0_2pins_a: auart0-2pins at 0 {
- reg = <0>;
+ auart0_2pins_a: auart0-2pins {
fsl,pinmux-ids = <
MX28_PAD_AUART0_RX__AUART0_RX
MX28_PAD_AUART0_TX__AUART0_TX
@@ -317,8 +303,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart1_pins_a: auart1 at 0 {
- reg = <0>;
+ auart1_pins_a: auart1 {
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__AUART1_RX
MX28_PAD_AUART1_TX__AUART1_TX
@@ -330,8 +315,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart1_2pins_a: auart1-2pins at 0 {
- reg = <0>;
+ auart1_2pins_a: auart1-2pins {
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__AUART1_RX
MX28_PAD_AUART1_TX__AUART1_TX
@@ -341,8 +325,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart2_2pins_a: auart2-2pins at 0 {
- reg = <0>;
+ auart2_2pins_a: auart2-2pins {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__AUART2_RX
MX28_PAD_SSP2_MOSI__AUART2_TX
@@ -352,8 +335,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart2_2pins_b: auart2-2pins at 1 {
- reg = <1>;
+ auart2_2pins_b: auart2-2pinsb {
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__AUART2_RX
MX28_PAD_AUART2_TX__AUART2_TX
@@ -363,8 +345,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart2_pins_a: auart2-pins at 0 {
- reg = <0>;
+ auart2_pins_a: auart2-pins {
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__AUART2_RX
MX28_PAD_AUART2_TX__AUART2_TX
@@ -376,8 +357,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart3_pins_a: auart3 at 0 {
- reg = <0>;
+ auart3_pins_a: auart3 {
fsl,pinmux-ids = <
MX28_PAD_AUART3_RX__AUART3_RX
MX28_PAD_AUART3_TX__AUART3_TX
@@ -389,8 +369,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart3_2pins_a: auart3-2pins at 0 {
- reg = <0>;
+ auart3_2pins_a: auart3-2pins {
fsl,pinmux-ids = <
MX28_PAD_SSP2_MISO__AUART3_RX
MX28_PAD_SSP2_SS0__AUART3_TX
@@ -400,8 +379,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart3_2pins_b: auart3-2pins at 1 {
- reg = <1>;
+ auart3_2pins_b: auart3-2pinsb {
fsl,pinmux-ids = <
MX28_PAD_AUART3_RX__AUART3_RX
MX28_PAD_AUART3_TX__AUART3_TX
@@ -411,8 +389,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart4_2pins_a: auart4 at 0 {
- reg = <0>;
+ auart4_2pins_a: auart4 {
fsl,pinmux-ids = <
MX28_PAD_SSP3_SCK__AUART4_TX
MX28_PAD_SSP3_MOSI__AUART4_RX
@@ -422,8 +399,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- auart4_2pins_b: auart4 at 1 {
- reg = <1>;
+ auart4_2pins_b: auart4b {
fsl,pinmux-ids = <
MX28_PAD_AUART0_CTS__AUART4_RX
MX28_PAD_AUART0_RTS__AUART4_TX
@@ -433,8 +409,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mac0_pins_a: mac0 at 0 {
- reg = <0>;
+ mac0_pins_a: mac0 {
fsl,pinmux-ids = <
MX28_PAD_ENET0_MDC__ENET0_MDC
MX28_PAD_ENET0_MDIO__ENET0_MDIO
@@ -451,8 +426,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mac0_pins_b: mac0 at 1 {
- reg = <1>;
+ mac0_pins_b: mac0b {
fsl,pinmux-ids = <
MX28_PAD_ENET0_MDC__ENET0_MDC
MX28_PAD_ENET0_MDIO__ENET0_MDIO
@@ -477,8 +451,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mac1_pins_a: mac1 at 0 {
- reg = <0>;
+ mac1_pins_a: mac1 {
fsl,pinmux-ids = <
MX28_PAD_ENET0_CRS__ENET1_RX_EN
MX28_PAD_ENET0_RXD2__ENET1_RXD0
@@ -492,8 +465,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc0_8bit_pins_a: mmc0-8bit at 0 {
- reg = <0>;
+ mmc0_8bit_pins_a: mmc0-8bit {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA0__SSP0_D0
MX28_PAD_SSP0_DATA1__SSP0_D1
@@ -512,8 +484,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc0_4bit_pins_a: mmc0-4bit at 0 {
- reg = <0>;
+ mmc0_4bit_pins_a: mmc0-4bit {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA0__SSP0_D0
MX28_PAD_SSP0_DATA1__SSP0_D1
@@ -528,16 +499,14 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc0_cd_cfg: mmc0-cd-cfg at 0 {
- reg = <0>;
+ mmc0_cd_cfg: mmc0-cd-cfg {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc0_sck_cfg: mmc0-sck-cfg at 0 {
- reg = <0>;
+ mmc0_sck_cfg: mmc0-sck-cfg {
fsl,pinmux-ids = <
MX28_PAD_SSP0_SCK__SSP0_SCK
>;
@@ -545,8 +514,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc1_4bit_pins_a: mmc1-4bit at 0 {
- reg = <0>;
+ mmc1_4bit_pins_a: mmc1-4bit {
fsl,pinmux-ids = <
MX28_PAD_GPMI_D00__SSP1_D0
MX28_PAD_GPMI_D01__SSP1_D1
@@ -561,16 +529,14 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc1_cd_cfg: mmc1-cd-cfg at 0 {
- reg = <0>;
+ mmc1_cd_cfg: mmc1-cd-cfg {
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc1_sck_cfg: mmc1-sck-cfg at 0 {
- reg = <0>;
+ mmc1_sck_cfg: mmc1-sck-cfg {
fsl,pinmux-ids = <
MX28_PAD_GPMI_WRN__SSP1_SCK
>;
@@ -579,8 +545,7 @@
};
- mmc2_4bit_pins_a: mmc2-4bit at 0 {
- reg = <0>;
+ mmc2_4bit_pins_a: mmc2-4bit {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA4__SSP2_D0
MX28_PAD_SSP1_SCK__SSP2_D1
@@ -595,8 +560,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc2_4bit_pins_b: mmc2-4bit at 1 {
- reg = <1>;
+ mmc2_4bit_pins_b: mmc2-4bitb {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__SSP2_SCK
MX28_PAD_SSP2_MOSI__SSP2_CMD
@@ -611,16 +575,14 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- mmc2_cd_cfg: mmc2-cd-cfg at 0 {
- reg = <0>;
+ mmc2_cd_cfg: mmc2-cd-cfg {
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc2_sck_cfg_a: mmc2-sck-cfg at 0 {
- reg = <0>;
+ mmc2_sck_cfg_a: mmc2-sck-cfg {
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA7__SSP2_SCK
>;
@@ -628,8 +590,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- mmc2_sck_cfg_b: mmc2-sck-cfg at 1 {
- reg = <1>;
+ mmc2_sck_cfg_b: mmc2-sck-cfgb {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__SSP2_SCK
>;
@@ -637,8 +598,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- i2c0_pins_a: i2c0 at 0 {
- reg = <0>;
+ i2c0_pins_a: i2c0 {
fsl,pinmux-ids = <
MX28_PAD_I2C0_SCL__I2C0_SCL
MX28_PAD_I2C0_SDA__I2C0_SDA
@@ -648,8 +608,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- i2c0_pins_b: i2c0 at 1 {
- reg = <1>;
+ i2c0_pins_b: i2c0b {
fsl,pinmux-ids = <
MX28_PAD_AUART0_RX__I2C0_SCL
MX28_PAD_AUART0_TX__I2C0_SDA
@@ -659,8 +618,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- i2c1_pins_a: i2c1 at 0 {
- reg = <0>;
+ i2c1_pins_a: i2c1 {
fsl,pinmux-ids = <
MX28_PAD_PWM0__I2C1_SCL
MX28_PAD_PWM1__I2C1_SDA
@@ -670,8 +628,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- i2c1_pins_b: i2c1 at 1 {
- reg = <1>;
+ i2c1_pins_b: i2c1n {
fsl,pinmux-ids = <
MX28_PAD_AUART2_CTS__I2C1_SCL
MX28_PAD_AUART2_RTS__I2C1_SDA
@@ -681,8 +638,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- saif0_pins_a: saif0 at 0 {
- reg = <0>;
+ saif0_pins_a: saif0 {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
@@ -694,8 +650,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- saif0_pins_b: saif0 at 1 {
- reg = <1>;
+ saif0_pins_b: saif0b {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
@@ -706,8 +661,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- saif1_pins_a: saif1 at 0 {
- reg = <0>;
+ saif1_pins_a: saif1 {
fsl,pinmux-ids = <
MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
>;
@@ -716,8 +670,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- pwm0_pins_a: pwm0 at 0 {
- reg = <0>;
+ pwm0_pins_a: pwm0 {
fsl,pinmux-ids = <
MX28_PAD_PWM0__PWM_0
>;
@@ -726,8 +679,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- pwm2_pins_a: pwm2 at 0 {
- reg = <0>;
+ pwm2_pins_a: pwm2 {
fsl,pinmux-ids = <
MX28_PAD_PWM2__PWM_2
>;
@@ -736,8 +688,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- pwm3_pins_a: pwm3 at 0 {
- reg = <0>;
+ pwm3_pins_a: pwm3 {
fsl,pinmux-ids = <
MX28_PAD_PWM3__PWM_3
>;
@@ -746,8 +697,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- pwm3_pins_b: pwm3 at 1 {
- reg = <1>;
+ pwm3_pins_b: pwm3b {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__PWM_3
>;
@@ -756,8 +706,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- pwm4_pins_a: pwm4 at 0 {
- reg = <0>;
+ pwm4_pins_a: pwm4 {
fsl,pinmux-ids = <
MX28_PAD_PWM4__PWM_4
>;
@@ -766,8 +715,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_24bit_pins_a: lcdif-24bit at 0 {
- reg = <0>;
+ lcdif_24bit_pins_a: lcdif-24bit {
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
@@ -799,8 +747,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_18bit_pins_a: lcdif-18bit at 0 {
- reg = <0>;
+ lcdif_18bit_pins_a: lcdif-18bit {
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
@@ -826,8 +773,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_16bit_pins_a: lcdif-16bit at 0 {
- reg = <0>;
+ lcdif_16bit_pins_a: lcdif-16bit {
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
@@ -851,8 +797,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- lcdif_sync_pins_a: lcdif-sync at 0 {
- reg = <0>;
+ lcdif_sync_pins_a: lcdif-sync {
fsl,pinmux-ids = <
MX28_PAD_LCD_RS__LCD_DOTCLK
MX28_PAD_LCD_CS__LCD_ENABLE
@@ -864,8 +809,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- can0_pins_a: can0 at 0 {
- reg = <0>;
+ can0_pins_a: can0 {
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY2__CAN0_TX
MX28_PAD_GPMI_RDY3__CAN0_RX
@@ -875,8 +819,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- can1_pins_a: can1 at 0 {
- reg = <0>;
+ can1_pins_a: can1 {
fsl,pinmux-ids = <
MX28_PAD_GPMI_CE2N__CAN1_TX
MX28_PAD_GPMI_CE3N__CAN1_RX
@@ -886,8 +829,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- spi2_pins_a: spi2 at 0 {
- reg = <0>;
+ spi2_pins_a: spi2 {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__SSP2_SCK
MX28_PAD_SSP2_MOSI__SSP2_CMD
@@ -899,8 +841,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- spi3_pins_a: spi3 at 0 {
- reg = <0>;
+ spi3_pins_a: spi3 {
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__SSP3_D4
MX28_PAD_AUART2_TX__SSP3_D5
@@ -914,8 +855,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- spi3_pins_b: spi3 at 1 {
- reg = <1>;
+ spi3_pins_b: spi3b {
fsl,pinmux-ids = <
MX28_PAD_SSP3_SCK__SSP3_SCK
MX28_PAD_SSP3_MOSI__SSP3_CMD
@@ -927,8 +867,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- usb0_pins_a: usb0 at 0 {
- reg = <0>;
+ usb0_pins_a: usb0 {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
>;
@@ -937,8 +876,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- usb0_pins_b: usb0 at 1 {
- reg = <1>;
+ usb0_pins_b: usb0b {
fsl,pinmux-ids = <
MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
>;
@@ -947,8 +885,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- usb1_pins_a: usb1 at 0 {
- reg = <0>;
+ usb1_pins_a: usb1 {
fsl,pinmux-ids = <
MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
>;
@@ -957,8 +894,7 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
- usb0_id_pins_a: usb0id at 0 {
- reg = <0>;
+ usb0_id_pins_a: usb0id {
fsl,pinmux-ids = <
MX28_PAD_AUART1_RTS__USB0_ID
>;
@@ -967,8 +903,7 @@
fsl,pull-up = <MXS_PULL_ENABLE>;
};
- usb0_id_pins_b: usb0id1 at 0 {
- reg = <0>;
+ usb0_id_pins_b: usb0id1 {
fsl,pinmux-ids = <
MX28_PAD_PWM2__USB0_ID
>;
--
2.7.4
^ permalink raw reply related
* [PATCH 1/3] ARM: dts: imx6/7: Remove unit-address from anatop regulators
From: Fabio Estevam @ 2018-05-11 0:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@nxp.com>
Remove unit-address and reg property from anatop regulators to fix
the following DTC warnings with W=1:
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140)
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140)
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140)
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 20 ++++++--------------
arch/arm/boot/dts/imx6sl.dtsi | 20 ++++++--------------
arch/arm/boot/dts/imx6sx.dtsi | 20 ++++++--------------
arch/arm/boot/dts/imx6ul.dtsi | 11 +++--------
arch/arm/boot/dts/imx7s.dtsi | 8 ++------
5 files changed, 23 insertions(+), 56 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 69648e2..22942dd 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -692,11 +692,8 @@
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- regulator-1p1 at 20c8110 {
- reg = <0x20c8110>;
+ regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <1000000>;
@@ -711,8 +708,7 @@
anatop-enable-bit = <0>;
};
- regulator-3p0 at 20c8120 {
- reg = <0x20c8120>;
+ regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@@ -727,8 +723,7 @@
anatop-enable-bit = <0>;
};
- regulator-2p5 at 20c8130 {
- reg = <0x20c8130>;
+ regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2250000>;
@@ -743,8 +738,7 @@
anatop-enable-bit = <0>;
};
- reg_arm: regulator-vddcore at 20c8140 {
- reg = <0x20c8140>;
+ reg_arm: regulator-vddcore {
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@@ -761,8 +755,7 @@
anatop-max-voltage = <1450000>;
};
- reg_pu: regulator-vddpu at 20c8140 {
- reg = <0x20c8140>;
+ reg_pu: regulator-vddpu {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
@@ -779,8 +772,7 @@
anatop-max-voltage = <1450000>;
};
- reg_soc: regulator-vddsoc at 20c8140 {
- reg = <0x20c8140>;
+ reg_soc: regulator-vddsoc {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 2002db2..8c838ba 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -524,11 +524,8 @@
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- regulator-1p1 at 20c8110 {
- reg = <0x20c8110>;
+ regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
@@ -543,8 +540,7 @@
anatop-enable-bit = <0>;
};
- regulator-3p0 at 20c8120 {
- reg = <0x20c8120>;
+ regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@@ -559,8 +555,7 @@
anatop-enable-bit = <0>;
};
- regulator-2p5 at 20c8130 {
- reg = <0x20c8130>;
+ regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
@@ -575,8 +570,7 @@
anatop-enable-bit = <0>;
};
- reg_arm: regulator-vddcore at 20c8140 {
- reg = <0x20c8140>;
+ reg_arm: regulator-vddcore {
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@@ -593,8 +587,7 @@
anatop-max-voltage = <1450000>;
};
- reg_pu: regulator-vddpu at 20c8140 {
- reg = <0x20c8140>;
+ reg_pu: regulator-vddpu {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
@@ -611,8 +604,7 @@
anatop-max-voltage = <1450000>;
};
- reg_soc: regulator-vddsoc at 20c8140 {
- reg = <0x20c8140>;
+ reg_soc: regulator-vddsoc {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7e463d2..4a97513 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -591,11 +591,8 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- regulator-1p1 at 20c8110 {
- reg = <0x20c8110>;
+ regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
@@ -610,8 +607,7 @@
anatop-enable-bit = <0>;
};
- regulator-3p0 at 20c8120 {
- reg = <0x20c8120>;
+ regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@@ -626,8 +622,7 @@
anatop-enable-bit = <0>;
};
- regulator-2p5 at 20c8130 {
- reg = <0x20c8130>;
+ regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
@@ -642,8 +637,7 @@
anatop-enable-bit = <0>;
};
- reg_arm: regulator-vddcore at 20c8140 {
- reg = <0x20c8140>;
+ reg_arm: regulator-vddcore {
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@@ -660,8 +654,7 @@
anatop-max-voltage = <1450000>;
};
- reg_pcie: regulator-vddpcie at 20c8140 {
- reg = <0x20c8140>;
+ reg_pcie: regulator-vddpcie {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpcie";
regulator-min-microvolt = <725000>;
@@ -677,8 +670,7 @@
anatop-max-voltage = <1450000>;
};
- reg_soc: regulator-vddsoc at 20c8140 {
- reg = <0x20c8140>;
+ reg_soc: regulator-vddsoc {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 2b854d1..1818b6c 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -551,11 +551,8 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg_3p0: regulator-3p0 at 20c8110 {
- reg = <0x20c8110>;
+ reg_3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2625000>;
@@ -569,8 +566,7 @@
anatop-enable-bit = <0>;
};
- reg_arm: regulator-vddcore at 20c8140 {
- reg = <0x20c8140>;
+ reg_arm: regulator-vddcore {
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
@@ -587,8 +583,7 @@
anatop-max-voltage = <1450000>;
};
- reg_soc: regulator-vddsoc at 20c8140 {
- reg = <0x20c8140>;
+ reg_soc: regulator-vddsoc {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index b416d2b..99f92ec 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -557,11 +557,8 @@
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg_1p0d: regulator-vdd1p0d at 30360210 {
- reg = <0x30360210>;
+ reg_1p0d: regulator-vdd1p0d {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p0d";
regulator-min-microvolt = <800000>;
@@ -575,8 +572,7 @@
anatop-enable-bit = <0>;
};
- reg_1p2: regulator-vdd1p2 at 30360220 {
- reg = <0x30360220>;
+ reg_1p2: regulator-vdd1p2 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p2";
regulator-min-microvolt = <1100000>;
--
2.7.4
^ permalink raw reply related
* [PATCH] armpmu: broadcast overflow irq on multi-core system having one muxed SPI for PMU.
From: 류호은 @ 2018-05-10 23:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180510102114.obmctt3nn7xakggi@lakrids.cambridge.arm.com>
Thank you for the reply.
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland at arm.com]
> Sent: Thursday, May 10, 2018 7:21 PM
> To: Hoeun Ryu <hoeun.ryu@lge.com.com>
> Cc: Will Deacon <will.deacon@arm.com>; Hoeun Ryu <hoeun.ryu@lge.com>;
> linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org
> Subject: Re: [PATCH] armpmu: broadcast overflow irq on multi-core system
> having one muxed SPI for PMU.
>
> Hi,
> On Thu, May 10, 2018 at 05:36:17PM +0900, Hoeun Ryu wrote:
> > From: Hoeun Ryu <hoeun.ryu@lge.com>
> >
> > On some SoCs like i.MX6DL/QL have only one muxed SPI for multi-core
> system.
> > On the systems, a CPU can be interrupted by overflow irq but it is
> > possible that the overflow actually occurs on another CPU.
>
> Muxing the PMU IRQs is a really broken system design, and there's no good
> way of supporting it.
Yes. I agree with that. I scratched my head when I found the system has one
muxed SPI.
>
> What we should do for such systems is:
>
> * Add a flag to the DT to describe that the IRQs are muxed, as this
> cannot be probed.
>
> * Add hrtimer code to periodically update the counters, to avoid
> overflow (e.g. as we do in the l2x0 PMU).
>
> * Reject sampling for such systems, as this cannot be done reliably or
> efficiently.
>
> NAK to broadcasting the IRQ -- there are a number of issues with the
> general approach.
>
The second solution would be good if sampling is necessary even like those
systems.
Actually I'm working on FIQ available ARM32 system and trying to enable the
hard lockup detector by routing the PMU IRQ to FIQ.
Because of that, I really need the interrupt event if it is a muxed SPI,
beside I also need to make an dedicated IPI FIQ to broadcast the IRQ in
this approach.
What would you do if you were in the same situation ?
> We should update the PMU probing code to warn when we have fewer IRQs than
> CPUs, and fail gracefully to the above.
>
> [...]
>
> > static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) {
>
> > + /* smp_call_function cannot be called with irq
> disabled */
> > + local_irq_enable();
> > + preempt_disable();
> > + smp_call_function_many(&mask, __armpmu_handle_irq,
dev,
> 0);
> > + preempt_enable();
> > + local_irq_disable();
>
> For many reasons, this sequence is not safe.
>
> It is not safe to enable IRQs in irq handlers. Please never do this.
I was not sure it was safe to enable IRQs in irq handlers.
Thank you for pointing that.
>
> Thus it's also never safe to call smp_call_function*() in IRQ handlers.
Yes. I found out that it is due to csd lock.
>
> Futher, If you ever encounter a case where you need to avoid preemption
> across enabling IRQs, preemption must be disabled *before* enabling IRQs.
Ah, OK.
Enabling IRQs can cause scheduling tasks in the end of exception or other
scheduling points, right ?
>
> Thanks,
> Mark.
^ permalink raw reply
* [PATCH v2 00/10] PCI: leak fixes, removable generic PCI host, assorted stuff
From: Bjorn Helgaas @ 2018-05-10 22:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1525067324.git.jan.kiszka@siemens.com>
On Mon, Apr 30, 2018 at 07:48:34AM +0200, Jan Kiszka wrote:
> Changes in v2:
> - patch 1: commit message reworking as suggested by Lorenzo
> - patch 3-6: split-up as suggested by Bjorn
> - patch 8: new
> - patch 10: select PCI_DOMAINS from PCI_HOST_GENERIC, rather than
> allowing manual choice, as suggested by Lorenzo
>
> This primarily enables to unbind the generic PCI host controller without
> leaving lots of memory leaks behind. A previous proposal patch 5 was
> rejected because of those issues [1].
>
> The fixes have been validated in the Jailhouse setup, where we add and
> remove a virtual PCI host controller on hypervisor activation/
> deactivation, with the help of kmemleak.
>
> Besides that, there is tiny PCI API cleanup at the beginning and
> support for manually enabled PCI domains at the end that enables the
> Jailhouse scenario.
>
> Jan
>
> [1] http://lkml.iu.edu/hypermail/linux/kernel/1606.3/00072.html
>
>
> CC: Jingoo Han <jingoohan1@gmail.com>
> CC: Joao Pinto <Joao.Pinto@synopsys.com>
> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> CC: Will Deacon <will.deacon@arm.com>
>
> Jan Kiszka (10):
> PCI: Make pci_get_new_domain_nr() static
> PCI: Fix memory leak of devm_pci_alloc_host_bridge()
> PCI: Factor out __of_pci_get_host_bridge_resources()
> PCI: Add dev parameter to __of_pci_get_host_bridge_resources()
> PCI: Replace pr_*() with dev_*() in
> __of_pci_get_host_bridge_resources()
> PCI: Introduce devm_of_pci_get_host_bridge_resources()
> PCI: Convert of_pci_get_host_bridge_resources() users to devm variant
> PCI: Deprecate of_pci_get_host_bridge_resources()
> PCI: Add support for unbinding the generic PCI host controller
> PCI: Enable PCI_DOMAINS along with generic PCI host controller
Applied to pci/resource for v4.18, thanks!
I added the reviewed-by tags from Vladimir (thank you!) and replaced the
"Deprecate" patch by the v3 "Remove" patch.
> drivers/pci/dwc/pcie-designware-host.c | 2 +-
> drivers/pci/host/Kconfig | 1 +
> drivers/pci/host/pci-aardvark.c | 5 +-
> drivers/pci/host/pci-ftpci100.c | 4 +-
> drivers/pci/host/pci-host-common.c | 13 ++++
> drivers/pci/host/pci-host-generic.c | 1 +
> drivers/pci/host/pci-v3-semi.c | 3 +-
> drivers/pci/host/pci-versatile.c | 3 +-
> drivers/pci/host/pci-xgene.c | 3 +-
> drivers/pci/host/pcie-altera.c | 5 +-
> drivers/pci/host/pcie-iproc-platform.c | 4 +-
> drivers/pci/host/pcie-rcar.c | 5 +-
> drivers/pci/host/pcie-rockchip.c | 4 +-
> drivers/pci/host/pcie-xilinx-nwl.c | 4 +-
> drivers/pci/host/pcie-xilinx.c | 4 +-
> drivers/pci/of.c | 105 +++++++++++++++++++++------------
> drivers/pci/pci.c | 6 +-
> drivers/pci/probe.c | 4 +-
> include/linux/of_pci.h | 42 ++++++++++++-
> include/linux/pci-ecam.h | 1 +
> include/linux/pci.h | 3 -
> 21 files changed, 149 insertions(+), 73 deletions(-)
>
> --
> 2.13.6
>
^ permalink raw reply
* [RFC][PATCH] arm64: update iomem_resource.end
From: Nicolin Chen @ 2018-05-10 22:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cfb81f55-f917-431f-0afd-c97e7641a2f8@arm.com>
Thanks for the comments, Robin.
On Thu, May 10, 2018 at 06:45:59PM +0100, Robin Murphy wrote:
> On 09/05/18 23:58, Nicolin Chen wrote:
> >The iomem_resource.end is -1 by default and should be updated in
> >arch-level code.
> >
> >ARM64 so far hasn't updated it while core kernel code (mm/hmm.c)
> >started to use iomem_resource.end for boundary check. So it'd be
> >better to assign iomem_resource.end using a valid value, the end
> >of physical address space for example because iomem_resource.end
> >in theory should reflect that.
> >
> >However, VA_BITS might be smaller than PA_BITS in ARM64. So using
> >the end of physical address space doesn't make a lot of sense in
> >this case, or could be even harmful since virtual address cannot
> >reach that memory region.
>
> Why? There's plenty of stuff in the physical address space that will
> only ever be accessed via ioremap/memremap. There's no reason you
> shouldn't be able to run a VA_BITS < 48 kernel on a Cavium ThunderX
I'm running VA_BITS_39 and PA_BITS_48 on Tegra 210. There had
not been any problem of it, however with hmm.....
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/mm/hmm.c#n1144
This hmm_devmem_add() requests a region with PFNs being outside
of the linear region in ARM64 case which takes MAX_PHYSMEM_BITS
(48 bits) over iomem_resource.end without this patch. Then when
dealing with page structures in vmemmap region from a given PFN
directly (CONFIG_SPARSEMEM_VMEMMAP=y), and the given PFN is the
last one based on physical region (48 bits), the address of its
page structure will go beyond vmemmap region. Does this sound a
problem?
> where *all* the I/O is in the top half of the PA space. We already
> constrain RAM in this very function to those regions which fit into
> the linear map, and if you're accessing anything other than RAM
> through the linear map you're probably doing something wrong.
If I understand this part correctly, since ARM64 has applied the
memory limit already, does it mean that probably we should fix
something in the region_intersects() or add an extra check in the
hmm_devmem_add(), instead of limiting the iomem_resource?
> Furthermore, the physical region covered by the linear map doesn't
> necessarily start at physical address 0 anyway - see PHYS_OFFSET.
Hmm...okay...but there still should be a protection somewhere if
it happens to access a page structure via pfn_to_page() while the
PFN is not covered by the vmemmap linear mapping, right?
Thanks!
^ permalink raw reply
* [RESEND PATCH] pinctrl: rockchip: Disable interrupt when changing it's capability
From: Brian Norris @ 2018-05-10 22:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAD=FV=WZ+2MNbe341M7OQD11+RxaJuzdM6zMnXYB4dka74K1hQ@mail.gmail.com>
+ irqchip maintainers
[ irqchip is weird -- it's all over drivers/{pinctrl,gpio,irqchip}/ :D ]
Hi Doug,
On Tue, May 08, 2018 at 10:18:18PM -0700, Doug Anderson wrote:
> On Tue, May 8, 2018 at 7:21 PM, JeffyChen <jeffy.chen@rock-chips.com> wrote:
> > On 05/09/2018 03:46 AM, Doug Anderson wrote:
> >> One note is that in the case Brian points at (where we need to
> >> simulate EDGE_BOTH by swapping edges) we purposely ignored the TRM and
> >> we needed to do that to avoid losing interrupts. For details, see
> >> commit 53b1bfc76df2 ("pinctrl: rockchip: Avoid losing interrupts when
> >> supporting both edges"). We did this because:
> >>
> >> 1. We believed that the IP block in Rockchip SoCs has nearly the same
> >> logic as "gpio-dwapb.c" and that's what "gpio-dwapb.c" did.
> >>
> >
> > hmm, but i saw the gpio-dwapb.c actually toggle trigger after handle irq,
> > which might avoid the race Brian mentioned:
> > + generic_handle_irq(gpio_irq);
> > + irq_status &= ~BIT(hwirq);
> > +
> > + if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
> > + == IRQ_TYPE_EDGE_BOTH)
> > + dwapb_toggle_trigger(gpio, hwirq);
>
> The code you point at in dwapb_toggle_trigger() specifically is an
> example of toggling the polarity _without_ disabling the interrupt in
> between. We took this as "working" code and as proof that it was OK
> to change polarity without disabling the interrupt in-between.
There's a crucial ordering difference though: gpio-dwapb performs its
polarity adjustments *after* calling generic_handle_irq(), which among
other things calls ->irq_ack(). This means that it's re-ensuring that
the polarity is correct *after* the point at which it last ack'ed the
interrupt. So there's no chance of it clearing a second interrupt
without appropriately reconfiguring the polarity.
> > and i also saw ./qcom/pinctrl-msm.c do the
> > toggle(msm_gpio_update_dual_edge_pos) at the end of msm_gpio_irq_set_type
> > and msm_gpio_irq_ack, that seems can avoid the polarity races too.
> >
> >> 2. We were actually losing real interrupts and this was the only way
> >> we could figure out how to fix it.
> >>
> >> When I tested that back in the day I was fairly convinced that we
> >> weren't losing any interrupts in the EDGE_BOTH case after my fix, but
> >> I certainly could have messed up.
> >>
> >>
> >> For the EDGE_BOTH case it was important not to lose an interrupt
> >> because, as you guys are talking about, we could end up configured the
> >> wrong way. I think in your case where you're just picking one
> >> polarity losing an interrupt shouldn't matter since it's undefined
> >> exactly if an edge happens while you're in the middle of executing
> >> rockchip_irq_set_type(). Is that right?
> >
> >
> > right, so we now have 2 cases: rockchip_irq_demux/ rockchip_irq_set_type
> >
> > if i'm right about the spurious irq(only happen when set rising for a high
> > gpio, or set falling for a low gpio), then:
> >
> > 1/ rockchip_irq_demux
> > it's important to not losing irqs in this case, maybe we can
> >
> > a) ack irq
> > b) update polarity for edge both irq
> >
> > we don't need to disable irq in b), since we would not hit the spurious irq
> > cases here(always check gpio level to toggle it)
>
> Unless you have some sort of proof that rockchip_irq_demux(), I would
> take it as an example of something that works. I remember stress
> testing the heck out of it. Do you have some evidence that it's not
> working? I think Brian was simply speculating that there might be a
> race here, but I don't think anyone has shown it have they? Looking
> back at my notes, the thing I really made sure to stress was that we
> never got into a situation where we were losing an edge (AKA we were
> never configured to look for a falling edge when the line was already
> low). I'm not sure I confirmed that we never got an extra interrupt.
I'll agree wholeheartedly that I'm only at the speculation stage right
now :) I can try to poke at it sometime if I get some cycles. I'd
definitely want to get better test results to prove this before changing
this part.
This is really just a side tangent anyway, because apparently the
existing code is working well enough for rockchip_irq_demux(), and for
$subject, we're really only working on improving set_type().
> I'm at home right now and I can't add prints and poke at things, but
> as I understand it for edge interrupts the usual flow to make sure
> interrupts aren't ever lost is:
>
> 1. See that the interrupt went off
> 2. Ack it (clear it)
> 3. Call the interrupt handler
>
> ...presumably in this case rockchip_irq_demux() is called after step
> #2 (but I don't know if it's called before or after step #3). If the
One thing to note here is that we're talking about a 2-level (chained)
interrupt system. We've got the GIC, which does all of 1, 2, 3 at its
level, and as part of #3 for the GIC, it runs the 2nd-level handler --
rockchip_irq_demux() -- which has to perform all of 1, 2, 3 at its level.
1 -> this is looping over GPIO_INT_STATUS in rockchip_irq_demux()
2 -> this happens when writing to GPIO_PORTS_EOI, which only is called
by ->irq_ack() (irq_gc_ack_set_bit()) ... which happens from:
rockchip_irq_demux()
-> generic_handle_irq()
-> handle_edge_irq()
-> desc->irq_data.chip->irq_ack() = irq_gc_ack_set_bit()
3 -> same callpath as 2, except it's
-> handle_edge_irq()
-> handle_irq_event()
Those all happen in the correct order.
But the problem is that you left out the part about "change polarity for
emulating EDGE_BOTH"; in your example (gpio-dwapb.c), polarity
adjustment happens *after* 2; in Rockchip's driver, we have it before.
I'm pretty sure dwapb is correct, and we are not.
> line is toggling like crazy while the 3 steps are going on, it's OK if
> the interrupt handler is called more than once. In general this could
> be considered expected. That's why you Ack before handling--any extra
> edges that come in any time after the interrupt handler starts (even
> after the very first instruction) need to cause the interrupt handler
> to get called again.
>
> This is different than Brian's understanding since he seemed to think
> the Ack was happening later. If you're in front of something where
> you can add printouts, maybe you can tell us. I tried to look through
> the code and it was too twisted for me to be sure.
I'm not sure your understanding of my understanding is accurate :)
Hopefully the above clarifies what I'm thinking?
> > 2/ rockchip_irq_set_type
> > it's important to not having spurious irqs
> >
> > so we can disable irq during changing polarity only in these case:
> > ((rising && gpio is heigh) || (falling && gpio is low))
> >
> > i'm still confirming the spurious irq with IC guys.
>
> Hmmm, thinking about all this more, I'm curious how callers expect
> this to work. Certainly things are undefined if you have the
> following situation:
>
> Start: rising edge trigger, line is actually high
> Request: change to falling edge trigger
> Line falls during the request
>
> In that case it's OK to throw the interrupt away because it can be
> argued that the line could have fallen before the request actually
> took place. ...but it seems like there could be situations where the
> user wouldn't expect interrupts to be thrown away by a call to
> irq_set_type(). In other words:
>
> Start: rising edge trigger, line is actually high
> Request: change to falling edge trigger
> Line falls, rises, and falls during the request
>
> ...in that case you'd expect that some sort of interrupt would have
> gone off and not be thrown away. No matter what instant in time the
> request actually took place it should have caught an edge, right?
>
>
> Said another way: As a client of irq_set_type() I'd expect it to not
> throw away interrupts, but I'd expect that the change in type would be
> atomic. That is: if the interrupt came in before the type change in
> type applied then it should trigger with the old rules. If the
> interrupt came in after the type change then it should trigger with
> the new rules.
I'm not sure it's totally possible to differentiate these, but that
seems about right I think.
> I would be tempted to confirm your testing and just clear the spurious
> interrupts that you're aware of. AKA: if there's no interrupt pending
> and you change the type to "IRQ_TYPE_EDGE_RISING" or
> "IRQ_TYPE_EDGE_FALLING" then you should clear the interrupt. It's
> still racy, but I guess it's the best you can do unless IC guys come
> up with something better.
Thanks! Yeah, clearing (rather than temporarily disabling) seems to make
more sense.
> Anyway, it's past my bedtime. Hopefully some of the above made sense.
> I'm sure you'll tell me if it didn't or if I said something
> stupid/wrong. :-P
Brian
^ permalink raw reply
* [PATCH v3 6/8] arm64: module-plts: Extend veneer to address 52-bit VAs
From: Ard Biesheuvel @ 2018-05-10 22:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180510162347.3858-7-steve.capper@arm.com>
On 10 May 2018 at 18:23, Steve Capper <steve.capper@arm.com> wrote:
> From: Ard Bieusheuval <ard.biesheuvel@linaro.org>
>
> In preparation for 52-bit VA support in the Linux kernel, we extend the
> plts veneer to support 52-bit addresses via an extra movk instruction.
>
> [Steve: code from Ard off-list, changed the #ifdef logic to inequality]
> Signed-off-by: Steve Capper <steve.capper@arm.com>
>
> ---
>
> New in V3 of the series.
>
> I'm not sure if this is strictly necessary as the VAs of the module
> space will fit within 48-bits of addressing even when a 52-bit VA space
> is enabled.
What about the kernel text itself? Is that also guaranteed to have
bits [51:48] of its VAs equal 0xf, even under randomization?
If so, I agree we don't need the patch.
> However, this may act to future-proof the 52-bit VA support
> should any future adjustments be made to the VA space.
> ---
> arch/arm64/include/asm/module.h | 13 ++++++++++++-
> arch/arm64/kernel/module-plts.c | 12 ++++++++++++
> 2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/module.h b/arch/arm64/include/asm/module.h
> index 97d0ef12e2ff..30b8ca95d19a 100644
> --- a/arch/arm64/include/asm/module.h
> +++ b/arch/arm64/include/asm/module.h
> @@ -59,6 +59,9 @@ struct plt_entry {
> __le32 mov0; /* movn x16, #0x.... */
> __le32 mov1; /* movk x16, #0x...., lsl #16 */
> __le32 mov2; /* movk x16, #0x...., lsl #32 */
> +#if CONFIG_ARM64_VA_BITS > 48
> + __le32 mov3; /* movk x16, #0x...., lsl #48 */
> +#endif
> __le32 br; /* br x16 */
> };
>
> @@ -71,7 +74,8 @@ static inline struct plt_entry get_plt_entry(u64 val)
> * +--------+------------+--------+-----------+-------------+---------+
> *
> * Rd := 0x10 (x16)
> - * hw := 0b00 (no shift), 0b01 (lsl #16), 0b10 (lsl #32)
> + * hw := 0b00 (no shift), 0b01 (lsl #16), 0b10 (lsl #32),
> + * 0b11 (lsl #48)
> * opc := 0b11 (MOVK), 0b00 (MOVN), 0b10 (MOVZ)
> * sf := 1 (64-bit variant)
> */
> @@ -79,6 +83,9 @@ static inline struct plt_entry get_plt_entry(u64 val)
> cpu_to_le32(0x92800010 | (((~val ) & 0xffff)) << 5),
> cpu_to_le32(0xf2a00010 | ((( val >> 16) & 0xffff)) << 5),
> cpu_to_le32(0xf2c00010 | ((( val >> 32) & 0xffff)) << 5),
> +#if CONFIG_ARM64_VA_BITS > 48
> + cpu_to_le32(0xf2e00010 | ((( val >> 48) & 0xffff)) << 5),
> +#endif
> cpu_to_le32(0xd61f0200)
> };
> }
> @@ -86,6 +93,10 @@ static inline struct plt_entry get_plt_entry(u64 val)
> static inline bool plt_entries_equal(const struct plt_entry *a,
> const struct plt_entry *b)
> {
> +#if CONFIG_ARM64_VA_BITS > 48
> + if (a->mov3 != b->mov3)
> + return false;
> +#endif
> return a->mov0 == b->mov0 &&
> a->mov1 == b->mov1 &&
> a->mov2 == b->mov2;
> diff --git a/arch/arm64/kernel/module-plts.c b/arch/arm64/kernel/module-plts.c
> index f0690c2ca3e0..4d5617e09943 100644
> --- a/arch/arm64/kernel/module-plts.c
> +++ b/arch/arm64/kernel/module-plts.c
> @@ -50,6 +50,9 @@ u64 module_emit_veneer_for_adrp(struct module *mod, void *loc, u64 val)
> struct plt_entry *plt = (struct plt_entry *)pltsec->plt->sh_addr;
> int i = pltsec->plt_num_entries++;
> u32 mov0, mov1, mov2, br;
> +#if CONFIG_ARM64_VA_BITS > 48
> + u32 mov3;
> +#endif
> int rd;
>
> if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries))
> @@ -69,6 +72,12 @@ u64 module_emit_veneer_for_adrp(struct module *mod, void *loc, u64 val)
> mov2 = aarch64_insn_gen_movewide(rd, (u16)(val >> 32), 32,
> AARCH64_INSN_VARIANT_64BIT,
> AARCH64_INSN_MOVEWIDE_KEEP);
> +#if CONFIG_ARM64_VA_BITS > 48
> + mov3 = aarch64_insn_gen_movewide(rd, (u16)(val >> 48), 48,
> + AARCH64_INSN_VARIANT_64BIT,
> + AARCH64_INSN_MOVEWIDE_KEEP);
> +#endif
> +
> br = aarch64_insn_gen_branch_imm((u64)&plt[i].br, (u64)loc + 4,
> AARCH64_INSN_BRANCH_NOLINK);
>
> @@ -76,6 +85,9 @@ u64 module_emit_veneer_for_adrp(struct module *mod, void *loc, u64 val)
> cpu_to_le32(mov0),
> cpu_to_le32(mov1),
> cpu_to_le32(mov2),
> +#if CONFIG_ARM64_VA_BITS > 48
> + cpu_to_le32(mov3),
> +#endif
> cpu_to_le32(br)
> };
>
> --
> 2.11.0
>
^ permalink raw reply
* [PATCH] ARM: dts: BCM5301X: Switch D-Link DIR-885L to the new partitions syntax
From: Rafał Miłecki @ 2018-05-10 21:20 UTC (permalink / raw)
To: linux-arm-kernel
From: Rafa? Mi?ecki <rafal@milecki.pl>
This new syntax is slightly better designed & uses "compatible" string.
For details see Documentation/devicetree/bindings/mtd/partition.txt .
Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
---
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
index 494dbd39658c..d173bcd93b91 100644
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
@@ -26,9 +26,15 @@
nand: nand at 18028000 {
nandcs at 0 {
- partition at 0 {
- label = "firmware";
- reg = <0x00000000 0x08000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "firmware";
+ reg = <0x00000000 0x08000000>;
+ };
};
};
};
--
2.13.6
^ permalink raw reply related
* [PATCH] arm64: dts: stratix10: Add QSPI support for Stratix10
From: thor.thayer at linux.intel.com @ 2018-05-10 20:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Thor Thayer <thor.thayer@linux.intel.com>
Add qspi_clock
The qspi_clk frequency is updated by U-Boot before starting Linux.
Add QSPI interface node.
Add QSPI flash memory child node.
Setup the QSPI memory in 2 partitions.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 22 +++++++++++++++
.../boot/dts/altera/socfpga_stratix10_socdk.dts | 31 ++++++++++++++++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index e6b059378dc0..ed47dfce3ba6 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -119,6 +119,12 @@
#clock-cells = <0>;
compatible = "fixed-clock";
};
+
+ qspi_clk: qspi_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
};
gmac0: ethernet at ff800000 {
@@ -466,5 +472,21 @@
interrupts = <16 4>, <48 4>;
};
};
+
+ qspi: spi at ff8d2000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff8d2000 0x100>,
+ <0xff900000 0x100000>;
+ interrupts = <0 3 4>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
+ bus-num = <1>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index f9b1ef12db48..60251462067a 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -147,3 +147,34 @@
reg = <0x68>;
};
};
+
+&qspi {
+ flash0: n25q00 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00aa";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partition at qspi-boot {
+ label = "Boot and fpga data";
+ /* 64MB for boot and FPGA data */
+ reg = <0x0 0x4000000>;
+ };
+
+ partition at qspi-rootfs {
+ label = "Root Filesystem - JFFS2";
+ /* 64MB for Linux jffs2 */
+ reg = <0x4000000 0x4000000>;
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v6 2/2] drivers: soc: Add LLCC driver
From: Evan Green @ 2018-05-10 20:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525810921-15878-3-git-send-email-rishabhb@codeaurora.org>
Hi Rishabh,
On Tue, May 8, 2018 at 1:23 PM Rishabh Bhatnagar <rishabhb@codeaurora.org>
wrote:
> LLCC (Last Level Cache Controller) provides additional cache memory
> in the system. LLCC is partitioned into multiple slices and each
> slice gets its own priority, size, ID and other config parameters.
> LLCC driver programs these parameters for each slice. Clients that
> are assigned to use LLCC need to get information such size & ID of the
> slice they get and activate or deactivate the slice as needed. LLCC driver
> provides API for the clients to perform these operations.
> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
> Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
> ---
> drivers/soc/qcom/Kconfig | 17 ++
> drivers/soc/qcom/Makefile | 2 +
> drivers/soc/qcom/llcc-sdm845.c | 106 ++++++++++++
> drivers/soc/qcom/llcc-slice.c | 335
+++++++++++++++++++++++++++++++++++++
> include/linux/soc/qcom/llcc-qcom.h | 162 ++++++++++++++++++
> 5 files changed, 622 insertions(+)
> create mode 100644 drivers/soc/qcom/llcc-sdm845.c
> create mode 100644 drivers/soc/qcom/llcc-slice.c
> create mode 100644 include/linux/soc/qcom/llcc-qcom.h
...
> diff --git a/drivers/soc/qcom/llcc-sdm845.c
b/drivers/soc/qcom/llcc-sdm845.c
> new file mode 100644
> index 0000000..e5e792c
> --- /dev/null
> +++ b/drivers/soc/qcom/llcc-sdm845.c
> @@ -0,0 +1,106 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
> + *
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/soc/qcom/llcc-qcom.h>
> +
> +/*
> + * SCT(System Cache Table) entry contains of the following members:
> + * usecase_id: Unique id for the client's use case
> + * slice_id: llcc slice id for each client
> + * max_cap: The maximum capacity of the cache slice provided in KB
> + * priority: Priority of the client used to select victim line for
replacement
> + * fixed_size: Boolean indicating if the slice has a fixed capacity
> + * bonus_ways: Bonus ways are additional ways to be used for any slice,
> + * if client ends up using more than reserved cache ways.
Bonus
> + * ways are allocated only if they are not reserved for some
> + * other client.
> + * res_ways: Reserved ways for the cache slice, the reserved ways cannot
> + * be used by any other client than the one its assigned to.
> + * cache_mode: Each slice operates as a cache, this controls the mode of
the
> + * slice: normal or TCM(Tightly Coupled Memory)
> + * probe_target_ways: Determines what ways to probe for access hit. When
> + * configured to 1 only bonus and reserved ways are
probed.
> + * When configured to 0 all ways in llcc are probed.
> + * dis_cap_alloc: Disable capacity based allocation for a client
> + * retain_on_pc: If this bit is set and client has maintained active vote
> + * then the ways assigned to this client are not flushed
on power
> + * collapse.
> + * activate_on_init: Activate the slice immediately after the SCT is
programmed
> + */
> +#define SCT_ENTRY(uid, sid, mc, p, fs, bway, rway, cmod, ptw, dca, rp,
a) \
> + { \
> + .usecase_id = uid, \
> + .slice_id = sid, \
> + .max_cap = mc, \
> + .priority = p, \
> + .fixed_size = fs, \
> + .bonus_ways = bway, \
> + .res_ways = rway, \
> + .cache_mode = cmod, \
> + .probe_target_ways = ptw, \
> + .dis_cap_alloc = dca, \
> + .retain_on_pc = rp, \
> + .activate_on_init = a, \
> + }
> +
> +static struct llcc_slice_config sdm845_data[] = {
> + SCT_ENTRY(1, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1),
> + SCT_ENTRY(2, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0),
> + SCT_ENTRY(3, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0),
> + SCT_ENTRY(4, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0),
> + SCT_ENTRY(5, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
> + SCT_ENTRY(6, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
> + SCT_ENTRY(7, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0),
> + SCT_ENTRY(8, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
> + SCT_ENTRY(10, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
> + SCT_ENTRY(11, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0),
> + SCT_ENTRY(12, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0),
> + SCT_ENTRY(13, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1),
> + SCT_ENTRY(15, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
> + SCT_ENTRY(16, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
> + SCT_ENTRY(17, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
> + SCT_ENTRY(20, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0),
> + SCT_ENTRY(21, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0),
> + SCT_ENTRY(22, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0),
> +};
Now that drivers are hardcoding IDs when calling llcc_slice_getd, should we
add #defines in llcc-qcom.h for each of the usecase IDs? Then this would
change the entries to look like:
SCT_ENTRY(QCOM_LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1,
1, 1),
and drivers using it would call llcc_slice_getd(QCOM_LLCC_CPUSS), rather
than llcc_slice_getd(1).
> diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
> new file mode 100644
> index 0000000..209df55
> --- /dev/null
> +++ b/drivers/soc/qcom/llcc-slice.c
> @@ -0,0 +1,335 @@
...
> +
> +/**
> + * llcc_slice_activate - Activate the llcc slice
> + * @desc: Pointer to llcc slice descriptor
> + *
> + * A value of zero will be returned on success and a negative errno will
> + * be returned in error cases
> + */
> +int llcc_slice_activate(struct llcc_slice_desc *desc)
> +{
> + int ret;
> + u32 act_ctrl_val;
> +
> + mutex_lock(&drv_data->lock);
> + if (test_bit(desc->slice_id, drv_data->bitmap)) {
> + mutex_unlock(&drv_data->lock);
> + return 0;
> + }
> +
> + act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
> +
> + ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
> + DEACTIVATE);
> + if (ret)
> + return ret;
I had asked for this in the last revision, and thank you for putting that
in so that the bitmap matches reality. Unfortunately this introduces
another error, which is that you never unlock the mutex :(
> +
> + __set_bit(desc->slice_id, drv_data->bitmap);
> + mutex_unlock(&drv_data->lock);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(llcc_slice_activate);
> +
> +/**
> + * llcc_slice_deactivate - Deactivate the llcc slice
> + * @desc: Pointer to llcc slice descriptor
> + *
> + * A value of zero will be returned on success and a negative errno will
> + * be returned in error cases
> + */
> +int llcc_slice_deactivate(struct llcc_slice_desc *desc)
> +{
> + u32 act_ctrl_val;
> + int ret;
> +
> + mutex_lock(&drv_data->lock);
> + if (!test_bit(desc->slice_id, drv_data->bitmap)) {
> + mutex_unlock(&drv_data->lock);
> + return 0;
> + }
> + act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE <<
ACT_CTRL_OPCODE_SHIFT;
> +
> + ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
> + ACTIVATE);
> + if (ret)
> + return ret;
Same here, mutex left locked.
> +
> + __clear_bit(desc->slice_id, drv_data->bitmap);
> + mutex_unlock(&drv_data->lock);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
> +
> +/**
> + * llcc_get_slice_id - return the slice id
> + * @desc: Pointer to llcc slice descriptor
> + */
> +int llcc_get_slice_id(struct llcc_slice_desc *desc)
> +{
> + return desc->slice_id;
> +}
> +EXPORT_SYMBOL_GPL(llcc_get_slice_id);
> +
> +/**
> + * llcc_get_slice_size - return the slice id
> + * @desc: Pointer to llcc slice descriptor
> + */
> +size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
> +{
> + return desc->slice_size;
> +}
> +EXPORT_SYMBOL_GPL(llcc_get_slice_size);
> +
> +static int qcom_llcc_cfg_program(struct platform_device *pdev)
> +{
> + int i;
> + u32 attr1_cfg;
> + u32 attr0_cfg;
> + u32 attr1_val;
> + u32 attr0_val;
> + u32 max_cap_cacheline;
> + u32 sz;
> + int ret = 0;
> + const struct llcc_slice_config *llcc_table;
> + struct llcc_slice_desc desc;
> + u32 bcast_off = drv_data->bcast_off;
> +
> + sz = drv_data->cfg_size;
> + llcc_table = drv_data->cfg;
> +
> + for (i = 0; i < sz; i++) {
> + attr1_cfg = bcast_off +
> +
LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
> + attr0_cfg = bcast_off +
> +
LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
> +
> + attr1_val = llcc_table[i].cache_mode;
> + attr1_val |= llcc_table[i].probe_target_ways <<
> + ATTR1_PROBE_TARGET_WAYS_SHIFT;
> + attr1_val |= llcc_table[i].fixed_size <<
> + ATTR1_FIXED_SIZE_SHIFT;
> + attr1_val |= llcc_table[i].priority <<
ATTR1_PRIORITY_SHIFT;
> +
> + max_cap_cacheline =
MAX_CAP_TO_BYTES(llcc_table[i].max_cap);
> +
> + /* LLCC instances can vary for each target.
> + * The SW writes to broadcast register which gets
propagated
> + * to each llcc instace (llcc0,.. llccN).
> + * Since the size of the memory is divided equally
amongst the
> + * llcc instances, we need to configure the max cap
accordingly.
> + */
> + max_cap_cacheline = max_cap_cacheline /
drv_data->num_banks;
> + max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
> + attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
> +
> + attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
> + attr0_val |= llcc_table[i].bonus_ways <<
ATTR0_BONUS_WAYS_SHIFT;
> +
> + ret = regmap_write(drv_data->regmap, attr1_cfg,
attr1_val);
> + if (ret)
> + return ret;
> + ret = regmap_write(drv_data->regmap, attr0_cfg,
attr0_val);
> + if (ret)
> + return ret;
> + if (llcc_table[i].activate_on_init) {
> + desc.slice_id = llcc_table[i].slice_id;
> + ret = llcc_slice_activate(&desc);
> + }
> + }
> + return ret;
> +}
> +
> +int qcom_llcc_probe(struct platform_device *pdev,
> + const struct llcc_slice_config *llcc_cfg, u32 sz)
> +{
> +
> + u32 num_banks = 0;
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + void __iomem *base;
> + int ret = 0;
> + int i;
> +
> + drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
> + if (!drv_data)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + drv_data->regmap = devm_regmap_init_mmio(dev, base,
> + &llcc_regmap_config);
> + if (IS_ERR(drv_data->regmap))
> + return PTR_ERR(drv_data->regmap);
> +
> + ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
> + &num_banks);
> + if (ret)
> + return ret;
> +
> + num_banks &= LLCC_LB_CNT_MASK;
> + num_banks >>= LLCC_LB_CNT_SHIFT;
> + drv_data->num_banks = num_banks;
> +
> + ret = of_property_read_u32(pdev->dev.of_node, "max-slices",
> + &drv_data->max_slices);
> + if (ret)
> + return ret;
> +
The way this driver is written, there is only one sane value for
max-slices, and it can be derived by finding the max slice_id in llcc_cfg.
You only use "max-slices" to size the bitmap, but then use the slice_id
everywhere when indexing into the bitmap, so as far as I can tell this DT
property is not needed. Can we remove it from the binding and just derive
the value by iterating over llcc_cfg to find the max slice_id?
-Evan
^ permalink raw reply
* [PATCH 2/4] pid: Export find_task_by_vpid for use in external modules
From: Russell King - ARM Linux @ 2018-05-10 19:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANLsYkwaNmZCUjwJXK0X1ia+RnzumfbpB8EvZJ-HDtOHj8rafQ@mail.gmail.com>
On Thu, May 10, 2018 at 01:39:18PM -0600, Mathieu Poirier wrote:
> Hi Russell,
>
> On 10 May 2018 at 02:40, Russell King - ARM Linux <linux@armlinux.org.uk> wrote:
> > This does not leak information from other namespaces because of the
> > uniqueness of the global PID. However, what it does leak is the value
> > of the global PID which is meaningless in the namespace. So, before
> > the event stream is delivered to userspace, this value needs to be
> > re-written to the namespace's PID value.
>
> Unfortunately that can't be done. The trace stream is compressed and
> needs to be decompressed using an external library. I think the only
> option is to return an error if a user is trying to use this feature
> from a namespace.
That sounds like a sensible approach, and that should get rid of the
vpid stuff too.
Eric, would this solve all your concerns?
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
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