* [PATCH v2 0/3] Fix an Atmel USBA UDC issue introducted in 4.17-rc1
From: Romain Izard @ 2018-05-11 10:19 UTC (permalink / raw)
To: linux-arm-kernel
The use of GPIO descriptors takes care of inversion flags declared in
the device tree. The conversion of the Atmel USBA UDC driver introduced
in 4.17-rc1 missed it, and as a result the inversion will not work.
In addition, cleanup the code to remove an include left behind after
the suppression of the support of platform_data to declare USBA
controllers.
These changes have not been tested on any hardware, as I do not have
a board that needs to use inverted GPIOs.
--
Changes in v2:
- Use the correct format for the "Fixes:" tag
- Collect "Acked-by:" tags
Romain Izard (3):
usb: gadget: udc: atmel: GPIO inversion is handled by gpiod
usb: gadget: udc: atmel: Remove obsolete include
usb: gadget: udc: atmel: Fix indenting
drivers/usb/gadget/udc/atmel_usba_udc.c | 22 ++++++++++------------
drivers/usb/gadget/udc/atmel_usba_udc.h | 1 -
include/linux/usb/atmel_usba_udc.h | 24 ------------------------
3 files changed, 10 insertions(+), 37 deletions(-)
delete mode 100644 include/linux/usb/atmel_usba_udc.h
--
2.14.1
^ permalink raw reply
* [PATCH v2 1/3] usb: gadget: udc: atmel: GPIO inversion is handled by gpiod
From: Romain Izard @ 2018-05-11 10:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511101956.11782-1-romain.izard.pro@gmail.com>
When converting to GPIO descriptors, gpiod_get_value automatically
handles the line inversion flags from the device tree.
Do not invert the line twice.
Fixes: 3df034081021 ("usb: gadget: udc: atmel: convert to use GPIO descriptors")
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
drivers/usb/gadget/udc/atmel_usba_udc.c | 3 +--
drivers/usb/gadget/udc/atmel_usba_udc.h | 1 -
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c b/drivers/usb/gadget/udc/atmel_usba_udc.c
index 27c16399c7e8..0fe3d0feb8f7 100644
--- a/drivers/usb/gadget/udc/atmel_usba_udc.c
+++ b/drivers/usb/gadget/udc/atmel_usba_udc.c
@@ -417,7 +417,7 @@ static inline void usba_int_enb_set(struct usba_udc *udc, u32 val)
static int vbus_is_present(struct usba_udc *udc)
{
if (udc->vbus_pin)
- return gpiod_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
+ return gpiod_get_value(udc->vbus_pin);
/* No Vbus detection: Assume always present */
return 1;
@@ -2076,7 +2076,6 @@ static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
udc->vbus_pin = devm_gpiod_get_optional(&pdev->dev, "atmel,vbus",
GPIOD_IN);
- udc->vbus_pin_inverted = gpiod_is_active_low(udc->vbus_pin);
if (fifo_mode == 0) {
pp = NULL;
diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.h b/drivers/usb/gadget/udc/atmel_usba_udc.h
index 969ce8f3c3e2..d7eb7cf4fd5c 100644
--- a/drivers/usb/gadget/udc/atmel_usba_udc.h
+++ b/drivers/usb/gadget/udc/atmel_usba_udc.h
@@ -326,7 +326,6 @@ struct usba_udc {
const struct usba_udc_errata *errata;
int irq;
struct gpio_desc *vbus_pin;
- int vbus_pin_inverted;
int num_ep;
int configured_ep;
struct usba_fifo_cfg *fifo_cfg;
--
2.14.1
^ permalink raw reply related
* [PATCH v2 2/3] usb: gadget: udc: atmel: Remove obsolete include
From: Romain Izard @ 2018-05-11 10:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511101956.11782-1-romain.izard.pro@gmail.com>
The include defines the private platform_data structure used with AVR
platforms. It has no user since 7c55984e191f. Remove it.
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
drivers/usb/gadget/udc/atmel_usba_udc.c | 1 -
include/linux/usb/atmel_usba_udc.h | 24 ------------------------
2 files changed, 25 deletions(-)
delete mode 100644 include/linux/usb/atmel_usba_udc.h
diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c b/drivers/usb/gadget/udc/atmel_usba_udc.c
index 0fe3d0feb8f7..b9623e228609 100644
--- a/drivers/usb/gadget/udc/atmel_usba_udc.c
+++ b/drivers/usb/gadget/udc/atmel_usba_udc.c
@@ -20,7 +20,6 @@
#include <linux/ctype.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
-#include <linux/usb/atmel_usba_udc.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/irq.h>
diff --git a/include/linux/usb/atmel_usba_udc.h b/include/linux/usb/atmel_usba_udc.h
deleted file mode 100644
index 9bb00df3b53f..000000000000
--- a/include/linux/usb/atmel_usba_udc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Platform data definitions for Atmel USBA gadget driver.
- */
-#ifndef __LINUX_USB_USBA_H
-#define __LINUX_USB_USBA_H
-
-struct usba_ep_data {
- char *name;
- int index;
- int fifo_size;
- int nr_banks;
- int can_dma;
- int can_isoc;
-};
-
-struct usba_platform_data {
- int vbus_pin;
- int vbus_pin_inverted;
- int num_ep;
- struct usba_ep_data ep[0];
-};
-
-#endif /* __LINUX_USB_USBA_H */
--
2.14.1
^ permalink raw reply related
* [PATCH v2 3/3] usb: gadget: udc: atmel: Fix indenting
From: Romain Izard @ 2018-05-11 10:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511101956.11782-1-romain.izard.pro@gmail.com>
Fix the fallout of the conversion to GPIO descriptors in 3df034081021.
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
---
drivers/usb/gadget/udc/atmel_usba_udc.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c b/drivers/usb/gadget/udc/atmel_usba_udc.c
index b9623e228609..2f586f2bda7e 100644
--- a/drivers/usb/gadget/udc/atmel_usba_udc.c
+++ b/drivers/usb/gadget/udc/atmel_usba_udc.c
@@ -2277,15 +2277,15 @@ static int usba_udc_probe(struct platform_device *pdev)
if (udc->vbus_pin) {
irq_set_status_flags(gpiod_to_irq(udc->vbus_pin), IRQ_NOAUTOEN);
ret = devm_request_threaded_irq(&pdev->dev,
- gpiod_to_irq(udc->vbus_pin), NULL,
- usba_vbus_irq_thread, USBA_VBUS_IRQFLAGS,
- "atmel_usba_udc", udc);
- if (ret) {
- udc->vbus_pin = NULL;
- dev_warn(&udc->pdev->dev,
- "failed to request vbus irq; "
- "assuming always on\n");
- }
+ gpiod_to_irq(udc->vbus_pin), NULL,
+ usba_vbus_irq_thread, USBA_VBUS_IRQFLAGS,
+ "atmel_usba_udc", udc);
+ if (ret) {
+ udc->vbus_pin = NULL;
+ dev_warn(&udc->pdev->dev,
+ "failed to request vbus irq; "
+ "assuming always on\n");
+ }
}
ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
--
2.14.1
^ permalink raw reply related
* [PATCH v3 02/14] drivers: soc: sunxi: Add dedicated compatibles for the A13, A20 and A33
From: Maxime Ripard @ 2018-05-11 10:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v67An8RSCKEDSgW_jY7m8iw22K4rRHb02q67decmCBcjhg@mail.gmail.com>
On Thu, May 10, 2018 at 10:05:33PM -0700, Chen-Yu Tsai wrote:
> On Mon, May 7, 2018 at 5:44 AM, Paul Kocialkowski
> <paul.kocialkowski@bootlin.com> wrote:
> > This introduces platform-specific compatibles for the A13, A20 and A33
> > SRAM driver. No particular adaptation for these platforms is required at
> > this point, although this might become the case in the future.
> >
> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> > ---
> > drivers/soc/sunxi/sunxi_sram.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
> > index 74cb81f37bd6..43ebc3bd33f2 100644
> > --- a/drivers/soc/sunxi/sunxi_sram.c
> > +++ b/drivers/soc/sunxi/sunxi_sram.c
> > @@ -315,6 +315,9 @@ static int sunxi_sram_probe(struct platform_device *pdev)
> >
> > static const struct of_device_id sunxi_sram_dt_match[] = {
> > { .compatible = "allwinner,sun4i-a10-sram-controller" },
> > + { .compatible = "allwinner,sun5i-a13-sram-controller" },
> > + { .compatible = "allwinner,sun7i-a20-sram-controller" },
> > + { .compatible = "allwinner,sun8i-a33-sram-controller" },
>
> We should probably name these "system-controller". Maxime?
This would make sense yes, but we don't really need to add the A20 one
to the driver, it's exactly the same than the A10.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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* [PATCH v2 1/2] ARM: dts: vexpress: use standard gpio bindings for sys_{led, mci, flash}
From: Sudeep Holla @ 2018-05-11 10:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525884482-19855-1-git-send-email-sudeep.holla@arm.com>
Commit 2cff6dba57b7 ("ARM: dts: vexpress: fix node name unit-address presence warnings")
removed the unit address as there was no associated reg property in
these sysreg nodes.
Also the latest DTC throws warnings for character '_' in the node names.
Warning (node_name_chars_strict): /sysreg at 10000/sys_led: Character '_' not recommended in node name
Warning (node_name_chars_strict): /sysreg at 10000/sys_mci: Character '_' not recommended in node name
Warning (node_name_chars_strict): /sysreg at 10000/sys_flash: Character '_' not recommended in node name
The correct way to fix this as well as the original unit-address presence
warnings is to use the standard gpio controller binding and specify the
reg properties as per the hardware as it was before.
However note that Vexpress sysreg MFD driver will still continue to use
the hardcoded values for compatibility reasons.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 11 ++++++++---
arch/arm/boot/dts/vexpress-v2m.dtsi | 11 ++++++++---
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 7b8ff5b3b912..a8586a0b957d 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -76,21 +76,26 @@
v2m_sysreg: sysreg at 10000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- v2m_led_gpios: sys_led {
+ v2m_led_gpios: gpio at 8 {
compatible = "arm,vexpress-sysreg,sys_led";
+ reg = <0x008 4>;
gpio-controller;
#gpio-cells = <2>;
};
- v2m_mmc_gpios: sys_mci {
+ v2m_mmc_gpios: gpio at 48 {
compatible = "arm,vexpress-sysreg,sys_mci";
+ reg = <0x048 4>;
gpio-controller;
#gpio-cells = <2>;
};
- v2m_flash_gpios: sys_flash {
+ v2m_flash_gpios: gpio at 4c {
compatible = "arm,vexpress-sysreg,sys_flash";
+ reg = <0x04c 4>;
gpio-controller;
#gpio-cells = <2>;
};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index 9cd5e146abd5..37ecccebd937 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -76,21 +76,26 @@
v2m_sysreg: sysreg at 0 {
compatible = "arm,vexpress-sysreg";
reg = <0x00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- v2m_led_gpios: sys_led {
+ v2m_led_gpios: gpio at 8 {
compatible = "arm,vexpress-sysreg,sys_led";
+ reg = <0x008 4>;
gpio-controller;
#gpio-cells = <2>;
};
- v2m_mmc_gpios: sys_mci {
+ v2m_mmc_gpios: gpio at 48 {
compatible = "arm,vexpress-sysreg,sys_mci";
+ reg = <0x048 4>;
gpio-controller;
#gpio-cells = <2>;
};
- v2m_flash_gpios: sys_flash {
+ v2m_flash_gpios: gpio at 4c {
compatible = "arm,vexpress-sysreg,sys_flash";
+ reg = <0x04c 4>;
gpio-controller;
#gpio-cells = <2>;
};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/2] ARM: dts: vexpress: replace '_' with '-' in node names
From: Sudeep Holla @ 2018-05-11 10:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526034208-9690-1-git-send-email-sudeep.holla@arm.com>
The latest DTC throws warnings for character '_' in the node names.
Warning (node_name_chars_strict): /pmu_a15: Character '_' not recommended in node name
Warning (node_name_chars_strict): /pmu_a7: Character '_' not recommended in node name
The general recommendation is to use character '-' for all the node names.
This patch fixes the warnings following the recommendation.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
v1->v2:
- This patch is newly added in v2 and was missing earlier
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 65a874ea66be..ac6b90e9d806 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -204,7 +204,7 @@
<1 10 0xf08>;
};
- pmu_a15 {
+ pmu-a15 {
compatible = "arm,cortex-a15-pmu";
interrupts = <0 68 4>,
<0 69 4>;
@@ -212,7 +212,7 @@
<&cpu1>;
};
- pmu_a7 {
+ pmu-a7 {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 128 4>,
<0 129 4>,
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: arm: Add bindings for Mediatek MT8183 SoC Platform
From: Erin Lo @ 2018-05-11 10:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4a32814b-e905-74e8-ed5c-5e68f38faa28@gmail.com>
On Fri, 2018-05-11 at 10:33 +0200, Matthias Brugger wrote:
>
> On 05/11/2018 08:11 AM, Erin Lo wrote:
> > This adds dt-binding documentation for Mediatek MT8183.
> > Only include very basic items: cpu, gic and uart.
> >
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/arm/mediatek.txt | 4 ++++
> > .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 +
> > Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
> > 3 files changed, 6 insertions(+)
> >
>
> This touches different maintainers and the patches should go through their
> trees, so that no merge conflicts occur.
> I'm fine with take it through my tree but it's more work as we might need a
> stable branch that the other maintainers can merge. Apart I'd need the Acked-by
> from the maintainers.
>
> I'm fine with either way.
>
For prevent merge conflict and review convenient, I will split it into
different patches in next round.
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
> > index 7d21ab3..2754535 100644
> > --- a/Documentation/devicetree/bindings/arm/mediatek.txt
> > +++ b/Documentation/devicetree/bindings/arm/mediatek.txt
> > @@ -19,6 +19,7 @@ compatible: Must contain one of
> > "mediatek,mt8127"
> > "mediatek,mt8135"
> > "mediatek,mt8173"
> > + "mediatek,mt8183"
> >
> >
> > Supported boards:
> > @@ -73,3 +74,6 @@ Supported boards:
> > - MTK mt8173 tablet EVB:
> > Required root node properties:
> > - compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
> > +- Evaluation board for MT8183:
> > + Required root node properties:
> > + - compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> > index 07bf0b9..5ff48a8 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> > @@ -5,6 +5,7 @@ interrupt.
> >
> > Required properties:
> > - compatible: should be
> > + "mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
> > "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
> > "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
> > "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
> > diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> > index f73abff..6e6d168 100644
> > --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
> > +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> > @@ -15,6 +15,7 @@ Required properties:
> > * "mediatek,mt8127-uart" for MT8127 compatible UARTS
> > * "mediatek,mt8135-uart" for MT8135 compatible UARTS
> > * "mediatek,mt8173-uart" for MT8173 compatible UARTS
> > + * "mediatek,mt8183-uart" for MT8183 compatible UARTS
>
> If you add this compatible without a fallback that you will need an update in
> the driver. Is there really anything new in the serial console with regard to
> older devices?
>
> Regards,
> Matthias
>
No new function in MT8183..now
How about this...
"mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible
UARTS
Regards,
Erin
> > * "mediatek,mt6577-uart" for MT6577 and all of the above
> >
> > - reg: The base address of the UART register bank.
> >
^ permalink raw reply
* [PATCH v3 0/6] Driver for at91 usart in spi mode
From: Radu Pirea @ 2018-05-11 10:38 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This is the second version of driver. I added a mfd driver which by
default probes atmel_serial driver and if in dt is specified to probe
the spi driver, then the spi-at91-usart driver will be probed. The
compatible for atmel_serial is now the compatible for at91-usart mfd
driver and compatilbe for atmel_serial driver was changed in order to
keep the bindings for serial as they are.
Changes in v1:
- added spi-at91-usart driver
Changes in v2:
- added at91-usart mfd driver
- modified spi-at91-usart driver to work as mfd driver child
- modified atmel_serial driver to work as mfd driver child
Changes in v3:
- fixed spi slaves probing
Radu Pirea (6):
MAINTAINERS: add at91 usart mfd driver
mfd: at91-usart: added mfd driver for usart
MAINTAINERS: add at91 usart spi driver
dt-bindings: add binding for at91-usart in spi mode
spi: at91-usart: add driver for at91-usart as spi
tty/serial: atmel: changed the driver to work under at91-usart mfd
.../bindings/spi/microchip,at91-usart-spi.txt | 28 +
MAINTAINERS | 14 +
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/at91-usart.c | 75 +++
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-at91-usart.c | 544 ++++++++++++++++++
drivers/tty/serial/Kconfig | 1 +
drivers/tty/serial/atmel_serial.c | 29 +-
include/dt-bindings/mfd/at91-usart.h | 17 +
11 files changed, 715 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/microchip,at91-usart-spi.txt
create mode 100644 drivers/mfd/at91-usart.c
create mode 100644 drivers/spi/spi-at91-usart.c
create mode 100644 include/dt-bindings/mfd/at91-usart.h
--
2.17.0
^ permalink raw reply
* [PATCH v3 1/6] MAINTAINERS: add at91 usart mfd driver
From: Radu Pirea @ 2018-05-11 10:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511103822.31698-1-radu.pirea@microchip.com>
Added entry for at91 usart mfd driver.
Signed-off-by: Radu Pirea <radu.pirea@microchip.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8e2a2fddbd19..ca06c6f58299 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9192,6 +9192,13 @@ S: Supported
F: drivers/mtd/nand/raw/atmel/*
F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
+MICROCHIP AT91 USART MFD DRIVER
+M: Radu Pirea <radu.pirea@microchip.com>
+L: linux-kernel at vger.kernel.org
+S: Supported
+F: drivers/mfd/at91-usart.c
+F: include/dt-bindings/mfd/at91-usart.h
+
MICROCHIP KSZ SERIES ETHERNET SWITCH DRIVER
M: Woojung Huh <Woojung.Huh@microchip.com>
M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
--
2.17.0
^ permalink raw reply related
* [PATCH v3 2/6] mfd: at91-usart: added mfd driver for usart
From: Radu Pirea @ 2018-05-11 10:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511103822.31698-1-radu.pirea@microchip.com>
This mfd driver is just a wrapper over atmel_serial driver and
spi-at91-usart driver. Selection of one of the drivers is based on a
property from device tree. If the property is not specified, the default
driver is atmel_serial.
Signed-off-by: Radu Pirea <radu.pirea@microchip.com>
---
drivers/mfd/Kconfig | 10 ++++
drivers/mfd/Makefile | 1 +
drivers/mfd/at91-usart.c | 75 ++++++++++++++++++++++++++++
include/dt-bindings/mfd/at91-usart.h | 17 +++++++
4 files changed, 103 insertions(+)
create mode 100644 drivers/mfd/at91-usart.c
create mode 100644 include/dt-bindings/mfd/at91-usart.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b860eb5aa194..de99b79061b7 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -99,6 +99,16 @@ config MFD_AAT2870_CORE
additional drivers must be enabled in order to use the
functionality of the device.
+config MFD_AT91_USART
+ tristate "AT91 USART Driver"
+ select MFD_CORE
+ depends on OF
+ help
+ Select this to get support for AT91 USART IP. This is a wrapper
+ over at91-usart-serial driver and usart-spi-driver. Only one function
+ can be used at a time. The choice is done at boot time by the probe
+ function of this MFD driver according to a device tree property.
+
config MFD_ATMEL_FLEXCOM
tristate "Atmel Flexcom (Flexible Serial Communication Unit)"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index d9d2cf0d32ef..db1332aa96db 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -185,6 +185,7 @@ obj-$(CONFIG_MFD_SPMI_PMIC) += qcom-spmi-pmic.o
obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o
obj-$(CONFIG_MFD_TPS65090) += tps65090.o
obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
+obj-$(CONFIG_MFD_AT91_USART) += at91-usart.o
obj-$(CONFIG_MFD_ATMEL_FLEXCOM) += atmel-flexcom.o
obj-$(CONFIG_MFD_ATMEL_HLCDC) += atmel-hlcdc.o
obj-$(CONFIG_MFD_ATMEL_SMC) += atmel-smc.o
diff --git a/drivers/mfd/at91-usart.c b/drivers/mfd/at91-usart.c
new file mode 100644
index 000000000000..87094463f8f4
--- /dev/null
+++ b/drivers/mfd/at91-usart.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for AT91 USART
+ *
+ * Copyright (C) 2018 Microchip Technology
+ *
+ * Author: Radu Pirea <radu.pirea@microchip.com>
+ *
+ */
+
+#include <dt-bindings/mfd/at91-usart.h>
+
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mfd/core.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+static struct mfd_cell at91_usart_spi_subdev = {
+ .name = "at91_usart_spi",
+ .of_compatible = "microchip,at91sam9g45-usart-spi",
+ };
+
+static struct mfd_cell at91_usart_serial_subdev = {
+ .name = "atmel_usart_serial",
+ .of_compatible = "atmel,at91rm9200-usart-serial",
+ };
+
+static int at91_usart_mode_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct mfd_cell cell;
+ u32 opmode;
+ int err;
+
+ err = of_property_read_u32(np, "at91,usart-mode", &opmode);
+
+ switch (opmode) {
+ case AT91_USART_MODE_SPI:
+ cell = at91_usart_spi_subdev;
+ break;
+ case AT91_USART_MODE_SERIAL:
+ default:
+ cell = at91_usart_serial_subdev;
+ }
+
+ return mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, &cell, 1,
+ NULL, 0, NULL);
+}
+
+static const struct of_device_id at91_usart_mode_of_match[] = {
+ { .compatible = "atmel,at91rm9200-usart" },
+ { .compatible = "atmel,at91sam9260-usart" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, at91_flexcom_of_match);
+
+static struct platform_driver at91_usart_mfd = {
+ .probe = at91_usart_mode_probe,
+ .driver = {
+ .name = "at91_usart_mode",
+ .of_match_table = at91_usart_mode_of_match,
+ },
+};
+
+module_platform_driver(at91_usart_mfd);
+
+MODULE_AUTHOR("Radu Pirea <radu.pirea@microchip.com>");
+MODULE_DESCRIPTION("AT91 USART MFD driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/dt-bindings/mfd/at91-usart.h b/include/dt-bindings/mfd/at91-usart.h
new file mode 100644
index 000000000000..ac811628a42d
--- /dev/null
+++ b/include/dt-bindings/mfd/at91-usart.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides macros for AT91 USART DT bindings.
+ *
+ * Copyright (C) 2018 Microchip Technology
+ *
+ * Author: Radu Pirea <radu.pirea@microchip.com>
+ *
+ */
+
+#ifndef __DT_BINDINGS_AT91_USART_H__
+#define __DT_BINDINGS_AT91_USART_H__
+
+#define AT91_USART_MODE_SERIAL 1
+#define AT91_USART_MODE_SPI 2
+
+#endif /* __DT_BINDINGS_AT91_USART_H__ */
--
2.17.0
^ permalink raw reply related
* [PATCH v3 3/6] MAINTAINERS: add at91 usart spi driver
From: Radu Pirea @ 2018-05-11 10:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511103822.31698-1-radu.pirea@microchip.com>
Added entry for at91 usart mfd driver.
Signed-off-by: Radu Pirea <radu.pirea@microchip.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ca06c6f58299..9243b9007966 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9199,6 +9199,13 @@ S: Supported
F: drivers/mfd/at91-usart.c
F: include/dt-bindings/mfd/at91-usart.h
+MICROCHIP AT91 USART SPI DRIVER
+M: Radu Pirea <radu.pirea@microchip.com>
+L: linux-spi at vger.kernel.org
+S: Supported
+F: drivers/spi/spi-at91-usart.c
+F: Documentation/devicetree/bindings/spi/microchip,at91-usart-spi.txt
+
MICROCHIP KSZ SERIES ETHERNET SWITCH DRIVER
M: Woojung Huh <Woojung.Huh@microchip.com>
M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
--
2.17.0
^ permalink raw reply related
* [PATCH v3 4/6] dt-bindings: add binding for at91-usart in spi mode
From: Radu Pirea @ 2018-05-11 10:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511103822.31698-1-radu.pirea@microchip.com>
These are bindings for at91-usart IP in spi spi mode. There is no support for
internal chip select. Only kind of chip selects available are gpio chip
selects.
Signed-off-by: Radu Pirea <radu.pirea@microchip.com>
---
.../bindings/spi/microchip,at91-usart-spi.txt | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/microchip,at91-usart-spi.txt
diff --git a/Documentation/devicetree/bindings/spi/microchip,at91-usart-spi.txt b/Documentation/devicetree/bindings/spi/microchip,at91-usart-spi.txt
new file mode 100644
index 000000000000..b68a3bec4121
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,at91-usart-spi.txt
@@ -0,0 +1,28 @@
+* Universal Synchronous Asynchronous Receiver/Transmitter (USART) in SPI mode
+
+Required properties:
+- #size-cells : Must be <0>
+- #address-cells : Must be <1>
+- compatible: Should be "atmel,at91rm9200-usart" or "atmel,at91sam9260-usart"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt
+- clocks: phandles to input clocks.
+- clock-names: tuple listing input clock names.
+ Required elements: "usart"
+- cs-gpios: chipselects (internal cs not supported)
+- at91,usart-mode: AT91_USART_MODE_SPI (found in dt-bindings/mfd/at91-usart.h)
+
+Example:
+ #include <dt-bindings/mfd/at91-usart.h>
+
+ spi0: spi at f001c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart";
+ at91,usart-mode = <AT91_USART_MODE_SPI>;
+ reg = <0xf001c000 0x100>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usart0_clk>;
+ clock-names = "usart";
+ cs-gpios = <&pioB 3 0>;
+ };
--
2.17.0
^ permalink raw reply related
* [PATCH v3 5/6] spi: at91-usart: add driver for at91-usart as spi
From: Radu Pirea @ 2018-05-11 10:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511103822.31698-1-radu.pirea@microchip.com>
This is the driver for at91-usart in spi mode. The USART IP can be configured
to work in many modes and one of them is SPI.
The driver was tested on sama5d3-xplained and sama5d4-xplained boards with
enc28j60 ethernet controller as slave.
Signed-off-by: Radu Pirea <radu.pirea@microchip.com>
---
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-at91-usart.c | 544 +++++++++++++++++++++++++++++++++++
3 files changed, 554 insertions(+)
create mode 100644 drivers/spi/spi-at91-usart.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 6fb0347a24f2..c675e6b8dd5a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -77,6 +77,15 @@ config SPI_ATMEL
This selects a driver for the Atmel SPI Controller, present on
many AT91 (ARM) chips.
+config SPI_AT91_USART
+ tristate "Atmel USART Controller as SPI"
+ depends on HAS_DMA
+ depends on (ARCH_AT91 || COMPILE_TEST)
+ select MFD_AT91_USART
+ help
+ This selects a driver for the AT91 USART Controller as SPI Master,
+ present on AT91 and SAMA5 SoC series.
+
config SPI_AU1550
tristate "Au1550/Au1200/Au1300 SPI Controller"
depends on MIPS_ALCHEMY
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 34c5f2832ddf..fb6cb42f4eaa 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
+obj-$(CONFIG_SPI_AT91_USART) += spi-at91-usart.o
obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
obj-$(CONFIG_SPI_AXI_SPI_ENGINE) += spi-axi-spi-engine.o
diff --git a/drivers/spi/spi-at91-usart.c b/drivers/spi/spi-at91-usart.c
new file mode 100644
index 000000000000..79a59759d2ee
--- /dev/null
+++ b/drivers/spi/spi-at91-usart.c
@@ -0,0 +1,544 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for AT91 USART Controllers as SPI
+ *
+ * Copyright (C) 2018 Microchip Technology Inc.
+ * Author: Radu Pirea <radu.pirea@microchip.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+
+#include <linux/pinctrl/consumer.h>
+
+#include <linux/spi/spi.h>
+
+#define US_CR 0x00
+#define US_MR 0x04
+#define US_IER 0x08
+#define US_IDR 0x0C
+#define US_CSR 0x14
+#define US_RHR 0x18
+#define US_THR 0x1C
+#define US_BRGR 0x20
+#define US_VERSION 0xFC
+
+#define US_CR_RSTRX BIT(2)
+#define US_CR_RSTTX BIT(3)
+#define US_CR_RXEN BIT(4)
+#define US_CR_RXDIS BIT(5)
+#define US_CR_TXEN BIT(6)
+#define US_CR_TXDIS BIT(7)
+
+#define US_MR_SPI_MASTER 0x0E
+#define US_MR_CHRL GENMASK(7, 6)
+#define US_MR_CPHA BIT(8)
+#define US_MR_CPOL BIT(16)
+#define US_MR_CLKO BIT(18)
+#define US_MR_WRDBT BIT(20)
+#define US_MR_LOOP BIT(15)
+
+#define US_IR_RXRDY BIT(0)
+#define US_IR_TXRDY BIT(1)
+#define US_IR_OVRE BIT(5)
+
+#define US_BRGR_SIZE BIT(16)
+
+#define US_MIN_CLK_DIV 0x06
+#define US_MAX_CLK_DIV BIT(16)
+
+#define US_DUMMY_TX 0xFF
+
+/* Register access macros */
+#define spi_readl(port, reg) \
+ readl_relaxed((port)->regs + US_##reg)
+#define spi_writel(port, reg, value) \
+ writel_relaxed((value), (port)->regs + US_##reg)
+
+#define spi_readb(port, reg) \
+ readb_relaxed((port)->regs + US_##reg)
+#define spi_writeb(port, reg, value) \
+ writeb_relaxed((value), (port)->regs + US_##reg)
+
+struct at91_usart_spi {
+ struct spi_transfer *current_transfer;
+ void __iomem *regs;
+ struct device *dev;
+ struct clk *clk;
+
+ /*used in interrupt to protect data reading*/
+ spinlock_t lock;
+
+ int irq;
+ unsigned int current_tx_remaining_bytes;
+ unsigned int current_rx_remaining_bytes;
+ int done_status;
+
+ u32 spi_clk;
+ u32 status;
+
+ bool xfer_failed;
+ bool keep_cs;
+ bool cs_active;
+};
+
+struct at91_usart_spi_device {
+ struct gpio_desc *npcs_pin;
+ u32 mr;
+};
+
+static inline u32 at91_usart_spi_tx_ready(struct at91_usart_spi *aus)
+{
+ return aus->status & US_IR_TXRDY;
+}
+
+static inline u32 at91_usart_spi_rx_ready(struct at91_usart_spi *aus)
+{
+ return aus->status & US_IR_RXRDY;
+}
+
+static inline u32 at91_usart_spi_check_overrun(struct at91_usart_spi *aus)
+{
+ return aus->status & US_IR_OVRE;
+}
+
+static inline u32 at91_usart_spi_read_status(struct at91_usart_spi *aus)
+{
+ aus->status = spi_readl(aus, CSR);
+ return aus->status;
+}
+
+static inline void at91_usart_spi_tx(struct at91_usart_spi *aus)
+{
+ unsigned int len = aus->current_transfer->len;
+ unsigned int remaining = aus->current_tx_remaining_bytes;
+ const u8 *tx_buf = aus->current_transfer->tx_buf;
+
+ if (tx_buf && remaining) {
+ if (at91_usart_spi_tx_ready(aus))
+ spi_writel(aus, THR, tx_buf[len - remaining]);
+ aus->current_tx_remaining_bytes--;
+ } else {
+ if (at91_usart_spi_tx_ready(aus))
+ spi_writel(aus, THR, US_DUMMY_TX);
+ }
+}
+
+static inline void at91_usart_spi_rx(struct at91_usart_spi *aus)
+{
+ int len = aus->current_transfer->len;
+ int remaining = aus->current_rx_remaining_bytes;
+ u8 *rx_buf = aus->current_transfer->rx_buf;
+
+ if (aus->current_rx_remaining_bytes) {
+ rx_buf[len - remaining] = spi_readb(aus, RHR);
+ aus->current_rx_remaining_bytes--;
+ } else {
+ spi_readb(aus, RHR);
+ }
+}
+
+static inline void at91_usart_spi_cs_activate(struct spi_device *spi)
+{
+ struct at91_usart_spi_device *ausd = spi->controller_state;
+ struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
+ u32 active = spi->mode & SPI_CS_HIGH;
+
+ gpiod_set_value(ausd->npcs_pin, active);
+ aus->cs_active = true;
+}
+
+static inline void at91_usart_spi_cs_deactivate(struct spi_device *spi)
+{
+ struct at91_usart_spi_device *ausd = spi->controller_state;
+ struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
+ u32 active = spi->mode & SPI_CS_HIGH;
+
+ gpiod_set_value(ausd->npcs_pin, !active);
+ aus->cs_active = false;
+}
+
+static inline void at91_usart_spi_set_mode_register(struct spi_device *spi)
+{
+ struct at91_usart_spi_device *ausd = spi->controller_state;
+ struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
+
+ spi_writel(aus, MR, ausd->mr);
+}
+
+static inline void
+at91_usart_spi_enable_irq_and_hw(struct at91_usart_spi *aus)
+{
+ spi_writel(aus, CR, US_CR_RXEN | US_CR_TXEN);
+ spi_writel(aus, IER, US_IR_OVRE | US_IR_RXRDY);
+}
+
+static inline void
+at91_usart_spi_disable_irq_and_hw(struct at91_usart_spi *aus)
+{
+ spi_writel(aus, CR, US_CR_RXDIS | US_CR_TXDIS |
+ US_CR_RSTRX | US_CR_RSTTX);
+ spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY);
+}
+
+static inline void
+at91_usart_spi_set_xfer_speed(struct at91_usart_spi *aus,
+ struct spi_transfer *xfer)
+{
+ spi_writel(aus, BRGR,
+ DIV_ROUND_UP(aus->spi_clk, xfer->speed_hz));
+}
+
+static irqreturn_t at91_usart_spi_interrupt(int irq, void *dev_id)
+{
+ struct spi_controller *controller = dev_id;
+ struct at91_usart_spi *aus = spi_master_get_devdata(controller);
+
+ spin_lock(&aus->lock);
+
+ at91_usart_spi_read_status(aus);
+
+ if (at91_usart_spi_check_overrun(aus)) {
+ aus->xfer_failed = true;
+ aus->done_status = -EIO;
+ spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY);
+ spin_unlock(&aus->lock);
+ return IRQ_HANDLED;
+ }
+
+ if (at91_usart_spi_rx_ready(aus)) {
+ at91_usart_spi_rx(aus);
+ spin_unlock(&aus->lock);
+ return IRQ_HANDLED;
+ }
+ spin_unlock(&aus->lock);
+
+ return IRQ_NONE;
+}
+
+static int at91_usart_spi_setup(struct spi_device *spi)
+{
+ struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
+ struct at91_usart_spi_device *ausd = spi->controller_state;
+ struct gpio_desc *npcs_pin;
+ unsigned int mr = spi_readl(aus, MR);
+ u8 bits = spi->bits_per_word;
+
+ if (bits != 8) {
+ dev_dbg(&spi->dev, "Only 8 bits per word are supported\n");
+ return -EINVAL;
+ }
+
+ if (spi->mode & SPI_CPOL)
+ mr |= US_MR_CPOL;
+ else
+ mr &= ~US_MR_CPOL;
+
+ if (spi->mode & SPI_CPHA)
+ mr |= US_MR_CPHA;
+ else
+ mr &= ~US_MR_CPHA;
+
+ if (spi->mode & SPI_LOOP)
+ mr |= US_MR_LOOP;
+ else
+ mr &= ~US_MR_LOOP;
+
+ if (!ausd) {
+ if (gpio_is_valid(spi->cs_gpio)) {
+ npcs_pin = gpio_to_desc(spi->cs_gpio);
+ } else {
+ dev_dbg(&spi->dev, "Invalid chip select\n");
+ return -EINVAL;
+ }
+
+ ausd = kzalloc(sizeof(*ausd), GFP_KERNEL);
+ if (!ausd)
+ return -ENOMEM;
+ gpiod_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
+
+ ausd->npcs_pin = npcs_pin;
+ spi->controller_state = ausd;
+ }
+
+ ausd->mr = mr;
+
+ dev_dbg(&spi->dev,
+ "setup: bpw %u mode 0x%x -> mr %d %08x\n",
+ bits, spi->mode, spi->chip_select, mr);
+
+ return 0;
+}
+
+static int at91_usart_spi_one_transfer(struct spi_controller *controller,
+ struct spi_message *msg,
+ struct spi_transfer *xfer)
+{
+ struct at91_usart_spi *aus = spi_master_get_devdata(controller);
+ struct spi_device *spi = msg->spi;
+ const u8 *tx_buf = xfer->tx_buf;
+ u8 *rx_buf = xfer->rx_buf;
+
+ if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
+ dev_dbg(&spi->dev, "missing rx and tx buf\n");
+ return -EINVAL;
+ }
+
+ at91_usart_spi_set_xfer_speed(aus, xfer);
+ aus->done_status = 0;
+ aus->xfer_failed = false;
+ aus->current_transfer = xfer;
+ aus->current_tx_remaining_bytes = xfer->len;
+ aus->current_rx_remaining_bytes = xfer->len;
+ if (!tx_buf)
+ aus->current_tx_remaining_bytes = 0;
+ if (!rx_buf)
+ aus->current_rx_remaining_bytes = 0;
+
+ while ((aus->current_tx_remaining_bytes ||
+ aus->current_rx_remaining_bytes) && !aus->xfer_failed) {
+ at91_usart_spi_read_status(aus);
+ at91_usart_spi_tx(aus);
+ cpu_relax();
+ }
+ if (aus->xfer_failed) {
+ dev_err(aus->dev, "Overrun!\n");
+ return -EIO;
+ }
+
+ if (xfer->delay_usecs)
+ udelay(xfer->delay_usecs);
+
+ if (xfer->cs_change) {
+ if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
+ aus->keep_cs = true;
+ } else {
+ aus->cs_active = !aus->cs_active;
+ if (aus->cs_active)
+ at91_usart_spi_cs_activate(spi);
+ else
+ at91_usart_spi_cs_deactivate(spi);
+ }
+ }
+
+ return 0;
+}
+
+static int
+at91_usart_spi_transfer_one_message(struct spi_controller *controller,
+ struct spi_message *msg)
+{
+ struct at91_usart_spi *aus = spi_master_get_devdata(controller);
+ struct spi_transfer *xfer;
+ struct spi_device *spi = msg->spi;
+ int ret;
+
+ dev_dbg(&spi->dev, "new message %p submitted for %s\n",
+ msg, dev_name(&spi->dev));
+ at91_usart_spi_enable_irq_and_hw(aus);
+ at91_usart_spi_set_mode_register(spi);
+ at91_usart_spi_cs_activate(spi);
+
+ aus->keep_cs = false;
+
+ msg->status = 0;
+ msg->actual_length = 0;
+
+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
+ ret = at91_usart_spi_one_transfer(controller, msg, xfer);
+ if (ret)
+ goto msg_done;
+ }
+
+msg_done:
+
+ if (!aus->keep_cs)
+ at91_usart_spi_cs_deactivate(spi);
+
+ at91_usart_spi_disable_irq_and_hw(aus);
+
+ msg->status = aus->done_status;
+ spi_finalize_current_message(spi->master);
+
+ return ret;
+}
+
+static void at91_usart_spi_cleanup(struct spi_device *spi)
+{
+ struct at91_usart_spi_device *ausd = spi->controller_state;
+
+ if (!ausd)
+ return;
+
+ spi->controller_state = NULL;
+ kfree(ausd);
+}
+
+static int at91_usart_spi_gpio_cs(struct platform_device *pdev)
+{
+ struct spi_controller *controller = platform_get_drvdata(pdev);
+ struct device_node *np = controller->dev.parent->of_node;
+ struct gpio_desc *cs_gpio;
+ int nb;
+ int i;
+
+ if (!np)
+ return 0;
+
+ nb = of_gpio_named_count(np, "cs-gpios");
+ for (i = 0; i < nb; i++) {
+ cs_gpio = devm_gpiod_get_from_of_node(&pdev->dev,
+ pdev->dev.parent->of_node,
+ "cs-gpios",
+ i, GPIOD_OUT_HIGH,
+ dev_name(&pdev->dev));
+ if (IS_ERR(cs_gpio))
+ return PTR_ERR(cs_gpio);
+ }
+
+ controller->num_chipselect = nb;
+
+ return 0;
+}
+
+static void at91_usart_spi_init(struct at91_usart_spi *aus)
+{
+ spi_writel(aus, MR, US_MR_SPI_MASTER | US_MR_CHRL | US_MR_CLKO |
+ US_MR_WRDBT);
+ spi_writel(aus, CR, US_CR_RXDIS | US_CR_TXDIS | US_CR_RSTRX |
+ US_CR_RSTTX);
+}
+
+static int at91_usart_spi_probe(struct platform_device *pdev)
+{
+ struct resource *regs;
+ struct spi_controller *controller;
+ struct at91_usart_spi *aus;
+ struct clk *clk;
+ int irq;
+ int ret;
+
+ regs = platform_get_resource(to_platform_device(pdev->dev.parent),
+ IORESOURCE_MEM, 0);
+ if (!regs)
+ return -ENXIO;
+
+ irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
+ if (irq < 0)
+ return irq;
+
+ clk = devm_clk_get(pdev->dev.parent, "usart");
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ ret = -ENOMEM;
+ controller = spi_alloc_master(&pdev->dev, sizeof(*aus));
+ if (!controller)
+ goto at91_usart_spi_probe_fail;
+
+ controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
+ controller->dev.of_node = pdev->dev.parent->of_node;
+ controller->bits_per_word_mask = SPI_BPW_MASK(8);
+ controller->num_chipselect = 0;
+ controller->setup = at91_usart_spi_setup;
+ controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
+ controller->transfer_one_message = at91_usart_spi_transfer_one_message;
+ controller->cleanup = at91_usart_spi_cleanup;
+ controller->max_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
+ US_MIN_CLK_DIV);
+ controller->min_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
+ US_MAX_CLK_DIV);
+ platform_set_drvdata(pdev, controller);
+
+ aus = spi_master_get_devdata(controller);
+
+ aus->dev = &pdev->dev;
+ aus->regs = devm_ioremap_resource(&pdev->dev, regs);
+ if (IS_ERR(aus->regs)) {
+ ret = PTR_ERR(aus->regs);
+ goto at91_usart_spi_probe_fail;
+ }
+
+ aus->irq = irq;
+ aus->clk = clk;
+
+ ret = at91_usart_spi_gpio_cs(pdev);
+ if (ret)
+ goto at91_usart_spi_probe_fail;
+
+ ret = devm_request_irq(&pdev->dev, irq, at91_usart_spi_interrupt, 0,
+ dev_name(&pdev->dev), controller);
+ if (ret)
+ goto at91_usart_spi_probe_fail;
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ goto at91_usart_spi_probe_fail;
+
+ aus->spi_clk = clk_get_rate(clk);
+ at91_usart_spi_init(aus);
+
+ spin_lock_init(&aus->lock);
+ ret = devm_spi_register_master(&pdev->dev, controller);
+ if (ret)
+ goto fail_register_master;
+
+ dev_info(&pdev->dev,
+ "Atmel USART SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
+ spi_readl(aus, VERSION),
+ (unsigned long)regs->start, irq);
+
+ return 0;
+
+fail_register_master:
+ clk_disable_unprepare(clk);
+at91_usart_spi_probe_fail:
+ spi_master_put(controller);
+ return ret;
+}
+
+static int at91_usart_spi_remove(struct platform_device *pdev)
+{
+ struct spi_master *master = platform_get_drvdata(pdev);
+ struct at91_usart_spi *aus = spi_master_get_devdata(master);
+
+ clk_disable_unprepare(aus->clk);
+
+ return 0;
+}
+
+static const struct of_device_id at91_usart_spi_dt_ids[] = {
+ { .compatible = "microchip,sama5d3-usart-spi"},
+ { .compatible = "microchip,sama5d4-usart-spi"},
+ { .compatible = "microchip,at91sam9g45-usart-spi"},
+ { /* sentinel */}
+};
+
+MODULE_DEVICE_TABLE(of, at91_usart_spi_dt_ids);
+
+static struct platform_driver at91_usart_spi_driver = {
+ .driver = {
+ .name = "at91_usart_spi",
+ .of_match_table = of_match_ptr(at91_usart_spi_dt_ids),
+ },
+ .probe = at91_usart_spi_probe,
+ .remove = at91_usart_spi_remove, };
+module_platform_driver(at91_usart_spi_driver);
+
+MODULE_DESCRIPTION("Microchip AT91 USART SPI Controller driver");
+MODULE_AUTHOR("Radu Pirea <radu.pirea@microchip.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:at91_usart_spi");
--
2.17.0
^ permalink raw reply related
* [PATCH v3 6/6] tty/serial: atmel: changed the driver to work under at91-usart mfd
From: Radu Pirea @ 2018-05-11 10:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511103822.31698-1-radu.pirea@microchip.com>
This patch modifies the place where resources and device tree properties
are searched.
Signed-off-by: Radu Pirea <radu.pirea@microchip.com>
---
drivers/tty/serial/Kconfig | 1 +
drivers/tty/serial/atmel_serial.c | 29 +++++++++++++++--------------
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 3682fd3e960c..25e55332f8b1 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -119,6 +119,7 @@ config SERIAL_ATMEL
depends on ARCH_AT91 || COMPILE_TEST
select SERIAL_CORE
select SERIAL_MCTRL_GPIO if GPIOLIB
+ select MFD_AT91_USART
help
This enables the driver for the on-chip UARTs of the Atmel
AT91 processors.
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index df46a9e88c34..6b4494352853 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -193,8 +193,8 @@ static struct console atmel_console;
#if defined(CONFIG_OF)
static const struct of_device_id atmel_serial_dt_ids[] = {
- { .compatible = "atmel,at91rm9200-usart" },
- { .compatible = "atmel,at91sam9260-usart" },
+ { .compatible = "atmel,at91rm9200-usart-serial" },
+ { .compatible = "atmel,at91sam9260-usart-serial" },
{ /* sentinel */ }
};
#endif
@@ -1631,7 +1631,7 @@ static void atmel_tasklet_tx_func(unsigned long data)
static void atmel_init_property(struct atmel_uart_port *atmel_port,
struct platform_device *pdev)
{
- struct device_node *np = pdev->dev.of_node;
+ struct device_node *np = pdev->dev.parent->of_node;
/* DMA/PDC usage specification */
if (of_property_read_bool(np, "atmel,use-dma-rx")) {
@@ -2223,7 +2223,8 @@ static const char *atmel_type(struct uart_port *port)
static void atmel_release_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
- int size = pdev->resource[0].end - pdev->resource[0].start + 1;
+ int size = to_platform_device(pdev->dev.parent)->resource[0].end -
+ to_platform_device(pdev->dev.parent)->resource[0].start + 1;
release_mem_region(port->mapbase, size);
@@ -2239,7 +2240,8 @@ static void atmel_release_port(struct uart_port *port)
static int atmel_request_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
- int size = pdev->resource[0].end - pdev->resource[0].start + 1;
+ int size = to_platform_device(pdev->dev.parent)->resource[0].end -
+ to_platform_device(pdev->dev.parent)->resource[0].start + 1;
if (!request_mem_region(port->mapbase, size, "atmel_serial"))
return -EBUSY;
@@ -2345,23 +2347,23 @@ static int atmel_init_port(struct atmel_uart_port *atmel_port,
atmel_init_property(atmel_port, pdev);
atmel_set_ops(port);
- uart_get_rs485_mode(&pdev->dev, &port->rs485);
+ uart_get_rs485_mode(pdev->dev.parent, &port->rs485);
port->iotype = UPIO_MEM;
port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
port->ops = &atmel_pops;
port->fifosize = 1;
port->dev = &pdev->dev;
- port->mapbase = pdev->resource[0].start;
- port->irq = pdev->resource[1].start;
+ port->mapbase = to_platform_device(pdev->dev.parent)->resource[0].start;
+ port->irq = to_platform_device(pdev->dev.parent)->resource[1].start;
port->rs485_config = atmel_config_rs485;
- port->membase = NULL;
+ port->membase = NULL;
memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
/* for console, the clock could already be configured */
if (!atmel_port->clk) {
- atmel_port->clk = clk_get(&pdev->dev, "usart");
+ atmel_port->clk = clk_get(pdev->dev.parent, "usart");
if (IS_ERR(atmel_port->clk)) {
ret = PTR_ERR(atmel_port->clk);
atmel_port->clk = NULL;
@@ -2656,7 +2658,7 @@ static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
atmel_port->rts_low = 0;
atmel_port->rts_high = 0;
- if (of_property_read_u32(pdev->dev.of_node,
+ if (of_property_read_u32(pdev->dev.parent->of_node,
"atmel,fifo-size",
&atmel_port->fifo_size))
return;
@@ -2694,11 +2696,10 @@ static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
static int atmel_serial_probe(struct platform_device *pdev)
{
struct atmel_uart_port *atmel_port;
- struct device_node *np = pdev->dev.of_node;
+ struct device_node *np = pdev->dev.parent->of_node;
void *data;
int ret = -ENODEV;
bool rs485_enabled;
-
BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
ret = of_alias_get_id(np, "serial");
@@ -2845,7 +2846,7 @@ static struct platform_driver atmel_serial_driver = {
.suspend = atmel_serial_suspend,
.resume = atmel_serial_resume,
.driver = {
- .name = "atmel_usart",
+ .name = "atmel_usart_serial",
.of_match_table = of_match_ptr(atmel_serial_dt_ids),
},
};
--
2.17.0
^ permalink raw reply related
* [PATCH] armpmu: broadcast overflow irq on multi-core system having one muxed SPI for PMU.
From: Mark Rutland @ 2018-05-11 10:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <010c01d3e8b5$8839a480$98aced80$@lge.com>
On Fri, May 11, 2018 at 08:20:49AM +0900, ????? wrote:
> Thank you for the reply.
>
> > -----Original Message-----
> > From: Mark Rutland [mailto:mark.rutland at arm.com]
> > Sent: Thursday, May 10, 2018 7:21 PM
> > To: Hoeun Ryu <hoeun.ryu@lge.com.com>
> > Cc: Will Deacon <will.deacon@arm.com>; Hoeun Ryu <hoeun.ryu@lge.com>;
> > linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org
> > Subject: Re: [PATCH] armpmu: broadcast overflow irq on multi-core system
> > having one muxed SPI for PMU.
> > Muxing the PMU IRQs is a really broken system design, and there's no good
> > way of supporting it.
> > What we should do for such systems is:
> >
> > * Add a flag to the DT to describe that the IRQs are muxed, as this
> > cannot be probed.
> >
> > * Add hrtimer code to periodically update the counters, to avoid
> > overflow (e.g. as we do in the l2x0 PMU).
> >
> > * Reject sampling for such systems, as this cannot be done reliably or
> > efficiently.
> >
> > NAK to broadcasting the IRQ -- there are a number of issues with the
> > general approach.
>
> The second solution would be good if sampling is necessary even like those
> systems.
Please note that I mean *all* of the above. There would be no sampling
on systems with muxed PMU IRQs, since there's no correlation between
overflow events and the hrtimer interrupts -- the results of sampling
would be misleading.
> Actually I'm working on FIQ available ARM32 system and trying to enable the
> hard lockup detector by routing the PMU IRQ to FIQ.
> Because of that, I really need the interrupt event if it is a muxed SPI,
> beside I also need to make an dedicated IPI FIQ to broadcast the IRQ in
> this approach.
> What would you do if you were in the same situation ?
I don't think that this can work with a muxed IRQ, sorry.
It would be better to use some kind of timer.
[...]
> > Futher, If you ever encounter a case where you need to avoid preemption
> > across enabling IRQs, preemption must be disabled *before* enabling IRQs.
>
> Ah, OK.
> Enabling IRQs can cause scheduling tasks in the end of exception or other
> scheduling points, right ?
Yes. If an IRQ was taken *between* enabling IRQs and disabling
preemption, preemption may occur as part of the exception return.
Thanks,
Mark.
^ permalink raw reply
* [PATCH 2/2] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Erin Lo @ 2018-05-11 10:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <860cba8a-3af8-31d6-ec3f-81706d2d998b@gmail.com>
On Fri, 2018-05-11 at 10:36 +0200, Matthias Brugger wrote:
>
> On 05/11/2018 08:11 AM, Erin Lo wrote:
> > From: Ben Ho <Ben.Ho@mediatek.com>
> >
> > Add basic chip support for Mediatek 8183
> >
> > Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++++
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 178 ++++++++++++++++++++++++++++
> > 3 files changed, 210 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> > index ac17f60..2836261 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > new file mode 100644
> > index 0000000..9a3d6b7
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > @@ -0,0 +1,31 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: Ben Ho <ben.ho@mediatek.com>
> > + * Erin Lo <erin.lo@mediatek.com>
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt8183.dtsi"
> > +
> > +/ {
> > + model = "MediaTek MT8183 evaluation board";
> > + compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + memory at 40000000 {
> > + device_type = "memory";
> > + reg = <0 0x40000000 0 0x80000000>;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:921600n8";
> > + };
> > +};
> > +
> > +&uart0 {
> > + status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > new file mode 100644
> > index 0000000..8564a26
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -0,0 +1,178 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: Ben Ho <ben.ho@mediatek.com>
> > + * Erin Lo <erin.lo@mediatek.com>
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > + compatible = "mediatek,mt8183";
> > + interrupt-parent = <&sysirq>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > + core1 {
> > + cpu = <&cpu1>;
> > + };
> > + core2 {
> > + cpu = <&cpu2>;
> > + };
> > + core3 {
> > + cpu = <&cpu3>;
> > + };
> > + };
> > +
> > + cluster1 {
> > + core0 {
> > + cpu = <&cpu4>;
> > + };
> > + core1 {
> > + cpu = <&cpu5>;
> > + };
> > + core2 {
> > + cpu = <&cpu6>;
> > + };
> > + core3 {
> > + cpu = <&cpu7>;
> > + };
> > + };
> > + };
> > +
> > + cpu0: cpu at 000 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x000>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu1: cpu at 001 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x001>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu2: cpu at 002 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x002>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu3: cpu at 003 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x003>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu4: cpu at 100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a73";
> > + reg = <0x100>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu5: cpu at 101 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a73";
> > + reg = <0x101>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu6: cpu at 102 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a73";
> > + reg = <0x102>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu7: cpu at 103 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a73";
> > + reg = <0x103>;
> > + enable-method = "psci";
> > + };
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
> > + uart_clk: dummy26m {
> > + compatible = "fixed-clock";
> > + clock-frequency = <26000000>;
> > + #clock-cells = <0>;
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > + };
> > +
> > + gic: interrupt-controller at 0c000000 {
> > + compatible = "arm,gic-v3";
> > + #interrupt-cells = <3>;
> > + interrupt-parent = <&gic>;
> > + interrupt-controller;
> > + reg = <0 0x0c000000 0 0x40000>, // CID
> > + <0 0x0c100000 0 0x200000>; // CIR
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + sysirq: intpol-controller at 0c530a80 {
> > + compatible = "mediatek,mt8183-sysirq",
> > + "mediatek,mt6577-sysirq";
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + interrupt-parent = <&gic>;
> > + reg = <0 0x0c530a80 0 0x50>;
> > + };
> > +
> > + uart0: serial at 11002000 {
> > + compatible = "mediatek,mt8183-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x1000>;
> > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&uart_clk>, <&uart_clk>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial at 11003000 {
> > + compatible = "mediatek,mt8183-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11003000 0 0x1000>;
> > + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&uart_clk>, <&uart_clk>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial at 11004000 {
> > + compatible = "mediatek,mt8183-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11004000 0 0x1000>;
> > + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&uart_clk>, <&uart_clk>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +};
> >
>
> I wonder if there aren't any other devices which can be supported out of the box.
> I understand that for now we are missing the clock driver and the pinctrl
> driver. Are you planning to submit them in the near future?
>
> I'm asking because I don't want to bloat the dts with boards that only can boot
> to an initramfs with a serial console. Especially if there is no HW + datasheet
> available for anyone in the community who wants to work on this.
>
> Regards,
> Matthias
>
> Regards,
> Matthias
We have implement clock and pinctrl driver these days, and plan to
submit them maybe next month.
After that we will submit other drivers of MT8183 continuously.
Regards,
Erin
^ permalink raw reply
* [RFC][PATCH] arm64: update iomem_resource.end
From: Robin Murphy @ 2018-05-11 11:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180510222920.GA20553@Asurada-Nvidia>
On 10/05/18 23:29, Nicolin Chen wrote:
> Thanks for the comments, Robin.
>
> On Thu, May 10, 2018 at 06:45:59PM +0100, Robin Murphy wrote:
>> On 09/05/18 23:58, Nicolin Chen wrote:
>>> The iomem_resource.end is -1 by default and should be updated in
>>> arch-level code.
>>>
>>> ARM64 so far hasn't updated it while core kernel code (mm/hmm.c)
>>> started to use iomem_resource.end for boundary check. So it'd be
>>> better to assign iomem_resource.end using a valid value, the end
>>> of physical address space for example because iomem_resource.end
>>> in theory should reflect that.
>>>
>>> However, VA_BITS might be smaller than PA_BITS in ARM64. So using
>>> the end of physical address space doesn't make a lot of sense in
>>> this case, or could be even harmful since virtual address cannot
>>> reach that memory region.
>>
>> Why? There's plenty of stuff in the physical address space that will
>> only ever be accessed via ioremap/memremap. There's no reason you
>> shouldn't be able to run a VA_BITS < 48 kernel on a Cavium ThunderX
>
> I'm running VA_BITS_39 and PA_BITS_48 on Tegra 210. There had
> not been any problem of it, however with hmm.....
>
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/mm/hmm.c#n1144
>
> This hmm_devmem_add() requests a region with PFNs being outside
> of the linear region in ARM64 case which takes MAX_PHYSMEM_BITS
> (48 bits) over iomem_resource.end without this patch. Then when
> dealing with page structures in vmemmap region from a given PFN
> directly (CONFIG_SPARSEMEM_VMEMMAP=y), and the given PFN is the
> last one based on physical region (48 bits), the address of its
> page structure will go beyond vmemmap region. Does this sound a
> problem?
Yes, but as far as we're concerned here it's not a problem with arm64:
config ARCH_HAS_HMM
...
depends on (X86_64 || PPC64)
depends on ZONE_DEVICE
...
depends on MEMORY_HOTPLUG
depends on MEMORY_HOTREMOVE
...
Whatever out-of-tree changes you have to address all of those are
clearly implemented incorrectly; *that's* your problem.
>> where *all* the I/O is in the top half of the PA space. We already
>> constrain RAM in this very function to those regions which fit into
>> the linear map, and if you're accessing anything other than RAM
>> through the linear map you're probably doing something wrong.
>
> If I understand this part correctly, since ARM64 has applied the
> memory limit already, does it mean that probably we should fix
> something in the region_intersects() or add an extra check in the
> hmm_devmem_add(), instead of limiting the iomem_resource?
It means we should implement memory hotplug correctly. Which,
unfortunately, I happen to know is really hard (it's something I've been
looking at from the device-DAX angle).
>> Furthermore, the physical region covered by the linear map doesn't
>> necessarily start at physical address 0 anyway - see PHYS_OFFSET.
>
> Hmm...okay...but there still should be a protection somewhere if
> it happens to access a page structure via pfn_to_page() while the
> PFN is not covered by the vmemmap linear mapping, right?
There already is: pfn_valid() will return false for anything outside the
intersection of memblock regions and the linear map region as calculated
by arm64_memblock_init(); anything calling pfn_to_page() without
checking pfn_valid() first is fundamentally broken. Or if you have
out-of-tree changes to the pfn_valid() implementation then all bets are
off, and it's not something for mainline to work around.
Robin.
^ permalink raw reply
* [PATCH] firmware: ti_sci: Correct the timeout type in ti_sci_do_xfer()
From: Peter Ujfalusi @ 2018-05-11 11:17 UTC (permalink / raw)
To: linux-arm-kernel
It should be 'unsigned long', not int.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/firmware/ti_sci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index b74a533ef35b..398a6db4da88 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -419,7 +419,7 @@ static inline int ti_sci_do_xfer(struct ti_sci_info *info,
struct ti_sci_xfer *xfer)
{
int ret;
- int timeout;
+ unsigned long timeout;
struct device *dev = info->dev;
ret = mbox_send_message(info->chan_tx, &xfer->tx_message);
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Matthias Brugger @ 2018-05-11 11:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526035267.13828.13.camel@mtksdaap41>
On 05/11/2018 12:41 PM, Erin Lo wrote:
> On Fri, 2018-05-11 at 10:36 +0200, Matthias Brugger wrote:
>>
>> On 05/11/2018 08:11 AM, Erin Lo wrote:
[...]
>>
>> I wonder if there aren't any other devices which can be supported out of the box.
>> I understand that for now we are missing the clock driver and the pinctrl
>> driver. Are you planning to submit them in the near future?
>>
>> I'm asking because I don't want to bloat the dts with boards that only can boot
>> to an initramfs with a serial console. Especially if there is no HW + datasheet
>> available for anyone in the community who wants to work on this.
>>
>> Regards,
>> Matthias
>>
>> Regards,
>> Matthias
>
>
> We have implement clock and pinctrl driver these days, and plan to
> submit them maybe next month.
> After that we will submit other drivers of MT8183 continuously.
>
I'm happy to hear this. So in this case I'm fine with merging these once you
figured out the dt-bindings.
Thanks a lot,
Matthias
^ permalink raw reply
* [PATCH 1/3] dt-bindings: media: rcar-vin: Add R8A77995 support
From: Niklas Söderlund @ 2018-05-11 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526032802-14376-2-git-send-email-jacopo+renesas@jmondi.org>
Hi Jacopo,
Thanks for your work.
On 2018-05-11 12:00:00 +0200, Jacopo Mondi wrote:
> Add compatible string for R-Car D3 R8A7795 to list of SoCs supported by
> rcar-vin driver.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Acked-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> Documentation/devicetree/bindings/media/rcar_vin.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
> index a19517e1..5c6f2a7 100644
> --- a/Documentation/devicetree/bindings/media/rcar_vin.txt
> +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
> @@ -22,6 +22,7 @@ on Gen3 platforms to a CSI-2 receiver.
> - "renesas,vin-r8a7795" for the R8A7795 device
> - "renesas,vin-r8a7796" for the R8A7796 device
> - "renesas,vin-r8a77970" for the R8A77970 device
> + - "renesas,vin-r8a77995" for the R8A77995 device
> - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
> device.
>
> --
> 2.7.4
>
--
Regards,
Niklas S?derlund
^ permalink raw reply
* [PATCH] [stable 4.14] arm64: Add work around for Arm Cortex-A55 Erratum 1024718
From: Suzuki K Poulose @ 2018-05-11 11:23 UTC (permalink / raw)
To: linux-arm-kernel
commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream
Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table entry is modified without a break-before-make
sequence. The work around is to disable the hardware DBM feature
on the affected cores. The hardware Access Flag management features
is not affected.
The hardware DBM feature is a non-conflicting capability, i.e, the
kernel could handle cores using the feature and those without having
the features running at the same time. So this work around is detected
at early boot time, rather than delaying it until the CPUs are brought
up into the kernel with MMU turned on. This also avoids other complexities
with late CPUs turning online, with or without the hardware DBM features.
Cc: stable at vger.kernel.org # v4.14
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Note: The upstream commit is on top of a reworked capability
infrastructure for arm64 heterogeneous systems, which allows
delaying the CPU model checks. This backport is based on the
original version of the patch [0], which checks the affected
CPU models during the early boot.
[0] https://lkml.kernel.org/r/20180116102323.3470-1-suzuki.poulose at arm.com
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 14 ++++++++++++
arch/arm64/include/asm/assembler.h | 40 ++++++++++++++++++++++++++++++++++
arch/arm64/include/asm/cputype.h | 2 ++
arch/arm64/mm/proc.S | 5 +++++
5 files changed, 62 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index f3d0d31..e4fe6ad 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -55,6 +55,7 @@ stable kernels.
| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
| ARM | Cortex-A72 | #853709 | N/A |
| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
+| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
| ARM | MMU-500 | #841119,#826419 | N/A |
| | | | |
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index c2abb4e..2d5f7ac 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -443,6 +443,20 @@ config ARM64_ERRATUM_843419
If unsure, say Y.
+config ARM64_ERRATUM_1024718
+ bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
+ default y
+ help
+ This option adds work around for Arm Cortex-A55 Erratum 1024718.
+
+ Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+ update of the hardware dirty bit when the DBM/AP bits are updated
+ without a break-before-make. The work around is to disable the usage
+ of hardware DBM locally on the affected cores. CPUs not affected by
+ erratum will continue to use the feature.
+
+ If unsure, say Y.
+
config CAVIUM_ERRATUM_22375
bool "Cavium erratum 22375, 24313"
default y
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 463619d..25b2a41 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -25,6 +25,7 @@
#include <asm/asm-offsets.h>
#include <asm/cpufeature.h>
+#include <asm/cputype.h>
#include <asm/page.h>
#include <asm/pgtable-hwdef.h>
#include <asm/ptrace.h>
@@ -495,4 +496,43 @@ alternative_endif
and \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
.endm
+/*
+ * Check the MIDR_EL1 of the current CPU for a given model and a range of
+ * variant/revision. See asm/cputype.h for the macros used below.
+ *
+ * model: MIDR_CPU_MODEL of CPU
+ * rv_min: Minimum of MIDR_CPU_VAR_REV()
+ * rv_max: Maximum of MIDR_CPU_VAR_REV()
+ * res: Result register.
+ * tmp1, tmp2, tmp3: Temporary registers
+ *
+ * Corrupts: res, tmp1, tmp2, tmp3
+ * Returns: 0, if the CPU id doesn't match. Non-zero otherwise
+ */
+ .macro cpu_midr_match model, rv_min, rv_max, res, tmp1, tmp2, tmp3
+ mrs \res, midr_el1
+ mov_q \tmp1, (MIDR_REVISION_MASK | MIDR_VARIANT_MASK)
+ mov_q \tmp2, MIDR_CPU_MODEL_MASK
+ and \tmp3, \res, \tmp2 // Extract model
+ and \tmp1, \res, \tmp1 // rev & variant
+ mov_q \tmp2, \model
+ cmp \tmp3, \tmp2
+ cset \res, eq
+ cbz \res, .Ldone\@ // Model matches ?
+
+ .if (\rv_min != 0) // Skip min check if rv_min == 0
+ mov_q \tmp3, \rv_min
+ cmp \tmp1, \tmp3
+ cset \res, ge
+ .endif // \rv_min != 0
+ /* Skip rv_max check if rv_min == rv_max && rv_min != 0 */
+ .if ((\rv_min != \rv_max) || \rv_min == 0)
+ mov_q \tmp2, \rv_max
+ cmp \tmp1, \tmp2
+ cset \tmp2, le
+ and \res, \res, \tmp2
+ .endif
+.Ldone\@:
+ .endm
+
#endif /* __ASM_ASSEMBLER_H */
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index be7bd19..30da091 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -78,6 +78,7 @@
#define ARM_CPU_PART_AEM_V8 0xD0F
#define ARM_CPU_PART_FOUNDATION 0xD00
+#define ARM_CPU_PART_CORTEX_A55 0xD05
#define ARM_CPU_PART_CORTEX_A57 0xD07
#define ARM_CPU_PART_CORTEX_A72 0xD08
#define ARM_CPU_PART_CORTEX_A53 0xD03
@@ -98,6 +99,7 @@
#define QCOM_CPU_PART_KRYO 0x200
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
+#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 139320a..e338165 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -438,6 +438,11 @@ ENTRY(__cpu_setup)
cbz x9, 2f
cmp x9, #2
b.lt 1f
+#ifdef CONFIG_ARM64_ERRATUM_1024718
+ /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */
+ cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(1, 0), x1, x2, x3, x4
+ cbnz x1, 1f
+#endif
orr x10, x10, #TCR_HD // hardware Dirty flag update
1: orr x10, x10, #TCR_HA // hardware Access flag update
2:
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/2] soc: mediatek: reuse regmap_read_poll_timeout helpers
From: Matthias Brugger @ 2018-05-11 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed866d3345a27b2c87b570562d9ad9132bca6062.1524465345.git.sean.wang@mediatek.com>
Hi Sean,
On 04/23/2018 08:42 AM, sean.wang at mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
>
> Reuse the common helpers regmap_read_poll_timeout provided by Linux core
> instead of an open-coded handling.
>
> v1 -> v2:
> - use macro definitions MTK_POLL_DELAY_US and MTK_POLL_TIMEOUT for
> arguments sleep_us and timeout_us passing in regmap_read_poll_timeout.
> - remove unnecessary linux/iopoll.h being included in.
>
I just realized that you wrote the changelog here, which will make it show up in
the commit log. Thant's not what we want... (see below)
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> Cc: Matthias Brugger <matthias.bgg@gmail.com>
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Cc: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-infracfg.c | 46 ++++++++++---------------------------
> 1 file changed, 12 insertions(+), 34 deletions(-)
>
Please write your changelog here in the future.
I'll fix that up in my tree now, but please remember the next time :)
Thanks
Matthias
^ permalink raw reply
* [PATCH 2/3] arm64: dts: renesas: r8a77995: Add VIN4
From: Niklas Söderlund @ 2018-05-11 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526032802-14376-3-git-send-email-jacopo+renesas@jmondi.org>
Hi Jacopo,
Thanks for your work.
On 2018-05-11 12:00:01 +0200, Jacopo Mondi wrote:
> Describe VIN4 interface for R-Car D3 R8A77995 SoC.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Acked-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> index 82aed7e..bdf7017 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> @@ -783,6 +783,17 @@
> };
> };
> };
> +
> + vin4: video at e6ef4000 {
> + compatible = "renesas,vin-r8a77995";
> + reg = <0 0xe6ef4000 0 0x1000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 807>;
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 807>;
> + renesas,id = <4>;
> + status = "disabled";
> + };
> };
>
> timer {
> --
> 2.7.4
>
--
Regards,
Niklas S?derlund
^ permalink raw reply
* [PATCH] soc: mediatek: remove unneeded semicolon
From: Matthias Brugger @ 2018-05-11 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a4b9c30335194d90072baf9373e41a21b349bc54.1525920846.git.sean.wang@mediatek.com>
On 05/10/2018 04:57 AM, sean.wang at mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
>
> Fix up drivers/soc/mediatek/mtk-scpsys.c:255:2-3: Unneeded semicolon
> accidently being added in commit f9e2f65dd561 ("soc: mediatek: add a
> fixed wait for SRAM stable").
>
> Fixes: f9e2f65dd561 ("soc: mediatek: add a fixed wait for SRAM stable")
> Reported-by: kbuild test robot <lkp@intel.com>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
pushed to v4.17-next/soc
Thanks
> drivers/soc/mediatek/mtk-scpsys.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index 2080c8f..128e3dd 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -252,7 +252,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> if (ret < 0)
> goto err_pwr_ack;
> - };
> + }
>
> if (scpd->data->bus_prot_mask) {
> ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
>
^ permalink raw reply
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