* [PATCH 2/3] arm64: dts: renesas: r8a77995: Add VIN4
From: Simon Horman @ 2018-05-11 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511112523.GK18974@bigcity.dyn.berto.se>
On Fri, May 11, 2018 at 01:25:23PM +0200, Niklas S?derlund wrote:
> Hi Jacopo,
>
> Thanks for your work.
>
> On 2018-05-11 12:00:01 +0200, Jacopo Mondi wrote:
> > Describe VIN4 interface for R-Car D3 R8A77995 SoC.
> >
> > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
>
> Acked-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
>
> > ---
> > arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> > index 82aed7e..bdf7017 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> > @@ -783,6 +783,17 @@
> > };
> > };
> > };
> > +
> > + vin4: video at e6ef4000 {
> > + compatible = "renesas,vin-r8a77995";
> > + reg = <0 0xe6ef4000 0 0x1000>;
> > + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 807>;
> > + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> > + resets = <&cpg 807>;
> > + renesas,id = <4>;
> > + status = "disabled";
> > + };
> > };
Thanks, I have moved the new node to preserve sorting of nodes by bus
address and applied the result. It is as follows:
From: Jacopo Mondi <jacopo+renesas@jmondi.org>
Subject: [PATCH] arm64: dts: renesas: r8a77995: Add VIN4
Describe VIN4 interface for R-Car D3 R8A77995 SoC.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Acked-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
[simon: sorted node by bus address]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index ba98865b0c9b..2506f46293e8 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -610,6 +610,17 @@
status = "disabled";
};
+ vin4: video at e6ef4000 {
+ compatible = "renesas,vin-r8a77995";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ renesas,id = <4>;
+ status = "disabled";
+ };
+
ohci0: usb at ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
--
2.11.0
^ permalink raw reply related
* [PATCH RESEND v2 1/2] perf cs-etm: Support unknown_thread in cs_etm_auxtrace
From: Arnaldo Carvalho de Melo @ 2018-05-11 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525924920-4381-1-git-send-email-leo.yan@linaro.org>
Em Thu, May 10, 2018 at 12:01:59PM +0800, Leo Yan escreveu:
> CoreSight doesn't allocate thread structure for unknown_thread in etm
> auxtrace, so unknown_thread is NULL pointer. If the perf data doesn't
> contain valid tid and then cs_etm__mem_access() uses unknown_thread
> instead as thread handler, this results in segmentation fault when
> thread__find_addr_map() accesses thread handler.
>
> This commit creates new thread data which is used by unknown_thread, so
> CoreSight tracing can roll back to use unknown_thread if perf data
> doesn't include valid thread info. This commit also releases thread
> data for initialization failure case and for normal auxtrace free flow.
>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Thanks, applied to perf/urgent.
And please use a more descriptive, eye catching summary, something like:
perf cs-etm: Fix segfault when accessing NULL unknown_thread variable
:-)
- Arnaldo
^ permalink raw reply
* [PATCH] [stable 4.9] arm64: Add work around for Arm Cortex-A55 Erratum 1024718
From: Suzuki K Poulose @ 2018-05-11 13:51 UTC (permalink / raw)
To: linux-arm-kernel
commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream
Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table entry is modified without a break-before-make
sequence. The work around is to disable the hardware DBM feature
on the affected cores. The hardware Access Flag management features
is not affected.
The hardware DBM feature is a non-conflicting capability, i.e, the
kernel could handle cores using the feature and those without having
the features running at the same time. So this work around is detected
at early boot time, rather than delaying it until the CPUs are brought
up into the kernel with MMU turned on. This also avoids other complexities
with late CPUs turning online, with or without the hardware DBM features.
Cc: stable at vger.kernel.org # v4.9
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Note: The upstream commit is on top of a reworked capability
infrastructure for arm64 heterogeneous systems, which allows
delaying the CPU model checks. This backport is based on the
original version of the patch [0], which checks the affected
CPU models during the early boot.
[0] https://lkml.kernel.org/r/20180116102323.3470-1-suzuki.poulose at arm.com
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 14 ++++++++++++
arch/arm64/include/asm/assembler.h | 40 ++++++++++++++++++++++++++++++++++
arch/arm64/include/asm/cputype.h | 5 +++++
arch/arm64/mm/proc.S | 5 +++++
5 files changed, 65 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index d11af52..ac9489f 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -54,6 +54,7 @@ stable kernels.
| ARM | Cortex-A57 | #852523 | N/A |
| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
| ARM | Cortex-A72 | #853709 | N/A |
+| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
| ARM | MMU-500 | #841119,#826419 | N/A |
| | | | |
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 90e58bb..d0df361 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -427,6 +427,20 @@ config ARM64_ERRATUM_843419
If unsure, say Y.
+config ARM64_ERRATUM_1024718
+ bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
+ default y
+ help
+ This option adds work around for Arm Cortex-A55 Erratum 1024718.
+
+ Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+ update of the hardware dirty bit when the DBM/AP bits are updated
+ without a break-before-make. The work around is to disable the usage
+ of hardware DBM locally on the affected cores. CPUs not affected by
+ erratum will continue to use the feature.
+
+ If unsure, say Y.
+
config CAVIUM_ERRATUM_22375
bool "Cavium erratum 22375, 24313"
default y
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index e60375c..bfcfec3 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -25,6 +25,7 @@
#include <asm/asm-offsets.h>
#include <asm/cpufeature.h>
+#include <asm/cputype.h>
#include <asm/page.h>
#include <asm/pgtable-hwdef.h>
#include <asm/ptrace.h>
@@ -435,4 +436,43 @@ alternative_endif
and \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
.endm
+/*
+ * Check the MIDR_EL1 of the current CPU for a given model and a range of
+ * variant/revision. See asm/cputype.h for the macros used below.
+ *
+ * model: MIDR_CPU_MODEL of CPU
+ * rv_min: Minimum of MIDR_CPU_VAR_REV()
+ * rv_max: Maximum of MIDR_CPU_VAR_REV()
+ * res: Result register.
+ * tmp1, tmp2, tmp3: Temporary registers
+ *
+ * Corrupts: res, tmp1, tmp2, tmp3
+ * Returns: 0, if the CPU id doesn't match. Non-zero otherwise
+ */
+ .macro cpu_midr_match model, rv_min, rv_max, res, tmp1, tmp2, tmp3
+ mrs \res, midr_el1
+ mov_q \tmp1, (MIDR_REVISION_MASK | MIDR_VARIANT_MASK)
+ mov_q \tmp2, MIDR_CPU_MODEL_MASK
+ and \tmp3, \res, \tmp2 // Extract model
+ and \tmp1, \res, \tmp1 // rev & variant
+ mov_q \tmp2, \model
+ cmp \tmp3, \tmp2
+ cset \res, eq
+ cbz \res, .Ldone\@ // Model matches ?
+
+ .if (\rv_min != 0) // Skip min check if rv_min == 0
+ mov_q \tmp3, \rv_min
+ cmp \tmp1, \tmp3
+ cset \res, ge
+ .endif // \rv_min != 0
+ /* Skip rv_max check if rv_min == rv_max && rv_min != 0 */
+ .if ((\rv_min != \rv_max) || \rv_min == 0)
+ mov_q \tmp2, \rv_max
+ cmp \tmp1, \tmp2
+ cset \tmp2, le
+ and \res, \res, \tmp2
+ .endif
+.Ldone\@:
+ .endm
+
#endif /* __ASM_ASSEMBLER_H */
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 9ee3038..39d1db6 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -56,6 +56,9 @@
(0xf << MIDR_ARCHITECTURE_SHIFT) | \
((partnum) << MIDR_PARTNUM_SHIFT))
+#define MIDR_CPU_VAR_REV(var, rev) \
+ (((var) << MIDR_VARIANT_SHIFT) | (rev))
+
#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
MIDR_ARCHITECTURE_MASK)
@@ -74,6 +77,7 @@
#define ARM_CPU_PART_AEM_V8 0xD0F
#define ARM_CPU_PART_FOUNDATION 0xD00
+#define ARM_CPU_PART_CORTEX_A55 0xD05
#define ARM_CPU_PART_CORTEX_A57 0xD07
#define ARM_CPU_PART_CORTEX_A72 0xD08
#define ARM_CPU_PART_CORTEX_A53 0xD03
@@ -89,6 +93,7 @@
#define BRCM_CPU_PART_VULCAN 0x516
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
+#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 619da1c..66cce21 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -425,6 +425,11 @@ ENTRY(__cpu_setup)
cbz x9, 2f
cmp x9, #2
b.lt 1f
+#ifdef CONFIG_ARM64_ERRATUM_1024718
+ /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */
+ cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(1, 0), x1, x2, x3, x4
+ cbnz x1, 1f
+#endif
orr x10, x10, #TCR_HD // hardware Dirty flag update
1: orr x10, x10, #TCR_HA // hardware Access flag update
2:
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] arm64: defconfig: sync it with savedefconfig
From: Wei Xu @ 2018-05-11 13:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526007049-27884-1-git-send-email-shawn.guo@linaro.org>
Hi Shawn,
On 2018/5/11 3:50, Shawn Guo wrote:
> Sync the defconfig with savedefconfig with the following commands:
>
> make defconfig
> make savedefconfig
> cp defconfig arch/arm64/configs/defconfig
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Series applied into the hisilicon defconfig tree.
Thanks!
BR,
Wei
> ---
> arch/arm64/configs/defconfig | 80 +++++++++++++++++---------------------------
> 1 file changed, 30 insertions(+), 50 deletions(-)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index ecf613761e78..af0992f2fee7 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -47,6 +47,7 @@ CONFIG_ARCH_MVEBU=y
> CONFIG_ARCH_QCOM=y
> CONFIG_ARCH_ROCKCHIP=y
> CONFIG_ARCH_SEATTLE=y
> +CONFIG_ARCH_SYNQUACER=y
> CONFIG_ARCH_RENESAS=y
> CONFIG_ARCH_R8A7795=y
> CONFIG_ARCH_R8A7796=y
> @@ -57,7 +58,6 @@ CONFIG_ARCH_R8A77995=y
> CONFIG_ARCH_STRATIX10=y
> CONFIG_ARCH_TEGRA=y
> CONFIG_ARCH_SPRD=y
> -CONFIG_ARCH_SYNQUACER=y
> CONFIG_ARCH_THUNDER=y
> CONFIG_ARCH_THUNDER2=y
> CONFIG_ARCH_UNIPHIER=y
> @@ -73,16 +73,16 @@ CONFIG_HOTPLUG_PCI_ACPI=y
> CONFIG_PCI_LAYERSCAPE=y
> CONFIG_PCI_HISI=y
> CONFIG_PCIE_QCOM=y
> -CONFIG_PCIE_KIRIN=y
> CONFIG_PCIE_ARMADA_8K=y
> +CONFIG_PCIE_KIRIN=y
> CONFIG_PCI_AARDVARK=y
> CONFIG_PCI_TEGRA=y
> CONFIG_PCIE_RCAR=y
> -CONFIG_PCIE_ROCKCHIP=m
> CONFIG_PCI_HOST_GENERIC=y
> CONFIG_PCI_XGENE=y
> CONFIG_PCI_HOST_THUNDER_PEM=y
> CONFIG_PCI_HOST_THUNDER_ECAM=y
> +CONFIG_PCIE_ROCKCHIP=m
> CONFIG_ARM64_VA_BITS_48=y
> CONFIG_SCHED_MC=y
> CONFIG_NUMA=y
> @@ -101,8 +101,6 @@ CONFIG_HIBERNATION=y
> CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
> CONFIG_ARM_CPUIDLE=y
> CONFIG_CPU_FREQ=y
> -CONFIG_CPU_FREQ_GOV_ATTR_SET=y
> -CONFIG_CPU_FREQ_GOV_COMMON=y
> CONFIG_CPU_FREQ_STAT=y
> CONFIG_CPU_FREQ_GOV_POWERSAVE=m
> CONFIG_CPU_FREQ_GOV_USERSPACE=y
> @@ -110,11 +108,11 @@ CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
> CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
> CONFIG_CPUFREQ_DT=y
> +CONFIG_ACPI_CPPC_CPUFREQ=m
> CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
> CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
> CONFIG_ARM_SCPI_CPUFREQ=y
> CONFIG_ARM_TEGRA186_CPUFREQ=y
> -CONFIG_ACPI_CPPC_CPUFREQ=m
> CONFIG_NET=y
> CONFIG_PACKET=y
> CONFIG_UNIX=y
> @@ -223,11 +221,6 @@ CONFIG_SMSC911X=y
> CONFIG_SNI_AVE=y
> CONFIG_SNI_NETSEC=y
> CONFIG_STMMAC_ETH=m
> -CONFIG_DWMAC_IPQ806X=m
> -CONFIG_DWMAC_MESON=m
> -CONFIG_DWMAC_ROCKCHIP=m
> -CONFIG_DWMAC_SUNXI=m
> -CONFIG_DWMAC_SUN8I=m
> CONFIG_MDIO_BUS_MUX_MMIOREG=y
> CONFIG_AT803X_PHY=m
> CONFIG_MARVELL_PHY=m
> @@ -251,8 +244,8 @@ CONFIG_WL18XX=m
> CONFIG_WLCORE_SDIO=m
> CONFIG_INPUT_EVDEV=y
> CONFIG_KEYBOARD_ADC=m
> -CONFIG_KEYBOARD_CROS_EC=y
> CONFIG_KEYBOARD_GPIO=y
> +CONFIG_KEYBOARD_CROS_EC=y
> CONFIG_INPUT_MISC=y
> CONFIG_INPUT_PM8941_PWRKEY=y
> CONFIG_INPUT_HISI_POWERKEY=y
> @@ -276,15 +269,12 @@ CONFIG_SERIAL_SAMSUNG=y
> CONFIG_SERIAL_SAMSUNG_CONSOLE=y
> CONFIG_SERIAL_TEGRA=y
> CONFIG_SERIAL_SH_SCI=y
> -CONFIG_SERIAL_SH_SCI_NR_UARTS=11
> -CONFIG_SERIAL_SH_SCI_CONSOLE=y
> CONFIG_SERIAL_MSM=y
> CONFIG_SERIAL_MSM_CONSOLE=y
> CONFIG_SERIAL_XILINX_PS_UART=y
> CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
> CONFIG_SERIAL_MVEBU_UART=y
> CONFIG_SERIAL_DEV_BUS=y
> -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_I2C_CHARDEV=y
> CONFIG_I2C_MUX=y
> @@ -303,20 +293,20 @@ CONFIG_I2C_UNIPHIER_F=y
> CONFIG_I2C_RCAR=y
> CONFIG_I2C_CROS_EC_TUNNEL=y
> CONFIG_SPI=y
> -CONFIG_SPI_MESON_SPICC=m
> -CONFIG_SPI_MESON_SPIFC=m
> CONFIG_SPI_BCM2835=m
> CONFIG_SPI_BCM2835AUX=m
> +CONFIG_SPI_MESON_SPICC=m
> +CONFIG_SPI_MESON_SPIFC=m
> CONFIG_SPI_ORION=y
> CONFIG_SPI_PL022=y
> -CONFIG_SPI_QUP=y
> CONFIG_SPI_ROCKCHIP=y
> +CONFIG_SPI_QUP=y
> CONFIG_SPI_S3C64XX=y
> CONFIG_SPI_SPIDEV=m
> CONFIG_SPMI=y
> -CONFIG_PINCTRL_IPQ8074=y
> CONFIG_PINCTRL_SINGLE=y
> CONFIG_PINCTRL_MAX77620=y
> +CONFIG_PINCTRL_IPQ8074=y
> CONFIG_PINCTRL_MSM8916=y
> CONFIG_PINCTRL_MSM8994=y
> CONFIG_PINCTRL_MSM8996=y
> @@ -343,12 +333,12 @@ CONFIG_SENSORS_INA2XX=m
> CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
> CONFIG_CPU_THERMAL=y
> CONFIG_THERMAL_EMULATION=y
> +CONFIG_ROCKCHIP_THERMAL=m
> +CONFIG_RCAR_GEN3_THERMAL=y
> CONFIG_BRCMSTB_THERMAL=m
> CONFIG_EXYNOS_THERMAL=y
> -CONFIG_RCAR_GEN3_THERMAL=y
> -CONFIG_QCOM_TSENS=y
> -CONFIG_ROCKCHIP_THERMAL=m
> CONFIG_TEGRA_BPMP_THERMAL=m
> +CONFIG_QCOM_TSENS=y
> CONFIG_UNIPHIER_THERMAL=y
> CONFIG_WATCHDOG=y
> CONFIG_S3C2410_WATCHDOG=y
> @@ -368,9 +358,9 @@ CONFIG_MFD_MAX77620=y
> CONFIG_MFD_SPMI_PMIC=y
> CONFIG_MFD_RK808=y
> CONFIG_MFD_SEC_CORE=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> CONFIG_REGULATOR_AXP20X=y
> CONFIG_REGULATOR_FAN53555=y
> -CONFIG_REGULATOR_FIXED_VOLTAGE=y
> CONFIG_REGULATOR_GPIO=y
> CONFIG_REGULATOR_HI6421V530=y
> CONFIG_REGULATOR_HI655X=y
> @@ -380,16 +370,15 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y
> CONFIG_REGULATOR_QCOM_SPMI=y
> CONFIG_REGULATOR_RK808=y
> CONFIG_REGULATOR_S2MPS11=y
> +CONFIG_RC_CORE=m
> +CONFIG_RC_DECODERS=y
> +CONFIG_RC_DEVICES=y
> +CONFIG_IR_MESON=m
> CONFIG_MEDIA_SUPPORT=m
> CONFIG_MEDIA_CAMERA_SUPPORT=y
> CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
> CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
> CONFIG_MEDIA_CONTROLLER=y
> -CONFIG_MEDIA_RC_SUPPORT=y
> -CONFIG_RC_CORE=m
> -CONFIG_RC_DEVICES=y
> -CONFIG_RC_DECODERS=y
> -CONFIG_IR_MESON=m
> CONFIG_VIDEO_V4L2_SUBDEV_API=y
> # CONFIG_DVB_NET is not set
> CONFIG_V4L_MEM2MEM_DRIVERS=y
> @@ -414,8 +403,7 @@ CONFIG_ROCKCHIP_DW_HDMI=y
> CONFIG_ROCKCHIP_DW_MIPI_DSI=y
> CONFIG_ROCKCHIP_INNO_HDMI=y
> CONFIG_DRM_RCAR_DU=m
> -CONFIG_DRM_RCAR_LVDS=y
> -CONFIG_DRM_RCAR_VSP=y
> +CONFIG_DRM_RCAR_LVDS=m
> CONFIG_DRM_TEGRA=m
> CONFIG_DRM_PANEL_SIMPLE=m
> CONFIG_DRM_I2C_ADV7511=m
> @@ -428,7 +416,6 @@ CONFIG_FB_ARMCLCD=y
> CONFIG_BACKLIGHT_GENERIC=m
> CONFIG_BACKLIGHT_PWM=m
> CONFIG_BACKLIGHT_LP855X=m
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> CONFIG_LOGO=y
> # CONFIG_LOGO_LINUX_MONO is not set
> # CONFIG_LOGO_LINUX_VGA16 is not set
> @@ -473,12 +460,12 @@ CONFIG_MMC_BLOCK_MINORS=32
> CONFIG_MMC_ARMMMCI=y
> CONFIG_MMC_SDHCI=y
> CONFIG_MMC_SDHCI_ACPI=y
> -CONFIG_MMC_SDHCI_F_SDH30=y
> CONFIG_MMC_SDHCI_PLTFM=y
> CONFIG_MMC_SDHCI_OF_ARASAN=y
> CONFIG_MMC_SDHCI_OF_ESDHC=y
> CONFIG_MMC_SDHCI_CADENCE=y
> CONFIG_MMC_SDHCI_TEGRA=y
> +CONFIG_MMC_SDHCI_F_SDH30=y
> CONFIG_MMC_MESON_GX=y
> CONFIG_MMC_SDHCI_MSM=y
> CONFIG_MMC_SPI=y
> @@ -495,11 +482,11 @@ CONFIG_LEDS_CLASS=y
> CONFIG_LEDS_GPIO=y
> CONFIG_LEDS_PWM=y
> CONFIG_LEDS_SYSCON=y
> +CONFIG_LEDS_TRIGGER_DISK=y
> CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> CONFIG_LEDS_TRIGGER_CPU=y
> CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> CONFIG_LEDS_TRIGGER_PANIC=y
> -CONFIG_LEDS_TRIGGER_DISK=y
> CONFIG_EDAC=y
> CONFIG_EDAC_GHES=y
> CONFIG_RTC_CLASS=y
> @@ -569,7 +556,6 @@ CONFIG_ARCH_TEGRA_186_SOC=y
> CONFIG_ARCH_TEGRA_194_SOC=y
> CONFIG_EXTCON_USB_GPIO=y
> CONFIG_MEMORY=y
> -CONFIG_TEGRA_MC=y
> CONFIG_IIO=y
> CONFIG_EXYNOS_ADC=y
> CONFIG_ROCKCHIP_SARADC=m
> @@ -581,22 +567,22 @@ CONFIG_PWM_RCAR=m
> CONFIG_PWM_ROCKCHIP=y
> CONFIG_PWM_SAMSUNG=y
> CONFIG_PWM_TEGRA=m
> -CONFIG_PHY_RCAR_GEN3_USB2=y
> -CONFIG_PHY_RCAR_GEN3_USB3=m
> -CONFIG_PHY_HI6220_USB=y
> -CONFIG_PHY_QCOM_USB_HS=y
> +CONFIG_PHY_XGENE=y
> CONFIG_PHY_SUN4I_USB=y
> +CONFIG_PHY_HI6220_USB=y
> CONFIG_PHY_MVEBU_CP110_COMPHY=y
> -CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_QCOM_USB_HS=y
> +CONFIG_PHY_RCAR_GEN3_USB2=y
> +CONFIG_PHY_RCAR_GEN3_USB3=m
> CONFIG_PHY_ROCKCHIP_EMMC=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> CONFIG_PHY_ROCKCHIP_PCIE=m
> -CONFIG_PHY_XGENE=y
> CONFIG_PHY_TEGRA_XUSB=y
> CONFIG_QCOM_L2_PMU=y
> CONFIG_QCOM_L3_PMU=y
> -CONFIG_MESON_EFUSE=m
> CONFIG_QCOM_QFPROM=y
> CONFIG_UNIPHIER_EFUSE=y
> +CONFIG_MESON_EFUSE=m
> CONFIG_TEE=y
> CONFIG_OPTEE=y
> CONFIG_ARM_SCPI_PROTOCOL=y
> @@ -640,7 +626,6 @@ CONFIG_DEBUG_INFO=y
> CONFIG_DEBUG_FS=y
> CONFIG_MAGIC_SYSRQ=y
> CONFIG_DEBUG_KERNEL=y
> -CONFIG_LOCKUP_DETECTOR=y
> # CONFIG_SCHED_DEBUG is not set
> # CONFIG_DEBUG_PREEMPT is not set
> # CONFIG_FTRACE is not set
> @@ -649,20 +634,15 @@ CONFIG_SECURITY=y
> CONFIG_CRYPTO_ECHAINIV=y
> CONFIG_CRYPTO_ANSI_CPRNG=y
> CONFIG_ARM64_CRYPTO=y
> -CONFIG_CRYPTO_SHA256_ARM64=m
> -CONFIG_CRYPTO_SHA512_ARM64=m
> CONFIG_CRYPTO_SHA1_ARM64_CE=y
> CONFIG_CRYPTO_SHA2_ARM64_CE=y
> +CONFIG_CRYPTO_SHA512_ARM64_CE=m
> +CONFIG_CRYPTO_SHA3_ARM64=m
> +CONFIG_CRYPTO_SM3_ARM64_CE=m
> CONFIG_CRYPTO_GHASH_ARM64_CE=y
> CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
> CONFIG_CRYPTO_CRC32_ARM64_CE=m
> -CONFIG_CRYPTO_AES_ARM64=m
> -CONFIG_CRYPTO_AES_ARM64_CE=m
> CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
> CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
> -CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m
> CONFIG_CRYPTO_CHACHA20_NEON=m
> CONFIG_CRYPTO_AES_ARM64_BS=m
> -CONFIG_CRYPTO_SHA512_ARM64_CE=m
> -CONFIG_CRYPTO_SHA3_ARM64=m
> -CONFIG_CRYPTO_SM3_ARM64_CE=m
>
^ permalink raw reply
* [PATCH v3 0/3] arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)
From: Catalin Marinas @ 2018-05-11 13:55 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
The previous version of this patch [1] didn't make it into 4.17 because
of the (compile-time) conflicts with the generic dma-direct.h changes.
I'm reposting it for 4.18 with some minor changes:
- phys_to_dma()/dma_to_phys() now gained underscores to match the
generic dma-direct.h implementation
- the patch is split in three to make the changes clearer to the
reviewers
If at some point in the future the generic swiotlb code gain
non-choerent DMA awareness, the last patch in the series could be
refactored. In the meantime, the simplest, non-intrusive approach is to
select ARCH_HAS_PHYS_TO_DMA on arm64 and force bounce buffering through
an arch-specific dma_capable() implementation.
Thanks,
Catalin
[1] http://lkml.kernel.org/r/20180228184720.25467-1-catalin.marinas at arm.com
Catalin Marinas (3):
Revert "arm64: Increase the max granular size"
arm64: Increase ARCH_DMA_MINALIGN to 128
arm64: Force swiotlb bounce buffering for non-coherent DMA with large
CWG
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/cache.h | 6 +++---
arch/arm64/include/asm/dma-direct.h | 43 +++++++++++++++++++++++++++++++++++++
arch/arm64/kernel/cpufeature.c | 9 ++------
arch/arm64/mm/dma-mapping.c | 17 +++++++++++++++
arch/arm64/mm/init.c | 3 ++-
6 files changed, 68 insertions(+), 11 deletions(-)
create mode 100644 arch/arm64/include/asm/dma-direct.h
^ permalink raw reply
* [PATCH v3 1/3] Revert "arm64: Increase the max granular size"
From: Catalin Marinas @ 2018-05-11 13:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511135547.34521-1-catalin.marinas@arm.com>
This reverts commit 97303480753e48fb313dc0e15daaf11b0451cdb8.
Commit 97303480753e ("arm64: Increase the max granular size") increased
the cache line size to 128 to match Cavium ThunderX, apparently for some
performance benefit which could not be confirmed. This change, however,
has an impact on the network packet allocation in certain circumstances,
requiring slightly over a 4K page with a significant performance
degradation. The patch reverts L1_CACHE_SHIFT back to 6 (64-byte cache
line).
Cc: Will Deacon <will.deacon@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/include/asm/cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 9bbffc7a301f..1dd2c2db0010 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -33,7 +33,7 @@
#define ICACHE_POLICY_VIPT 2
#define ICACHE_POLICY_PIPT 3
-#define L1_CACHE_SHIFT 7
+#define L1_CACHE_SHIFT (6)
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
^ permalink raw reply related
* [PATCH v3 2/3] arm64: Increase ARCH_DMA_MINALIGN to 128
From: Catalin Marinas @ 2018-05-11 13:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511135547.34521-1-catalin.marinas@arm.com>
This patch increases the ARCH_DMA_MINALIGN to 128 so that it covers the
currently known Cache Writeback Granule (CTR_EL0.CWG) on arm64 and moves
the fallback in cache_line_size() from L1_CACHE_BYTES to this constant.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/include/asm/cache.h | 4 ++--
arch/arm64/kernel/cpufeature.c | 9 ++-------
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 1dd2c2db0010..5df5cfe1c143 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -43,7 +43,7 @@
* cache before the transfer is done, causing old data to be seen by
* the CPU.
*/
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+#define ARCH_DMA_MINALIGN (128)
#ifndef __ASSEMBLY__
@@ -77,7 +77,7 @@ static inline u32 cache_type_cwg(void)
static inline int cache_line_size(void)
{
u32 cwg = cache_type_cwg();
- return cwg ? 4 << cwg : L1_CACHE_BYTES;
+ return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
}
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9d1b06d67c53..fbee8c17a4e6 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1606,7 +1606,6 @@ static void __init setup_system_capabilities(void)
void __init setup_cpu_features(void)
{
u32 cwg;
- int cls;
setup_system_capabilities();
mark_const_caps_ready();
@@ -1627,13 +1626,9 @@ void __init setup_cpu_features(void)
* Check for sane CTR_EL0.CWG value.
*/
cwg = cache_type_cwg();
- cls = cache_line_size();
if (!cwg)
- pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
- cls);
- if (L1_CACHE_BYTES < cls)
- pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
- L1_CACHE_BYTES, cls);
+ pr_warn("No Cache Writeback Granule information, assuming %d\n",
+ ARCH_DMA_MINALIGN);
}
static bool __maybe_unused
^ permalink raw reply related
* [PATCH v3 3/3] arm64: Force swiotlb bounce buffering for non-coherent DMA with large CWG
From: Catalin Marinas @ 2018-05-11 13:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511135547.34521-1-catalin.marinas@arm.com>
On systems with a Cache Writeback Granule (CTR_EL0.CWG) greater than
ARCH_DMA_MINALIGN, DMA cache maintenance on sub-CWG ranges is not safe,
leading to data corruption. If such configuration is detected, the
kernel will force swiotlb bounce buffering for all non-coherent devices.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Christoph Hellwig <hch@lst.de>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/dma-direct.h | 43 +++++++++++++++++++++++++++++++++++++
arch/arm64/mm/dma-mapping.c | 17 +++++++++++++++
arch/arm64/mm/init.c | 3 ++-
4 files changed, 63 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/include/asm/dma-direct.h
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index eb2cf4938f6d..ef56b2478205 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -17,6 +17,7 @@ config ARM64
select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
select ARCH_HAS_KCOV
select ARCH_HAS_MEMBARRIER_SYNC_CORE
+ select ARCH_HAS_PHYS_TO_DMA
select ARCH_HAS_SET_MEMORY
select ARCH_HAS_SG_CHAIN
select ARCH_HAS_STRICT_KERNEL_RWX
diff --git a/arch/arm64/include/asm/dma-direct.h b/arch/arm64/include/asm/dma-direct.h
new file mode 100644
index 000000000000..0c18a4d56702
--- /dev/null
+++ b/arch/arm64/include/asm/dma-direct.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_DMA_DIRECT_H
+#define __ASM_DMA_DIRECT_H
+
+#include <linux/jump_label.h>
+#include <linux/swiotlb.h>
+
+#include <asm/cache.h>
+
+DECLARE_STATIC_KEY_FALSE(swiotlb_noncoherent_bounce);
+
+static inline dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+ dma_addr_t dev_addr = (dma_addr_t)paddr;
+
+ return dev_addr - ((dma_addr_t)dev->dma_pfn_offset << PAGE_SHIFT);
+}
+
+static inline phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dev_addr)
+{
+ phys_addr_t paddr = (phys_addr_t)dev_addr;
+
+ return paddr + ((phys_addr_t)dev->dma_pfn_offset << PAGE_SHIFT);
+}
+
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+ if (!dev->dma_mask)
+ return false;
+
+ /*
+ * Force swiotlb buffer bouncing when ARCH_DMA_MINALIGN < CWG. The
+ * swiotlb bounce buffers are aligned to (1 << IO_TLB_SHIFT).
+ */
+ if (static_branch_unlikely(&swiotlb_noncoherent_bounce) &&
+ !is_device_dma_coherent(dev) &&
+ !is_swiotlb_buffer(__dma_to_phys(dev, addr)))
+ return false;
+
+ return addr + size - 1 <= *dev->dma_mask;
+}
+
+#endif /* __ASM_DMA_DIRECT_H */
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index a96ec0181818..1e9dac8684ca 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -33,6 +33,7 @@
#include <asm/cacheflush.h>
static int swiotlb __ro_after_init;
+DEFINE_STATIC_KEY_FALSE(swiotlb_noncoherent_bounce);
static pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot,
bool coherent)
@@ -504,6 +505,14 @@ static int __init arm64_dma_init(void)
max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT))
swiotlb = 1;
+ if (WARN_TAINT(ARCH_DMA_MINALIGN < cache_line_size(),
+ TAINT_CPU_OUT_OF_SPEC,
+ "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
+ ARCH_DMA_MINALIGN, cache_line_size())) {
+ swiotlb = 1;
+ static_branch_enable(&swiotlb_noncoherent_bounce);
+ }
+
return atomic_pool_init();
}
arch_initcall(arm64_dma_init);
@@ -882,6 +891,14 @@ static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
const struct iommu_ops *iommu, bool coherent)
{
+ /*
+ * Enable swiotlb for buffer bouncing if ARCH_DMA_MINALIGN < CWG.
+ * dma_capable() forces the actual bounce if the device is
+ * non-coherent.
+ */
+ if (static_branch_unlikely(&swiotlb_noncoherent_bounce) && !coherent)
+ iommu = NULL;
+
if (!dev->dma_ops)
dev->dma_ops = &arm64_swiotlb_dma_ops;
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 9f3c47acf8ff..664acf177799 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -586,7 +586,8 @@ static void __init free_unused_memmap(void)
void __init mem_init(void)
{
if (swiotlb_force == SWIOTLB_FORCE ||
- max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT))
+ max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT) ||
+ ARCH_DMA_MINALIGN < cache_line_size())
swiotlb_init(1);
else
swiotlb_force = SWIOTLB_NO_FORCE;
^ permalink raw reply related
* [PATCH 04/20] arm-nommu: use generic dma_noncoherent_ops
From: John Garry @ 2018-05-11 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511075945.16548-5-hch@lst.de>
On 11/05/2018 08:59, Christoph Hellwig wrote:
> Switch to the generic noncoherent direct mapping implementation for
> the nommu dma map implementation.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> arch/arc/Kconfig | 1 +
> arch/arm/Kconfig | 4 +
> arch/arm/mm/dma-mapping-nommu.c | 139 +++++---------------------------
> 3 files changed, 23 insertions(+), 121 deletions(-)
>
> diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
> index 89d47eac18b2..3a492a9aeaad 100644
> --- a/arch/arc/Kconfig
> +++ b/arch/arc/Kconfig
> @@ -9,6 +9,7 @@
> config ARC
> def_bool y
> select ARC_TIMERS
> + select ARCH_HAS_SYNC_DMA_FOR_DEVICE
> select ARCH_HAS_SYNC_DMA_FOR_CPU
> select ARCH_HAS_SYNC_DMA_FOR_DEVICE
I guess that this arc change is here by accident, no? And isn't
ARCH_HAS_SYNC_DMA_FOR_DEVICE already selected (by 3/20)?
> select ARCH_HAS_SG_CHAIN
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index c43f5bb55ac8..76ddd0064f87 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
^ permalink raw reply
* [PATCH 1/3] arm64: dts: hi3798cv200: enable PCIe support for poplar board
From: Wei Xu @ 2018-05-11 13:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526004220-17030-1-git-send-email-shawn.guo@linaro.org>
Hi Shawn,
On 2018/5/11 3:03, Shawn Guo wrote:
> It adds combophy devices under peripheral controller and enables PCIe
> support for Hi3798CV200 Poplar board.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Series applied into the hisilicon dt tree.
Thanks!
BR,
Wei
> ---
> .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 15 ++++++
> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 63 ++++++++++++++++++++++
> 2 files changed, 78 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
> index 4d5d644abb12..c4382e1f3c92 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
> @@ -61,6 +61,15 @@
> default-state = "off";
> };
> };
> +
> + reg_pcie: regulator-pcie {
> + compatible = "regulator-fixed";
> + regulator-name = "3V3_PCIE0";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio6 7 0>;
> + enable-active-high;
> + };
> };
>
> &gmac1 {
> @@ -146,6 +155,12 @@
> status = "okay";
> };
>
> +&pcie {
> + reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
> + vpcie-supply = <®_pcie>;
> + status = "okay";
> +};
> +
> &sd0 {
> bus-width = <4>;
> cap-sd-highspeed;
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
> index 962bd79139e4..5b73403551e6 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
> @@ -8,7 +8,9 @@
> */
>
> #include <dt-bindings/clock/histb-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/reset/ti-syscon.h>
>
> / {
> @@ -106,6 +108,37 @@
> #reset-cells = <2>;
> };
>
> + perictrl: peripheral-controller at 8a20000 {
> + compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
> + "simple-mfd";
> + reg = <0x8a20000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x8a20000 0x1000>;
> +
> + combphy0: phy at 850 {
> + compatible = "hisilicon,hi3798cv200-combphy";
> + reg = <0x850 0x8>;
> + #phy-cells = <1>;
> + clocks = <&crg HISTB_COMBPHY0_CLK>;
> + resets = <&crg 0x188 4>;
> + assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
> + assigned-clock-rates = <100000000>;
> + hisilicon,fixed-mode = <PHY_TYPE_USB3>;
> + };
> +
> + combphy1: phy at 858 {
> + compatible = "hisilicon,hi3798cv200-combphy";
> + reg = <0x858 0x8>;
> + #phy-cells = <1>;
> + clocks = <&crg HISTB_COMBPHY1_CLK>;
> + resets = <&crg 0x188 12>;
> + assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
> + assigned-clock-rates = <100000000>;
> + hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
> + };
> + };
> +
> uart0: serial at 8b00000 {
> compatible = "arm,pl011", "arm,primecell";
> reg = <0x8b00000 0x1000>;
> @@ -419,5 +452,35 @@
> clocks = <&sysctrl HISTB_IR_CLK>;
> status = "disabled";
> };
> +
> + pcie: pcie at 9860000 {
> + compatible = "hisilicon,hi3798cv200-pcie";
> + reg = <0x9860000 0x1000>,
> + <0x0 0x2000>,
> + <0x2000000 0x01000000>;
> + reg-names = "control", "rc-dbi", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + bus-range = <0 15>;
> + num-lanes = <1>;
> + ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
> + 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&crg HISTB_PCIE_AUX_CLK>,
> + <&crg HISTB_PCIE_PIPE_CLK>,
> + <&crg HISTB_PCIE_SYS_CLK>,
> + <&crg HISTB_PCIE_BUS_CLK>;
> + clock-names = "aux", "pipe", "sys", "bus";
> + resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
> + reset-names = "soft", "sys", "bus";
> + phys = <&combphy1 PHY_TYPE_PCIE>;
> + phy-names = "phy";
> + status = "disabled";
> + };
> };
> };
>
^ permalink raw reply
* [PATCH 0/3] HiSilicon LPC defconfig and DT patches
From: Wei Xu @ 2018-05-11 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525101342-27120-1-git-send-email-john.garry@huawei.com>
Hi John,
On 2018/4/30 16:15, John Garry wrote:
> This series introduces 3 patches, to enable the
> HISILICON_LPC config in the arm64 defconfig
> and also add the relevant LPC DT entries.
>
> For hip06 UART support, we depend on this patch:
> https://lkml.org/lkml/2018/4/27/258
>
> John Garry (3):
> arm64: defconfig: Enable HISILICON_LPC
> arm64: dts: hisi: Enable Hisi LPC node for hip06
> arm64: dts: hisi: Enable Hisi LPC node for hip07
>
> arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 8 ++++++++
> arch/arm64/boot/dts/hisilicon/hip06.dtsi | 21 +++++++++++++++++++++
> arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 4 ++++
> arch/arm64/boot/dts/hisilicon/hip07.dtsi | 14 ++++++++++++++
> arch/arm64/configs/defconfig | 1 +
> 5 files changed, 48 insertions(+)
>
Series applied into the hisilicon tree.
Thanks!
BR,
Wei
^ permalink raw reply
* [PATCH 5/5] hisi: Consolidate the Kconfigs for the CLOCK_STUB and the MAILBOX
From: Wei Xu @ 2018-05-11 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180509040255.GF23540@leoy-ThinkPad-X240s>
Hi Leo,
On 2018/5/9 5:02, Leo Yan wrote:
> On Wed, May 09, 2018 at 09:19:13AM +0530, Jassi Brar wrote:
>> On Wed, Apr 4, 2018 at 8:44 AM, Leo Yan <leo.yan@linaro.org> wrote:
>>> From: Daniel Lezcano <daniel.lezcano@linaro.org>
>>>
>>> The current defconfig is inconsistent as it selects the mailbox and
>>> the clock for the hi6220 and the hi3660 without having their Kconfigs
>>> making sure the dependencies are correct. It ends up when selecting
>>> different versions for the kernel (for example when git bisecting)
>>> those options disappear and they don't get back, leading to unexpected
>>> behaviors. In our case, the cpufreq driver does no longer work because
>>> the clock fails to initialize due to the clock stub and the mailbox
>>> missing.
>>>
>>> In order to have the dependencies correctly set when defaulting, let's
>>> do the same as commit 3a49afb84ca074e ("clk: enable hi655x common clk
>>> automatically") where we select automatically the driver when the
>>> parent driver is selected. With sensible defaults in place, we can leave
>>> other choices for EXPERT.
>>>
>> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
>
> Thanks Jassi & Stephen.
>
> Wei, could you pick this patch?
Thanks!
Series applied into the hisilicon tree.
BR,
Wei
>
> Thanks,
> Leo Yan
>
> .
>
^ permalink raw reply
* [PATCH v3 2/2] arm64: dts: hi3660: Add pcie msi interrupt attribute
From: Wei Xu @ 2018-05-11 14:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526030149-23985-3-git-send-email-chenyao11@huawei.com>
Hi Yao,
On 2018/5/11 10:15, Yao Chen wrote:
> Add pcie msi interrupt attribute for hi3660 SOC.
>
> Signed-off-by: Yao Chen <chenyao11@huawei.com>
Applied patch 2 into the hisilicon dt tree.
Thanks!
BR,
Wei
> ---
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index ec3eb8e..2cef8f4 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -872,6 +872,8 @@
> 0x0 0x02000000>;
> num-lanes = <1>;
> #interrupt-cells = <1>;
> + interrupts = <0 283 4>;
> + interrupt-names = "msi";
> interrupt-map-mask = <0xf800 0 0 7>;
> interrupt-map = <0x0 0 0 1
> &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
>
^ permalink raw reply
* [PATCH 0/2] clk: davinci: some more fixes
From: Sekhar Nori @ 2018-05-11 14:10 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Some more fixes to make DM646x and DM365 EVMs boot after
common clock framework conversion. With this, I have tested
all DaVinci SoCs.
Sekhar Nori (2):
clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
clk: davinci: psc-dm365: fix few clocks
drivers/clk/davinci/pll-dm646x.c | 2 +-
drivers/clk/davinci/psc-dm365.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
--
2.16.2
^ permalink raw reply
* [PATCH 1/2] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
From: Sekhar Nori @ 2018-05-11 14:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511141037.25250-1-nsekhar@ti.com>
PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
drivers/clk/davinci/pll-dm646x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/davinci/pll-dm646x.c b/drivers/clk/davinci/pll-dm646x.c
index eb96dd72b6b7..5bdf1cb5fda8 100644
--- a/drivers/clk/davinci/pll-dm646x.c
+++ b/drivers/clk/davinci/pll-dm646x.c
@@ -72,7 +72,7 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = {
.flags = 0,
};
-SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);
int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
--
2.16.2
^ permalink raw reply related
* [PATCH 2/2] clk: davinci: psc-dm365: fix few clocks
From: Sekhar Nori @ 2018-05-11 14:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511141037.25250-1-nsekhar@ti.com>
Fix parent of emac and voice codec PSC clocks. This now matches
existing implementation in arch/arm/mach-davinci/dm365.c
Also, there is only one power domain on DM365. Fix the power
domain of voice codec and vpss dac modules.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
drivers/clk/davinci/psc-dm365.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/davinci/psc-dm365.c b/drivers/clk/davinci/psc-dm365.c
index 5b5b55b0b59a..beeda10fd2f0 100644
--- a/drivers/clk/davinci/psc-dm365.c
+++ b/drivers/clk/davinci/psc-dm365.c
@@ -65,9 +65,9 @@ static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
LPSC(31, 0, arm, pll2_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
LPSC(38, 0, spi3, pll1_sysclk4, spi3_clkdev, 0),
LPSC(39, 0, spi4, pll1_auxclk, spi4_clkdev, 0),
- LPSC(40, 0, emac, pll2_sysclk4, emac_clkdev, 0),
- LPSC(44, 1, voice_codec, pll1_sysclk3, voice_codec_clkdev, 0),
- LPSC(46, 1, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
+ LPSC(40, 0, emac, pll1_sysclk4, emac_clkdev, 0),
+ LPSC(44, 0, voice_codec, pll2_sysclk4, voice_codec_clkdev, 0),
+ LPSC(46, 0, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
LPSC(50, 0, mjcp, pll1_sysclk3, NULL, 0),
{ }
--
2.16.2
^ permalink raw reply related
* [PATCH v2] arm64: signal: Report signal frame size to userspace via auxv
From: Dave Martin @ 2018-05-11 14:10 UTC (permalink / raw)
To: linux-arm-kernel
Stateful CPU architecture extensions may require the signal frame
to grow to a size that exceeds the arch's MINSIGSTKSZ #define.
However, changing this #define is an ABI break.
To allow userspace the option of determining the signal frame size
in a more forwards-compatible way, this patch adds a new auxv entry
tagged with AT_MINSIGSTKSZ, which provides the maximum signal frame
size that the process can observe during its lifetime.
If AT_MINSIGSTKSZ is absent from the aux vector, the caller can
assume that the MINSIGSTKSZ #define is sufficient. This allows for
a consistent interface with older kernels that do not provide
AT_MINSIGSTKSZ.
The idea is that libc could expose this via sysconf() or some
similar mechanism.
There is deliberately no AT_SIGSTKSZ. The kernel knows nothing
about userspace's own stack overheads and should not pretend to
know.
For arm64:
The primary motivation for this interface is the Scalable Vector
Extension, which can require at least 4KB or so of extra space
in the signal frame for the largest hardware implementations.
To determine the correct value, a "Christmas tree" mode (via the
add_all argument) is added to setup_sigframe_layout(), to simulate
addition of all possible records to the signal frame at maximum
possible size.
If this procedure goes wrong somehow, resulting in a stupidly large
frame layout and hence failure of sigframe_alloc() to allocate a
record to the frame, then this is indicative of a kernel bug: the
kernel's internal SIGFRAME_MAXSZ is supposed to sanity-check
against generting frames that we consider _impossibly_ large. In
this case, SIGSTKSZ is returned as a "reasonable guess that is at
least bigger than MINSIGSTKSZ" and we WARN().
For arm64 SVE:
The SVE context block in the signal frame needs to be considered
too when computing the maximum possible signal frame size.
Because the size of this block depends on the vector length, this
patch computes the size based not on the thread's current vector
length but instead on the maximum possible vector length: this
determines the maximum size of SVE context block that can be
observed in any signal frame for the lifetime of the process.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Alex Benn?e <alex.bennee@linaro.org>
---
Changes since v1 [1]:
* Merged the SVE frame size computation into this patch. It
no longer makes sense for it to be separate, and without the
latter patch an incorrect overall value is computed anyway.
Best to avoid this.
Suggested by Mark Rutland:
* Hook the minsigstksz initialisation into the end of cpufeatures
setup so that we don't have to worry about parallelism. It's
reasonable to assume that the sigframe size is known by this point
(and currently the case).
[1] [PATCH 0/2] arm64: Report signal frame size to userspace via auxv
http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576269.html
---
arch/arm64/include/asm/elf.h | 11 ++++++++
arch/arm64/include/asm/processor.h | 5 ++++
arch/arm64/include/uapi/asm/auxvec.h | 3 ++-
arch/arm64/kernel/cpufeature.c | 1 +
arch/arm64/kernel/signal.c | 51 +++++++++++++++++++++++++++++++-----
5 files changed, 63 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index fac1c4d..dc32adb 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -24,6 +24,11 @@
#include <asm/ptrace.h>
#include <asm/user.h>
+#ifndef __ASSEMBLY__
+#include <linux/bug.h>
+#include <asm/processor.h> /* for signal_minsigstksz, used by ARCH_DLINFO */
+#endif
+
/*
* AArch64 static relocation types.
*/
@@ -146,8 +151,14 @@ typedef struct user_fpsimd_state elf_fpregset_t;
/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
#define ARCH_DLINFO \
do { \
+ int minsigstksz = signal_minsigstksz; \
+ \
+ if (WARN_ON(minsigstksz <= 0)) \
+ minsigstksz = MINSIGSTKSZ; \
+ \
NEW_AUX_ENT(AT_SYSINFO_EHDR, \
(elf_addr_t)current->mm->context.vdso); \
+ NEW_AUX_ENT(AT_MINSIGSTKSZ, minsigstksz); \
} while (0)
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 7675989..6f60e92 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -35,6 +35,8 @@
#ifdef __KERNEL__
#include <linux/build_bug.h>
+#include <linux/cache.h>
+#include <linux/init.h>
#include <linux/stddef.h>
#include <linux/string.h>
@@ -244,6 +246,9 @@ void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused);
void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused);
void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused);
+extern int __ro_after_init signal_minsigstksz; /* user signal frame size */
+extern void __init minsigstksz_setup(void);
+
/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
#define SVE_SET_VL(arg) sve_set_current_vl(arg)
#define SVE_GET_VL() sve_get_current_vl()
diff --git a/arch/arm64/include/uapi/asm/auxvec.h b/arch/arm64/include/uapi/asm/auxvec.h
index ec0a86d..a35797e 100644
--- a/arch/arm64/include/uapi/asm/auxvec.h
+++ b/arch/arm64/include/uapi/asm/auxvec.h
@@ -19,7 +19,8 @@
/* vDSO location */
#define AT_SYSINFO_EHDR 33
+#define AT_MINSIGSTKSZ 34 /* stack needed for signal delivery */
-#define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */
+#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
#endif
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9d1b06d..0e0b53d 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1619,6 +1619,7 @@ void __init setup_cpu_features(void)
pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
sve_setup();
+ minsigstksz_setup();
/* Advertise that we have computed the system capabilities */
set_sys_caps_initialised();
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index 154b7d3..ae8d4ea 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -17,6 +17,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <linux/cache.h>
#include <linux/compat.h>
#include <linux/errno.h>
#include <linux/kernel.h>
@@ -570,8 +571,15 @@ asmlinkage long sys_rt_sigreturn(struct pt_regs *regs)
return 0;
}
-/* Determine the layout of optional records in the signal frame */
-static int setup_sigframe_layout(struct rt_sigframe_user_layout *user)
+/*
+ * Determine the layout of optional records in the signal frame
+ *
+ * add_all: if true, lays out the biggest possible signal frame for
+ * this task; otherwise, generates a layout for the current state
+ * of the task.
+ */
+static int setup_sigframe_layout(struct rt_sigframe_user_layout *user,
+ bool add_all)
{
int err;
@@ -581,7 +589,7 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user)
return err;
/* fault information, if valid */
- if (current->thread.fault_code) {
+ if (add_all || current->thread.fault_code) {
err = sigframe_alloc(user, &user->esr_offset,
sizeof(struct esr_context));
if (err)
@@ -591,8 +599,18 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user)
if (system_supports_sve()) {
unsigned int vq = 0;
- if (test_thread_flag(TIF_SVE))
- vq = sve_vq_from_vl(current->thread.sve_vl);
+ if (add_all || test_thread_flag(TIF_SVE)) {
+ int vl = sve_max_vl;
+
+ if (!add_all)
+ vl = current->thread.sve_vl;
+
+ /* Fail safe if something wasn't initialised */
+ if (WARN_ON(!sve_vl_valid(vl)))
+ vl = SVE_VL_MIN;
+
+ vq = sve_vq_from_vl(vl);
+ }
err = sigframe_alloc(user, &user->sve_offset,
SVE_SIG_CONTEXT_SIZE(vq));
@@ -603,7 +621,6 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user)
return sigframe_alloc_end(user);
}
-
static int setup_sigframe(struct rt_sigframe_user_layout *user,
struct pt_regs *regs, sigset_t *set)
{
@@ -701,7 +718,7 @@ static int get_sigframe(struct rt_sigframe_user_layout *user,
int err;
init_user_layout(user);
- err = setup_sigframe_layout(user);
+ err = setup_sigframe_layout(user, false);
if (err)
return err;
@@ -936,3 +953,23 @@ asmlinkage void do_notify_resume(struct pt_regs *regs,
thread_flags = READ_ONCE(current_thread_info()->flags);
} while (thread_flags & _TIF_WORK_MASK);
}
+
+int __ro_after_init signal_minsigstksz;
+
+/*
+ * Determine the stack space required for guaranteed signal devliery.
+ * This function is used to populate AT_MINSIGSTKSZ at process startup.
+ */
+void __init minsigstksz_setup(void)
+{
+ struct rt_sigframe_user_layout user;
+
+ init_user_layout(&user);
+
+ if (WARN_ON(setup_sigframe_layout(&user, true)))
+ signal_minsigstksz = SIGSTKSZ;
+ else
+ signal_minsigstksz = sigframe_size(&user) +
+ round_up(sizeof(struct frame_record), 16) +
+ 16; /* max alignment padding */
+}
--
2.1.4
^ permalink raw reply related
* [GIT PULL] arm64: dts: hisilicon dts updates for v4.18
From: Wei Xu @ 2018-05-11 14:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Hi Olof,
Please help to pull the following changes.
Thanks!
Best Regards,
Wei
---
The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
are available in the Git repository at:
git://github.com/hisilicon/linux-hisi.git tags/hisi-arm64-dt-for-4.18
for you to fetch changes up to 84f7ed0f22e8eb42e81b69cd7772c3600c9f4959:
arm64: dts: hi3798cv200: enable emmc support for poplar board (2018-05-11 11:23:10 +0100)
----------------------------------------------------------------
ARM64: DT: Hisilicon SoC DT updates for 4.18
- Add mailbox, stub clock, CPU frequency scaling, thermal cooling
management and pcie msi interruption support for hi3660
- Add LPC support for hip06 and hip07
- Add PCIe, usb and emmc support for hi3798cv200
----------------------------------------------------------------
John Garry (2):
arm64: dts: hisi: Enable Hisi LPC node for hip06
arm64: dts: hisi: Enable Hisi LPC node for hip07
Kaihua Zhong (2):
dts: arm64: hi3660: Add mailbox node
dts: arm64: hi3660: Add stub clock node
Leo Yan (1):
dts: arm64: hi3660: Add CPU frequency scaling support
Shawn Guo (3):
arm64: dts: hi3798cv200: enable PCIe support for poplar board
arm64: dts: hi3798cv200: enable usb2 support for poplar board
arm64: dts: hi3798cv200: enable emmc support for poplar board
Tao Wang (1):
dts: arm64: hi3660: Add thermal cooling management
Yao Chen (1):
arm64: dts: hi3660: Add pcie msi interrupt attribute
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 147 +++++++++++++++
.../boot/dts/hisilicon/hi3798cv200-poplar.dts | 38 ++++
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 205 ++++++++++++++++++++-
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 8 +
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 21 +++
arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 4 +
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 14 ++
arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi | 98 ++++++++++
8 files changed, 532 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi
^ permalink raw reply
* [PATCH 0/4] KVM: arm/arm64: Fix locking issues
From: Andre Przywara @ 2018-05-11 14:20 UTC (permalink / raw)
To: linux-arm-kernel
Jan recently reported lockdep complaints regarding various locks in our
VGIC emulation [1][2].
This boiled down to two separate issues:
- When promoting the vgic_irq->irq_lock to require IRQs being disabled,
we forgot to amend some instances of this lock on the way. Also this
needs to be applied to dependent locks as well. The first two patches
fix that. The patch split is designed to simplify backporting.
Those patches have been posted before, I am resending them as part
of this series.
- Calling kvm_read_guest() requires us to be inside an SRCU critical
section. On some architectures we are always in it when handling VCPU
exits, but on ARM we need to lock it individually. Patches 3 and 4
fix that, the split is again made to ease backporting.
Each of the hunks fix an indiviual commit, but I refrained from
splitting this down into eight patches just to put proper Fixes: tags
on it. Eventually those commits are part of one out of two series, I put
the respective kernel release version as a tag to the Cc: stable line.
I couldn't reproduce the full lockdep splat on my setup, but at least
could show one instance and prove that these patches fixes that.
Thanks to Jan for reporting.
Cheers,
Andre.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/575718.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/575833.html
Andre Przywara (4):
KVM: ARM: Properly protect VGIC locks from IRQs
KVM: ARM: VGIC/ITS: Promote irq_lock() in update_affinity
KVM: arm/arm64: VGIC/ITS: protect kvm_read_guest() calls with SRCU lock
KVM: arm/arm64: VGIC/ITS save/restore: protect kvm_read_guest() calls
arch/arm/include/asm/kvm_mmu.h | 16 ++++++++++++++++
arch/arm64/include/asm/kvm_mmu.h | 16 ++++++++++++++++
virt/kvm/arm/vgic/vgic-debug.c | 5 +++--
virt/kvm/arm/vgic/vgic-its.c | 34 +++++++++++++++++++---------------
virt/kvm/arm/vgic/vgic-v3.c | 4 ++--
virt/kvm/arm/vgic/vgic.c | 22 ++++++++++++++--------
6 files changed, 70 insertions(+), 27 deletions(-)
--
2.14.1
^ permalink raw reply
* [PATCH 1/4] KVM: arm/arm64: Properly protect VGIC locks from IRQs
From: Andre Przywara @ 2018-05-11 14:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511142015.21953-1-andre.przywara@arm.com>
As Jan reported [1], lockdep complains about the VGIC not being bullet
proof. This seems to be due to two issues:
- When commit 006df0f34930 ("KVM: arm/arm64: Support calling
vgic_update_irq_pending from irq context") promoted irq_lock and
ap_list_lock to _irqsave, we forgot two instances of irq_lock.
lockdeps seems to pick those up.
- If a lock is _irqsave, any other locks we take inside them should be
_irqsafe as well. So the lpi_list_lock needs to be promoted also.
This fixes both issues by simply making the remaining instances of those
locks _irqsave.
One irq_lock is addressed in a separate patch, to simplify backporting.
Cc: stable at vger.kernel.org
Fixes: 006df0f34930 ("KVM: arm/arm64: Support calling vgic_update_irq_pending from irq context")
Reported-by: Jan Glauber <jan.glauber@caviumnetworks.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/575718.html
---
virt/kvm/arm/vgic/vgic-debug.c | 5 +++--
virt/kvm/arm/vgic/vgic-its.c | 10 ++++++----
virt/kvm/arm/vgic/vgic.c | 22 ++++++++++++++--------
3 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-debug.c b/virt/kvm/arm/vgic/vgic-debug.c
index 10b38178cff2..4ffc0b5e6105 100644
--- a/virt/kvm/arm/vgic/vgic-debug.c
+++ b/virt/kvm/arm/vgic/vgic-debug.c
@@ -211,6 +211,7 @@ static int vgic_debug_show(struct seq_file *s, void *v)
struct vgic_state_iter *iter = (struct vgic_state_iter *)v;
struct vgic_irq *irq;
struct kvm_vcpu *vcpu = NULL;
+ unsigned long flags;
if (iter->dist_id == 0) {
print_dist_state(s, &kvm->arch.vgic);
@@ -227,9 +228,9 @@ static int vgic_debug_show(struct seq_file *s, void *v)
irq = &kvm->arch.vgic.spis[iter->intid - VGIC_NR_PRIVATE_IRQS];
}
- spin_lock(&irq->irq_lock);
+ spin_lock_irqsave(&irq->irq_lock, flags);
print_irq_state(s, irq, vcpu);
- spin_unlock(&irq->irq_lock);
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
return 0;
}
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index a8f07243aa9f..41abf92f2699 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -52,6 +52,7 @@ static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid,
{
struct vgic_dist *dist = &kvm->arch.vgic;
struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intid), *oldirq;
+ unsigned long flags;
int ret;
/* In this case there is no put, since we keep the reference. */
@@ -71,7 +72,7 @@ static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid,
irq->intid = intid;
irq->target_vcpu = vcpu;
- spin_lock(&dist->lpi_list_lock);
+ spin_lock_irqsave(&dist->lpi_list_lock, flags);
/*
* There could be a race with another vgic_add_lpi(), so we need to
@@ -99,7 +100,7 @@ static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid,
dist->lpi_list_count++;
out_unlock:
- spin_unlock(&dist->lpi_list_lock);
+ spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
/*
* We "cache" the configuration table entries in our struct vgic_irq's.
@@ -315,6 +316,7 @@ static int vgic_copy_lpi_list(struct kvm_vcpu *vcpu, u32 **intid_ptr)
{
struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
struct vgic_irq *irq;
+ unsigned long flags;
u32 *intids;
int irq_count, i = 0;
@@ -330,7 +332,7 @@ static int vgic_copy_lpi_list(struct kvm_vcpu *vcpu, u32 **intid_ptr)
if (!intids)
return -ENOMEM;
- spin_lock(&dist->lpi_list_lock);
+ spin_lock_irqsave(&dist->lpi_list_lock, flags);
list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
if (i == irq_count)
break;
@@ -339,7 +341,7 @@ static int vgic_copy_lpi_list(struct kvm_vcpu *vcpu, u32 **intid_ptr)
continue;
intids[i++] = irq->intid;
}
- spin_unlock(&dist->lpi_list_lock);
+ spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
*intid_ptr = intids;
return i;
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index 27219313a406..1dfb5b2f1b12 100644
--- a/virt/kvm/arm/vgic/vgic.c
+++ b/virt/kvm/arm/vgic/vgic.c
@@ -43,9 +43,13 @@ struct vgic_global kvm_vgic_global_state __ro_after_init = {
* kvm->lock (mutex)
* its->cmd_lock (mutex)
* its->its_lock (mutex)
- * vgic_cpu->ap_list_lock
- * kvm->lpi_list_lock
- * vgic_irq->irq_lock
+ * vgic_cpu->ap_list_lock must be taken with IRQs disabled
+ * kvm->lpi_list_lock must be taken with IRQs disabled
+ * vgic_irq->irq_lock must be taken with IRQs disabled
+ *
+ * As the ap_list_lock might be taken from the timer interrupt handler,
+ * we have to disable IRQs before taking this lock and everything lower
+ * than it.
*
* If you need to take multiple locks, always take the upper lock first,
* then the lower ones, e.g. first take the its_lock, then the irq_lock.
@@ -72,8 +76,9 @@ static struct vgic_irq *vgic_get_lpi(struct kvm *kvm, u32 intid)
{
struct vgic_dist *dist = &kvm->arch.vgic;
struct vgic_irq *irq = NULL;
+ unsigned long flags;
- spin_lock(&dist->lpi_list_lock);
+ spin_lock_irqsave(&dist->lpi_list_lock, flags);
list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
if (irq->intid != intid)
@@ -89,7 +94,7 @@ static struct vgic_irq *vgic_get_lpi(struct kvm *kvm, u32 intid)
irq = NULL;
out_unlock:
- spin_unlock(&dist->lpi_list_lock);
+ spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
return irq;
}
@@ -134,19 +139,20 @@ static void vgic_irq_release(struct kref *ref)
void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq)
{
struct vgic_dist *dist = &kvm->arch.vgic;
+ unsigned long flags;
if (irq->intid < VGIC_MIN_LPI)
return;
- spin_lock(&dist->lpi_list_lock);
+ spin_lock_irqsave(&dist->lpi_list_lock, flags);
if (!kref_put(&irq->refcount, vgic_irq_release)) {
- spin_unlock(&dist->lpi_list_lock);
+ spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
return;
};
list_del(&irq->lpi_list);
dist->lpi_list_count--;
- spin_unlock(&dist->lpi_list_lock);
+ spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
kfree(irq);
}
--
2.14.1
^ permalink raw reply related
* [PATCH 2/4] KVM: arm/arm64: VGIC/ITS: Promote irq_lock() in update_affinity
From: Andre Przywara @ 2018-05-11 14:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511142015.21953-1-andre.przywara@arm.com>
Apparently the development of update_affinity() overlapped with the
promotion of irq_lock to be _irqsave, so the patch didn't convert this
lock over. This will make lockdep complain.
Fix this by disabling IRQs around the lock.
Cc: stable at vger.kernel.org
Fixes: 08c9fd042117 ("KVM: arm/arm64: vITS: Add a helper to update the affinity of an LPI")
Reported-by: Jan Glauber <jan.glauber@caviumnetworks.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
virt/kvm/arm/vgic/vgic-its.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 41abf92f2699..51a80b600632 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -350,10 +350,11 @@ static int vgic_copy_lpi_list(struct kvm_vcpu *vcpu, u32 **intid_ptr)
static int update_affinity(struct vgic_irq *irq, struct kvm_vcpu *vcpu)
{
int ret = 0;
+ unsigned long flags;
- spin_lock(&irq->irq_lock);
+ spin_lock_irqsave(&irq->irq_lock, flags);
irq->target_vcpu = vcpu;
- spin_unlock(&irq->irq_lock);
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
if (irq->hw) {
struct its_vlpi_map map;
--
2.14.1
^ permalink raw reply related
* [PATCH 3/4] KVM: arm/arm64: VGIC/ITS: protect kvm_read_guest() calls with SRCU lock
From: Andre Przywara @ 2018-05-11 14:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511142015.21953-1-andre.przywara@arm.com>
kvm_read_guest() will eventually look up in kvm_memslots(), which requires
either to hold the kvm->slots_lock or to be inside a kvm->srcu critical
section.
In contrast to x86 and s390 we don't take the SRCU lock on every guest
exit, so we have to do it individually for each kvm_read_guest() call.
Provide a wrapper which does that and use that everywhere.
Note that ending the SRCU critical section before returning from the
kvm_read_guest() wrapper is safe, because the data has been *copied*, so
we don't need to rely on valid references to the memslot anymore.
Cc: Stable <stable@vger.kernel.org> # 4.8+
Reported-by: Jan Glauber <jan.glauber@caviumnetworks.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/include/asm/kvm_mmu.h | 16 ++++++++++++++++
arch/arm64/include/asm/kvm_mmu.h | 16 ++++++++++++++++
virt/kvm/arm/vgic/vgic-its.c | 15 ++++++++-------
3 files changed, 40 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 707a1f06dc5d..f675162663f0 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -309,6 +309,22 @@ static inline unsigned int kvm_get_vmid_bits(void)
return 8;
}
+/*
+ * We are not in the kvm->srcu critical section most of the time, so we take
+ * the SRCU read lock here. Since we copy the data from the user page, we
+ * can immediately drop the lock again.
+ */
+static inline int kvm_read_guest_lock(struct kvm *kvm,
+ gpa_t gpa, void *data, unsigned long len)
+{
+ int srcu_idx = srcu_read_lock(&kvm->srcu);
+ int ret = kvm_read_guest(kvm, gpa, data, len);
+
+ srcu_read_unlock(&kvm->srcu, srcu_idx);
+
+ return ret;
+}
+
static inline void *kvm_get_hyp_vector(void)
{
return kvm_ksym_ref(__kvm_hyp_vector);
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 082110993647..6128992c2ded 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -360,6 +360,22 @@ static inline unsigned int kvm_get_vmid_bits(void)
return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8;
}
+/*
+ * We are not in the kvm->srcu critical section most of the time, so we take
+ * the SRCU read lock here. Since we copy the data from the user page, we
+ * can immediately drop the lock again.
+ */
+static inline int kvm_read_guest_lock(struct kvm *kvm,
+ gpa_t gpa, void *data, unsigned long len)
+{
+ int srcu_idx = srcu_read_lock(&kvm->srcu);
+ int ret = kvm_read_guest(kvm, gpa, data, len);
+
+ srcu_read_unlock(&kvm->srcu, srcu_idx);
+
+ return ret;
+}
+
#ifdef CONFIG_KVM_INDIRECT_VECTORS
/*
* EL2 vectors can be mapped and rerouted in a number of ways,
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 51a80b600632..7cb060e01a76 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -281,8 +281,8 @@ static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
int ret;
unsigned long flags;
- ret = kvm_read_guest(kvm, propbase + irq->intid - GIC_LPI_OFFSET,
- &prop, 1);
+ ret = kvm_read_guest_lock(kvm, propbase + irq->intid - GIC_LPI_OFFSET,
+ &prop, 1);
if (ret)
return ret;
@@ -444,8 +444,9 @@ static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
* this very same byte in the last iteration. Reuse that.
*/
if (byte_offset != last_byte_offset) {
- ret = kvm_read_guest(vcpu->kvm, pendbase + byte_offset,
- &pendmask, 1);
+ ret = kvm_read_guest_lock(vcpu->kvm,
+ pendbase + byte_offset,
+ &pendmask, 1);
if (ret) {
kfree(intids);
return ret;
@@ -789,7 +790,7 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id,
return false;
/* Each 1st level entry is represented by a 64-bit value. */
- if (kvm_read_guest(its->dev->kvm,
+ if (kvm_read_guest_lock(its->dev->kvm,
BASER_ADDRESS(baser) + index * sizeof(indirect_ptr),
&indirect_ptr, sizeof(indirect_ptr)))
return false;
@@ -1370,8 +1371,8 @@ static void vgic_its_process_commands(struct kvm *kvm, struct vgic_its *its)
cbaser = CBASER_ADDRESS(its->cbaser);
while (its->cwriter != its->creadr) {
- int ret = kvm_read_guest(kvm, cbaser + its->creadr,
- cmd_buf, ITS_CMD_SIZE);
+ int ret = kvm_read_guest_lock(kvm, cbaser + its->creadr,
+ cmd_buf, ITS_CMD_SIZE);
/*
* If kvm_read_guest() fails, this could be due to the guest
* programming a bogus value in CBASER or something else going
--
2.14.1
^ permalink raw reply related
* [PATCH 4/4] KVM: arm/arm64: VGIC/ITS save/restore: protect kvm_read_guest() calls
From: Andre Przywara @ 2018-05-11 14:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180511142015.21953-1-andre.przywara@arm.com>
kvm_read_guest() will eventually look up in kvm_memslots(), which requires
either to hold the kvm->slots_lock or to be inside a kvm->srcu critical
section.
In contrast to x86 and s390 we don't take the SRCU lock on every guest
exit, so we have to do it individually for each kvm_read_guest() call.
Use the newly introduced wrapper for that.
Cc: Stable <stable@vger.kernel.org> # 4.12+
Reported-by: Jan Glauber <jan.glauber@caviumnetworks.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
virt/kvm/arm/vgic/vgic-its.c | 4 ++--
virt/kvm/arm/vgic/vgic-v3.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 7cb060e01a76..4ed79c939fb4 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -1897,7 +1897,7 @@ static int scan_its_table(struct vgic_its *its, gpa_t base, int size, int esz,
int next_offset;
size_t byte_offset;
- ret = kvm_read_guest(kvm, gpa, entry, esz);
+ ret = kvm_read_guest_lock(kvm, gpa, entry, esz);
if (ret)
return ret;
@@ -2267,7 +2267,7 @@ static int vgic_its_restore_cte(struct vgic_its *its, gpa_t gpa, int esz)
int ret;
BUG_ON(esz > sizeof(val));
- ret = kvm_read_guest(kvm, gpa, &val, esz);
+ ret = kvm_read_guest_lock(kvm, gpa, &val, esz);
if (ret)
return ret;
val = le64_to_cpu(val);
diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
index c7423f3768e5..bdcf8e7a6161 100644
--- a/virt/kvm/arm/vgic/vgic-v3.c
+++ b/virt/kvm/arm/vgic/vgic-v3.c
@@ -344,7 +344,7 @@ int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
bit_nr = irq->intid % BITS_PER_BYTE;
ptr = pendbase + byte_offset;
- ret = kvm_read_guest(kvm, ptr, &val, 1);
+ ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
if (ret)
return ret;
@@ -397,7 +397,7 @@ int vgic_v3_save_pending_tables(struct kvm *kvm)
ptr = pendbase + byte_offset;
if (byte_offset != last_byte_offset) {
- ret = kvm_read_guest(kvm, ptr, &val, 1);
+ ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
if (ret)
return ret;
last_byte_offset = byte_offset;
--
2.14.1
^ permalink raw reply related
* [PATCH 0/3] perf: make Arm CCI driver modular
From: Robin Murphy @ 2018-05-11 14:29 UTC (permalink / raw)
To: linux-arm-kernel
Now that it has been surgically removed from the MCPM port-control code,
we can let the CCI PMU driver be modular. Probing the PMU in the first
place still depends on the bus driver stub being built-in, but it's a
small price to pay compared to the major upheaval of completely reworking
the DT-handling code across the two drivers.
Robin.
Robin Murphy (3):
perf/arm-cc*: Fix MODULE_LICENSE() tags
perf/arm-cci: Remove pointless PMU disabling
perf/arm-cci: Allow building as a module
drivers/perf/Kconfig | 31 +++++++++++++++++--------------
drivers/perf/arm-cci.c | 32 ++++++++++++++++++++------------
drivers/perf/arm-ccn.c | 2 +-
3 files changed, 38 insertions(+), 27 deletions(-)
--
2.17.0.dirty
^ permalink raw reply
* [PATCH 1/3] perf/arm-cc*: Fix MODULE_LICENSE() tags
From: Robin Murphy @ 2018-05-11 14:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526048005.git.robin.murphy@arm.com>
The CCI/CCN drivers are licensed under GPLv2, but the MODULE_LICENSE()
tags are using the bare "GPL" string implying GPLv2 or later. Fix them
to match their actual file license.
Acked-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
drivers/perf/arm-cci.c | 2 +-
drivers/perf/arm-ccn.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/arm-cci.c b/drivers/perf/arm-cci.c
index 383b2d3dcbc6..53c774b20563 100644
--- a/drivers/perf/arm-cci.c
+++ b/drivers/perf/arm-cci.c
@@ -1718,5 +1718,5 @@ static struct platform_driver cci_pmu_driver = {
};
builtin_platform_driver(cci_pmu_driver);
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("ARM CCI PMU support");
diff --git a/drivers/perf/arm-ccn.c b/drivers/perf/arm-ccn.c
index 65b7e4042ece..917b47e776df 100644
--- a/drivers/perf/arm-ccn.c
+++ b/drivers/perf/arm-ccn.c
@@ -1594,4 +1594,4 @@ module_init(arm_ccn_init);
module_exit(arm_ccn_exit);
MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
--
2.17.0.dirty
^ permalink raw reply related
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